Attachment 135456 Details for Bug 103741 – dmesg -w

dmesg -w

dmesg-w (text/plain), 349.16 KB, created by Hector Velazquez on 2017-11-14 17:34:27 UTC

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Creator: Hector Velazquez

Created: 2017-11-14 17:34:27 UTC

Size: 349.16 KB

patch

obsolete

>[ 4269.345108] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[ 4269.345165] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 4269.345222] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[ 4269.345278] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 4269.345333] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 4269.345393] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[ 4269.345449] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 4269.345509] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 1B] FB:137, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[ 4269.345566] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[ 4269.345623] [drm:intel_dump_pipe_config [i915]] [PLANE:40:plane 2B] FB:134, fb = 256x256 format = XR24 little-endian (0x34325258)
>[ 4269.345679] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+256+256 dst 1065x425+256+256
>[ 4269.345737] [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor B] FB:135, fb = 128x128 format = AR24 little-endian (0x34325241)
>[ 4269.345793] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+128+128 dst 1014x632+128+128
>[ 4269.345856] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 4269.345915] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[ 4269.345983] [drm:intel_find_shared_dpll [i915]] [CRTC:46:pipe B] allocated DPLL 1
>[ 4269.346041] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[ 4269.347315] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 4269.355818] [drm:intel_power_well_disable [i915]] disabling DDI B IO power well
>[ 4269.355890] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 2, on? 1) for crtc 46
>[ 4269.355954] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[ 4269.356022] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DDI B]
>[ 4269.356082] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST A]
>[ 4269.356138] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST B]
>[ 4269.356193] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST C]
>[ 4269.356246] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI C]
>[ 4269.356299] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[ 4269.356352] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[ 4269.356405] [drm:intel_atomic_commit_tail [i915]] [ENCODER:70:DP-MST C]
>[ 4269.356457] [drm:intel_atomic_commit_tail [i915]] [ENCODER:72:DDI D]
>[ 4269.356510] [drm:intel_atomic_commit_tail [i915]] [ENCODER:74:DP-MST A]
>[ 4269.356562] [drm:intel_atomic_commit_tail [i915]] [ENCODER:75:DP-MST B]
>[ 4269.356614] [drm:intel_atomic_commit_tail [i915]] [ENCODER:76:DP-MST C]
>[ 4269.356668] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:58:DP-1]
>[ 4269.356725] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[ 4269.356780] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[ 4269.356835] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[ 4269.356888] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[ 4269.356947] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 2, on? 0) for crtc 46
>[ 4269.357003] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[ 4269.358364] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well
>[ 4269.360228] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 4269.360290] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 4269.360348] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 4269.360404] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 4269.362988] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 4269.363051] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 4269.364798] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 4269.366369] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:67:DP-2] Link Training Passed at Link Rate = 162000, Lane count = 4
>[ 4269.367366] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 4269.367438] [drm:intel_edp_drrs_enable [i915]] Panel doesn't support DRRS
>[ 4269.384234] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:67:DP-2]
>[ 4269.384311] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe B]
>[ 4269.384399] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[ 4269.434637] [drm:drm_mode_addfb2 [drm]] [FB:142]
>[ 4269.434862] [drm:drm_mode_addfb2 [drm]] [FB:144]
>[ 4269.437723] [drm:drm_mode_addfb2 [drm]] [FB:146]
>[ 4269.467971] [drm:drm_mode_addfb2 [drm]] [FB:155]
>[ 4269.488021] [drm:intel_atomic_check [i915]] [CONNECTOR:73:DP-3] checking for sink bpp constrains
>[ 4269.488088] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 4269.488157] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 297000KHz
>[ 4269.488223] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 4 clock 270000 bpp 24
>[ 4269.488282] [drm:intel_dp_compute_config [i915]] DP link bw required 891000 available 1080000
>[ 4269.488346] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 4269.488409] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe B][modeset]
>[ 4269.488469] [drm:intel_dump_pipe_config [i915]] output_types: DP (0x80)
>[ 4269.488529] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 4269.488589] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6920601, gmch_n: 8388608, link_m: 576716, link_n: 524288, tu: 64
>[ 4269.488646] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 4269.488701] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 4269.488734] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"3840x2160" 30 297000 3840 4016 4104 4400 2160 2168 2178 2250 0x48 0x9
>[ 4269.488792] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 4269.488820] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"3840x2160" 30 297000 3840 4016 4104 4400 2160 2168 2178 2250 0x48 0x9
>[ 4269.488879] [drm:intel_dump_pipe_config [i915]] crtc timings: 297000 3840 4016 4104 4400 2160 2168 2178 2250, type: 0x48 flags: 0x9
>[ 4269.488937] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 3840x2160, pixel rate 297000
>[ 4269.488993] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[ 4269.489049] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 4269.489103] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 4269.489164] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[ 4269.489218] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 4269.489278] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 1B] FB:146, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[ 4269.489334] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1200 dst 0x0+1920+1200
>[ 4269.489390] [drm:intel_dump_pipe_config [i915]] [PLANE:40:plane 2B] FB:142, fb = 256x256 format = XR24 little-endian (0x34325258)
>[ 4269.489446] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+256+256 dst 478x660+256+256
>[ 4269.489503] [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor B] FB:144, fb = 128x128 format = AR24 little-endian (0x34325241)
>[ 4269.489558] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+128+128 dst 904x518+128+128
>[ 4269.489621] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 4269.489678] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[ 4269.489748] [drm:intel_find_shared_dpll [i915]] [CRTC:46:pipe B] allocated DPLL 1
>[ 4269.489807] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[ 4269.493791] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 4269.502544] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well
>[ 4269.502616] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 2, on? 1) for crtc 46
>[ 4269.502680] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[ 4269.502748] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DDI B]
>[ 4269.502808] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST A]
>[ 4269.502864] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST B]
>[ 4269.502919] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST C]
>[ 4269.502973] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI C]
>[ 4269.503029] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[ 4269.503082] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[ 4269.503135] [drm:intel_atomic_commit_tail [i915]] [ENCODER:70:DP-MST C]
>[ 4269.503188] [drm:intel_atomic_commit_tail [i915]] [ENCODER:72:DDI D]
>[ 4269.503241] [drm:intel_atomic_commit_tail [i915]] [ENCODER:74:DP-MST A]
>[ 4269.503293] [drm:intel_atomic_commit_tail [i915]] [ENCODER:75:DP-MST B]
>[ 4269.503345] [drm:intel_atomic_commit_tail [i915]] [ENCODER:76:DP-MST C]
>[ 4269.503400] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:67:DP-2]
>[ 4269.503456] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[ 4269.503512] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[ 4269.503567] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[ 4269.503620] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[ 4269.503680] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 2, on? 0) for crtc 46
>[ 4269.503736] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[ 4269.505880] [drm:intel_power_well_enable [i915]] enabling DDI D IO power well
>[ 4269.506495] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4269.507758] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4269.509021] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4269.510288] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4269.511554] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4269.512430] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[ 4269.513414] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 4269.513473] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 4269.513529] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 4269.513583] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 4269.532301] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 4269.532346] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[ 4269.551004] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 4269.553103] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:73:DP-3] Link Training Passed at Link Rate = 270000, Lane count = 4
>[ 4269.553500] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 4269.553523] [drm:intel_edp_drrs_enable [i915]] Panel doesn't support DRRS
>[ 4269.553541] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:73:DP-3], [ENCODER:72:DDI D]
>[ 4269.553559] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 4269.553579] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 4269.586983] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:73:DP-3]
>[ 4269.587011] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe B]
>[ 4269.587044] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[ 4269.687523] [drm:drm_mode_addfb2 [drm]] [FB:157]
>[ 4269.687805] [drm:drm_mode_addfb2 [drm]] [FB:158]
>[ 4269.696705] [drm:drm_mode_addfb2 [drm]] [FB:161]
>[ 4269.754081] [drm:drm_mode_addfb2 [drm]] [FB:162]
>[ 4269.759699] [drm:intel_atomic_check [i915]] [CONNECTOR:58:DP-1] checking for sink bpp constrains
>[ 4269.759769] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 4269.759838] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 148500KHz
>[ 4269.759904] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 4269.759964] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 648000
>[ 4269.760029] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 4269.760093] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe B][modeset]
>[ 4269.760154] [drm:intel_dump_pipe_config [i915]] output_types: DP (0x80)
>[ 4269.760214] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 4269.760274] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5767168, gmch_n: 8388608, link_m: 240298, link_n: 262144, tu: 64
>[ 4269.760332] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[ 4269.760388] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 4269.760421] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[ 4269.760480] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 4269.760509] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[ 4269.760570] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[ 4269.760627] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1080, pixel rate 148500
>[ 4269.760684] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[ 4269.760740] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 4269.760795] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 4269.760856] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x3, cfgcr1: 0x0, cfgcr2: 0x0
>[ 4269.760912] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 4269.760972] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 1B] FB:161, fb = 3840x2160 format = XR24 little-endian (0x34325258)
>[ 4269.761029] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+3840+2160 dst 0x0+3840+2160
>[ 4269.761086] [drm:intel_dump_pipe_config [i915]] [PLANE:40:plane 2B] FB:157, fb = 256x256 format = XR24 little-endian (0x34325258)
>[ 4269.761143] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+256+256 dst 3416x1082+256+256
>[ 4269.761200] [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor B] FB:158, fb = 128x128 format = AR24 little-endian (0x34325241)
>[ 4269.761256] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+128+128 dst 1677x38+128+128
>[ 4269.761319] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 4269.761377] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[ 4269.761447] [drm:intel_find_shared_dpll [i915]] [CRTC:46:pipe B] allocated DPLL 1
>[ 4269.761507] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[ 4269.762692] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 4269.762764] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[ 4269.762860] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 4269.787611] [drm:intel_power_well_disable [i915]] disabling DDI D IO power well
>[ 4269.787692] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 2, on? 1) for crtc 46
>[ 4269.787764] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[ 4269.787842] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DDI B]
>[ 4269.787907] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST A]
>[ 4269.787988] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST B]
>[ 4269.788043] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST C]
>[ 4269.788098] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI C]
>[ 4269.788151] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[ 4269.788204] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[ 4269.788257] [drm:intel_atomic_commit_tail [i915]] [ENCODER:70:DP-MST C]
>[ 4269.788309] [drm:intel_atomic_commit_tail [i915]] [ENCODER:72:DDI D]
>[ 4269.788364] [drm:intel_atomic_commit_tail [i915]] [ENCODER:74:DP-MST A]
>[ 4269.788415] [drm:intel_atomic_commit_tail [i915]] [ENCODER:75:DP-MST B]
>[ 4269.788467] [drm:intel_atomic_commit_tail [i915]] [ENCODER:76:DP-MST C]
>[ 4269.788521] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:73:DP-3]
>[ 4269.788578] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[ 4269.788634] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[ 4269.788688] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[ 4269.788741] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[ 4269.788801] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 2, on? 0) for crtc 46
>[ 4269.788856] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[ 4269.790376] [drm:intel_power_well_enable [i915]] enabling DDI B IO power well
>[ 4269.791569] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 4269.791639] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 4269.791704] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 4269.791767] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 4269.793566] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 04000000
>[ 4269.793627] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[ 4269.793684] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 4269.795498] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 4269.795561] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 4269.797650] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[ 4269.797713] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[ 4269.797769] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[ 4269.798740] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 4269.800856] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:58:DP-1] Link Training Passed at Link Rate = 162000, Lane count = 4
>[ 4269.801501] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 4269.801564] [drm:intel_edp_drrs_enable [i915]] Panel doesn't support DRRS
>[ 4269.818330] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:58:DP-1]
>[ 4269.818396] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe B]
>[ 4269.818476] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[ 4269.868910] [drm:drm_mode_addfb2 [drm]] [FB:167]
>[ 4269.869182] [drm:drm_mode_addfb2 [drm]] [FB:168]
>[ 4269.871791] [drm:drm_mode_addfb2 [drm]] [FB:169]
>[ 4269.902035] [drm:drm_mode_addfb2 [drm]] [FB:170]
>[ 4269.908305] [drm:intel_atomic_check [i915]] [CONNECTOR:67:DP-2] checking for sink bpp constrains
>[ 4269.908373] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 4269.908440] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 4269.908505] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 4269.908564] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 4269.908628] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 4269.908691] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe B][modeset]
>[ 4269.908752] [drm:intel_dump_pipe_config [i915]] output_types: DP (0x80)
>[ 4269.908811] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 4269.908872] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 4269.908929] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[ 4269.908985] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 4269.909017] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[ 4269.909075] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 4269.909103] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[ 4269.909163] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[ 4269.909221] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 4269.909277] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[ 4269.909334] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 4269.909389] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 4269.909449] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[ 4269.909506] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 4269.909566] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 1B] FB:169, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[ 4269.909623] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[ 4269.909681] [drm:intel_dump_pipe_config [i915]] [PLANE:40:plane 2B] FB:167, fb = 256x256 format = XR24 little-endian (0x34325258)
>[ 4269.909737] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+256+256 dst 661x157+256+256
>[ 4269.909794] [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor B] FB:168, fb = 128x128 format = AR24 little-endian (0x34325241)
>[ 4269.909850] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+128+128 dst 198x310+128+128
>[ 4269.909913] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 4269.909971] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[ 4269.910041] [drm:intel_find_shared_dpll [i915]] [CRTC:46:pipe B] allocated DPLL 1
>[ 4269.910101] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[ 4269.911417] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 4269.919922] [drm:intel_power_well_disable [i915]] disabling DDI B IO power well
>[ 4269.919994] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 2, on? 1) for crtc 46
>[ 4269.920058] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[ 4269.920125] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DDI B]
>[ 4269.920185] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST A]
>[ 4269.920242] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST B]
>[ 4269.920296] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST C]
>[ 4269.920351] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI C]
>[ 4269.920404] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[ 4269.920456] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[ 4269.920509] [drm:intel_atomic_commit_tail [i915]] [ENCODER:70:DP-MST C]
>[ 4269.920560] [drm:intel_atomic_commit_tail [i915]] [ENCODER:72:DDI D]
>[ 4269.920612] [drm:intel_atomic_commit_tail [i915]] [ENCODER:74:DP-MST A]
>[ 4269.920664] [drm:intel_atomic_commit_tail [i915]] [ENCODER:75:DP-MST B]
>[ 4269.920715] [drm:intel_atomic_commit_tail [i915]] [ENCODER:76:DP-MST C]
>[ 4269.920770] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:58:DP-1]
>[ 4269.920826] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[ 4269.920882] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[ 4269.920937] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[ 4269.920991] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[ 4269.921051] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 2, on? 0) for crtc 46
>[ 4269.921106] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[ 4269.922365] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well
>[ 4269.924227] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 4269.924290] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 4269.924347] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 4269.924403] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 4269.926989] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 4269.927053] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 4269.928801] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 4269.930362] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:67:DP-2] Link Training Passed at Link Rate = 162000, Lane count = 4
>[ 4269.931365] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 4269.931437] [drm:intel_edp_drrs_enable [i915]] Panel doesn't support DRRS
>[ 4269.948237] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:67:DP-2]
>[ 4269.948314] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe B]
>[ 4269.948401] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[ 4269.998799] [drm:drm_mode_addfb2 [drm]] [FB:171]
>[ 4269.999042] [drm:drm_mode_addfb2 [drm]] [FB:172]
>[ 4270.001855] [drm:drm_mode_addfb2 [drm]] [FB:173]
>[ 4270.031995] [drm:drm_mode_addfb2 [drm]] [FB:174]
>[ 4270.052185] [drm:intel_atomic_check [i915]] [CONNECTOR:73:DP-3] checking for sink bpp constrains
>[ 4270.052253] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 4270.052320] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 297000KHz
>[ 4270.052385] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 4 clock 270000 bpp 24
>[ 4270.052444] [drm:intel_dp_compute_config [i915]] DP link bw required 891000 available 1080000
>[ 4270.052508] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 4270.052571] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe B][modeset]
>[ 4270.052632] [drm:intel_dump_pipe_config [i915]] output_types: DP (0x80)
>[ 4270.052691] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 4270.052750] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6920601, gmch_n: 8388608, link_m: 576716, link_n: 524288, tu: 64
>[ 4270.052807] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 4270.052863] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 4270.052895] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"3840x2160" 30 297000 3840 4016 4104 4400 2160 2168 2178 2250 0x48 0x9
>[ 4270.052953] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 4270.052980] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"3840x2160" 30 297000 3840 4016 4104 4400 2160 2168 2178 2250 0x48 0x9
>[ 4270.053041] [drm:intel_dump_pipe_config [i915]] crtc timings: 297000 3840 4016 4104 4400 2160 2168 2178 2250, type: 0x48 flags: 0x9
>[ 4270.053098] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 3840x2160, pixel rate 297000
>[ 4270.053154] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[ 4270.053210] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 4270.053265] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 4270.053326] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[ 4270.053383] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 4270.053443] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 1B] FB:173, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[ 4270.053500] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1200 dst 0x0+1920+1200
>[ 4270.053558] [drm:intel_dump_pipe_config [i915]] [PLANE:40:plane 2B] FB:171, fb = 256x256 format = XR24 little-endian (0x34325258)
>[ 4270.053613] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+256+256 dst 616x349+256+256
>[ 4270.053670] [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor B] FB:172, fb = 128x128 format = AR24 little-endian (0x34325241)
>[ 4270.053726] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+128+128 dst 1386x436+128+128
>[ 4270.053789] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 4270.053847] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[ 4270.053918] [drm:intel_find_shared_dpll [i915]] [CRTC:46:pipe B] allocated DPLL 1
>[ 4270.053977] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[ 4270.057957] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 4270.066693] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well
>[ 4270.066765] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 2, on? 1) for crtc 46
>[ 4270.066829] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[ 4270.066897] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DDI B]
>[ 4270.066957] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST A]
>[ 4270.067014] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST B]
>[ 4270.067070] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST C]
>[ 4270.067124] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI C]
>[ 4270.067180] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[ 4270.067234] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[ 4270.067287] [drm:intel_atomic_commit_tail [i915]] [ENCODER:70:DP-MST C]
>[ 4270.067340] [drm:intel_atomic_commit_tail [i915]] [ENCODER:72:DDI D]
>[ 4270.067392] [drm:intel_atomic_commit_tail [i915]] [ENCODER:74:DP-MST A]
>[ 4270.067444] [drm:intel_atomic_commit_tail [i915]] [ENCODER:75:DP-MST B]
>[ 4270.067495] [drm:intel_atomic_commit_tail [i915]] [ENCODER:76:DP-MST C]
>[ 4270.067550] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:67:DP-2]
>[ 4270.067606] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[ 4270.067661] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[ 4270.067715] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[ 4270.067768] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[ 4270.067829] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 2, on? 0) for crtc 46
>[ 4270.067884] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[ 4270.070016] [drm:intel_power_well_enable [i915]] enabling DDI D IO power well
>[ 4270.070653] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4270.071917] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4270.073179] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4270.074437] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4270.075698] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4270.076574] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[ 4270.077557] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 4270.077615] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 4270.077670] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 4270.077726] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 4270.096470] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 4270.096503] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[ 4270.115154] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 4270.117242] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:73:DP-3] Link Training Passed at Link Rate = 270000, Lane count = 4
>[ 4270.117624] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 4270.117643] [drm:intel_edp_drrs_enable [i915]] Panel doesn't support DRRS
>[ 4270.117660] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:73:DP-3], [ENCODER:72:DDI D]
>[ 4270.117676] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 4270.117693] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 4270.151076] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:73:DP-3]
>[ 4270.151098] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe B]
>[ 4270.151127] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[ 4270.251661] [drm:drm_mode_addfb2 [drm]] [FB:175]
>[ 4270.251905] [drm:drm_mode_addfb2 [drm]] [FB:176]
>[ 4270.261075] [drm:drm_mode_addfb2 [drm]] [FB:177]
>[ 4270.318153] [drm:drm_mode_addfb2 [drm]] [FB:178]
>[ 4270.323659] [drm:intel_atomic_check [i915]] [CONNECTOR:58:DP-1] checking for sink bpp constrains
>[ 4270.323727] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 4270.323794] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 148500KHz
>[ 4270.323859] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 4270.323917] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 648000
>[ 4270.323981] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 4270.324044] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe B][modeset]
>[ 4270.324105] [drm:intel_dump_pipe_config [i915]] output_types: DP (0x80)
>[ 4270.324164] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 4270.324224] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5767168, gmch_n: 8388608, link_m: 240298, link_n: 262144, tu: 64
>[ 4270.324281] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[ 4270.324338] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 4270.324368] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[ 4270.324426] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 4270.324455] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[ 4270.324515] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[ 4270.324573] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1080, pixel rate 148500
>[ 4270.324630] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[ 4270.324686] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 4270.324742] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 4270.324803] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x3, cfgcr1: 0x0, cfgcr2: 0x0
>[ 4270.324859] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 4270.324918] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 1B] FB:177, fb = 3840x2160 format = XR24 little-endian (0x34325258)
>[ 4270.324974] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+3840+2160 dst 0x0+3840+2160
>[ 4270.325032] [drm:intel_dump_pipe_config [i915]] [PLANE:40:plane 2B] FB:175, fb = 256x256 format = XR24 little-endian (0x34325258)
>[ 4270.325088] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+256+256 dst 3150x30+256+256
>[ 4270.325144] [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor B] FB:176, fb = 128x128 format = AR24 little-endian (0x34325241)
>[ 4270.325201] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+128+128 dst 2367x495+128+128
>[ 4270.325264] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 4270.325322] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[ 4270.325391] [drm:intel_find_shared_dpll [i915]] [CRTC:46:pipe B] allocated DPLL 1
>[ 4270.325453] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[ 4270.326628] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 4270.326702] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[ 4270.326793] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 4270.351720] [drm:intel_power_well_disable [i915]] disabling DDI D IO power well
>[ 4270.351801] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 2, on? 1) for crtc 46
>[ 4270.351872] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[ 4270.351949] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DDI B]
>[ 4270.352015] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST A]
>[ 4270.352078] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST B]
>[ 4270.352139] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST C]
>[ 4270.352200] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI C]
>[ 4270.352260] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[ 4270.352319] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[ 4270.352378] [drm:intel_atomic_commit_tail [i915]] [ENCODER:70:DP-MST C]
>[ 4270.352438] [drm:intel_atomic_commit_tail [i915]] [ENCODER:72:DDI D]
>[ 4270.352498] [drm:intel_atomic_commit_tail [i915]] [ENCODER:74:DP-MST A]
>[ 4270.352557] [drm:intel_atomic_commit_tail [i915]] [ENCODER:75:DP-MST B]
>[ 4270.352614] [drm:intel_atomic_commit_tail [i915]] [ENCODER:76:DP-MST C]
>[ 4270.352676] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:73:DP-3]
>[ 4270.352738] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[ 4270.352801] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[ 4270.352861] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[ 4270.352921] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[ 4270.352993] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 2, on? 0) for crtc 46
>[ 4270.353056] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[ 4270.354379] [drm:intel_power_well_enable [i915]] enabling DDI B IO power well
>[ 4270.355554] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 4270.355618] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 4270.355675] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 4270.355731] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 4270.357546] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 04000000
>[ 4270.357616] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[ 4270.357681] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 4270.359482] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 4270.359546] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 4270.361648] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[ 4270.361717] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[ 4270.361781] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[ 4270.362768] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 4270.364880] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:58:DP-1] Link Training Passed at Link Rate = 162000, Lane count = 4
>[ 4270.365545] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 4270.365616] [drm:intel_edp_drrs_enable [i915]] Panel doesn't support DRRS
>[ 4270.382366] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:58:DP-1]
>[ 4270.382433] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe B]
>[ 4270.382513] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[ 4270.432946] [drm:drm_mode_addfb2 [drm]] [FB:179]
>[ 4270.433207] [drm:drm_mode_addfb2 [drm]] [FB:180]
>[ 4270.435850] [drm:drm_mode_addfb2 [drm]] [FB:181]
>[ 4270.466164] [drm:drm_mode_addfb2 [drm]] [FB:182]
>[ 4270.472981] [drm:intel_atomic_check [i915]] [CONNECTOR:67:DP-2] checking for sink bpp constrains
>[ 4270.473059] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 4270.473135] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 4270.473208] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 4270.473276] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 4270.473348] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 4270.473418] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe B][modeset]
>[ 4270.473486] [drm:intel_dump_pipe_config [i915]] output_types: DP (0x80)
>[ 4270.473553] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 4270.473620] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 4270.473685] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[ 4270.473748] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 4270.473783] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[ 4270.473849] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 4270.473881] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[ 4270.473949] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[ 4270.474013] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 4270.474077] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[ 4270.474141] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 4270.474203] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 4270.474294] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[ 4270.474371] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 4270.474450] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 1B] FB:181, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[ 4270.474523] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[ 4270.474599] [drm:intel_dump_pipe_config [i915]] [PLANE:40:plane 2B] FB:179, fb = 256x256 format = XR24 little-endian (0x34325258)
>[ 4270.474672] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+256+256 dst 661x157+256+256
>[ 4270.474744] [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor B] FB:180, fb = 128x128 format = AR24 little-endian (0x34325241)
>[ 4270.474815] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+128+128 dst 198x310+128+128
>[ 4270.474893] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 4270.474966] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[ 4270.475049] [drm:intel_find_shared_dpll [i915]] [CRTC:46:pipe B] allocated DPLL 1
>[ 4270.475124] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[ 4270.476458] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 4270.482683] [drm:intel_power_well_disable [i915]] disabling DDI B IO power well
>[ 4270.482764] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 2, on? 1) for crtc 46
>[ 4270.482834] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[ 4270.482908] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DDI B]
>[ 4270.482981] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST A]
>[ 4270.483045] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST B]
>[ 4270.483107] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST C]
>[ 4270.483168] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI C]
>[ 4270.483229] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[ 4270.483290] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[ 4270.483349] [drm:intel_atomic_commit_tail [i915]] [ENCODER:70:DP-MST C]
>[ 4270.483409] [drm:intel_atomic_commit_tail [i915]] [ENCODER:72:DDI D]
>[ 4270.483467] [drm:intel_atomic_commit_tail [i915]] [ENCODER:74:DP-MST A]
>[ 4270.483525] [drm:intel_atomic_commit_tail [i915]] [ENCODER:75:DP-MST B]
>[ 4270.483583] [drm:intel_atomic_commit_tail [i915]] [ENCODER:76:DP-MST C]
>[ 4270.483645] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:58:DP-1]
>[ 4270.483708] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[ 4270.483770] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[ 4270.483830] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[ 4270.483890] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[ 4270.483976] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 2, on? 0) for crtc 46
>[ 4270.484031] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[ 4270.486178] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well
>[ 4270.488068] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 4270.488128] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 4270.488184] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 4270.488239] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 4270.490826] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 4270.490889] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 4270.492636] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 4270.494364] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:67:DP-2] Link Training Passed at Link Rate = 162000, Lane count = 4
>[ 4270.495370] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 4270.495444] [drm:intel_edp_drrs_enable [i915]] Panel doesn't support DRRS
>[ 4270.512363] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:67:DP-2]
>[ 4270.512443] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe B]
>[ 4270.512531] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[ 4270.562810] [drm:drm_mode_addfb2 [drm]] [FB:183]
>[ 4270.563075] [drm:drm_mode_addfb2 [drm]] [FB:184]
>[ 4270.566126] [drm:drm_mode_addfb2 [drm]] [FB:185]
>[ 4270.596035] [drm:drm_mode_addfb2 [drm]] [FB:186]
>[ 4270.615808] [drm:intel_atomic_check [i915]] [CONNECTOR:73:DP-3] checking for sink bpp constrains
>[ 4270.615873] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 4270.615935] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 297000KHz
>[ 4270.615995] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 4 clock 270000 bpp 24
>[ 4270.616051] [drm:intel_dp_compute_config [i915]] DP link bw required 891000 available 1080000
>[ 4270.616110] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 4270.616169] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe B][modeset]
>[ 4270.616226] [drm:intel_dump_pipe_config [i915]] output_types: DP (0x80)
>[ 4270.616281] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 4270.616337] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6920601, gmch_n: 8388608, link_m: 576716, link_n: 524288, tu: 64
>[ 4270.616390] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 4270.616442] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 4270.616472] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"3840x2160" 30 297000 3840 4016 4104 4400 2160 2168 2178 2250 0x48 0x9
>[ 4270.616524] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 4270.616551] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"3840x2160" 30 297000 3840 4016 4104 4400 2160 2168 2178 2250 0x48 0x9
>[ 4270.616606] [drm:intel_dump_pipe_config [i915]] crtc timings: 297000 3840 4016 4104 4400 2160 2168 2178 2250, type: 0x48 flags: 0x9
>[ 4270.616659] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 3840x2160, pixel rate 297000
>[ 4270.616712] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[ 4270.616764] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 4270.616815] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 4270.616872] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[ 4270.616923] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 4270.616977] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 1B] FB:185, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[ 4270.617030] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1200 dst 0x0+1920+1200
>[ 4270.617084] [drm:intel_dump_pipe_config [i915]] [PLANE:40:plane 2B] FB:183, fb = 256x256 format = XR24 little-endian (0x34325258)
>[ 4270.617136] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+256+256 dst 616x349+256+256
>[ 4270.617189] [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor B] FB:184, fb = 128x128 format = AR24 little-endian (0x34325241)
>[ 4270.617242] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+128+128 dst 1386x436+128+128
>[ 4270.617300] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 4270.617354] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[ 4270.617421] [drm:intel_find_shared_dpll [i915]] [CRTC:46:pipe B] allocated DPLL 1
>[ 4270.617477] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[ 4270.621449] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 4270.630230] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well
>[ 4270.630303] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 2, on? 1) for crtc 46
>[ 4270.630367] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[ 4270.630434] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DDI B]
>[ 4270.630493] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST A]
>[ 4270.630549] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST B]
>[ 4270.630604] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST C]
>[ 4270.630658] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI C]
>[ 4270.630713] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[ 4270.630766] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[ 4270.630818] [drm:intel_atomic_commit_tail [i915]] [ENCODER:70:DP-MST C]
>[ 4270.630870] [drm:intel_atomic_commit_tail [i915]] [ENCODER:72:DDI D]
>[ 4270.630922] [drm:intel_atomic_commit_tail [i915]] [ENCODER:74:DP-MST A]
>[ 4270.630975] [drm:intel_atomic_commit_tail [i915]] [ENCODER:75:DP-MST B]
>[ 4270.631026] [drm:intel_atomic_commit_tail [i915]] [ENCODER:76:DP-MST C]
>[ 4270.631081] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:67:DP-2]
>[ 4270.631138] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[ 4270.631194] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[ 4270.631249] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[ 4270.631303] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[ 4270.631363] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 2, on? 0) for crtc 46
>[ 4270.631419] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[ 4270.633570] [drm:intel_power_well_enable [i915]] enabling DDI D IO power well
>[ 4270.634203] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4270.635453] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4270.636715] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4270.637966] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4270.639205] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4270.640082] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[ 4270.641065] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 4270.641123] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 4270.641178] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 4270.641233] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 4270.659982] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 4270.660027] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[ 4270.678669] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 4270.680757] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:73:DP-3] Link Training Passed at Link Rate = 270000, Lane count = 4
>[ 4270.681153] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 4270.681173] [drm:intel_edp_drrs_enable [i915]] Panel doesn't support DRRS
>[ 4270.681190] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:73:DP-3], [ENCODER:72:DDI D]
>[ 4270.681206] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 4270.681224] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 4270.714591] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:73:DP-3]
>[ 4270.714612] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe B]
>[ 4270.714638] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[ 4270.815192] [drm:drm_mode_addfb2 [drm]] [FB:187]
>[ 4270.815435] [drm:drm_mode_addfb2 [drm]] [FB:188]
>[ 4270.824352] [drm:drm_mode_addfb2 [drm]] [FB:189]
>[ 4270.881623] [IGT] kms_plane_multiple: exiting, ret=0
>[ 4270.981538] [drm:intel_atomic_check [i915]] [CONNECTOR:58:DP-1] checking for sink bpp constrains
>[ 4270.981607] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 4270.981675] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 148500KHz
>[ 4270.981739] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 4270.981797] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 648000
>[ 4270.981861] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 4270.981923] [drm:intel_dump_pipe_config [i915]] [CRTC:36:pipe A][modeset]
>[ 4270.981984] [drm:intel_dump_pipe_config [i915]] output_types: DP (0x80)
>[ 4270.982042] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 4270.982101] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5767168, gmch_n: 8388608, link_m: 240298, link_n: 262144, tu: 64
>[ 4270.982157] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[ 4270.982259] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 4270.982305] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[ 4270.982373] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 4270.982409] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[ 4270.982476] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[ 4270.982542] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1080, pixel rate 148500
>[ 4270.982607] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[ 4270.982669] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 4270.982727] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 4270.982795] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[ 4270.982854] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 4270.982913] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 1A] disabled, scaler_id = -1
>[ 4270.982971] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 2A] disabled, scaler_id = -1
>[ 4270.983029] [drm:intel_dump_pipe_config [i915]] [PLANE:33:cursor A] disabled, scaler_id = -1
>[ 4270.983095] [drm:intel_atomic_check [i915]] [CONNECTOR:67:DP-2] checking for sink bpp constrains
>[ 4270.983155] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 4270.983218] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 4270.983280] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 4270.983339] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 4270.983400] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 4270.983461] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe B][modeset]
>[ 4270.983521] [drm:intel_dump_pipe_config [i915]] output_types: DP (0x80)
>[ 4270.983581] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 4270.983641] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 4270.983701] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[ 4270.983759] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 4270.983790] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[ 4270.983850] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 4270.983880] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[ 4270.983941] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[ 4270.984001] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 4270.984059] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[ 4270.984117] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 4270.984173] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 4270.984236] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x3, cfgcr1: 0x0, cfgcr2: 0x0
>[ 4270.984293] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 4270.984351] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 1B] disabled, scaler_id = -1
>[ 4270.984408] [drm:intel_dump_pipe_config [i915]] [PLANE:40:plane 2B] disabled, scaler_id = -1
>[ 4270.984466] [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor B] disabled, scaler_id = -1
>[ 4270.984529] [drm:intel_atomic_check [i915]] [CONNECTOR:73:DP-3] checking for sink bpp constrains
>[ 4270.984590] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 4270.984652] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 297000KHz
>[ 4270.984715] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 4 clock 270000 bpp 24
>[ 4270.984775] [drm:intel_dp_compute_config [i915]] DP link bw required 891000 available 1080000
>[ 4270.984836] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 4270.984897] [drm:intel_dump_pipe_config [i915]] [CRTC:56:pipe C][modeset]
>[ 4270.984957] [drm:intel_dump_pipe_config [i915]] output_types: DP (0x80)
>[ 4270.985015] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 4270.985074] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6920601, gmch_n: 8388608, link_m: 576716, link_n: 524288, tu: 64
>[ 4270.985131] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 4270.985188] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 4270.985218] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"3840x2160" 30 297000 3840 4016 4104 4400 2160 2168 2178 2250 0x48 0x9
>[ 4270.985278] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 4270.985307] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"3840x2160" 30 297000 3840 4016 4104 4400 2160 2168 2178 2250 0x48 0x9
>[ 4270.985369] [drm:intel_dump_pipe_config [i915]] crtc timings: 297000 3840 4016 4104 4400 2160 2168 2178 2250, type: 0x48 flags: 0x9
>[ 4270.985427] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 3840x2160, pixel rate 297000
>[ 4270.985486] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[ 4270.985542] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 4270.985599] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 4270.985660] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x3, cfgcr1: 0x0, cfgcr2: 0x0
>[ 4270.985717] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 4270.985774] [drm:intel_dump_pipe_config [i915]] [PLANE:47:plane 1C] disabled, scaler_id = -1
>[ 4270.985831] [drm:intel_dump_pipe_config [i915]] [PLANE:50:plane 2C] disabled, scaler_id = -1
>[ 4270.985887] [drm:intel_dump_pipe_config [i915]] [PLANE:53:cursor C] disabled, scaler_id = -1
>[ 4270.985953] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 4270.986014] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[ 4270.986086] [drm:intel_find_shared_dpll [i915]] [CRTC:36:pipe A] allocated DPLL 1
>[ 4270.986147] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[ 4270.986227] [drm:intel_find_shared_dpll [i915]] [CRTC:46:pipe B] sharing existing DPLL 1 (crtc mask 0x00000001, active 2)
>[ 4270.986295] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[ 4270.986363] [drm:intel_find_shared_dpll [i915]] [CRTC:56:pipe C] allocated DPLL 2
>[ 4270.986427] [drm:intel_reference_shared_dpll [i915]] using DPLL 2 for pipe C
>[ 4270.986545] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 4270.986614] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[ 4270.986702] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 4271.014713] [drm:intel_power_well_disable [i915]] disabling DDI D IO power well
>[ 4271.014739] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 2, on? 1) for crtc 46
>[ 4271.014762] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[ 4271.014783] [drm:intel_disable_sagv [i915]] Disabling the SAGV
>[ 4271.014814] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DDI B]
>[ 4271.014835] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST A]
>[ 4271.014855] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST B]
>[ 4271.014873] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST C]
>[ 4271.014892] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI C]
>[ 4271.014911] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[ 4271.014929] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[ 4271.014947] [drm:intel_atomic_commit_tail [i915]] [ENCODER:70:DP-MST C]
>[ 4271.014965] [drm:intel_atomic_commit_tail [i915]] [ENCODER:72:DDI D]
>[ 4271.014983] [drm:intel_atomic_commit_tail [i915]] [ENCODER:74:DP-MST A]
>[ 4271.015000] [drm:intel_atomic_commit_tail [i915]] [ENCODER:75:DP-MST B]
>[ 4271.015018] [drm:intel_atomic_commit_tail [i915]] [ENCODER:76:DP-MST C]
>[ 4271.015037] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[ 4271.015056] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[ 4271.015075] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[ 4271.015094] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[ 4271.015115] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 2, on? 0) for crtc 46
>[ 4271.015134] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[ 4271.017231] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well
>[ 4271.018987] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 4271.019011] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 4271.019033] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 4271.019055] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 4271.021548] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 4271.021577] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 4271.023265] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 4271.025362] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:67:DP-2] Link Training Passed at Link Rate = 162000, Lane count = 4
>[ 4271.026176] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 4271.026228] [drm:intel_edp_drrs_enable [i915]] Panel doesn't support DRRS
>[ 4271.043035] [drm:intel_enable_shared_dpll [i915]] enable DPLL 2 (active 4, on? 0) for crtc 56
>[ 4271.043102] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 2
>[ 4271.045255] [drm:intel_power_well_enable [i915]] enabling DDI D IO power well
>[ 4271.045868] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4271.047085] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4271.048347] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4271.049583] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4271.050897] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4271.051772] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[ 4271.052754] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 4271.052812] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 4271.052869] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 4271.052923] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 4271.071694] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 4271.071759] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[ 4271.089622] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 4271.091721] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:73:DP-3] Link Training Passed at Link Rate = 270000, Lane count = 4
>[ 4271.092185] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 4271.092216] [drm:intel_edp_drrs_enable [i915]] Panel doesn't support DRRS
>[ 4271.092242] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:73:DP-3], [ENCODER:72:DDI D]
>[ 4271.092267] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 4271.092294] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 4271.092351] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 3, on? 1) for crtc 36
>[ 4271.092380] [drm:intel_power_well_enable [i915]] enabling DDI B IO power well
>[ 4271.093441] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 4271.093465] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 4271.093488] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 4271.093510] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 4271.096314] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 04000000
>[ 4271.096337] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[ 4271.096357] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 4271.098038] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 4271.098061] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 4271.100054] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[ 4271.100077] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[ 4271.100097] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[ 4271.100997] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 4271.102284] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:58:DP-1] Link Training Passed at Link Rate = 162000, Lane count = 4
>[ 4271.102670] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 4271.102693] [drm:intel_edp_drrs_enable [i915]] Panel doesn't support DRRS
>[ 4271.102714] [drm:intel_fbc_enable [i915]] reserved 16588800 bytes of contiguous stolen space for FBC, threshold: 1
>[ 4271.102732] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 4271.125640] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:58:DP-1]
>[ 4271.125664] [drm:intel_atomic_commit_tail [i915]] [CRTC:36:pipe A]
>[ 4271.125693] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[ 4271.125723] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:67:DP-2]
>[ 4271.125744] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe B]
>[ 4271.125771] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[ 4271.125798] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:73:DP-3]
>[ 4271.125818] [drm:intel_atomic_commit_tail [i915]] [CRTC:56:pipe C]
>[ 4271.125844] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[ 4280.217691] [IGT] kms_plane_multiple: executing
>[ 4280.435757] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:58:DP-1]
>[ 4280.435836] [drm:intel_dp_detect [i915]] [CONNECTOR:58:DP-1]
>[ 4280.436393] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 01 02 00 00 00 00 00 00
>[ 4280.436761] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>[ 4280.436819] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[ 4280.436875] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[ 4280.437280] [drm:drm_dp_read_desc [drm_kms_helper]] DP sink: OUI 4c-e0-00 dev-ID  HW-rev 0.0 SW-rev 0.0 quirks 0x0000
>[ 4280.437336] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[ 4280.443056] [drm:drm_add_edid_modes [drm]] ELD: no CEA Extension found
>[ 4280.443118] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:58:DP-1] probed modes :
>[ 4280.443123] [drm:drm_mode_debug_printmodeline [drm]] Modeline 80:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[ 4280.443128] [drm:drm_mode_debug_printmodeline [drm]] Modeline 85:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[ 4280.443133] [drm:drm_mode_debug_printmodeline [drm]] Modeline 86:"1680x1050" 60 146250 1680 1784 1960 2240 1050 1053 1059 1089 0x40 0x6
>[ 4280.443138] [drm:drm_mode_debug_printmodeline [drm]] Modeline 83:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[ 4280.443142] [drm:drm_mode_debug_printmodeline [drm]] Modeline 84:"1440x900" 60 106500 1440 1520 1672 1904 900 903 909 934 0x40 0x6
>[ 4280.443147] [drm:drm_mode_debug_printmodeline [drm]] Modeline 82:"1280x960" 60 108000 1280 1376 1488 1800 960 961 964 1000 0x40 0x5
>[ 4280.443151] [drm:drm_mode_debug_printmodeline [drm]] Modeline 81:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[ 4280.443155] [drm:drm_mode_debug_printmodeline [drm]] Modeline 90:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[ 4280.443159] [drm:drm_mode_debug_printmodeline [drm]] Modeline 87:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[ 4280.443163] [drm:drm_mode_debug_printmodeline [drm]] Modeline 88:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[ 4280.443167] [drm:drm_mode_debug_printmodeline [drm]] Modeline 89:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[ 4280.443194] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:64:HDMI-A-1]
>[ 4280.443209] [drm:intel_hdmi_detect [i915]] [CONNECTOR:64:HDMI-A-1]
>[ 4280.443605] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[ 4280.443618] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[ 4280.446068] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[ 4280.446076] [drm:drm_do_probe_ddc_edid [drm]] drm: skipping non-existent adapter i915 gmbus dpb
>[ 4280.446538] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[ 4280.446553] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[ 4280.446925] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[ 4280.446929] [drm:drm_dp_dual_mode_detect [drm_kms_helper]] DP dual mode HDMI ID:  (err -6)
>[ 4280.446932] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:64:HDMI-A-1] disconnected
>[ 4280.446956] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:67:DP-2]
>[ 4280.446972] [drm:intel_dp_detect [i915]] [CONNECTOR:67:DP-2]
>[ 4280.447860] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 00 00 00 00 00
>[ 4280.448611] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>[ 4280.448652] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[ 4280.448665] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[ 4280.449492] [drm:drm_dp_read_desc [drm_kms_helper]] DP sink: OUI 4c-e0-00 dev-ID  HW-rev 0.0 SW-rev 0.0 quirks 0x0000
>[ 4280.449520] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[ 4280.455940] [drm:drm_add_edid_modes [drm]] ELD: no CEA Extension found
>[ 4280.455980] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:67:DP-2] probed modes :
>[ 4280.455987] [drm:drm_mode_debug_printmodeline [drm]] Modeline 92:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[ 4280.455993] [drm:drm_mode_debug_printmodeline [drm]] Modeline 97:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0xa
>[ 4280.455999] [drm:drm_mode_debug_printmodeline [drm]] Modeline 95:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[ 4280.456004] [drm:drm_mode_debug_printmodeline [drm]] Modeline 96:"1680x1050" 60 146250 1680 1784 1960 2240 1050 1053 1059 1089 0x40 0x6
>[ 4280.456009] [drm:drm_mode_debug_printmodeline [drm]] Modeline 94:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[ 4280.456015] [drm:drm_mode_debug_printmodeline [drm]] Modeline 93:"1280x960" 60 108000 1280 1376 1488 1800 960 961 964 1000 0x40 0x5
>[ 4280.456020] [drm:drm_mode_debug_printmodeline [drm]] Modeline 101:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[ 4280.456025] [drm:drm_mode_debug_printmodeline [drm]] Modeline 98:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[ 4280.456030] [drm:drm_mode_debug_printmodeline [drm]] Modeline 99:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[ 4280.456035] [drm:drm_mode_debug_printmodeline [drm]] Modeline 100:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[ 4280.456057] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:71:HDMI-A-2]
>[ 4280.456074] [drm:intel_hdmi_detect [i915]] [CONNECTOR:71:HDMI-A-2]
>[ 4280.458483] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[ 4280.458500] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[ 4280.460908] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[ 4280.460917] [drm:drm_do_probe_ddc_edid [drm]] drm: skipping non-existent adapter i915 gmbus dpc
>[ 4280.462461] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[ 4280.462479] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[ 4280.462858] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[ 4280.462862] [drm:drm_dp_dual_mode_detect [drm_kms_helper]] DP dual mode HDMI ID:  (err -6)
>[ 4280.462866] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:71:HDMI-A-2] disconnected
>[ 4280.462893] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:73:DP-3]
>[ 4280.462913] [drm:intel_dp_detect [i915]] [CONNECTOR:73:DP-3]
>[ 4280.463236] [drm:lspcon_wake_native_aux_ch [i915]] Native AUX CH up, DPCD version: 1.2
>[ 4280.463301] [drm:lspcon_resume [i915]] LSPCON recovering in PCON mode after 0 ms
>[ 4280.463715] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4280.464938] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4280.466171] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4280.467382] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4280.468603] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4280.469413] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[ 4280.469814] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 00 01 00 00 04 00 0f 00 04
>[ 4280.470499] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>[ 4280.470515] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000
>[ 4280.470530] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000
>[ 4280.470894] [drm:drm_dp_read_desc [drm_kms_helper]] DP branch: OUI 00-60-ad dev-ID MC2800 HW-rev 2.2 SW-rev 1.66 quirks 0x0000
>[ 4280.471183] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[ 4280.471910] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4280.473133] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4280.474345] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4280.475533] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4280.476755] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4280.477961] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4280.479194] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4280.480418] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4280.481633] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4280.482910] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4280.484257] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4280.485607] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4280.486958] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4280.488307] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4280.489626] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4280.490963] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4280.492301] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4280.493480] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4280.494705] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4280.495927] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4280.497142] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4280.498497] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4280.499843] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4280.501192] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4280.502547] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4280.503895] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4280.505245] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4280.506601] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4280.507941] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4280.508742] [drm:drm_detect_monitor_audio [drm]] Monitor has basic audio support
>[ 4280.509025] [drm:drm_add_edid_modes [drm]] ELD monitor ASUS PB287Q
>[ 4280.509032] [drm:drm_add_edid_modes [drm]] HDMI: latency present 0 0, video latency 0 1, audio latency 96 2
>[ 4280.509037] [drm:drm_add_edid_modes [drm]] ELD size 36, SAD count 1
>[ 4280.509042] [drm:drm_add_edid_modes [drm]] HDMI: DVI dual 0, max TMDS clock 300000 kHz
>[ 4280.509263] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:73:DP-3] probed modes :
>[ 4280.509270] [drm:drm_mode_debug_printmodeline [drm]] Modeline 105:"3840x2160" 30 297000 3840 4016 4104 4400 2160 2168 2178 2250 0x48 0x9
>[ 4280.509275] [drm:drm_mode_debug_printmodeline [drm]] Modeline 149:"3840x2160" 30 297000 3840 4016 4104 4400 2160 2168 2178 2250 0x40 0x5
>[ 4280.509281] [drm:drm_mode_debug_printmodeline [drm]] Modeline 165:"3840x2160" 30 296703 3840 4016 4104 4400 2160 2168 2178 2250 0x40 0x5
>[ 4280.509286] [drm:drm_mode_debug_printmodeline [drm]] Modeline 150:"3840x2160" 25 297000 3840 4896 4984 5280 2160 2168 2178 2250 0x40 0x5
>[ 4280.509292] [drm:drm_mode_debug_printmodeline [drm]] Modeline 151:"3840x2160" 24 297000 3840 5116 5204 5500 2160 2168 2178 2250 0x40 0x5
>[ 4280.509297] [drm:drm_mode_debug_printmodeline [drm]] Modeline 166:"3840x2160" 24 296703 3840 5116 5204 5500 2160 2168 2178 2250 0x40 0x5
>[ 4280.509302] [drm:drm_mode_debug_printmodeline [drm]] Modeline 108:"2560x1600" 60 268500 2560 2608 2640 2720 1600 1603 1609 1646 0x40 0x9
>[ 4280.509307] [drm:drm_mode_debug_printmodeline [drm]] Modeline 107:"2560x1440" 60 241500 2560 2608 2640 2720 1440 1443 1448 1481 0x40 0x5
>[ 4280.509312] [drm:drm_mode_debug_printmodeline [drm]] Modeline 106:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[ 4280.509317] [drm:drm_mode_debug_printmodeline [drm]] Modeline 152:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[ 4280.509322] [drm:drm_mode_debug_printmodeline [drm]] Modeline 140:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[ 4280.509327] [drm:drm_mode_debug_printmodeline [drm]] Modeline 159:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[ 4280.509332] [drm:drm_mode_debug_printmodeline [drm]] Modeline 145:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[ 4280.509337] [drm:drm_mode_debug_printmodeline [drm]] Modeline 139:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[ 4280.509342] [drm:drm_mode_debug_printmodeline [drm]] Modeline 148:"1920x1080" 30 74250 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[ 4280.509346] [drm:drm_mode_debug_printmodeline [drm]] Modeline 164:"1920x1080" 30 74176 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[ 4280.509351] [drm:drm_mode_debug_printmodeline [drm]] Modeline 147:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[ 4280.509356] [drm:drm_mode_debug_printmodeline [drm]] Modeline 163:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[ 4280.509361] [drm:drm_mode_debug_printmodeline [drm]] Modeline 114:"1680x1050" 60 119000 1680 1728 1760 1840 1050 1053 1059 1080 0x40 0x9
>[ 4280.509366] [drm:drm_mode_debug_printmodeline [drm]] Modeline 124:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[ 4280.509370] [drm:drm_mode_debug_printmodeline [drm]] Modeline 112:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[ 4280.509375] [drm:drm_mode_debug_printmodeline [drm]] Modeline 113:"1440x900" 60 88750 1440 1488 1520 1600 900 903 909 926 0x40 0x9
>[ 4280.509380] [drm:drm_mode_debug_printmodeline [drm]] Modeline 111:"1280x960" 60 108000 1280 1376 1488 1800 960 961 964 1000 0x40 0x5
>[ 4280.509385] [drm:drm_mode_debug_printmodeline [drm]] Modeline 115:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[ 4280.509390] [drm:drm_mode_debug_printmodeline [drm]] Modeline 116:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[ 4280.509395] [drm:drm_mode_debug_printmodeline [drm]] Modeline 153:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[ 4280.509399] [drm:drm_mode_debug_printmodeline [drm]] Modeline 109:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[ 4280.509404] [drm:drm_mode_debug_printmodeline [drm]] Modeline 143:"1440x576" 50 54000 1440 1464 1592 1728 576 581 586 625 0x40 0xa
>[ 4280.509409] [drm:drm_mode_debug_printmodeline [drm]] Modeline 125:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[ 4280.509414] [drm:drm_mode_debug_printmodeline [drm]] Modeline 126:"1024x768" 70 75000 1024 1048 1184 1328 768 771 777 806 0x40 0xa
>[ 4280.509418] [drm:drm_mode_debug_printmodeline [drm]] Modeline 127:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[ 4280.509423] [drm:drm_mode_debug_printmodeline [drm]] Modeline 160:"1440x480" 60 54054 1440 1472 1596 1716 480 489 495 525 0x40 0xa
>[ 4280.509428] [drm:drm_mode_debug_printmodeline [drm]] Modeline 141:"1440x480" 60 54000 1440 1472 1596 1716 480 489 495 525 0x40 0xa
>[ 4280.509433] [drm:drm_mode_debug_printmodeline [drm]] Modeline 128:"832x624" 75 57284 832 864 928 1152 624 625 628 667 0x40 0xa
>[ 4280.509438] [drm:drm_mode_debug_printmodeline [drm]] Modeline 129:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[ 4280.509442] [drm:drm_mode_debug_printmodeline [drm]] Modeline 130:"800x600" 72 50000 800 856 976 1040 600 637 643 666 0x40 0x5
>[ 4280.509447] [drm:drm_mode_debug_printmodeline [drm]] Modeline 117:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[ 4280.509452] [drm:drm_mode_debug_printmodeline [drm]] Modeline 118:"800x600" 56 36000 800 824 896 1024 600 601 603 625 0x40 0x5
>[ 4280.509457] [drm:drm_mode_debug_printmodeline [drm]] Modeline 110:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[ 4280.509461] [drm:drm_mode_debug_printmodeline [drm]] Modeline 156:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[ 4280.509466] [drm:drm_mode_debug_printmodeline [drm]] Modeline 132:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[ 4280.509471] [drm:drm_mode_debug_printmodeline [drm]] Modeline 119:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[ 4280.509476] [drm:drm_mode_debug_printmodeline [drm]] Modeline 120:"640x480" 73 31500 640 664 704 832 480 489 492 520 0x40 0xa
>[ 4280.509480] [drm:drm_mode_debug_printmodeline [drm]] Modeline 121:"640x480" 67 30240 640 704 768 864 480 483 486 525 0x40 0xa
>[ 4280.509485] [drm:drm_mode_debug_printmodeline [drm]] Modeline 154:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[ 4280.509490] [drm:drm_mode_debug_printmodeline [drm]] Modeline 122:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[ 4280.509495] [drm:drm_mode_debug_printmodeline [drm]] Modeline 123:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[ 4280.509544] [IGT] kms_plane_multiple: starting subtest atomic-pipe-B-tiling-y
>[ 4280.509607] [drm:drm_mode_addfb2 [drm]] [FB:136]
>[ 4280.511508] [drm:intel_atomic_check [i915]] [CONNECTOR:58:DP-1] checking for sink bpp constrains
>[ 4280.511525] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 4280.511542] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 148500KHz
>[ 4280.511558] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 4280.511573] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 648000
>[ 4280.511589] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 4280.511605] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe B][modeset]
>[ 4280.511620] [drm:intel_dump_pipe_config [i915]] output_types: DP (0x80)
>[ 4280.511635] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 4280.511650] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5767168, gmch_n: 8388608, link_m: 240298, link_n: 262144, tu: 64
>[ 4280.511664] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[ 4280.511678] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 4280.511686] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[ 4280.511700] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 4280.511707] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[ 4280.511722] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[ 4280.511736] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1080, pixel rate 148500
>[ 4280.511750] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[ 4280.511764] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 4280.511777] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 4280.511793] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[ 4280.511807] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 4280.511822] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 1B] FB:133, fb = 3840x2160 format = XR24 little-endian (0x34325258)
>[ 4280.511836] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1200 dst 0x0+1920+1200
>[ 4280.511850] [drm:intel_dump_pipe_config [i915]] [PLANE:40:plane 2B] disabled, scaler_id = -1
>[ 4280.511864] [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor B] disabled, scaler_id = -1
>[ 4280.511880] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 4280.511894] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[ 4280.511913] [drm:intel_find_shared_dpll [i915]] [CRTC:46:pipe B] allocated DPLL 1
>[ 4280.511928] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[ 4280.512213] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 4280.520644] [drm:intel_power_well_disable [i915]] disabling DDI B IO power well
>[ 4280.520663] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 4280.520680] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 3, on? 1) for crtc 36
>[ 4280.520707] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 4280.536201] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well
>[ 4280.536225] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 2, on? 1) for crtc 46
>[ 4280.536245] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[ 4280.536267] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 4280.536288] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[ 4280.536316] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 4280.559409] [drm:intel_power_well_disable [i915]] disabling DDI D IO power well
>[ 4280.559451] [drm:intel_disable_shared_dpll [i915]] disable DPLL 2 (active 4, on? 1) for crtc 56
>[ 4280.559487] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 2
>[ 4280.559537] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DDI B]
>[ 4280.559570] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST A]
>[ 4280.559602] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST B]
>[ 4280.559634] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST C]
>[ 4280.559665] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI C]
>[ 4280.559696] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[ 4280.559726] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[ 4280.559756] [drm:intel_atomic_commit_tail [i915]] [ENCODER:70:DP-MST C]
>[ 4280.559786] [drm:intel_atomic_commit_tail [i915]] [ENCODER:72:DDI D]
>[ 4280.559816] [drm:intel_atomic_commit_tail [i915]] [ENCODER:74:DP-MST A]
>[ 4280.559845] [drm:intel_atomic_commit_tail [i915]] [ENCODER:75:DP-MST B]
>[ 4280.559874] [drm:intel_atomic_commit_tail [i915]] [ENCODER:76:DP-MST C]
>[ 4280.559906] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:64:HDMI-A-1]
>[ 4280.559937] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:67:DP-2]
>[ 4280.559969] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:71:HDMI-A-2]
>[ 4280.560000] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:73:DP-3]
>[ 4280.560031] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[ 4280.560062] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[ 4280.560092] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[ 4280.560122] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[ 4280.560158] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 2, on? 0) for crtc 46
>[ 4280.560189] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[ 4280.562436] [drm:intel_power_well_enable [i915]] enabling DDI B IO power well
>[ 4280.563566] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 4280.563609] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 4280.563649] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 4280.563688] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 4280.566562] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 04000000
>[ 4280.566619] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[ 4280.566671] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 4280.568434] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 4280.568491] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 4280.570595] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[ 4280.570653] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[ 4280.570703] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[ 4280.571675] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 4280.573784] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:58:DP-1] Link Training Passed at Link Rate = 162000, Lane count = 4
>[ 4280.574448] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 4280.574514] [drm:intel_edp_drrs_enable [i915]] Panel doesn't support DRRS
>[ 4280.591251] [drm:intel_atomic_commit_tail [i915]] [CRTC:36:pipe A]
>[ 4280.591336] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:58:DP-1]
>[ 4280.591399] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe B]
>[ 4280.591478] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[ 4280.591541] [drm:intel_atomic_commit_tail [i915]] [CRTC:56:pipe C]
>[ 4280.591588] [drm:intel_enable_sagv [i915]] Enabling the SAGV
>[ 4280.641726] [drm:drm_mode_addfb2 [drm]] [FB:134]
>[ 4280.642518] [drm:drm_mode_addfb2 [drm]] [FB:135]
>[ 4280.644677] [drm:drm_mode_addfb2 [drm]] [FB:137]
>[ 4280.674930] [drm:drm_mode_addfb2 [drm]] [FB:138]
>[ 4280.680687] [drm:intel_atomic_check [i915]] [CONNECTOR:67:DP-2] checking for sink bpp constrains
>[ 4280.680755] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 4280.680823] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 4280.680887] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 4280.680946] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 4280.681010] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 4280.681073] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe B][modeset]
>[ 4280.681134] [drm:intel_dump_pipe_config [i915]] output_types: DP (0x80)
>[ 4280.681193] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 4280.681252] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 4280.681309] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[ 4280.681366] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 4280.681397] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[ 4280.681455] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 4280.681484] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[ 4280.681544] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[ 4280.681602] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 4280.681659] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[ 4280.681715] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 4280.681771] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 4280.681832] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[ 4280.681888] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 4280.681948] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 1B] FB:137, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[ 4280.682005] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[ 4280.682064] [drm:intel_dump_pipe_config [i915]] [PLANE:40:plane 2B] FB:134, fb = 256x256 format = XR24 little-endian (0x34325258)
>[ 4280.682120] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+256+256 dst 656x398+256+256
>[ 4280.682177] [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor B] FB:135, fb = 128x128 format = AR24 little-endian (0x34325241)
>[ 4280.682257] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+128+128 dst 1685x263+128+128
>[ 4280.682332] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 4280.682402] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[ 4280.682479] [drm:intel_find_shared_dpll [i915]] [CRTC:46:pipe B] allocated DPLL 1
>[ 4280.682547] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[ 4280.683309] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 4280.692744] [drm:intel_power_well_disable [i915]] disabling DDI B IO power well
>[ 4280.692816] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 2, on? 1) for crtc 46
>[ 4280.692880] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[ 4280.692948] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DDI B]
>[ 4280.693008] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST A]
>[ 4280.693065] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST B]
>[ 4280.693121] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST C]
>[ 4280.693175] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI C]
>[ 4280.693229] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[ 4280.693283] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[ 4280.693335] [drm:intel_atomic_commit_tail [i915]] [ENCODER:70:DP-MST C]
>[ 4280.693388] [drm:intel_atomic_commit_tail [i915]] [ENCODER:72:DDI D]
>[ 4280.693441] [drm:intel_atomic_commit_tail [i915]] [ENCODER:74:DP-MST A]
>[ 4280.693492] [drm:intel_atomic_commit_tail [i915]] [ENCODER:75:DP-MST B]
>[ 4280.693544] [drm:intel_atomic_commit_tail [i915]] [ENCODER:76:DP-MST C]
>[ 4280.693598] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:58:DP-1]
>[ 4280.693655] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[ 4280.693711] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[ 4280.693765] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[ 4280.693819] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[ 4280.693878] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 2, on? 0) for crtc 46
>[ 4280.693934] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[ 4280.696108] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well
>[ 4280.697959] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 4280.698020] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 4280.698077] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 4280.698133] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 4280.700713] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 4280.700776] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 4280.702526] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 4280.704674] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:67:DP-2] Link Training Passed at Link Rate = 162000, Lane count = 4
>[ 4280.705641] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 4280.705711] [drm:intel_edp_drrs_enable [i915]] Panel doesn't support DRRS
>[ 4280.722524] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:67:DP-2]
>[ 4280.722601] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe B]
>[ 4280.722687] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[ 4280.773138] [drm:drm_mode_addfb2 [drm]] [FB:142]
>[ 4280.773809] [drm:drm_mode_addfb2 [drm]] [FB:144]
>[ 4280.776817] [drm:drm_mode_addfb2 [drm]] [FB:146]
>[ 4280.806355] [drm:drm_mode_addfb2 [drm]] [FB:155]
>[ 4280.826251] [drm:intel_atomic_check [i915]] [CONNECTOR:73:DP-3] checking for sink bpp constrains
>[ 4280.826320] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 4280.826389] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 297000KHz
>[ 4280.826453] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 4 clock 270000 bpp 24
>[ 4280.826514] [drm:intel_dp_compute_config [i915]] DP link bw required 891000 available 1080000
>[ 4280.826578] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 4280.826642] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe B][modeset]
>[ 4280.826704] [drm:intel_dump_pipe_config [i915]] output_types: DP (0x80)
>[ 4280.826764] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 4280.826824] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6920601, gmch_n: 8388608, link_m: 576716, link_n: 524288, tu: 64
>[ 4280.826882] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 4280.826938] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 4280.826971] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"3840x2160" 30 297000 3840 4016 4104 4400 2160 2168 2178 2250 0x48 0x9
>[ 4280.827029] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 4280.827057] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"3840x2160" 30 297000 3840 4016 4104 4400 2160 2168 2178 2250 0x48 0x9
>[ 4280.827118] [drm:intel_dump_pipe_config [i915]] crtc timings: 297000 3840 4016 4104 4400 2160 2168 2178 2250, type: 0x48 flags: 0x9
>[ 4280.827175] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 3840x2160, pixel rate 297000
>[ 4280.827233] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[ 4280.827289] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 4280.827345] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 4280.827405] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[ 4280.827462] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 4280.827522] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 1B] FB:146, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[ 4280.827579] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1200 dst 0x0+1920+1200
>[ 4280.827637] [drm:intel_dump_pipe_config [i915]] [PLANE:40:plane 2B] FB:142, fb = 256x256 format = XR24 little-endian (0x34325258)
>[ 4280.827693] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+256+256 dst 699x777+256+256
>[ 4280.827751] [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor B] FB:144, fb = 128x128 format = AR24 little-endian (0x34325241)
>[ 4280.827807] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+128+128 dst 684x603+128+128
>[ 4280.827870] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 4280.827930] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[ 4280.828000] [drm:intel_find_shared_dpll [i915]] [CRTC:46:pipe B] allocated DPLL 1
>[ 4280.828060] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[ 4280.830389] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 4280.840977] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well
>[ 4280.841049] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 2, on? 1) for crtc 46
>[ 4280.841113] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[ 4280.841180] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DDI B]
>[ 4280.841238] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST A]
>[ 4280.841295] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST B]
>[ 4280.841349] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST C]
>[ 4280.841403] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI C]
>[ 4280.841459] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[ 4280.841512] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[ 4280.841564] [drm:intel_atomic_commit_tail [i915]] [ENCODER:70:DP-MST C]
>[ 4280.841616] [drm:intel_atomic_commit_tail [i915]] [ENCODER:72:DDI D]
>[ 4280.841668] [drm:intel_atomic_commit_tail [i915]] [ENCODER:74:DP-MST A]
>[ 4280.841720] [drm:intel_atomic_commit_tail [i915]] [ENCODER:75:DP-MST B]
>[ 4280.841772] [drm:intel_atomic_commit_tail [i915]] [ENCODER:76:DP-MST C]
>[ 4280.841827] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:67:DP-2]
>[ 4280.841884] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[ 4280.841940] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[ 4280.841995] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[ 4280.842048] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[ 4280.842108] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 2, on? 0) for crtc 46
>[ 4280.842164] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[ 4280.844336] [drm:intel_power_well_enable [i915]] enabling DDI D IO power well
>[ 4280.844946] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4280.846226] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4280.847505] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4280.848760] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4280.850022] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4280.850906] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[ 4280.851890] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 4280.851949] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 4280.852004] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 4280.852059] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 4280.870741] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 4280.870785] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[ 4280.889441] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 4280.891535] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:73:DP-3] Link Training Passed at Link Rate = 270000, Lane count = 4
>[ 4280.891931] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 4280.891951] [drm:intel_edp_drrs_enable [i915]] Panel doesn't support DRRS
>[ 4280.891967] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:73:DP-3], [ENCODER:72:DDI D]
>[ 4280.891983] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 4280.892001] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 4280.925479] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:73:DP-3]
>[ 4280.925502] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe B]
>[ 4280.925530] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[ 4281.026054] [drm:drm_mode_addfb2 [drm]] [FB:157]
>[ 4281.026762] [drm:drm_mode_addfb2 [drm]] [FB:158]
>[ 4281.036138] [drm:drm_mode_addfb2 [drm]] [FB:161]
>[ 4281.092439] [drm:drm_mode_addfb2 [drm]] [FB:162]
>[ 4281.097418] [drm:intel_atomic_check [i915]] [CONNECTOR:58:DP-1] checking for sink bpp constrains
>[ 4281.097486] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 4281.097554] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 148500KHz
>[ 4281.097619] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 4281.097678] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 648000
>[ 4281.097742] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 4281.097806] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe B][modeset]
>[ 4281.097866] [drm:intel_dump_pipe_config [i915]] output_types: DP (0x80)
>[ 4281.097925] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 4281.097986] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5767168, gmch_n: 8388608, link_m: 240298, link_n: 262144, tu: 64
>[ 4281.098043] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[ 4281.098098] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 4281.098130] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[ 4281.098188] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 4281.098239] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[ 4281.098300] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[ 4281.098370] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1080, pixel rate 148500
>[ 4281.098437] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[ 4281.098502] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 4281.098566] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 4281.098634] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x3, cfgcr1: 0x0, cfgcr2: 0x0
>[ 4281.098698] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 4281.098765] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 1B] FB:161, fb = 3840x2160 format = XR24 little-endian (0x34325258)
>[ 4281.098826] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+3840+2160 dst 0x0+3840+2160
>[ 4281.098888] [drm:intel_dump_pipe_config [i915]] [PLANE:40:plane 2B] FB:157, fb = 256x256 format = XR24 little-endian (0x34325258)
>[ 4281.098951] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+256+256 dst 3234x1566+256+256
>[ 4281.099015] [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor B] FB:158, fb = 128x128 format = AR24 little-endian (0x34325241)
>[ 4281.099074] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+128+128 dst 2504x1090+128+128
>[ 4281.099141] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 4281.099202] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[ 4281.099274] [drm:intel_find_shared_dpll [i915]] [CRTC:46:pipe B] allocated DPLL 1
>[ 4281.099337] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[ 4281.100032] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 4281.100102] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[ 4281.100184] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 4281.127376] [drm:intel_power_well_disable [i915]] disabling DDI D IO power well
>[ 4281.127447] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 2, on? 1) for crtc 46
>[ 4281.127511] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[ 4281.127578] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DDI B]
>[ 4281.127638] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST A]
>[ 4281.127695] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST B]
>[ 4281.127750] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST C]
>[ 4281.127805] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI C]
>[ 4281.127859] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[ 4281.127912] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[ 4281.127965] [drm:intel_atomic_commit_tail [i915]] [ENCODER:70:DP-MST C]
>[ 4281.128017] [drm:intel_atomic_commit_tail [i915]] [ENCODER:72:DDI D]
>[ 4281.128071] [drm:intel_atomic_commit_tail [i915]] [ENCODER:74:DP-MST A]
>[ 4281.128124] [drm:intel_atomic_commit_tail [i915]] [ENCODER:75:DP-MST B]
>[ 4281.128176] [drm:intel_atomic_commit_tail [i915]] [ENCODER:76:DP-MST C]
>[ 4281.128231] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:73:DP-3]
>[ 4281.128287] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[ 4281.128343] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[ 4281.128397] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[ 4281.128450] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[ 4281.128510] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 2, on? 0) for crtc 46
>[ 4281.128565] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[ 4281.130365] [drm:intel_power_well_enable [i915]] enabling DDI B IO power well
>[ 4281.131542] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 4281.131605] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 4281.131661] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 4281.131717] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 4281.133506] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 04000000
>[ 4281.133569] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[ 4281.133626] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 4281.135366] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 4281.135421] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 4281.137505] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[ 4281.137568] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[ 4281.137625] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[ 4281.138597] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 4281.140706] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:58:DP-1] Link Training Passed at Link Rate = 162000, Lane count = 4
>[ 4281.141372] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 4281.141435] [drm:intel_edp_drrs_enable [i915]] Panel doesn't support DRRS
>[ 4281.158186] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:58:DP-1]
>[ 4281.158265] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe B]
>[ 4281.158345] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[ 4281.208617] [drm:drm_mode_addfb2 [drm]] [FB:167]
>[ 4281.209232] [drm:drm_mode_addfb2 [drm]] [FB:168]
>[ 4281.211497] [drm:drm_mode_addfb2 [drm]] [FB:169]
>[ 4281.241828] [drm:drm_mode_addfb2 [drm]] [FB:170]
>[ 4281.247585] [drm:intel_atomic_check [i915]] [CONNECTOR:67:DP-2] checking for sink bpp constrains
>[ 4281.247653] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 4281.247722] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 4281.247788] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 4281.247848] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 4281.247913] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 4281.247976] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe B][modeset]
>[ 4281.248038] [drm:intel_dump_pipe_config [i915]] output_types: DP (0x80)
>[ 4281.248097] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 4281.248157] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 4281.248216] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[ 4281.248273] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 4281.248304] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[ 4281.248362] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 4281.248391] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[ 4281.248451] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[ 4281.248509] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 4281.248567] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[ 4281.248624] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 4281.248679] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 4281.248740] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[ 4281.248797] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 4281.248858] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 1B] FB:169, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[ 4281.248915] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[ 4281.248973] [drm:intel_dump_pipe_config [i915]] [PLANE:40:plane 2B] FB:167, fb = 256x256 format = XR24 little-endian (0x34325258)
>[ 4281.249029] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+256+256 dst 656x398+256+256
>[ 4281.249086] [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor B] FB:168, fb = 128x128 format = AR24 little-endian (0x34325241)
>[ 4281.249142] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+128+128 dst 1685x263+128+128
>[ 4281.249206] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 4281.249264] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[ 4281.249333] [drm:intel_find_shared_dpll [i915]] [CRTC:46:pipe B] allocated DPLL 1
>[ 4281.249393] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[ 4281.250165] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 4281.259961] [drm:intel_power_well_disable [i915]] disabling DDI B IO power well
>[ 4281.260033] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 2, on? 1) for crtc 46
>[ 4281.260098] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[ 4281.260165] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DDI B]
>[ 4281.260226] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST A]
>[ 4281.260284] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST B]
>[ 4281.260339] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST C]
>[ 4281.260393] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI C]
>[ 4281.260447] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[ 4281.260501] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[ 4281.260553] [drm:intel_atomic_commit_tail [i915]] [ENCODER:70:DP-MST C]
>[ 4281.260607] [drm:intel_atomic_commit_tail [i915]] [ENCODER:72:DDI D]
>[ 4281.260659] [drm:intel_atomic_commit_tail [i915]] [ENCODER:74:DP-MST A]
>[ 4281.260711] [drm:intel_atomic_commit_tail [i915]] [ENCODER:75:DP-MST B]
>[ 4281.260763] [drm:intel_atomic_commit_tail [i915]] [ENCODER:76:DP-MST C]
>[ 4281.260818] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:58:DP-1]
>[ 4281.260874] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[ 4281.260930] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[ 4281.260987] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[ 4281.261041] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[ 4281.261101] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 2, on? 0) for crtc 46
>[ 4281.261156] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[ 4281.262368] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well
>[ 4281.264233] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 4281.264296] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 4281.264353] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 4281.264409] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 4281.266995] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 4281.267059] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 4281.268806] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 4281.270363] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:67:DP-2] Link Training Passed at Link Rate = 162000, Lane count = 4
>[ 4281.271360] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 4281.271431] [drm:intel_edp_drrs_enable [i915]] Panel doesn't support DRRS
>[ 4281.288242] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:67:DP-2]
>[ 4281.288320] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe B]
>[ 4281.288407] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[ 4281.338686] [drm:drm_mode_addfb2 [drm]] [FB:171]
>[ 4281.339267] [drm:drm_mode_addfb2 [drm]] [FB:172]
>[ 4281.341950] [drm:drm_mode_addfb2 [drm]] [FB:173]
>[ 4281.371987] [drm:drm_mode_addfb2 [drm]] [FB:174]
>[ 4281.391709] [drm:intel_atomic_check [i915]] [CONNECTOR:73:DP-3] checking for sink bpp constrains
>[ 4281.391777] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 4281.391845] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 297000KHz
>[ 4281.391909] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 4 clock 270000 bpp 24
>[ 4281.391968] [drm:intel_dp_compute_config [i915]] DP link bw required 891000 available 1080000
>[ 4281.392031] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 4281.392095] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe B][modeset]
>[ 4281.392155] [drm:intel_dump_pipe_config [i915]] output_types: DP (0x80)
>[ 4281.392215] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 4281.392275] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6920601, gmch_n: 8388608, link_m: 576716, link_n: 524288, tu: 64
>[ 4281.392333] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 4281.392389] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 4281.392421] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"3840x2160" 30 297000 3840 4016 4104 4400 2160 2168 2178 2250 0x48 0x9
>[ 4281.392479] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 4281.392507] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"3840x2160" 30 297000 3840 4016 4104 4400 2160 2168 2178 2250 0x48 0x9
>[ 4281.392568] [drm:intel_dump_pipe_config [i915]] crtc timings: 297000 3840 4016 4104 4400 2160 2168 2178 2250, type: 0x48 flags: 0x9
>[ 4281.392625] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 3840x2160, pixel rate 297000
>[ 4281.392683] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[ 4281.392739] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 4281.392794] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 4281.392855] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[ 4281.392912] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 4281.392971] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 1B] FB:173, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[ 4281.393028] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1200 dst 0x0+1920+1200
>[ 4281.393087] [drm:intel_dump_pipe_config [i915]] [PLANE:40:plane 2B] FB:171, fb = 256x256 format = XR24 little-endian (0x34325258)
>[ 4281.393143] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+256+256 dst 699x777+256+256
>[ 4281.393201] [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor B] FB:172, fb = 128x128 format = AR24 little-endian (0x34325241)
>[ 4281.393258] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+128+128 dst 684x603+128+128
>[ 4281.393322] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 4281.393380] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[ 4281.393451] [drm:intel_find_shared_dpll [i915]] [CRTC:46:pipe B] allocated DPLL 1
>[ 4281.393510] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[ 4281.395851] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 4281.406645] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well
>[ 4281.406718] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 2, on? 1) for crtc 46
>[ 4281.406781] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[ 4281.406848] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DDI B]
>[ 4281.406908] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST A]
>[ 4281.406964] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST B]
>[ 4281.407019] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST C]
>[ 4281.407073] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI C]
>[ 4281.407128] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[ 4281.407181] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[ 4281.407232] [drm:intel_atomic_commit_tail [i915]] [ENCODER:70:DP-MST C]
>[ 4281.407285] [drm:intel_atomic_commit_tail [i915]] [ENCODER:72:DDI D]
>[ 4281.407337] [drm:intel_atomic_commit_tail [i915]] [ENCODER:74:DP-MST A]
>[ 4281.407388] [drm:intel_atomic_commit_tail [i915]] [ENCODER:75:DP-MST B]
>[ 4281.407440] [drm:intel_atomic_commit_tail [i915]] [ENCODER:76:DP-MST C]
>[ 4281.407495] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:67:DP-2]
>[ 4281.407551] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[ 4281.407607] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[ 4281.407662] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[ 4281.407716] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[ 4281.407776] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 2, on? 0) for crtc 46
>[ 4281.407831] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[ 4281.409989] [drm:intel_power_well_enable [i915]] enabling DDI D IO power well
>[ 4281.410634] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4281.411897] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4281.413160] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4281.414419] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4281.415681] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4281.416556] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[ 4281.417540] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 4281.417598] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 4281.417653] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 4281.417707] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 4281.436461] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 4281.436505] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[ 4281.455205] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 4281.457295] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:73:DP-3] Link Training Passed at Link Rate = 270000, Lane count = 4
>[ 4281.457692] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 4281.457714] [drm:intel_edp_drrs_enable [i915]] Panel doesn't support DRRS
>[ 4281.457733] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:73:DP-3], [ENCODER:72:DDI D]
>[ 4281.457751] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 4281.457771] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 4281.491131] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:73:DP-3]
>[ 4281.491157] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe B]
>[ 4281.491189] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[ 4281.591710] [drm:drm_mode_addfb2 [drm]] [FB:175]
>[ 4281.592376] [drm:drm_mode_addfb2 [drm]] [FB:176]
>[ 4281.601485] [drm:drm_mode_addfb2 [drm]] [FB:177]
>[ 4281.658307] [drm:drm_mode_addfb2 [drm]] [FB:178]
>[ 4281.663690] [drm:intel_atomic_check [i915]] [CONNECTOR:58:DP-1] checking for sink bpp constrains
>[ 4281.663758] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 4281.663826] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 148500KHz
>[ 4281.663890] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 4281.663951] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 648000
>[ 4281.664016] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 4281.664078] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe B][modeset]
>[ 4281.664139] [drm:intel_dump_pipe_config [i915]] output_types: DP (0x80)
>[ 4281.664198] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 4281.664258] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5767168, gmch_n: 8388608, link_m: 240298, link_n: 262144, tu: 64
>[ 4281.664315] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[ 4281.664371] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 4281.664403] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[ 4281.664461] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 4281.664490] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[ 4281.664551] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[ 4281.664608] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1080, pixel rate 148500
>[ 4281.664664] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[ 4281.664720] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 4281.664775] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 4281.664836] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x3, cfgcr1: 0x0, cfgcr2: 0x0
>[ 4281.664892] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 4281.664951] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 1B] FB:177, fb = 3840x2160 format = XR24 little-endian (0x34325258)
>[ 4281.665006] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+3840+2160 dst 0x0+3840+2160
>[ 4281.665064] [drm:intel_dump_pipe_config [i915]] [PLANE:40:plane 2B] FB:175, fb = 256x256 format = XR24 little-endian (0x34325258)
>[ 4281.665119] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+256+256 dst 3234x1566+256+256
>[ 4281.665176] [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor B] FB:176, fb = 128x128 format = AR24 little-endian (0x34325241)
>[ 4281.665232] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+128+128 dst 2504x1090+128+128
>[ 4281.665295] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 4281.665353] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[ 4281.665423] [drm:intel_find_shared_dpll [i915]] [CRTC:46:pipe B] allocated DPLL 1
>[ 4281.665484] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[ 4281.666195] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 4281.666267] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[ 4281.666357] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 4281.692670] [drm:intel_power_well_disable [i915]] disabling DDI D IO power well
>[ 4281.692742] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 2, on? 1) for crtc 46
>[ 4281.692805] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[ 4281.692875] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DDI B]
>[ 4281.692935] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST A]
>[ 4281.692992] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST B]
>[ 4281.693046] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST C]
>[ 4281.693100] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI C]
>[ 4281.693153] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[ 4281.693207] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[ 4281.693259] [drm:intel_atomic_commit_tail [i915]] [ENCODER:70:DP-MST C]
>[ 4281.693311] [drm:intel_atomic_commit_tail [i915]] [ENCODER:72:DDI D]
>[ 4281.693365] [drm:intel_atomic_commit_tail [i915]] [ENCODER:74:DP-MST A]
>[ 4281.693418] [drm:intel_atomic_commit_tail [i915]] [ENCODER:75:DP-MST B]
>[ 4281.693469] [drm:intel_atomic_commit_tail [i915]] [ENCODER:76:DP-MST C]
>[ 4281.693525] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:73:DP-3]
>[ 4281.693581] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[ 4281.693637] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[ 4281.693692] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[ 4281.693745] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[ 4281.693805] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 2, on? 0) for crtc 46
>[ 4281.693861] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[ 4281.696014] [drm:intel_power_well_enable [i915]] enabling DDI B IO power well
>[ 4281.697162] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 4281.697224] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 4281.697281] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 4281.697338] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 4281.699130] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 04000000
>[ 4281.699191] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[ 4281.699248] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 4281.701027] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 4281.701090] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 4281.703181] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[ 4281.703242] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[ 4281.703300] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[ 4281.704268] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 4281.706365] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:58:DP-1] Link Training Passed at Link Rate = 162000, Lane count = 4
>[ 4281.707056] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 4281.707128] [drm:intel_edp_drrs_enable [i915]] Panel doesn't support DRRS
>[ 4281.723945] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:58:DP-1]
>[ 4281.724024] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe B]
>[ 4281.724111] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[ 4281.774422] [drm:drm_mode_addfb2 [drm]] [FB:179]
>[ 4281.775024] [drm:drm_mode_addfb2 [drm]] [FB:180]
>[ 4281.777197] [drm:drm_mode_addfb2 [drm]] [FB:181]
>[ 4281.807566] [drm:drm_mode_addfb2 [drm]] [FB:182]
>[ 4281.813347] [drm:intel_atomic_check [i915]] [CONNECTOR:67:DP-2] checking for sink bpp constrains
>[ 4281.813415] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 4281.813483] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 4281.813548] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 4281.813608] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 4281.813672] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 4281.813736] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe B][modeset]
>[ 4281.813796] [drm:intel_dump_pipe_config [i915]] output_types: DP (0x80)
>[ 4281.813855] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 4281.813915] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 4281.813973] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[ 4281.814029] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 4281.814062] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[ 4281.814120] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 4281.814149] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[ 4281.814210] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[ 4281.814291] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 4281.814359] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[ 4281.814428] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 4281.814491] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 4281.814560] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[ 4281.814624] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 4281.814691] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 1B] FB:181, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[ 4281.814757] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[ 4281.814822] [drm:intel_dump_pipe_config [i915]] [PLANE:40:plane 2B] FB:179, fb = 256x256 format = XR24 little-endian (0x34325258)
>[ 4281.814884] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+256+256 dst 688x82+256+256
>[ 4281.814946] [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor B] FB:180, fb = 128x128 format = AR24 little-endian (0x34325241)
>[ 4281.815008] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+128+128 dst 412x839+128+128
>[ 4281.815077] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 4281.815138] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[ 4281.815210] [drm:intel_find_shared_dpll [i915]] [CRTC:46:pipe B] allocated DPLL 1
>[ 4281.815271] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[ 4281.816042] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 4281.825847] [drm:intel_power_well_disable [i915]] disabling DDI B IO power well
>[ 4281.825919] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 2, on? 1) for crtc 46
>[ 4281.825994] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[ 4281.826061] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DDI B]
>[ 4281.826121] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST A]
>[ 4281.826178] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST B]
>[ 4281.826266] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST C]
>[ 4281.826329] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI C]
>[ 4281.826395] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[ 4281.826456] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[ 4281.826517] [drm:intel_atomic_commit_tail [i915]] [ENCODER:70:DP-MST C]
>[ 4281.826574] [drm:intel_atomic_commit_tail [i915]] [ENCODER:72:DDI D]
>[ 4281.826630] [drm:intel_atomic_commit_tail [i915]] [ENCODER:74:DP-MST A]
>[ 4281.826688] [drm:intel_atomic_commit_tail [i915]] [ENCODER:75:DP-MST B]
>[ 4281.826744] [drm:intel_atomic_commit_tail [i915]] [ENCODER:76:DP-MST C]
>[ 4281.826801] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:58:DP-1]
>[ 4281.826860] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[ 4281.826919] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[ 4281.826976] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[ 4281.827033] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[ 4281.827096] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 2, on? 0) for crtc 46
>[ 4281.827153] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[ 4281.829301] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well
>[ 4281.831142] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 4281.831203] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 4281.831260] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 4281.831315] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 4281.833878] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 4281.833942] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 4281.835690] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 4281.837835] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:67:DP-2] Link Training Passed at Link Rate = 162000, Lane count = 4
>[ 4281.838801] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 4281.838870] [drm:intel_edp_drrs_enable [i915]] Panel doesn't support DRRS
>[ 4281.855772] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:67:DP-2]
>[ 4281.855852] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe B]
>[ 4281.855941] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[ 4281.906213] [drm:drm_mode_addfb2 [drm]] [FB:183]
>[ 4281.906836] [drm:drm_mode_addfb2 [drm]] [FB:184]
>[ 4281.909444] [drm:drm_mode_addfb2 [drm]] [FB:185]
>[ 4281.939428] [drm:drm_mode_addfb2 [drm]] [FB:186]
>[ 4281.959197] [drm:intel_atomic_check [i915]] [CONNECTOR:73:DP-3] checking for sink bpp constrains
>[ 4281.959265] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 4281.959333] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 297000KHz
>[ 4281.959399] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 4 clock 270000 bpp 24
>[ 4281.959459] [drm:intel_dp_compute_config [i915]] DP link bw required 891000 available 1080000
>[ 4281.959524] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 4281.959587] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe B][modeset]
>[ 4281.959649] [drm:intel_dump_pipe_config [i915]] output_types: DP (0x80)
>[ 4281.959709] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 4281.959769] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6920601, gmch_n: 8388608, link_m: 576716, link_n: 524288, tu: 64
>[ 4281.959826] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 4281.959883] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 4281.959915] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"3840x2160" 30 297000 3840 4016 4104 4400 2160 2168 2178 2250 0x48 0x9
>[ 4281.959975] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 4281.960003] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"3840x2160" 30 297000 3840 4016 4104 4400 2160 2168 2178 2250 0x48 0x9
>[ 4281.960064] [drm:intel_dump_pipe_config [i915]] crtc timings: 297000 3840 4016 4104 4400 2160 2168 2178 2250, type: 0x48 flags: 0x9
>[ 4281.960122] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 3840x2160, pixel rate 297000
>[ 4281.960179] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[ 4281.960236] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 4281.960291] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 4281.960353] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[ 4281.960410] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 4281.960470] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 1B] FB:185, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[ 4281.960526] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1200 dst 0x0+1920+1200
>[ 4281.960584] [drm:intel_dump_pipe_config [i915]] [PLANE:40:plane 2B] FB:183, fb = 256x256 format = XR24 little-endian (0x34325258)
>[ 4281.960640] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+256+256 dst 926x501+256+256
>[ 4281.960698] [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor B] FB:184, fb = 128x128 format = AR24 little-endian (0x34325241)
>[ 4281.960754] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+128+128 dst 1328x966+128+128
>[ 4281.960818] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 4281.960877] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[ 4281.960947] [drm:intel_find_shared_dpll [i915]] [CRTC:46:pipe B] allocated DPLL 1
>[ 4281.961007] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[ 4281.964181] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 4281.973029] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well
>[ 4281.973102] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 2, on? 1) for crtc 46
>[ 4281.973165] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[ 4281.973235] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DDI B]
>[ 4281.973294] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST A]
>[ 4281.973350] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST B]
>[ 4281.973405] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST C]
>[ 4281.973460] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI C]
>[ 4281.973516] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[ 4281.973569] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[ 4281.973621] [drm:intel_atomic_commit_tail [i915]] [ENCODER:70:DP-MST C]
>[ 4281.973673] [drm:intel_atomic_commit_tail [i915]] [ENCODER:72:DDI D]
>[ 4281.973725] [drm:intel_atomic_commit_tail [i915]] [ENCODER:74:DP-MST A]
>[ 4281.973778] [drm:intel_atomic_commit_tail [i915]] [ENCODER:75:DP-MST B]
>[ 4281.973831] [drm:intel_atomic_commit_tail [i915]] [ENCODER:76:DP-MST C]
>[ 4281.973886] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:67:DP-2]
>[ 4281.973942] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[ 4281.973998] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[ 4281.974052] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[ 4281.974106] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[ 4281.974166] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 2, on? 0) for crtc 46
>[ 4281.974251] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[ 4281.976409] [drm:intel_power_well_enable [i915]] enabling DDI D IO power well
>[ 4281.977021] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4281.978299] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4281.979571] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4281.980829] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4281.982095] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4281.982976] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[ 4281.983966] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 4281.984024] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 4281.984079] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 4281.984134] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 4282.002885] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 4282.002928] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[ 4282.021605] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 4282.023694] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:73:DP-3] Link Training Passed at Link Rate = 270000, Lane count = 4
>[ 4282.024104] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 4282.024128] [drm:intel_edp_drrs_enable [i915]] Panel doesn't support DRRS
>[ 4282.024146] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:73:DP-3], [ENCODER:72:DDI D]
>[ 4282.024164] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 4282.024184] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 4282.057560] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:73:DP-3]
>[ 4282.057587] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe B]
>[ 4282.057619] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[ 4282.158149] [drm:drm_mode_addfb2 [drm]] [FB:187]
>[ 4282.158797] [drm:drm_mode_addfb2 [drm]] [FB:188]
>[ 4282.167114] [drm:drm_mode_addfb2 [drm]] [FB:189]
>[ 4282.224655] [IGT] kms_plane_multiple: exiting, ret=0
>[ 4282.324576] [drm:intel_atomic_check [i915]] [CONNECTOR:58:DP-1] checking for sink bpp constrains
>[ 4282.324645] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 4282.324714] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 148500KHz
>[ 4282.324779] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 4282.324838] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 648000
>[ 4282.324902] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 4282.324965] [drm:intel_dump_pipe_config [i915]] [CRTC:36:pipe A][modeset]
>[ 4282.325026] [drm:intel_dump_pipe_config [i915]] output_types: DP (0x80)
>[ 4282.325084] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 4282.325143] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5767168, gmch_n: 8388608, link_m: 240298, link_n: 262144, tu: 64
>[ 4282.325199] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[ 4282.325255] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 4282.325288] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[ 4282.325345] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 4282.325374] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[ 4282.325434] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[ 4282.325491] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1080, pixel rate 148500
>[ 4282.325547] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[ 4282.325603] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 4282.325658] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 4282.325718] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[ 4282.325773] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 4282.325830] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 1A] disabled, scaler_id = -1
>[ 4282.325885] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 2A] disabled, scaler_id = -1
>[ 4282.325940] [drm:intel_dump_pipe_config [i915]] [PLANE:33:cursor A] disabled, scaler_id = -1
>[ 4282.326002] [drm:intel_atomic_check [i915]] [CONNECTOR:67:DP-2] checking for sink bpp constrains
>[ 4282.326060] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 4282.326120] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 4282.326179] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 4282.326281] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 4282.326352] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 4282.326423] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe B][modeset]
>[ 4282.326487] [drm:intel_dump_pipe_config [i915]] output_types: DP (0x80)
>[ 4282.326552] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 4282.326618] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 4282.326691] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[ 4282.326751] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 4282.326787] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[ 4282.326848] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 4282.326882] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[ 4282.326945] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[ 4282.327005] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 4282.327065] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[ 4282.327125] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 4282.327186] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 4282.327246] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x3, cfgcr1: 0x0, cfgcr2: 0x0
>[ 4282.327301] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 4282.327356] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 1B] disabled, scaler_id = -1
>[ 4282.327418] [drm:intel_dump_pipe_config [i915]] [PLANE:40:plane 2B] disabled, scaler_id = -1
>[ 4282.327475] [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor B] disabled, scaler_id = -1
>[ 4282.327537] [drm:intel_atomic_check [i915]] [CONNECTOR:73:DP-3] checking for sink bpp constrains
>[ 4282.327593] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 4282.327653] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 297000KHz
>[ 4282.327711] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 4 clock 270000 bpp 24
>[ 4282.327767] [drm:intel_dp_compute_config [i915]] DP link bw required 891000 available 1080000
>[ 4282.327825] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 4282.327884] [drm:intel_dump_pipe_config [i915]] [CRTC:56:pipe C][modeset]
>[ 4282.327941] [drm:intel_dump_pipe_config [i915]] output_types: DP (0x80)
>[ 4282.327997] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 4282.328052] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6920601, gmch_n: 8388608, link_m: 576716, link_n: 524288, tu: 64
>[ 4282.328107] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 4282.328160] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 4282.328190] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"3840x2160" 30 297000 3840 4016 4104 4400 2160 2168 2178 2250 0x48 0x9
>[ 4282.328244] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 4282.328273] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"3840x2160" 30 297000 3840 4016 4104 4400 2160 2168 2178 2250 0x48 0x9
>[ 4282.328330] [drm:intel_dump_pipe_config [i915]] crtc timings: 297000 3840 4016 4104 4400 2160 2168 2178 2250, type: 0x48 flags: 0x9
>[ 4282.328385] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 3840x2160, pixel rate 297000
>[ 4282.328440] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[ 4282.328494] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 4282.328547] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 4282.328605] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x3, cfgcr1: 0x0, cfgcr2: 0x0
>[ 4282.328659] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 4282.328715] [drm:intel_dump_pipe_config [i915]] [PLANE:47:plane 1C] disabled, scaler_id = -1
>[ 4282.328769] [drm:intel_dump_pipe_config [i915]] [PLANE:50:plane 2C] disabled, scaler_id = -1
>[ 4282.328823] [drm:intel_dump_pipe_config [i915]] [PLANE:53:cursor C] disabled, scaler_id = -1
>[ 4282.328884] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 4282.328941] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[ 4282.329010] [drm:intel_find_shared_dpll [i915]] [CRTC:36:pipe A] allocated DPLL 1
>[ 4282.329067] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[ 4282.329129] [drm:intel_find_shared_dpll [i915]] [CRTC:46:pipe B] sharing existing DPLL 1 (crtc mask 0x00000001, active 2)
>[ 4282.329185] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[ 4282.329243] [drm:intel_find_shared_dpll [i915]] [CRTC:56:pipe C] allocated DPLL 2
>[ 4282.329298] [drm:intel_reference_shared_dpll [i915]] using DPLL 2 for pipe C
>[ 4282.329406] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 4282.329469] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[ 4282.329548] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 4282.358404] [drm:intel_power_well_disable [i915]] disabling DDI D IO power well
>[ 4282.358449] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 2, on? 1) for crtc 46
>[ 4282.358464] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[ 4282.358478] [drm:intel_disable_sagv [i915]] Disabling the SAGV
>[ 4282.358494] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DDI B]
>[ 4282.358507] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST A]
>[ 4282.358520] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST B]
>[ 4282.358532] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST C]
>[ 4282.358544] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI C]
>[ 4282.358555] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[ 4282.358567] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[ 4282.358579] [drm:intel_atomic_commit_tail [i915]] [ENCODER:70:DP-MST C]
>[ 4282.358590] [drm:intel_atomic_commit_tail [i915]] [ENCODER:72:DDI D]
>[ 4282.358602] [drm:intel_atomic_commit_tail [i915]] [ENCODER:74:DP-MST A]
>[ 4282.358613] [drm:intel_atomic_commit_tail [i915]] [ENCODER:75:DP-MST B]
>[ 4282.358624] [drm:intel_atomic_commit_tail [i915]] [ENCODER:76:DP-MST C]
>[ 4282.358636] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[ 4282.358649] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[ 4282.358661] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[ 4282.358673] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[ 4282.358687] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 2, on? 0) for crtc 46
>[ 4282.358699] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[ 4282.360894] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well
>[ 4282.362660] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 4282.362676] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 4282.362690] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 4282.362705] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 4282.365198] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 4282.365214] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 4282.366881] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 4282.369041] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:67:DP-2] Link Training Passed at Link Rate = 162000, Lane count = 4
>[ 4282.369739] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 4282.369761] [drm:intel_edp_drrs_enable [i915]] Panel doesn't support DRRS
>[ 4282.386635] [drm:intel_enable_shared_dpll [i915]] enable DPLL 2 (active 4, on? 0) for crtc 56
>[ 4282.386667] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 2
>[ 4282.388783] [drm:intel_power_well_enable [i915]] enabling DDI D IO power well
>[ 4282.389362] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4282.390581] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4282.391813] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4282.393038] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4282.394280] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4282.395106] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[ 4282.396051] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 4282.396089] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 4282.396124] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 4282.396160] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 4282.414905] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 4282.414957] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[ 4282.433652] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 4282.435753] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:73:DP-3] Link Training Passed at Link Rate = 270000, Lane count = 4
>[ 4282.436219] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 4282.436248] [drm:intel_edp_drrs_enable [i915]] Panel doesn't support DRRS
>[ 4282.436271] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:73:DP-3], [ENCODER:72:DDI D]
>[ 4282.436294] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 4282.436319] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 4282.436373] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 3, on? 1) for crtc 36
>[ 4282.436400] [drm:intel_power_well_enable [i915]] enabling DDI B IO power well
>[ 4282.437457] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 4282.437479] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 4282.437500] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 4282.437521] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 4282.440311] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 04000000
>[ 4282.440335] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[ 4282.440357] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 4282.442034] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 4282.442055] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 4282.444043] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[ 4282.444063] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[ 4282.444082] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[ 4282.444975] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 4282.446293] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:58:DP-1] Link Training Passed at Link Rate = 162000, Lane count = 4
>[ 4282.446671] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 4282.446693] [drm:intel_edp_drrs_enable [i915]] Panel doesn't support DRRS
>[ 4282.446713] [drm:intel_fbc_enable [i915]] reserved 16588800 bytes of contiguous stolen space for FBC, threshold: 1
>[ 4282.446730] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 4282.469666] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:58:DP-1]
>[ 4282.469688] [drm:intel_atomic_commit_tail [i915]] [CRTC:36:pipe A]
>[ 4282.469716] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[ 4282.469744] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:67:DP-2]
>[ 4282.469765] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe B]
>[ 4282.469791] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[ 4282.469817] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:73:DP-3]
>[ 4282.469836] [drm:intel_atomic_commit_tail [i915]] [CRTC:56:pipe C]
>[ 4282.469861] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[ 4292.916969] [IGT] kms_plane_multiple: executing
>[ 4293.131817] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:58:DP-1]
>[ 4293.131896] [drm:intel_dp_detect [i915]] [CONNECTOR:58:DP-1]
>[ 4293.132457] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 01 02 00 00 00 00 00 00
>[ 4293.132823] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>[ 4293.132883] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[ 4293.132941] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[ 4293.133347] [drm:drm_dp_read_desc [drm_kms_helper]] DP sink: OUI 4c-e0-00 dev-ID  HW-rev 0.0 SW-rev 0.0 quirks 0x0000
>[ 4293.133403] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[ 4293.139073] [drm:drm_add_edid_modes [drm]] ELD: no CEA Extension found
>[ 4293.139134] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:58:DP-1] probed modes :
>[ 4293.139140] [drm:drm_mode_debug_printmodeline [drm]] Modeline 80:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[ 4293.139145] [drm:drm_mode_debug_printmodeline [drm]] Modeline 85:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[ 4293.139150] [drm:drm_mode_debug_printmodeline [drm]] Modeline 86:"1680x1050" 60 146250 1680 1784 1960 2240 1050 1053 1059 1089 0x40 0x6
>[ 4293.139154] [drm:drm_mode_debug_printmodeline [drm]] Modeline 83:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[ 4293.139159] [drm:drm_mode_debug_printmodeline [drm]] Modeline 84:"1440x900" 60 106500 1440 1520 1672 1904 900 903 909 934 0x40 0x6
>[ 4293.139163] [drm:drm_mode_debug_printmodeline [drm]] Modeline 82:"1280x960" 60 108000 1280 1376 1488 1800 960 961 964 1000 0x40 0x5
>[ 4293.139167] [drm:drm_mode_debug_printmodeline [drm]] Modeline 81:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[ 4293.139171] [drm:drm_mode_debug_printmodeline [drm]] Modeline 90:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[ 4293.139175] [drm:drm_mode_debug_printmodeline [drm]] Modeline 87:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[ 4293.139179] [drm:drm_mode_debug_printmodeline [drm]] Modeline 88:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[ 4293.139183] [drm:drm_mode_debug_printmodeline [drm]] Modeline 89:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[ 4293.139211] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:64:HDMI-A-1]
>[ 4293.139225] [drm:intel_hdmi_detect [i915]] [CONNECTOR:64:HDMI-A-1]
>[ 4293.139561] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[ 4293.139573] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[ 4293.141976] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[ 4293.141983] [drm:drm_do_probe_ddc_edid [drm]] drm: skipping non-existent adapter i915 gmbus dpb
>[ 4293.144415] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[ 4293.144431] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[ 4293.146455] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[ 4293.146460] [drm:drm_dp_dual_mode_detect [drm_kms_helper]] DP dual mode HDMI ID:  (err -6)
>[ 4293.146463] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:64:HDMI-A-1] disconnected
>[ 4293.146489] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:67:DP-2]
>[ 4293.146507] [drm:intel_dp_detect [i915]] [CONNECTOR:67:DP-2]
>[ 4293.147419] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 00 00 00 00 00
>[ 4293.148185] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>[ 4293.148200] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[ 4293.148215] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[ 4293.149042] [drm:drm_dp_read_desc [drm_kms_helper]] DP sink: OUI 4c-e0-00 dev-ID  HW-rev 0.0 SW-rev 0.0 quirks 0x0000
>[ 4293.149071] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[ 4293.155495] [drm:drm_add_edid_modes [drm]] ELD: no CEA Extension found
>[ 4293.155539] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:67:DP-2] probed modes :
>[ 4293.155547] [drm:drm_mode_debug_printmodeline [drm]] Modeline 92:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[ 4293.155554] [drm:drm_mode_debug_printmodeline [drm]] Modeline 97:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0xa
>[ 4293.155560] [drm:drm_mode_debug_printmodeline [drm]] Modeline 95:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[ 4293.155567] [drm:drm_mode_debug_printmodeline [drm]] Modeline 96:"1680x1050" 60 146250 1680 1784 1960 2240 1050 1053 1059 1089 0x40 0x6
>[ 4293.155572] [drm:drm_mode_debug_printmodeline [drm]] Modeline 94:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[ 4293.155578] [drm:drm_mode_debug_printmodeline [drm]] Modeline 93:"1280x960" 60 108000 1280 1376 1488 1800 960 961 964 1000 0x40 0x5
>[ 4293.155584] [drm:drm_mode_debug_printmodeline [drm]] Modeline 101:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[ 4293.155590] [drm:drm_mode_debug_printmodeline [drm]] Modeline 98:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[ 4293.155595] [drm:drm_mode_debug_printmodeline [drm]] Modeline 99:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[ 4293.155600] [drm:drm_mode_debug_printmodeline [drm]] Modeline 100:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[ 4293.155630] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:71:HDMI-A-2]
>[ 4293.155649] [drm:intel_hdmi_detect [i915]] [CONNECTOR:71:HDMI-A-2]
>[ 4293.158065] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[ 4293.158085] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[ 4293.160501] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[ 4293.160510] [drm:drm_do_probe_ddc_edid [drm]] drm: skipping non-existent adapter i915 gmbus dpc
>[ 4293.162444] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[ 4293.162462] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[ 4293.162860] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[ 4293.162865] [drm:drm_dp_dual_mode_detect [drm_kms_helper]] DP dual mode HDMI ID:  (err -6)
>[ 4293.162869] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:71:HDMI-A-2] disconnected
>[ 4293.162898] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:73:DP-3]
>[ 4293.162918] [drm:intel_dp_detect [i915]] [CONNECTOR:73:DP-3]
>[ 4293.163246] [drm:lspcon_wake_native_aux_ch [i915]] Native AUX CH up, DPCD version: 1.2
>[ 4293.163311] [drm:lspcon_resume [i915]] LSPCON recovering in PCON mode after 0 ms
>[ 4293.163728] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4293.164948] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4293.166172] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4293.167396] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4293.168616] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4293.169425] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[ 4293.169828] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 00 01 00 00 04 00 0f 00 04
>[ 4293.170515] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>[ 4293.170533] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000
>[ 4293.170549] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000
>[ 4293.170914] [drm:drm_dp_read_desc [drm_kms_helper]] DP branch: OUI 00-60-ad dev-ID MC2800 HW-rev 2.2 SW-rev 1.66 quirks 0x0000
>[ 4293.171204] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[ 4293.171933] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4293.173153] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4293.174383] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4293.175600] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4293.176822] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4293.178031] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4293.179254] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4293.180477] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4293.181689] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4293.182959] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4293.184304] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4293.185626] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4293.186956] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4293.188301] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4293.189617] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4293.190960] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4293.192297] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4293.193476] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4293.194700] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4293.195922] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4293.197134] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4293.198481] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4293.199827] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4293.201171] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4293.202518] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4293.203872] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4293.205222] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4293.206567] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4293.207903] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4293.208702] [drm:drm_detect_monitor_audio [drm]] Monitor has basic audio support
>[ 4293.208987] [drm:drm_add_edid_modes [drm]] ELD monitor ASUS PB287Q
>[ 4293.208995] [drm:drm_add_edid_modes [drm]] HDMI: latency present 0 0, video latency 0 1, audio latency 96 2
>[ 4293.209001] [drm:drm_add_edid_modes [drm]] ELD size 36, SAD count 1
>[ 4293.209007] [drm:drm_add_edid_modes [drm]] HDMI: DVI dual 0, max TMDS clock 300000 kHz
>[ 4293.209248] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:73:DP-3] probed modes :
>[ 4293.209255] [drm:drm_mode_debug_printmodeline [drm]] Modeline 105:"3840x2160" 30 297000 3840 4016 4104 4400 2160 2168 2178 2250 0x48 0x9
>[ 4293.209262] [drm:drm_mode_debug_printmodeline [drm]] Modeline 149:"3840x2160" 30 297000 3840 4016 4104 4400 2160 2168 2178 2250 0x40 0x5
>[ 4293.209268] [drm:drm_mode_debug_printmodeline [drm]] Modeline 165:"3840x2160" 30 296703 3840 4016 4104 4400 2160 2168 2178 2250 0x40 0x5
>[ 4293.209274] [drm:drm_mode_debug_printmodeline [drm]] Modeline 150:"3840x2160" 25 297000 3840 4896 4984 5280 2160 2168 2178 2250 0x40 0x5
>[ 4293.209279] [drm:drm_mode_debug_printmodeline [drm]] Modeline 151:"3840x2160" 24 297000 3840 5116 5204 5500 2160 2168 2178 2250 0x40 0x5
>[ 4293.209285] [drm:drm_mode_debug_printmodeline [drm]] Modeline 166:"3840x2160" 24 296703 3840 5116 5204 5500 2160 2168 2178 2250 0x40 0x5
>[ 4293.209291] [drm:drm_mode_debug_printmodeline [drm]] Modeline 108:"2560x1600" 60 268500 2560 2608 2640 2720 1600 1603 1609 1646 0x40 0x9
>[ 4293.209296] [drm:drm_mode_debug_printmodeline [drm]] Modeline 107:"2560x1440" 60 241500 2560 2608 2640 2720 1440 1443 1448 1481 0x40 0x5
>[ 4293.209302] [drm:drm_mode_debug_printmodeline [drm]] Modeline 106:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[ 4293.209307] [drm:drm_mode_debug_printmodeline [drm]] Modeline 152:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[ 4293.209313] [drm:drm_mode_debug_printmodeline [drm]] Modeline 140:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[ 4293.209318] [drm:drm_mode_debug_printmodeline [drm]] Modeline 159:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[ 4293.209324] [drm:drm_mode_debug_printmodeline [drm]] Modeline 145:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[ 4293.209329] [drm:drm_mode_debug_printmodeline [drm]] Modeline 139:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[ 4293.209334] [drm:drm_mode_debug_printmodeline [drm]] Modeline 148:"1920x1080" 30 74250 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[ 4293.209340] [drm:drm_mode_debug_printmodeline [drm]] Modeline 164:"1920x1080" 30 74176 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[ 4293.209345] [drm:drm_mode_debug_printmodeline [drm]] Modeline 147:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[ 4293.209350] [drm:drm_mode_debug_printmodeline [drm]] Modeline 163:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[ 4293.209355] [drm:drm_mode_debug_printmodeline [drm]] Modeline 114:"1680x1050" 60 119000 1680 1728 1760 1840 1050 1053 1059 1080 0x40 0x9
>[ 4293.209361] [drm:drm_mode_debug_printmodeline [drm]] Modeline 124:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[ 4293.209366] [drm:drm_mode_debug_printmodeline [drm]] Modeline 112:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[ 4293.209371] [drm:drm_mode_debug_printmodeline [drm]] Modeline 113:"1440x900" 60 88750 1440 1488 1520 1600 900 903 909 926 0x40 0x9
>[ 4293.209377] [drm:drm_mode_debug_printmodeline [drm]] Modeline 111:"1280x960" 60 108000 1280 1376 1488 1800 960 961 964 1000 0x40 0x5
>[ 4293.209382] [drm:drm_mode_debug_printmodeline [drm]] Modeline 115:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[ 4293.209387] [drm:drm_mode_debug_printmodeline [drm]] Modeline 116:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[ 4293.209392] [drm:drm_mode_debug_printmodeline [drm]] Modeline 153:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[ 4293.209398] [drm:drm_mode_debug_printmodeline [drm]] Modeline 109:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[ 4293.209403] [drm:drm_mode_debug_printmodeline [drm]] Modeline 143:"1440x576" 50 54000 1440 1464 1592 1728 576 581 586 625 0x40 0xa
>[ 4293.209408] [drm:drm_mode_debug_printmodeline [drm]] Modeline 125:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[ 4293.209413] [drm:drm_mode_debug_printmodeline [drm]] Modeline 126:"1024x768" 70 75000 1024 1048 1184 1328 768 771 777 806 0x40 0xa
>[ 4293.209418] [drm:drm_mode_debug_printmodeline [drm]] Modeline 127:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[ 4293.209423] [drm:drm_mode_debug_printmodeline [drm]] Modeline 160:"1440x480" 60 54054 1440 1472 1596 1716 480 489 495 525 0x40 0xa
>[ 4293.209429] [drm:drm_mode_debug_printmodeline [drm]] Modeline 141:"1440x480" 60 54000 1440 1472 1596 1716 480 489 495 525 0x40 0xa
>[ 4293.209434] [drm:drm_mode_debug_printmodeline [drm]] Modeline 128:"832x624" 75 57284 832 864 928 1152 624 625 628 667 0x40 0xa
>[ 4293.209439] [drm:drm_mode_debug_printmodeline [drm]] Modeline 129:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[ 4293.209444] [drm:drm_mode_debug_printmodeline [drm]] Modeline 130:"800x600" 72 50000 800 856 976 1040 600 637 643 666 0x40 0x5
>[ 4293.209450] [drm:drm_mode_debug_printmodeline [drm]] Modeline 117:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[ 4293.209455] [drm:drm_mode_debug_printmodeline [drm]] Modeline 118:"800x600" 56 36000 800 824 896 1024 600 601 603 625 0x40 0x5
>[ 4293.209460] [drm:drm_mode_debug_printmodeline [drm]] Modeline 110:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[ 4293.209465] [drm:drm_mode_debug_printmodeline [drm]] Modeline 156:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[ 4293.209470] [drm:drm_mode_debug_printmodeline [drm]] Modeline 132:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[ 4293.209475] [drm:drm_mode_debug_printmodeline [drm]] Modeline 119:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[ 4293.209481] [drm:drm_mode_debug_printmodeline [drm]] Modeline 120:"640x480" 73 31500 640 664 704 832 480 489 492 520 0x40 0xa
>[ 4293.209486] [drm:drm_mode_debug_printmodeline [drm]] Modeline 121:"640x480" 67 30240 640 704 768 864 480 483 486 525 0x40 0xa
>[ 4293.209491] [drm:drm_mode_debug_printmodeline [drm]] Modeline 154:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[ 4293.209496] [drm:drm_mode_debug_printmodeline [drm]] Modeline 122:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[ 4293.209501] [drm:drm_mode_debug_printmodeline [drm]] Modeline 123:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[ 4293.209557] [IGT] kms_plane_multiple: starting subtest atomic-pipe-B-tiling-yf
>[ 4293.209632] [drm:drm_mode_addfb2 [drm]] [FB:136]
>[ 4293.211633] [drm:intel_atomic_check [i915]] [CONNECTOR:58:DP-1] checking for sink bpp constrains
>[ 4293.211652] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 4293.211671] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 148500KHz
>[ 4293.211689] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 4293.211705] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 648000
>[ 4293.211722] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 4293.211740] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe B][modeset]
>[ 4293.211756] [drm:intel_dump_pipe_config [i915]] output_types: DP (0x80)
>[ 4293.211773] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 4293.211789] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5767168, gmch_n: 8388608, link_m: 240298, link_n: 262144, tu: 64
>[ 4293.211805] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[ 4293.211820] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 4293.211830] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[ 4293.211845] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 4293.211853] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[ 4293.211869] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[ 4293.211885] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1080, pixel rate 148500
>[ 4293.211900] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[ 4293.211915] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 4293.211930] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 4293.211947] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[ 4293.211962] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 4293.211979] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 1B] FB:133, fb = 3840x2160 format = XR24 little-endian (0x34325258)
>[ 4293.211994] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1200 dst 0x0+1920+1200
>[ 4293.212009] [drm:intel_dump_pipe_config [i915]] [PLANE:40:plane 2B] disabled, scaler_id = -1
>[ 4293.212025] [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor B] disabled, scaler_id = -1
>[ 4293.212042] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 4293.212058] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[ 4293.212079] [drm:intel_find_shared_dpll [i915]] [CRTC:46:pipe B] allocated DPLL 1
>[ 4293.212095] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[ 4293.212409] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 4293.214434] [drm:intel_power_well_disable [i915]] disabling DDI B IO power well
>[ 4293.214454] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 4293.214473] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 3, on? 1) for crtc 36
>[ 4293.214502] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 4293.231074] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well
>[ 4293.231097] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 2, on? 1) for crtc 46
>[ 4293.231118] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[ 4293.231140] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 4293.231161] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[ 4293.231188] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 4293.237544] [drm:intel_power_well_disable [i915]] disabling DDI D IO power well
>[ 4293.237570] [drm:intel_disable_shared_dpll [i915]] disable DPLL 2 (active 4, on? 1) for crtc 56
>[ 4293.237593] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 2
>[ 4293.237625] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DDI B]
>[ 4293.237647] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST A]
>[ 4293.237667] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST B]
>[ 4293.237687] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST C]
>[ 4293.237707] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI C]
>[ 4293.237727] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[ 4293.237746] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[ 4293.237765] [drm:intel_atomic_commit_tail [i915]] [ENCODER:70:DP-MST C]
>[ 4293.237784] [drm:intel_atomic_commit_tail [i915]] [ENCODER:72:DDI D]
>[ 4293.237804] [drm:intel_atomic_commit_tail [i915]] [ENCODER:74:DP-MST A]
>[ 4293.237823] [drm:intel_atomic_commit_tail [i915]] [ENCODER:75:DP-MST B]
>[ 4293.237841] [drm:intel_atomic_commit_tail [i915]] [ENCODER:76:DP-MST C]
>[ 4293.237861] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:64:HDMI-A-1]
>[ 4293.237881] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:67:DP-2]
>[ 4293.237902] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:71:HDMI-A-2]
>[ 4293.237924] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:73:DP-3]
>[ 4293.237944] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[ 4293.237964] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[ 4293.237983] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[ 4293.238002] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[ 4293.238025] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 2, on? 0) for crtc 46
>[ 4293.238045] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[ 4293.240146] [drm:intel_power_well_enable [i915]] enabling DDI B IO power well
>[ 4293.242318] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 4293.242343] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 4293.242367] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 4293.242390] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 4293.244086] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 04000000
>[ 4293.244111] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[ 4293.244135] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 4293.245821] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 4293.245846] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 4293.247843] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[ 4293.247868] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[ 4293.247891] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[ 4293.248804] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 4293.250287] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:58:DP-1] Link Training Passed at Link Rate = 162000, Lane count = 4
>[ 4293.250731] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 4293.250762] [drm:intel_edp_drrs_enable [i915]] Panel doesn't support DRRS
>[ 4293.267587] [drm:intel_atomic_commit_tail [i915]] [CRTC:36:pipe A]
>[ 4293.267656] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:58:DP-1]
>[ 4293.267705] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe B]
>[ 4293.267766] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[ 4293.267813] [drm:intel_atomic_commit_tail [i915]] [CRTC:56:pipe C]
>[ 4293.267850] [drm:intel_enable_sagv [i915]] Enabling the SAGV
>[ 4293.318013] [drm:drm_mode_addfb2 [drm]] [FB:134]
>[ 4293.318830] [drm:drm_mode_addfb2 [drm]] [FB:135]
>[ 4293.320857] [drm:drm_mode_addfb2 [drm]] [FB:137]
>[ 4293.351255] [drm:drm_mode_addfb2 [drm]] [FB:138]
>[ 4293.356977] [drm:intel_atomic_check [i915]] [CONNECTOR:67:DP-2] checking for sink bpp constrains
>[ 4293.357045] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 4293.357113] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 4293.357177] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 4293.357237] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 4293.357301] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 4293.357365] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe B][modeset]
>[ 4293.357425] [drm:intel_dump_pipe_config [i915]] output_types: DP (0x80)
>[ 4293.357484] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 4293.357543] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 4293.357600] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[ 4293.357656] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 4293.357688] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[ 4293.357747] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 4293.357775] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[ 4293.357835] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[ 4293.357892] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 4293.357949] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[ 4293.358005] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 4293.358059] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 4293.358120] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[ 4293.358176] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 4293.358262] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 1B] FB:137, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[ 4293.358331] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[ 4293.358398] [drm:intel_dump_pipe_config [i915]] [PLANE:40:plane 2B] FB:134, fb = 256x256 format = XR24 little-endian (0x34325258)
>[ 4293.358462] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+256+256 dst 251x374+256+256
>[ 4293.358528] [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor B] FB:135, fb = 128x128 format = AR24 little-endian (0x34325241)
>[ 4293.358591] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+128+128 dst 1609x754+128+128
>[ 4293.358664] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 4293.358729] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[ 4293.358805] [drm:intel_find_shared_dpll [i915]] [CRTC:46:pipe B] allocated DPLL 1
>[ 4293.358867] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[ 4293.359631] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 4293.368745] [drm:intel_power_well_disable [i915]] disabling DDI B IO power well
>[ 4293.368817] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 2, on? 1) for crtc 46
>[ 4293.368881] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[ 4293.368947] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DDI B]
>[ 4293.369008] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST A]
>[ 4293.369064] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST B]
>[ 4293.369118] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST C]
>[ 4293.369173] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI C]
>[ 4293.369226] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[ 4293.369279] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[ 4293.369331] [drm:intel_atomic_commit_tail [i915]] [ENCODER:70:DP-MST C]
>[ 4293.369383] [drm:intel_atomic_commit_tail [i915]] [ENCODER:72:DDI D]
>[ 4293.369435] [drm:intel_atomic_commit_tail [i915]] [ENCODER:74:DP-MST A]
>[ 4293.369487] [drm:intel_atomic_commit_tail [i915]] [ENCODER:75:DP-MST B]
>[ 4293.369539] [drm:intel_atomic_commit_tail [i915]] [ENCODER:76:DP-MST C]
>[ 4293.369594] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:58:DP-1]
>[ 4293.369650] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[ 4293.369706] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[ 4293.369760] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[ 4293.369813] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[ 4293.369874] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 2, on? 0) for crtc 46
>[ 4293.369929] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[ 4293.372061] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well
>[ 4293.373899] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 4293.373961] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 4293.374017] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 4293.374072] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 4293.376657] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 4293.376720] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 4293.378473] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 4293.380619] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:67:DP-2] Link Training Passed at Link Rate = 162000, Lane count = 4
>[ 4293.381583] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 4293.381652] [drm:intel_edp_drrs_enable [i915]] Panel doesn't support DRRS
>[ 4293.398468] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:67:DP-2]
>[ 4293.398545] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe B]
>[ 4293.398632] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[ 4293.449046] [drm:drm_mode_addfb2 [drm]] [FB:142]
>[ 4293.449663] [drm:drm_mode_addfb2 [drm]] [FB:144]
>[ 4293.452456] [drm:drm_mode_addfb2 [drm]] [FB:146]
>[ 4293.482186] [drm:drm_mode_addfb2 [drm]] [FB:155]
>[ 4293.501945] [drm:intel_atomic_check [i915]] [CONNECTOR:73:DP-3] checking for sink bpp constrains
>[ 4293.502014] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 4293.502081] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 297000KHz
>[ 4293.502147] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 4 clock 270000 bpp 24
>[ 4293.502206] [drm:intel_dp_compute_config [i915]] DP link bw required 891000 available 1080000
>[ 4293.502294] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 4293.502371] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe B][modeset]
>[ 4293.502444] [drm:intel_dump_pipe_config [i915]] output_types: DP (0x80)
>[ 4293.502511] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 4293.502579] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6920601, gmch_n: 8388608, link_m: 576716, link_n: 524288, tu: 64
>[ 4293.502642] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 4293.502703] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 4293.502737] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"3840x2160" 30 297000 3840 4016 4104 4400 2160 2168 2178 2250 0x48 0x9
>[ 4293.502799] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 4293.502830] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"3840x2160" 30 297000 3840 4016 4104 4400 2160 2168 2178 2250 0x48 0x9
>[ 4293.502894] [drm:intel_dump_pipe_config [i915]] crtc timings: 297000 3840 4016 4104 4400 2160 2168 2178 2250, type: 0x48 flags: 0x9
>[ 4293.502954] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 3840x2160, pixel rate 297000
>[ 4293.503014] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[ 4293.503071] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 4293.503129] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 4293.503192] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[ 4293.503251] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 4293.503313] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 1B] FB:146, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[ 4293.503372] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1200 dst 0x0+1920+1200
>[ 4293.503432] [drm:intel_dump_pipe_config [i915]] [PLANE:40:plane 2B] FB:142, fb = 256x256 format = XR24 little-endian (0x34325258)
>[ 4293.503490] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+256+256 dst 128x737+256+256
>[ 4293.503549] [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor B] FB:144, fb = 128x128 format = AR24 little-endian (0x34325241)
>[ 4293.503607] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+128+128 dst 577x776+128+128
>[ 4293.503673] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 4293.503734] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[ 4293.503808] [drm:intel_find_shared_dpll [i915]] [CRTC:46:pipe B] allocated DPLL 1
>[ 4293.503871] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[ 4293.506163] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 4293.516972] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well
>[ 4293.517044] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 2, on? 1) for crtc 46
>[ 4293.517107] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[ 4293.517175] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DDI B]
>[ 4293.517235] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST A]
>[ 4293.517292] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST B]
>[ 4293.517347] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST C]
>[ 4293.517402] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI C]
>[ 4293.517458] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[ 4293.517511] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[ 4293.517564] [drm:intel_atomic_commit_tail [i915]] [ENCODER:70:DP-MST C]
>[ 4293.517616] [drm:intel_atomic_commit_tail [i915]] [ENCODER:72:DDI D]
>[ 4293.517668] [drm:intel_atomic_commit_tail [i915]] [ENCODER:74:DP-MST A]
>[ 4293.517720] [drm:intel_atomic_commit_tail [i915]] [ENCODER:75:DP-MST B]
>[ 4293.517772] [drm:intel_atomic_commit_tail [i915]] [ENCODER:76:DP-MST C]
>[ 4293.517826] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:67:DP-2]
>[ 4293.517883] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[ 4293.517939] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[ 4293.517994] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[ 4293.518048] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[ 4293.518108] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 2, on? 0) for crtc 46
>[ 4293.518163] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[ 4293.520337] [drm:intel_power_well_enable [i915]] enabling DDI D IO power well
>[ 4293.520946] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4293.522225] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4293.523504] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4293.524757] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4293.526020] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4293.526899] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[ 4293.527882] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 4293.527940] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 4293.527995] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 4293.528050] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 4293.546803] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 4293.546847] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[ 4293.565500] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 4293.567589] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:73:DP-3] Link Training Passed at Link Rate = 270000, Lane count = 4
>[ 4293.568000] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 4293.568022] [drm:intel_edp_drrs_enable [i915]] Panel doesn't support DRRS
>[ 4293.568041] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:73:DP-3], [ENCODER:72:DDI D]
>[ 4293.568059] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 4293.568079] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 4293.601473] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:73:DP-3]
>[ 4293.601500] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe B]
>[ 4293.601534] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[ 4293.702056] [drm:drm_mode_addfb2 [drm]] [FB:157]
>[ 4293.702701] [drm:drm_mode_addfb2 [drm]] [FB:158]
>[ 4293.711518] [drm:drm_mode_addfb2 [drm]] [FB:161]
>[ 4293.768576] [drm:drm_mode_addfb2 [drm]] [FB:162]
>[ 4293.773977] [drm:intel_atomic_check [i915]] [CONNECTOR:58:DP-1] checking for sink bpp constrains
>[ 4293.774046] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 4293.774114] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 148500KHz
>[ 4293.774179] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 4293.774263] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 648000
>[ 4293.774341] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 4293.774414] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe B][modeset]
>[ 4293.774476] [drm:intel_dump_pipe_config [i915]] output_types: DP (0x80)
>[ 4293.774538] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 4293.774602] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5767168, gmch_n: 8388608, link_m: 240298, link_n: 262144, tu: 64
>[ 4293.774662] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[ 4293.774722] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 4293.774757] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[ 4293.774818] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 4293.774849] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[ 4293.774912] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[ 4293.774972] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1080, pixel rate 148500
>[ 4293.775031] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[ 4293.775090] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 4293.775148] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 4293.775211] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x3, cfgcr1: 0x0, cfgcr2: 0x0
>[ 4293.775269] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 4293.775331] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 1B] FB:161, fb = 3840x2160 format = XR24 little-endian (0x34325258)
>[ 4293.775392] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+3840+2160 dst 0x0+3840+2160
>[ 4293.775451] [drm:intel_dump_pipe_config [i915]] [PLANE:40:plane 2B] FB:157, fb = 256x256 format = XR24 little-endian (0x34325258)
>[ 4293.775511] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+256+256 dst 421x769+256+256
>[ 4293.775571] [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor B] FB:158, fb = 128x128 format = AR24 little-endian (0x34325241)
>[ 4293.775630] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+128+128 dst 3404x1459+128+128
>[ 4293.775696] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 4293.775756] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[ 4293.775829] [drm:intel_find_shared_dpll [i915]] [CRTC:46:pipe B] allocated DPLL 1
>[ 4293.775891] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[ 4293.776608] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 4293.776677] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[ 4293.776760] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 4293.803313] [drm:intel_power_well_disable [i915]] disabling DDI D IO power well
>[ 4293.803385] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 2, on? 1) for crtc 46
>[ 4293.803448] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[ 4293.803517] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DDI B]
>[ 4293.803575] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST A]
>[ 4293.803632] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST B]
>[ 4293.803686] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST C]
>[ 4293.803740] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI C]
>[ 4293.803793] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[ 4293.803846] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[ 4293.803898] [drm:intel_atomic_commit_tail [i915]] [ENCODER:70:DP-MST C]
>[ 4293.803951] [drm:intel_atomic_commit_tail [i915]] [ENCODER:72:DDI D]
>[ 4293.804005] [drm:intel_atomic_commit_tail [i915]] [ENCODER:74:DP-MST A]
>[ 4293.804056] [drm:intel_atomic_commit_tail [i915]] [ENCODER:75:DP-MST B]
>[ 4293.804108] [drm:intel_atomic_commit_tail [i915]] [ENCODER:76:DP-MST C]
>[ 4293.804163] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:73:DP-3]
>[ 4293.804218] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[ 4293.804273] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[ 4293.804327] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[ 4293.804381] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[ 4293.804441] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 2, on? 0) for crtc 46
>[ 4293.804496] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[ 4293.806365] [drm:intel_power_well_enable [i915]] enabling DDI B IO power well
>[ 4293.807547] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 4293.807608] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 4293.807666] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 4293.807722] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 4293.809511] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 04000000
>[ 4293.809574] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[ 4293.809632] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 4293.811432] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 4293.811495] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 4293.813588] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[ 4293.813650] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[ 4293.813707] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[ 4293.814684] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 4293.816792] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:58:DP-1] Link Training Passed at Link Rate = 162000, Lane count = 4
>[ 4293.817434] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 4293.817498] [drm:intel_edp_drrs_enable [i915]] Panel doesn't support DRRS
>[ 4293.834275] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:58:DP-1]
>[ 4293.834343] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe B]
>[ 4293.834423] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[ 4293.884784] [drm:drm_mode_addfb2 [drm]] [FB:167]
>[ 4293.885511] [drm:drm_mode_addfb2 [drm]] [FB:168]
>[ 4293.887928] [drm:drm_mode_addfb2 [drm]] [FB:169]
>[ 4293.918041] [drm:drm_mode_addfb2 [drm]] [FB:170]
>[ 4293.924150] [drm:intel_atomic_check [i915]] [CONNECTOR:67:DP-2] checking for sink bpp constrains
>[ 4293.924218] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 4293.924284] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 4293.924350] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 4293.924410] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 4293.924474] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 4293.924537] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe B][modeset]
>[ 4293.924599] [drm:intel_dump_pipe_config [i915]] output_types: DP (0x80)
>[ 4293.924658] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 4293.924718] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 4293.924774] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[ 4293.924830] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 4293.924862] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[ 4293.924920] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 4293.924949] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[ 4293.925009] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[ 4293.925067] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 4293.925124] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[ 4293.925181] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 4293.925236] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 4293.925297] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[ 4293.925354] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 4293.925414] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 1B] FB:169, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[ 4293.925471] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[ 4293.925529] [drm:intel_dump_pipe_config [i915]] [PLANE:40:plane 2B] FB:167, fb = 256x256 format = XR24 little-endian (0x34325258)
>[ 4293.925586] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+256+256 dst 1190x444+256+256
>[ 4293.925643] [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor B] FB:168, fb = 128x128 format = AR24 little-endian (0x34325241)
>[ 4293.925700] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+128+128 dst 1424x420+128+128
>[ 4293.925763] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 4293.925822] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[ 4293.925892] [drm:intel_find_shared_dpll [i915]] [CRTC:46:pipe B] allocated DPLL 1
>[ 4293.925952] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[ 4293.926738] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 4293.934458] [drm:intel_power_well_disable [i915]] disabling DDI B IO power well
>[ 4293.934530] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 2, on? 1) for crtc 46
>[ 4293.934595] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[ 4293.934663] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DDI B]
>[ 4293.934724] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST A]
>[ 4293.934781] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST B]
>[ 4293.934836] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST C]
>[ 4293.934891] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI C]
>[ 4293.934946] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[ 4293.935000] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[ 4293.935052] [drm:intel_atomic_commit_tail [i915]] [ENCODER:70:DP-MST C]
>[ 4293.935104] [drm:intel_atomic_commit_tail [i915]] [ENCODER:72:DDI D]
>[ 4293.935156] [drm:intel_atomic_commit_tail [i915]] [ENCODER:74:DP-MST A]
>[ 4293.935208] [drm:intel_atomic_commit_tail [i915]] [ENCODER:75:DP-MST B]
>[ 4293.935259] [drm:intel_atomic_commit_tail [i915]] [ENCODER:76:DP-MST C]
>[ 4293.935314] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:58:DP-1]
>[ 4293.935371] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[ 4293.935427] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[ 4293.935482] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[ 4293.935536] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[ 4293.935597] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 2, on? 0) for crtc 46
>[ 4293.935653] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[ 4293.937797] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well
>[ 4293.939676] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 4293.939737] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 4293.939793] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 4293.939850] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 4293.942435] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 4293.942498] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 4293.944247] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 4293.946364] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:67:DP-2] Link Training Passed at Link Rate = 162000, Lane count = 4
>[ 4293.947367] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 4293.947439] [drm:intel_edp_drrs_enable [i915]] Panel doesn't support DRRS
>[ 4293.964241] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:67:DP-2]
>[ 4293.964318] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe B]
>[ 4293.964404] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[ 4294.014686] [drm:drm_mode_addfb2 [drm]] [FB:171]
>[ 4294.015282] [drm:drm_mode_addfb2 [drm]] [FB:172]
>[ 4294.017874] [drm:drm_mode_addfb2 [drm]] [FB:173]
>[ 4294.047990] [drm:drm_mode_addfb2 [drm]] [FB:174]
>[ 4294.067697] [drm:intel_atomic_check [i915]] [CONNECTOR:73:DP-3] checking for sink bpp constrains
>[ 4294.067766] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 4294.067833] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 297000KHz
>[ 4294.067898] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 4 clock 270000 bpp 24
>[ 4294.067959] [drm:intel_dp_compute_config [i915]] DP link bw required 891000 available 1080000
>[ 4294.068023] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 4294.068086] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe B][modeset]
>[ 4294.068147] [drm:intel_dump_pipe_config [i915]] output_types: DP (0x80)
>[ 4294.068206] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 4294.068265] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6920601, gmch_n: 8388608, link_m: 576716, link_n: 524288, tu: 64
>[ 4294.068323] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 4294.068379] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 4294.068412] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"3840x2160" 30 297000 3840 4016 4104 4400 2160 2168 2178 2250 0x48 0x9
>[ 4294.068470] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 4294.068498] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"3840x2160" 30 297000 3840 4016 4104 4400 2160 2168 2178 2250 0x48 0x9
>[ 4294.068559] [drm:intel_dump_pipe_config [i915]] crtc timings: 297000 3840 4016 4104 4400 2160 2168 2178 2250, type: 0x48 flags: 0x9
>[ 4294.068617] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 3840x2160, pixel rate 297000
>[ 4294.068674] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[ 4294.068729] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 4294.068784] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 4294.068845] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[ 4294.068900] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 4294.068959] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 1B] FB:173, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[ 4294.069016] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1200 dst 0x0+1920+1200
>[ 4294.069073] [drm:intel_dump_pipe_config [i915]] [PLANE:40:plane 2B] FB:171, fb = 256x256 format = XR24 little-endian (0x34325258)
>[ 4294.069130] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+256+256 dst 1575x633+256+256
>[ 4294.069187] [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor B] FB:172, fb = 128x128 format = AR24 little-endian (0x34325241)
>[ 4294.069242] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+128+128 dst 27x822+128+128
>[ 4294.069305] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 4294.069364] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[ 4294.069436] [drm:intel_find_shared_dpll [i915]] [CRTC:46:pipe B] allocated DPLL 1
>[ 4294.069496] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[ 4294.071835] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 4294.082647] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well
>[ 4294.082720] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 2, on? 1) for crtc 46
>[ 4294.082784] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[ 4294.082854] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DDI B]
>[ 4294.082913] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST A]
>[ 4294.082970] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST B]
>[ 4294.083025] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST C]
>[ 4294.083079] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI C]
>[ 4294.083136] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[ 4294.083189] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[ 4294.083242] [drm:intel_atomic_commit_tail [i915]] [ENCODER:70:DP-MST C]
>[ 4294.083295] [drm:intel_atomic_commit_tail [i915]] [ENCODER:72:DDI D]
>[ 4294.083348] [drm:intel_atomic_commit_tail [i915]] [ENCODER:74:DP-MST A]
>[ 4294.083400] [drm:intel_atomic_commit_tail [i915]] [ENCODER:75:DP-MST B]
>[ 4294.083452] [drm:intel_atomic_commit_tail [i915]] [ENCODER:76:DP-MST C]
>[ 4294.083507] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:67:DP-2]
>[ 4294.083563] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[ 4294.083619] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[ 4294.083673] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[ 4294.083727] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[ 4294.083786] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 2, on? 0) for crtc 46
>[ 4294.083842] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[ 4294.085993] [drm:intel_power_well_enable [i915]] enabling DDI D IO power well
>[ 4294.086636] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4294.087917] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4294.089179] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4294.090440] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4294.091700] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4294.092576] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[ 4294.093557] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 4294.093615] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 4294.093671] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 4294.093727] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 4294.112497] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 4294.112542] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[ 4294.131216] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 4294.133305] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:73:DP-3] Link Training Passed at Link Rate = 270000, Lane count = 4
>[ 4294.133702] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 4294.133725] [drm:intel_edp_drrs_enable [i915]] Panel doesn't support DRRS
>[ 4294.133744] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:73:DP-3], [ENCODER:72:DDI D]
>[ 4294.133761] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 4294.133781] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 4294.167145] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:73:DP-3]
>[ 4294.167173] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe B]
>[ 4294.167207] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[ 4294.267761] [drm:drm_mode_addfb2 [drm]] [FB:175]
>[ 4294.268436] [drm:drm_mode_addfb2 [drm]] [FB:176]
>[ 4294.277652] [drm:drm_mode_addfb2 [drm]] [FB:177]
>[ 4294.334394] [drm:drm_mode_addfb2 [drm]] [FB:178]
>[ 4294.339904] [drm:intel_atomic_check [i915]] [CONNECTOR:58:DP-1] checking for sink bpp constrains
>[ 4294.339999] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 4294.340076] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 148500KHz
>[ 4294.340148] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 4294.340215] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 648000
>[ 4294.340287] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 4294.340358] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe B][modeset]
>[ 4294.340425] [drm:intel_dump_pipe_config [i915]] output_types: DP (0x80)
>[ 4294.340492] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 4294.340559] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5767168, gmch_n: 8388608, link_m: 240298, link_n: 262144, tu: 64
>[ 4294.340624] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[ 4294.340687] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 4294.340723] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[ 4294.340787] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 4294.340820] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[ 4294.340888] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[ 4294.340953] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1080, pixel rate 148500
>[ 4294.341017] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[ 4294.341081] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 4294.341144] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 4294.341212] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x3, cfgcr1: 0x0, cfgcr2: 0x0
>[ 4294.341274] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 4294.341340] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 1B] FB:177, fb = 3840x2160 format = XR24 little-endian (0x34325258)
>[ 4294.341404] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+3840+2160 dst 0x0+3840+2160
>[ 4294.341468] [drm:intel_dump_pipe_config [i915]] [PLANE:40:plane 2B] FB:175, fb = 256x256 format = XR24 little-endian (0x34325258)
>[ 4294.341531] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+256+256 dst 2292x891+256+256
>[ 4294.341595] [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor B] FB:176, fb = 128x128 format = AR24 little-endian (0x34325241)
>[ 4294.341658] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+128+128 dst 130x545+128+128
>[ 4294.341729] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 4294.341795] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[ 4294.341873] [drm:intel_find_shared_dpll [i915]] [CRTC:46:pipe B] allocated DPLL 1
>[ 4294.341939] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[ 4294.342701] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 4294.342782] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[ 4294.342878] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 4294.369324] [drm:intel_power_well_disable [i915]] disabling DDI D IO power well
>[ 4294.369404] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 2, on? 1) for crtc 46
>[ 4294.369476] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[ 4294.369554] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DDI B]
>[ 4294.369619] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST A]
>[ 4294.369683] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST B]
>[ 4294.369744] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST C]
>[ 4294.369804] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI C]
>[ 4294.369863] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[ 4294.369923] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[ 4294.369981] [drm:intel_atomic_commit_tail [i915]] [ENCODER:70:DP-MST C]
>[ 4294.370039] [drm:intel_atomic_commit_tail [i915]] [ENCODER:72:DDI D]
>[ 4294.370099] [drm:intel_atomic_commit_tail [i915]] [ENCODER:74:DP-MST A]
>[ 4294.370157] [drm:intel_atomic_commit_tail [i915]] [ENCODER:75:DP-MST B]
>[ 4294.370252] [drm:intel_atomic_commit_tail [i915]] [ENCODER:76:DP-MST C]
>[ 4294.370325] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:73:DP-3]
>[ 4294.370399] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[ 4294.370468] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[ 4294.370539] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[ 4294.370606] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[ 4294.370680] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 2, on? 0) for crtc 46
>[ 4294.370745] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[ 4294.373002] [drm:intel_power_well_enable [i915]] enabling DDI B IO power well
>[ 4294.374167] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 4294.374270] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 4294.374344] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 4294.374418] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 4294.376233] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 04000000
>[ 4294.376304] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[ 4294.376368] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 4294.378168] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 4294.378266] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 4294.380336] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[ 4294.380393] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[ 4294.380447] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[ 4294.381410] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 4294.383558] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:58:DP-1] Link Training Passed at Link Rate = 162000, Lane count = 4
>[ 4294.384240] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 4294.384310] [drm:intel_edp_drrs_enable [i915]] Panel doesn't support DRRS
>[ 4294.401124] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:58:DP-1]
>[ 4294.401202] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe B]
>[ 4294.401290] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[ 4294.451590] [drm:drm_mode_addfb2 [drm]] [FB:179]
>[ 4294.452199] [drm:drm_mode_addfb2 [drm]] [FB:180]
>[ 4294.454346] [drm:drm_mode_addfb2 [drm]] [FB:181]
>[ 4294.484745] [drm:drm_mode_addfb2 [drm]] [FB:182]
>[ 4294.490503] [drm:intel_atomic_check [i915]] [CONNECTOR:67:DP-2] checking for sink bpp constrains
>[ 4294.490571] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 4294.490638] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 4294.490702] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 4294.490762] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 4294.490826] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 4294.490888] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe B][modeset]
>[ 4294.490949] [drm:intel_dump_pipe_config [i915]] output_types: DP (0x80)
>[ 4294.491009] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 4294.491069] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 4294.491127] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[ 4294.491184] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 4294.491215] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[ 4294.491274] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 4294.491303] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[ 4294.491363] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[ 4294.491421] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 4294.491478] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[ 4294.491535] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 4294.491592] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 4294.491654] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[ 4294.491710] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 4294.491770] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 1B] FB:181, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[ 4294.491826] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[ 4294.491884] [drm:intel_dump_pipe_config [i915]] [PLANE:40:plane 2B] FB:179, fb = 256x256 format = XR24 little-endian (0x34325258)
>[ 4294.491940] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+256+256 dst 1149x402+256+256
>[ 4294.491996] [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor B] FB:180, fb = 128x128 format = AR24 little-endian (0x34325241)
>[ 4294.492052] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+128+128 dst 1726x12+128+128
>[ 4294.492116] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 4294.492176] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[ 4294.492244] [drm:intel_find_shared_dpll [i915]] [CRTC:46:pipe B] allocated DPLL 1
>[ 4294.492304] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[ 4294.493071] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 4294.502942] [drm:intel_power_well_disable [i915]] disabling DDI B IO power well
>[ 4294.503016] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 2, on? 1) for crtc 46
>[ 4294.503080] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[ 4294.503149] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DDI B]
>[ 4294.503210] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST A]
>[ 4294.503268] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST B]
>[ 4294.503325] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST C]
>[ 4294.503379] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI C]
>[ 4294.503433] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[ 4294.503488] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[ 4294.503541] [drm:intel_atomic_commit_tail [i915]] [ENCODER:70:DP-MST C]
>[ 4294.503594] [drm:intel_atomic_commit_tail [i915]] [ENCODER:72:DDI D]
>[ 4294.503647] [drm:intel_atomic_commit_tail [i915]] [ENCODER:74:DP-MST A]
>[ 4294.503700] [drm:intel_atomic_commit_tail [i915]] [ENCODER:75:DP-MST B]
>[ 4294.503753] [drm:intel_atomic_commit_tail [i915]] [ENCODER:76:DP-MST C]
>[ 4294.503807] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:58:DP-1]
>[ 4294.503864] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[ 4294.503919] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[ 4294.503973] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[ 4294.504027] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[ 4294.504087] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 2, on? 0) for crtc 46
>[ 4294.504142] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[ 4294.506362] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well
>[ 4294.508220] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 4294.508280] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 4294.508337] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 4294.508393] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 4294.510975] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 4294.511038] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 4294.512788] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 4294.514372] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:67:DP-2] Link Training Passed at Link Rate = 162000, Lane count = 4
>[ 4294.515371] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 4294.515445] [drm:intel_edp_drrs_enable [i915]] Panel doesn't support DRRS
>[ 4294.532363] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:67:DP-2]
>[ 4294.532441] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe B]
>[ 4294.532529] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[ 4294.582913] [drm:drm_mode_addfb2 [drm]] [FB:183]
>[ 4294.583631] [drm:drm_mode_addfb2 [drm]] [FB:184]
>[ 4294.586572] [drm:drm_mode_addfb2 [drm]] [FB:185]
>[ 4294.616186] [drm:drm_mode_addfb2 [drm]] [FB:186]
>[ 4294.637009] [drm:intel_atomic_check [i915]] [CONNECTOR:73:DP-3] checking for sink bpp constrains
>[ 4294.637077] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 4294.637144] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 297000KHz
>[ 4294.637208] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 4 clock 270000 bpp 24
>[ 4294.637268] [drm:intel_dp_compute_config [i915]] DP link bw required 891000 available 1080000
>[ 4294.637331] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 4294.637394] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe B][modeset]
>[ 4294.637455] [drm:intel_dump_pipe_config [i915]] output_types: DP (0x80)
>[ 4294.637514] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 4294.637573] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6920601, gmch_n: 8388608, link_m: 576716, link_n: 524288, tu: 64
>[ 4294.637630] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 4294.637687] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 4294.637720] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"3840x2160" 30 297000 3840 4016 4104 4400 2160 2168 2178 2250 0x48 0x9
>[ 4294.637779] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 4294.637807] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"3840x2160" 30 297000 3840 4016 4104 4400 2160 2168 2178 2250 0x48 0x9
>[ 4294.637868] [drm:intel_dump_pipe_config [i915]] crtc timings: 297000 3840 4016 4104 4400 2160 2168 2178 2250, type: 0x48 flags: 0x9
>[ 4294.637926] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 3840x2160, pixel rate 297000
>[ 4294.637983] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[ 4294.638040] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 4294.638095] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 4294.638155] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[ 4294.638244] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 4294.638316] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 1B] FB:185, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[ 4294.638383] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1200 dst 0x0+1920+1200
>[ 4294.638446] [drm:intel_dump_pipe_config [i915]] [PLANE:40:plane 2B] FB:183, fb = 256x256 format = XR24 little-endian (0x34325258)
>[ 4294.638511] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+256+256 dst 386x685+256+256
>[ 4294.638576] [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor B] FB:184, fb = 128x128 format = AR24 little-endian (0x34325241)
>[ 4294.638640] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+128+128 dst 1416x59+128+128
>[ 4294.638712] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 4294.638779] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[ 4294.638857] [drm:intel_find_shared_dpll [i915]] [CRTC:46:pipe B] allocated DPLL 1
>[ 4294.638919] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[ 4294.641252] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 4294.650194] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well
>[ 4294.650287] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 2, on? 1) for crtc 46
>[ 4294.650352] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[ 4294.650421] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DDI B]
>[ 4294.650479] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST A]
>[ 4294.650536] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST B]
>[ 4294.650591] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST C]
>[ 4294.650645] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI C]
>[ 4294.650701] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[ 4294.650755] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[ 4294.650807] [drm:intel_atomic_commit_tail [i915]] [ENCODER:70:DP-MST C]
>[ 4294.650860] [drm:intel_atomic_commit_tail [i915]] [ENCODER:72:DDI D]
>[ 4294.650913] [drm:intel_atomic_commit_tail [i915]] [ENCODER:74:DP-MST A]
>[ 4294.650965] [drm:intel_atomic_commit_tail [i915]] [ENCODER:75:DP-MST B]
>[ 4294.651018] [drm:intel_atomic_commit_tail [i915]] [ENCODER:76:DP-MST C]
>[ 4294.651073] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:67:DP-2]
>[ 4294.651129] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[ 4294.651185] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[ 4294.651240] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[ 4294.651293] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[ 4294.651353] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 2, on? 0) for crtc 46
>[ 4294.651408] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[ 4294.653638] [drm:intel_power_well_enable [i915]] enabling DDI D IO power well
>[ 4294.654276] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4294.655550] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4294.656812] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4294.658068] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4294.659344] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4294.660205] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[ 4294.661189] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 4294.661246] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 4294.661300] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 4294.661355] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 4294.680098] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 4294.680143] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[ 4294.698740] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 4294.700909] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:73:DP-3] Link Training Passed at Link Rate = 270000, Lane count = 4
>[ 4294.701302] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 4294.701324] [drm:intel_edp_drrs_enable [i915]] Panel doesn't support DRRS
>[ 4294.701340] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:73:DP-3], [ENCODER:72:DDI D]
>[ 4294.701356] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 4294.701374] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 4294.734849] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:73:DP-3]
>[ 4294.734872] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe B]
>[ 4294.734900] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[ 4294.835442] [drm:drm_mode_addfb2 [drm]] [FB:187]
>[ 4294.836079] [drm:drm_mode_addfb2 [drm]] [FB:188]
>[ 4294.845325] [drm:drm_mode_addfb2 [drm]] [FB:189]
>[ 4294.901907] [IGT] kms_plane_multiple: exiting, ret=0
>[ 4295.001787] [drm:intel_atomic_check [i915]] [CONNECTOR:58:DP-1] checking for sink bpp constrains
>[ 4295.001856] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 4295.001924] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 148500KHz
>[ 4295.001989] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 4295.002047] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 648000
>[ 4295.002111] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 4295.002173] [drm:intel_dump_pipe_config [i915]] [CRTC:36:pipe A][modeset]
>[ 4295.002288] [drm:intel_dump_pipe_config [i915]] output_types: DP (0x80)
>[ 4295.002358] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 4295.002432] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5767168, gmch_n: 8388608, link_m: 240298, link_n: 262144, tu: 64
>[ 4295.002500] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[ 4295.002565] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 4295.002607] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[ 4295.002667] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 4295.002706] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[ 4295.002768] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[ 4295.002827] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1080, pixel rate 148500
>[ 4295.002887] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[ 4295.002944] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 4295.003002] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 4295.003065] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[ 4295.003123] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 4295.003181] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 1A] disabled, scaler_id = -1
>[ 4295.003240] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 2A] disabled, scaler_id = -1
>[ 4295.003297] [drm:intel_dump_pipe_config [i915]] [PLANE:33:cursor A] disabled, scaler_id = -1
>[ 4295.003361] [drm:intel_atomic_check [i915]] [CONNECTOR:67:DP-2] checking for sink bpp constrains
>[ 4295.003422] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 4295.003486] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 4295.003547] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 4295.003607] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 4295.003669] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 4295.003730] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe B][modeset]
>[ 4295.003789] [drm:intel_dump_pipe_config [i915]] output_types: DP (0x80)
>[ 4295.003848] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 4295.003908] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 4295.003966] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[ 4295.004022] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 4295.004054] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[ 4295.004112] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 4295.004143] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[ 4295.004203] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[ 4295.004262] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 4295.004319] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[ 4295.004378] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 4295.004434] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 4295.004496] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x3, cfgcr1: 0x0, cfgcr2: 0x0
>[ 4295.004552] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 4295.004612] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 1B] disabled, scaler_id = -1
>[ 4295.004669] [drm:intel_dump_pipe_config [i915]] [PLANE:40:plane 2B] disabled, scaler_id = -1
>[ 4295.004727] [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor B] disabled, scaler_id = -1
>[ 4295.004790] [drm:intel_atomic_check [i915]] [CONNECTOR:73:DP-3] checking for sink bpp constrains
>[ 4295.004851] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 4295.004912] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 297000KHz
>[ 4295.004974] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 4 clock 270000 bpp 24
>[ 4295.005032] [drm:intel_dp_compute_config [i915]] DP link bw required 891000 available 1080000
>[ 4295.005094] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 4295.005154] [drm:intel_dump_pipe_config [i915]] [CRTC:56:pipe C][modeset]
>[ 4295.005214] [drm:intel_dump_pipe_config [i915]] output_types: DP (0x80)
>[ 4295.005273] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 4295.005331] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6920601, gmch_n: 8388608, link_m: 576716, link_n: 524288, tu: 64
>[ 4295.005388] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 4295.005446] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 4295.005476] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"3840x2160" 30 297000 3840 4016 4104 4400 2160 2168 2178 2250 0x48 0x9
>[ 4295.005535] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 4295.005565] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"3840x2160" 30 297000 3840 4016 4104 4400 2160 2168 2178 2250 0x48 0x9
>[ 4295.005627] [drm:intel_dump_pipe_config [i915]] crtc timings: 297000 3840 4016 4104 4400 2160 2168 2178 2250, type: 0x48 flags: 0x9
>[ 4295.005685] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 3840x2160, pixel rate 297000
>[ 4295.005743] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[ 4295.005800] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 4295.005858] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 4295.005919] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x3, cfgcr1: 0x0, cfgcr2: 0x0
>[ 4295.005977] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 4295.006035] [drm:intel_dump_pipe_config [i915]] [PLANE:47:plane 1C] disabled, scaler_id = -1
>[ 4295.006093] [drm:intel_dump_pipe_config [i915]] [PLANE:50:plane 2C] disabled, scaler_id = -1
>[ 4295.006150] [drm:intel_dump_pipe_config [i915]] [PLANE:53:cursor C] disabled, scaler_id = -1
>[ 4295.006235] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 4295.006303] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[ 4295.006382] [drm:intel_find_shared_dpll [i915]] [CRTC:36:pipe A] allocated DPLL 1
>[ 4295.006451] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[ 4295.006525] [drm:intel_find_shared_dpll [i915]] [CRTC:46:pipe B] sharing existing DPLL 1 (crtc mask 0x00000001, active 2)
>[ 4295.006591] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[ 4295.006659] [drm:intel_find_shared_dpll [i915]] [CRTC:56:pipe C] allocated DPLL 2
>[ 4295.006724] [drm:intel_reference_shared_dpll [i915]] using DPLL 2 for pipe C
>[ 4295.006829] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 4295.006900] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[ 4295.006993] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 4295.035517] [drm:intel_power_well_disable [i915]] disabling DDI D IO power well
>[ 4295.035543] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 2, on? 1) for crtc 46
>[ 4295.035565] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[ 4295.035586] [drm:intel_disable_sagv [i915]] Disabling the SAGV
>[ 4295.035611] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DDI B]
>[ 4295.035632] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST A]
>[ 4295.035651] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST B]
>[ 4295.035670] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST C]
>[ 4295.035689] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI C]
>[ 4295.035708] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[ 4295.035726] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[ 4295.035744] [drm:intel_atomic_commit_tail [i915]] [ENCODER:70:DP-MST C]
>[ 4295.035762] [drm:intel_atomic_commit_tail [i915]] [ENCODER:72:DDI D]
>[ 4295.035781] [drm:intel_atomic_commit_tail [i915]] [ENCODER:74:DP-MST A]
>[ 4295.035799] [drm:intel_atomic_commit_tail [i915]] [ENCODER:75:DP-MST B]
>[ 4295.035817] [drm:intel_atomic_commit_tail [i915]] [ENCODER:76:DP-MST C]
>[ 4295.035836] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[ 4295.035855] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[ 4295.035874] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[ 4295.035919] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[ 4295.035943] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 2, on? 0) for crtc 46
>[ 4295.035964] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[ 4295.038054] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well
>[ 4295.039817] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 4295.039840] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 4295.039863] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 4295.039885] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 4295.042380] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 4295.042408] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 4295.044093] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 4295.046211] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:67:DP-2] Link Training Passed at Link Rate = 162000, Lane count = 4
>[ 4295.047032] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 4295.047070] [drm:intel_edp_drrs_enable [i915]] Panel doesn't support DRRS
>[ 4295.063931] [drm:intel_enable_shared_dpll [i915]] enable DPLL 2 (active 4, on? 0) for crtc 56
>[ 4295.063999] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 2
>[ 4295.066146] [drm:intel_power_well_enable [i915]] enabling DDI D IO power well
>[ 4295.066797] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4295.068059] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4295.069324] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4295.070574] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4295.071842] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4295.072718] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[ 4295.073701] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 4295.073759] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 4295.073815] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 4295.073870] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 4295.092657] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 4295.092721] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[ 4295.111428] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 4295.113534] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:73:DP-3] Link Training Passed at Link Rate = 270000, Lane count = 4
>[ 4295.114052] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 4295.114089] [drm:intel_edp_drrs_enable [i915]] Panel doesn't support DRRS
>[ 4295.114121] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:73:DP-3], [ENCODER:72:DDI D]
>[ 4295.114151] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 4295.114200] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 4295.114270] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 3, on? 1) for crtc 36
>[ 4295.114306] [drm:intel_power_well_enable [i915]] enabling DDI B IO power well
>[ 4295.115382] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 4295.115411] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 4295.115440] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 4295.115468] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 4295.118268] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 04000000
>[ 4295.118295] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[ 4295.118320] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 4295.120016] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 4295.120043] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 4295.122034] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[ 4295.122056] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[ 4295.122077] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[ 4295.122976] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 4295.125071] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:58:DP-1] Link Training Passed at Link Rate = 162000, Lane count = 4
>[ 4295.125468] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 4295.125494] [drm:intel_edp_drrs_enable [i915]] Panel doesn't support DRRS
>[ 4295.125517] [drm:intel_fbc_enable [i915]] reserved 16588800 bytes of contiguous stolen space for FBC, threshold: 1
>[ 4295.125538] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 4295.147504] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:58:DP-1]
>[ 4295.147527] [drm:intel_atomic_commit_tail [i915]] [CRTC:36:pipe A]
>[ 4295.147557] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[ 4295.147587] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:67:DP-2]
>[ 4295.147609] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe B]
>[ 4295.147636] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[ 4295.147664] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:73:DP-3]
>[ 4295.147684] [drm:intel_atomic_commit_tail [i915]] [CRTC:56:pipe C]
>[ 4295.147710] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[ 4305.579603] [IGT] kms_plane_multiple: executing
>[ 4305.623763] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:58:DP-1]
>[ 4305.623842] [drm:intel_dp_detect [i915]] [CONNECTOR:58:DP-1]
>[ 4305.624384] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 01 02 00 00 00 00 00 00
>[ 4305.624748] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>[ 4305.624805] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[ 4305.624860] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[ 4305.625263] [drm:drm_dp_read_desc [drm_kms_helper]] DP sink: OUI 4c-e0-00 dev-ID  HW-rev 0.0 SW-rev 0.0 quirks 0x0000
>[ 4305.625320] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[ 4305.631051] [drm:drm_add_edid_modes [drm]] ELD: no CEA Extension found
>[ 4305.631112] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:58:DP-1] probed modes :
>[ 4305.631118] [drm:drm_mode_debug_printmodeline [drm]] Modeline 80:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[ 4305.631123] [drm:drm_mode_debug_printmodeline [drm]] Modeline 85:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[ 4305.631128] [drm:drm_mode_debug_printmodeline [drm]] Modeline 86:"1680x1050" 60 146250 1680 1784 1960 2240 1050 1053 1059 1089 0x40 0x6
>[ 4305.631132] [drm:drm_mode_debug_printmodeline [drm]] Modeline 83:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[ 4305.631137] [drm:drm_mode_debug_printmodeline [drm]] Modeline 84:"1440x900" 60 106500 1440 1520 1672 1904 900 903 909 934 0x40 0x6
>[ 4305.631141] [drm:drm_mode_debug_printmodeline [drm]] Modeline 82:"1280x960" 60 108000 1280 1376 1488 1800 960 961 964 1000 0x40 0x5
>[ 4305.631145] [drm:drm_mode_debug_printmodeline [drm]] Modeline 81:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[ 4305.631150] [drm:drm_mode_debug_printmodeline [drm]] Modeline 90:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[ 4305.631154] [drm:drm_mode_debug_printmodeline [drm]] Modeline 87:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[ 4305.631158] [drm:drm_mode_debug_printmodeline [drm]] Modeline 88:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[ 4305.631162] [drm:drm_mode_debug_printmodeline [drm]] Modeline 89:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[ 4305.631186] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:64:HDMI-A-1]
>[ 4305.631199] [drm:intel_hdmi_detect [i915]] [CONNECTOR:64:HDMI-A-1]
>[ 4305.633624] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[ 4305.633639] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[ 4305.633980] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0050 w(1)
>[ 4305.633987] [drm:drm_do_probe_ddc_edid [drm]] drm: skipping non-existent adapter i915 gmbus dpb
>[ 4305.634392] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[ 4305.634409] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK on first message, retry
>[ 4305.634852] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpb] NAK for addr: 0040 w(1)
>[ 4305.634855] [drm:drm_dp_dual_mode_detect [drm_kms_helper]] DP dual mode HDMI ID:  (err -6)
>[ 4305.634858] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:64:HDMI-A-1] disconnected
>[ 4305.634901] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:67:DP-2]
>[ 4305.634916] [drm:intel_dp_detect [i915]] [CONNECTOR:67:DP-2]
>[ 4305.635818] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 80 02 00 00 00 00 00 00
>[ 4305.636568] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>[ 4305.636595] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[ 4305.636608] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[ 4305.637434] [drm:drm_dp_read_desc [drm_kms_helper]] DP sink: OUI 4c-e0-00 dev-ID  HW-rev 0.0 SW-rev 0.0 quirks 0x0000
>[ 4305.637448] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[ 4305.643864] [drm:drm_add_edid_modes [drm]] ELD: no CEA Extension found
>[ 4305.643904] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:67:DP-2] probed modes :
>[ 4305.643911] [drm:drm_mode_debug_printmodeline [drm]] Modeline 92:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[ 4305.643917] [drm:drm_mode_debug_printmodeline [drm]] Modeline 97:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0xa
>[ 4305.643923] [drm:drm_mode_debug_printmodeline [drm]] Modeline 95:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[ 4305.643928] [drm:drm_mode_debug_printmodeline [drm]] Modeline 96:"1680x1050" 60 146250 1680 1784 1960 2240 1050 1053 1059 1089 0x40 0x6
>[ 4305.643933] [drm:drm_mode_debug_printmodeline [drm]] Modeline 94:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[ 4305.643938] [drm:drm_mode_debug_printmodeline [drm]] Modeline 93:"1280x960" 60 108000 1280 1376 1488 1800 960 961 964 1000 0x40 0x5
>[ 4305.643944] [drm:drm_mode_debug_printmodeline [drm]] Modeline 101:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[ 4305.643949] [drm:drm_mode_debug_printmodeline [drm]] Modeline 98:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[ 4305.643954] [drm:drm_mode_debug_printmodeline [drm]] Modeline 99:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[ 4305.643959] [drm:drm_mode_debug_printmodeline [drm]] Modeline 100:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[ 4305.643981] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:71:HDMI-A-2]
>[ 4305.643998] [drm:intel_hdmi_detect [i915]] [CONNECTOR:71:HDMI-A-2]
>[ 4305.644384] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[ 4305.644398] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[ 4305.646491] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[ 4305.646500] [drm:drm_do_probe_ddc_edid [drm]] drm: skipping non-existent adapter i915 gmbus dpc
>[ 4305.646884] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[ 4305.646900] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[ 4305.649288] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[ 4305.649293] [drm:drm_dp_dual_mode_detect [drm_kms_helper]] DP dual mode HDMI ID:  (err -6)
>[ 4305.649297] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:71:HDMI-A-2] disconnected
>[ 4305.649323] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:73:DP-3]
>[ 4305.649344] [drm:intel_dp_detect [i915]] [CONNECTOR:73:DP-3]
>[ 4305.649670] [drm:lspcon_wake_native_aux_ch [i915]] Native AUX CH up, DPCD version: 1.2
>[ 4305.649732] [drm:lspcon_resume [i915]] LSPCON recovering in PCON mode after 0 ms
>[ 4305.650146] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4305.651358] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4305.652562] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4305.653778] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4305.654932] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4305.655743] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[ 4305.656144] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 00 01 00 00 04 00 0f 00 04
>[ 4305.656826] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>[ 4305.656841] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000
>[ 4305.656855] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000
>[ 4305.657219] [drm:drm_dp_read_desc [drm_kms_helper]] DP branch: OUI 00-60-ad dev-ID MC2800 HW-rev 2.2 SW-rev 1.66 quirks 0x0000
>[ 4305.657507] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[ 4305.658236] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4305.659457] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4305.660683] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4305.661898] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4305.663110] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4305.664316] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4305.665510] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4305.666739] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4305.667953] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4305.669299] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4305.670619] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4305.671972] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4305.673319] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4305.674638] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4305.675985] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4305.677337] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4305.678657] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4305.679874] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4305.681100] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4305.682330] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4305.683512] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4305.684860] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4305.686207] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4305.687555] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4305.688904] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4305.690252] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4305.691605] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4305.692953] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4305.694297] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4305.695066] [drm:drm_detect_monitor_audio [drm]] Monitor has basic audio support
>[ 4305.695350] [drm:drm_add_edid_modes [drm]] ELD monitor ASUS PB287Q
>[ 4305.695357] [drm:drm_add_edid_modes [drm]] HDMI: latency present 0 0, video latency 0 1, audio latency 96 2
>[ 4305.695362] [drm:drm_add_edid_modes [drm]] ELD size 36, SAD count 1
>[ 4305.695368] [drm:drm_add_edid_modes [drm]] HDMI: DVI dual 0, max TMDS clock 300000 kHz
>[ 4305.695586] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:73:DP-3] probed modes :
>[ 4305.695593] [drm:drm_mode_debug_printmodeline [drm]] Modeline 105:"3840x2160" 30 297000 3840 4016 4104 4400 2160 2168 2178 2250 0x48 0x9
>[ 4305.695599] [drm:drm_mode_debug_printmodeline [drm]] Modeline 149:"3840x2160" 30 297000 3840 4016 4104 4400 2160 2168 2178 2250 0x40 0x5
>[ 4305.695605] [drm:drm_mode_debug_printmodeline [drm]] Modeline 165:"3840x2160" 30 296703 3840 4016 4104 4400 2160 2168 2178 2250 0x40 0x5
>[ 4305.695611] [drm:drm_mode_debug_printmodeline [drm]] Modeline 150:"3840x2160" 25 297000 3840 4896 4984 5280 2160 2168 2178 2250 0x40 0x5
>[ 4305.695616] [drm:drm_mode_debug_printmodeline [drm]] Modeline 151:"3840x2160" 24 297000 3840 5116 5204 5500 2160 2168 2178 2250 0x40 0x5
>[ 4305.695621] [drm:drm_mode_debug_printmodeline [drm]] Modeline 166:"3840x2160" 24 296703 3840 5116 5204 5500 2160 2168 2178 2250 0x40 0x5
>[ 4305.695626] [drm:drm_mode_debug_printmodeline [drm]] Modeline 108:"2560x1600" 60 268500 2560 2608 2640 2720 1600 1603 1609 1646 0x40 0x9
>[ 4305.695631] [drm:drm_mode_debug_printmodeline [drm]] Modeline 107:"2560x1440" 60 241500 2560 2608 2640 2720 1440 1443 1448 1481 0x40 0x5
>[ 4305.695636] [drm:drm_mode_debug_printmodeline [drm]] Modeline 106:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[ 4305.695641] [drm:drm_mode_debug_printmodeline [drm]] Modeline 152:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[ 4305.695646] [drm:drm_mode_debug_printmodeline [drm]] Modeline 140:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[ 4305.695651] [drm:drm_mode_debug_printmodeline [drm]] Modeline 159:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[ 4305.695656] [drm:drm_mode_debug_printmodeline [drm]] Modeline 145:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[ 4305.695661] [drm:drm_mode_debug_printmodeline [drm]] Modeline 139:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[ 4305.695665] [drm:drm_mode_debug_printmodeline [drm]] Modeline 148:"1920x1080" 30 74250 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[ 4305.695670] [drm:drm_mode_debug_printmodeline [drm]] Modeline 164:"1920x1080" 30 74176 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[ 4305.695675] [drm:drm_mode_debug_printmodeline [drm]] Modeline 147:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[ 4305.695680] [drm:drm_mode_debug_printmodeline [drm]] Modeline 163:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[ 4305.695685] [drm:drm_mode_debug_printmodeline [drm]] Modeline 114:"1680x1050" 60 119000 1680 1728 1760 1840 1050 1053 1059 1080 0x40 0x9
>[ 4305.695689] [drm:drm_mode_debug_printmodeline [drm]] Modeline 124:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[ 4305.695694] [drm:drm_mode_debug_printmodeline [drm]] Modeline 112:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[ 4305.695699] [drm:drm_mode_debug_printmodeline [drm]] Modeline 113:"1440x900" 60 88750 1440 1488 1520 1600 900 903 909 926 0x40 0x9
>[ 4305.695704] [drm:drm_mode_debug_printmodeline [drm]] Modeline 111:"1280x960" 60 108000 1280 1376 1488 1800 960 961 964 1000 0x40 0x5
>[ 4305.695709] [drm:drm_mode_debug_printmodeline [drm]] Modeline 115:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[ 4305.695713] [drm:drm_mode_debug_printmodeline [drm]] Modeline 116:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[ 4305.695718] [drm:drm_mode_debug_printmodeline [drm]] Modeline 153:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[ 4305.695723] [drm:drm_mode_debug_printmodeline [drm]] Modeline 109:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[ 4305.695728] [drm:drm_mode_debug_printmodeline [drm]] Modeline 143:"1440x576" 50 54000 1440 1464 1592 1728 576 581 586 625 0x40 0xa
>[ 4305.695732] [drm:drm_mode_debug_printmodeline [drm]] Modeline 125:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[ 4305.695737] [drm:drm_mode_debug_printmodeline [drm]] Modeline 126:"1024x768" 70 75000 1024 1048 1184 1328 768 771 777 806 0x40 0xa
>[ 4305.695742] [drm:drm_mode_debug_printmodeline [drm]] Modeline 127:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[ 4305.695747] [drm:drm_mode_debug_printmodeline [drm]] Modeline 160:"1440x480" 60 54054 1440 1472 1596 1716 480 489 495 525 0x40 0xa
>[ 4305.695751] [drm:drm_mode_debug_printmodeline [drm]] Modeline 141:"1440x480" 60 54000 1440 1472 1596 1716 480 489 495 525 0x40 0xa
>[ 4305.695756] [drm:drm_mode_debug_printmodeline [drm]] Modeline 128:"832x624" 75 57284 832 864 928 1152 624 625 628 667 0x40 0xa
>[ 4305.695761] [drm:drm_mode_debug_printmodeline [drm]] Modeline 129:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[ 4305.695766] [drm:drm_mode_debug_printmodeline [drm]] Modeline 130:"800x600" 72 50000 800 856 976 1040 600 637 643 666 0x40 0x5
>[ 4305.695770] [drm:drm_mode_debug_printmodeline [drm]] Modeline 117:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[ 4305.695775] [drm:drm_mode_debug_printmodeline [drm]] Modeline 118:"800x600" 56 36000 800 824 896 1024 600 601 603 625 0x40 0x5
>[ 4305.695780] [drm:drm_mode_debug_printmodeline [drm]] Modeline 110:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[ 4305.695784] [drm:drm_mode_debug_printmodeline [drm]] Modeline 156:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[ 4305.695789] [drm:drm_mode_debug_printmodeline [drm]] Modeline 132:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[ 4305.695794] [drm:drm_mode_debug_printmodeline [drm]] Modeline 119:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[ 4305.695799] [drm:drm_mode_debug_printmodeline [drm]] Modeline 120:"640x480" 73 31500 640 664 704 832 480 489 492 520 0x40 0xa
>[ 4305.695803] [drm:drm_mode_debug_printmodeline [drm]] Modeline 121:"640x480" 67 30240 640 704 768 864 480 483 486 525 0x40 0xa
>[ 4305.695808] [drm:drm_mode_debug_printmodeline [drm]] Modeline 154:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[ 4305.695813] [drm:drm_mode_debug_printmodeline [drm]] Modeline 122:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[ 4305.695817] [drm:drm_mode_debug_printmodeline [drm]] Modeline 123:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[ 4305.695867] [IGT] kms_plane_multiple: starting subtest legacy-pipe-B-tiling-none
>[ 4305.695931] [drm:drm_mode_addfb2 [drm]] [FB:136]
>[ 4305.697712] [drm:drm_mode_setcrtc [drm]] [CRTC:36:pipe A]
>[ 4305.697740] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 4305.697756] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[ 4305.697794] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 4305.710336] [drm:intel_power_well_disable [i915]] disabling DDI B IO power well
>[ 4305.710355] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 4305.710372] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 3, on? 1) for crtc 36
>[ 4305.710397] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DDI B]
>[ 4305.710413] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST A]
>[ 4305.710428] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST B]
>[ 4305.710443] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST C]
>[ 4305.710458] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI C]
>[ 4305.710472] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[ 4305.710487] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[ 4305.710501] [drm:intel_atomic_commit_tail [i915]] [ENCODER:70:DP-MST C]
>[ 4305.710514] [drm:intel_atomic_commit_tail [i915]] [ENCODER:72:DDI D]
>[ 4305.710528] [drm:intel_atomic_commit_tail [i915]] [ENCODER:74:DP-MST A]
>[ 4305.710542] [drm:intel_atomic_commit_tail [i915]] [ENCODER:75:DP-MST B]
>[ 4305.710556] [drm:intel_atomic_commit_tail [i915]] [ENCODER:76:DP-MST C]
>[ 4305.710570] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:58:DP-1]
>[ 4305.710585] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[ 4305.710600] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[ 4305.710615] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[ 4305.710629] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[ 4305.747546] [drm:intel_atomic_commit_tail [i915]] [CRTC:36:pipe A]
>[ 4305.747661] [drm:drm_mode_setcrtc [drm]] [CRTC:46:pipe B]
>[ 4305.747679] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:58:DP-1]
>[ 4305.747734] [drm:intel_atomic_check [i915]] [CONNECTOR:58:DP-1] checking for sink bpp constrains
>[ 4305.747772] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 4305.747810] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 148500KHz
>[ 4305.747846] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 4305.747879] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 648000
>[ 4305.747916] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 4305.747951] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe B][modeset]
>[ 4305.747986] [drm:intel_dump_pipe_config [i915]] output_types: DP (0x80)
>[ 4305.748020] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 4305.748053] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5767168, gmch_n: 8388608, link_m: 240298, link_n: 262144, tu: 64
>[ 4305.748085] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[ 4305.748117] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 4305.748134] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[ 4305.748167] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 4305.748183] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[ 4305.748217] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[ 4305.748249] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1080, pixel rate 148500
>[ 4305.748281] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[ 4305.748312] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 4305.748343] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 4305.748378] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[ 4305.748409] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 4305.748443] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 1B] FB:133, fb = 3840x2160 format = XR24 little-endian (0x34325258)
>[ 4305.748475] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1200 dst 0x0+1920+1200
>[ 4305.748506] [drm:intel_dump_pipe_config [i915]] [PLANE:40:plane 2B] disabled, scaler_id = -1
>[ 4305.748537] [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor B] disabled, scaler_id = -1
>[ 4305.748573] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 4305.748606] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[ 4305.748645] [drm:intel_find_shared_dpll [i915]] [CRTC:46:pipe B] allocated DPLL 1
>[ 4305.748678] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[ 4305.749402] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 4305.758139] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well
>[ 4305.758204] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 2, on? 1) for crtc 46
>[ 4305.758289] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[ 4305.758361] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DDI B]
>[ 4305.758418] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST A]
>[ 4305.758471] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST B]
>[ 4305.758523] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST C]
>[ 4305.758575] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI C]
>[ 4305.758627] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[ 4305.758678] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[ 4305.758727] [drm:intel_atomic_commit_tail [i915]] [ENCODER:70:DP-MST C]
>[ 4305.758778] [drm:intel_atomic_commit_tail [i915]] [ENCODER:72:DDI D]
>[ 4305.758827] [drm:intel_atomic_commit_tail [i915]] [ENCODER:74:DP-MST A]
>[ 4305.758877] [drm:intel_atomic_commit_tail [i915]] [ENCODER:75:DP-MST B]
>[ 4305.758926] [drm:intel_atomic_commit_tail [i915]] [ENCODER:76:DP-MST C]
>[ 4305.758980] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:67:DP-2]
>[ 4305.759033] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[ 4305.759087] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[ 4305.759140] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[ 4305.759192] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[ 4305.759248] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 2, on? 0) for crtc 46
>[ 4305.759300] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[ 4305.761436] [drm:intel_power_well_enable [i915]] enabling DDI B IO power well
>[ 4305.762591] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 4305.762652] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 4305.762709] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 4305.762765] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 4305.764550] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 04000000
>[ 4305.764612] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[ 4305.764669] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 4305.766438] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 4305.766495] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 4305.768540] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[ 4305.768592] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[ 4305.768642] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[ 4305.769603] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 4305.771750] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:58:DP-1] Link Training Passed at Link Rate = 162000, Lane count = 4
>[ 4305.772409] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 4305.772479] [drm:intel_edp_drrs_enable [i915]] Panel doesn't support DRRS
>[ 4305.789276] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:58:DP-1]
>[ 4305.789352] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe B]
>[ 4305.789439] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[ 4305.789572] [drm:drm_mode_setcrtc [drm]] [CRTC:56:pipe C]
>[ 4305.789655] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 4305.789717] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[ 4305.789817] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe C
>[ 4305.789882] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[ 4305.789965] [drm:intel_disable_pipe [i915]] disabling pipe C
>[ 4305.814987] [drm:intel_power_well_disable [i915]] disabling DDI D IO power well
>[ 4305.815058] [drm:intel_disable_shared_dpll [i915]] disable DPLL 2 (active 4, on? 1) for crtc 56
>[ 4305.815123] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 2
>[ 4305.815202] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DDI B]
>[ 4305.815261] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST A]
>[ 4305.815318] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST B]
>[ 4305.815373] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST C]
>[ 4305.815427] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI C]
>[ 4305.815481] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[ 4305.815535] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[ 4305.815588] [drm:intel_atomic_commit_tail [i915]] [ENCODER:70:DP-MST C]
>[ 4305.815641] [drm:intel_atomic_commit_tail [i915]] [ENCODER:72:DDI D]
>[ 4305.815695] [drm:intel_atomic_commit_tail [i915]] [ENCODER:74:DP-MST A]
>[ 4305.815748] [drm:intel_atomic_commit_tail [i915]] [ENCODER:75:DP-MST B]
>[ 4305.815801] [drm:intel_atomic_commit_tail [i915]] [ENCODER:76:DP-MST C]
>[ 4305.815855] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:73:DP-3]
>[ 4305.815911] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[ 4305.815968] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[ 4305.816023] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[ 4305.816077] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[ 4305.822617] [drm:intel_atomic_commit_tail [i915]] [CRTC:56:pipe C]
>[ 4305.822678] [drm:intel_enable_sagv [i915]] Enabling the SAGV
>[ 4305.889461] [drm:drm_mode_addfb2 [drm]] [FB:103]
>[ 4305.889959] [drm:drm_mode_addfb2 [drm]] [FB:134]
>[ 4305.890135] [drm:drm_mode_addfb2 [drm]] [FB:135]
>[ 4305.895447] [drm:drm_mode_setcrtc [drm]] [CRTC:46:pipe B]
>[ 4305.895481] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:58:DP-1]
>[ 4305.939613] [drm:drm_mode_addfb2 [drm]] [FB:138]
>[ 4305.945657] [drm:drm_mode_setcrtc [drm]] [CRTC:46:pipe B]
>[ 4305.945690] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:67:DP-2]
>[ 4305.945793] [drm:intel_atomic_check [i915]] [CONNECTOR:67:DP-2] checking for sink bpp constrains
>[ 4305.945860] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 4305.945928] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 4305.945991] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 4305.946051] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 4305.946116] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 4305.946178] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe B][modeset]
>[ 4305.946263] [drm:intel_dump_pipe_config [i915]] output_types: DP (0x80)
>[ 4305.946332] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 4305.946402] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 4305.946467] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[ 4305.946532] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 4305.946570] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[ 4305.946635] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 4305.946666] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[ 4305.946729] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[ 4305.946788] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 4305.946849] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[ 4305.946907] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 4305.946965] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 4305.947029] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[ 4305.947087] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 4305.947150] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 1B] FB:135, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[ 4305.947209] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[ 4305.947270] [drm:intel_dump_pipe_config [i915]] [PLANE:40:plane 2B] FB:103, fb = 256x256 format = XR24 little-endian (0x34325258)
>[ 4305.947327] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+256+256 dst 313x608+256+256
>[ 4305.947388] [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor B] FB:137, fb = 128x128 format = AR24 little-endian (0x34325241)
>[ 4305.947445] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+128+128 dst 1721x248+128+128
>[ 4305.947511] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 4305.947572] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[ 4305.947645] [drm:intel_find_shared_dpll [i915]] [CRTC:46:pipe B] allocated DPLL 1
>[ 4305.947706] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[ 4305.948962] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 4305.956751] [drm:intel_power_well_disable [i915]] disabling DDI B IO power well
>[ 4305.956824] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 2, on? 1) for crtc 46
>[ 4305.956889] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[ 4305.956957] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DDI B]
>[ 4305.957018] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST A]
>[ 4305.957075] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST B]
>[ 4305.957130] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST C]
>[ 4305.957184] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI C]
>[ 4305.957237] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[ 4305.957291] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[ 4305.957343] [drm:intel_atomic_commit_tail [i915]] [ENCODER:70:DP-MST C]
>[ 4305.957395] [drm:intel_atomic_commit_tail [i915]] [ENCODER:72:DDI D]
>[ 4305.957447] [drm:intel_atomic_commit_tail [i915]] [ENCODER:74:DP-MST A]
>[ 4305.957498] [drm:intel_atomic_commit_tail [i915]] [ENCODER:75:DP-MST B]
>[ 4305.957550] [drm:intel_atomic_commit_tail [i915]] [ENCODER:76:DP-MST C]
>[ 4305.957604] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:58:DP-1]
>[ 4305.957659] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[ 4305.957715] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[ 4305.957770] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[ 4305.957823] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[ 4305.957884] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 2, on? 0) for crtc 46
>[ 4305.957938] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[ 4305.960067] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well
>[ 4305.961906] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 4305.961967] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 4305.962023] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 4305.962079] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 4305.964667] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 4305.964732] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 4305.966486] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 4305.968631] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:67:DP-2] Link Training Passed at Link Rate = 162000, Lane count = 4
>[ 4305.969595] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 4305.969664] [drm:intel_edp_drrs_enable [i915]] Panel doesn't support DRRS
>[ 4305.986482] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:67:DP-2]
>[ 4305.986559] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe B]
>[ 4305.986646] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[ 4306.070022] [drm:drm_mode_addfb2 [drm]] [FB:137]
>[ 4306.070556] [drm:drm_mode_addfb2 [drm]] [FB:142]
>[ 4306.070737] [drm:drm_mode_addfb2 [drm]] [FB:144]
>[ 4306.076759] [drm:drm_mode_setcrtc [drm]] [CRTC:46:pipe B]
>[ 4306.076791] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:67:DP-2]
>[ 4306.120369] [drm:drm_mode_addfb2 [drm]] [FB:155]
>[ 4306.140596] [drm:drm_mode_setcrtc [drm]] [CRTC:46:pipe B]
>[ 4306.140631] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:73:DP-3]
>[ 4306.140738] [drm:intel_atomic_check [i915]] [CONNECTOR:73:DP-3] checking for sink bpp constrains
>[ 4306.140805] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 4306.140873] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 297000KHz
>[ 4306.140938] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 4 clock 270000 bpp 24
>[ 4306.140998] [drm:intel_dp_compute_config [i915]] DP link bw required 891000 available 1080000
>[ 4306.141062] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 4306.141125] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe B][modeset]
>[ 4306.141185] [drm:intel_dump_pipe_config [i915]] output_types: DP (0x80)
>[ 4306.141245] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 4306.141305] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6920601, gmch_n: 8388608, link_m: 576716, link_n: 524288, tu: 64
>[ 4306.141362] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 4306.141418] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 4306.141448] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"3840x2160" 30 297000 3840 4016 4104 4400 2160 2168 2178 2250 0x48 0x9
>[ 4306.141506] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 4306.141534] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"3840x2160" 30 297000 3840 4016 4104 4400 2160 2168 2178 2250 0x48 0x9
>[ 4306.141595] [drm:intel_dump_pipe_config [i915]] crtc timings: 297000 3840 4016 4104 4400 2160 2168 2178 2250, type: 0x48 flags: 0x9
>[ 4306.141653] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 3840x2160, pixel rate 297000
>[ 4306.141710] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[ 4306.141768] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 4306.141823] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 4306.141885] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[ 4306.141940] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 4306.142000] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 1B] FB:144, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[ 4306.142056] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1200 dst 0x0+1920+1200
>[ 4306.142114] [drm:intel_dump_pipe_config [i915]] [PLANE:40:plane 2B] FB:137, fb = 256x256 format = XR24 little-endian (0x34325258)
>[ 4306.142171] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+256+256 dst 883x916+256+256
>[ 4306.142255] [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor B] FB:146, fb = 128x128 format = AR24 little-endian (0x34325241)
>[ 4306.142321] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+128+128 dst 1585x611+128+128
>[ 4306.142397] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 4306.142462] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[ 4306.142543] [drm:intel_find_shared_dpll [i915]] [CRTC:46:pipe B] allocated DPLL 1
>[ 4306.142614] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[ 4306.146581] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 4306.154906] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well
>[ 4306.154979] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 2, on? 1) for crtc 46
>[ 4306.155043] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[ 4306.155111] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DDI B]
>[ 4306.155171] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST A]
>[ 4306.155228] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST B]
>[ 4306.155283] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST C]
>[ 4306.155337] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI C]
>[ 4306.155392] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[ 4306.155445] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[ 4306.155498] [drm:intel_atomic_commit_tail [i915]] [ENCODER:70:DP-MST C]
>[ 4306.155550] [drm:intel_atomic_commit_tail [i915]] [ENCODER:72:DDI D]
>[ 4306.155603] [drm:intel_atomic_commit_tail [i915]] [ENCODER:74:DP-MST A]
>[ 4306.155656] [drm:intel_atomic_commit_tail [i915]] [ENCODER:75:DP-MST B]
>[ 4306.155708] [drm:intel_atomic_commit_tail [i915]] [ENCODER:76:DP-MST C]
>[ 4306.155763] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:67:DP-2]
>[ 4306.155821] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[ 4306.155877] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[ 4306.155932] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[ 4306.155986] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[ 4306.156046] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 2, on? 0) for crtc 46
>[ 4306.156101] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[ 4306.158264] [drm:intel_power_well_enable [i915]] enabling DDI D IO power well
>[ 4306.158891] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4306.160152] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4306.161412] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4306.162691] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4306.163951] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4306.164827] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[ 4306.165810] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 4306.165869] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 4306.165924] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 4306.165982] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 4306.184727] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 4306.184772] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[ 4306.203445] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 4306.205535] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:73:DP-3] Link Training Passed at Link Rate = 270000, Lane count = 4
>[ 4306.205964] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 4306.205984] [drm:intel_edp_drrs_enable [i915]] Panel doesn't support DRRS
>[ 4306.206001] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:73:DP-3], [ENCODER:72:DDI D]
>[ 4306.206017] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 4306.206034] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 4306.239449] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:73:DP-3]
>[ 4306.239471] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe B]
>[ 4306.239499] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[ 4306.406376] [drm:drm_mode_addfb2 [drm]] [FB:146]
>[ 4306.406874] [drm:drm_mode_addfb2 [drm]] [FB:157]
>[ 4306.407095] [drm:drm_mode_addfb2 [drm]] [FB:158]
>[ 4306.426968] [drm:drm_mode_setcrtc [drm]] [CRTC:46:pipe B]
>[ 4306.427004] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:73:DP-3]
>[ 4306.506567] [drm:drm_mode_addfb2 [drm]] [FB:162]
>[ 4306.511973] [drm:drm_mode_setcrtc [drm]] [CRTC:46:pipe B]
>[ 4306.512007] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:58:DP-1]
>[ 4306.512113] [drm:intel_atomic_check [i915]] [CONNECTOR:58:DP-1] checking for sink bpp constrains
>[ 4306.512180] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 4306.512249] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 148500KHz
>[ 4306.512313] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 4306.512374] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 648000
>[ 4306.512438] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 4306.512501] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe B][modeset]
>[ 4306.512562] [drm:intel_dump_pipe_config [i915]] output_types: DP (0x80)
>[ 4306.512621] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 4306.512680] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5767168, gmch_n: 8388608, link_m: 240298, link_n: 262144, tu: 64
>[ 4306.512737] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[ 4306.512792] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 4306.512822] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[ 4306.512878] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 4306.512907] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[ 4306.512966] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[ 4306.513024] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1080, pixel rate 148500
>[ 4306.513080] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[ 4306.513135] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 4306.513191] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 4306.513251] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x3, cfgcr1: 0x0, cfgcr2: 0x0
>[ 4306.513306] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 4306.513365] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 1B] FB:158, fb = 3840x2160 format = XR24 little-endian (0x34325258)
>[ 4306.513422] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+3840+2160 dst 0x0+3840+2160
>[ 4306.513479] [drm:intel_dump_pipe_config [i915]] [PLANE:40:plane 2B] FB:146, fb = 256x256 format = XR24 little-endian (0x34325258)
>[ 4306.513535] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+256+256 dst 2079x1738+256+256
>[ 4306.513591] [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor B] FB:161, fb = 128x128 format = AR24 little-endian (0x34325241)
>[ 4306.513646] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+128+128 dst 1839x831+128+128
>[ 4306.513709] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 4306.513767] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[ 4306.513839] [drm:intel_find_shared_dpll [i915]] [CRTC:46:pipe B] allocated DPLL 1
>[ 4306.513898] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[ 4306.515053] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 4306.515136] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[ 4306.515245] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 4306.540343] [drm:intel_power_well_disable [i915]] disabling DDI D IO power well
>[ 4306.540415] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 2, on? 1) for crtc 46
>[ 4306.540478] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[ 4306.540546] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DDI B]
>[ 4306.540604] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST A]
>[ 4306.540661] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST B]
>[ 4306.540717] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST C]
>[ 4306.540772] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI C]
>[ 4306.540826] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[ 4306.540880] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[ 4306.540934] [drm:intel_atomic_commit_tail [i915]] [ENCODER:70:DP-MST C]
>[ 4306.540987] [drm:intel_atomic_commit_tail [i915]] [ENCODER:72:DDI D]
>[ 4306.541041] [drm:intel_atomic_commit_tail [i915]] [ENCODER:74:DP-MST A]
>[ 4306.541094] [drm:intel_atomic_commit_tail [i915]] [ENCODER:75:DP-MST B]
>[ 4306.541146] [drm:intel_atomic_commit_tail [i915]] [ENCODER:76:DP-MST C]
>[ 4306.541201] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:73:DP-3]
>[ 4306.541258] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[ 4306.541314] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[ 4306.541369] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[ 4306.541423] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[ 4306.541484] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 2, on? 0) for crtc 46
>[ 4306.541540] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[ 4306.543686] [drm:intel_power_well_enable [i915]] enabling DDI B IO power well
>[ 4306.544834] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 4306.544896] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 4306.544953] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 4306.545009] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 4306.546802] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 04000000
>[ 4306.546865] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[ 4306.546922] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 4306.548704] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 4306.548767] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 4306.550788] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[ 4306.550845] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[ 4306.550899] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[ 4306.551864] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 4306.553967] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:58:DP-1] Link Training Passed at Link Rate = 162000, Lane count = 4
>[ 4306.554631] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 4306.554693] [drm:intel_edp_drrs_enable [i915]] Panel doesn't support DRRS
>[ 4306.571489] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:58:DP-1]
>[ 4306.571566] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe B]
>[ 4306.571652] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[ 4306.654975] [drm:drm_mode_addfb2 [drm]] [FB:161]
>[ 4306.655510] [drm:drm_mode_addfb2 [drm]] [FB:167]
>[ 4306.655692] [drm:drm_mode_addfb2 [drm]] [FB:168]
>[ 4306.660988] [drm:drm_mode_setcrtc [drm]] [CRTC:46:pipe B]
>[ 4306.661021] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:58:DP-1]
>[ 4306.705233] [drm:drm_mode_addfb2 [drm]] [FB:170]
>[ 4306.711700] [drm:drm_mode_setcrtc [drm]] [CRTC:46:pipe B]
>[ 4306.711739] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:67:DP-2]
>[ 4306.711856] [drm:intel_atomic_check [i915]] [CONNECTOR:67:DP-2] checking for sink bpp constrains
>[ 4306.711931] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 4306.712006] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 4306.712076] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 4306.712143] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 4306.712214] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 4306.712286] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe B][modeset]
>[ 4306.712354] [drm:intel_dump_pipe_config [i915]] output_types: DP (0x80)
>[ 4306.712421] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 4306.712489] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 4306.712553] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[ 4306.712616] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 4306.712648] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[ 4306.712714] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 4306.712745] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[ 4306.712814] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[ 4306.712878] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 4306.712957] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[ 4306.713014] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 4306.713070] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 4306.713131] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[ 4306.713187] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 4306.713247] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 1B] FB:168, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[ 4306.713304] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[ 4306.713362] [drm:intel_dump_pipe_config [i915]] [PLANE:40:plane 2B] FB:161, fb = 256x256 format = XR24 little-endian (0x34325258)
>[ 4306.713418] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+256+256 dst 75x647+256+256
>[ 4306.713475] [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor B] FB:169, fb = 128x128 format = AR24 little-endian (0x34325241)
>[ 4306.713530] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+128+128 dst 1791x431+128+128
>[ 4306.713594] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 4306.713653] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[ 4306.713724] [drm:intel_find_shared_dpll [i915]] [CRTC:46:pipe B] allocated DPLL 1
>[ 4306.713784] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[ 4306.715104] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 4306.722668] [drm:intel_power_well_disable [i915]] disabling DDI B IO power well
>[ 4306.722741] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 2, on? 1) for crtc 46
>[ 4306.722804] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[ 4306.722872] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DDI B]
>[ 4306.722932] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST A]
>[ 4306.722989] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST B]
>[ 4306.723044] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST C]
>[ 4306.723098] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI C]
>[ 4306.723151] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[ 4306.723204] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[ 4306.723256] [drm:intel_atomic_commit_tail [i915]] [ENCODER:70:DP-MST C]
>[ 4306.723309] [drm:intel_atomic_commit_tail [i915]] [ENCODER:72:DDI D]
>[ 4306.723361] [drm:intel_atomic_commit_tail [i915]] [ENCODER:74:DP-MST A]
>[ 4306.723413] [drm:intel_atomic_commit_tail [i915]] [ENCODER:75:DP-MST B]
>[ 4306.723465] [drm:intel_atomic_commit_tail [i915]] [ENCODER:76:DP-MST C]
>[ 4306.723519] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:58:DP-1]
>[ 4306.723576] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[ 4306.723631] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[ 4306.723686] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[ 4306.723739] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[ 4306.723798] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 2, on? 0) for crtc 46
>[ 4306.723854] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[ 4306.726007] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well
>[ 4306.727851] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 4306.727913] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 4306.727970] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 4306.728025] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 4306.730605] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 4306.730668] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 4306.732417] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 4306.734362] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:67:DP-2] Link Training Passed at Link Rate = 162000, Lane count = 4
>[ 4306.735365] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 4306.735437] [drm:intel_edp_drrs_enable [i915]] Panel doesn't support DRRS
>[ 4306.752276] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:67:DP-2]
>[ 4306.752354] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe B]
>[ 4306.752442] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[ 4306.835795] [drm:drm_mode_addfb2 [drm]] [FB:169]
>[ 4306.836289] [drm:drm_mode_addfb2 [drm]] [FB:171]
>[ 4306.836466] [drm:drm_mode_addfb2 [drm]] [FB:172]
>[ 4306.842519] [drm:drm_mode_setcrtc [drm]] [CRTC:46:pipe B]
>[ 4306.842552] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:67:DP-2]
>[ 4306.886056] [drm:drm_mode_addfb2 [drm]] [FB:174]
>[ 4306.905967] [drm:drm_mode_setcrtc [drm]] [CRTC:46:pipe B]
>[ 4306.906001] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:73:DP-3]
>[ 4306.906107] [drm:intel_atomic_check [i915]] [CONNECTOR:73:DP-3] checking for sink bpp constrains
>[ 4306.906174] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 4306.906266] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 297000KHz
>[ 4306.906344] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 4 clock 270000 bpp 24
>[ 4306.906415] [drm:intel_dp_compute_config [i915]] DP link bw required 891000 available 1080000
>[ 4306.906483] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 4306.906548] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe B][modeset]
>[ 4306.906612] [drm:intel_dump_pipe_config [i915]] output_types: DP (0x80)
>[ 4306.906674] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 4306.906737] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6920601, gmch_n: 8388608, link_m: 576716, link_n: 524288, tu: 64
>[ 4306.906797] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 4306.906856] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 4306.906888] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"3840x2160" 30 297000 3840 4016 4104 4400 2160 2168 2178 2250 0x48 0x9
>[ 4306.906949] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 4306.906979] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"3840x2160" 30 297000 3840 4016 4104 4400 2160 2168 2178 2250 0x48 0x9
>[ 4306.907042] [drm:intel_dump_pipe_config [i915]] crtc timings: 297000 3840 4016 4104 4400 2160 2168 2178 2250, type: 0x48 flags: 0x9
>[ 4306.907101] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 3840x2160, pixel rate 297000
>[ 4306.907161] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[ 4306.907220] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 4306.907278] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 4306.907340] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[ 4306.907399] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 4306.907461] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 1B] FB:172, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[ 4306.907519] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1200 dst 0x0+1920+1200
>[ 4306.907579] [drm:intel_dump_pipe_config [i915]] [PLANE:40:plane 2B] FB:169, fb = 256x256 format = XR24 little-endian (0x34325258)
>[ 4306.907637] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+256+256 dst 1188x815+256+256
>[ 4306.907696] [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor B] FB:173, fb = 128x128 format = AR24 little-endian (0x34325241)
>[ 4306.907754] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+128+128 dst 1475x303+128+128
>[ 4306.907820] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 4306.907880] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[ 4306.907955] [drm:intel_find_shared_dpll [i915]] [CRTC:46:pipe B] allocated DPLL 1
>[ 4306.908017] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[ 4306.912024] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 4306.920584] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well
>[ 4306.920657] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 2, on? 1) for crtc 46
>[ 4306.920722] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[ 4306.920791] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DDI B]
>[ 4306.920850] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST A]
>[ 4306.920905] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST B]
>[ 4306.920960] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST C]
>[ 4306.921013] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI C]
>[ 4306.921068] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[ 4306.921122] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[ 4306.921174] [drm:intel_atomic_commit_tail [i915]] [ENCODER:70:DP-MST C]
>[ 4306.921227] [drm:intel_atomic_commit_tail [i915]] [ENCODER:72:DDI D]
>[ 4306.921280] [drm:intel_atomic_commit_tail [i915]] [ENCODER:74:DP-MST A]
>[ 4306.921332] [drm:intel_atomic_commit_tail [i915]] [ENCODER:75:DP-MST B]
>[ 4306.921384] [drm:intel_atomic_commit_tail [i915]] [ENCODER:76:DP-MST C]
>[ 4306.921438] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:67:DP-2]
>[ 4306.921495] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[ 4306.921550] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[ 4306.921605] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[ 4306.921659] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[ 4306.921719] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 2, on? 0) for crtc 46
>[ 4306.921773] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[ 4306.923921] [drm:intel_power_well_enable [i915]] enabling DDI D IO power well
>[ 4306.924536] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4306.925797] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4306.927011] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4306.928264] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4306.929527] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4306.930430] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[ 4306.931417] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 4306.931475] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 4306.931530] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 4306.931585] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 4306.950327] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 4306.950372] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[ 4306.969029] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 4306.970305] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:73:DP-3] Link Training Passed at Link Rate = 270000, Lane count = 4
>[ 4306.970708] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 4306.970732] [drm:intel_edp_drrs_enable [i915]] Panel doesn't support DRRS
>[ 4306.970751] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:73:DP-3], [ENCODER:72:DDI D]
>[ 4306.970769] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 4306.970790] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 4307.004251] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:73:DP-3]
>[ 4307.004273] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe B]
>[ 4307.004301] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[ 4307.171071] [drm:drm_mode_addfb2 [drm]] [FB:173]
>[ 4307.171581] [drm:drm_mode_addfb2 [drm]] [FB:175]
>[ 4307.171766] [drm:drm_mode_addfb2 [drm]] [FB:176]
>[ 4307.191648] [drm:drm_mode_setcrtc [drm]] [CRTC:46:pipe B]
>[ 4307.191683] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:73:DP-3]
>[ 4307.271234] [drm:drm_mode_addfb2 [drm]] [FB:178]
>[ 4307.276518] [drm:drm_mode_setcrtc [drm]] [CRTC:46:pipe B]
>[ 4307.276549] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:58:DP-1]
>[ 4307.276653] [drm:intel_atomic_check [i915]] [CONNECTOR:58:DP-1] checking for sink bpp constrains
>[ 4307.276719] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 4307.276787] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 148500KHz
>[ 4307.276851] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 4307.276909] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 648000
>[ 4307.276973] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 4307.277036] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe B][modeset]
>[ 4307.277096] [drm:intel_dump_pipe_config [i915]] output_types: DP (0x80)
>[ 4307.277156] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 4307.277216] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5767168, gmch_n: 8388608, link_m: 240298, link_n: 262144, tu: 64
>[ 4307.277273] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[ 4307.277329] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 4307.277359] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[ 4307.277418] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 4307.277446] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[ 4307.277506] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[ 4307.277564] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1080, pixel rate 148500
>[ 4307.277621] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[ 4307.277677] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 4307.277732] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 4307.277793] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x3, cfgcr1: 0x0, cfgcr2: 0x0
>[ 4307.277847] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 4307.277906] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 1B] FB:176, fb = 3840x2160 format = XR24 little-endian (0x34325258)
>[ 4307.277962] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+3840+2160 dst 0x0+3840+2160
>[ 4307.278019] [drm:intel_dump_pipe_config [i915]] [PLANE:40:plane 2B] FB:173, fb = 256x256 format = XR24 little-endian (0x34325258)
>[ 4307.278076] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+256+256 dst 2339x1436+256+256
>[ 4307.278132] [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor B] FB:177, fb = 128x128 format = AR24 little-endian (0x34325241)
>[ 4307.278188] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+128+128 dst 3075x550+128+128
>[ 4307.278274] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 4307.278346] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[ 4307.278425] [drm:intel_find_shared_dpll [i915]] [CRTC:46:pipe B] allocated DPLL 1
>[ 4307.278491] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[ 4307.279634] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 4307.279699] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[ 4307.279781] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 4307.304800] [drm:intel_power_well_disable [i915]] disabling DDI D IO power well
>[ 4307.304871] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 2, on? 1) for crtc 46
>[ 4307.304936] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[ 4307.305003] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DDI B]
>[ 4307.305062] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST A]
>[ 4307.305119] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST B]
>[ 4307.305174] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST C]
>[ 4307.305229] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI C]
>[ 4307.305282] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[ 4307.305335] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[ 4307.305387] [drm:intel_atomic_commit_tail [i915]] [ENCODER:70:DP-MST C]
>[ 4307.305439] [drm:intel_atomic_commit_tail [i915]] [ENCODER:72:DDI D]
>[ 4307.305493] [drm:intel_atomic_commit_tail [i915]] [ENCODER:74:DP-MST A]
>[ 4307.305545] [drm:intel_atomic_commit_tail [i915]] [ENCODER:75:DP-MST B]
>[ 4307.305596] [drm:intel_atomic_commit_tail [i915]] [ENCODER:76:DP-MST C]
>[ 4307.305651] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:73:DP-3]
>[ 4307.305708] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[ 4307.305764] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[ 4307.305819] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[ 4307.305873] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[ 4307.305933] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 2, on? 0) for crtc 46
>[ 4307.305987] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[ 4307.308129] [drm:intel_power_well_enable [i915]] enabling DDI B IO power well
>[ 4307.309279] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 4307.309339] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 4307.309395] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 4307.309451] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 4307.311233] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 04000000
>[ 4307.311286] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[ 4307.311337] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 4307.313068] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 4307.313119] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 4307.315206] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[ 4307.315269] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[ 4307.315326] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[ 4307.316291] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 4307.318362] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:58:DP-1] Link Training Passed at Link Rate = 162000, Lane count = 4
>[ 4307.319051] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 4307.319122] [drm:intel_edp_drrs_enable [i915]] Panel doesn't support DRRS
>[ 4307.335884] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:58:DP-1]
>[ 4307.335952] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe B]
>[ 4307.336033] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[ 4307.419354] [drm:drm_mode_addfb2 [drm]] [FB:177]
>[ 4307.419820] [drm:drm_mode_addfb2 [drm]] [FB:179]
>[ 4307.420028] [drm:drm_mode_addfb2 [drm]] [FB:180]
>[ 4307.425340] [drm:drm_mode_setcrtc [drm]] [CRTC:46:pipe B]
>[ 4307.425371] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:58:DP-1]
>[ 4307.469570] [drm:drm_mode_addfb2 [drm]] [FB:182]
>[ 4307.475674] [drm:drm_mode_setcrtc [drm]] [CRTC:46:pipe B]
>[ 4307.475709] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:67:DP-2]
>[ 4307.475814] [drm:intel_atomic_check [i915]] [CONNECTOR:67:DP-2] checking for sink bpp constrains
>[ 4307.475881] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 4307.475948] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 4307.476011] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 4307.476070] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 4307.476134] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 4307.476196] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe B][modeset]
>[ 4307.476254] [drm:intel_dump_pipe_config [i915]] output_types: DP (0x80)
>[ 4307.476313] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 4307.476373] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 4307.476429] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[ 4307.476484] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 4307.476513] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[ 4307.476570] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 4307.476597] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[ 4307.476657] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[ 4307.476714] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 4307.476770] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[ 4307.476826] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 4307.476882] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 4307.476942] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[ 4307.476998] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 4307.477057] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 1B] FB:180, fb = 1920x1080 format = XR24 little-endian (0x34325258)
>[ 4307.477113] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[ 4307.477170] [drm:intel_dump_pipe_config [i915]] [PLANE:40:plane 2B] FB:177, fb = 256x256 format = XR24 little-endian (0x34325258)
>[ 4307.477226] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+256+256 dst 75x647+256+256
>[ 4307.477282] [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor B] FB:181, fb = 128x128 format = AR24 little-endian (0x34325241)
>[ 4307.477338] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+128+128 dst 1791x431+128+128
>[ 4307.477400] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 4307.477458] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[ 4307.477529] [drm:intel_find_shared_dpll [i915]] [CRTC:46:pipe B] allocated DPLL 1
>[ 4307.477588] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[ 4307.478884] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 4307.486458] [drm:intel_power_well_disable [i915]] disabling DDI B IO power well
>[ 4307.486531] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 2, on? 1) for crtc 46
>[ 4307.486595] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[ 4307.486662] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DDI B]
>[ 4307.486723] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST A]
>[ 4307.486780] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST B]
>[ 4307.486836] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST C]
>[ 4307.486891] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI C]
>[ 4307.486946] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[ 4307.487000] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[ 4307.487053] [drm:intel_atomic_commit_tail [i915]] [ENCODER:70:DP-MST C]
>[ 4307.487105] [drm:intel_atomic_commit_tail [i915]] [ENCODER:72:DDI D]
>[ 4307.487158] [drm:intel_atomic_commit_tail [i915]] [ENCODER:74:DP-MST A]
>[ 4307.487210] [drm:intel_atomic_commit_tail [i915]] [ENCODER:75:DP-MST B]
>[ 4307.487262] [drm:intel_atomic_commit_tail [i915]] [ENCODER:76:DP-MST C]
>[ 4307.487317] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:58:DP-1]
>[ 4307.487373] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[ 4307.487429] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[ 4307.487484] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[ 4307.487538] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[ 4307.487598] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 2, on? 0) for crtc 46
>[ 4307.487653] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[ 4307.489798] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well
>[ 4307.491675] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 4307.491737] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 4307.491793] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 4307.491849] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 4307.494442] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 4307.494506] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 4307.496256] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 4307.498364] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:67:DP-2] Link Training Passed at Link Rate = 162000, Lane count = 4
>[ 4307.499360] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 4307.499432] [drm:intel_edp_drrs_enable [i915]] Panel doesn't support DRRS
>[ 4307.516249] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:67:DP-2]
>[ 4307.516325] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe B]
>[ 4307.516413] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[ 4307.599881] [drm:drm_mode_addfb2 [drm]] [FB:181]
>[ 4307.600417] [drm:drm_mode_addfb2 [drm]] [FB:183]
>[ 4307.600599] [drm:drm_mode_addfb2 [drm]] [FB:184]
>[ 4307.606666] [drm:drm_mode_setcrtc [drm]] [CRTC:46:pipe B]
>[ 4307.606700] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:67:DP-2]
>[ 4307.650023] [drm:drm_mode_addfb2 [drm]] [FB:186]
>[ 4307.669997] [drm:drm_mode_setcrtc [drm]] [CRTC:46:pipe B]
>[ 4307.670031] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:73:DP-3]
>[ 4307.670139] [drm:intel_atomic_check [i915]] [CONNECTOR:73:DP-3] checking for sink bpp constrains
>[ 4307.670207] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 4307.670297] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 297000KHz
>[ 4307.670373] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 4 clock 270000 bpp 24
>[ 4307.670442] [drm:intel_dp_compute_config [i915]] DP link bw required 891000 available 1080000
>[ 4307.670511] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 4307.670577] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe B][modeset]
>[ 4307.670640] [drm:intel_dump_pipe_config [i915]] output_types: DP (0x80)
>[ 4307.670702] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 4307.670764] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6920601, gmch_n: 8388608, link_m: 576716, link_n: 524288, tu: 64
>[ 4307.670823] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 4307.670882] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 4307.670914] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"3840x2160" 30 297000 3840 4016 4104 4400 2160 2168 2178 2250 0x48 0x9
>[ 4307.670975] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 4307.671006] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"3840x2160" 30 297000 3840 4016 4104 4400 2160 2168 2178 2250 0x48 0x9
>[ 4307.671068] [drm:intel_dump_pipe_config [i915]] crtc timings: 297000 3840 4016 4104 4400 2160 2168 2178 2250, type: 0x48 flags: 0x9
>[ 4307.671126] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 3840x2160, pixel rate 297000
>[ 4307.671186] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[ 4307.671245] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 4307.671303] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 4307.671365] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[ 4307.671424] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 4307.671485] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 1B] FB:184, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[ 4307.671545] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1200 dst 0x0+1920+1200
>[ 4307.671605] [drm:intel_dump_pipe_config [i915]] [PLANE:40:plane 2B] FB:181, fb = 256x256 format = XR24 little-endian (0x34325258)
>[ 4307.671664] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+256+256 dst 1188x815+256+256
>[ 4307.671723] [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor B] FB:185, fb = 128x128 format = AR24 little-endian (0x34325241)
>[ 4307.671781] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+128+128 dst 1475x303+128+128
>[ 4307.671846] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 4307.671907] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[ 4307.671980] [drm:intel_find_shared_dpll [i915]] [CRTC:46:pipe B] allocated DPLL 1
>[ 4307.672042] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[ 4307.676019] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 4307.684785] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well
>[ 4307.684858] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 2, on? 1) for crtc 46
>[ 4307.684922] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[ 4307.684993] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DDI B]
>[ 4307.685052] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST A]
>[ 4307.685108] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST B]
>[ 4307.685162] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST C]
>[ 4307.685215] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI C]
>[ 4307.685270] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[ 4307.685323] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[ 4307.685376] [drm:intel_atomic_commit_tail [i915]] [ENCODER:70:DP-MST C]
>[ 4307.685427] [drm:intel_atomic_commit_tail [i915]] [ENCODER:72:DDI D]
>[ 4307.685480] [drm:intel_atomic_commit_tail [i915]] [ENCODER:74:DP-MST A]
>[ 4307.685532] [drm:intel_atomic_commit_tail [i915]] [ENCODER:75:DP-MST B]
>[ 4307.685583] [drm:intel_atomic_commit_tail [i915]] [ENCODER:76:DP-MST C]
>[ 4307.685638] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:67:DP-2]
>[ 4307.685695] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[ 4307.685750] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[ 4307.685805] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[ 4307.685859] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[ 4307.685918] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 2, on? 0) for crtc 46
>[ 4307.685973] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[ 4307.688111] [drm:intel_power_well_enable [i915]] enabling DDI D IO power well
>[ 4307.688722] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4307.689985] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4307.691231] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4307.692494] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4307.693762] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4307.694592] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[ 4307.695578] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 4307.695637] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 4307.695692] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 4307.695747] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 4307.714447] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 4307.714477] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[ 4307.733132] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 4307.734292] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:73:DP-3] Link Training Passed at Link Rate = 270000, Lane count = 4
>[ 4307.734675] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 4307.734696] [drm:intel_edp_drrs_enable [i915]] Panel doesn't support DRRS
>[ 4307.734712] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:73:DP-3], [ENCODER:72:DDI D]
>[ 4307.734727] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 4307.734745] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 4307.768141] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:73:DP-3]
>[ 4307.768171] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe B]
>[ 4307.768207] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[ 4307.935082] [drm:drm_mode_addfb2 [drm]] [FB:185]
>[ 4307.935611] [drm:drm_mode_addfb2 [drm]] [FB:187]
>[ 4307.935802] [drm:drm_mode_addfb2 [drm]] [FB:188]
>[ 4307.956596] [drm:drm_mode_setcrtc [drm]] [CRTC:46:pipe B]
>[ 4307.956631] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:73:DP-3]
>[ 4308.035247] [IGT] kms_plane_multiple: exiting, ret=0
>[ 4308.101747] [drm:intel_atomic_check [i915]] [CONNECTOR:58:DP-1] checking for sink bpp constrains
>[ 4308.101824] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 4308.101900] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 148500KHz
>[ 4308.101972] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 4308.102039] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 648000
>[ 4308.102110] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 4308.102185] [drm:intel_dump_pipe_config [i915]] [CRTC:36:pipe A][modeset]
>[ 4308.102301] [drm:intel_dump_pipe_config [i915]] output_types: DP (0x80)
>[ 4308.102375] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 4308.102452] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5767168, gmch_n: 8388608, link_m: 240298, link_n: 262144, tu: 64
>[ 4308.102522] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[ 4308.102590] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 4308.102631] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[ 4308.102694] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 4308.102733] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[ 4308.102798] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[ 4308.102862] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1080, pixel rate 148500
>[ 4308.102924] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[ 4308.102986] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 4308.103046] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 4308.103113] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[ 4308.103175] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 4308.103238] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 1A] disabled, scaler_id = -1
>[ 4308.103299] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 2A] disabled, scaler_id = -1
>[ 4308.103361] [drm:intel_dump_pipe_config [i915]] [PLANE:33:cursor A] disabled, scaler_id = -1
>[ 4308.103430] [drm:intel_atomic_check [i915]] [CONNECTOR:67:DP-2] checking for sink bpp constrains
>[ 4308.103496] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 4308.103564] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 4308.103630] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 4308.103693] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 4308.103759] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 4308.103825] [drm:intel_dump_pipe_config [i915]] [CRTC:46:pipe B][modeset]
>[ 4308.103889] [drm:intel_dump_pipe_config [i915]] output_types: DP (0x80)
>[ 4308.103952] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 4308.104016] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 4308.104077] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[ 4308.104137] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 4308.104171] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[ 4308.104233] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 4308.104265] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[ 4308.104330] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[ 4308.104392] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 4308.104453] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[ 4308.104514] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 4308.104574] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 4308.104640] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x3, cfgcr1: 0x0, cfgcr2: 0x0
>[ 4308.104700] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 4308.104762] [drm:intel_dump_pipe_config [i915]] [PLANE:37:plane 1B] disabled, scaler_id = -1
>[ 4308.104824] [drm:intel_dump_pipe_config [i915]] [PLANE:40:plane 2B] disabled, scaler_id = -1
>[ 4308.104887] [drm:intel_dump_pipe_config [i915]] [PLANE:43:cursor B] FB:189, fb = 128x128 format = AR24 little-endian (0x34325241)
>[ 4308.104948] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+128+128 dst 3075x550+128+128
>[ 4308.105015] [drm:intel_atomic_check [i915]] [CONNECTOR:73:DP-3] checking for sink bpp constrains
>[ 4308.105079] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 4308.105146] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 297000KHz
>[ 4308.105211] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 4 clock 270000 bpp 24
>[ 4308.105274] [drm:intel_dp_compute_config [i915]] DP link bw required 891000 available 1080000
>[ 4308.105339] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 4308.105405] [drm:intel_dump_pipe_config [i915]] [CRTC:56:pipe C][modeset]
>[ 4308.105469] [drm:intel_dump_pipe_config [i915]] output_types: DP (0x80)
>[ 4308.105532] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 24, dithering: 0
>[ 4308.105594] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 6920601, gmch_n: 8388608, link_m: 576716, link_n: 524288, tu: 64
>[ 4308.105656] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 4308.105716] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 4308.105749] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"3840x2160" 30 297000 3840 4016 4104 4400 2160 2168 2178 2250 0x48 0x9
>[ 4308.105809] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 4308.105841] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"3840x2160" 30 297000 3840 4016 4104 4400 2160 2168 2178 2250 0x48 0x9
>[ 4308.105904] [drm:intel_dump_pipe_config [i915]] crtc timings: 297000 3840 4016 4104 4400 2160 2168 2178 2250, type: 0x48 flags: 0x9
>[ 4308.105967] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 3840x2160, pixel rate 297000
>[ 4308.106027] [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>[ 4308.106088] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 4308.106147] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 4308.106214] [drm:skl_dump_hw_state [i915]] dpll_hw_state: ctrl1: 0x3, cfgcr1: 0x0, cfgcr2: 0x0
>[ 4308.106288] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 4308.106361] [drm:intel_dump_pipe_config [i915]] [PLANE:47:plane 1C] disabled, scaler_id = -1
>[ 4308.106428] [drm:intel_dump_pipe_config [i915]] [PLANE:50:plane 2C] disabled, scaler_id = -1
>[ 4308.106495] [drm:intel_dump_pipe_config [i915]] [PLANE:53:cursor C] disabled, scaler_id = -1
>[ 4308.106569] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 4308.106636] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[ 4308.106717] [drm:intel_find_shared_dpll [i915]] [CRTC:36:pipe A] allocated DPLL 1
>[ 4308.106786] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[ 4308.106859] [drm:intel_find_shared_dpll [i915]] [CRTC:46:pipe B] sharing existing DPLL 1 (crtc mask 0x00000001, active 2)
>[ 4308.106927] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[ 4308.106962] [drm:intel_find_shared_dpll [i915]] [CRTC:56:pipe C] allocated DPLL 2
>[ 4308.106991] [drm:intel_reference_shared_dpll [i915]] using DPLL 2 for pipe C
>[ 4308.107043] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 4308.107059] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[ 4308.107103] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 4308.135099] [drm:intel_power_well_disable [i915]] disabling DDI D IO power well
>[ 4308.135128] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 2, on? 1) for crtc 46
>[ 4308.135153] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[ 4308.135176] [drm:intel_disable_sagv [i915]] Disabling the SAGV
>[ 4308.135203] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DDI B]
>[ 4308.135226] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST A]
>[ 4308.135248] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DP-MST B]
>[ 4308.135270] [drm:intel_atomic_commit_tail [i915]] [ENCODER:61:DP-MST C]
>[ 4308.135291] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI C]
>[ 4308.135312] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[ 4308.135334] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[ 4308.135354] [drm:intel_atomic_commit_tail [i915]] [ENCODER:70:DP-MST C]
>[ 4308.135375] [drm:intel_atomic_commit_tail [i915]] [ENCODER:72:DDI D]
>[ 4308.135396] [drm:intel_atomic_commit_tail [i915]] [ENCODER:74:DP-MST A]
>[ 4308.135416] [drm:intel_atomic_commit_tail [i915]] [ENCODER:75:DP-MST B]
>[ 4308.135437] [drm:intel_atomic_commit_tail [i915]] [ENCODER:76:DP-MST C]
>[ 4308.135458] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[ 4308.135480] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[ 4308.135502] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[ 4308.135524] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[ 4308.135548] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 2, on? 0) for crtc 46
>[ 4308.135569] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[ 4308.137749] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well
>[ 4308.139522] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 4308.139550] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 4308.139575] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 4308.139601] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 4308.142101] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 4308.142135] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 4308.143834] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 4308.145985] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:67:DP-2] Link Training Passed at Link Rate = 162000, Lane count = 4
>[ 4308.146836] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 4308.146883] [drm:intel_edp_drrs_enable [i915]] Panel doesn't support DRRS
>[ 4308.163796] [drm:intel_enable_shared_dpll [i915]] enable DPLL 2 (active 4, on? 0) for crtc 56
>[ 4308.163864] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 2
>[ 4308.166111] [drm:intel_power_well_enable [i915]] enabling DDI D IO power well
>[ 4308.166732] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4308.167992] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4308.169253] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4308.170512] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4308.171773] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4308.172648] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[ 4308.173629] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 4308.173687] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 4308.173743] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 4308.173798] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 4308.192573] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 4308.192636] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[ 4308.211391] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 4308.213579] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:73:DP-3] Link Training Passed at Link Rate = 270000, Lane count = 4
>[ 4308.214113] [drm:intel_enable_pipe [i915]] enabling pipe C
>[ 4308.214152] [drm:intel_edp_drrs_enable [i915]] Panel doesn't support DRRS
>[ 4308.214208] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:73:DP-3], [ENCODER:72:DDI D]
>[ 4308.214242] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe C, 36 bytes ELD
>[ 4308.214279] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 4308.214356] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 3, on? 1) for crtc 36
>[ 4308.214394] [drm:intel_power_well_enable [i915]] enabling DDI B IO power well
>[ 4308.215471] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 4308.215501] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 4308.215529] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 4308.215558] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 4308.218295] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 04000000
>[ 4308.218318] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[ 4308.218339] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 4308.220027] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 4308.220054] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 4308.222044] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 05000000
>[ 4308.222066] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[ 4308.222087] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[ 4308.222987] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 4308.225078] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:58:DP-1] Link Training Passed at Link Rate = 162000, Lane count = 4
>[ 4308.225475] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 4308.225500] [drm:intel_edp_drrs_enable [i915]] Panel doesn't support DRRS
>[ 4308.225524] [drm:intel_fbc_enable [i915]] reserved 16588800 bytes of contiguous stolen space for FBC, threshold: 1
>[ 4308.225545] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 4308.247560] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:58:DP-1]
>[ 4308.247584] [drm:intel_atomic_commit_tail [i915]] [CRTC:36:pipe A]
>[ 4308.247614] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[ 4308.247644] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:67:DP-2]
>[ 4308.247665] [drm:intel_atomic_commit_tail [i915]] [CRTC:46:pipe B]
>[ 4308.247692] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[ 4308.247720] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:73:DP-3]
>[ 4308.247740] [drm:intel_atomic_commit_tail [i915]] [CRTC:56:pipe C]
>[ 4308.247765] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2

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Attachments on bug 103741: 135455 | 135456

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