Attachment 135830 Details for Bug 103997 – log_testdisplay_hang

log_testdisplay_hang

logs-disp-hang (text/plain), 19.52 KB, created by Elizabeth on 2017-11-30 15:36:39 UTC

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Creator: Elizabeth

Created: 2017-11-30 15:36:39 UTC

Size: 19.52 KB

patch

obsolete

>
>$ sudo testdisplay 
>CRTC(42):[0]  2560x1440 60 2560 2608 2640 2720 1440 1442 1447 1480 0xa 0x48 241500
>CRTC(42):[1]  2560x1440 48 2560 2608 2640 2720 1440 1442 1447 1480 0xa 0x40 193220
>CRTC(42):[0]  3840x2160 30 3840 4016 4104 4400 2160 2168 2178 2250 0x5 0x40 297000
>(hard hang)
>
>dmesg:
>
>[  407.985935] [drm:drm_mode_addfb2] [FB:132]
>[  408.055009] [drm:drm_mode_setcrtc] [CRTC:42:pipe A]
>[  408.055021] [drm:drm_mode_setcrtc] [CONNECTOR:76:eDP-1]
>[  408.055026] [drm:drm_atomic_state_init] Allocated atomic state ffff8802607b6c00
>[  408.055052] [drm:drm_atomic_get_crtc_state] Added [CRTC:42:pipe A] ffff8802608ba800 state to ffff8802607b6c00
>[  408.055055] [drm:drm_atomic_get_plane_state] Added [PLANE:27:plane 1A] ffff88025ee63200 state to ffff8802607b6c00
>[  408.055058] [drm:drm_atomic_set_mode_for_crtc] Set [MODE:2560x1440] for CRTC state ffff8802608ba800
>[  408.055060] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88025ee63200 to [CRTC:42:pipe A]
>[  408.055062] [drm:drm_atomic_set_fb_for_plane] Set [FB:132] for plane state ffff88025ee63200
>[  408.055065] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:42:pipe A] to ffff8802607b6c00
>[  408.055068] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:76:eDP-1] ffff880260888880 state to ffff8802607b6c00
>[  408.055071] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff880260888880 to [NOCRTC]
>[  408.055073] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff880260888880 to [CRTC:42:pipe A]
>[  408.055077] [drm:drm_atomic_check_only] checking ffff8802607b6c00
>[  408.055081] [drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:76:eDP-1]
>[  408.055084] [drm:drm_atomic_helper_check_modeset] [CONNECTOR:76:eDP-1] keeps [ENCODER:75:DDI A], now on [CRTC:42:pipe A]
>[  408.055115] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:42:pipe A] has [PLANE:27:plane 1A] with fb 132
>[  408.055135] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:27:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>[  408.055168] [drm:drm_atomic_commit] committing ffff8802607b6c00
>[  408.058444] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff8802607b6c00
>[  408.058470] [drm:__drm_atomic_state_free] Freeing atomic state ffff8802607b6c00
>[  409.119399] [drm:intel_dp_set_drrs_state.isra.23 [i915]] eDP Refresh Rate set to : 48Hz
>[  413.058965] [drm:drm_mode_addfb2] [FB:100]
>[  413.092637] [drm:drm_mode_setcrtc] [CRTC:42:pipe A]
>[  413.092650] [drm:drm_mode_setcrtc] [CONNECTOR:76:eDP-1]
>[  413.092678] [drm:drm_atomic_state_init] Allocated atomic state ffff8802607b6c00
>[  413.092682] [drm:drm_atomic_get_crtc_state] Added [CRTC:42:pipe A] ffff8802608bd800 state to ffff8802607b6c00
>[  413.092685] [drm:drm_atomic_get_plane_state] Added [PLANE:27:plane 1A] ffff88025ee63300 state to ffff8802607b6c00
>[  413.092689] [drm:drm_atomic_set_mode_for_crtc] Set [MODE:2560x1440] for CRTC state ffff8802608bd800
>[  413.092691] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff88025ee63300 to [CRTC:42:pipe A]
>[  413.092693] [drm:drm_atomic_set_fb_for_plane] Set [FB:100] for plane state ffff88025ee63300
>[  413.092695] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:42:pipe A] to ffff8802607b6c00
>[  413.092698] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:76:eDP-1] ffff880260888f00 state to ffff8802607b6c00
>[  413.092701] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff880260888f00 to [NOCRTC]
>[  413.092704] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff880260888f00 to [CRTC:42:pipe A]
>[  413.092708] [drm:drm_atomic_check_only] checking ffff8802607b6c00
>[  413.092711] [drm:drm_atomic_helper_check_modeset] [CRTC:42:pipe A] mode changed
>[  413.092713] [drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:76:eDP-1]
>[  413.092716] [drm:drm_atomic_helper_check_modeset] [CONNECTOR:76:eDP-1] keeps [ENCODER:75:DDI A], now on [CRTC:42:pipe A]
>[  413.092718] [drm:drm_atomic_helper_check_modeset] [CRTC:42:pipe A] needs all connectors, enable: y, active: y
>[  413.092720] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:42:pipe A] to ffff8802607b6c00
>[  413.092724] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:42:pipe A] to ffff8802607b6c00
>[  413.102525] [drm:intel_atomic_check.part.136 [i915]] [CONNECTOR:76:eDP-1] checking for sink bpp constrains
>[  413.102547] [drm:intel_atomic_check.part.136 [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  413.102554] [drm:drm_mode_debug_printmodeline] Modeline 82:"2560x1440" 48 193220 2560 2608 2640 2720 1440 1442 1447 1480 0x40 0xa
>[  413.102578] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 193220KHz
>[  413.102611] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 4 clock 270000 bpp 24
>[  413.102628] [drm:intel_dp_compute_config [i915]] DP link bw required 579660 available 1080000
>[  413.102645] [drm:intel_psr_compute_config [i915]] PSR disable by flag
>[  413.102664] [drm:intel_atomic_check.part.136 [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  413.102683] [drm:intel_dump_pipe_config [i915]] [CRTC:42:pipe A][modeset]
>[  413.102699] [drm:intel_dump_pipe_config [i915]] output_types: EDP (0x100)
>[  413.102712] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0
>[  413.102726] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 4502352, gmch_n: 8388608, link_m: 375196, link_n: 524288, tu: 64
>[  413.102739] [drm:intel_dump_pipe_config [i915]] dp m2_n2: lanes: 4; gmch_m: 4502352, gmch_n: 8388608, link_m: 375196, link_n: 524288, tu: 64
>[  413.102752] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  413.102765] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  413.102769] [drm:drm_mode_debug_printmodeline] Modeline 0:"2560x1440" 48 193220 2560 2608 2640 2720 1440 1442 1447 1480 0x40 0xa
>[  413.102780] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  413.102784] [drm:drm_mode_debug_printmodeline] Modeline 0:"2560x1440" 48 193220 2560 2608 2640 2720 1440 1442 1447 1480 0x40 0xa
>[  413.102796] [drm:intel_dump_pipe_config [i915]] crtc timings: 193220 2560 2608 2640 2720 1440 1442 1447 1480, type: 0x40 flags: 0xa
>[  413.10280
>
>9] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 2560x1440, pixel rate 193220
>[  413.102821] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  413.102834] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  413.102846] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  413.102863] [drm:cnl_dump_hw_state [i915]] dpll_hw_state: cfgcr0: 0x22000000, cfgcr1: 0x0
>[  413.102875] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  413.102889] [drm:intel_dump_pipe_config [i915]] [PLANE:27:plane 1A] FB:132, fb = 2560x1440 format = XR24 little-endian (0x34325258)
>[  413.102902] [drm:intel_dump_pipe_config [i915]]      scaler:-1 src 0x0+2560+1440 dst 0x0+2560+1440
>[  413.102914] [drm:intel_dump_pipe_config [i915]] [PLANE:30:plane 2A] disabled, scaler_id = -1
>[  413.102927] [drm:intel_dump_pipe_config [i915]] [PLANE:33:plane 3A] disabled, scaler_id = -1
>[  413.102939] [drm:intel_dump_pipe_config [i915]] [PLANE:36:plane 4A] disabled, scaler_id = -1
>[  413.102951] [drm:intel_dump_pipe_config [i915]] [PLANE:39:cursor A] disabled, scaler_id = -1
>[  413.102969] [drm:intel_atomic_check.part.136 [i915]] New cdclk calculated to be logical 336000 kHz, actual 336000 kHz
>[  413.102984] [drm:intel_atomic_check.part.136 [i915]] New voltage level calculated to be logical 1, actual 1
>[  413.103006] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:42:pipe A] has [PLANE:27:plane 1A] with fb 100
>[  413.103024] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:27:plane 1A] visible 1 -> 1, off 1, on 1, ms 1
>[  413.103042] [drm:intel_find_shared_dpll [i915]] [CRTC:42:pipe A] allocated DPLL 0
>[  413.103056] [drm:intel_reference_shared_dpll [i915]] using DPLL 0 for pipe A
>[  413.103064] [drm:drm_atomic_commit] committing ffff8802607b6c00
>[  413.104650] [drm:intel_dp_set_drrs_state.isra.23 [i915]] eDP Refresh Rate set to : 60Hz
>[  413.104667] [drm:intel_edp_backlight_off [i915]] 
>[  413.104679] [drm:intel_power_well_enable [i915]] enabling AUX A
>[  413.104810] [drm:intel_power_well_disable [i915]] disabling AUX A
>[  413.311382] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0
>[  413.311572] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  413.321168] [drm:intel_power_well_enable [i915]] enabling AUX A
>[  413.321280] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[  413.321552] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b
>[  413.321898] [drm:intel_edp_panel_off.part.30 [i915]] Turn eDP port A panel power off
>[  413.322080] [drm:intel_edp_panel_off.part.30 [i915]] Wait for panel power off time
>[  413.322309] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000002 control 00000060
>[  413.372480] [drm:wait_panel_status [i915]] Wait complete
>[  413.372535] [drm:intel_power_well_disable [i915]] disabling AUX A
>[  413.374869] [drm:intel_power_well_disable [i915]] disabling DDI A IO power well
>[  413.377288] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  413.377360] [drm:intel_disable_shared_dpll [i915]] disable DPLL 0 (active 1, on? 1) for crtc 42
>[  413.377418] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 0
>[  413.377487] [drm:intel_atomic_commit_tail [i915]] [ENCODER:75:DDI A]
>[  413.377537] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DDI B]
>[  413.377581] [drm:intel_atomic_commit_tail [i915]] [ENCODER:88:DP-MST A]
>[  413.377624] [drm:intel_atomic_commit_tail [i915]] [ENCODER:89:DP-MST B]
>[  413.377664] [drm:intel_atomic_commit_tail [i915]] [ENCODER:90:DP-MST C]
>[  413.377704] [drm:intel_atomic_commit_tail [i915]] [ENCODER:91:DDI C]
>[  413.377744] [drm:intel_atomic_commit_tail [i915]] [ENCODER:94:DDI D]
>[  413.377783] [drm:intel_atomic_commit_tail [i915]] [ENCODER:96:DP-MST A]
>[  413.377822] [drm:intel_atomic_commit_tail [i915]] [ENCODER:97:DP-MST B]
>[  413.377860] [drm:intel_atomic_commit_tail [i915]] [ENCODER:98:DP-MST C]
>[  413.377909] [drm:verify_single_dpll_state.isra.115 [i915]] DPLL 0
>[  413.377958] [drm:verify_single_dpll_state.isra.115 [i915]] DPLL 1
>[  413.378155] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010
>[  413.378205] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  413.378252] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0
>[  413.378372] [drm:verify_single_dpll_state.isra.115 [i915]] DPLL 2
>[  413.378446] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  413.378522] [drm:intel_enable_shared_dpll [i915]] enable DPLL 0 (active 1, on? 0) for crtc 42
>[  413.378582] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 0
>[  413.380975] [drm:intel_power_well_enable [i915]] enabling AUX A
>[  413.381049] [drm:edp_panel_on [i915]] Turn eDP port A panel power on
>[  413.381199] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle
>[  413.983330] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 00000000 control 00000060
>[  413.983429] [drm:wait_panel_status [i915]] Wait complete
>[  413.983588] [drm:edp_panel_on [i915]] Wait for panel power on
>[  413.983818] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 00000063
>[  414.074699] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010
>[  414.074770] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  414.074828] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1
>[  414.074988] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  414.184831] [drm:wait_panel_status [i915]] Wait complete
>[  414.184885] [drm:intel_power_well_disable [i915]] disabling AUX A
>[  414.187088] [drm:intel_power_well_enable [i915]] enabling DDI A IO power well
>[  414.1872[  414.204820] [drm:intel_ddi_enable_transcoder_func [i915]] *ERROR* I915-DEBUG: intel_ddi_enable_transcoder_func 1604 transcoder: 3 port: 0 old: 2000006 new: 82000006
>86] [drm:intel_power_well_enable [i915]] enabling AUX A
>[  414.187400] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[  414.187683] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b
>intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  414.189607] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  414.189658] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  414.194653] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  414.194667] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 1
>[  414.199482] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  414.199496] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  414.204327] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  414.204343] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:76:eDP-1] Link Training Passed at Link Rate = 270000, Lane count = 4
>[  414.204820] [drm:intel_ddi_enable_transcoder_func [i915]] *ERROR* I915-DEBUG: intel_ddi_enable_transcoder_func 1604 transcoder: 3 port: 0 old: 2000006 new: 82000006
>[  414.219950] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  414.219986] [drm:intel_edp_backlight_on [i915]] 
>[  414.220001] [drm:intel_panel_enable_backlight [i915]] pipe A
>[  414.220073] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 6000
>[  414.220339] [drm:intel_fbc_enable [i915]] reserved 29491200 bytes of contiguous stolen space for FBC, threshold: 1
>[  414.220354] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  414.241134] [drm:verify_connector_state.isra.114 [i915]] [CONNECTOR:76:eDP-1]
>[  414.241205] [drm:intel_atomic_commit_tail [i915]] [CRTC:42:pipe A]
>[  414.251555] [drm:verify_single_dpll_state.isra.115 [i915]] DPLL 0
>[  414.251576] [drm:drm_atomic_state_default_clear] Clearing atomic state ffff8802607b6c00
>[  414.251583] [drm:__drm_atomic_state_free] Freeing atomic state ffff8802607b6c00
>[  415.263399] [drm:intel_dp_set_drrs_state.isra.23 [i915]] eDP Refresh Rate set to : 48Hz
>[  417.247467] [drm:edp_panel_vdd_off_sync [i915]] Turning eDP port A VDD off
>[  417.247730] [drm:edp_panel_vdd_off_sync [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x00000067
>[  417.247786] [drm:intel_power_well_disable [i915]] disabling AUX A
>[  419.252054] [drm:drm_atomic_state_init] Allocated atomic state ffff880262a4e400
>[  419.252077] [drm:drm_atomic_get_plane_state] Added [PLANE:27:plane 1A] ffff880263b5ae00 state to ffff880262a4e400
>[  419.252088] [drm:drm_atomic_get_crtc_state] Added [CRTC:42:pipe A] ffff8802623ef000 state to ffff880262a4e400
>[  419.252095] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:42:pipe A] to ffff880262a4e400
>[  419.252105] [drm:drm_atomic_get_connector_state] Added [CONNECTOR:76:eDP-1] ffff880262ac3e00 state to ffff880262a4e400
>[  419.252132] [drm:drm_atomic_set_mode_for_crtc] Set [NOMODE] for CRTC state ffff8802623ef000
>[  419.252137] [drm:drm_atomic_set_fb_for_plane] Set [NOFB] for plane state ffff880263b5ae00
>[  419.252144] [drm:drm_atomic_set_crtc_for_plane] Link plane state ffff880263b5ae00 to [NOCRTC]
>[  419.252151] [drm:drm_atomic_set_crtc_for_connector] Link connector state ffff880262ac3e00 to [NOCRTC]
>[  419.252158] [drm:drm_atomic_check_only] checking ffff880262a4e400
>[  419.252167] [drm:drm_atomic_helper_check_modeset] [CRTC:42:pipe A] mode changed
>[  419.252171] [drm:drm_atomic_helper_check_modeset] [CRTC:42:pipe A] enable changed
>[  419.252176] [drm:drm_atomic_helper_check_modeset] [CRTC:42:pipe A] active changed
>[  419.252182] [drm:drm_atomic_helper_check_modeset] Updating routing for [CONNECTOR:76:eDP-1]
>[  419.252187] [drm:drm_atomic_helper_check_modeset] Disabling [CONNECTOR:76:eDP-1]
>[  419.252195] [drm:drm_atomic_helper_check_modeset] [CRTC:42:pipe A] needs all connectors, enable: n, active: n
>[  419.252201] [drm:drm_atomic_add_affected_connectors] Adding all current connectors for [CRTC:42:pipe A] to ffff880262a4e400
>[  419.252288] [drm:intel_atomic_check.part.136 [i915]] New cdclk calculated to be logical 336000 kHz, actual 336000 kHz
>[  419.252347] [drm:intel_atomic_check.part.136 [i915]] New voltage level calculated to be logical 1, actual 1
>[  419.252407] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:42:pipe A] has [PLANE:27:plane 1A] with fb -1
>[  419.252455] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:27:plane 1A] visible 1 -> 0, off 1, on 0, ms 1
>[  419.252470] [drm:drm_atomic_get_crtc_state] Added [CRTC:58:pipe B] ffff8802623ea800 state to ffff880262a4e400
>[  419.252481] [drm:drm_atomic_get_plane_state] Added [PLANE:43:plane 1B] ffff880263b5a700 state to ffff880262a4e400
>[  419.252488] [drm:drm_atomic_get_crtc_state] Added [CRTC:74:pipe C] ffff8802623ec800 state to ffff880262a4e400
>[  419.252536] [drm:skl_compute_wm [i915]] [PLANE:27:plane 1A] ddb (0 - 502) -> (0 - 0)
>[  419.252578] [drm:skl_compute_wm [i915]] [PLANE:39:cursor A] ddb (502 - 510) -> (0 - 0)
>[  419.252619] [drm:skl_compute_wm [i915]] [PLANE:43:plane 1B] ddb (510 - 1012) -> (0 - 988)
>[  419.252655] [drm:skl_compute_wm [i915]] [PLANE:55:cursor B] ddb (1012 - 1020) -> (988 - 1020)
>[  419.252663] [drm:drm_atomic_commit] committing ffff880262a4e400
>[  419.252763] [drm:intel_dp_set_drrs_state.isra.23 [i915]] eDP Refresh Rate set to : 60Hz
>[  419.252820] [drm:intel_edp_backlight_off [i915]] 
>[  419.252863] [drm:intel_power_well_enable [i915]] enabling AUX A
> [i915]] disabling AUX A
>[  419.463217] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0
>[  419.463405] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  419.483661] [drm:intel_power_well_enable [i915]] enabling AUX A
>[  419.483772] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[  419.484093] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b
>[  419.484467] [drm:intel_edp_panel_off.part.30 [i915]] Turn eDP port A panel power off
>[  419.484631] [drm:intel_edp_panel_off.part.30 [i915]] Wait for panel power off time
>[  419.484875] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000002 control 00000060
>[  419.535873] [drm:wait_panel_status [i915]] Wait complete
>[  419.535927] [drm:intel_power_well_disable [i915]] disabling AUX A
>[  419.538041] [drm:intel_power_well_disable [i915]] disabling DDI A IO power well
>[  419.540152] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  419.540210] [drm:intel_disable_shared_dpll [i915]] disable DPLL 0 (active 1, on? 1) for crtc 42
>[  419.540261] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 0
>[  419.540362] [drm:intel_atomic_commit_tail [i915]] [ENCODER:75:DDI A]
>[  419.540420] [drm:intel_atomic_commit_tail [i915]] [ENCODER:86:DDI B]
>[  419.540469] [drm:intel_atomic_commit_tail [i915]] [ENCODER:88:DP-MST A]
>[  419.540732] [drm:intel_get_hpd_pins [i915]] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010
>[  419.540781] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  419.540821] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0
>[  419.540873] [drm:intel_atomic_commit_tail [i915][  419.727154] [drm:intel_ddi_enable_transcoder_func [i915]] *ERROR* I915-DEBUG: intel_ddi_enable_transcoder_func 1604 transcoder: 0 port: 2 old: 30000 new: a0030000
>] [ENCODER:90:DP[  421.826702] Kernel panic - not syncing: Timeout: Not all CPUs entered broadcast exception handler
>[  422.903219] Shutting down cpus with NMI
>[  422.917799] Kernel Offset: disabled

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