Attachment 135861 Details for Bug 104021 – dmesg -w

dmesg -w

KmsFbconPsrSuspend-dmesg-w (text/plain), 2.60 MB, created by Hector Velazquez on 2017-12-01 18:30:41 UTC

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Creator: Hector Velazquez

Created: 2017-12-01 18:30:41 UTC

Size: 2.60 MB

patch

obsolete

>[    0.000000] Linux version 4.15.0-rc1-drm-tip-ww48-commit-4faecf8+ (gfx@bifrost) (gcc version 5.4.0 20160609 (Ubuntu 5.4.0-6ubuntu1~16.04.4)) #1 SMP Thu Nov 30 06:27:25 CST 2017
>[    0.000000] Command line: BOOT_IMAGE=/boot/vmlinuz-4.15.0-rc1-drm-tip-ww48-commit-4faecf8+ root=UUID=2a8388ef-fcb0-4ae0-964a-bd124748729c ro quiet drm.debug=0xe pci=pcie_bus_safe intel_iommu=igfx_off i915.alpha_support=1 auto i915.enable_guc_loading=1 i915.enable_guc_submission=1 panic=1 nmi_watchdog=panic log_buf_len=4M resume=/dev/nvme0n1p3 fastboot
>[    0.000000] KERNEL supported cpus:
>[    0.000000]   Intel GenuineIntel
>[    0.000000]   AMD AuthenticAMD
>[    0.000000]   Centaur CentaurHauls
>[    0.000000] x86/fpu: Supporting XSAVE feature 0x001: 'x87 floating point registers'
>[    0.000000] x86/fpu: Supporting XSAVE feature 0x002: 'SSE registers'
>[    0.000000] x86/fpu: Supporting XSAVE feature 0x004: 'AVX registers'
>[    0.000000] x86/fpu: Supporting XSAVE feature 0x008: 'MPX bounds registers'
>[    0.000000] x86/fpu: Supporting XSAVE feature 0x010: 'MPX CSR'
>[    0.000000] x86/fpu: xstate_offset[2]:  576, xstate_sizes[2]:  256
>[    0.000000] x86/fpu: xstate_offset[3]:  832, xstate_sizes[3]:   64
>[    0.000000] x86/fpu: xstate_offset[4]:  896, xstate_sizes[4]:   64
>[    0.000000] x86/fpu: Enabled xstate features 0x1f, context size is 960 bytes, using 'compacted' format.
>[    0.000000] e820: BIOS-provided physical RAM map:
>[    0.000000] BIOS-e820: [mem 0x0000000000000000-0x000000000009efff] usable
>[    0.000000] BIOS-e820: [mem 0x000000000009f000-0x00000000000fffff] reserved
>[    0.000000] BIOS-e820: [mem 0x0000000000100000-0x000000008c2e3fff] usable
>[    0.000000] BIOS-e820: [mem 0x000000008c2e4000-0x000000008c308fff] type 20
>[    0.000000] BIOS-e820: [mem 0x000000008c309000-0x000000008c991fff] reserved
>[    0.000000] BIOS-e820: [mem 0x000000008c992000-0x000000008cb81fff] ACPI NVS
>[    0.000000] BIOS-e820: [mem 0x000000008cb82000-0x000000008cc0efff] ACPI data
>[    0.000000] BIOS-e820: [mem 0x000000008cc0f000-0x000000008cc0ffff] usable
>[    0.000000] BIOS-e820: [mem 0x000000008cc10000-0x000000008fffffff] reserved
>[    0.000000] BIOS-e820: [mem 0x00000000fe010000-0x00000000fe010fff] reserved
>[    0.000000] BIOS-e820: [mem 0x00000000ff600000-0x00000000ffffffff] reserved
>[    0.000000] BIOS-e820: [mem 0x0000000100000000-0x000000046dffffff] usable
>[    0.000000] NX (Execute Disable) protection: active
>[    0.000000] efi: EFI v2.60 by Intel
>[    0.000000] efi:  SMBIOS=0x8c58d000  ACPI=0x8cc0e000  ACPI 2.0=0x8cc0e014  ESRT=0x89692a18 
>[    0.000000] random: fast init done
>[    0.000000] SMBIOS 3.0 present.
>[    0.000000] DMI: Intel Corporation CoffeeLake Client Platform/CoffeeLake S UDIMM RVP, BIOS CNLSFWR1.R00.X104.A03.1709140535 09/14/2017
>[    0.000000] e820: update [mem 0x00000000-0x00000fff] usable ==> reserved
>[    0.000000] e820: remove [mem 0x000a0000-0x000fffff] usable
>[    0.000000] e820: last_pfn = 0x46e000 max_arch_pfn = 0x400000000
>[    0.000000] MTRR default type: write-back
>[    0.000000] MTRR fixed ranges enabled:
>[    0.000000]   00000-9FFFF write-back
>[    0.000000]   A0000-BFFFF uncachable
>[    0.000000]   C0000-FFFFF write-protect
>[    0.000000] MTRR variable ranges enabled:
>[    0.000000]   0 base 00C0000000 mask 7FC0000000 uncachable
>[    0.000000]   1 base 00A0000000 mask 7FF0000000 write-combining
>[    0.000000]   2 base 0090000000 mask 7FF0000000 uncachable
>[    0.000000]   3 base 008E000000 mask 7FFE000000 uncachable
>[    0.000000]   4 base 008D800000 mask 7FFF800000 uncachable
>[    0.000000]   5 base 00B0000000 mask 7FF0000000 uncachable
>[    0.000000]   6 disabled
>[    0.000000]   7 disabled
>[    0.000000]   8 disabled
>[    0.000000]   9 disabled
>[    0.000000] x86/PAT: Configuration [0-7]: WB  WC  UC- UC  WB  WP  UC- WT  
>[    0.000000] e820: last_pfn = 0x8cc10 max_arch_pfn = 0x400000000
>[    0.000000] esrt: Reserving ESRT space from 0x0000000089692a18 to 0x0000000089692a78.
>[    0.000000] Scanning 1 areas for low memory corruption
>[    0.000000] Base memory trampoline at [ffff983980096000] 96000 size 24576
>[    0.000000] Using GB pages for direct mapping
>[    0.000000] BRK [0x186fac000, 0x186facfff] PGTABLE
>[    0.000000] BRK [0x186fad000, 0x186fadfff] PGTABLE
>[    0.000000] BRK [0x186fae000, 0x186faefff] PGTABLE
>[    0.000000] BRK [0x186faf000, 0x186faffff] PGTABLE
>[    0.000000] BRK [0x186fb0000, 0x186fb0fff] PGTABLE
>[    0.000000] BRK [0x186fb1000, 0x186fb1fff] PGTABLE
>[    0.000000] BRK [0x186fb2000, 0x186fb2fff] PGTABLE
>[    0.000000] BRK [0x186fb3000, 0x186fb3fff] PGTABLE
>[    0.000000] log_buf_len: 4194304 bytes
>[    0.000000] early log buf free: 257472(98%)
>[    0.000000] Secure boot could not be determined
>[    0.000000] RAMDISK: [mem 0x331ca000-0x358dcfff]
>[    0.000000] ACPI: Early table checksum verification disabled
>[    0.000000] ACPI: RSDP 0x000000008CC0E014 000024 (v02 INTEL )
>[    0.000000] ACPI: XSDT 0x000000008CBA1188 0000EC (v01 INTEL  CFL      20170001 INTL 20160422)
>[    0.000000] ACPI: FACP 0x000000008CC04000 000114 (v06 INTEL  CFL      20170001 INTL 20160422)
>[    0.000000] ACPI: DSDT 0x000000008CBB6000 04A663 (v02 INTEL  CFL      20170001 INTL 20160422)
>[    0.000000] ACPI: FACS 0x000000008C9F7000 000040
>[    0.000000] ACPI: SSDT 0x000000008CC0B000 0017CB (v02 CpuRef CpuSsdt  00003000 INTL 20160422)
>[    0.000000] ACPI: SSDT 0x000000008CC07000 003229 (v02 SaSsdt SaSsdt   00003000 INTL 20160422)
>[    0.000000] ACPI: UEFI 0x000000008CA09000 000042 (v01 INTEL  CFL      20170001 INTL 20160422)
>[    0.000000] ACPI: SSDT 0x000000008CC06000 0005B6 (v02 Intel  PerfTune 00001000 INTL 20160422)
>[    0.000000] ACPI: ECDT 0x000000008CC05000 000069 (v01 INTEL  CFL      20170001 INTL 20160422)
>[    0.000000] ACPI: HPET 0x000000008CC03000 000038 (v01 INTEL  CFL      20170001 INTL 20160422)
>[    0.000000] ACPI: APIC 0x000000008CC02000 00012C (v03 INTEL  CFL      20170001 INTL 20160422)
>[    0.000000] ACPI: MCFG 0x000000008CC01000 00003C (v01 INTEL  CFL      20170001 INTL 20160422)
>[    0.000000] ACPI: SSDT 0x000000008CBB3000 002958 (v02 INTEL  CflS_Rvp 00001000 INTL 20160422)
>[    0.000000] ACPI: SSDT 0x000000008CBB1000 0011B1 (v02 INTEL  Ther_Rvp 00001000 INTL 20160422)
>[    0.000000] ACPI: SSDT 0x000000008CBAF000 00137A (v02 INTEL  xh_cfsd4 00000000 INTL 20160422)
>[    0.000000] ACPI: BOOT 0x000000008CBAE000 000028 (v01 INTEL  TIANO    00000002 MSFT 01000013)
>[    0.000000] ACPI: SSDT 0x000000008CBAC000 00198A (v02 INTEL  UsbCTabl 00001000 INTL 20160422)
>[    0.000000] ACPI: LPIT 0x000000008CBAB000 000094 (v01 INTEL  CFL      20170001 INTL 20160422)
>[    0.000000] ACPI: WSMT 0x000000008CBAA000 000028 (v01 INTEL  CFL      20170001 INTL 20160422)
>[    0.000000] ACPI: SSDT 0x000000008CBA7000 002815 (v02 INTEL  PtidDevc 00001000 INTL 20160422)
>[    0.000000] ACPI: SSDT 0x000000008CBA6000 000FBB (v02 INTEL  TbtTypeC 00000000 INTL 20160422)
>[    0.000000] ACPI: DBGP 0x000000008CBA5000 000034 (v01 INTEL  CFL      20170001 INTL 20160422)
>[    0.000000] ACPI: DBG2 0x000000008CBA4000 000054 (v00 INTEL  CFL      20170001 INTL 20160422)
>[    0.000000] ACPI: NHLT 0x000000008CBA2000 001783 (v00 INTEL  CFL      00000002      01000013)
>[    0.000000] ACPI: DMAR 0x000000008CC0D000 000114 (v01 INTEL  CFL      00000002      01000013)
>[    0.000000] ACPI: FPDT 0x000000008CBA0000 000044 (v01 INTEL  CFL      20170001 INTL 20160422)
>[    0.000000] ACPI: ASF! 0x000000008CB9F000 0000A0 (v32 INTEL   HCG     00000001 TFSM 000F4240)
>[    0.000000] ACPI: BGRT 0x000000008CB9E000 000038 (v01 INTEL  CFL      20170001 INTL 20160422)
>[    0.000000] ACPI: Local APIC address 0xfee00000
>[    0.000000] No NUMA configuration found
>[    0.000000] Faking a node at [mem 0x0000000000000000-0x000000046dffffff]
>[    0.000000] NODE_DATA(0) allocated [mem 0x46dbfb000-0x46dbfffff]
>[    0.000000] Zone ranges:
>[    0.000000]   DMA      [mem 0x0000000000001000-0x0000000000ffffff]
>[    0.000000]   DMA32    [mem 0x0000000001000000-0x00000000ffffffff]
>[    0.000000]   Normal   [mem 0x0000000100000000-0x000000046dffffff]
>[    0.000000]   Device   empty
>[    0.000000] Movable zone start for each node
>[    0.000000] Early memory node ranges
>[    0.000000]   node   0: [mem 0x0000000000001000-0x000000000009efff]
>[    0.000000]   node   0: [mem 0x0000000000100000-0x000000008c2e3fff]
>[    0.000000]   node   0: [mem 0x000000008cc0f000-0x000000008cc0ffff]
>[    0.000000]   node   0: [mem 0x0000000100000000-0x000000046dffffff]
>[    0.000000] Initmem setup node 0 [mem 0x0000000000001000-0x000000046dffffff]
>[    0.000000] On node 0 totalpages: 4170371
>[    0.000000]   DMA zone: 64 pages used for memmap
>[    0.000000]   DMA zone: 27 pages reserved
>[    0.000000]   DMA zone: 3998 pages, LIFO batch:0
>[    0.000000]   DMA32 zone: 8908 pages used for memmap
>[    0.000000]   DMA32 zone: 570085 pages, LIFO batch:31
>[    0.000000]   Normal zone: 56192 pages used for memmap
>[    0.000000]   Normal zone: 3596288 pages, LIFO batch:31
>[    0.000000] Reserved but unavailable: 98 pages
>[    0.000000] ACPI: PM-Timer IO Port: 0x1808
>[    0.000000] ACPI: Local APIC address 0xfee00000
>[    0.000000] ACPI: LAPIC_NMI (acpi_id[0x01] high edge lint[0x1])
>[    0.000000] ACPI: LAPIC_NMI (acpi_id[0x02] high edge lint[0x1])
>[    0.000000] ACPI: LAPIC_NMI (acpi_id[0x03] high edge lint[0x1])
>[    0.000000] ACPI: LAPIC_NMI (acpi_id[0x04] high edge lint[0x1])
>[    0.000000] ACPI: LAPIC_NMI (acpi_id[0x05] high edge lint[0x1])
>[    0.000000] ACPI: LAPIC_NMI (acpi_id[0x06] high edge lint[0x1])
>[    0.000000] ACPI: LAPIC_NMI (acpi_id[0x07] high edge lint[0x1])
>[    0.000000] ACPI: LAPIC_NMI (acpi_id[0x08] high edge lint[0x1])
>[    0.000000] ACPI: LAPIC_NMI (acpi_id[0x09] high edge lint[0x1])
>[    0.000000] ACPI: LAPIC_NMI (acpi_id[0x0a] high edge lint[0x1])
>[    0.000000] ACPI: LAPIC_NMI (acpi_id[0x0b] high edge lint[0x1])
>[    0.000000] ACPI: LAPIC_NMI (acpi_id[0x0c] high edge lint[0x1])
>[    0.000000] ACPI: LAPIC_NMI (acpi_id[0x0d] high edge lint[0x1])
>[    0.000000] ACPI: LAPIC_NMI (acpi_id[0x0e] high edge lint[0x1])
>[    0.000000] ACPI: LAPIC_NMI (acpi_id[0x0f] high edge lint[0x1])
>[    0.000000] ACPI: LAPIC_NMI (acpi_id[0x10] high edge lint[0x1])
>[    0.000000] IOAPIC[0]: apic_id 2, version 32, address 0xfec00000, GSI 0-119
>[    0.000000] ACPI: INT_SRC_OVR (bus 0 bus_irq 0 global_irq 2 dfl dfl)
>[    0.000000] ACPI: INT_SRC_OVR (bus 0 bus_irq 9 global_irq 9 high level)
>[    0.000000] ACPI: IRQ0 used by override.
>[    0.000000] ACPI: IRQ9 used by override.
>[    0.000000] Using ACPI (MADT) for SMP configuration information
>[    0.000000] ACPI: HPET id: 0x8086a201 base: 0xfed00000
>[    0.000000] smpboot: Allowing 12 CPUs, 0 hotplug CPUs
>[    0.000000] PM: Registered nosave memory: [mem 0x00000000-0x00000fff]
>[    0.000000] PM: Registered nosave memory: [mem 0x0009f000-0x000fffff]
>[    0.000000] PM: Registered nosave memory: [mem 0x8c2e4000-0x8c308fff]
>[    0.000000] PM: Registered nosave memory: [mem 0x8c309000-0x8c991fff]
>[    0.000000] PM: Registered nosave memory: [mem 0x8c992000-0x8cb81fff]
>[    0.000000] PM: Registered nosave memory: [mem 0x8cb82000-0x8cc0efff]
>[    0.000000] PM: Registered nosave memory: [mem 0x8cc10000-0x8fffffff]
>[    0.000000] PM: Registered nosave memory: [mem 0x90000000-0xfe00ffff]
>[    0.000000] PM: Registered nosave memory: [mem 0xfe010000-0xfe010fff]
>[    0.000000] PM: Registered nosave memory: [mem 0xfe011000-0xff5fffff]
>[    0.000000] PM: Registered nosave memory: [mem 0xff600000-0xffffffff]
>[    0.000000] e820: [mem 0x90000000-0xfe00ffff] available for PCI devices
>[    0.000000] Booting paravirtualized kernel on bare hardware
>[    0.000000] clocksource: refined-jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645519600211568 ns
>[    0.000000] setup_percpu: NR_CPUS:256 nr_cpumask_bits:256 nr_cpu_ids:12 nr_node_ids:1
>[    0.000000] percpu: Embedded 39 pages/cpu @ffff983ddce00000 s119064 r8192 d32488 u262144
>[    0.000000] pcpu-alloc: s119064 r8192 d32488 u262144 alloc=1*2097152
>[    0.000000] pcpu-alloc: [0] 00 01 02 03 04 05 06 07 [0] 08 09 10 11 -- -- -- -- 
>[    0.000000] Built 1 zonelists, mobility grouping on.  Total pages: 4105180
>[    0.000000] Policy zone: Normal
>[    0.000000] Kernel command line: BOOT_IMAGE=/boot/vmlinuz-4.15.0-rc1-drm-tip-ww48-commit-4faecf8+ root=UUID=2a8388ef-fcb0-4ae0-964a-bd124748729c ro quiet drm.debug=0xe pci=pcie_bus_safe intel_iommu=igfx_off i915.alpha_support=1 auto i915.enable_guc_loading=1 i915.enable_guc_submission=1 panic=1 nmi_watchdog=panic log_buf_len=4M resume=/dev/nvme0n1p3 fastboot
>[    0.000000] DMAR: Disable GFX device mapping
>[    0.000000] Calgary: detecting Calgary via BIOS EBDA area
>[    0.000000] Calgary: Unable to locate Rio Grande table in EBDA - bailing!
>[    0.000000] Memory: 16223876K/16681484K available (8969K kernel code, 1488K rwdata, 3844K rodata, 1620K init, 1164K bss, 457608K reserved, 0K cma-reserved)
>[    0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=12, Nodes=1
>[    0.000000] ftrace: allocating 37599 entries in 147 pages
>[    0.000000] Hierarchical RCU implementation.
>[    0.000000] 	RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=12.
>[    0.000000] 	Tasks RCU enabled.
>[    0.000000] RCU: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=12
>[    0.000000] NR_IRQS: 16640, nr_irqs: 2152, preallocated irqs: 16
>[    0.000000] Console: colour dummy device 80x25
>[    0.000000] console [tty0] enabled
>[    0.000000] clocksource: hpet: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 79635855245 ns
>[    0.000000] hpet clockevent registered
>[    0.004000] tsc: Detected 3600.000 MHz processor
>[    0.004000] Calibrating delay loop (skipped), value calculated using timer frequency.. 7200.00 BogoMIPS (lpj=14400000)
>[    0.004000] pid_max: default: 32768 minimum: 301
>[    0.004000] ACPI: Core revision 20170831
>[    0.031841] ACPI: 10 ACPI AML tables successfully acquired and loaded
>[    0.032230] Security Framework initialized
>[    0.032231] Yama: becoming mindful.
>[    0.032242] AppArmor: AppArmor initialized
>[    0.033592] Dentry cache hash table entries: 2097152 (order: 12, 16777216 bytes)
>[    0.034263] Inode-cache hash table entries: 1048576 (order: 11, 8388608 bytes)
>[    0.034289] Mount-cache hash table entries: 32768 (order: 6, 262144 bytes)
>[    0.034309] Mountpoint-cache hash table entries: 32768 (order: 6, 262144 bytes)
>[    0.034443] CPU: Physical Processor ID: 0
>[    0.034443] CPU: Processor Core ID: 0
>[    0.034446] ENERGY_PERF_BIAS: Set to 'normal', was 'performance'
>[    0.034447] ENERGY_PERF_BIAS: View and update with x86_energy_perf_policy(8)
>[    0.034450] mce: CPU supports 12 MCE banks
>[    0.034457] CPU0: Thermal monitoring enabled (TM1)
>[    0.034474] process: using mwait in idle threads
>[    0.034475] Last level iTLB entries: 4KB 64, 2MB 8, 4MB 8
>[    0.034476] Last level dTLB entries: 4KB 64, 2MB 0, 4MB 0, 1GB 4
>[    0.034581] Freeing SMP alternatives memory: 36K
>[    0.037005] DMAR: Host address width 39
>[    0.037006] DMAR: DRHD base: 0x000000fed90000 flags: 0x0
>[    0.037011] DMAR: dmar0: reg_base_addr fed90000 ver 1:0 cap 1c0000c40660462 ecap 19e2ff0505e
>[    0.037011] DMAR: DRHD base: 0x000000fed91000 flags: 0x1
>[    0.037013] DMAR: dmar1: reg_base_addr fed91000 ver 1:0 cap d2008c40660462 ecap f050da
>[    0.037014] DMAR: RMRR base: 0x0000008c93c000 end: 0x0000008c95bfff
>[    0.037015] DMAR: RMRR base: 0x0000008d800000 end: 0x0000008fffffff
>[    0.037016] DMAR: ANDD device: 1 name: \_SB.PCI0.I2C0
>[    0.037016] DMAR: ANDD device: 2 name: \_SB.PCI0.I2C1
>[    0.037016] DMAR: ANDD device: a name: \_SB.PCI0.UA00
>[    0.037017] DMAR-IR: IOAPIC id 2 under DRHD base  0xfed91000 IOMMU 1
>[    0.037018] DMAR-IR: HPET id 0 under DRHD base 0xfed91000
>[    0.037018] DMAR-IR: Queued invalidation will be enabled to support x2apic and Intr-remapping.
>[    0.041823] DMAR-IR: Enabled IRQ remapping in x2apic mode
>[    0.041823] x2apic enabled
>[    0.041845] Switched APIC routing to cluster x2apic.
>[    0.051240] ..TIMER: vector=0x30 apic1=0 pin1=2 apic2=-1 pin2=-1
>[    0.090981] TSC deadline timer enabled
>[    0.090993] smpboot: CPU0: Genuine Intel(R) CPU 0000 @ 3.60GHz (family: 0x6, model: 0x9e, stepping: 0xa)
>[    0.091032] Performance Events: PEBS fmt3+, Skylake events, 32-deep LBR, full-width counters, Intel PMU driver.
>[    0.091052] ... version:                4
>[    0.091052] ... bit width:              48
>[    0.091052] ... generic registers:      4
>[    0.091053] ... value mask:             0000ffffffffffff
>[    0.091053] ... max period:             00007fffffffffff
>[    0.091053] ... fixed-purpose events:   3
>[    0.091054] ... event mask:             000000070000000f
>[    0.091078] Hierarchical SRCU implementation.
>[    0.091655] NMI watchdog: Enabled. Permanently consumes one hw-PMU counter.
>[    0.091663] smp: Bringing up secondary CPUs ...
>[    0.091701] x86: Booting SMP configuration:
>[    0.091701] .... node  #0, CPUs:        #1  #2  #3  #4  #5  #6  #7  #8  #9 #10 #11
>[    0.092457] smp: Brought up 1 node, 12 CPUs
>[    0.092457] smpboot: Max logical packages: 1
>[    0.092457] smpboot: Total of 12 processors activated (86400.00 BogoMIPS)
>[    0.096338] devtmpfs: initialized
>[    0.096338] x86/mm: Memory block size: 128MB
>[    0.096723] evm: security.selinux
>[    0.096723] evm: security.SMACK64
>[    0.096724] evm: security.SMACK64EXEC
>[    0.096724] evm: security.SMACK64TRANSMUTE
>[    0.096724] evm: security.SMACK64MMAP
>[    0.096724] evm: security.apparmor
>[    0.096725] evm: security.ima
>[    0.096725] evm: security.capability
>[    0.096734] PM: Registering ACPI NVS region [mem 0x8c992000-0x8cb81fff] (2031616 bytes)
>[    0.096734] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
>[    0.096734] futex hash table entries: 4096 (order: 6, 262144 bytes)
>[    0.096734] pinctrl core: initialized pinctrl subsystem
>[    0.096734] RTC time: 16:28:36, date: 12/01/17
>[    0.096734] NET: Registered protocol family 16
>[    0.096734] audit: initializing netlink subsys (disabled)
>[    0.096734] audit: type=2000 audit(1512145716.096:1): state=initialized audit_enabled=0 res=1
>[    0.096734] cpuidle: using governor ladder
>[    0.096734] cpuidle: using governor menu
>[    0.096734] Simple Boot Flag at 0x47 set to 0x1
>[    0.096734] ACPI: bus type PCI registered
>[    0.096734] acpiphp: ACPI Hot Plug PCI Controller Driver version: 0.5
>[    0.096734] PCI: MMCONFIG for domain 0000 [bus 00-ff] at [mem 0xe0000000-0xefffffff] (base 0xe0000000)
>[    0.096734] PCI: not using MMCONFIG
>[    0.096734] PCI: Using configuration type 1 for base access
>[    0.096779] HugeTLB registered 1.00 GiB page size, pre-allocated 0 pages
>[    0.096779] HugeTLB registered 2.00 MiB page size, pre-allocated 0 pages
>[    0.096780] ACPI: Added _OSI(Module Device)
>[    0.096780] ACPI: Added _OSI(Processor Device)
>[    0.096780] ACPI: Added _OSI(3.0 _SCP Extensions)
>[    0.096780] ACPI: Added _OSI(Processor Aggregator Device)
>[    0.096780] ACPI: EC: EC started
>[    0.096780] ACPI: EC: interrupt blocked
>[    0.227662] ACPI: \: Used as first EC
>[    0.227663] ACPI: \: GPE=0x6e, EC_CMD/EC_SC=0x66, EC_DATA=0x62
>[    0.227664] ACPI: \: Used as boot ECDT EC to handle transactions
>[    0.238676] ACPI Error: [SLOT] Namespace lookup failure, AE_ALREADY_EXISTS (20170831/dswload2-346)
>[    0.238676] ACPI Exception: AE_ALREADY_EXISTS, During name lookup/catalog (20170831/psobject-252)
>[    0.238676] ACPI Error: Method parse/execution failed \, AE_ALREADY_EXISTS (20170831/psparse-550)
>[    0.238676] ACPI: Marking method \___ as Serialized because of AE_ALREADY_EXISTS error
>[    0.238676] ACPI Error: [_INI] Namespace lookup failure, AE_ALREADY_EXISTS (20170831/dswload2-346)
>[    0.238676] ACPI Exception: AE_ALREADY_EXISTS, During name lookup/catalog (20170831/psobject-252)
>[    0.238676] ACPI Error: Method parse/execution failed \, AE_ALREADY_EXISTS (20170831/psparse-550)
>[    0.238676] ACPI: Marking method \___ as Serialized because of AE_ALREADY_EXISTS error
>[    0.238676] ACPI: Executed 61 blocks of module-level executable AML code
>[    0.314153] ACPI: Dynamic OEM Table Load:
>[    0.314153] ACPI: SSDT 0xFFFF983DDA75F800 00078C (v02 PmRef  Cpu0Ist  00003000 INTL 20160422)
>[    0.314153] ACPI: Executed 1 blocks of module-level executable AML code
>[    0.314153] ACPI: \_SB_.PR00: _OSC native thermal LVT Acked
>[    0.314153] ACPI: Dynamic OEM Table Load:
>[    0.314153] ACPI: SSDT 0xFFFF983DDA004000 00046F (v02 PmRef  Cpu0Cst  00003001 INTL 20160422)
>[    0.314153] ACPI: Executed 1 blocks of module-level executable AML code
>[    0.314153] ACPI: Dynamic OEM Table Load:
>[    0.314153] ACPI: SSDT 0xFFFF983DD9C0BC00 00011B (v02 PmRef  Cpu0Hwp  00003000 INTL 20160422)
>[    0.314153] ACPI: Executed 1 blocks of module-level executable AML code
>[    0.314153] ACPI: Dynamic OEM Table Load:
>[    0.314153] ACPI: SSDT 0xFFFF983DDA006800 000724 (v02 PmRef  HwpLvt   00003000 INTL 20160422)
>[    0.314153] ACPI: Executed 1 blocks of module-level executable AML code
>[    0.316222] ACPI: Dynamic OEM Table Load:
>[    0.316229] ACPI: SSDT 0xFFFF983DDA061000 000EF1 (v02 PmRef  ApIst    00003000 INTL 20160422)
>[    0.316659] ACPI: Executed 1 blocks of module-level executable AML code
>[    0.316666] ACPI: Dynamic OEM Table Load:
>[    0.316666] ACPI: SSDT 0xFFFF983DDA255C00 000317 (v02 PmRef  ApHwp    00003000 INTL 20160422)
>[    0.316666] ACPI: Executed 1 blocks of module-level executable AML code
>[    0.316666] ACPI: Dynamic OEM Table Load:
>[    0.316666] ACPI: SSDT 0xFFFF983DDA278C00 00030A (v02 PmRef  ApCst    00003000 INTL 20160422)
>[    0.316666] ACPI: Executed 1 blocks of module-level executable AML code
>[    0.316666] ACPI: Interpreter enabled
>[    0.316666] ACPI: (supports S0 S3 S4 S5)
>[    0.316666] ACPI: Using IOAPIC for interrupt routing
>[    0.316666] PCI: MMCONFIG for domain 0000 [bus 00-ff] at [mem 0xe0000000-0xefffffff] (base 0xe0000000)
>[    0.318946] PCI: MMCONFIG at [mem 0xe0000000-0xefffffff] reserved in ACPI motherboard resources
>[    0.318955] PCI: Using host bridge windows from ACPI; if necessary, use "pci=nocrs" and report a bug
>[    0.320000] ACPI: Enabled 6 GPEs in block 00 to 7F
>[    0.331807] ACPI: Power Resource [BTPR] (on)
>[    0.332479] ACPI: Power Resource [USBC] (on)
>[    0.332585] ACPI: Power Resource [PAUD] (on)
>[    0.342556] ACPI: Power Resource [V0PR] (on)
>[    0.342677] ACPI: Power Resource [V1PR] (on)
>[    0.342796] ACPI: Power Resource [V2PR] (on)
>[    0.355848] acpi ABCD0000:00: ACPI dock station (docks/bays count: 1)
>[    0.359497] ACPI: Power Resource [FN00] (off)
>[    0.359547] ACPI: Power Resource [FN01] (off)
>[    0.359594] ACPI: Power Resource [FN02] (off)
>[    0.359644] ACPI: Power Resource [FN03] (off)
>[    0.359691] ACPI: Power Resource [FN04] (off)
>[    0.360320] ACPI: PCI Root Bridge [PCI0] (domain 0000 [bus 00-fe])
>[    0.360324] acpi PNP0A08:00: _OSC: OS supports [ExtendedConfig ASPM ClockPM Segments MSI]
>[    0.365410] acpi PNP0A08:00: _OSC: OS now controls [PCIeHotplug PME AER PCIeCapability]
>[    0.367585] PCI host bridge to bus 0000:00
>[    0.367586] pci_bus 0000:00: root bus resource [io  0x0000-0x0cf7 window]
>[    0.367587] pci_bus 0000:00: root bus resource [io  0x0d00-0xffff window]
>[    0.367588] pci_bus 0000:00: root bus resource [mem 0x000a0000-0x000bffff window]
>[    0.367588] pci_bus 0000:00: root bus resource [mem 0x90000000-0xdfffffff window]
>[    0.367589] pci_bus 0000:00: root bus resource [mem 0xfc800000-0xfe7fffff window]
>[    0.367590] pci_bus 0000:00: root bus resource [bus 00-fe]
>[    0.367594] pci 0000:00:00.0: [8086:3ec2] type 00 class 0x060000
>[    0.368398] pci 0000:00:02.0: [8086:3e92] type 00 class 0x030000
>[    0.368405] pci 0000:00:02.0: reg 0x10: [mem 0xb0000000-0xb0ffffff 64bit]
>[    0.368409] pci 0000:00:02.0: reg 0x18: [mem 0xa0000000-0xafffffff 64bit pref]
>[    0.368411] pci 0000:00:02.0: reg 0x20: [io  0x3000-0x303f]
>[    0.368421] pci 0000:00:02.0: BAR 2: assigned to efifb
>[    0.369102] pci 0000:00:08.0: [8086:1911] type 00 class 0x088000
>[    0.369111] pci 0000:00:08.0: reg 0x10: [mem 0xb123c000-0xb123cfff 64bit]
>[    0.369845] pci 0000:00:12.0: [8086:a379] type 00 class 0x118000
>[    0.369896] pci 0000:00:12.0: reg 0x10: [mem 0xb123d000-0xb123dfff 64bit]
>[    0.370762] pci 0000:00:14.0: [8086:a36d] type 00 class 0x0c0330
>[    0.370810] pci 0000:00:14.0: reg 0x10: [mem 0xb1220000-0xb122ffff 64bit]
>[    0.370961] pci 0000:00:14.0: PME# supported from D3hot D3cold
>[    0.371658] pci 0000:00:14.2: [8086:a36f] type 00 class 0x050000
>[    0.371697] pci 0000:00:14.2: reg 0x10: [mem 0xb1238000-0xb1239fff 64bit]
>[    0.371718] pci 0000:00:14.2: reg 0x18: [mem 0xb123e000-0xb123efff 64bit]
>[    0.372487] pci 0000:00:14.3: [8086:a370] type 00 class 0x028000
>[    0.372656] pci 0000:00:14.3: reg 0x10: [mem 0xb1230000-0xb1233fff 64bit]
>[    0.373217] pci 0000:00:14.3: PME# supported from D0 D3hot D3cold
>[    0.374260] pci 0000:00:15.0: [8086:a368] type 00 class 0x0c8000
>[    0.374988] pci 0000:00:15.0: reg 0x10: [mem 0xb123f000-0xb123ffff 64bit]
>[    0.377964] pci 0000:00:15.1: [8086:a369] type 00 class 0x0c8000
>[    0.378692] pci 0000:00:15.1: reg 0x10: [mem 0xb1240000-0xb1240fff 64bit]
>[    0.381470] pci 0000:00:16.0: [8086:a360] type 00 class 0x078000
>[    0.381516] pci 0000:00:16.0: reg 0x10: [mem 0xb1241000-0xb1241fff 64bit]
>[    0.381645] pci 0000:00:16.0: PME# supported from D3hot
>[    0.382441] pci 0000:00:17.0: [8086:a352] type 00 class 0x010601
>[    0.382504] pci 0000:00:17.0: reg 0x10: [mem 0xb123a000-0xb123bfff]
>[    0.382530] pci 0000:00:17.0: reg 0x14: [mem 0xb1246000-0xb12460ff]
>[    0.382554] pci 0000:00:17.0: reg 0x18: [io  0x3080-0x3087]
>[    0.382581] pci 0000:00:17.0: reg 0x1c: [io  0x3088-0x308b]
>[    0.382606] pci 0000:00:17.0: reg 0x20: [io  0x3060-0x307f]
>[    0.382631] pci 0000:00:17.0: reg 0x24: [mem 0xb1245000-0xb12457ff]
>[    0.382772] pci 0000:00:17.0: PME# supported from D3hot
>[    0.383468] pci 0000:00:1b.0: [8086:a340] type 01 class 0x060400
>[    0.383658] pci 0000:00:1b.0: PME# supported from D0 D3hot D3cold
>[    0.384703] pci 0000:00:1e.0: [8086:a328] type 00 class 0x078000
>[    0.385432] pci 0000:00:1e.0: reg 0x10: [mem 0xb1242000-0xb1242fff 64bit]
>[    0.388248] pci 0000:00:1f.0: [8086:a306] type 00 class 0x060100
>[    0.389062] pci 0000:00:1f.3: [8086:a348] type 00 class 0x040100
>[    0.389110] pci 0000:00:1f.3: reg 0x10: [mem 0xb1234000-0xb1237fff 64bit]
>[    0.389183] pci 0000:00:1f.3: reg 0x20: [mem 0xb1000000-0xb10fffff 64bit]
>[    0.389321] pci 0000:00:1f.3: PME# supported from D3hot D3cold
>[    0.390093] pci 0000:00:1f.4: [8086:a323] type 00 class 0x0c0500
>[    0.390264] pci 0000:00:1f.4: reg 0x10: [mem 0xb1243000-0xb12430ff 64bit]
>[    0.390414] pci 0000:00:1f.4: reg 0x20: [io  0xefa0-0xefbf]
>[    0.391241] pci 0000:00:1f.5: [8086:a324] type 00 class 0x0c8000
>[    0.391269] pci 0000:00:1f.5: reg 0x10: [mem 0xfe010000-0xfe010fff]
>[    0.392012] pci 0000:00:1f.6: [8086:15bc] type 00 class 0x020000
>[    0.392069] pci 0000:00:1f.6: reg 0x10: [mem 0xb1200000-0xb121ffff]
>[    0.392285] pci 0000:00:1f.6: PME# supported from D0 D3hot D3cold
>[    0.393075] pci 0000:01:00.0: [8086:f1a5] type 00 class 0x010802
>[    0.393127] pci 0000:01:00.0: reg 0x10: [mem 0xb1100000-0xb1103fff 64bit]
>[    0.404266] pci 0000:00:1b.0: PCI bridge to [bus 01]
>[    0.404276] pci 0000:00:1b.0:   bridge window [mem 0xb1100000-0xb11fffff]
>[    0.404311] pci 0000:00:1b.0: Max Payload Size set to  128/ 256 (was  128), Max Read Rq  128
>[    0.404367] pci 0000:01:00.0: Max Payload Size set to  128/ 128 (was  128), Max Read Rq  512
>[    0.406108] ACPI: PCI Interrupt Link [LNKA] (IRQs 3 4 5 6 10 11 12 14 *15), disabled.
>[    0.406165] ACPI: PCI Interrupt Link [LNKB] (IRQs 3 4 5 6 10 11 12 14 *15), disabled.
>[    0.406224] ACPI: PCI Interrupt Link [LNKC] (IRQs 3 4 5 6 10 11 12 14 *15), disabled.
>[    0.406282] ACPI: PCI Interrupt Link [LNKD] (IRQs 3 4 5 6 10 11 12 14 *15), disabled.
>[    0.406339] ACPI: PCI Interrupt Link [LNKE] (IRQs 3 4 5 6 10 11 12 14 *15), disabled.
>[    0.406396] ACPI: PCI Interrupt Link [LNKF] (IRQs 3 4 5 6 10 11 12 14 *15), disabled.
>[    0.406454] ACPI: PCI Interrupt Link [LNKG] (IRQs 3 4 5 6 10 11 12 14 *15), disabled.
>[    0.406513] ACPI: PCI Interrupt Link [LNKH] (IRQs 3 4 5 6 10 11 12 14 *15), disabled.
>[    0.407028] ACPI: EC: interrupt unblocked
>[    0.407050] ACPI: EC: event unblocked
>[    0.407096] ACPI: \_SB_.PCI0.LPCB.H_EC: GPE=0x6e, EC_CMD/EC_SC=0x66, EC_DATA=0x62
>[    0.407096] ACPI: \_SB_.PCI0.LPCB.H_EC: Used as boot DSDT EC to handle transactions and events
>[    0.407145] pci 0000:00:02.0: vgaarb: setting as boot VGA device
>[    0.407145] pci 0000:00:02.0: vgaarb: VGA device added: decodes=io+mem,owns=io+mem,locks=none
>[    0.407145] pci 0000:00:02.0: vgaarb: bridge control possible
>[    0.407145] vgaarb: loaded
>[    0.407145] SCSI subsystem initialized
>[    0.407145] libata version 3.00 loaded.
>[    0.407145] ACPI: bus type USB registered
>[    0.407145] usbcore: registered new interface driver usbfs
>[    0.407145] usbcore: registered new interface driver hub
>[    0.407145] usbcore: registered new device driver usb
>[    0.407145] EDAC MC: Ver: 3.0.0
>[    0.407145] Registered efivars operations
>[    0.415528] PCI: Using ACPI for IRQ routing
>[    0.498304] PCI: pci_cache_line_size set to 64 bytes
>[    0.498893] e820: reserve RAM buffer [mem 0x0009f000-0x0009ffff]
>[    0.498893] e820: reserve RAM buffer [mem 0x8c2e4000-0x8fffffff]
>[    0.498894] e820: reserve RAM buffer [mem 0x8cc10000-0x8fffffff]
>[    0.498894] e820: reserve RAM buffer [mem 0x46e000000-0x46fffffff]
>[    0.498944] NetLabel: Initializing
>[    0.498944] NetLabel:  domain hash size = 128
>[    0.498944] NetLabel:  protocols = UNLABELED CIPSOv4 CALIPSO
>[    0.498952] NetLabel:  unlabeled traffic allowed by default
>[    0.500161] hpet0: at MMIO 0xfed00000, IRQs 2, 8, 0, 0, 0, 0, 0, 0
>[    0.500164] hpet0: 8 comparators, 64-bit 24.000000 MHz counter
>[    0.504023] clocksource: Switched to clocksource hpet
>[    0.509947] VFS: Disk quotas dquot_6.6.0
>[    0.509957] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
>[    0.510020] AppArmor: AppArmor Filesystem Enabled
>[    0.510031] pnp: PnP ACPI init
>[    0.510230] system 00:00: [io  0x1800-0x18fe] has been reserved
>[    0.510232] system 00:00: [mem 0xfd000000-0xfd69ffff] has been reserved
>[    0.510232] system 00:00: [mem 0xfd6c0000-0xfd6cffff] has been reserved
>[    0.510233] system 00:00: [mem 0xfd6f0000-0xfdffffff] has been reserved
>[    0.510234] system 00:00: [mem 0xfe000000-0xfe01ffff] could not be reserved
>[    0.510235] system 00:00: [mem 0xfe200000-0xfe7fffff] has been reserved
>[    0.510237] system 00:00: Plug and Play ACPI device, IDs PNP0c02 (active)
>[    0.510420] system 00:01: [io  0x2000-0x20fe] has been reserved
>[    0.510422] system 00:01: Plug and Play ACPI device, IDs PNP0c02 (active)
>[    0.510527] system 00:02: [io  0x06a4] has been reserved
>[    0.510527] system 00:02: [io  0x06a0] has been reserved
>[    0.510529] system 00:02: Plug and Play ACPI device, IDs PNP0c02 (active)
>[    0.510649] system 00:03: [io  0x0680-0x069f] has been reserved
>[    0.510650] system 00:03: [io  0x164e-0x164f] has been reserved
>[    0.510651] system 00:03: Plug and Play ACPI device, IDs PNP0c02 (active)
>[    0.510662] pnp 00:04: Plug and Play ACPI device, IDs PNP0b00 (active)
>[    0.510715] system 00:05: [io  0x1854-0x1857] has been reserved
>[    0.510717] system 00:05: Plug and Play ACPI device, IDs INT3f0d PNP0c02 (active)
>[    0.510784] pnp 00:06: Plug and Play ACPI device, IDs PNP0501 (active)
>[    0.510817] pnp 00:07: Plug and Play ACPI device, IDs PNP0303 (active)
>[    0.511453] system 00:08: Plug and Play ACPI device, IDs PNP0c02 (active)
>[    0.512140] system 00:09: [mem 0xfed10000-0xfed17fff] has been reserved
>[    0.512141] system 00:09: [mem 0xfed18000-0xfed18fff] has been reserved
>[    0.512142] system 00:09: [mem 0xfed19000-0xfed19fff] has been reserved
>[    0.512143] system 00:09: [mem 0xe0000000-0xefffffff] has been reserved
>[    0.512143] system 00:09: [mem 0xfed20000-0xfed3ffff] has been reserved
>[    0.512144] system 00:09: [mem 0xfed90000-0xfed93fff] could not be reserved
>[    0.512145] system 00:09: [mem 0xfed45000-0xfed8ffff] has been reserved
>[    0.512145] system 00:09: [mem 0xff000000-0xffffffff] could not be reserved
>[    0.512146] system 00:09: [mem 0xfee00000-0xfeefffff] has been reserved
>[    0.512148] system 00:09: Plug and Play ACPI device, IDs PNP0c02 (active)
>[    0.512497] system 00:0a: [mem 0x00000000-0x0009cfff] could not be reserved
>[    0.512499] system 00:0a: Plug and Play ACPI device, IDs PNP0c01 (active)
>[    0.512583] pnp: PnP ACPI: found 11 devices
>[    0.523354] clocksource: acpi_pm: mask: 0xffffff max_cycles: 0xffffff, max_idle_ns: 2085701024 ns
>[    0.523385] pci 0000:00:1b.0: PCI bridge to [bus 01]
>[    0.523393] pci 0000:00:1b.0:   bridge window [mem 0xb1100000-0xb11fffff]
>[    0.523407] pci_bus 0000:00: resource 4 [io  0x0000-0x0cf7 window]
>[    0.523408] pci_bus 0000:00: resource 5 [io  0x0d00-0xffff window]
>[    0.523409] pci_bus 0000:00: resource 6 [mem 0x000a0000-0x000bffff window]
>[    0.523409] pci_bus 0000:00: resource 7 [mem 0x90000000-0xdfffffff window]
>[    0.523410] pci_bus 0000:00: resource 8 [mem 0xfc800000-0xfe7fffff window]
>[    0.523411] pci_bus 0000:01: resource 1 [mem 0xb1100000-0xb11fffff]
>[    0.523549] NET: Registered protocol family 2
>[    0.523634] TCP established hash table entries: 131072 (order: 8, 1048576 bytes)
>[    0.523806] TCP bind hash table entries: 65536 (order: 8, 1048576 bytes)
>[    0.523875] TCP: Hash tables configured (established 131072 bind 65536)
>[    0.523899] UDP hash table entries: 8192 (order: 6, 262144 bytes)
>[    0.523924] UDP-Lite hash table entries: 8192 (order: 6, 262144 bytes)
>[    0.523968] NET: Registered protocol family 1
>[    0.523975] pci 0000:00:02.0: Video device with shadowed ROM at [mem 0x000c0000-0x000dffff]
>[    0.524298] PCI: CLS 0 bytes, default 64
>[    0.524316] Trying to unpack rootfs image as initramfs...
>[    0.962218] Freeing initrd memory: 40012K
>[    0.962256] DMAR: ACPI device "device:7f" under DMAR at fed91000 as 00:15.0
>[    0.962258] DMAR: ACPI device "device:80" under DMAR at fed91000 as 00:15.1
>[    0.962259] DMAR: ACPI device "device:81" under DMAR at fed91000 as 00:1e.0
>[    0.962269] PCI-DMA: Using software bounce buffering for IO (SWIOTLB)
>[    0.962270] software IO TLB [mem 0x8463e000-0x8863e000] (64MB) mapped at [ffff983a0463e000-ffff983a0863dfff]
>[    0.963009] clocksource: tsc: mask: 0xffffffffffffffff max_cycles: 0x33e452fbb2f, max_idle_ns: 440795236593 ns
>[    0.963679] Scanning for low memory corruption every 60 seconds
>[    0.964448] Initialise system trusted keyrings
>[    0.964453] Key type blacklist registered
>[    0.964599] workingset: timestamp_bits=40 max_order=22 bucket_order=0
>[    0.965162] zbud: loaded
>[    0.965401] squashfs: version 4.0 (2009/01/31) Phillip Lougher
>[    0.965637] fuse init (API version 7.26)
>[    0.965758] Allocating IMA blacklist keyring.
>[    0.971813] Key type asymmetric registered
>[    0.971813] Asymmetric key parser 'x509' registered
>[    0.971829] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 247)
>[    0.971969] io scheduler noop registered
>[    0.971970] io scheduler deadline registered (default)
>[    0.971991] io scheduler cfq registered
>[    0.971991] io scheduler mq-deadline registered (default)
>[    0.971992] io scheduler kyber registered
>[    0.973029] pcieport 0000:00:1b.0: AER enabled with IRQ 122
>[    0.973054] pcieport 0000:00:1b.0: Signaling PME with IRQ 122
>[    0.973073] dpc 0000:00:1b.0:pcie010: DPC error containment capabilities: Int Msg #0, RPExt+ PoisonedTLP+ SwTrigger+ RP PIO Log 4, DL_ActiveErr+
>[    0.973093] efifb: probing for efifb
>[    0.973101] efifb: framebuffer at 0xa0000000, using 8128k, total 8128k
>[    0.973101] efifb: mode is 1920x1080x32, linelength=7680, pages=1
>[    0.973101] efifb: scrolling: redraw
>[    0.973102] efifb: Truecolor: size=8:8:8:8, shift=24:16:8:0
>[    0.975635] Console: switching to colour frame buffer device 240x67
>[    0.978148] fb0: EFI VGA frame buffer device
>[    0.978153] intel_idle: MWAIT substates: 0x11142120
>[    0.978153] intel_idle: v0.4.1 model 0x9E
>[    0.979119] intel_idle: lapic_timer_reliable_states 0xffffffff
>[    0.979223] input: Power Button as /devices/LNXSYSTM:00/LNXSYBUS:00/PNP0C0C:00/input/input0
>[    0.979360] ACPI: Power Button [PWRB]
>[    0.979379] input: Sleep Button as /devices/LNXSYSTM:00/LNXSYBUS:00/PNP0C0E:00/input/input1
>[    0.979403] ACPI: Sleep Button [SLPB]
>[    0.979425] input: Power Button as /devices/LNXSYSTM:00/LNXPWRBN:00/input/input2
>[    0.979537] ACPI: Power Button [PWRF]
>[    1.044299] (NULL device *): hwmon_device_register() is deprecated. Please convert the driver to use hwmon_device_register_with_info().
>[    1.119459] thermal LNXTHERM:00: registered as thermal_zone0
>[    1.119460] ACPI: Thermal Zone [TZ00] (41 C)
>[    1.124970] thermal LNXTHERM:01: registered as thermal_zone1
>[    1.124971] ACPI: Thermal Zone [TZ01] (0 C)
>[    1.125265] Serial: 8250/16550 driver, 32 ports, IRQ sharing enabled
>[    1.147297] 00:06: ttyS0 at I/O 0x3f8 (irq = 4, base_baud = 115200) is a 16550A
>[    1.151925] Linux agpgart interface v0.103
>[    1.156164] brd: module loaded
>[    1.157863] loop: module loaded
>[    1.158270] nvme nvme0: pci function 0000:01:00.0
>[    1.158308] libphy: Fixed MDIO Bus: probed
>[    1.158308] tun: Universal TUN/TAP device driver, 1.6
>[    1.158626] PPP generic driver version 2.4.2
>[    1.158767] ehci_hcd: USB 2.0 'Enhanced' Host Controller (EHCI) Driver
>[    1.158768] ehci-pci: EHCI PCI platform driver
>[    1.158773] ehci-platform: EHCI generic platform driver
>[    1.158779] ohci_hcd: USB 1.1 'Open' Host Controller (OHCI) Driver
>[    1.158779] ohci-pci: OHCI PCI platform driver
>[    1.158784] ohci-platform: OHCI generic platform driver
>[    1.158787] uhci_hcd: USB Universal Host Controller Interface driver
>[    1.158901] xhci_hcd 0000:00:14.0: xHCI Host Controller
>[    1.158904] xhci_hcd 0000:00:14.0: new USB bus registered, assigned bus number 1
>[    1.160278] xhci_hcd 0000:00:14.0: hcc params 0x20007fc1 hci version 0x110 quirks 0x00009810
>[    1.160286] xhci_hcd 0000:00:14.0: cache line size of 64 is not supported
>[    1.160496] usb usb1: New USB device found, idVendor=1d6b, idProduct=0002
>[    1.160497] usb usb1: New USB device strings: Mfr=3, Product=2, SerialNumber=1
>[    1.160498] usb usb1: Product: xHCI Host Controller
>[    1.160499] usb usb1: Manufacturer: Linux 4.15.0-rc1-drm-tip-ww48-commit-4faecf8+ xhci-hcd
>[    1.160499] usb usb1: SerialNumber: 0000:00:14.0
>[    1.160619] hub 1-0:1.0: USB hub found
>[    1.160647] hub 1-0:1.0: 16 ports detected
>[    1.160675] ACPI Error: [\_SB_.UBTC.CR01._PLD] Namespace lookup failure, AE_NOT_FOUND (20170831/psargs-364)
>[    1.160700] ACPI Error: Method parse/execution failed \_SB.UBTC.RUCC, AE_NOT_FOUND (20170831/psparse-550)
>[    1.160722] ACPI Error: Method parse/execution failed \_SB.PCI0.XHC.RHUB.HS01._PLD, AE_NOT_FOUND (20170831/psparse-550)
>[    1.161932] xhci_hcd 0000:00:14.0: xHCI Host Controller
>[    1.161934] xhci_hcd 0000:00:14.0: new USB bus registered, assigned bus number 2
>[    1.161935] xhci_hcd 0000:00:14.0: Host supports USB 3.1 Enhanced SuperSpeed
>[    1.161961] usb usb2: New USB device found, idVendor=1d6b, idProduct=0003
>[    1.161962] usb usb2: New USB device strings: Mfr=3, Product=2, SerialNumber=1
>[    1.161962] usb usb2: Product: xHCI Host Controller
>[    1.161963] usb usb2: Manufacturer: Linux 4.15.0-rc1-drm-tip-ww48-commit-4faecf8+ xhci-hcd
>[    1.161963] usb usb2: SerialNumber: 0000:00:14.0
>[    1.162116] hub 2-0:1.0: USB hub found
>[    1.162150] hub 2-0:1.0: 10 ports detected
>[    1.162171] ACPI Error: [\_SB_.UBTC.CR01._PLD] Namespace lookup failure, AE_NOT_FOUND (20170831/psargs-364)
>[    1.162193] ACPI Error: Method parse/execution failed \_SB.UBTC.RUCC, AE_NOT_FOUND (20170831/psparse-550)
>[    1.162215] ACPI Error: Method parse/execution failed \_SB.PCI0.XHC.RHUB.SS01._PLD, AE_NOT_FOUND (20170831/psparse-550)
>[    1.163068] i8042: PNP: PS/2 Controller [PNP0303:PS2K] at 0x60,0x64 irq 1
>[    1.163068] i8042: PNP: PS/2 appears to have AUX port disabled, if this is incorrect please boot with i8042.nopnp
>[    1.163385] i8042: Warning: Keylock active
>[    1.163588] serio: i8042 KBD port at 0x60,0x64 irq 1
>[    1.163825] mousedev: PS/2 mouse device common for all mice
>[    1.164293] rtc_cmos 00:04: RTC can wake from S4
>[    1.165252] rtc_cmos 00:04: rtc core: registered rtc_cmos as rtc0
>[    1.165436] rtc_cmos 00:04: alarms up to one month, y3k, 242 bytes nvram, hpet irqs
>[    1.165460] i2c /dev entries driver
>[    1.165502] device-mapper: uevent: version 1.0.3
>[    1.165638] device-mapper: ioctl: 4.37.0-ioctl (2017-09-20) initialised: dm-devel@redhat.com
>[    1.165640] intel_pstate: Intel P-state driver initializing
>[    1.171299] intel_pstate: HWP enabled
>[    1.172608] ledtrig-cpu: registered to indicate activity on CPUs
>[    1.172615] EFI Variables Facility v0.08 2004-May-17
>[    1.184701] NET: Registered protocol family 10
>[    1.184997] Segment Routing with IPv6
>[    1.185005] NET: Registered protocol family 17
>[    1.185010] Key type dns_resolver registered
>[    1.186734] microcode: sig=0x906ea, pf=0x2, revision=0x70
>[    1.187628] microcode: Microcode Update Driver: v2.2.
>[    1.187632] sched_clock: Marking stable (1187615403, 0)->(1196227145, -8611742)
>[    1.188482] registered taskstats version 1
>[    1.188483] Loading compiled-in X.509 certificates
>[    1.190165] Loaded X.509 cert 'Build time autogenerated kernel key: 1e0c709e78d7d964f8145e966f0b59855ad28d02'
>[    1.190175] zswap: loaded using pool lzo/zbud
>[    1.193103] Key type big_key registered
>[    1.194413] Key type trusted registered
>[    1.195785] Key type encrypted registered
>[    1.195786] AppArmor: AppArmor sha1 policy hashing enabled
>[    1.195787] ima: No TPM chip found, activating TPM-bypass! (rc=-19)
>[    1.195794] evm: HMAC attrs: 0x1
>[    1.197261]   Magic number: 13:733:488
>[    1.197316] regulator regulator.0: hash matches
>[    1.197695] rtc_cmos 00:04: setting system clock to 2017-12-01 16:28:37 UTC (1512145717)
>[    1.197982] BIOS EDD facility v0.16 2004-Jun-25, 0 devices found
>[    1.197983] EDD information not available.
>[    1.381588]  nvme0n1: p1 p2 p3
>[    1.392080] atkbd serio0: Failed to deactivate keyboard on isa0060/serio0
>[    1.496476] usb 1-2: new high-speed USB device number 2 using xhci_hcd
>[    1.669098] usb 1-2: New USB device found, idVendor=0b95, idProduct=7720
>[    1.669099] usb 1-2: New USB device strings: Mfr=1, Product=2, SerialNumber=3
>[    1.669100] usb 1-2: Product: AX88772 
>[    1.669100] usb 1-2: SerialNumber: 00D921
>[    1.768490] atkbd serio0: Failed to enable keyboard on isa0060/serio0
>[    1.768533] input: AT Translated Set 2 keyboard as /devices/platform/i8042/serio0/input/input3
>[    1.769463] PM: Image not found (code -22)
>[    1.770428] Freeing unused kernel memory: 1620K
>[    1.770429] Write protecting the kernel read-only data: 14336k
>[    1.770898] Freeing unused kernel memory: 1244K
>[    1.771284] Freeing unused kernel memory: 252K
>[    1.774734] x86/mm: Checked W+X mappings: passed, no W+X pages found.
>[    1.796101] usb 1-14: new full-speed USB device number 3 using xhci_hcd
>[    1.816691] hidraw: raw HID events driver (C) Jiri Kosina
>[    1.888582] acpi PNP0C14:02: duplicate WMI GUID 05901221-D566-11D1-B2F0-00A0C9062910 (first instance was on PNP0C14:01)
>[    1.889062] pps_core: LinuxPPS API ver. 1 registered
>[    1.889063] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
>[    1.890756] PTP clock support registered
>[    1.890783] ahci 0000:00:17.0: version 3.0
>[    1.891321] ahci 0000:00:17.0: AHCI 0001.0301 32 slots 3 ports 6 Gbps 0xe impl SATA mode
>[    1.891322] ahci 0000:00:17.0: flags: 64bit ncq sntf pm clo only pio slum part ems deso sadm sds apst 
>[    1.893995] e1000e: Intel(R) PRO/1000 Network Driver - 3.2.6-k
>[    1.893996] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
>[    1.919628] Setting dangerous option alpha_support - tainting kernel
>[    1.919629] Setting dangerous option enable_guc_loading - tainting kernel
>[    1.919630] Setting dangerous option enable_guc_submission - tainting kernel
>[    1.946320] usb 1-14: New USB device found, idVendor=8087, idProduct=0aaa
>[    1.946324] usb 1-14: New USB device strings: Mfr=0, Product=0, SerialNumber=0
>[    1.980921] clocksource: Switched to clocksource tsc
>[    2.012474] scsi host0: ahci
>[    2.012665] scsi host1: ahci
>[    2.012905] scsi host2: ahci
>[    2.013093] scsi host3: ahci
>[    2.013118] ata1: DUMMY
>[    2.013134] ata2: SATA max UDMA/133 abar m2048@0xb1245000 port 0xb1245180 irq 132
>[    2.013136] ata3: SATA max UDMA/133 abar m2048@0xb1245000 port 0xb1245200 irq 132
>[    2.013141] ata4: SATA max UDMA/133 abar m2048@0xb1245000 port 0xb1245280 irq 132
>[    2.013227] e1000e 0000:00:1f.6: enabling device (0000 -> 0002)
>[    2.013522] e1000e 0000:00:1f.6: Interrupt Throttling Rate (ints/sec) set to dynamic conservative mode
>[    2.258045] e1000e 0000:00:1f.6 0000:00:1f.6 (uninitialized): registered PHC clock
>[    2.326269] ata2: SATA link down (SStatus 4 SControl 300)
>[    2.326296] ata3: SATA link down (SStatus 4 SControl 300)
>[    2.326325] ata4: SATA link down (SStatus 4 SControl 300)
>[    2.346267] e1000e 0000:00:1f.6 eth0: (PCI Express:2.5GT/s:Width x1) 88:88:88:88:87:88
>[    2.346269] e1000e 0000:00:1f.6 eth0: Intel(R) PRO/1000 Network Connection
>[    2.346433] e1000e 0000:00:1f.6 eth0: MAC: 13, PHY: 12, PBA No: FFFFFF-0FF
>[    2.346891] [drm:i915_driver_load [i915]] Found Cannon Lake PCH (CNP)
>[    2.346925] [drm:intel_power_domains_init [i915]] Allowed DC state mask 03
>[    2.347044] [drm:intel_device_info_dump [i915]] i915 device info: platform=COFFEELAKE gen=9 pciid=0x3e92 rev=0x00
>[    2.347061] [drm:intel_device_info_dump [i915]] i915 device info: is_mobile: no
>[    2.347076] [drm:intel_device_info_dump [i915]] i915 device info: is_lp: no
>[    2.347091] [drm:intel_device_info_dump [i915]] i915 device info: is_alpha_support: no
>[    2.347119] [drm:intel_device_info_dump [i915]] i915 device info: has_64bit_reloc: yes
>[    2.347133] [drm:intel_device_info_dump [i915]] i915 device info: has_aliasing_ppgtt: yes
>[    2.347134] e1000e 0000:00:1f.6 enp0s31f6: renamed from eth0
>[    2.347148] [drm:intel_device_info_dump [i915]] i915 device info: has_csr: yes
>[    2.347174] [drm:intel_device_info_dump [i915]] i915 device info: has_ddi: yes
>[    2.347200] [drm:intel_device_info_dump [i915]] i915 device info: has_dp_mst: yes
>[    2.347213] [drm:intel_device_info_dump [i915]] i915 device info: has_reset_engine: yes
>[    2.347226] [drm:intel_device_info_dump [i915]] i915 device info: has_fbc: yes
>[    2.347238] [drm:intel_device_info_dump [i915]] i915 device info: has_fpga_dbg: yes
>[    2.347251] [drm:intel_device_info_dump [i915]] i915 device info: has_full_ppgtt: yes
>[    2.347263] [drm:intel_device_info_dump [i915]] i915 device info: has_full_48bit_ppgtt: yes
>[    2.347276] [drm:intel_device_info_dump [i915]] i915 device info: has_gmch_display: no
>[    2.347289] [drm:intel_device_info_dump [i915]] i915 device info: has_guc: yes
>[    2.347301] [drm:intel_device_info_dump [i915]] i915 device info: has_guc_ct: no
>[    2.347313] [drm:intel_device_info_dump [i915]] i915 device info: has_hotplug: yes
>[    2.347325] [drm:intel_device_info_dump [i915]] i915 device info: has_l3_dpf: no
>[    2.347337] [drm:intel_device_info_dump [i915]] i915 device info: has_llc: yes
>[    2.347349] [drm:intel_device_info_dump [i915]] i915 device info: has_logical_ring_contexts: yes
>[    2.347360] [drm:intel_device_info_dump [i915]] i915 device info: has_logical_ring_preemption: yes
>[    2.347372] [drm:intel_device_info_dump [i915]] i915 device info: has_overlay: no
>[    2.347384] [drm:intel_device_info_dump [i915]] i915 device info: has_pooled_eu: no
>[    2.347396] [drm:intel_device_info_dump [i915]] i915 device info: has_psr: yes
>[    2.347408] [drm:intel_device_info_dump [i915]] i915 device info: has_rc6: yes
>[    2.347420] [drm:intel_device_info_dump [i915]] i915 device info: has_rc6p: no
>[    2.347431] [drm:intel_device_info_dump [i915]] i915 device info: has_resource_streamer: yes
>[    2.347443] [drm:intel_device_info_dump [i915]] i915 device info: has_runtime_pm: yes
>[    2.347455] [drm:intel_device_info_dump [i915]] i915 device info: has_snoop: no
>[    2.347467] [drm:intel_device_info_dump [i915]] i915 device info: unfenced_needs_alignment: no
>[    2.347479] [drm:intel_device_info_dump [i915]] i915 device info: cursor_needs_physical: no
>[    2.347490] [drm:intel_device_info_dump [i915]] i915 device info: hws_needs_physical: no
>[    2.347502] [drm:intel_device_info_dump [i915]] i915 device info: overlay_needs_physical: no
>[    2.347514] [drm:intel_device_info_dump [i915]] i915 device info: supports_tv: no
>[    2.347528] [drm:i915_driver_load [i915]] i915 device info: has_ipc: yes
>[    2.347920] [drm:intel_device_info_runtime_init [i915]] slice mask: 0001
>[    2.347933] [drm:intel_device_info_runtime_init [i915]] slice total: 1
>[    2.347945] [drm:intel_device_info_runtime_init [i915]] subslice total: 3
>[    2.347957] [drm:intel_device_info_runtime_init [i915]] subslice mask 0007
>[    2.347969] [drm:intel_device_info_runtime_init [i915]] subslice per slice: 3
>[    2.347981] [drm:intel_device_info_runtime_init [i915]] EU total: 24
>[    2.347993] [drm:intel_device_info_runtime_init [i915]] EU per subslice: 8
>[    2.348007] [drm:intel_device_info_runtime_init [i915]] has slice power gating: n
>[    2.348053] [drm:intel_device_info_runtime_init [i915]] has subslice power gating: n
>[    2.348065] [drm:intel_device_info_runtime_init [i915]] has EU power gating: y
>[    2.348100] [drm:i915_driver_load [i915]] CS timestamp frequency: 12000 kHz
>[    2.348114] [drm:i915_driver_load [i915]] ppgtt mode: 3
>[    2.348122] [drm] Memory usable by graphics device = 4078M
>[    2.348140] [drm:i915_ggtt_probe_hw [i915]] GMADR size = 256M
>[    2.348156] [drm:i915_ggtt_probe_hw [i915]] GTT stolen size = 32M
>[    2.348157] checking generic (a0000000 7f0000) vs hw (a0000000 10000000)
>[    2.348158] fb: switching to inteldrmfb from EFI VGA
>[    2.348168] Console: switching to colour dummy device 80x25
>[    2.348305] [drm] Replacing VGA console driver
>[    2.348376] [drm:i915_gem_init_stolen [i915]] Memory reserved for graphics device: 32768K, usable: 31744K
>[    2.348402] [drm:intel_opregion_setup [i915]] graphic opregion physical addr: 0x8cb19018
>[    2.348468] [drm:intel_opregion_setup [i915]] Public ACPI methods supported
>[    2.348488] [drm:intel_opregion_setup [i915]] SWSCI supported
>[    2.349492] [drm:intel_opregion_setup [i915]] SWSCI GBDA callbacks 00000cb3, SBCB callbacks 00300483
>[    2.349509] [drm:intel_opregion_setup [i915]] ASLE supported
>[    2.349526] [drm:intel_opregion_setup [i915]] ASLE extension supported
>[    2.349543] [drm:intel_opregion_setup [i915]] Found valid VBT in ACPI OpRegion (Mailbox #4)
>[    2.349588] [drm:intel_gvt_init [i915]] GVT-g is disabled by kernel params
>[    2.349589] [drm] Supports vblank timestamp caching Rev 2 (21.10.2013).
>[    2.349589] [drm] Driver supports precise vblank timestamp query.
>[    2.349609] [drm:intel_bios_init [i915]] Set default to SSC at 120000 kHz
>[    2.349628] [drm:intel_bios_init [i915]] VBT signature "$VBT SKYLAKE        ", BDB version 212
>[    2.349647] [drm:intel_bios_init [i915]] BDB_GENERAL_FEATURES int_tv_support 0 int_crt_support 0 lvds_use_ssc 0 lvds_ssc_freq 120000 display_clock_mode 1 fdi_rx_polarity_inverted 0
>[    2.349664] [drm:intel_bios_init [i915]] crt_ddc_bus_pin: 2
>[    2.349682] [drm:intel_bios_init [i915]] Expected child device config size for VBT version 212 not known; assuming 38
>[    2.350014] [drm:intel_opregion_get_panel_type [i915]] Ignoring OpRegion panel type (0)
>[    2.350032] [drm:intel_bios_init [i915]] Panel type: 2 (VBT)
>[    2.350049] [drm:intel_bios_init [i915]] DRRS supported mode is static
>[    2.350066] [drm:intel_bios_init [i915]] Found panel mode in BIOS VBT tables:
>[    2.350073] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1024x768" 0 65000 1024 1048 1184 1344 768 771 777 806 0x8 0xa
>[    2.350091] [drm:intel_bios_init [i915]] VBT initial LVDS value 300
>[    2.350108] [drm:intel_bios_init [i915]] VBT backlight PWM modulation frequency 200 Hz, active high, min brightness 0, level 255, controller 0
>[    2.350125] [drm:intel_bios_init [i915]] DRRS State Enabled:1
>[    2.350142] [drm:intel_bios_init [i915]] Skipping SDVO device mapping
>[    2.350159] [drm:intel_bios_init [i915]] Port A VBT info: DP:1 HDMI:0 DVI:0 EDP:1 CRT:0
>[    2.350175] [drm:intel_bios_init [i915]] VBT HDMI level shift for port A: 0
>[    2.350191] [drm:intel_bios_init [i915]] Port B VBT info: DP:1 HDMI:1 DVI:1 EDP:0 CRT:0
>[    2.350207] [drm:intel_bios_init [i915]] VBT HDMI level shift for port B: 8
>[    2.350223] [drm:intel_bios_init [i915]] Port C VBT info: DP:1 HDMI:1 DVI:1 EDP:0 CRT:0
>[    2.350239] [drm:intel_bios_init [i915]] VBT HDMI level shift for port C: 8
>[    2.350255] [drm:intel_bios_init [i915]] Port D VBT info: DP:1 HDMI:1 DVI:1 EDP:0 CRT:0
>[    2.350271] [drm:intel_bios_init [i915]] VBT HDMI level shift for port D: 8
>[    2.350304] [drm:intel_dsm_detect [i915]] no _DSM method for intel device
>[    2.350360] [drm:i915_driver_load [i915]] rawclk rate: 24000 kHz
>[    2.350378] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 00
>[    2.350395] [drm:intel_power_well_enable [i915]] enabling power well 1
>[    2.350412] [drm:intel_power_well_enable [i915]] enabling MISC IO power well
>[    2.350433] [drm:intel_dump_cdclk_state [i915]] Current CDCLK 337500 kHz, VCO 8100000 kHz, ref 24000 kHz, voltage level 0
>[    2.350452] [drm:intel_update_max_cdclk [i915]] Max CD clock rate: 675000 kHz
>[    2.350469] [drm:skl_init_cdclk [i915]] Max dotclock rate: 675000 kHz
>[    2.350497] [drm:intel_power_well_enable [i915]] enabling always-on
>[    2.350512] [drm:intel_power_well_enable [i915]] enabling DC off
>[    2.350528] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 00
>[    2.350544] [drm:intel_power_well_enable [i915]] enabling power well 2
>[    2.350546] i915 0000:00:02.0: vgaarb: changed VGA decodes: olddecodes=io+mem,decodes=io+mem:owns=io+mem
>[    2.350562] [drm:intel_power_well_enable [i915]] enabling DDI A/E IO power well
>[    2.350576] [drm:intel_power_well_enable [i915]] enabling DDI B IO power well
>[    2.350590] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well
>[    2.350605] [drm:intel_power_well_enable [i915]] enabling DDI D IO power well
>[    2.350625] [drm:intel_csr_ucode_init [i915]] Loading i915/kbl_dmc_ver1_04.bin
>[    2.350961] [drm] Finished loading DMC firmware i915/kbl_dmc_ver1_04.bin (v1.4)
>[    2.351648] [drm:intel_fbc_init [i915]] Sanitized enable_fbc value: 1
>[    2.351670] [drm:intel_print_wm_latency [i915]] Gen9 Plane WM0 latency 2 (2.0 usec)
>[    2.351687] [drm:intel_print_wm_latency [i915]] Gen9 Plane WM1 latency 19 (19.0 usec)
>[    2.351703] [drm:intel_print_wm_latency [i915]] Gen9 Plane WM2 latency 28 (28.0 usec)
>[    2.351719] [drm:intel_print_wm_latency [i915]] Gen9 Plane WM3 latency 32 (32.0 usec)
>[    2.351734] [drm:intel_print_wm_latency [i915]] Gen9 Plane WM4 latency 63 (63.0 usec)
>[    2.351748] [drm:intel_print_wm_latency [i915]] Gen9 Plane WM5 latency 77 (77.0 usec)
>[    2.351763] [drm:intel_print_wm_latency [i915]] Gen9 Plane WM6 latency 83 (83.0 usec)
>[    2.351777] [drm:intel_print_wm_latency [i915]] Gen9 Plane WM7 latency 99 (99.0 usec)
>[    2.351799] [drm:intel_modeset_init [i915]] 2 display pipes available.
>[    2.351834] [drm:intel_dump_cdclk_state [i915]] Current CDCLK 337500 kHz, VCO 8100000 kHz, ref 24000 kHz, voltage level 0
>[    2.352156] [drm:intel_dp_init_connector [i915]] Adding eDP connector on port A
>[    2.352177] [drm:intel_dp_init_connector [i915]] using AUX A for port A (VBT)
>[    2.352247] [drm:intel_pps_dump_state [i915]] cur t1_t3 0 t8 0 t9 0 t10 500 t11_t12 6000
>[    2.352265] [drm:intel_pps_dump_state [i915]] vbt t1_t3 2000 t8 10 t9 2000 t10 500 t11_t12 6000
>[    2.352283] [drm:intel_dp_init_panel_power_sequencer [i915]] panel power up delay 200, power down delay 50, power cycle delay 600
>[    2.352300] [drm:intel_dp_init_panel_power_sequencer [i915]] backlight on delay 1, off delay 200
>[    2.352425] [drm:intel_dp_init_panel_power_sequencer_registers [i915]] panel power sequencer register settings: PP_ON 0x7d00001, PP_OFF 0x1f40001, PP_DIV 0x60
>[    2.352482] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[    2.352590] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006f
>[    2.353120] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 0a 82 41 00 00 01 80 02 00 00 00 0f 0b 00
>[    2.353588] [drm:drm_dp_read_desc [drm_kms_helper]] DP sink: OUI 00-1c-f8 dev-ID  HW-rev 0.1 SW-rev 1.22 quirks 0x0000
>[    2.354045] [drm:intel_dp_init_connector [i915]] Detected EDP PSR Panel.
>[    2.354463] [drm:intel_dp_init_connector [i915]] eDP DPCD: 02 8a 81
>[    2.358557] [drm:drm_add_edid_modes [drm]] ELD: no CEA Extension found
>[    2.358583] [drm:intel_dp_init_connector [i915]] VBT doesn't support DRRS
>[    2.358654] [drm:intel_panel_setup_backlight [i915]] Connector eDP-1 backlight initialized, enabled, brightness 120000/120000
>[    2.358701] [drm:intel_ddi_init [i915]] VBT says port B has lspcon
>[    2.358722] [drm:intel_dp_init_connector [i915]] Adding DP connector on port B
>[    2.358742] [drm:intel_dp_init_connector [i915]] using AUX B for port B (VBT)
>[    2.359062] [drm:lspcon_wake_native_aux_ch [i915]] Native AUX CH up, DPCD version: 1.2
>[    2.359474] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[    2.360715] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[    2.362022] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[    2.363327] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[    2.364755] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[    2.365638] [drm:drm_dp_dual_mode_detect [drm_kms_helper]] DP dual mode HDMI ID: DP-HDMI ADAPTOR\004 (err 0)
>[    2.366051] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[    2.367360] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[    2.368669] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[    2.369963] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[    2.371270] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[    2.372154] [drm:drm_dp_dual_mode_detect [drm_kms_helper]] DP dual mode adaptor ID: a8 (err 0)
>[    2.372203] [drm:lspcon_init [i915]] LSPCON detected
>[    2.372616] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[    2.373924] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[    2.375237] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[    2.376540] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[    2.377851] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[    2.378764] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[    2.379194] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 00 00 04 00 0f 00 04
>[    2.379557] [drm:drm_dp_read_desc [drm_kms_helper]] DP branch: OUI 00-60-ad dev-ID MC2800 HW-rev 2.2 SW-rev 1.70 quirks 0x0000
>[    2.379590] [drm:lspcon_init [i915]] Success: LSPCON init
>[    2.379610] [drm:intel_modeset_init [i915]] LSPCON init success on port B
>[    2.379632] [drm:intel_dp_init_connector [i915]] Adding DP connector on port C
>[    2.379651] [drm:intel_dp_init_connector [i915]] using AUX C for port C (VBT)
>[    2.379671] [drm:intel_hdmi_init_connector [i915]] Adding HDMI connector on port C
>[    2.379690] [drm:intel_hdmi_init_connector [i915]] Using DDC pin 0x2 for port C (platform default)
>[    2.379710] [drm:intel_dp_init_connector [i915]] Adding DP connector on port D
>[    2.379728] [drm:intel_dp_init_connector [i915]] using AUX D for port D (VBT)
>[    2.379746] [drm:intel_hdmi_init_connector [i915]] Adding HDMI connector on port D
>[    2.379764] [drm:intel_hdmi_init_connector [i915]] Using DDC pin 0x4 for port D (VBT)
>[    2.379790] [drm:intel_modeset_setup_hw_state [i915]] pipe A active planes 0x1
>[    2.379810] [drm:intel_modeset_setup_hw_state [i915]] pipe A active planes 0x1
>[    2.379829] [drm:intel_modeset_setup_hw_state [i915]] pipe A active planes 0x1
>[    2.379848] [drm:intel_modeset_setup_hw_state [i915]] [CRTC:37:pipe A] hw state readout: enabled
>[    2.379867] [drm:intel_modeset_setup_hw_state [i915]] pipe B active planes 0x0
>[    2.379885] [drm:intel_modeset_setup_hw_state [i915]] pipe B active planes 0x0
>[    2.379903] [drm:intel_modeset_setup_hw_state [i915]] pipe B active planes 0x0
>[    2.379920] [drm:intel_modeset_setup_hw_state [i915]] [CRTC:47:pipe B] hw state readout: disabled
>[    2.379938] [drm:intel_modeset_setup_hw_state [i915]] DPLL 0 hw state readout: crtc_mask 0x00000001, on 1
>[    2.379955] [drm:intel_modeset_setup_hw_state [i915]] DPLL 1 hw state readout: crtc_mask 0x00000000, on 0
>[    2.379972] [drm:intel_modeset_setup_hw_state [i915]] DPLL 2 hw state readout: crtc_mask 0x00000000, on 0
>[    2.379989] [drm:intel_modeset_setup_hw_state [i915]] DPLL 3 hw state readout: crtc_mask 0x00000000, on 0
>[    2.380010] [drm:intel_ddi_get_config [i915]] pipe has 24 bpp for eDP panel, overriding BIOS-provided max 18 bpp
>[    2.380046] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:48:DDI A] hw state readout: enabled, pipe A
>[    2.380090] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:56:DDI B] hw state readout: disabled, pipe A
>[    2.380107] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:58:DP-MST A] hw state readout: disabled, pipe A
>[    2.380124] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:59:DP-MST B] hw state readout: disabled, pipe B
>[    2.380141] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:60:DDI C] hw state readout: disabled, pipe A
>[    2.380188] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:62:DP-MST A] hw state readout: disabled, pipe A
>[    2.380205] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:63:DP-MST B] hw state readout: disabled, pipe B
>[    2.380223] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:66:DDI D] hw state readout: disabled, pipe A
>[    2.380240] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:68:DP-MST A] hw state readout: disabled, pipe A
>[    2.380270] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:69:DP-MST B] hw state readout: disabled, pipe B
>[    2.380287] [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:49:eDP-1] hw state readout: enabled
>[    2.380304] [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:57:DP-1] hw state readout: disabled
>[    2.380321] [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:61:DP-2] hw state readout: disabled
>[    2.380352] [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:64:HDMI-A-1] hw state readout: disabled
>[    2.380370] [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:67:DP-3] hw state readout: disabled
>[    2.380388] [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:70:HDMI-A-2] hw state readout: disabled
>[    2.380413] [drm:intel_dump_pipe_config [i915]] [CRTC:37:pipe A][setup_hw_state]
>[    2.380432] [drm:intel_dump_pipe_config [i915]] output_types: EDP (0x100)
>[    2.380451] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0
>[    2.380470] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 6467616, gmch_n: 8388608, link_m: 269484, link_n: 524288, tu: 64
>[    2.380489] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[    2.380507] [drm:intel_dump_pipe_config [i915]] requested mode:
>[    2.380513] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 138779 1920 1966 1996 2080 1080 1082 1086 1112 0x40 0xa
>[    2.380531] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[    2.380537] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 138779 1920 1966 1996 2080 1080 1082 1086 1112 0x40 0xa
>[    2.380556] [drm:intel_dump_pipe_config [i915]] crtc timings: 138779 1920 1966 1996 2080 1080 1082 1086 1112, type: 0x40 flags: 0xa
>[    2.380575] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 138779
>[    2.380592] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[    2.380610] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[    2.380628] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[    2.380645] [drm:intel_dump_pipe_config [i915]] dpll_hw_state: ctrl1: 0x3, cfgcr1: 0x0, cfgcr2: 0x0
>[    2.380662] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[    2.380680] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 1A] disabled, scaler_id = -1
>[    2.380697] [drm:intel_dump_pipe_config [i915]] [PLANE:31:plane 2A] disabled, scaler_id = -1
>[    2.380714] [drm:intel_dump_pipe_config [i915]] [PLANE:34:cursor A] disabled, scaler_id = -1
>[    2.380731] [drm:intel_dump_pipe_config [i915]] [CRTC:47:pipe B][setup_hw_state]
>[    2.380748] [drm:intel_dump_pipe_config [i915]] output_types:  (0x0)
>[    2.380766] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 0, dithering: 0
>[    2.380782] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[    2.380799] [drm:intel_dump_pipe_config [i915]] requested mode:
>[    2.380805] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[    2.380822] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[    2.380828] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[    2.380846] [drm:intel_dump_pipe_config [i915]] crtc timings: 0 0 0 0 0 0 0 0 0, type: 0x0 flags: 0x0
>[    2.380863] [drm:intel_dump_pipe_config [i915]] port clock: 0, pipe src size: 0x0, pixel rate 0
>[    2.380881] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[    2.380898] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[    2.380915] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[    2.380932] [drm:intel_dump_pipe_config [i915]] dpll_hw_state: ctrl1: 0x0, cfgcr1: 0x0, cfgcr2: 0x0
>[    2.380949] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[    2.380966] [drm:intel_dump_pipe_config [i915]] [PLANE:38:plane 1B] disabled, scaler_id = -1
>[    2.380982] [drm:intel_dump_pipe_config [i915]] [PLANE:41:plane 2B] disabled, scaler_id = -1
>[    2.380999] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor B] disabled, scaler_id = -1
>[    2.381031] [drm:intel_power_well_disable [i915]] disabling DDI D IO power well
>[    2.381050] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well
>[    2.381068] [drm:intel_power_well_disable [i915]] disabling DDI B IO power well
>[    2.381085] [drm:intel_power_well_disable [i915]] disabling power well 2
>[    2.381113] [drm:skylake_get_initial_plane_config [i915]] pipe A/plane 1A with fb: size=1920x1080@32, offset=0, pitch 7680, size 0x7e9000
>[    2.381134] [drm:i915_gem_object_create_stolen_for_preallocated [i915]] creating preallocated stolen object: stolen_offset=0, gtt_offset=0, size=7e9000
>[    2.381153] [drm:i915_gem_object_create_stolen_for_preallocated [i915]] failed to allocate stolen space
>[    2.381174] [drm:intel_plane_disable_noatomic [i915]] pipe A active planes 0x0
>[    2.381195] [drm:intel_uc_fw_fetch [i915]] HuC fw fetch i915/kbl_huc_ver02_00_1810.bin
>[    2.381214] [drm:intel_uc_fw_fetch [i915]] HuC fw fetch PENDING
>[    2.381265] [drm:intel_uc_fw_fetch [i915]] HuC fw size 218688 ptr ffff983dd102e7c0
>[    2.381284] [drm:intel_uc_fw_fetch [i915]] HuC fw version 2.0 (wanted 2.0)
>[    2.381332] [drm:intel_uc_fw_fetch [i915]] HuC fw fetch SUCCESS
>[    2.381352] [drm:intel_uc_fw_fetch [i915]] GuC fw fetch i915/kbl_guc_ver9_39.bin
>[    2.381370] [drm:intel_uc_fw_fetch [i915]] GuC fw fetch PENDING
>[    2.381405] [drm:intel_uc_fw_fetch [i915]] GuC fw size 147776 ptr ffff983dd102e7c0
>[    2.381423] [drm:intel_uc_fw_fetch [i915]] GuC fw version 9.39 (wanted 9.39)
>[    2.381459] [drm:intel_uc_fw_fetch [i915]] GuC fw fetch SUCCESS
>[    2.381901] [drm:i915_gem_init_ggtt [i915]] clearing unused GTT space: [1000, fee00000]
>[    2.381932] [drm:i915_gem_contexts_init [i915]] logical context support initialized
>[    2.381955] [drm:intel_engine_create_scratch [i915]] rcs0 pipe control offset: 0xfedff000
>[    2.382108] [drm:intel_engine_init_common [i915]] rcs0 hws offset: 0xfedcf000
>[    2.382214] [drm:intel_engine_init_common [i915]] bcs0 hws offset: 0xfedc8000
>[    2.382316] [drm:intel_engine_init_common [i915]] vcs0 hws offset: 0xfedc1000
>[    2.382415] [drm:intel_engine_init_common [i915]] vecs0 hws offset: 0xfedba000
>[    2.382529] [drm:intel_uc_fw_upload [i915]] HuC fw load i915/kbl_huc_ver02_00_1810.bin
>[    2.382548] [drm:intel_uc_fw_upload [i915]] HuC fw load PENDING
>[    2.383984] [drm:huc_ucode_xfer [i915]] HuC DMA transfer wait over with ret 0
>[    2.384008] [drm:intel_uc_fw_upload [i915]] HuC fw load SUCCESS
>[    2.384011] [drm] HuC: Loaded firmware i915/kbl_huc_ver02_00_1810.bin (version 2.0)
>[    2.384042] [drm:intel_uc_fw_upload [i915]] GuC fw load i915/kbl_guc_ver9_39.bin
>[    2.384063] [drm:intel_uc_fw_upload [i915]] GuC fw load PENDING
>[    2.385656] [drm:guc_fw_xfer [i915]] GuC DMA status 0x10
>[    2.394862] [drm:guc_fw_xfer [i915]] GuC status 0x8002f0ec
>[    2.394885] [drm:intel_uc_fw_upload [i915]] GuC fw load SUCCESS
>[    2.394886] [drm] GuC: Loaded firmware i915/kbl_guc_ver9_39.bin (version 9.39)
>[    2.405524] [drm:guc_client_alloc [i915]] reserved cacheline 0x0, next 0x40, linesize 64
>[    2.405547] [drm:guc_client_alloc [i915]] Host engines 0x17 => GuC engines used 0xf
>[    2.405569] [drm:__reserve_doorbell [i915]] client 0 (high prio=no) reserved doorbell: 0
>[    2.405668] [drm:guc_client_alloc [i915]] new priority 2 client ffff983dd0468300 for engine(s) 0x17: stage_id 0
>[    2.405688] [drm:guc_client_alloc [i915]] doorbell id 0, cacheline offset 0x0
>[    2.405713] [drm:guc_client_alloc [i915]] reserved cacheline 0x40, next 0x80, linesize 64
>[    2.405733] [drm:guc_client_alloc [i915]] Host engines 0x17 => GuC engines used 0xf
>[    2.405752] [drm:__reserve_doorbell [i915]] client 1 (high prio=yes) reserved doorbell: 128
>[    2.405849] [drm:guc_client_alloc [i915]] new priority 0 client ffff983dd0468f80 for engine(s) 0x17: stage_id 1
>[    2.405867] [drm:guc_client_alloc [i915]] doorbell id 128, cacheline offset 0x40
>[    2.406134] i915 0000:00:02.0: GuC submission enabled (firmware i915/kbl_guc_ver9_39.bin [version 9.39])
>[    2.406226] [drm:gen8_init_common_ring [i915]] Execlists enabled for rcs0
>[    2.406262] [drm:init_workarounds_ring [i915]] rcs0: Number of context specific w/a: 14
>[    2.406319] [drm:gen8_init_common_ring [i915]] Execlists enabled for bcs0
>[    2.406377] [drm:gen8_init_common_ring [i915]] Execlists enabled for vcs0
>[    2.406432] [drm:gen8_init_common_ring [i915]] Execlists enabled for vecs0
>[    2.406502] [drm] RC6 on
>[    2.406897] [drm:intel_fbdev_init [i915]] pipe A not active or no fb, skipping
>[    2.406918] [drm:intel_fbdev_init [i915]] pipe B not active or no fb, skipping
>[    2.406937] [drm:intel_fbdev_init [i915]] no active fbs found, not using BIOS config
>[    2.407626] [drm:intel_backlight_device_register [i915]] Connector eDP-1 backlight sysfs interface registered
>[    2.407647] [drm:intel_dp_connector_register [i915]] registering DPDDC-A bus for card0-eDP-1
>[    2.407779] [drm:intel_dp_connector_register [i915]] registering DPDDC-B bus for card0-DP-1
>[    2.407836] [drm:intel_dp_connector_register [i915]] registering DPDDC-C bus for card0-DP-2
>[    2.407899] [drm:intel_dp_connector_register [i915]] registering DPDDC-D bus for card0-DP-3
>[    2.407935] [drm] Initialized i915 1.6.0 20171117 for 0000:00:02.0 on minor 0
>[    2.407993] [drm:intel_opregion_register [i915]] 6 outputs detected
>[    2.409128] ACPI: Video Device [GFX0] (multi-head: yes  rom: no  post: no)
>[    2.409381] input: Video Bus as /devices/LNXSYSTM:00/LNXSYBUS:00/PNP0A08:00/LNXVIDEO:00/input/input4
>[    2.409462] [drm:drm_setup_crtcs [drm_kms_helper]] 
>[    2.409466] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:49:eDP-1]
>[    2.409493] [drm:intel_dp_detect [i915]] [CONNECTOR:49:eDP-1]
>[    2.409517] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>[    2.409538] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[    2.409559] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[    2.409981] [drm:drm_dp_read_desc [drm_kms_helper]] DP sink: OUI 00-1c-f8 dev-ID  HW-rev 0.1 SW-rev 1.22 quirks 0x0000
>[    2.410674] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:49:eDP-1] status updated from unknown to connected
>[    2.410683] [drm:drm_add_edid_modes [drm]] ELD: no CEA Extension found
>[    2.410693] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:49:eDP-1] probed modes :
>[    2.410699] [drm:drm_mode_debug_printmodeline [drm]] Modeline 50:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[    2.410701] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:57:DP-1]
>[    2.410724] [drm:intel_dp_detect [i915]] [CONNECTOR:57:DP-1]
>[    2.410742] [drm:intel_power_well_enable [i915]] enabling power well 2
>[    2.411066] [drm:lspcon_wake_native_aux_ch [i915]] Native AUX CH up, DPCD version: 1.2
>[    2.411112] [drm:lspcon_resume [i915]] LSPCON recovering in PCON mode after 0 ms
>[    2.411525] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[    2.412675] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[    2.413941] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[    2.415210] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[    2.416482] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[    2.417349] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[    2.417752] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 00 00 04 00 0f 00 04
>[    2.418434] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>[    2.418454] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000
>[    2.418473] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000
>[    2.418836] [drm:drm_dp_read_desc [drm_kms_helper]] DP branch: OUI 00-60-ad dev-ID MC2800 HW-rev 2.2 SW-rev 1.70 quirks 0x0000
>[    2.419127] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[    2.419851] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[    2.421116] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[    2.422388] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[    2.423652] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[    2.424804] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[    2.426072] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[    2.427345] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[    2.428618] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[    2.429883] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[    2.431280] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[    2.432679] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[    2.434077] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[    2.435474] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[    2.436820] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[    2.438218] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[    2.439615] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[    2.440932] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[    2.442201] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[    2.443473] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[    2.444695] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[    2.445963] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[    2.447360] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[    2.448759] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[    2.450160] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[    2.451560] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[    2.452892] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[    2.454290] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[    2.455693] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[    2.457081] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[    2.458223] [drm:intel_power_well_disable [i915]] disabling power well 2
>[    2.458229] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:57:DP-1] status updated from unknown to connected
>[    2.458237] [drm:drm_add_edid_modes [drm]] ELD monitor HP E232
>[    2.458243] [drm:drm_add_edid_modes [drm]] HDMI: latency present 0 0, video latency 0 0, audio latency 0 0
>[    2.458247] [drm:drm_add_edid_modes [drm]] ELD size 28, SAD count 0
>[    2.458251] [drm:drm_add_edid_modes [drm]] HDMI: DVI dual 0, max TMDS clock 170000 kHz
>[    2.458312] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:57:DP-1] probed modes :
>[    2.458318] [drm:drm_mode_debug_printmodeline [drm]] Modeline 73:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[    2.458323] [drm:drm_mode_debug_printmodeline [drm]] Modeline 95:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[    2.458327] [drm:drm_mode_debug_printmodeline [drm]] Modeline 75:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[    2.458331] [drm:drm_mode_debug_printmodeline [drm]] Modeline 80:"1680x1050" 60 119000 1680 1728 1760 1840 1050 1053 1059 1080 0x40 0x9
>[    2.458335] [drm:drm_mode_debug_printmodeline [drm]] Modeline 79:"1600x900" 60 108000 1600 1624 1704 1800 900 901 904 1000 0x40 0x5
>[    2.458339] [drm:drm_mode_debug_printmodeline [drm]] Modeline 83:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[    2.458343] [drm:drm_mode_debug_printmodeline [drm]] Modeline 81:"1440x900" 60 88750 1440 1488 1520 1600 900 903 909 926 0x40 0x9
>[    2.458347] [drm:drm_mode_debug_printmodeline [drm]] Modeline 82:"1280x800" 60 71000 1280 1328 1360 1440 800 803 809 823 0x40 0x9
>[    2.458351] [drm:drm_mode_debug_printmodeline [drm]] Modeline 76:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[    2.458355] [drm:drm_mode_debug_printmodeline [drm]] Modeline 97:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[    2.458359] [drm:drm_mode_debug_printmodeline [drm]] Modeline 77:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[    2.458363] [drm:drm_mode_debug_printmodeline [drm]] Modeline 86:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[    2.458367] [drm:drm_mode_debug_printmodeline [drm]] Modeline 84:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[    2.458371] [drm:drm_mode_debug_printmodeline [drm]] Modeline 93:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[    2.458375] [drm:drm_mode_debug_printmodeline [drm]] Modeline 98:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[    2.458379] [drm:drm_mode_debug_printmodeline [drm]] Modeline 78:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[    2.458383] [drm:drm_mode_debug_printmodeline [drm]] Modeline 99:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[    2.458387] [drm:drm_mode_debug_printmodeline [drm]] Modeline 85:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[    2.458389] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:61:DP-2]
>[    2.458413] [drm:intel_dp_detect [i915]] [CONNECTOR:61:DP-2]
>[    2.458432] [drm:intel_power_well_enable [i915]] enabling power well 2
>[    2.458476] [drm:intel_power_well_disable [i915]] disabling power well 2
>[    2.458481] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:61:DP-2] status updated from unknown to disconnected
>[    2.458483] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:61:DP-2] disconnected
>[    2.458486] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:64:HDMI-A-1]
>[    2.458508] [drm:intel_hdmi_detect [i915]] [CONNECTOR:64:HDMI-A-1]
>[    2.458856] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[    2.458876] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[    2.459138] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[    2.459144] [drm:drm_do_probe_ddc_edid [drm]] drm: skipping non-existent adapter i915 gmbus dpc
>[    2.459507] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[    2.459526] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[    2.459873] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[    2.459877] [drm:drm_dp_dual_mode_detect [drm_kms_helper]] DP dual mode HDMI ID:  (err -6)
>[    2.459879] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:64:HDMI-A-1] status updated from unknown to disconnected
>[    2.459882] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:64:HDMI-A-1] disconnected
>[    2.459884] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:67:DP-3]
>[    2.459903] [drm:intel_dp_detect [i915]] [CONNECTOR:67:DP-3]
>[    2.459922] [drm:intel_power_well_enable [i915]] enabling power well 2
>[    2.459966] [drm:intel_power_well_disable [i915]] disabling power well 2
>[    2.459970] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:67:DP-3] status updated from unknown to disconnected
>[    2.459973] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:67:DP-3] disconnected
>[    2.459975] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:70:HDMI-A-2]
>[    2.459995] [drm:intel_hdmi_detect [i915]] [CONNECTOR:70:HDMI-A-2]
>[    2.471347] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0050 w(1)
>[    2.471370] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK on first message, retry
>[    2.482813] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0050 w(1)
>[    2.482819] [drm:drm_do_probe_ddc_edid [drm]] drm: skipping non-existent adapter i915 gmbus dpd
>[    2.494279] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0040 w(1)
>[    2.494302] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK on first message, retry
>[    2.505753] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0040 w(1)
>[    2.505757] [drm:drm_dp_dual_mode_detect [drm_kms_helper]] DP dual mode HDMI ID:  (err -6)
>[    2.505760] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:70:HDMI-A-2] status updated from unknown to disconnected
>[    2.505762] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:70:HDMI-A-2] disconnected
>[    2.505765] [drm:drm_setup_crtcs [drm_kms_helper]] connector 49 enabled? yes
>[    2.505767] [drm:drm_setup_crtcs [drm_kms_helper]] connector 57 enabled? yes
>[    2.505769] [drm:drm_setup_crtcs [drm_kms_helper]] connector 61 enabled? no
>[    2.505771] [drm:drm_setup_crtcs [drm_kms_helper]] connector 64 enabled? no
>[    2.505773] [drm:drm_setup_crtcs [drm_kms_helper]] connector 67 enabled? no
>[    2.505775] [drm:drm_setup_crtcs [drm_kms_helper]] connector 70 enabled? no
>[    2.505799] [drm:intel_fb_initial_config [i915]] Not using firmware configuration
>[    2.505802] [drm:drm_setup_crtcs [drm_kms_helper]] looking for cmdline mode on connector 49
>[    2.505804] [drm:drm_setup_crtcs [drm_kms_helper]] looking for preferred mode on connector 49 0
>[    2.505806] [drm:drm_setup_crtcs [drm_kms_helper]] found mode 1920x1080
>[    2.505808] [drm:drm_setup_crtcs [drm_kms_helper]] looking for cmdline mode on connector 57
>[    2.505810] [drm:drm_setup_crtcs [drm_kms_helper]] looking for preferred mode on connector 57 0
>[    2.505812] [drm:drm_setup_crtcs [drm_kms_helper]] found mode 1920x1080
>[    2.505814] [drm:drm_setup_crtcs [drm_kms_helper]] picking CRTCs for 8192x8192 config
>[    2.505818] [drm:drm_setup_crtcs [drm_kms_helper]] desired mode 1920x1080 set on crtc 37 (0,0)
>[    2.505820] [drm:drm_setup_crtcs [drm_kms_helper]] desired mode 1920x1080 set on crtc 47 (0,0)
>[    2.505842] [drm:intelfb_create [i915]] no BIOS fb, allocating a new one
>[    2.506177] [drm:intelfb_create [i915]] allocated 1920x1080 fb: 0x00180000
>[    2.506264] fbcon: inteldrmfb (fb0) is primary device
>[    2.506317] [drm:intel_atomic_check [i915]] [CONNECTOR:49:eDP-1] checking for sink bpp constrains
>[    2.506340] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[    2.506347] [drm:drm_mode_debug_printmodeline [drm]] Modeline 52:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[    2.506370] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 138780KHz
>[    2.506395] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24
>[    2.506415] [drm:intel_dp_compute_config [i915]] DP link bw required 416340 available 540000
>[    2.506435] [drm:intel_dp_compute_config [i915]] PSR disable by flag
>[    2.506457] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[    2.506479] [drm:intel_dump_pipe_config [i915]] [CRTC:37:pipe A][modeset]
>[    2.506499] [drm:intel_dump_pipe_config [i915]] output_types: EDP (0x100)
>[    2.506519] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0
>[    2.506539] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 6467616, gmch_n: 8388608, link_m: 269484, link_n: 524288, tu: 64
>[    2.506558] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[    2.506577] [drm:intel_dump_pipe_config [i915]] requested mode:
>[    2.506583] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[    2.506602] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[    2.506608] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[    2.506628] [drm:intel_dump_pipe_config [i915]] crtc timings: 138780 1920 1966 1996 2080 1080 1082 1086 1112, type: 0x48 flags: 0xa
>[    2.506647] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 138780
>[    2.506665] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[    2.506684] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[    2.506702] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[    2.506720] [drm:intel_dump_pipe_config [i915]] dpll_hw_state: ctrl1: 0x3, cfgcr1: 0x0, cfgcr2: 0x0
>[    2.506738] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[    2.506756] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 1A] disabled, scaler_id = -1
>[    2.506774] [drm:intel_dump_pipe_config [i915]] [PLANE:31:plane 2A] disabled, scaler_id = -1
>[    2.506792] [drm:intel_dump_pipe_config [i915]] [PLANE:34:cursor A] disabled, scaler_id = -1
>[    2.506812] [drm:intel_atomic_check [i915]] [CONNECTOR:57:DP-1] checking for sink bpp constrains
>[    2.506832] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[    2.506853] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 148500KHz
>[    2.506875] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[    2.506895] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 648000
>[    2.506916] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[    2.506936] [drm:intel_dump_pipe_config [i915]] [CRTC:47:pipe B][modeset]
>[    2.506956] [drm:intel_dump_pipe_config [i915]] output_types: DP (0x80)
>[    2.506975] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[    2.506994] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5767168, gmch_n: 8388608, link_m: 240298, link_n: 262144, tu: 64
>[    2.507013] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[    2.507031] [drm:intel_dump_pipe_config [i915]] requested mode:
>[    2.507038] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[    2.507056] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[    2.507063] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[    2.507082] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[    2.507101] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1080, pixel rate 148500
>[    2.507119] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[    2.507137] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[    2.507154] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[    2.507172] [drm:intel_dump_pipe_config [i915]] dpll_hw_state: ctrl1: 0x0, cfgcr1: 0x0, cfgcr2: 0x0
>[    2.507190] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[    2.507208] [drm:intel_dump_pipe_config [i915]] [PLANE:38:plane 1B] disabled, scaler_id = -1
>[    2.507226] [drm:intel_dump_pipe_config [i915]] [PLANE:41:plane 2B] disabled, scaler_id = -1
>[    2.507243] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor B] disabled, scaler_id = -1
>[    2.507263] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[    2.507282] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[    2.507305] [drm:intel_find_shared_dpll [i915]] [CRTC:37:pipe A] allocated DPLL 0
>[    2.507325] [drm:intel_reference_shared_dpll [i915]] using DPLL 0 for pipe A
>[    2.507346] [drm:intel_find_shared_dpll [i915]] [CRTC:47:pipe B] allocated DPLL 1
>[    2.507365] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[    2.507395] [drm:intel_edp_backlight_off [i915]] 
>[    2.712169] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0
>[    2.712249] [drm:intel_disable_pipe [i915]] disabling pipe A
>[    2.720845] [drm:intel_edp_panel_off.part.31 [i915]] Turn eDP port A panel power off
>[    2.720917] [drm:intel_edp_panel_off.part.31 [i915]] Wait for panel power off time
>[    2.721017] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000003 control 00000060
>[    2.772226] [drm:wait_panel_status [i915]] Wait complete
>[    2.772246] [drm:intel_power_well_disable [i915]] disabling DDI A/E IO power well
>[    2.772272] [drm:intel_disable_shared_dpll [i915]] disable DPLL 0 (active 1, on? 1) for crtc 37
>[    2.772293] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 0
>[    2.772313] [drm:intel_power_well_enable [i915]] enabling power well 2
>[    2.772336] [drm:intel_disable_sagv [i915]] Disabling the SAGV
>[    2.772360] [drm:intel_atomic_commit_tail [i915]] [ENCODER:48:DDI A]
>[    2.772381] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI B]
>[    2.772400] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[    2.772419] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[    2.772438] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DDI C]
>[    2.772456] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST A]
>[    2.772474] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST B]
>[    2.772492] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI D]
>[    2.772509] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[    2.772527] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[    2.772546] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[    2.772564] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[    2.772583] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[    2.772601] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[    2.772622] [drm:intel_enable_shared_dpll [i915]] enable DPLL 0 (active 1, on? 0) for crtc 37
>[    2.772641] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 0
>[    2.772668] [drm:edp_panel_on [i915]] Turn eDP port A panel power on
>[    2.772714] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle
>[    2.781025] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010
>[    2.781048] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[    2.781069] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0
>[    2.781099] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[    3.388657] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 00000000 control 00000060
>[    3.388726] [drm:wait_panel_status [i915]] Wait complete
>[    3.388847] [drm:edp_panel_on [i915]] Wait for panel power on
>[    3.388943] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 00000063
>[    3.421052] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010
>[    3.421075] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[    3.421096] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1
>[    3.421152] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[    3.590919] [drm:wait_panel_status [i915]] Wait complete
>[    3.590940] [drm:intel_power_well_enable [i915]] enabling DDI A/E IO power well
>[    3.590992] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[    3.591101] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b
>[    3.592287] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[    3.592306] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[    3.592323] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[    3.592341] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[    3.593015] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[    3.593045] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[    3.594070] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[    3.594088] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:49:eDP-1] Link Training Passed at Link Rate = 270000, Lane count = 2
>[    3.594465] [drm:intel_enable_pipe [i915]] enabling pipe A
>[    3.594489] [drm:intel_edp_backlight_on [i915]] 
>[    3.594509] [drm:intel_panel_enable_backlight [i915]] pipe A
>[    3.594566] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 120000
>[    3.600157] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS
>[    3.600180] [drm:intel_fbc_enable [i915]] reserved 16588800 bytes of contiguous stolen space for FBC, threshold: 1
>[    3.600199] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[    3.611285] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 2, on? 0) for crtc 47
>[    3.611307] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[    3.611644] [drm:intel_power_well_enable [i915]] enabling DDI B IO power well
>[    3.612202] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[    3.613515] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[    3.614807] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[    3.616096] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[    3.617392] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[    3.618304] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[    3.619227] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[    3.619246] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[    3.619264] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[    3.619282] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[    3.638092] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[    3.638113] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[    3.655938] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[    3.656281] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:57:DP-1] Link Training Passed at Link Rate = 162000, Lane count = 4
>[    3.656662] [drm:intel_enable_pipe [i915]] enabling pipe B
>[    3.656719] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS
>[    3.673546] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:49:eDP-1]
>[    3.673572] [drm:intel_atomic_commit_tail [i915]] [CRTC:37:pipe A]
>[    3.673601] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[    3.673629] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:57:DP-1]
>[    3.673651] [drm:intel_atomic_commit_tail [i915]] [CRTC:47:pipe B]
>[    3.673677] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[    3.673688] Console: switching to colour frame buffer device 240x67
>[    3.692430] i915 0000:00:02.0: fb0: inteldrmfb frame buffer device
>[    3.708156] [drm:drm_fb_helper_hotplug_event.part.30 [drm_kms_helper]] 
>[    3.708158] [drm:drm_setup_crtcs [drm_kms_helper]] 
>[    3.708162] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:49:eDP-1]
>[    3.708217] [drm:intel_dp_detect [i915]] [CONNECTOR:49:eDP-1]
>[    3.708239] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>[    3.708266] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[    3.708304] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[    3.708745] [drm:drm_dp_read_desc [drm_kms_helper]] DP sink: OUI 00-1c-f8 dev-ID  HW-rev 0.1 SW-rev 1.22 quirks 0x0000
>[    3.709455] [drm:drm_add_edid_modes [drm]] ELD: no CEA Extension found
>[    3.709467] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:49:eDP-1] probed modes :
>[    3.709473] [drm:drm_mode_debug_printmodeline [drm]] Modeline 50:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[    3.709476] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:57:DP-1]
>[    3.709507] [drm:intel_dp_detect [i915]] [CONNECTOR:57:DP-1]
>[    3.709885] [drm:lspcon_wake_native_aux_ch [i915]] Native AUX CH up, DPCD version: 1.2
>[    3.709927] [drm:lspcon_resume [i915]] LSPCON recovering in PCON mode after 0 ms
>[    3.710341] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[    3.711516] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[    3.712699] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[    3.713980] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[    3.715262] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[    3.716140] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[    3.716549] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 00 00 04 00 0f 00 04
>[    3.717238] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>[    3.717264] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000
>[    3.717275] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000
>[    3.717648] [drm:drm_dp_read_desc [drm_kms_helper]] DP branch: OUI 00-60-ad dev-ID MC2800 HW-rev 2.2 SW-rev 1.70 quirks 0x0000
>[    3.717932] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[    3.718655] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[    3.719805] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[    3.721014] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[    3.722188] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[    3.723363] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[    3.724525] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[    3.725321] EXT4-fs (nvme0n1p2): INFO: recovery required on readonly filesystem
>[    3.725322] EXT4-fs (nvme0n1p2): write access will be enabled during recovery
>[    3.725724] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[    3.726908] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[    3.728079] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[    3.729386] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[    3.730700] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[    3.732000] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[    3.733310] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[    3.734618] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[    3.735925] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[    3.737232] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[    3.738533] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[    3.739700] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[    3.740877] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[    3.742062] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[    3.743237] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[    3.744547] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[    3.745855] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[    3.747163] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[    3.748479] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[    3.749789] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[    3.751098] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[    3.752407] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[    3.753706] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[    3.754745] [drm:drm_add_edid_modes [drm]] ELD monitor HP E232
>[    3.754764] [drm:drm_add_edid_modes [drm]] HDMI: latency present 0 0, video latency 0 0, audio latency 0 0
>[    3.754768] [drm:drm_add_edid_modes [drm]] ELD size 28, SAD count 0
>[    3.754772] [drm:drm_add_edid_modes [drm]] HDMI: DVI dual 0, max TMDS clock 170000 kHz
>[    3.754833] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:57:DP-1] probed modes :
>[    3.754839] [drm:drm_mode_debug_printmodeline [drm]] Modeline 73:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[    3.754843] [drm:drm_mode_debug_printmodeline [drm]] Modeline 95:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[    3.754847] [drm:drm_mode_debug_printmodeline [drm]] Modeline 75:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[    3.754851] [drm:drm_mode_debug_printmodeline [drm]] Modeline 80:"1680x1050" 60 119000 1680 1728 1760 1840 1050 1053 1059 1080 0x40 0x9
>[    3.754855] [drm:drm_mode_debug_printmodeline [drm]] Modeline 79:"1600x900" 60 108000 1600 1624 1704 1800 900 901 904 1000 0x40 0x5
>[    3.754859] [drm:drm_mode_debug_printmodeline [drm]] Modeline 83:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[    3.754863] [drm:drm_mode_debug_printmodeline [drm]] Modeline 81:"1440x900" 60 88750 1440 1488 1520 1600 900 903 909 926 0x40 0x9
>[    3.754867] [drm:drm_mode_debug_printmodeline [drm]] Modeline 82:"1280x800" 60 71000 1280 1328 1360 1440 800 803 809 823 0x40 0x9
>[    3.754870] [drm:drm_mode_debug_printmodeline [drm]] Modeline 76:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[    3.754874] [drm:drm_mode_debug_printmodeline [drm]] Modeline 97:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[    3.754877] [drm:drm_mode_debug_printmodeline [drm]] Modeline 77:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[    3.754881] [drm:drm_mode_debug_printmodeline [drm]] Modeline 86:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[    3.754885] [drm:drm_mode_debug_printmodeline [drm]] Modeline 84:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[    3.754889] [drm:drm_mode_debug_printmodeline [drm]] Modeline 93:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[    3.754892] [drm:drm_mode_debug_printmodeline [drm]] Modeline 98:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[    3.754896] [drm:drm_mode_debug_printmodeline [drm]] Modeline 78:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[    3.754899] [drm:drm_mode_debug_printmodeline [drm]] Modeline 99:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[    3.754903] [drm:drm_mode_debug_printmodeline [drm]] Modeline 85:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[    3.754906] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:61:DP-2]
>[    3.754921] [drm:intel_dp_detect [i915]] [CONNECTOR:61:DP-2]
>[    3.754935] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:61:DP-2] disconnected
>[    3.754937] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:64:HDMI-A-1]
>[    3.754951] [drm:intel_hdmi_detect [i915]] [CONNECTOR:64:HDMI-A-1]
>[    3.755256] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[    3.755268] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[    3.755565] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[    3.755570] [drm:drm_do_probe_ddc_edid [drm]] drm: skipping non-existent adapter i915 gmbus dpc
>[    3.755875] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[    3.755886] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[    3.756213] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[    3.756216] [drm:drm_dp_dual_mode_detect [drm_kms_helper]] DP dual mode HDMI ID:  (err -6)
>[    3.756218] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:64:HDMI-A-1] disconnected
>[    3.756221] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:67:DP-3]
>[    3.756233] [drm:intel_dp_detect [i915]] [CONNECTOR:67:DP-3]
>[    3.756247] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:67:DP-3] disconnected
>[    3.756249] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:70:HDMI-A-2]
>[    3.756260] [drm:intel_hdmi_detect [i915]] [CONNECTOR:70:HDMI-A-2]
>[    3.766829] random: crng init done
>[    3.766912] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0050 w(1)
>[    3.766927] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK on first message, retry
>[    3.777650] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0050 w(1)
>[    3.777657] [drm:drm_do_probe_ddc_edid [drm]] drm: skipping non-existent adapter i915 gmbus dpd
>[    3.788375] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0040 w(1)
>[    3.788390] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK on first message, retry
>[    3.799111] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0040 w(1)
>[    3.799117] [drm:drm_dp_dual_mode_detect [drm_kms_helper]] DP dual mode HDMI ID:  (err -6)
>[    3.799120] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:70:HDMI-A-2] disconnected
>[    3.799123] [drm:drm_setup_crtcs [drm_kms_helper]] connector 49 enabled? yes
>[    3.799125] [drm:drm_setup_crtcs [drm_kms_helper]] connector 57 enabled? yes
>[    3.799128] [drm:drm_setup_crtcs [drm_kms_helper]] connector 61 enabled? no
>[    3.799130] [drm:drm_setup_crtcs [drm_kms_helper]] connector 64 enabled? no
>[    3.799132] [drm:drm_setup_crtcs [drm_kms_helper]] connector 67 enabled? no
>[    3.799134] [drm:drm_setup_crtcs [drm_kms_helper]] connector 70 enabled? no
>[    3.799151] [drm:intel_fb_initial_config [i915]] Not using firmware configuration
>[    3.799153] [drm:drm_setup_crtcs [drm_kms_helper]] looking for cmdline mode on connector 49
>[    3.799156] [drm:drm_setup_crtcs [drm_kms_helper]] looking for preferred mode on connector 49 0
>[    3.799158] [drm:drm_setup_crtcs [drm_kms_helper]] found mode 1920x1080
>[    3.799160] [drm:drm_setup_crtcs [drm_kms_helper]] looking for cmdline mode on connector 57
>[    3.799162] [drm:drm_setup_crtcs [drm_kms_helper]] looking for preferred mode on connector 57 0
>[    3.799164] [drm:drm_setup_crtcs [drm_kms_helper]] found mode 1920x1080
>[    3.799166] [drm:drm_setup_crtcs [drm_kms_helper]] picking CRTCs for 1920x1080 config
>[    3.799171] [drm:drm_setup_crtcs [drm_kms_helper]] desired mode 1920x1080 set on crtc 37 (0,0)
>[    3.799173] [drm:drm_setup_crtcs [drm_kms_helper]] desired mode 1920x1080 set on crtc 47 (0,0)
>[    3.811210] [drm:drm_fb_helper_hotplug_event.part.30 [drm_kms_helper]] 
>[    3.811213] [drm:drm_setup_crtcs [drm_kms_helper]] 
>[    3.811216] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:49:eDP-1]
>[    3.811233] [drm:intel_dp_detect [i915]] [CONNECTOR:49:eDP-1]
>[    3.811249] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>[    3.811263] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[    3.811276] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[    3.811683] [drm:drm_dp_read_desc [drm_kms_helper]] DP sink: OUI 00-1c-f8 dev-ID  HW-rev 0.1 SW-rev 1.22 quirks 0x0000
>[    3.812387] [drm:drm_add_edid_modes [drm]] ELD: no CEA Extension found
>[    3.812412] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:49:eDP-1] probed modes :
>[    3.812417] [drm:drm_mode_debug_printmodeline [drm]] Modeline 50:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[    3.812420] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:57:DP-1]
>[    3.812435] [drm:intel_dp_detect [i915]] [CONNECTOR:57:DP-1]
>[    3.812734] [drm:lspcon_wake_native_aux_ch [i915]] Native AUX CH up, DPCD version: 1.2
>[    3.812772] [drm:lspcon_resume [i915]] LSPCON recovering in PCON mode after 0 ms
>[    3.813185] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[    3.814363] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[    3.815546] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[    3.816723] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[    3.817909] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[    3.818703] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[    3.819115] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 00 00 04 00 0f 00 04
>[    3.819790] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>[    3.819803] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000
>[    3.819815] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000
>[    3.820178] [drm:drm_dp_read_desc [drm_kms_helper]] DP branch: OUI 00-60-ad dev-ID MC2800 HW-rev 2.2 SW-rev 1.70 quirks 0x0000
>[    3.820478] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[    3.821204] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[    3.822390] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[    3.823575] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[    3.824751] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[    3.825939] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[    3.827109] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[    3.828329] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[    3.829095] EXT4-fs (nvme0n1p2): recovery complete
>[    3.829484] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[    3.830650] EXT4-fs (nvme0n1p2): mounted filesystem with ordered data mode. Opts: (null)
>[    3.830667] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[    3.831975] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[    3.833286] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[    3.834567] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[    3.835843] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[    3.837153] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[    3.838429] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[    3.839702] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[    3.841002] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[    3.842173] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[    3.843349] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[    3.844535] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[    3.845710] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[    3.847016] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[    3.848328] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[    3.849634] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[    3.850961] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[    3.852261] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[    3.853578] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[    3.854885] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[    3.856177] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[    3.857213] [drm:drm_add_edid_modes [drm]] ELD monitor HP E232
>[    3.857233] [drm:drm_add_edid_modes [drm]] HDMI: latency present 0 0, video latency 0 0, audio latency 0 0
>[    3.857237] [drm:drm_add_edid_modes [drm]] ELD size 28, SAD count 0
>[    3.857242] [drm:drm_add_edid_modes [drm]] HDMI: DVI dual 0, max TMDS clock 170000 kHz
>[    3.857303] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:57:DP-1] probed modes :
>[    3.857309] [drm:drm_mode_debug_printmodeline [drm]] Modeline 73:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[    3.857314] [drm:drm_mode_debug_printmodeline [drm]] Modeline 95:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[    3.857318] [drm:drm_mode_debug_printmodeline [drm]] Modeline 75:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[    3.857322] [drm:drm_mode_debug_printmodeline [drm]] Modeline 80:"1680x1050" 60 119000 1680 1728 1760 1840 1050 1053 1059 1080 0x40 0x9
>[    3.857326] [drm:drm_mode_debug_printmodeline [drm]] Modeline 79:"1600x900" 60 108000 1600 1624 1704 1800 900 901 904 1000 0x40 0x5
>[    3.857331] [drm:drm_mode_debug_printmodeline [drm]] Modeline 83:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[    3.857334] [drm:drm_mode_debug_printmodeline [drm]] Modeline 81:"1440x900" 60 88750 1440 1488 1520 1600 900 903 909 926 0x40 0x9
>[    3.857338] [drm:drm_mode_debug_printmodeline [drm]] Modeline 82:"1280x800" 60 71000 1280 1328 1360 1440 800 803 809 823 0x40 0x9
>[    3.857342] [drm:drm_mode_debug_printmodeline [drm]] Modeline 76:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[    3.857346] [drm:drm_mode_debug_printmodeline [drm]] Modeline 97:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[    3.857350] [drm:drm_mode_debug_printmodeline [drm]] Modeline 77:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[    3.857354] [drm:drm_mode_debug_printmodeline [drm]] Modeline 86:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[    3.857358] [drm:drm_mode_debug_printmodeline [drm]] Modeline 84:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[    3.857362] [drm:drm_mode_debug_printmodeline [drm]] Modeline 93:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[    3.857365] [drm:drm_mode_debug_printmodeline [drm]] Modeline 98:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[    3.857369] [drm:drm_mode_debug_printmodeline [drm]] Modeline 78:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[    3.857373] [drm:drm_mode_debug_printmodeline [drm]] Modeline 99:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[    3.857377] [drm:drm_mode_debug_printmodeline [drm]] Modeline 85:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[    3.857379] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:61:DP-2]
>[    3.857397] [drm:intel_dp_detect [i915]] [CONNECTOR:61:DP-2]
>[    3.857411] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:61:DP-2] disconnected
>[    3.857414] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:64:HDMI-A-1]
>[    3.857428] [drm:intel_hdmi_detect [i915]] [CONNECTOR:64:HDMI-A-1]
>[    3.857730] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[    3.857742] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[    3.858049] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[    3.858055] [drm:drm_do_probe_ddc_edid [drm]] drm: skipping non-existent adapter i915 gmbus dpc
>[    3.858363] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[    3.858374] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[    3.858682] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[    3.858686] [drm:drm_dp_dual_mode_detect [drm_kms_helper]] DP dual mode HDMI ID:  (err -6)
>[    3.858688] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:64:HDMI-A-1] disconnected
>[    3.858691] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:67:DP-3]
>[    3.858703] [drm:intel_dp_detect [i915]] [CONNECTOR:67:DP-3]
>[    3.858715] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:67:DP-3] disconnected
>[    3.858718] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:70:HDMI-A-2]
>[    3.858729] [drm:intel_hdmi_detect [i915]] [CONNECTOR:70:HDMI-A-2]
>[    3.869386] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0050 w(1)
>[    3.869401] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK on first message, retry
>[    3.880222] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0050 w(1)
>[    3.880228] [drm:drm_do_probe_ddc_edid [drm]] drm: skipping non-existent adapter i915 gmbus dpd
>[    3.890374] ip_tables: (C) 2000-2006 Netfilter Core Team
>[    3.890885] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0040 w(1)
>[    3.890899] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK on first message, retry
>[    3.901788] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0040 w(1)
>[    3.901792] [drm:drm_dp_dual_mode_detect [drm_kms_helper]] DP dual mode HDMI ID:  (err -6)
>[    3.901795] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:70:HDMI-A-2] disconnected
>[    3.901798] [drm:drm_setup_crtcs [drm_kms_helper]] connector 49 enabled? yes
>[    3.901888] [drm:drm_setup_crtcs [drm_kms_helper]] connector 57 enabled? yes
>[    3.901890] [drm:drm_setup_crtcs [drm_kms_helper]] connector 61 enabled? no
>[    3.901892] [drm:drm_setup_crtcs [drm_kms_helper]] connector 64 enabled? no
>[    3.901894] [drm:drm_setup_crtcs [drm_kms_helper]] connector 67 enabled? no
>[    3.901896] [drm:drm_setup_crtcs [drm_kms_helper]] connector 70 enabled? no
>[    3.901911] [drm:intel_fb_initial_config [i915]] Not using firmware configuration
>[    3.901913] [drm:drm_setup_crtcs [drm_kms_helper]] looking for cmdline mode on connector 49
>[    3.902003] [drm:drm_setup_crtcs [drm_kms_helper]] looking for preferred mode on connector 49 0
>[    3.902005] [drm:drm_setup_crtcs [drm_kms_helper]] found mode 1920x1080
>[    3.902007] [drm:drm_setup_crtcs [drm_kms_helper]] looking for cmdline mode on connector 57
>[    3.902009] [drm:drm_setup_crtcs [drm_kms_helper]] looking for preferred mode on connector 57 0
>[    3.902011] [drm:drm_setup_crtcs [drm_kms_helper]] found mode 1920x1080
>[    3.902013] [drm:drm_setup_crtcs [drm_kms_helper]] picking CRTCs for 1920x1080 config
>[    3.902017] [drm:drm_setup_crtcs [drm_kms_helper]] desired mode 1920x1080 set on crtc 37 (0,0)
>[    3.902020] [drm:drm_setup_crtcs [drm_kms_helper]] desired mode 1920x1080 set on crtc 47 (0,0)
>[    3.913558] systemd[1]: systemd 231 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ -LZ4 +SECCOMP +BLKID +ELFUTILS +KMOD +IDN)
>[    3.932167] systemd[1]: Detected architecture x86-64.
>[    3.932332] systemd[1]: Set hostname to <CFL-1>.
>[    3.983125] systemd[1]: Created slice System Slice.
>[    3.983199] systemd[1]: Created slice system-systemd\x2dfsck.slice.
>[    3.983219] systemd[1]: Listening on udev Control Socket.
>[    3.983224] systemd[1]: Reached target Encrypted Volumes.
>[    3.983265] systemd[1]: Created slice User and Session Slice.
>[    3.983270] systemd[1]: Reached target Slices.
>[    3.983281] systemd[1]: Listening on udev Kernel Socket.
>[    3.994925] lp: driver loaded but no devices found
>[    3.996232] ppdev: user-space parallel port driver
>[    4.023214] EXT4-fs (nvme0n1p2): re-mounted. Opts: (null)
>[    4.026216] systemd-journald[306]: Received request to flush runtime journal from PID 1
>[    4.109551] (NULL device *): hwmon_device_register() is deprecated. Please convert the driver to use hwmon_device_register_with_info().
>[    4.119198] [drm:intel_backlight_device_update_status [i915]] updating intel_backlight, brightness=120000/120000
>[    4.119199] intel-lpss 0000:00:15.0: enabling device (0000 -> 0002)
>[    4.119223] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 120000
>[    4.140875] RAPL PMU: API unit is 2^-32 Joules, 5 fixed counters, 655360 ms ovfl timer
>[    4.140875] RAPL PMU: hw unit of domain pp0-core 2^-14 Joules
>[    4.140876] RAPL PMU: hw unit of domain package 2^-14 Joules
>[    4.140876] RAPL PMU: hw unit of domain dram 2^-14 Joules
>[    4.140877] RAPL PMU: hw unit of domain pp1-gpu 2^-14 Joules
>[    4.140877] RAPL PMU: hw unit of domain psys 2^-14 Joules
>[    4.143092] idma64 idma64.0: Found Intel integrated DMA 64-bit
>[    4.143587] cfg80211: Loading compiled-in X.509 certificates for regulatory database
>[    4.150007] AVX2 version of gcm_enc/dec engaged.
>[    4.150007] AES CTR mode by8 optimization enabled
>[    4.153283] intel-lpss 0000:00:15.1: enabling device (0000 -> 0002)
>[    4.153326] cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
>[    4.153490] idma64 idma64.1: Found Intel integrated DMA 64-bit
>[    4.153801] Bluetooth: Core ver 2.22
>[    4.153808] NET: Registered protocol family 31
>[    4.153808] Bluetooth: HCI device and connection manager initialized
>[    4.153809] Bluetooth: HCI socket layer initialized
>[    4.153810] Bluetooth: L2CAP socket layer initialized
>[    4.153813] Bluetooth: SCO socket layer initialized
>[    4.153997] platform regulatory.0: Direct firmware load for regulatory.db failed with error -2
>[    4.153998] cfg80211: failed to load regulatory.db
>[    4.159097] Intel(R) Wireless WiFi driver for Linux
>[    4.159097] Copyright(c) 2003- 2015 Intel Corporation
>[    4.159579] usbcore: registered new interface driver btusb
>[    4.162347] shpchp: Standard Hot Plug PCI Controller Driver version: 0.4
>[    4.164132] Bluetooth: hci0: Bootloader revision 0.1 build 42 week 52 2015
>[    4.164507] intel-lpss 0000:00:1e.0: enabling device (0000 -> 0002)
>[    4.164719] idma64 idma64.2: Found Intel integrated DMA 64-bit
>[    4.164924] iwlwifi 0000:00:14.3: enabling device (0000 -> 0002)
>[    4.165067] Bluetooth: hci0: Device revision is 2
>[    4.165067] Bluetooth: hci0: Secure boot is enabled
>[    4.165067] Bluetooth: hci0: OTP lock is disabled
>[    4.165068] Bluetooth: hci0: API lock is disabled
>[    4.165068] Bluetooth: hci0: Debug lock is disabled
>[    4.165069] Bluetooth: hci0: Minimum firmware build 1 week 10 2014
>[    4.166416] iwlwifi 0000:00:14.3: Direct firmware load for iwlwifi-9000-pu-b0-jf-b0-34.ucode failed with error -2
>[    4.166421] iwlwifi 0000:00:14.3: Direct firmware load for iwlwifi-9000-pu-b0-jf-b0-33.ucode failed with error -2
>[    4.166425] iwlwifi 0000:00:14.3: Direct firmware load for iwlwifi-9000-pu-b0-jf-b0-32.ucode failed with error -2
>[    4.166429] iwlwifi 0000:00:14.3: Direct firmware load for iwlwifi-9000-pu-b0-jf-b0-31.ucode failed with error -2
>[    4.166434] iwlwifi 0000:00:14.3: Direct firmware load for iwlwifi-9000-pu-b0-jf-b0-30.ucode failed with error -2
>[    4.166434] iwlwifi 0000:00:14.3: no suitable firmware found!
>[    4.166435] iwlwifi 0000:00:14.3: minimum version required: iwlwifi-9000-pu-b0-jf-b0-30
>[    4.166435] iwlwifi 0000:00:14.3: maximum version supported: iwlwifi-9000-pu-b0-jf-b0-34
>[    4.166436] iwlwifi 0000:00:14.3: check git://git.kernel.org/pub/scm/linux/kernel/git/firmware/linux-firmware.git
>[    4.166972] bluetooth hci0: Direct firmware load for intel/ibt-17-16-1.sfi failed with error -2
>[    4.166974] Bluetooth: hci0: Failed to load Intel firmware file (-2)
>[    4.174629] snd_hda_intel 0000:00:1f.3: enabling device (0000 -> 0002)
>[    4.180477] snd_hda_intel 0000:00:1f.3: bound 0000:00:02.0 (ops i915_audio_component_bind_ops [i915])
>[    4.193301] FAT-fs (nvme0n1p1): Volume was not properly unmounted. Some data may be corrupt. Please run fsck.
>[    4.194428] intel_rapl: Found RAPL domain package
>[    4.194429] intel_rapl: Found RAPL domain core
>[    4.194429] intel_rapl: Found RAPL domain uncore
>[    4.194430] intel_rapl: Found RAPL domain dram
>[    4.196590] Adding 16642044k swap on /dev/nvme0n1p3.  Priority:-2 extents:1 across:16642044k SSFS
>[    4.210546] snd_hda_codec_realtek hdaudioC0D0: autoconfig for ALC700: line_outs=1 (0x16/0x0/0x0/0x0/0x0) type:line
>[    4.210547] snd_hda_codec_realtek hdaudioC0D0:    speaker_outs=1 (0x15/0x0/0x0/0x0/0x0)
>[    4.210548] snd_hda_codec_realtek hdaudioC0D0:    hp_outs=1 (0x21/0x0/0x0/0x0/0x0)
>[    4.210548] snd_hda_codec_realtek hdaudioC0D0:    mono: mono_out=0x0
>[    4.210549] snd_hda_codec_realtek hdaudioC0D0:    inputs:
>[    4.210549] snd_hda_codec_realtek hdaudioC0D0:      Rear Mic=0x1b
>[    4.210550] snd_hda_codec_realtek hdaudioC0D0:      Front Mic=0x19
>[    4.228164] audit: type=1400 audit(1512145720.527:2): apparmor="STATUS" operation="profile_load" profile="unconfined" name="unity8-dash" pid=717 comm="apparmor_parser"
>[    4.228181] audit: type=1400 audit(1512145720.527:3): apparmor="STATUS" operation="profile_load" profile="unconfined" name="udm-extractor" pid=721 comm="apparmor_parser"
>[    4.228464] audit: type=1400 audit(1512145720.527:4): apparmor="STATUS" operation="profile_load" profile="unconfined" name="/usr/lib/snapd/snap-confine" pid=719 comm="apparmor_parser"
>[    4.228465] audit: type=1400 audit(1512145720.527:5): apparmor="STATUS" operation="profile_load" profile="unconfined" name="/usr/lib/snapd/snap-confine//mount-namespace-capture-helper" pid=719 comm="apparmor_parser"
>[    4.228527] audit: type=1400 audit(1512145720.527:6): apparmor="STATUS" operation="profile_load" profile="unconfined" name="/usr/sbin/cups-browsed" pid=722 comm="apparmor_parser"
>[    4.228735] audit: type=1400 audit(1512145720.527:7): apparmor="STATUS" operation="profile_load" profile="unconfined" name="/usr/sbin/ippusbxd" pid=724 comm="apparmor_parser"
>[    4.228850] audit: type=1400 audit(1512145720.527:8): apparmor="STATUS" operation="profile_load" profile="unconfined" name="/usr/sbin/tcpdump" pid=726 comm="apparmor_parser"
>[    4.229001] audit: type=1400 audit(1512145720.527:9): apparmor="STATUS" operation="profile_load" profile="unconfined" name="/usr/lib/lightdm/lightdm-guest-session" pid=713 comm="apparmor_parser"
>[    4.229003] audit: type=1400 audit(1512145720.527:10): apparmor="STATUS" operation="profile_load" profile="unconfined" name="/usr/lib/lightdm/lightdm-guest-session//chromium" pid=713 comm="apparmor_parser"
>[    4.296215] dw-apb-uart.2: ttyS4 at MMIO 0xb1242000 (irq = 20, base_baud = 7500000) is a 16550A
>[    4.388877] new mount options do not match the existing superblock, will be ignored
>[    4.413018] Bluetooth: BNEP (Ethernet Emulation) ver 1.3
>[    4.413018] Bluetooth: BNEP filters: protocol multicast
>[    4.413020] Bluetooth: BNEP socket layer initialized
>[    4.446718] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[    4.446734] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[    4.446754] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[    4.447164] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 00 00 04 00 0f 00 04
>[    4.447467] [drm:i915_hotplug_work_func [i915]] running encoder hotplug functions
>[    4.447489] [drm:i915_hotplug_work_func [i915]] Connector DP-1 (pin 5) received hotplug event.
>[    4.447510] [drm:intel_dp_detect [i915]] [CONNECTOR:57:DP-1]
>[    4.447816] [drm:lspcon_wake_native_aux_ch [i915]] Native AUX CH up, DPCD version: 1.2
>[    4.447844] [drm:lspcon_resume [i915]] LSPCON recovering in PCON mode after 0 ms
>[    4.448269] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[    4.449972] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[    4.451266] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[    4.452413] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[    4.453570] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[    4.454330] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[    4.454735] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 00 00 04 00 0f 00 04
>[    4.455026] [drm:i915_hotplug_work_func [i915]] [CONNECTOR:57:DP-1] status updated from connected to disconnected
>[    4.455042] [drm:drm_fb_helper_hotplug_event.part.30 [drm_kms_helper]] 
>[    4.455045] [drm:drm_setup_crtcs [drm_kms_helper]] 
>[    4.455049] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:49:eDP-1]
>[    4.455063] [drm:intel_dp_detect [i915]] [CONNECTOR:49:eDP-1]
>[    4.455078] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>[    4.455096] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[    4.455113] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[    4.455508] [drm:drm_dp_read_desc [drm_kms_helper]] DP sink: OUI 00-1c-f8 dev-ID  HW-rev 0.1 SW-rev 1.22 quirks 0x0000
>[    4.456169] [drm:drm_add_edid_modes [drm]] ELD: no CEA Extension found
>[    4.456182] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:49:eDP-1] probed modes :
>[    4.456188] [drm:drm_mode_debug_printmodeline [drm]] Modeline 50:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[    4.456191] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:57:DP-1]
>[    4.456211] [drm:intel_dp_detect [i915]] [CONNECTOR:57:DP-1]
>[    4.456515] [drm:lspcon_wake_native_aux_ch [i915]] Native AUX CH up, DPCD version: 1.2
>[    4.456538] [drm:lspcon_resume [i915]] LSPCON recovering in PCON mode after 0 ms
>[    4.456952] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[    4.458157] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[    4.459311] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[    4.460461] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[    4.461619] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[    4.462365] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[    4.462763] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 00 00 04 00 0f 00 04
>[    4.463039] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:57:DP-1] disconnected
>[    4.463046] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:61:DP-2]
>[    4.463061] [drm:intel_dp_detect [i915]] [CONNECTOR:61:DP-2]
>[    4.463075] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:61:DP-2] disconnected
>[    4.463078] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:64:HDMI-A-1]
>[    4.463091] [drm:intel_hdmi_detect [i915]] [CONNECTOR:64:HDMI-A-1]
>[    4.463399] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[    4.463411] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[    4.463720] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[    4.463728] [drm:drm_do_probe_ddc_edid [drm]] drm: skipping non-existent adapter i915 gmbus dpc
>[    4.464033] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[    4.464055] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[    4.464386] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[    4.464391] [drm:drm_dp_dual_mode_detect [drm_kms_helper]] DP dual mode HDMI ID:  (err -6)
>[    4.464393] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:64:HDMI-A-1] disconnected
>[    4.464396] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:67:DP-3]
>[    4.464409] [drm:intel_dp_detect [i915]] [CONNECTOR:67:DP-3]
>[    4.464421] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:67:DP-3] disconnected
>[    4.464423] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:70:HDMI-A-2]
>[    4.464435] [drm:intel_hdmi_detect [i915]] [CONNECTOR:70:HDMI-A-2]
>[    4.474719] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0050 w(1)
>[    4.474740] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK on first message, retry
>[    4.484869] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0050 w(1)
>[    4.484879] [drm:drm_do_probe_ddc_edid [drm]] drm: skipping non-existent adapter i915 gmbus dpd
>[    4.487029] ip6_tables: (C) 2000-2006 Netfilter Core Team
>[    4.494836] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0040 w(1)
>[    4.494851] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK on first message, retry
>[    4.504916] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0040 w(1)
>[    4.504923] [drm:drm_dp_dual_mode_detect [drm_kms_helper]] DP dual mode HDMI ID:  (err -6)
>[    4.504927] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:70:HDMI-A-2] disconnected
>[    4.504930] [drm:drm_setup_crtcs [drm_kms_helper]] connector 49 enabled? yes
>[    4.504933] [drm:drm_setup_crtcs [drm_kms_helper]] connector 57 enabled? no
>[    4.504935] [drm:drm_setup_crtcs [drm_kms_helper]] connector 61 enabled? no
>[    4.504937] [drm:drm_setup_crtcs [drm_kms_helper]] connector 64 enabled? no
>[    4.504939] [drm:drm_setup_crtcs [drm_kms_helper]] connector 67 enabled? no
>[    4.504942] [drm:drm_setup_crtcs [drm_kms_helper]] connector 70 enabled? no
>[    4.504959] [drm:intel_fb_initial_config [i915]] Not using firmware configuration
>[    4.504962] [drm:drm_setup_crtcs [drm_kms_helper]] looking for cmdline mode on connector 49
>[    4.504965] [drm:drm_setup_crtcs [drm_kms_helper]] looking for preferred mode on connector 49 0
>[    4.504967] [drm:drm_setup_crtcs [drm_kms_helper]] found mode 1920x1080
>[    4.504969] [drm:drm_setup_crtcs [drm_kms_helper]] picking CRTCs for 1920x1080 config
>[    4.504973] [drm:drm_setup_crtcs [drm_kms_helper]] desired mode 1920x1080 set on crtc 37 (0,0)
>[    4.505000] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[    4.505014] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[    4.505045] [drm:intel_disable_pipe [i915]] disabling pipe B
>[    4.507845] [drm:intel_power_well_disable [i915]] disabling DDI B IO power well
>[    4.507862] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 2, on? 1) for crtc 47
>[    4.507877] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[    4.507899] [drm:intel_atomic_commit_tail [i915]] [ENCODER:48:DDI A]
>[    4.507912] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI B]
>[    4.507925] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[    4.507937] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[    4.507949] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DDI C]
>[    4.507961] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST A]
>[    4.507972] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST B]
>[    4.507983] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI D]
>[    4.507994] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[    4.508008] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[    4.508030] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:57:DP-1]
>[    4.508046] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[    4.508059] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[    4.508073] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[    4.508086] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[    4.511203] [drm:intel_atomic_commit_tail [i915]] [CRTC:47:pipe B]
>[    4.511218] [drm:intel_enable_sagv [i915]] Enabling the SAGV
>[    4.645701] IPv6: ADDRCONF(NETDEV_UP): enp0s31f6: link is not ready
>[    4.702055] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[    4.702079] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[    4.702105] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[    4.702521] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 00 00 04 00 0f 00 04
>[    4.703206] [drm:i915_hotplug_work_func [i915]] running encoder hotplug functions
>[    4.703223] [drm:i915_hotplug_work_func [i915]] Connector DP-1 (pin 5) received hotplug event.
>[    4.703237] [drm:intel_dp_detect [i915]] [CONNECTOR:57:DP-1]
>[    4.703546] [drm:lspcon_wake_native_aux_ch [i915]] Native AUX CH up, DPCD version: 1.2
>[    4.703571] [drm:lspcon_resume [i915]] LSPCON recovering in PCON mode after 0 ms
>[    4.703988] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[    4.705170] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[    4.706355] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[    4.707530] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[    4.708683] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[    4.709427] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[    4.709828] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 00 00 04 00 0f 00 04
>[    4.710515] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>[    4.710530] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000
>[    4.710543] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000
>[    4.710911] [drm:drm_dp_read_desc [drm_kms_helper]] DP branch: OUI 00-60-ad dev-ID MC2800 HW-rev 2.2 SW-rev 1.70 quirks 0x0000
>[    4.711204] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[    4.711936] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[    4.713095] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[    4.714272] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[    4.715438] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[    4.716607] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[    4.717779] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[    4.718931] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[    4.720081] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[    4.721256] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[    4.722567] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[    4.723888] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[    4.725194] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[    4.726531] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[    4.727857] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[    4.729151] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[    4.730458] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[    4.731791] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[    4.732970] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[    4.734153] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[    4.735308] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[    4.736486] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[    4.737762] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[    4.739046] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[    4.740371] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[    4.741656] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[    4.742939] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[    4.744222] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[    4.745504] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[    4.746776] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[    4.747808] [drm:i915_hotplug_work_func [i915]] [CONNECTOR:57:DP-1] status updated from disconnected to connected
>[    4.747824] [drm:drm_fb_helper_hotplug_event.part.30 [drm_kms_helper]] 
>[    4.747828] [drm:drm_setup_crtcs [drm_kms_helper]] 
>[    4.747832] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:49:eDP-1]
>[    4.747855] [drm:intel_dp_detect [i915]] [CONNECTOR:49:eDP-1]
>[    4.747877] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>[    4.747896] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[    4.747914] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[    4.748312] [drm:drm_dp_read_desc [drm_kms_helper]] DP sink: OUI 00-1c-f8 dev-ID  HW-rev 0.1 SW-rev 1.22 quirks 0x0000
>[    4.748973] [drm:drm_add_edid_modes [drm]] ELD: no CEA Extension found
>[    4.748988] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:49:eDP-1] probed modes :
>[    4.748997] [drm:drm_mode_debug_printmodeline [drm]] Modeline 50:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[    4.749002] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:57:DP-1]
>[    4.749023] [drm:intel_dp_detect [i915]] [CONNECTOR:57:DP-1]
>[    4.749335] [drm:lspcon_wake_native_aux_ch [i915]] Native AUX CH up, DPCD version: 1.2
>[    4.749367] [drm:lspcon_resume [i915]] LSPCON recovering in PCON mode after 0 ms
>[    4.749781] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[    4.750938] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[    4.752114] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[    4.753289] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[    4.754471] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[    4.755237] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[    4.755632] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 00 00 04 00 0f 00 04
>[    4.756308] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>[    4.756322] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000
>[    4.756334] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000
>[    4.756695] [drm:drm_dp_read_desc [drm_kms_helper]] DP branch: OUI 00-60-ad dev-ID MC2800 HW-rev 2.2 SW-rev 1.70 quirks 0x0000
>[    4.756980] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[    4.757708] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[    4.758885] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[    4.760060] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[    4.761235] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[    4.762420] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[    4.763581] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[    4.764730] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[    4.765915] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[    4.767082] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[    4.768389] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[    4.769696] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[    4.771008] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[    4.772319] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[    4.773624] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[    4.774932] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[    4.776231] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[    4.777530] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[    4.778700] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[    4.779875] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[    4.781057] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[    4.782231] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[    4.783539] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[    4.784760] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[    4.786067] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[    4.787376] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[    4.788700] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[    4.790006] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[    4.791312] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[    4.792619] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[    4.793657] [drm:drm_add_edid_modes [drm]] ELD monitor HP E232
>[    4.793663] [drm:drm_add_edid_modes [drm]] HDMI: latency present 0 0, video latency 0 0, audio latency 0 0
>[    4.793668] [drm:drm_add_edid_modes [drm]] ELD size 28, SAD count 0
>[    4.793672] [drm:drm_add_edid_modes [drm]] HDMI: DVI dual 0, max TMDS clock 170000 kHz
>[    4.793736] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:57:DP-1] probed modes :
>[    4.793742] [drm:drm_mode_debug_printmodeline [drm]] Modeline 74:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[    4.793747] [drm:drm_mode_debug_printmodeline [drm]] Modeline 97:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[    4.793751] [drm:drm_mode_debug_printmodeline [drm]] Modeline 76:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[    4.793756] [drm:drm_mode_debug_printmodeline [drm]] Modeline 81:"1680x1050" 60 119000 1680 1728 1760 1840 1050 1053 1059 1080 0x40 0x9
>[    4.793760] [drm:drm_mode_debug_printmodeline [drm]] Modeline 80:"1600x900" 60 108000 1600 1624 1704 1800 900 901 904 1000 0x40 0x5
>[    4.793764] [drm:drm_mode_debug_printmodeline [drm]] Modeline 84:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[    4.793768] [drm:drm_mode_debug_printmodeline [drm]] Modeline 82:"1440x900" 60 88750 1440 1488 1520 1600 900 903 909 926 0x40 0x9
>[    4.793772] [drm:drm_mode_debug_printmodeline [drm]] Modeline 83:"1280x800" 60 71000 1280 1328 1360 1440 800 803 809 823 0x40 0x9
>[    4.793776] [drm:drm_mode_debug_printmodeline [drm]] Modeline 77:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[    4.793780] [drm:drm_mode_debug_printmodeline [drm]] Modeline 99:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[    4.793784] [drm:drm_mode_debug_printmodeline [drm]] Modeline 78:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[    4.793788] [drm:drm_mode_debug_printmodeline [drm]] Modeline 87:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[    4.793791] [drm:drm_mode_debug_printmodeline [drm]] Modeline 85:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[    4.793795] [drm:drm_mode_debug_printmodeline [drm]] Modeline 95:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[    4.793799] [drm:drm_mode_debug_printmodeline [drm]] Modeline 100:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[    4.793803] [drm:drm_mode_debug_printmodeline [drm]] Modeline 79:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[    4.793807] [drm:drm_mode_debug_printmodeline [drm]] Modeline 101:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[    4.793811] [drm:drm_mode_debug_printmodeline [drm]] Modeline 86:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[    4.793814] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:61:DP-2]
>[    4.793834] [drm:intel_dp_detect [i915]] [CONNECTOR:61:DP-2]
>[    4.793849] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:61:DP-2] disconnected
>[    4.793852] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:64:HDMI-A-1]
>[    4.793866] [drm:intel_hdmi_detect [i915]] [CONNECTOR:64:HDMI-A-1]
>[    4.794183] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[    4.794196] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[    4.794510] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[    4.794517] [drm:drm_do_probe_ddc_edid [drm]] drm: skipping non-existent adapter i915 gmbus dpc
>[    4.794832] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[    4.794843] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[    4.795155] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[    4.795158] [drm:drm_dp_dual_mode_detect [drm_kms_helper]] DP dual mode HDMI ID:  (err -6)
>[    4.795161] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:64:HDMI-A-1] disconnected
>[    4.795163] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:67:DP-3]
>[    4.795176] [drm:intel_dp_detect [i915]] [CONNECTOR:67:DP-3]
>[    4.795190] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:67:DP-3] disconnected
>[    4.795192] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:70:HDMI-A-2]
>[    4.795204] [drm:intel_hdmi_detect [i915]] [CONNECTOR:70:HDMI-A-2]
>[    4.805623] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0050 w(1)
>[    4.805638] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK on first message, retry
>[    4.815545] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0050 w(1)
>[    4.815553] [drm:drm_do_probe_ddc_edid [drm]] drm: skipping non-existent adapter i915 gmbus dpd
>[    4.826800] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0040 w(1)
>[    4.826815] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK on first message, retry
>[    4.837325] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0040 w(1)
>[    4.837331] [drm:drm_dp_dual_mode_detect [drm_kms_helper]] DP dual mode HDMI ID:  (err -6)
>[    4.837335] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:70:HDMI-A-2] disconnected
>[    4.837339] [drm:drm_setup_crtcs [drm_kms_helper]] connector 49 enabled? yes
>[    4.837341] [drm:drm_setup_crtcs [drm_kms_helper]] connector 57 enabled? yes
>[    4.837344] [drm:drm_setup_crtcs [drm_kms_helper]] connector 61 enabled? no
>[    4.837346] [drm:drm_setup_crtcs [drm_kms_helper]] connector 64 enabled? no
>[    4.837349] [drm:drm_setup_crtcs [drm_kms_helper]] connector 67 enabled? no
>[    4.837351] [drm:drm_setup_crtcs [drm_kms_helper]] connector 70 enabled? no
>[    4.837368] [drm:intel_fb_initial_config [i915]] Not using firmware configuration
>[    4.837371] [drm:drm_setup_crtcs [drm_kms_helper]] looking for cmdline mode on connector 49
>[    4.837373] [drm:drm_setup_crtcs [drm_kms_helper]] looking for preferred mode on connector 49 0
>[    4.837376] [drm:drm_setup_crtcs [drm_kms_helper]] found mode 1920x1080
>[    4.837378] [drm:drm_setup_crtcs [drm_kms_helper]] looking for cmdline mode on connector 57
>[    4.837380] [drm:drm_setup_crtcs [drm_kms_helper]] looking for preferred mode on connector 57 0
>[    4.837383] [drm:drm_setup_crtcs [drm_kms_helper]] found mode 1920x1080
>[    4.837385] [drm:drm_setup_crtcs [drm_kms_helper]] picking CRTCs for 1920x1080 config
>[    4.837390] [drm:drm_setup_crtcs [drm_kms_helper]] desired mode 1920x1080 set on crtc 37 (0,0)
>[    4.837392] [drm:drm_setup_crtcs [drm_kms_helper]] desired mode 1920x1080 set on crtc 47 (0,0)
>[    4.837420] [drm:intel_atomic_check [i915]] [CONNECTOR:57:DP-1] checking for sink bpp constrains
>[    4.837436] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[    4.837452] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 148500KHz
>[    4.837467] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[    4.837481] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 648000
>[    4.837497] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[    4.837512] [drm:intel_dump_pipe_config [i915]] [CRTC:47:pipe B][modeset]
>[    4.837526] [drm:intel_dump_pipe_config [i915]] output_types: DP (0x80)
>[    4.837540] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[    4.837554] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5767168, gmch_n: 8388608, link_m: 240298, link_n: 262144, tu: 64
>[    4.837568] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[    4.837582] [drm:intel_dump_pipe_config [i915]] requested mode:
>[    4.837591] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[    4.837604] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[    4.837611] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[    4.837625] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[    4.837639] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1080, pixel rate 148500
>[    4.837652] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[    4.837666] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[    4.837679] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[    4.837692] [drm:intel_dump_pipe_config [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[    4.837705] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[    4.837719] [drm:intel_dump_pipe_config [i915]] [PLANE:38:plane 1B] disabled, scaler_id = -1
>[    4.837732] [drm:intel_dump_pipe_config [i915]] [PLANE:41:plane 2B] disabled, scaler_id = -1
>[    4.837745] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor B] disabled, scaler_id = -1
>[    4.837760] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[    4.837774] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[    4.837792] [drm:intel_find_shared_dpll [i915]] [CRTC:47:pipe B] allocated DPLL 1
>[    4.837806] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[    4.837828] [drm:intel_disable_sagv [i915]] Disabling the SAGV
>[    4.837845] [drm:intel_atomic_commit_tail [i915]] [ENCODER:48:DDI A]
>[    4.837859] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI B]
>[    4.837873] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[    4.837886] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[    4.837899] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DDI C]
>[    4.837912] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST A]
>[    4.837925] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST B]
>[    4.837938] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI D]
>[    4.837951] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[    4.837964] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[    4.837978] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[    4.837992] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[    4.838006] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[    4.838019] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[    4.844526] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 2, on? 0) for crtc 47
>[    4.844541] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[    4.844629] [drm:intel_power_well_enable [i915]] enabling DDI B IO power well
>[    4.845186] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[    4.846368] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[    4.847552] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[    4.848629] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[    4.849812] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[    4.850585] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[    4.851487] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[    4.851501] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[    4.851513] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[    4.851526] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[    4.864256] IPv6: ADDRCONF(NETDEV_UP): enp0s31f6: link is not ready
>[    4.870178] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[    4.870193] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[    4.887946] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[    4.888276] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:57:DP-1] Link Training Passed at Link Rate = 162000, Lane count = 4
>[    4.888644] [drm:intel_enable_pipe [i915]] enabling pipe B
>[    4.888662] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS
>[    4.905387] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:57:DP-1]
>[    4.905405] [drm:intel_atomic_commit_tail [i915]] [CRTC:47:pipe B]
>[    4.905429] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[    5.395586] asix 1-2:1.0 eth0: register 'asix' at usb-0000:00:14.0-2, ASIX AX88772 USB 2.0 Ethernet, 00:10:60:31:c2:aa
>[    5.395609] usbcore: registered new interface driver asix
>[    5.398438] asix 1-2:1.0 enx00106031c2aa: renamed from eth0
>[    5.459369] IPv6: ADDRCONF(NETDEV_UP): enx00106031c2aa: link is not ready
>[    7.052514] IPv6: ADDRCONF(NETDEV_CHANGE): enx00106031c2aa: link becomes ready
>[    7.055796] asix 1-2:1.0 enx00106031c2aa: link up, 100Mbps, full-duplex, lpa 0xC5E1
>[    7.295205] [drm:i915_audio_component_get_eld [i915]] Not valid for port B
>[    7.295220] [drm:i915_audio_component_get_eld [i915]] Not valid for port B
>[    7.295220] ------------[ cut here ]------------
>[    7.295220] WARN_ON(pipe >= intel_info((dev_priv))->num_pipes)
>[    7.295244] WARNING: CPU: 10 PID: 392 at drivers/gpu/drm/i915/intel_audio.c:782 get_saved_enc+0x7a/0x80 [i915]
>[    7.295244] Modules linked in: snd_hda_codec_hdmi(+) asix usbnet mii ip6table_filter ip6_tables bnep iptable_filter snd_hda_codec_realtek snd_hda_codec_generic binfmt_misc intel_rapl nls_iso8859_1 x86_pkg_temp_thermal intel_powerclamp coretemp 8250_dw kvm_intel kvm snd_hda_intel snd_hda_codec snd_hda_core irqbypass snd_hwdep crct10dif_pclmul snd_pcm crc32_pclmul ghash_clmulni_intel btusb iwlwifi btrtl snd_seq_midi pcbc btbcm snd_seq_midi_event btintel snd_rawmidi bluetooth aesni_intel aes_x86_64 crypto_simd glue_helper cryptd snd_seq intel_cstate idma64 snd_seq_device virt_dma snd_timer intel_rapl_perf cfg80211 ecdh_generic snd input_leds shpchp soundcore serio_raw intel_lpss_pci intel_pch_thermal intel_lpss wmi_bmof acpi_als kfifo_buf industrialio winbond_cir rc_core soc_button_array spidev intel_hid
>[    7.295257]  acpi_pad sparse_keymap mac_hid parport_pc ppdev lp parport ip_tables x_tables autofs4 i915 i2c_algo_bit prime_numbers drm_kms_helper syscopyarea e1000e sysfillrect sysimgblt fb_sys_fops ahci ptp pps_core drm libahci wmi video i2c_hid hid
>[    7.295264] CPU: 10 PID: 392 Comm: systemd-udevd Tainted: G     U           4.15.0-rc1-drm-tip-ww48-commit-4faecf8+ #1
>[    7.295265] Hardware name: Intel Corporation CoffeeLake Client Platform/CoffeeLake S UDIMM RVP, BIOS CNLSFWR1.R00.X104.A03.1709140535 09/14/2017
>[    7.295265] task: ffff983dd171bd00 task.stack: ffffb84342674000
>[    7.295278] RIP: 0010:get_saved_enc+0x7a/0x80 [i915]
>[    7.295279] RSP: 0018:ffffb84342677aa8 EFLAGS: 00010282
>[    7.295280] RAX: 0000000000000000 RBX: ffff983dcfde8000 RCX: ffffffffb82551c8
>[    7.295280] RDX: 0000000000000001 RSI: 0000000000000082 RDI: 0000000000000202
>[    7.295280] RBP: 0000000000000100 R08: 0000000000000032 R09: 00000000000007a3
>[    7.295281] R10: ffffffffc043d9f0 R11: 00000000000007a3 R12: ffff983dd480aa10
>[    7.295281] R13: ffff983dcfded048 R14: 0000000000000001 R15: ffff983dd480aa08
>[    7.295282] FS:  00007f26668a38c0(0000) GS:ffff983ddd080000(0000) knlGS:0000000000000000
>[    7.295282] CS:  0010 DS: 0000 ES: 0000 CR0: 0000000080050033
>[    7.295283] CR2: 00007f11d4009028 CR3: 0000000450728005 CR4: 00000000003606e0
>[    7.295283] DR0: 0000000000000000 DR1: 0000000000000000 DR2: 0000000000000000
>[    7.295283] DR3: 0000000000000000 DR6: 00000000fffe0ff0 DR7: 0000000000000400
>[    7.295284] Call Trace:
>[    7.295297]  i915_audio_component_get_eld+0x48/0x150 [i915]
>[    7.295300]  hdmi_present_sense+0x9d/0x370 [snd_hda_codec_hdmi]
>[    7.295302]  generic_hdmi_build_controls+0x148/0x1f0 [snd_hda_codec_hdmi]
>[    7.295306]  snd_hda_codec_build_controls+0x1b1/0x200 [snd_hda_codec]
>[    7.295308]  hda_codec_driver_probe+0x81/0x100 [snd_hda_codec]
>[    7.295310]  driver_probe_device+0x2ae/0x490
>[    7.295311]  __driver_attach+0xda/0xe0
>[    7.295312]  ? driver_probe_device+0x490/0x490
>[    7.295313]  bus_for_each_dev+0x67/0xb0
>[    7.295314]  bus_add_driver+0x1ed/0x260
>[    7.295315]  ? 0xffffffffc0796000
>[    7.295315]  driver_register+0x57/0xc0
>[    7.295316]  ? 0xffffffffc0796000
>[    7.295317]  do_one_initcall+0x4e/0x1a0
>[    7.295320]  ? _cond_resched+0x16/0x40
>[    7.295322]  ? kmem_cache_alloc_trace+0xe6/0x1b0
>[    7.295323]  do_init_module+0x5b/0x218
>[    7.295324]  load_module+0x2735/0x2c80
>[    7.295326]  ? SYSC_finit_module+0xd2/0x100
>[    7.295326]  SYSC_finit_module+0xd2/0x100
>[    7.295328]  entry_SYSCALL_64_fastpath+0x1e/0x81
>[    7.295329] RIP: 0033:0x7f2665739d29
>[    7.295329] RSP: 002b:00007ffdbaa293c8 EFLAGS: 00000246 ORIG_RAX: 0000000000000139
>[    7.295330] RAX: ffffffffffffffda RBX: 0000000000000007 RCX: 00007f2665739d29
>[    7.295330] RDX: 0000000000000000 RSI: 00007f266605be23 RDI: 0000000000000007
>[    7.295331] RBP: 00007ffdbaa283d0 R08: 0000000000000000 R09: 0000000000000000
>[    7.295331] R10: 0000000000000007 R11: 0000000000000246 R12: 0000562961ea2e70
>[    7.295331] R13: 00007ffdbaa283b0 R14: 0000000000000005 R15: 000056296068a62c
>[    7.295332] Code: c2 01 39 d1 7f e0 31 c0 f3 c3 83 78 70 0b 74 f8 31 c0 85 d2 74 ca eb f0 48 c7 c6 18 47 50 c0 48 c7 c7 80 aa 4e c0 e8 66 e3 03 f7 <0f> ff 31 c0 c3 90 0f 1f 44 00 00 41 57 41 56 49 89 cf 41 55 41 
>[    7.295345] ---[ end trace cb83c5bd14c6efdb ]---
>[    7.295358] [drm:i915_audio_component_get_eld [i915]] Not valid for port B
>[    7.295370] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[    7.295381] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[    7.295382] ------------[ cut here ]------------
>[    7.295382] WARN_ON(pipe >= intel_info((dev_priv))->num_pipes)
>[    7.295400] WARNING: CPU: 10 PID: 392 at drivers/gpu/drm/i915/intel_audio.c:782 get_saved_enc+0x7a/0x80 [i915]
>[    7.295400] Modules linked in: snd_hda_codec_hdmi(+) asix usbnet mii ip6table_filter ip6_tables bnep iptable_filter snd_hda_codec_realtek snd_hda_codec_generic binfmt_misc intel_rapl nls_iso8859_1 x86_pkg_temp_thermal intel_powerclamp coretemp 8250_dw kvm_intel kvm snd_hda_intel snd_hda_codec snd_hda_core irqbypass snd_hwdep crct10dif_pclmul snd_pcm crc32_pclmul ghash_clmulni_intel btusb iwlwifi btrtl snd_seq_midi pcbc btbcm snd_seq_midi_event btintel snd_rawmidi bluetooth aesni_intel aes_x86_64 crypto_simd glue_helper cryptd snd_seq intel_cstate idma64 snd_seq_device virt_dma snd_timer intel_rapl_perf cfg80211 ecdh_generic snd input_leds shpchp soundcore serio_raw intel_lpss_pci intel_pch_thermal intel_lpss wmi_bmof acpi_als kfifo_buf industrialio winbond_cir rc_core soc_button_array spidev intel_hid
>[    7.295412]  acpi_pad sparse_keymap mac_hid parport_pc ppdev lp parport ip_tables x_tables autofs4 i915 i2c_algo_bit prime_numbers drm_kms_helper syscopyarea e1000e sysfillrect sysimgblt fb_sys_fops ahci ptp pps_core drm libahci wmi video i2c_hid hid
>[    7.295418] CPU: 10 PID: 392 Comm: systemd-udevd Tainted: G     U  W        4.15.0-rc1-drm-tip-ww48-commit-4faecf8+ #1
>[    7.295418] Hardware name: Intel Corporation CoffeeLake Client Platform/CoffeeLake S UDIMM RVP, BIOS CNLSFWR1.R00.X104.A03.1709140535 09/14/2017
>[    7.295418] task: ffff983dd171bd00 task.stack: ffffb84342674000
>[    7.295430] RIP: 0010:get_saved_enc+0x7a/0x80 [i915]
>[    7.295430] RSP: 0018:ffffb84342677aa8 EFLAGS: 00010282
>[    7.295431] RAX: 0000000000000000 RBX: ffff983dcfde8000 RCX: ffffffffb82551c8
>[    7.295431] RDX: 0000000000000001 RSI: 0000000000000082 RDI: 0000000000000202
>[    7.295432] RBP: 0000000000000100 R08: 0000000000000032 R09: 00000000000007d9
>[    7.295432] R10: ffffffffc043d9f0 R11: 00000000000007d9 R12: ffff983dd480aa10
>[    7.295432] R13: ffff983dcfded048 R14: 0000000000000002 R15: ffff983dd480aa08
>[    7.295433] FS:  00007f26668a38c0(0000) GS:ffff983ddd080000(0000) knlGS:0000000000000000
>[    7.295433] CS:  0010 DS: 0000 ES: 0000 CR0: 0000000080050033
>[    7.295434] CR2: 00007f11d4009028 CR3: 0000000450728005 CR4: 00000000003606e0
>[    7.295434] DR0: 0000000000000000 DR1: 0000000000000000 DR2: 0000000000000000
>[    7.295434] DR3: 0000000000000000 DR6: 00000000fffe0ff0 DR7: 0000000000000400
>[    7.295435] Call Trace:
>[    7.295446]  i915_audio_component_get_eld+0x48/0x150 [i915]
>[    7.295448]  hdmi_present_sense+0x9d/0x370 [snd_hda_codec_hdmi]
>[    7.295450]  generic_hdmi_build_controls+0x148/0x1f0 [snd_hda_codec_hdmi]
>[    7.295453]  snd_hda_codec_build_controls+0x1b1/0x200 [snd_hda_codec]
>[    7.295455]  hda_codec_driver_probe+0x81/0x100 [snd_hda_codec]
>[    7.295456]  driver_probe_device+0x2ae/0x490
>[    7.295456]  __driver_attach+0xda/0xe0
>[    7.295457]  ? driver_probe_device+0x490/0x490
>[    7.295458]  bus_for_each_dev+0x67/0xb0
>[    7.295459]  bus_add_driver+0x1ed/0x260
>[    7.295459]  ? 0xffffffffc0796000
>[    7.295460]  driver_register+0x57/0xc0
>[    7.295460]  ? 0xffffffffc0796000
>[    7.295461]  do_one_initcall+0x4e/0x1a0
>[    7.295463]  ? _cond_resched+0x16/0x40
>[    7.295464]  ? kmem_cache_alloc_trace+0xe6/0x1b0
>[    7.295465]  do_init_module+0x5b/0x218
>[    7.295465]  load_module+0x2735/0x2c80
>[    7.295467]  ? SYSC_finit_module+0xd2/0x100
>[    7.295468]  SYSC_finit_module+0xd2/0x100
>[    7.295469]  entry_SYSCALL_64_fastpath+0x1e/0x81
>[    7.295469] RIP: 0033:0x7f2665739d29
>[    7.295470] RSP: 002b:00007ffdbaa293c8 EFLAGS: 00000246 ORIG_RAX: 0000000000000139
>[    7.295470] RAX: ffffffffffffffda RBX: 0000000000000007 RCX: 00007f2665739d29
>[    7.295471] RDX: 0000000000000000 RSI: 00007f266605be23 RDI: 0000000000000007
>[    7.295471] RBP: 00007ffdbaa283d0 R08: 0000000000000000 R09: 0000000000000000
>[    7.295471] R10: 0000000000000007 R11: 0000000000000246 R12: 0000562961ea2e70
>[    7.295472] R13: 00007ffdbaa283b0 R14: 0000000000000005 R15: 000056296068a62c
>[    7.295472] Code: c2 01 39 d1 7f e0 31 c0 f3 c3 83 78 70 0b 74 f8 31 c0 85 d2 74 ca eb f0 48 c7 c6 18 47 50 c0 48 c7 c7 80 aa 4e c0 e8 66 e3 03 f7 <0f> ff 31 c0 c3 90 0f 1f 44 00 00 41 57 41 56 49 89 cf 41 55 41 
>[    7.295485] ---[ end trace cb83c5bd14c6efdc ]---
>[    7.295497] [drm:i915_audio_component_get_eld [i915]] Not valid for port C
>[    7.295508] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[    7.295519] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[    7.295519] ------------[ cut here ]------------
>[    7.295520] WARN_ON(pipe >= intel_info((dev_priv))->num_pipes)
>[    7.295536] WARNING: CPU: 10 PID: 392 at drivers/gpu/drm/i915/intel_audio.c:782 get_saved_enc+0x7a/0x80 [i915]
>[    7.295536] Modules linked in: snd_hda_codec_hdmi(+) asix usbnet mii ip6table_filter ip6_tables bnep iptable_filter snd_hda_codec_realtek snd_hda_codec_generic binfmt_misc intel_rapl nls_iso8859_1 x86_pkg_temp_thermal intel_powerclamp coretemp 8250_dw kvm_intel kvm snd_hda_intel snd_hda_codec snd_hda_core irqbypass snd_hwdep crct10dif_pclmul snd_pcm crc32_pclmul ghash_clmulni_intel btusb iwlwifi btrtl snd_seq_midi pcbc btbcm snd_seq_midi_event btintel snd_rawmidi bluetooth aesni_intel aes_x86_64 crypto_simd glue_helper cryptd snd_seq intel_cstate idma64 snd_seq_device virt_dma snd_timer intel_rapl_perf cfg80211 ecdh_generic snd input_leds shpchp soundcore serio_raw intel_lpss_pci intel_pch_thermal intel_lpss wmi_bmof acpi_als kfifo_buf industrialio winbond_cir rc_core soc_button_array spidev intel_hid
>[    7.295548]  acpi_pad sparse_keymap mac_hid parport_pc ppdev lp parport ip_tables x_tables autofs4 i915 i2c_algo_bit prime_numbers drm_kms_helper syscopyarea e1000e sysfillrect sysimgblt fb_sys_fops ahci ptp pps_core drm libahci wmi video i2c_hid hid
>[    7.295554] CPU: 10 PID: 392 Comm: systemd-udevd Tainted: G     U  W        4.15.0-rc1-drm-tip-ww48-commit-4faecf8+ #1
>[    7.295554] Hardware name: Intel Corporation CoffeeLake Client Platform/CoffeeLake S UDIMM RVP, BIOS CNLSFWR1.R00.X104.A03.1709140535 09/14/2017
>[    7.295554] task: ffff983dd171bd00 task.stack: ffffb84342674000
>[    7.295565] RIP: 0010:get_saved_enc+0x7a/0x80 [i915]
>[    7.295566] RSP: 0018:ffffb84342677aa8 EFLAGS: 00010282
>[    7.295566] RAX: 0000000000000000 RBX: ffff983dcfde8000 RCX: ffffffffb82551c8
>[    7.295566] RDX: 0000000000000001 RSI: 0000000000000082 RDI: 0000000000000202
>[    7.295567] RBP: 0000000000000100 R08: 0000000000000032 R09: 000000000000080f
>[    7.295567] R10: ffffffffc043d9f0 R11: 000000000000080f R12: ffff983dd480aa10
>[    7.295568] R13: ffff983dcfded048 R14: 0000000000000003 R15: ffff983dd480aa08
>[    7.295568] FS:  00007f26668a38c0(0000) GS:ffff983ddd080000(0000) knlGS:0000000000000000
>[    7.295568] CS:  0010 DS: 0000 ES: 0000 CR0: 0000000080050033
>[    7.295569] CR2: 00007f11d4009028 CR3: 0000000450728005 CR4: 00000000003606e0
>[    7.295569] DR0: 0000000000000000 DR1: 0000000000000000 DR2: 0000000000000000
>[    7.295569] DR3: 0000000000000000 DR6: 00000000fffe0ff0 DR7: 0000000000000400
>[    7.295570] Call Trace:
>[    7.295581]  i915_audio_component_get_eld+0x48/0x150 [i915]
>[    7.295583]  hdmi_present_sense+0x9d/0x370 [snd_hda_codec_hdmi]
>[    7.295585]  generic_hdmi_build_controls+0x148/0x1f0 [snd_hda_codec_hdmi]
>[    7.295587]  snd_hda_codec_build_controls+0x1b1/0x200 [snd_hda_codec]
>[    7.295589]  hda_codec_driver_probe+0x81/0x100 [snd_hda_codec]
>[    7.295590]  driver_probe_device+0x2ae/0x490
>[    7.295591]  __driver_attach+0xda/0xe0
>[    7.295592]  ? driver_probe_device+0x490/0x490
>[    7.295592]  bus_for_each_dev+0x67/0xb0
>[    7.295593]  bus_add_driver+0x1ed/0x260
>[    7.295594]  ? 0xffffffffc0796000
>[    7.295594]  driver_register+0x57/0xc0
>[    7.295595]  ? 0xffffffffc0796000
>[    7.295596]  do_one_initcall+0x4e/0x1a0
>[    7.295597]  ? _cond_resched+0x16/0x40
>[    7.295598]  ? kmem_cache_alloc_trace+0xe6/0x1b0
>[    7.295599]  do_init_module+0x5b/0x218
>[    7.295600]  load_module+0x2735/0x2c80
>[    7.295601]  ? SYSC_finit_module+0xd2/0x100
>[    7.295602]  SYSC_finit_module+0xd2/0x100
>[    7.295603]  entry_SYSCALL_64_fastpath+0x1e/0x81
>[    7.295604] RIP: 0033:0x7f2665739d29
>[    7.295604] RSP: 002b:00007ffdbaa293c8 EFLAGS: 00000246 ORIG_RAX: 0000000000000139
>[    7.295604] RAX: ffffffffffffffda RBX: 0000000000000007 RCX: 00007f2665739d29
>[    7.295605] RDX: 0000000000000000 RSI: 00007f266605be23 RDI: 0000000000000007
>[    7.295605] RBP: 00007ffdbaa283d0 R08: 0000000000000000 R09: 0000000000000000
>[    7.295605] R10: 0000000000000007 R11: 0000000000000246 R12: 0000562961ea2e70
>[    7.295606] R13: 00007ffdbaa283b0 R14: 0000000000000005 R15: 000056296068a62c
>[    7.295606] Code: c2 01 39 d1 7f e0 31 c0 f3 c3 83 78 70 0b 74 f8 31 c0 85 d2 74 ca eb f0 48 c7 c6 18 47 50 c0 48 c7 c7 80 aa 4e c0 e8 66 e3 03 f7 <0f> ff 31 c0 c3 90 0f 1f 44 00 00 41 57 41 56 49 89 cf 41 55 41 
>[    7.295619] ---[ end trace cb83c5bd14c6efdd ]---
>[    7.295631] [drm:i915_audio_component_get_eld [i915]] Not valid for port D
>[    7.297179] input: HDA Intel PCH Rear Mic as /devices/pci0000:00/0000:00:1f.3/sound/card0/input5
>[    7.297226] input: HDA Intel PCH Front Mic as /devices/pci0000:00/0000:00:1f.3/sound/card0/input6
>[    7.297254] input: HDA Intel PCH Line Out as /devices/pci0000:00/0000:00:1f.3/sound/card0/input7
>[    7.297280] input: HDA Intel PCH Front Headphone as /devices/pci0000:00/0000:00:1f.3/sound/card0/input8
>[    7.297309] input: HDA Intel PCH HDMI/DP,pcm=3 as /devices/pci0000:00/0000:00:1f.3/sound/card0/input9
>[    7.297336] input: HDA Intel PCH HDMI/DP,pcm=7 as /devices/pci0000:00/0000:00:1f.3/sound/card0/input10
>[    7.297363] input: HDA Intel PCH HDMI/DP,pcm=8 as /devices/pci0000:00/0000:00:1f.3/sound/card0/input11
>[    7.297389] input: HDA Intel PCH HDMI/DP,pcm=9 as /devices/pci0000:00/0000:00:1f.3/sound/card0/input12
>[    7.297415] input: HDA Intel PCH HDMI/DP,pcm=10 as /devices/pci0000:00/0000:00:1f.3/sound/card0/input13
>[    7.900348] [drm:edp_panel_vdd_off_sync [i915]] Turning eDP port A VDD off
>[    7.900482] [drm:edp_panel_vdd_off_sync [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x00000067
>[   92.898845] Console: switching to colour dummy device 80x25
>[   92.898863] [IGT] gem_shrink: executing
>[   92.960099] gem_shrink (1844): drop_caches: 4
>[   92.992263] [IGT] gem_shrink: starting subtest mmap-cpu-userptr
>[  285.915618] [IGT] gem_shrink: exiting, ret=0
>[  286.058935] [IGT] kms_flip: executing
>[  286.128095] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:49:eDP-1]
>[  286.128121] [drm:intel_dp_detect [i915]] [CONNECTOR:49:eDP-1]
>[  286.128140] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>[  286.128157] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  286.128173] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  286.128201] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[  286.128293] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006f
>[  286.128694] [drm:drm_dp_read_desc [drm_kms_helper]] DP sink: OUI 00-1c-f8 dev-ID  HW-rev 0.1 SW-rev 1.22 quirks 0x0000
>[  286.129351] [drm:drm_add_edid_modes [drm]] ELD: no CEA Extension found
>[  286.129365] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:49:eDP-1] probed modes :
>[  286.129372] [drm:drm_mode_debug_printmodeline [drm]] Modeline 50:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[  286.129379] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:57:DP-1]
>[  286.129399] [drm:intel_dp_detect [i915]] [CONNECTOR:57:DP-1]
>[  286.129703] [drm:lspcon_wake_native_aux_ch [i915]] Native AUX CH up, DPCD version: 1.2
>[  286.129730] [drm:lspcon_resume [i915]] LSPCON recovering in PCON mode after 0 ms
>[  286.130145] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  286.131383] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  286.132613] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  286.133790] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  286.134976] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  286.135748] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  286.136147] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 00 00 04 00 0f 00 04
>[  286.136823] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>[  286.136837] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000
>[  286.136850] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000
>[  286.137213] [drm:drm_dp_read_desc [drm_kms_helper]] DP branch: OUI 00-60-ad dev-ID MC2800 HW-rev 2.2 SW-rev 1.70 quirks 0x0000
>[  286.137498] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  286.138222] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  286.139399] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  286.140595] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  286.141765] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  286.142969] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  286.144194] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  286.145435] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  286.146673] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  286.147891] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  286.149249] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  286.150603] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  286.151955] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  286.153312] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  286.154661] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  286.156020] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  286.157379] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  286.158720] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  286.159933] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  286.161160] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  286.162386] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  286.163608] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  286.164903] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  286.166253] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  286.167602] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  286.168936] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  286.170266] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  286.171557] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  286.172853] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  286.174221] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  286.175309] [drm:drm_add_edid_modes [drm]] ELD monitor HP E232
>[  286.175320] [drm:drm_add_edid_modes [drm]] HDMI: latency present 0 0, video latency 0 0, audio latency 0 0
>[  286.175329] [drm:drm_add_edid_modes [drm]] ELD size 28, SAD count 0
>[  286.175337] [drm:drm_add_edid_modes [drm]] HDMI: DVI dual 0, max TMDS clock 170000 kHz
>[  286.175463] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:57:DP-1] probed modes :
>[  286.175474] [drm:drm_mode_debug_printmodeline [drm]] Modeline 74:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  286.175483] [drm:drm_mode_debug_printmodeline [drm]] Modeline 97:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  286.175492] [drm:drm_mode_debug_printmodeline [drm]] Modeline 76:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  286.175501] [drm:drm_mode_debug_printmodeline [drm]] Modeline 81:"1680x1050" 60 119000 1680 1728 1760 1840 1050 1053 1059 1080 0x40 0x9
>[  286.175509] [drm:drm_mode_debug_printmodeline [drm]] Modeline 80:"1600x900" 60 108000 1600 1624 1704 1800 900 901 904 1000 0x40 0x5
>[  286.175517] [drm:drm_mode_debug_printmodeline [drm]] Modeline 84:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  286.175525] [drm:drm_mode_debug_printmodeline [drm]] Modeline 82:"1440x900" 60 88750 1440 1488 1520 1600 900 903 909 926 0x40 0x9
>[  286.175533] [drm:drm_mode_debug_printmodeline [drm]] Modeline 83:"1280x800" 60 71000 1280 1328 1360 1440 800 803 809 823 0x40 0x9
>[  286.175541] [drm:drm_mode_debug_printmodeline [drm]] Modeline 77:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  286.175549] [drm:drm_mode_debug_printmodeline [drm]] Modeline 99:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  286.175556] [drm:drm_mode_debug_printmodeline [drm]] Modeline 78:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  286.175564] [drm:drm_mode_debug_printmodeline [drm]] Modeline 87:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  286.175572] [drm:drm_mode_debug_printmodeline [drm]] Modeline 85:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  286.175579] [drm:drm_mode_debug_printmodeline [drm]] Modeline 95:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  286.175587] [drm:drm_mode_debug_printmodeline [drm]] Modeline 100:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  286.175594] [drm:drm_mode_debug_printmodeline [drm]] Modeline 79:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  286.175602] [drm:drm_mode_debug_printmodeline [drm]] Modeline 101:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  286.175610] [drm:drm_mode_debug_printmodeline [drm]] Modeline 86:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  286.175627] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:61:DP-2]
>[  286.175658] [drm:intel_dp_detect [i915]] [CONNECTOR:61:DP-2]
>[  286.175676] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:61:DP-2] disconnected
>[  286.175686] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:64:HDMI-A-1]
>[  286.175714] [drm:intel_hdmi_detect [i915]] [CONNECTOR:64:HDMI-A-1]
>[  286.176048] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  286.176086] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  286.176447] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  286.176459] [drm:drm_do_probe_ddc_edid [drm]] drm: skipping non-existent adapter i915 gmbus dpc
>[  286.176778] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  286.176802] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  286.177129] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  286.177136] [drm:drm_dp_dual_mode_detect [drm_kms_helper]] DP dual mode HDMI ID:  (err -6)
>[  286.177141] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:64:HDMI-A-1] disconnected
>[  286.177150] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:67:DP-3]
>[  286.177176] [drm:intel_dp_detect [i915]] [CONNECTOR:67:DP-3]
>[  286.177196] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:67:DP-3] disconnected
>[  286.177203] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:70:HDMI-A-2]
>[  286.177227] [drm:intel_hdmi_detect [i915]] [CONNECTOR:70:HDMI-A-2]
>[  286.188040] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0050 w(1)
>[  286.188112] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK on first message, retry
>[  286.197903] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0050 w(1)
>[  286.197927] [drm:drm_do_probe_ddc_edid [drm]] drm: skipping non-existent adapter i915 gmbus dpd
>[  286.207693] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0040 w(1)
>[  286.207745] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK on first message, retry
>[  286.217018] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0040 w(1)
>[  286.217033] [drm:drm_dp_dual_mode_detect [drm_kms_helper]] DP dual mode HDMI ID:  (err -6)
>[  286.217042] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:70:HDMI-A-2] disconnected
>[  286.217541] [IGT] kms_flip: starting subtest flip-vs-panning-interruptible
>[  286.217813] [drm:drm_mode_addfb2 [drm]] [FB:73]
>[  286.217845] [drm:drm_mode_addfb2 [drm]] [FB:90]
>[  286.319434] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  286.319469] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  286.319487] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[  286.319526] [drm:intel_edp_backlight_off [i915]] 
>[  286.524093] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0
>[  286.524190] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  286.540167] [drm:intel_edp_panel_off.part.31 [i915]] Turn eDP port A panel power off
>[  286.540252] [drm:intel_edp_panel_off.part.31 [i915]] Wait for panel power off time
>[  286.540357] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000003 control 00000060
>[  286.592625] [drm:wait_panel_status [i915]] Wait complete
>[  286.592673] [drm:intel_power_well_disable [i915]] disabling DDI A/E IO power well
>[  286.592733] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  286.592792] [drm:intel_disable_shared_dpll [i915]] disable DPLL 0 (active 1, on? 1) for crtc 37
>[  286.592845] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 0
>[  286.592916] [drm:intel_atomic_commit_tail [i915]] [ENCODER:48:DDI A]
>[  286.592968] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI B]
>[  286.593017] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  286.593063] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  286.593110] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DDI C]
>[  286.593154] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST A]
>[  286.593199] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST B]
>[  286.593243] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI D]
>[  286.593286] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[  286.593329] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[  286.593377] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:49:eDP-1]
>[  286.593426] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[  286.593473] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[  286.593520] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[  286.593566] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[  286.600067] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010
>[  286.600127] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  286.600182] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0
>[  286.600267] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  286.606207] [drm:intel_atomic_commit_tail [i915]] [CRTC:37:pipe A]
>[  286.606261] [drm:intel_enable_sagv [i915]] Enabling the SAGV
>[  286.606323] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  286.606402] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  286.606456] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[  286.606552] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  286.625197] [drm:intel_power_well_disable [i915]] disabling DDI B IO power well
>[  286.625252] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 2, on? 1) for crtc 47
>[  286.625301] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  286.625362] [drm:intel_atomic_commit_tail [i915]] [ENCODER:48:DDI A]
>[  286.625406] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI B]
>[  286.625450] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  286.625490] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  286.625529] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DDI C]
>[  286.625567] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST A]
>[  286.625605] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST B]
>[  286.625642] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI D]
>[  286.625678] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[  286.625715] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[  286.625758] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:57:DP-1]
>[  286.625800] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[  286.625842] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[  286.625881] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[  286.625921] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[  286.625961] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  286.626010] [drm:intel_atomic_commit_tail [i915]] [CRTC:47:pipe B]
>[  286.626047] [drm:intel_power_well_disable [i915]] disabling DC off
>[  286.626081] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  286.626114] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  286.626548] [drm:intel_power_well_disable [i915]] disabling always-on
>[  286.626585] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  286.626608] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  286.626667] [drm:intel_atomic_check [i915]] [CONNECTOR:49:eDP-1] checking for sink bpp constrains
>[  286.626709] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  286.626731] [drm:drm_mode_debug_printmodeline [drm]] Modeline 52:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[  286.626778] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 138780KHz
>[  286.626834] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24
>[  286.626875] [drm:intel_dp_compute_config [i915]] DP link bw required 416340 available 540000
>[  286.626915] [drm:intel_dp_compute_config [i915]] PSR disable by flag
>[  286.626958] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  286.627002] [drm:intel_dump_pipe_config [i915]] [CRTC:37:pipe A][modeset]
>[  286.627044] [drm:intel_dump_pipe_config [i915]] output_types: EDP (0x100)
>[  286.627085] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0
>[  286.627125] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 6467616, gmch_n: 8388608, link_m: 269484, link_n: 524288, tu: 64
>[  286.627163] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  286.627201] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  286.627220] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[  286.627259] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  286.627278] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[  286.627317] [drm:intel_dump_pipe_config [i915]] crtc timings: 138780 1920 1966 1996 2080 1080 1082 1086 1112, type: 0x48 flags: 0xa
>[  286.627355] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 138780
>[  286.627393] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  286.627430] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  286.627467] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  286.627504] [drm:intel_dump_pipe_config [i915]] dpll_hw_state: ctrl1: 0x3, cfgcr1: 0x0, cfgcr2: 0x0
>[  286.627540] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  286.627577] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 1A] disabled, scaler_id = -1
>[  286.627614] [drm:intel_dump_pipe_config [i915]] [PLANE:31:plane 2A] disabled, scaler_id = -1
>[  286.627650] [drm:intel_dump_pipe_config [i915]] [PLANE:34:cursor A] disabled, scaler_id = -1
>[  286.627696] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  286.627736] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[  286.627785] [drm:intel_find_shared_dpll [i915]] [CRTC:37:pipe A] allocated DPLL 0
>[  286.627826] [drm:intel_reference_shared_dpll [i915]] using DPLL 0 for pipe A
>[  286.630267] [drm:intel_power_well_enable [i915]] enabling always-on
>[  286.630301] [drm:intel_power_well_enable [i915]] enabling DC off
>[  286.630634] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  286.630687] [drm:intel_atomic_commit_tail [i915]] [ENCODER:48:DDI A]
>[  286.630729] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI B]
>[  286.630772] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  286.630811] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  286.630851] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DDI C]
>[  286.630889] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST A]
>[  286.630927] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST B]
>[  286.630963] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI D]
>[  286.631000] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[  286.631038] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[  286.631079] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[  286.631121] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[  286.631161] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[  286.631200] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[  286.631245] [drm:intel_enable_shared_dpll [i915]] enable DPLL 0 (active 1, on? 0) for crtc 37
>[  286.631287] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 0
>[  286.631346] [drm:edp_panel_on [i915]] Turn eDP port A panel power on
>[  286.631402] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle
>[  287.228260] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 00000000 control 00000060
>[  287.228341] [drm:wait_panel_status [i915]] Wait complete
>[  287.228457] [drm:edp_panel_on [i915]] Wait for panel power on
>[  287.228565] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 00000063
>[  287.260281] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010
>[  287.260341] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  287.260395] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1
>[  287.260485] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  287.429877] [drm:wait_panel_status [i915]] Wait complete
>[  287.429937] [drm:intel_power_well_enable [i915]] enabling DDI A/E IO power well
>[  287.430033] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[  287.430178] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b
>[  287.431396] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  287.431461] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  287.431518] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  287.431575] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  287.432306] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  287.432360] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  287.433363] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  287.433419] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:49:eDP-1] Link Training Passed at Link Rate = 270000, Lane count = 2
>[  287.434054] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  287.434120] [drm:intel_edp_backlight_on [i915]] 
>[  287.434177] [drm:intel_panel_enable_backlight [i915]] pipe A
>[  287.434260] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 120000
>[  287.440151] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS
>[  287.440215] [drm:intel_fbc_enable [i915]] reserved 16588800 bytes of contiguous stolen space for FBC, threshold: 1
>[  287.440270] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  287.450928] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:49:eDP-1]
>[  287.451006] [drm:intel_atomic_commit_tail [i915]] [CRTC:37:pipe A]
>[  287.451095] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[  287.467749] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  287.467782] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  287.468059] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  287.468088] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  287.470386] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  287.470417] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  287.472490] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  287.472521] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  287.474768] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  287.474799] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  287.476984] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  287.477017] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  287.479253] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  287.479285] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  287.481507] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  287.481539] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  287.483784] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  287.483816] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  287.501084] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  287.501115] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  287.501859] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  287.501891] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  287.504161] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  287.504193] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  287.506417] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  287.506449] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  287.508532] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  287.508564] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  287.510805] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  287.510837] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  287.513030] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  287.513063] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  287.515308] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  287.515340] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  287.517554] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  287.517585] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  287.534422] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  287.534453] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  287.535607] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  287.535640] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  287.537864] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  287.537897] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  287.540152] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  287.540188] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  287.542414] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  287.542446] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  287.544538] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  287.544572] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  287.546764] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  287.546796] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  287.549000] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  287.549032] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  287.567762] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  287.567793] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  287.569162] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  287.569196] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  287.571427] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  287.571460] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  287.573674] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  287.573707] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  287.575943] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  287.575975] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  287.578207] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  287.578240] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  287.580361] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  287.580394] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  287.582625] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  287.582658] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  287.601066] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  287.601097] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  287.602867] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  287.602900] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  287.605092] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  287.605125] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  287.607360] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  287.607391] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  287.609614] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  287.609647] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  287.611883] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  287.611915] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  287.614143] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  287.614176] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  287.616319] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  287.616351] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  287.634420] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  287.634451] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  287.636493] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  287.636526] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  287.638763] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  287.638795] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  287.640888] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  287.640921] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  287.642988] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  287.643018] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  287.645243] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  287.645275] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  287.647488] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  287.647521] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  287.649739] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  287.649771] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  287.667690] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  287.667721] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  287.669901] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  287.669933] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  287.672179] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  287.672224] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  287.674423] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  287.674455] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  287.676535] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  287.676567] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  287.678806] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  287.678839] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  287.680917] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  287.680948] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  287.683036] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  287.683066] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  287.700975] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  287.701007] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  287.703090] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  287.703122] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  287.705329] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  287.705361] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  287.707596] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  287.707629] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  287.709860] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  287.709893] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  287.712164] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  287.712199] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  287.714417] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  287.714450] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  287.716525] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  287.716558] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  287.734450] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  287.734481] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  287.736532] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  287.736564] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  287.738802] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  287.738834] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  287.741030] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  287.741063] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  287.743303] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  287.743335] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  287.745549] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  287.745582] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  287.747791] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  287.747824] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  287.750054] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  287.750087] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  287.767788] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  287.767819] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  287.770099] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  287.770132] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  287.772355] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  287.772390] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  287.774622] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  287.774655] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  287.776828] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  287.776861] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  287.779095] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  287.779128] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  287.781330] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  287.781362] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  287.783601] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  287.783634] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  287.801087] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  287.801118] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  287.801551] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  287.801583] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  287.803823] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  287.803855] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  287.806091] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  287.806124] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  287.808338] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  287.808371] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  287.810605] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  287.810637] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  287.812824] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  287.812857] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  287.815089] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  287.815122] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  287.817341] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  287.817373] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  287.834440] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  287.834472] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  287.835398] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  287.835430] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  287.837648] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  287.837681] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  287.839916] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  287.839948] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  287.842182] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  287.842213] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  287.844346] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  287.844379] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  287.846617] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  287.846650] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  287.848833] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  287.848866] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  287.867753] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  287.867784] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  287.869106] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  287.869138] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  287.871372] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  287.871404] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  287.873627] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  287.873660] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  287.875889] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  287.875922] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  287.878165] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  287.878198] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  287.880354] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  287.880387] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  287.882609] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  287.882643] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  287.901054] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  287.901085] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  287.902951] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  287.902983] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  287.905194] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  287.905226] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  287.907462] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  287.907494] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  287.909724] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  287.909756] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  287.911999] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  287.912071] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  287.914269] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  287.914300] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  287.916399] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  287.916432] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  287.934301] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  287.934333] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  287.936076] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  287.936112] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  287.938153] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  287.938182] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  287.940314] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  287.940344] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  287.942415] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  287.942445] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  287.944532] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  287.944562] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  287.946645] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  287.946675] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  287.948761] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  287.948790] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  287.967581] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  287.967608] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  287.967831] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  287.967858] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  287.969954] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  287.969982] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  287.972098] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  287.972126] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  287.974207] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  287.974234] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  287.976317] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  287.976345] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  287.978614] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  287.978645] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  287.980833] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  287.980864] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  287.983106] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  287.983136] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  288.001115] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  288.001147] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  288.003345] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  288.003377] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  288.005461] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  288.005492] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  288.007734] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  288.007766] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  288.009872] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  288.009904] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  288.012157] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  288.012190] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  288.014417] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  288.014449] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  288.016525] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  288.016557] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  288.034447] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  288.034478] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  288.036581] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  288.036613] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  288.038850] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  288.038882] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  288.041089] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  288.041122] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  288.043355] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  288.043387] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  288.045604] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  288.045637] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  288.047704] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  288.047736] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  288.049979] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  288.050012] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  288.067776] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  288.067810] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  288.067885] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  288.067906] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  288.070156] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  288.070189] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  288.072354] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  288.072387] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  288.074617] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  288.074649] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  288.076831] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  288.076864] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  288.079097] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  288.079129] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  288.081349] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  288.081382] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  288.083618] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  288.083651] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  288.101100] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  288.101131] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  288.101559] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  288.101591] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  288.103835] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  288.103867] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  288.106106] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  288.106139] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  288.108354] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  288.108387] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  288.110622] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  288.110654] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  288.112848] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  288.112880] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  288.115116] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  288.115149] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  288.117365] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  288.117398] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  288.134426] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  288.134458] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  288.135483] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  288.135515] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  288.137696] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  288.137729] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  288.139962] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  288.139994] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  288.142221] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  288.142254] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  288.144357] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  288.144390] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  288.146625] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  288.146658] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  288.148852] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  288.148884] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  288.167733] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  288.167765] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  288.169200] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  288.169232] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  288.171468] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  288.171500] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  288.173713] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  288.173745] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  288.175980] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  288.176053] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  288.178246] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  288.178279] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  288.180374] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  288.180407] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  288.182639] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  288.182672] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  288.201062] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  288.201094] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  288.202603] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  288.202635] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  288.204725] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  288.204757] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  288.206989] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  288.207021] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  288.209234] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  288.209268] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  288.211499] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  288.211531] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  288.213759] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  288.213791] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  288.216071] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  288.216109] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  288.234384] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  288.234415] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  288.236160] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  288.236196] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  288.238422] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  288.238454] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  288.240546] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  288.240578] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  288.242809] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  288.242841] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  288.245049] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  288.245081] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  288.247322] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  288.247354] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  288.249570] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  288.249602] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  288.267640] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  288.267671] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  288.269841] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  288.269873] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  288.272142] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  288.272174] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  288.274380] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  288.274413] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  288.276491] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  288.276523] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  288.278761] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  288.278793] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  288.280895] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  288.280927] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  288.283162] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  288.283194] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  288.301116] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  288.301147] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  288.303360] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  288.303392] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  288.305609] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  288.305642] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  288.307874] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  288.307906] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  288.310140] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  288.310172] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  288.312286] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  288.312318] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  288.314573] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  288.314606] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  288.316690] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  288.316721] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  288.334438] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  288.334470] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  288.336614] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  288.336647] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  288.338892] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  288.338925] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  288.341019] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  288.341052] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  288.343291] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  288.343323] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  288.345552] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  288.345585] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  288.347822] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  288.347854] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  288.350099] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  288.350132] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  288.367773] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  288.367803] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  288.367873] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  288.367896] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  288.370129] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  288.370163] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  288.372335] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  288.372369] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  288.374602] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  288.374635] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  288.376688] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  288.376721] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  288.378959] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  288.378992] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  288.381202] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  288.381235] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  288.383472] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  288.383505] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  288.401072] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  288.401103] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  288.401175] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  288.401197] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  288.403530] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  288.403562] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  288.405797] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  288.405829] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  288.408108] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  288.408145] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  288.410327] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  288.410359] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  288.412452] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  288.412484] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  288.414729] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  288.414760] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  288.416952] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  288.416984] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  288.434434] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  288.434465] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  288.435035] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  288.435067] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  288.437285] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  288.437318] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  288.439555] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  288.439586] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  288.441812] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  288.441844] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  288.444126] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  288.444160] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  288.446352] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  288.446385] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  288.448431] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  288.448472] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  288.450749] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  288.450802] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  288.467753] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  288.467785] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  288.468709] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  288.468741] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  288.470977] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  288.471010] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  288.473224] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  288.473256] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  288.475495] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  288.475527] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  288.477754] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  288.477787] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  288.480062] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  288.480100] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  288.482271] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  288.482304] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  288.501062] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  288.501095] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  288.502487] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  288.502520] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  288.504608] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  288.504641] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  288.506883] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  288.506915] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  288.509131] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  288.509164] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  288.511395] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  288.511427] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  288.513653] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  288.513686] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  288.515920] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  288.515952] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  288.534367] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  288.534399] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  288.536286] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  288.536319] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  288.538554] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  288.538586] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  288.540776] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  288.540809] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  288.543038] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  288.543070] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  288.545293] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  288.545325] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  288.547576] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  288.547608] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  288.549821] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  288.549853] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  288.567738] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  288.567770] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  288.569957] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  288.569989] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  288.572245] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  288.572278] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  288.574515] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  288.574547] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  288.576619] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  288.576652] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  288.578902] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  288.578934] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  288.581150] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  288.581183] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  288.583415] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  288.583447] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  288.601064] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  288.601096] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  288.601167] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  288.601190] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  288.603489] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  288.603521] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  288.605740] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  288.605773] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  288.608007] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  288.608078] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  288.610272] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  288.610305] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  288.612366] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  288.612400] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  288.614664] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  288.614696] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  288.616886] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  288.616919] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  288.634429] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  288.634461] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  288.634961] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  288.634994] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  288.637202] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  288.637235] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  288.639462] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  288.639495] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  288.641726] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  288.641758] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  288.643994] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  288.644065] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  288.646263] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  288.646295] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  288.648392] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  288.648425] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  288.650652] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  288.650684] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  288.667756] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  288.667787] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  288.668684] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  288.668716] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  288.670954] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  288.670986] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  288.673193] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  288.673226] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  288.675455] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  288.675487] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  288.677717] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  288.677750] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  288.679986] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  288.680059] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  288.682256] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  288.682289] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  288.701073] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  288.701104] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  288.702414] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  288.702446] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  288.704541] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  288.704573] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  288.706803] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  288.706836] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  288.709044] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  288.709077] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  288.711313] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  288.711345] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  288.713572] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  288.713604] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  288.715843] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  288.715875] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  288.734399] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  288.734429] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  288.735995] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  288.736070] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  288.738258] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  288.738290] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  288.740387] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  288.740420] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  288.742662] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  288.742695] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  288.744890] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  288.744923] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  288.747156] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  288.747188] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  288.749403] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  288.749437] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  288.767644] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  288.767676] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  288.769654] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  288.769687] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  288.771920] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  288.771953] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  288.774191] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  288.774224] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  288.776346] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  288.776379] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  288.778600] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  288.778633] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  288.780815] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  288.780847] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  288.783088] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  288.783120] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  288.801056] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  288.801088] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  288.803282] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  288.803314] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  288.805535] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  288.805568] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  288.807799] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  288.807831] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  288.810066] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  288.810098] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  288.812346] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  288.812379] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  288.814612] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  288.814644] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  288.816823] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  288.816855] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  288.834424] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  288.834455] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  288.834744] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  288.834774] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  288.836986] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  288.837018] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  288.839256] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  288.839288] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  288.841510] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  288.841543] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  288.843780] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  288.843813] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  288.846048] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  288.846081] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  288.848331] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  288.848364] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  288.850574] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  288.850607] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  288.867757] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  288.867788] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  288.868424] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  288.868454] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  288.870715] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  288.870747] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  288.872837] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  288.872869] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  288.875110] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  288.875142] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  288.877364] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  288.877397] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  288.879632] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  288.879664] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  288.881883] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  288.881915] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  288.884187] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  288.884218] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  288.901068] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  288.901099] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  288.902145] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  288.902177] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  288.904345] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  288.904378] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  288.906598] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  288.906630] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  288.908749] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  288.908782] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  288.911019] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  288.911052] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  288.913268] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  288.913300] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  288.915534] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  288.915567] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  288.934412] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  288.934443] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  288.935631] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  288.935664] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  288.937893] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  288.937926] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  288.940159] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  288.940193] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  288.942424] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  288.942457] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  288.944511] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  288.944541] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  288.946797] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  288.946829] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  288.949042] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  288.949075] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  288.967730] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  288.967761] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  288.969304] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  288.969337] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  288.971570] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  288.971603] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  288.973837] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  288.973869] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  288.976150] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  288.976183] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  288.978381] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  288.978413] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  288.980505] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  288.980537] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  288.982774] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  288.982806] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  289.000966] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  289.000997] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  289.003036] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  289.003068] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  289.005282] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  289.005315] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  289.007559] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  289.007591] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  289.009820] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  289.009852] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  289.012122] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  289.012159] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  289.014350] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  289.014382] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  289.016461] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  289.016493] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  289.034400] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  289.034431] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  289.036467] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  289.036500] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  289.038734] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  289.038766] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  289.040861] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  289.040892] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  289.043129] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  289.043162] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  289.045371] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  289.045404] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  289.047641] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  289.047673] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  289.049897] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  289.049930] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  289.067762] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  289.067793] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  289.069981] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  289.070013] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  289.072271] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  289.072304] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  289.074542] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  289.074574] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  289.076627] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  289.076660] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  289.078895] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  289.078927] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  289.081020] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  289.081052] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  289.083292] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  289.083324] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  289.101100] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  289.101131] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  289.103329] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  289.103361] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  289.105430] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  289.105460] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  289.107721] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  289.107753] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  289.109980] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  289.110012] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  289.112265] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  289.112299] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  289.114539] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  289.114571] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  289.116620] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  289.116652] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  289.134429] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  289.134461] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  289.136540] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  289.136572] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  289.138808] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  289.138839] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  289.140934] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  289.140967] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  289.143204] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  289.143236] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  289.145309] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  289.145339] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  289.147601] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  289.147633] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  289.149852] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  289.149885] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  289.167763] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  289.167793] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  289.169977] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  289.170009] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  289.172272] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  289.172306] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  289.174537] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  289.174569] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  289.176618] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  289.176651] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  289.178890] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  289.178923] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  289.181021] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  289.181052] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  289.183295] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  289.183328] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  289.201067] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  289.201099] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  289.203411] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  289.203444] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  289.205670] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  289.205703] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  289.207938] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  289.207970] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  289.210211] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  289.210243] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  289.212345] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  289.212377] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  289.214609] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  289.214642] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  289.216694] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  289.216726] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  289.234436] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  289.234467] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  289.236545] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  289.236578] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  289.238818] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  289.238851] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  289.240901] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  289.240934] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  289.243170] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  289.243203] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  289.245267] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  289.245297] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  289.247558] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  289.247590] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  289.249820] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  289.249854] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  289.267690] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  289.267721] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  289.269902] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  289.269935] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  289.272184] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  289.272216] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  289.274346] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  289.274377] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  289.276467] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  289.276500] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  289.278653] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  289.278689] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  289.280802] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  289.280834] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  289.282964] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  289.282996] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  289.300995] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  289.301030] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  289.302380] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  289.302415] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  289.304514] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  289.304549] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  289.306681] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  289.306712] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  289.308833] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  289.308865] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  289.310985] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  289.311016] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  289.313146] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  289.313179] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  289.315305] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  289.315338] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  289.317508] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  289.317540] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  289.334306] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  289.334337] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  289.334615] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  289.334645] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  289.336804] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  289.336837] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  289.338964] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  289.338996] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  289.341130] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  289.341162] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  289.343295] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  289.343328] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  289.345465] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  289.345497] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  289.347630] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  289.347663] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  289.349797] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  289.349830] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  289.367648] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  289.367680] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  289.369218] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  289.369252] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  289.371375] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  289.371407] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  289.373542] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  289.373575] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  289.375700] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  289.375733] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  289.377870] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  289.377902] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  289.380087] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  289.380130] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  289.382315] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  289.382347] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  289.401078] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  289.401113] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  289.402343] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  289.402378] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  289.404468] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  289.404504] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  289.406734] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  289.406769] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  289.408961] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  289.408996] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  289.411226] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  289.411262] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  289.413480] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  289.413516] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  289.415763] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  289.415796] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  289.434391] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  289.434425] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  289.435999] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  289.436080] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  289.438273] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  289.438306] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  289.440383] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  289.440416] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  289.442651] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  289.442684] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  289.444882] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  289.444914] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  289.447153] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  289.447185] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  289.449407] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  289.449440] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  289.467615] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  289.467648] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  289.469715] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  289.469748] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  289.471984] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  289.472055] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  289.474251] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  289.474284] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  289.476386] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  289.476419] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  289.478658] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  289.478691] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  289.480887] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  289.480920] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  289.483159] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  289.483192] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  289.501096] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  289.501128] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  289.503406] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  289.503442] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  289.505659] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  289.505692] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  289.507907] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  289.507939] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  289.510153] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  289.510189] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  289.512336] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  289.512369] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  289.514613] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  289.514645] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  289.516834] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  289.516865] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  289.534427] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  289.534461] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  289.534774] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  289.534807] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  289.537019] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  289.537052] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  289.539286] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  289.539318] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  289.541539] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  289.541571] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  289.543806] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  289.543839] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  289.546043] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  289.546075] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  289.548319] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  289.548351] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  289.550584] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  289.550617] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  289.567748] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  289.567780] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  289.568656] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  289.568688] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  289.570928] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  289.570961] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  289.573135] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  289.573168] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  289.575400] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  289.575433] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  289.577637] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  289.577670] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  289.579905] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  289.579938] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  289.582204] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  289.582241] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  289.601079] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  289.601114] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  289.602402] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  289.602437] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  289.604513] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  289.604545] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  289.606792] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  289.606825] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  289.608922] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  289.608953] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  289.611192] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  289.611225] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  289.613452] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  289.613484] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  289.615720] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  289.615753] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  289.634389] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  289.634442] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  289.635778] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  289.635813] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  289.638057] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  289.638089] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  289.640311] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  289.640343] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  289.642578] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  289.642610] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  289.644792] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  289.644825] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  289.647067] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  289.647099] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  289.649317] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  289.649349] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  289.667694] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  289.667725] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  289.669478] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  289.669510] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  289.671751] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  289.671787] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  289.673976] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  289.674012] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  289.676259] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  289.676293] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  289.678526] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  289.678558] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  289.680639] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  289.680671] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  289.682910] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  289.682942] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  289.700960] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  289.700994] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  289.703101] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  289.703137] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  289.705352] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  289.705388] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  289.707618] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  289.707654] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  289.709880] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  289.709917] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  289.712183] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  289.712222] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  289.714415] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  289.714450] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  289.716532] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  289.716567] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  289.734430] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  289.734466] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  289.736618] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  289.736653] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  289.738884] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  289.738921] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  289.741107] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  289.741144] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  289.743374] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  289.743410] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  289.745630] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  289.745666] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  289.747897] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  289.747932] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  289.750164] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  289.750199] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  289.767764] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  289.767798] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  289.767901] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  289.767926] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  289.770249] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  289.770286] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  289.772391] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  289.772427] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  289.774638] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  289.774674] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  289.776854] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  289.776890] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  289.779121] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  289.779157] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  289.781369] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  289.781406] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  289.783634] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  289.783669] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  289.801055] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  289.801089] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  289.801185] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  289.801210] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  289.803539] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  289.803574] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  289.805787] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  289.805823] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  289.808093] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  289.808134] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  289.810345] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  289.810380] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  289.812491] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  289.812528] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  289.814746] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  289.814781] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  289.816965] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  289.817002] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  289.834423] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  289.834457] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  289.834944] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  289.834979] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  289.837186] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  289.837221] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  289.839447] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  289.839483] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  289.841690] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  289.841727] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  289.843955] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  289.843991] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  289.846212] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  289.846247] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  289.848359] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  289.848395] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  289.850622] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  289.850658] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  289.867737] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  289.867774] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  289.868518] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  289.868555] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  289.870785] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  289.870822] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  289.873013] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  289.873048] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  289.875284] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  289.875320] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  289.877533] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  289.877569] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  289.879795] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  289.879830] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  289.882069] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  289.882106] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  289.901059] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  289.901093] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  289.902423] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  289.902459] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  289.904544] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  289.904581] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  289.906811] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  289.906847] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  289.909045] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  289.909081] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  289.911307] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  289.911343] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  289.913562] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  289.913599] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  289.915827] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  289.915862] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  289.934370] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  289.934404] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  289.936082] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  289.936125] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  289.938306] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  289.938342] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  289.940434] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  289.940469] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  289.942692] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  289.942727] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  289.944915] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  289.944951] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  289.947178] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  289.947213] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  289.949408] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  289.949444] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  289.967628] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  289.967663] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  289.969682] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  289.969719] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  289.971946] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  289.971982] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  289.974215] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  289.974251] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  289.976360] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  289.976397] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  289.978614] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  289.978668] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  289.980846] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  289.980881] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  289.983111] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  289.983147] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  290.001080] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  290.001115] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  290.003292] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  290.003328] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  290.005537] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  290.005574] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  290.007800] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  290.007835] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  290.010068] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  290.010104] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  290.012352] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  290.012388] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  290.014611] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  290.014647] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  290.016821] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  290.016857] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  290.034416] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  290.034451] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  290.034718] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  290.034751] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  290.036960] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  290.036996] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  290.039224] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  290.039260] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  290.041478] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  290.041513] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  290.043742] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  290.043778] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  290.046009] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  290.046045] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  290.048298] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  290.048335] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  290.050566] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  290.050602] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  290.067747] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  290.067782] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  290.068325] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  290.068359] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  290.070614] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  290.070649] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  290.072758] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  290.072795] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  290.075022] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  290.075059] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  290.077265] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  290.077300] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  290.079524] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  290.079560] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  290.081775] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  290.081811] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  290.084104] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  290.084149] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  290.101067] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  290.101102] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  290.101996] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  290.102031] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  290.104280] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  290.104317] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  290.106537] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  290.106572] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  290.108694] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  290.108736] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  290.110980] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  290.111013] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  290.113205] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  290.113238] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  290.115473] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  290.115506] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  290.134390] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  290.134425] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  290.135839] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  290.135875] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  290.138094] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  290.138131] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  290.140352] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  290.140387] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  290.142616] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  290.142652] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  290.144828] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  290.144865] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  290.147094] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  290.147131] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  290.149340] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  290.149377] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  290.167695] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  290.167730] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  290.169546] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  290.169582] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  290.171808] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  290.171844] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  290.174079] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  290.174114] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  290.176349] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  290.176385] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  290.178614] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  290.178649] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  290.180824] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  290.180860] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  290.183088] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  290.183123] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  290.201084] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  290.201118] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  290.203294] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  290.203330] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  290.205542] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  290.205578] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  290.207809] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  290.207844] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  290.210074] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  290.210109] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  290.212356] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  290.212392] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  290.214619] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  290.214655] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  290.216832] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  290.216868] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  290.234414] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  290.234448] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  290.234744] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  290.234777] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  290.236987] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  290.237023] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  290.239256] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  290.239291] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  290.241507] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  290.241543] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  290.243770] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  290.243806] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  290.246030] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  290.246067] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  290.248308] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  290.248344] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  290.250566] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  290.250601] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  290.267730] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  290.267765] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  290.268400] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  290.268433] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  290.270690] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  290.270726] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  290.272903] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  290.272940] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  290.275165] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  290.275200] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  290.277406] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  290.277441] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  290.279668] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  290.279704] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  290.281929] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  290.281964] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  290.301051] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  290.301087] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  290.302242] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  290.302278] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  290.304371] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  290.304408] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  290.306629] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  290.306666] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  290.308855] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  290.308891] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  290.311123] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  290.311158] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  290.313366] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  290.313402] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  290.315639] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  290.315675] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  290.334388] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  290.334422] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  290.335625] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  290.335661] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  290.337886] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  290.337922] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  290.340160] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  290.340200] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  290.342417] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  290.342453] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  290.344534] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  290.344570] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  290.346802] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  290.346838] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  290.348934] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  290.348969] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  290.367715] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  290.367750] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  290.369150] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  290.369186] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  290.371412] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  290.371448] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  290.373671] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  290.373707] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  290.375932] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  290.375968] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  290.378193] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  290.378229] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  290.380349] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  290.380386] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  290.382604] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  290.382640] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  290.401022] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  290.401056] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  290.402943] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  290.402978] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  290.405185] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  290.405221] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  290.407451] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  290.407487] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  290.409706] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  290.409742] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  290.411967] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  290.412003] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  290.414229] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  290.414265] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  290.416366] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  290.416403] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  290.434412] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  290.434446] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  290.436489] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  290.436524] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  290.438751] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  290.438786] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  290.440981] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  290.441018] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  290.443240] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  290.443275] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  290.445492] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  290.445528] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  290.447755] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  290.447791] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  290.450024] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  290.450060] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  290.467747] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  290.467781] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  290.467866] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  290.467891] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  290.470163] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  290.470198] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  290.472349] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  290.472384] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  290.474615] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  290.474650] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  290.476734] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  290.476770] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  290.479010] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  290.479045] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  290.481254] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  290.481290] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  290.483518] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  290.483554] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  290.501069] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  290.501103] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  290.501184] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  290.501209] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  290.503538] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  290.503574] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  290.505797] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  290.505833] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  290.508107] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  290.508145] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  290.510322] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  290.510359] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  290.512448] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  290.512484] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  290.514712] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  290.514748] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  290.516924] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  290.516960] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  290.524276] [drm:edp_panel_vdd_off_sync [i915]] Turning eDP port A VDD off
>[  290.524423] [drm:edp_panel_vdd_off_sync [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x00000067
>[  290.524480] [drm:intel_power_well_disable [i915]] disabling DC off
>[  290.524537] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  290.524590] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  290.534434] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  290.534469] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  290.534746] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  290.534771] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  290.537028] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  290.537063] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  290.539296] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  290.539330] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  290.541553] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  290.541588] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  290.543817] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  290.543853] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  290.546083] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  290.546117] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  290.548349] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  290.548385] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  290.550618] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  290.550653] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  290.567762] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  290.567797] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  290.568427] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  290.568460] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  290.570699] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  290.570734] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  290.572798] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  290.572831] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  290.575082] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  290.575118] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  290.577328] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  290.577364] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  290.579595] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  290.579630] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  290.581858] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  290.581893] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  290.584164] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  290.584204] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  290.601073] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  290.601109] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  290.602113] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  290.602149] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  290.604342] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  290.604378] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  290.606595] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  290.606630] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  290.608817] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  290.608853] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  290.611072] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  290.611107] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  290.613318] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  290.613354] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  290.615581] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  290.615618] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  290.634388] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  290.634422] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  290.635856] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  290.635892] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  290.638123] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  290.638159] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  290.640332] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  290.640368] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  290.642588] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  290.642624] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  290.644804] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  290.644840] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  290.647068] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  290.647103] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  290.649315] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  290.649352] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  290.667689] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  290.667722] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  290.669454] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  290.669490] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  290.671718] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  290.671753] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  290.673976] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  290.674012] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  290.676258] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  290.676295] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  290.678522] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  290.678558] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  290.680605] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  290.680641] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  290.682873] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  290.682908] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  290.700972] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  290.701007] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  290.703002] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  290.703038] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  290.705102] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  290.705136] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  290.707384] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  290.707420] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  290.709639] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  290.709675] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  290.711902] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  290.711938] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  290.714170] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  290.714206] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  290.716333] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  290.716368] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  290.734421] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  290.734455] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  290.736442] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  290.736476] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  290.738717] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  290.738749] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  290.740952] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  290.740988] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  290.743234] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  290.743267] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  290.745472] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  290.745508] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  290.747735] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  290.747771] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  290.749997] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  290.750033] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  290.767748] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  290.767785] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  290.767864] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  290.767888] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  290.770143] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  290.770180] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  290.772355] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  290.772392] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  290.774610] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  290.774646] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  290.776820] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  290.776857] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  290.779085] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  290.779121] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  290.781331] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  290.781368] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  290.783596] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  290.783632] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  290.800963] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  290.800998] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  290.801652] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  290.801687] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  290.803920] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  290.803955] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  290.806175] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  290.806210] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  290.808349] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  290.808385] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  290.810615] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  290.810651] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  290.812825] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  290.812861] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  290.815089] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  290.815125] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  290.817317] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  290.817353] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  290.834389] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  290.834424] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  290.835140] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  290.835176] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  290.837398] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  290.837434] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  290.839663] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  290.839698] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  290.841923] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  290.841958] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  290.844185] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  290.844221] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  290.846437] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  290.846473] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  290.848527] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  290.848564] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  290.850800] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  290.850836] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  290.867715] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  290.867750] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  290.868857] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  290.868893] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  290.871124] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  290.871160] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  290.873366] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  290.873402] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  290.875631] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  290.875668] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  290.877894] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  290.877929] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  290.880168] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  290.880206] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  290.882442] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  290.882478] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  290.901035] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  290.901080] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  290.902605] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  290.902641] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  290.904794] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  290.904830] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  290.907046] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  290.907081] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  290.909291] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  290.909327] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  290.911562] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  290.911598] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  290.913818] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  290.913854] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  290.916122] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  290.916162] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  290.934288] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  290.934322] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  290.936316] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  290.936353] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  290.938580] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  290.938616] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  290.940786] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  290.940822] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  290.943052] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  290.943087] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  290.945287] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  290.945323] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  290.947551] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  290.947587] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  290.949809] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  290.949845] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  290.967692] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  290.967727] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  290.969901] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  290.969936] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  290.972169] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  290.972206] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  290.974434] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  290.974471] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  290.976507] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  290.976543] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  290.978775] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  290.978812] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  290.980922] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  290.980958] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  290.983188] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  290.983223] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  291.001041] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  291.001076] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  291.003391] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  291.003427] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  291.005649] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  291.005685] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  291.007910] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  291.007945] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  291.010173] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  291.010210] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  291.012350] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  291.012386] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  291.014616] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  291.014651] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  291.016818] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  291.016854] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  291.034402] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  291.034437] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  291.034721] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  291.034755] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  291.036969] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  291.037005] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  291.039231] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  291.039266] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  291.041481] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  291.041517] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  291.043750] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  291.043785] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  291.046020] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  291.046057] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  291.048305] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  291.048341] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  291.050572] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  291.050607] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  291.067730] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  291.067765] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  291.068305] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  291.068339] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  291.070605] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  291.070641] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  291.072724] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  291.072759] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  291.074995] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  291.075030] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  291.077235] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  291.077271] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  291.079503] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  291.079538] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  291.081717] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  291.081752] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  291.083980] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  291.084087] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  291.101043] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  291.101077] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  291.101837] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  291.101874] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  291.104156] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  291.104198] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  291.106378] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  291.106413] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  291.108508] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  291.108543] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  291.110777] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  291.110812] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  291.113002] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  291.113038] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  291.115266] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  291.115302] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  291.134366] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  291.134400] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  291.135662] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  291.135699] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  291.137881] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  291.137917] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  291.140160] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  291.140201] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  291.142426] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  291.142461] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  291.144545] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  291.144580] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  291.146818] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  291.146853] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  291.149048] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  291.149085] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  291.167702] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  291.167737] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  291.169202] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  291.169237] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  291.171470] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  291.171506] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  291.173722] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  291.173758] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  291.175987] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  291.176063] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  291.178251] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  291.178287] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  291.180385] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  291.180421] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  291.182645] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  291.182681] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  291.200931] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  291.200964] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  291.202986] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  291.203023] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  291.205229] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  291.205265] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  291.207495] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  291.207531] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  291.209708] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  291.209743] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  291.211970] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  291.212005] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  291.214232] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  291.214267] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  291.216371] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  291.216407] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  291.234394] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  291.234429] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  291.236470] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  291.236506] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  291.238736] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  291.238772] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  291.240954] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  291.240990] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  291.243218] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  291.243253] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  291.245465] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  291.245501] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  291.247728] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  291.247764] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  291.249991] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  291.250027] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  291.267739] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  291.267774] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  291.270054] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  291.270090] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  291.272338] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  291.272375] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  291.274596] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  291.274631] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  291.276739] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  291.276774] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  291.279003] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  291.279039] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  291.281244] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  291.281279] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  291.283508] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  291.283545] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  291.301032] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  291.301068] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  291.301146] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  291.301171] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  291.303451] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  291.303486] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  291.305705] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  291.305742] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  291.307968] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  291.308003] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  291.310233] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  291.310268] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  291.312370] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  291.312408] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  291.314635] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  291.314671] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  291.316839] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  291.316875] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  291.334399] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  291.334433] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  291.334649] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  291.334683] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  291.336880] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  291.336916] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  291.339141] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  291.339176] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  291.341387] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  291.341423] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  291.343654] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  291.343689] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  291.345925] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  291.345960] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  291.348199] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  291.348236] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  291.350459] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  291.350495] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  291.367725] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  291.367759] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  291.368311] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  291.368345] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  291.370606] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  291.370642] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  291.372740] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  291.372776] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  291.375007] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  291.375042] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  291.377255] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  291.377292] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  291.379519] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  291.379555] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  291.381779] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  291.381816] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  291.384114] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  291.384154] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  291.401037] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  291.401072] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  291.402001] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  291.402037] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  291.404261] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  291.404297] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  291.406519] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  291.406555] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  291.408656] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  291.408692] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  291.410926] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  291.410962] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  291.413159] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  291.413194] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  291.415422] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  291.415458] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  291.434372] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  291.434407] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  291.435795] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  291.435831] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  291.438058] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  291.438095] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  291.440338] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  291.440377] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  291.442609] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  291.442645] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  291.444820] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  291.444856] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  291.447085] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  291.447121] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  291.449327] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  291.449363] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  291.467674] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  291.467708] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  291.469436] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  291.469471] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  291.471701] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  291.471736] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  291.473967] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  291.474003] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  291.476246] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  291.476283] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  291.478509] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  291.478545] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  291.480637] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  291.480673] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  291.482907] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  291.482944] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  291.500935] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  291.500969] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  291.503158] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  291.503203] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  291.505252] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  291.505286] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  291.507542] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  291.507577] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  291.509787] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  291.509823] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  291.512088] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  291.512131] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  291.514316] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  291.514352] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  291.516431] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  291.516467] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  291.534398] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  291.534433] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  291.536485] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  291.536519] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  291.538761] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  291.538796] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  291.540975] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  291.541011] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  291.543242] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  291.543277] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  291.545490] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  291.545527] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  291.547757] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  291.547793] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  291.550028] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  291.550065] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  291.567719] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  291.567756] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  291.567831] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  291.567856] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  291.570118] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  291.570153] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  291.572354] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  291.572391] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  291.574612] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  291.574648] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  291.576828] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  291.576864] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  291.579097] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  291.579133] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  291.581341] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  291.581378] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  291.583608] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  291.583644] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  291.601052] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  291.601087] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  291.601701] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  291.601737] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  291.603807] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  291.603842] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  291.606096] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  291.606133] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  291.608353] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  291.608392] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  291.610608] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  291.610644] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  291.612818] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  291.612854] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  291.615082] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  291.615117] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  291.617324] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  291.617360] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  291.634382] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  291.634416] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  291.635442] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  291.635477] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  291.637697] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  291.637734] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  291.639959] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  291.639995] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  291.642223] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  291.642259] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  291.644368] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  291.644405] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  291.646632] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  291.646667] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  291.648832] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  291.648868] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  291.667703] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  291.667737] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  291.669068] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  291.669103] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  291.671333] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  291.671368] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  291.673579] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  291.673615] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  291.675847] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  291.675883] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  291.678111] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  291.678146] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  291.680352] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  291.680389] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  291.682615] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  291.682651] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  291.701010] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  291.701044] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  291.702688] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  291.702724] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  291.704813] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  291.704849] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  291.707085] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  291.707121] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  291.709325] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  291.709360] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  291.711594] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  291.711631] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  291.713841] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  291.713876] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  291.716142] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  291.716183] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  291.734267] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  291.734301] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  291.736325] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  291.736364] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  291.738588] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  291.738624] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  291.740731] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  291.740767] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  291.742995] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  291.743030] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  291.745238] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  291.745275] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  291.747506] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  291.747542] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  291.749756] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  291.749792] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  291.767718] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  291.767753] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  291.769925] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  291.769961] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  291.772202] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  291.772237] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  291.774462] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  291.774497] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  291.776587] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  291.776622] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  291.778856] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  291.778892] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  291.781095] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  291.781132] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  291.783357] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  291.783392] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  291.801055] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  291.801090] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  291.801288] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  291.801320] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  291.803580] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  291.803616] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  291.805843] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  291.805879] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  291.808147] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  291.808187] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  291.810375] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  291.810411] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  291.812500] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  291.812535] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  291.814782] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  291.814817] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  291.816924] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  291.816960] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  291.834394] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  291.834429] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  291.834509] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  291.834534] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  291.836680] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  291.836715] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  291.838944] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  291.838979] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  291.841052] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  291.841087] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  291.843341] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  291.843376] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  291.845588] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  291.845625] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  291.847854] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  291.847889] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  291.850096] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  291.850132] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  291.867714] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  291.867749] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  291.867840] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  291.867865] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  291.870192] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  291.870228] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  291.872349] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  291.872386] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  291.874616] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  291.874652] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  291.876823] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  291.876860] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  291.879089] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  291.879124] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  291.881343] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  291.881379] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  291.883599] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  291.883634] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  291.901053] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  291.901088] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  291.901661] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  291.901697] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  291.903931] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  291.903966] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  291.906190] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  291.906226] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  291.908335] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  291.908371] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  291.910595] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  291.910630] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  291.912725] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  291.912760] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  291.914994] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  291.915029] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  291.917246] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  291.917282] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  291.934371] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  291.934405] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  291.935354] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  291.935390] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  291.937605] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  291.937641] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  291.939869] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  291.939904] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  291.942134] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  291.942171] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  291.944349] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  291.944385] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  291.946614] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  291.946649] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  291.948822] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  291.948858] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  291.967699] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  291.967735] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  291.968829] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  291.968865] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  291.971093] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  291.971129] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  291.973344] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  291.973379] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  291.975609] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  291.975644] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  291.977827] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  291.977863] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  291.979955] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  291.979990] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  291.982225] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  291.982261] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  292.001023] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  292.001057] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  292.002405] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  292.002440] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  292.004528] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  292.004564] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  292.006791] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  292.006827] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  292.009004] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  292.009040] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  292.011272] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  292.011307] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  292.013523] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  292.013559] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  292.015790] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  292.015826] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  292.034339] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  292.034374] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  292.036066] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  292.036108] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  292.038290] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  292.038325] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  292.040377] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  292.040417] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  292.042684] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  292.042720] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  292.044903] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  292.044939] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  292.047166] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  292.047203] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  292.049414] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  292.049450] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  292.067596] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  292.067631] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  292.069616] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  292.069652] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  292.071884] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  292.071919] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  292.074151] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  292.074187] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  292.076348] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  292.076384] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  292.078603] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  292.078639] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  292.080811] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  292.080847] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  292.083076] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  292.083112] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  292.101059] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  292.101093] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  292.103303] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  292.103339] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  292.105415] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  292.105463] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  292.107699] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  292.107734] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  292.109958] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  292.109994] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  292.112243] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  292.112282] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  292.114504] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  292.114541] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  292.116633] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  292.116668] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  292.134386] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  292.134424] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  292.134506] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  292.134531] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  292.136669] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  292.136704] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  292.138934] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  292.138970] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  292.141165] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  292.141201] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  292.143428] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  292.143464] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  292.145676] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  292.145712] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  292.147944] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  292.147979] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  292.150208] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  292.150244] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  292.167711] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  292.167745] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  292.167837] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  292.167862] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  292.170193] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  292.170229] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  292.172345] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  292.172382] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  292.174608] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  292.174643] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  292.176818] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  292.176854] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  292.179088] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  292.179123] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  292.181334] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  292.181370] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  292.183599] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  292.183635] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  292.201038] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  292.201074] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  292.201679] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  292.201715] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  292.203944] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  292.203980] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  292.206075] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  292.206111] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  292.208352] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  292.208390] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  292.210608] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  292.210643] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  292.212816] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  292.212852] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  292.215082] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  292.215117] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  292.217326] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  292.217373] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  292.234356] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  292.234391] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  292.235428] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  292.235463] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  292.237674] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  292.237711] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  292.239941] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  292.239978] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  292.242209] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  292.242246] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  292.244344] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  292.244380] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  292.246610] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  292.246646] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  292.248819] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  292.248856] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  292.267685] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  292.267721] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  292.269071] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  292.269107] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  292.271336] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  292.271371] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  292.273583] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  292.273618] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  292.275855] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  292.275891] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  292.278121] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  292.278157] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  292.280351] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  292.280389] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  292.282616] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  292.282651] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  292.300978] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  292.301013] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  292.302869] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  292.302904] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  292.304967] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  292.305001] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  292.307226] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  292.307261] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  292.309474] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  292.309509] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  292.311738] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  292.311774] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  292.313996] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  292.314033] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  292.316282] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  292.316318] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  292.334334] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  292.334370] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  292.336372] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  292.336409] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  292.338674] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  292.338710] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  292.340886] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  292.340922] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  292.343158] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  292.343194] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  292.345402] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  292.345438] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  292.347666] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  292.347701] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  292.349926] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  292.349963] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  292.367714] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  292.367750] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  292.370051] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  292.370087] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  292.372334] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  292.372372] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  292.374596] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  292.374632] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  292.376741] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  292.376778] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  292.379005] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  292.379041] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  292.381247] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  292.381283] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  292.383515] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  292.383550] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  292.401044] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  292.401080] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  292.401600] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  292.401636] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  292.403870] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  292.403905] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  292.406135] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  292.406171] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  292.408350] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  292.408388] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  292.410613] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  292.410648] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  292.412817] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  292.412853] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  292.415085] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  292.415120] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  292.417318] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  292.417356] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  292.434369] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  292.434404] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  292.435427] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  292.435462] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  292.437680] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  292.437716] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  292.439945] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  292.439980] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  292.442214] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  292.442250] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  292.444352] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  292.444389] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  292.446608] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  292.446644] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  292.448756] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  292.448792] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  292.467673] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  292.467707] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  292.469041] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  292.469078] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  292.471311] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  292.471347] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  292.473560] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  292.473596] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  292.475828] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  292.475865] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  292.478098] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  292.478135] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  292.480349] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  292.480389] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  292.482613] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  292.482649] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  292.500908] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  292.500943] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  292.502980] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  292.503016] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  292.505220] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  292.505257] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  292.507429] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  292.507465] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  292.509684] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  292.509720] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  292.511952] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  292.511987] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  292.514214] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  292.514250] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  292.516353] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  292.516391] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  292.534375] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  292.534409] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  292.536457] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  292.536493] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  292.538723] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  292.538758] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  292.540939] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  292.540975] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  292.543203] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  292.543239] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  292.545457] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  292.545494] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  292.547724] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  292.547760] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  292.549985] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  292.550021] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  292.567707] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  292.567741] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  292.567819] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  292.567844] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  292.570134] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  292.570169] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  292.572346] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  292.572381] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  292.574607] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  292.574642] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  292.576813] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  292.576850] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  292.579070] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  292.579106] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  292.581312] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  292.581347] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  292.583574] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  292.583610] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  292.601034] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  292.601068] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  292.601664] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  292.601699] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  292.603930] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  292.603965] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  292.606167] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  292.606203] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  292.608327] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  292.608363] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  292.610592] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  292.610628] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  292.612799] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  292.612836] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  292.615063] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  292.615098] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  292.617299] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  292.617336] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  292.634353] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  292.634389] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  292.635414] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  292.635450] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  292.637666] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  292.637702] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  292.639936] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  292.639971] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  292.642199] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  292.642235] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  292.644350] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  292.644385] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  292.646617] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  292.646653] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  292.648833] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  292.648870] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  292.667688] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  292.667723] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  292.668821] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  292.668856] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  292.671090] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  292.671125] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  292.673339] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  292.673375] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  292.675604] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  292.675640] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  292.677861] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  292.677897] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  292.680154] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  292.680194] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  292.682412] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  292.682447] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  292.700996] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  292.701030] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  292.702633] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  292.702669] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  292.704770] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  292.704810] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  292.707043] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  292.707078] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  292.709265] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  292.709300] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  292.711538] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  292.711574] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  292.713797] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  292.713834] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  292.716099] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  292.716145] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  292.734254] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  292.734288] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  292.736276] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  292.736312] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  292.738545] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  292.738581] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  292.740674] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  292.740709] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  292.742942] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  292.742978] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  292.745182] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  292.745217] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  292.747439] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  292.747475] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  292.749698] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  292.749733] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  292.767704] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  292.767738] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  292.769902] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  292.769938] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  292.772189] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  292.772225] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  292.774446] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  292.774481] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  292.776568] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  292.776603] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  292.778832] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  292.778869] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  292.781062] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  292.781098] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  292.783325] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  292.783362] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  292.800998] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  292.801034] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  292.801154] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  292.801180] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  292.803490] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  292.803526] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  292.805743] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  292.805779] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  292.807997] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  292.808081] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  292.810275] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  292.810312] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  292.812367] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  292.812403] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  292.814657] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  292.814693] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  292.816875] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  292.816911] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  292.834359] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  292.834393] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  292.834926] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  292.834961] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  292.837023] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  292.837057] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  292.839312] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  292.839348] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  292.841562] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  292.841598] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  292.843824] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  292.843859] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  292.846090] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  292.846127] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  292.848354] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  292.848390] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  292.850616] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  292.850652] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  292.867686] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  292.867721] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  292.868558] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  292.868593] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  292.870821] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  292.870856] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  292.873056] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  292.873091] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  292.875320] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  292.875355] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  292.877570] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  292.877606] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  292.879835] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  292.879870] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  292.882103] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  292.882140] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  292.900998] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  292.901032] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  292.902448] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  292.902483] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  292.904570] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  292.904606] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  292.906840] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  292.906876] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  292.909073] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  292.909109] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  292.911337] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  292.911372] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  292.913591] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  292.913627] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  292.915856] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  292.915892] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  292.934312] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  292.934346] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  292.936211] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  292.936247] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  292.938470] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  292.938505] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  292.940595] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  292.940631] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  292.942853] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  292.942890] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  292.945085] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  292.945120] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  292.947347] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  292.947384] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  292.949608] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  292.949644] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  292.967668] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  292.967703] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  292.969872] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  292.969909] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  292.972157] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  292.972197] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  292.974427] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  292.974463] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  292.976554] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  292.976591] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  292.978818] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  292.978854] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  292.981051] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  292.981086] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  292.983312] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  292.983348] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  293.000996] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  293.001030] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  293.001133] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  293.001158] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  293.003478] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  293.003513] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  293.005731] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  293.005767] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  293.007996] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  293.008077] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  293.010255] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  293.010290] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  293.012391] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  293.012426] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  293.014656] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  293.014692] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  293.016871] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  293.016906] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  293.034364] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  293.034398] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  293.034888] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  293.034924] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  293.037115] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  293.037151] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  293.039382] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  293.039418] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  293.041631] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  293.041667] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  293.043896] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  293.043932] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  293.046159] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  293.046195] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  293.048352] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  293.048390] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  293.050611] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  293.050647] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  293.067690] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  293.067725] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  293.068476] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  293.068509] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  293.070764] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  293.070800] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  293.072994] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  293.073029] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  293.075255] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  293.075291] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  293.077509] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  293.077545] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  293.079776] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  293.079812] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  293.082038] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  293.082073] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  293.101009] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  293.101044] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  293.102359] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  293.102395] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  293.104473] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  293.104509] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  293.106740] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  293.106776] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  293.108952] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  293.108999] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  293.111228] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  293.111264] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  293.113476] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  293.113512] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  293.115740] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  293.115776] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  293.134311] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  293.134346] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  293.136059] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  293.136102] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  293.138288] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  293.138323] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  293.140391] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  293.140426] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  293.142679] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  293.142715] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  293.144892] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  293.144927] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  293.147154] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  293.147190] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  293.149400] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  293.149437] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  293.167565] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  293.167600] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  293.169633] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  293.169669] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  293.171893] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  293.171929] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  293.174161] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  293.174197] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  293.176350] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  293.176386] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  293.178609] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  293.178646] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  293.180822] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  293.180857] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  293.183079] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  293.183116] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  293.201045] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  293.201080] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  293.203351] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  293.203386] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  293.205604] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  293.205640] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  293.207867] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  293.207903] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  293.210097] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  293.210134] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  293.212350] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  293.212387] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  293.214610] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  293.214645] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  293.216815] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  293.216851] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  293.234357] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  293.234392] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  293.234833] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  293.234869] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  293.237069] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  293.237105] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  293.239338] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  293.239374] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  293.241543] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  293.241578] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  293.243805] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  293.243840] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  293.246057] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  293.246092] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  293.248339] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  293.248375] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  293.250601] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  293.250637] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  293.267685] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  293.267720] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  293.268563] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  293.268598] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  293.270819] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  293.270854] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  293.273059] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  293.273095] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  293.275322] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  293.275357] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  293.277574] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  293.277609] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  293.279836] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  293.279871] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  293.282105] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  293.282140] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  293.301005] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  293.301040] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  293.302339] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  293.302374] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  293.304466] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  293.304502] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  293.306731] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  293.306767] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  293.308949] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  293.308985] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  293.311196] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  293.311232] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  293.313446] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  293.313482] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  293.315712] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  293.315747] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  293.334341] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  293.334375] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  293.335578] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  293.335613] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  293.337836] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  293.337873] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  293.340136] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  293.340173] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  293.342367] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  293.342402] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  293.344496] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  293.344531] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  293.346753] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  293.346790] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  293.348973] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  293.349009] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  293.367664] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  293.367698] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  293.368921] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  293.368954] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  293.371213] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  293.371249] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  293.373459] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  293.373495] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  293.375720] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  293.375756] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  293.377990] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  293.378026] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  293.380270] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  293.380306] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  293.382531] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  293.382567] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  293.400974] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  293.401009] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  293.402794] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  293.402830] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  293.405024] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  293.405060] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  293.407289] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  293.407324] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  293.409543] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  293.409579] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  293.411789] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  293.411825] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  293.414049] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  293.414086] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  293.416328] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  293.416364] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  293.434361] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  293.434395] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  293.436437] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  293.436472] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  293.438694] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  293.438730] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  293.440909] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  293.440946] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  293.443172] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  293.443208] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  293.445420] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  293.445457] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  293.447687] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  293.447723] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  293.449937] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  293.449973] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  293.467687] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  293.467722] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  293.467803] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  293.467827] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  293.470141] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  293.470177] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  293.472351] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  293.472387] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  293.474614] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  293.474649] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  293.476824] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  293.476860] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  293.479087] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  293.479122] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  293.481333] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  293.481368] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  293.483597] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  293.483634] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  293.501016] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  293.501052] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  293.501671] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  293.501707] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  293.503936] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  293.503972] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  293.506198] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  293.506233] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  293.508349] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  293.508386] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  293.510585] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  293.510620] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  293.512730] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  293.512765] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  293.514993] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  293.515029] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  293.517234] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  293.517270] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  293.534352] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  293.534387] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  293.535313] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  293.535349] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  293.537556] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  293.537592] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  293.539819] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  293.539855] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  293.542089] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  293.542126] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  293.544352] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  293.544387] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  293.546617] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  293.546652] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  293.548818] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  293.548854] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  293.567657] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  293.567691] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  293.569022] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  293.569058] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  293.571284] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  293.571319] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  293.573531] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  293.573568] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  293.575795] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  293.575832] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  293.578064] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  293.578100] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  293.580340] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  293.580377] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  293.582603] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  293.582639] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  293.600916] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  293.600949] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  293.602926] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  293.602961] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  293.605162] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  293.605196] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  293.607432] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  293.607468] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  293.609686] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  293.609721] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  293.611919] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  293.611953] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  293.614185] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  293.614221] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  293.616346] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  293.616392] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  293.634361] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  293.634395] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  293.636380] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  293.636415] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  293.638666] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  293.638701] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  293.640881] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  293.640916] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  293.643142] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  293.643177] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  293.645389] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  293.645424] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  293.647650] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  293.647686] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  293.649912] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  293.649948] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  293.667711] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  293.667745] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  293.670020] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  293.670055] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  293.672307] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  293.672342] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  293.674551] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  293.674588] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  293.676761] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  293.676798] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  293.679023] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  293.679060] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  293.681264] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  293.681300] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  293.683529] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  293.683566] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  293.701006] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  293.701041] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  293.701318] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  293.701352] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  293.703588] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  293.703623] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  293.705846] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  293.705882] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  293.708146] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  293.708188] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  293.710386] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  293.710422] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  293.712503] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  293.712540] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  293.714769] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  293.714805] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  293.716892] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  293.716928] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  293.734372] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  293.734407] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  293.734958] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  293.734994] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  293.737203] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  293.737239] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  293.739468] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  293.739504] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  293.741721] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  293.741757] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  293.743984] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  293.744060] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  293.746249] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  293.746285] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  293.748372] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  293.748407] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  293.750634] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  293.750675] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  293.767664] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  293.767698] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  293.768555] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  293.768590] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  293.770806] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  293.770841] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  293.773033] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  293.773069] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  293.775297] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  293.775332] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  293.777548] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  293.777584] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  293.779809] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  293.779845] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  293.782073] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  293.782109] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  293.800995] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  293.801030] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  293.802208] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  293.802243] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  293.804339] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  293.804375] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  293.806606] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  293.806642] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  293.808812] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  293.808847] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  293.811074] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  293.811110] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  293.813315] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  293.813351] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  293.815577] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  293.815614] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  293.834328] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  293.834364] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  293.835670] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  293.835706] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  293.837927] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  293.837963] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  293.840203] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  293.840239] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  293.842469] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  293.842505] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  293.844584] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  293.844620] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  293.846848] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  293.846883] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  293.849090] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  293.849127] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  293.867672] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  293.867707] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  293.869250] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  293.869286] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  293.871514] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  293.871550] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  293.873770] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  293.873806] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  293.876072] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  293.876115] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  293.878286] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  293.878322] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  293.880378] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  293.880415] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  293.882680] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  293.882716] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  293.900885] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  293.900919] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  293.903014] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  293.903049] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  293.905111] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  293.905145] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  293.907396] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  293.907432] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  293.909645] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  293.909681] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  293.911899] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  293.911950] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  293.914171] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  293.914207] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  293.916344] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  293.916380] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  293.934354] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  293.934389] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  293.936424] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  293.936459] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  293.938694] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  293.938730] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  293.940909] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  293.940945] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  293.943171] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  293.943206] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  293.945418] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  293.945453] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  293.947683] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  293.947720] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  293.949939] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  293.949974] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  293.967651] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  293.967686] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  293.967872] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  293.967906] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  293.970163] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  293.970199] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  293.972349] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  293.972386] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  293.974603] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  293.974639] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  293.976808] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  293.976843] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  293.979070] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  293.979106] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  293.981216] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  293.981252] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  293.983477] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  293.983513] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  294.000991] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  294.001027] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  294.001530] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  294.001565] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  294.003796] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  294.003831] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  294.006057] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  294.006093] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  294.008336] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  294.008372] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  294.010594] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  294.010630] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  294.012795] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  294.012832] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  294.015056] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  294.015092] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  294.017306] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  294.017348] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  294.034332] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  294.034367] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  294.035359] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  294.035395] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  294.037610] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  294.037646] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  294.039872] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  294.039908] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  294.042140] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  294.042176] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  294.044343] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  294.044379] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  294.046611] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  294.046647] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  294.048819] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  294.048856] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  294.067645] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  294.067679] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  294.069018] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  294.069055] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  294.071279] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  294.071315] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  294.073530] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  294.073566] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  294.075791] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  294.075826] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  294.078054] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  294.078089] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  294.080336] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  294.080371] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  294.082588] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  294.082624] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  294.100881] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  294.100916] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  294.102986] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  294.103021] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  294.105224] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  294.105261] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  294.107497] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  294.107532] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  294.109753] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  294.109790] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  294.112018] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  294.112094] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  294.114276] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  294.114312] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  294.116401] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  294.116438] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  294.134345] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  294.134380] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  294.136384] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  294.136421] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  294.138681] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  294.138717] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  294.140895] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  294.140932] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  294.143157] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  294.143192] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  294.145381] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  294.145418] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  294.147646] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  294.147683] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  294.149909] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  294.149945] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  294.167514] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  294.167547] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  294.167845] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  294.167879] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  294.170135] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  294.170172] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  294.172351] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  294.172388] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  294.174613] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  294.174649] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  294.176826] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  294.176861] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  294.179091] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  294.179126] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  294.181334] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  294.181370] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  294.183600] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  294.183636] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  294.201008] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  294.201043] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  294.201694] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  294.201729] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  294.203959] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  294.203995] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  294.206221] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  294.206257] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  294.208357] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  294.208392] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  294.210623] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  294.210659] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  294.212831] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  294.212867] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  294.215092] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  294.215128] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  294.217349] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  294.217385] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  294.234335] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  294.234370] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  294.235251] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  294.235287] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  294.237499] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  294.237534] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  294.239763] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  294.239798] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  294.242009] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  294.242045] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  294.244290] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  294.244326] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  294.246557] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  294.246593] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  294.248700] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  294.248736] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  294.267660] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  294.267693] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  294.269017] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  294.269052] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  294.271145] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  294.271180] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  294.273385] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  294.273421] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  294.275650] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  294.275686] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  294.277899] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  294.277935] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  294.280168] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  294.280205] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  294.282417] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  294.282453] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  294.300979] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  294.301014] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  294.302467] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  294.302502] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  294.304577] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  294.304612] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  294.306852] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  294.306887] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  294.309082] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  294.309118] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  294.311343] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  294.311379] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  294.313480] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  294.313516] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  294.315737] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  294.315773] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  294.334316] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  294.334350] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  294.335629] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  294.335664] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  294.337889] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  294.337924] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  294.340175] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  294.340211] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  294.342425] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  294.342461] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  294.344553] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  294.344588] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  294.346816] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  294.346852] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  294.349045] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  294.349081] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  294.367647] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  294.367692] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  294.369256] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  294.369292] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  294.371519] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  294.371555] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  294.373774] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  294.373810] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  294.376075] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  294.376118] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  294.378300] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  294.378335] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  294.380398] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  294.380434] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  294.382690] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  294.382725] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  294.400875] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  294.400910] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  294.403057] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  294.403092] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  294.405302] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  294.405338] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  294.407565] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  294.407601] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  294.409781] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  294.409816] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  294.412079] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  294.412122] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  294.414257] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  294.414291] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  294.416403] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  294.416440] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  294.434339] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  294.434374] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  294.436433] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  294.436469] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  294.438698] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  294.438734] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  294.440907] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  294.440945] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  294.443174] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  294.443209] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  294.445418] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  294.445454] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  294.447683] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  294.447719] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  294.449942] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  294.449978] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  294.467671] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  294.467709] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  294.467785] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  294.467810] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  294.470057] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  294.470093] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  294.472333] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  294.472369] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  294.474597] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  294.474633] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  294.476796] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  294.476832] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  294.479059] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  294.479095] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  294.481277] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  294.481313] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  294.483536] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  294.483572] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  294.500978] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  294.501013] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  294.501451] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  294.501486] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  294.503717] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  294.503753] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  294.505982] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  294.506018] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  294.508263] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  294.508301] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  294.510527] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  294.510563] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  294.512652] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  294.512687] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  294.514882] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  294.514917] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  294.517121] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  294.517157] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  294.534321] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  294.534355] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  294.535171] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  294.535207] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  294.537412] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  294.537447] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  294.539683] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  294.539719] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  294.541943] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  294.541980] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  294.544220] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  294.544256] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  294.546472] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  294.546508] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  294.548589] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  294.548625] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  294.567650] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  294.567684] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  294.568916] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  294.568952] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  294.571178] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  294.571212] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  294.573429] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  294.573465] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  294.575688] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  294.575723] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  294.577950] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  294.577987] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  294.580228] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  294.580264] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  294.582488] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  294.582524] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  294.600957] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  294.600991] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  294.602777] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  294.602813] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  294.605004] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  294.605041] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  294.607268] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  294.607303] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  294.609514] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  294.609549] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  294.611776] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  294.611812] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  294.614037] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  294.614074] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  294.616306] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  294.616341] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  294.634359] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  294.634393] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  294.636368] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  294.636404] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  294.638674] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  294.638709] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  294.640889] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  294.640925] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  294.643154] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  294.643190] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  294.645377] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  294.645412] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  294.647636] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  294.647673] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  294.649899] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  294.649934] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  294.667688] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  294.667723] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  294.669885] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  294.669920] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  294.672161] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  294.672201] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  294.674423] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  294.674459] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  294.676552] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  294.676587] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  294.678818] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  294.678853] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  294.681046] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  294.681082] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  294.683311] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  294.683345] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  294.701011] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  294.701045] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  294.701258] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  294.701292] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  294.703546] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  294.703582] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  294.705663] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  294.705697] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  294.707950] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  294.707985] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  294.710214] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  294.710249] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  294.712347] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  294.712395] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  294.714596] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  294.714632] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  294.716796] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  294.716831] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  294.734353] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  294.734387] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  294.734821] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  294.734857] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  294.737082] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  294.737119] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  294.739345] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  294.739381] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  294.741604] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  294.741639] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  294.743865] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  294.743900] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  294.746132] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  294.746169] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  294.748335] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  294.748371] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  294.750597] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  294.750640] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  294.767654] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  294.767695] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  294.768471] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  294.768505] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  294.770750] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  294.770785] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  294.772884] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  294.772920] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  294.775148] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  294.775184] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  294.777395] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  294.777432] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  294.779657] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  294.779693] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  294.781920] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  294.781955] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  294.800991] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  294.801025] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  294.802333] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  294.802368] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  294.804465] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  294.804501] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  294.806731] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  294.806767] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  294.808961] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  294.808997] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  294.811225] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  294.811261] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  294.813477] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  294.813514] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  294.815594] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  294.815629] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  294.834144] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  294.834175] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  294.834696] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  294.834725] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  294.836831] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  294.836862] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  294.838966] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  294.838996] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  294.841101] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  294.841131] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  294.843230] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  294.843260] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  294.845365] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  294.845395] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  294.847500] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  294.847529] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  294.849628] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  294.849658] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  294.867465] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  294.867495] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  294.868788] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  294.868818] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  294.870916] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  294.870946] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  294.873053] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  294.873083] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  294.875183] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  294.875213] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  294.877320] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  294.877350] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  294.879449] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  294.879480] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  294.881586] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  294.881616] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  294.883715] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  294.883745] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  294.900768] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  294.900797] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  294.902841] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  294.902862] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  294.904974] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  294.904996] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  294.907102] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  294.907121] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  294.909239] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  294.909258] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  294.911370] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  294.911388] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  294.913507] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  294.913526] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  294.915806] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  294.915839] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  294.934266] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  294.934297] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  294.936151] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  294.936188] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  294.938433] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  294.938466] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  294.940558] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  294.940591] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  294.942830] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  294.942861] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  294.945072] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  294.945105] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  294.947343] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  294.947376] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  294.949598] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  294.949631] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  294.967665] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  294.967699] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  294.969838] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  294.969873] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  294.972140] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  294.972176] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  294.974365] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  294.974402] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  294.976483] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  294.976519] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  294.978754] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  294.978790] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  294.980968] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  294.981004] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  294.983231] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  294.983267] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  295.017706] [drm:drm_mode_addfb2 [drm]] [FB:72]
>[  295.017755] [drm:drm_mode_addfb2 [drm]] [FB:73]
>[  295.044603] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  295.044634] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  295.044648] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[  295.044668] [drm:intel_power_well_enable [i915]] enabling DC off
>[  295.044679] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  295.044697] [drm:intel_edp_backlight_off [i915]] 
>[  295.252295] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0
>[  295.252427] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  295.268706] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[  295.268864] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b
>[  295.269168] [drm:intel_edp_panel_off.part.31 [i915]] Turn eDP port A panel power off
>[  295.269280] [drm:intel_edp_panel_off.part.31 [i915]] Wait for panel power off time
>[  295.269410] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000002 control 00000060
>[  295.321214] [drm:wait_panel_status [i915]] Wait complete
>[  295.321277] [drm:intel_power_well_disable [i915]] disabling DDI A/E IO power well
>[  295.321360] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  295.321438] [drm:intel_disable_shared_dpll [i915]] disable DPLL 0 (active 1, on? 1) for crtc 37
>[  295.321509] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 0
>[  295.321598] [drm:intel_atomic_commit_tail [i915]] [ENCODER:48:DDI A]
>[  295.321669] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI B]
>[  295.321736] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  295.321801] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  295.321864] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DDI C]
>[  295.321925] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST A]
>[  295.321985] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST B]
>[  295.322046] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI D]
>[  295.322106] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[  295.322166] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[  295.322232] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:49:eDP-1]
>[  295.322299] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[  295.322365] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[  295.322428] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[  295.322490] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[  295.322566] [drm:intel_atomic_commit_tail [i915]] [CRTC:37:pipe A]
>[  295.322631] [drm:intel_power_well_disable [i915]] disabling DC off
>[  295.322694] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  295.322758] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  295.323200] [drm:intel_power_well_disable [i915]] disabling always-on
>[  295.323265] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  295.323342] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  295.323371] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  295.323460] [drm:intel_atomic_check [i915]] [CONNECTOR:49:eDP-1] checking for sink bpp constrains
>[  295.323523] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  295.323555] [drm:drm_mode_debug_printmodeline [drm]] Modeline 52:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[  295.323625] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 138780KHz
>[  295.323707] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24
>[  295.323770] [drm:intel_dp_compute_config [i915]] DP link bw required 416340 available 540000
>[  295.323831] [drm:intel_dp_compute_config [i915]] PSR disable by flag
>[  295.323896] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  295.323961] [drm:intel_dump_pipe_config [i915]] [CRTC:47:pipe B][modeset]
>[  295.324023] [drm:intel_dump_pipe_config [i915]] output_types: EDP (0x100)
>[  295.324127] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0
>[  295.324198] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 6467616, gmch_n: 8388608, link_m: 269484, link_n: 524288, tu: 64
>[  295.324265] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  295.324326] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  295.324362] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[  295.324427] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  295.324459] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[  295.324523] [drm:intel_dump_pipe_config [i915]] crtc timings: 138780 1920 1966 1996 2080 1080 1082 1086 1112, type: 0x48 flags: 0xa
>[  295.324584] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 138780
>[  295.324647] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  295.324707] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  295.324773] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  295.324851] [drm:intel_dump_pipe_config [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  295.324913] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  295.324976] [drm:intel_dump_pipe_config [i915]] [PLANE:38:plane 1B] disabled, scaler_id = -1
>[  295.325036] [drm:intel_dump_pipe_config [i915]] [PLANE:41:plane 2B] disabled, scaler_id = -1
>[  295.325097] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor B] disabled, scaler_id = -1
>[  295.325170] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  295.325238] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[  295.325316] [drm:intel_find_shared_dpll [i915]] [CRTC:47:pipe B] allocated DPLL 0
>[  295.325383] [drm:intel_reference_shared_dpll [i915]] using DPLL 0 for pipe B
>[  295.328208] [drm:intel_power_well_enable [i915]] enabling always-on
>[  295.328253] [drm:intel_power_well_enable [i915]] enabling DC off
>[  295.328546] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  295.328595] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  295.328675] [drm:intel_atomic_commit_tail [i915]] [ENCODER:48:DDI A]
>[  295.328735] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI B]
>[  295.328789] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  295.328841] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  295.328893] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DDI C]
>[  295.328942] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST A]
>[  295.329003] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST B]
>[  295.329053] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI D]
>[  295.329102] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[  295.329151] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[  295.329204] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[  295.329279] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[  295.329343] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010
>[  295.329413] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  295.329463] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[  295.329514] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[  295.329581] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0
>[  295.329642] [drm:intel_enable_shared_dpll [i915]] enable DPLL 0 (active 2, on? 0) for crtc 47
>[  295.329708] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  295.329769] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 0
>[  295.329853] [drm:edp_panel_on [i915]] Turn eDP port A panel power on
>[  295.329928] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle
>[  295.932435] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 00000000 control 00000060
>[  295.932542] [drm:wait_panel_status [i915]] Wait complete
>[  295.932681] [drm:edp_panel_on [i915]] Wait for panel power on
>[  295.932813] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 00000063
>[  295.964395] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010
>[  295.964477] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  295.964550] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1
>[  295.964661] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  296.134933] [drm:wait_panel_status [i915]] Wait complete
>[  296.134999] [drm:intel_power_well_enable [i915]] enabling DDI A/E IO power well
>[  296.135102] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[  296.135253] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b
>[  296.136492] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  296.136564] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  296.136629] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  296.136692] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  296.137407] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  296.137467] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  296.138478] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  296.138540] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:49:eDP-1] Link Training Passed at Link Rate = 270000, Lane count = 2
>[  296.139201] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  296.139304] [drm:intel_edp_backlight_on [i915]] 
>[  296.139367] [drm:intel_panel_enable_backlight [i915]] pipe B
>[  296.139456] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 120000
>[  296.144167] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS
>[  296.156130] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:49:eDP-1]
>[  296.156218] [drm:intel_atomic_commit_tail [i915]] [CRTC:47:pipe B]
>[  296.156315] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[  296.172805] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  296.172837] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  296.174837] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  296.174868] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  296.177068] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  296.177100] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  296.179353] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  296.179389] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  296.181587] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  296.181624] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  296.183844] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  296.183880] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  296.186101] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  296.186137] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  296.188368] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  296.188404] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  296.206303] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  296.206337] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  296.208385] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  296.208421] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  296.210631] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  296.210667] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  296.212843] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  296.212878] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  296.215102] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  296.215138] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  296.217341] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  296.217376] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  296.219602] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  296.219637] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  296.221845] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  296.221880] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  296.239639] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  296.239675] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  296.241927] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  296.241962] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  296.244195] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  296.244232] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  296.246449] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  296.246484] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  296.248574] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  296.248609] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  296.250836] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  296.250872] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  296.253058] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  296.253094] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  296.255321] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  296.255357] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  296.272923] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  296.272958] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  296.273050] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  296.273076] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  296.275395] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  296.275431] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  296.277649] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  296.277686] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  296.279905] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  296.279941] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  296.282158] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  296.282194] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  296.284347] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  296.284383] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  296.286607] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  296.286641] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  296.288806] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  296.288841] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  296.306299] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  296.306333] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  296.306412] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  296.306437] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  296.308586] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  296.308621] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  296.310847] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  296.310883] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  296.312976] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  296.313012] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  296.315239] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  296.315275] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  296.317487] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  296.317522] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  296.319749] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  296.319784] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  296.321997] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  296.322033] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  296.339634] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  296.339669] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  296.339749] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  296.339774] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  296.342088] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  296.342124] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  296.344359] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  296.344395] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  296.346610] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  296.346645] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  296.348820] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  296.348856] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  296.351082] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  296.351117] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  296.353327] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  296.353362] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  296.355588] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  296.355624] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  296.372959] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  296.372993] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  296.373583] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  296.373619] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  296.375845] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  296.375882] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  296.378105] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  296.378142] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  296.380344] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  296.380382] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  296.382610] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  296.382645] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  296.384816] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  296.384852] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  296.387081] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  296.387117] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  296.389347] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  296.389382] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  296.406282] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  296.406316] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  296.407423] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  296.407459] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  296.409662] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  296.409698] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  296.411920] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  296.411957] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  296.414186] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  296.414222] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  296.416341] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  296.416378] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  296.418607] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  296.418642] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  296.420811] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  296.420847] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  296.439595] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  296.439629] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  296.440999] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  296.441036] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  296.443259] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  296.443294] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  296.445509] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  296.445545] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  296.447771] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  296.447807] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  296.450034] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  296.450070] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  296.452318] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  296.452355] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  296.454583] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  296.454618] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  296.472830] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  296.472865] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  296.474916] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  296.474951] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  296.477146] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  296.477182] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  296.479407] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  296.479442] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  296.481662] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  296.481697] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  296.483927] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  296.483962] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  296.486189] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  296.486225] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  296.488341] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  296.488377] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  296.506304] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  296.506339] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  296.508371] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  296.508408] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  296.510640] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  296.510676] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  296.512853] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  296.512889] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  296.515116] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  296.515152] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  296.517359] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  296.517394] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  296.519620] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  296.519656] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  296.521831] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  296.521867] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  296.539639] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  296.539674] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  296.541969] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  296.542004] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  296.544238] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  296.544275] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  296.546503] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  296.546540] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  296.548628] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  296.548664] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  296.550898] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  296.550935] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  296.553133] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  296.553169] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  296.555389] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  296.555425] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  296.572957] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  296.572992] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  296.573442] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  296.573478] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  296.575695] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  296.575732] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  296.577950] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  296.577986] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  296.580224] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  296.580261] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  296.582491] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  296.582527] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  296.584616] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  296.584653] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  296.586876] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  296.586913] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  296.589113] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  296.589149] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  296.606287] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  296.606321] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  296.607189] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  296.607225] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  296.609436] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  296.609472] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  296.611703] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  296.611739] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  296.613963] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  296.614000] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  296.616232] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  296.616267] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  296.618498] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  296.618534] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  296.620622] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  296.620658] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  296.639606] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  296.639640] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  296.640926] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  296.640962] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  296.643191] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  296.643227] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  296.645435] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  296.645470] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  296.647697] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  296.647732] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  296.649959] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  296.649995] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  296.652230] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  296.652265] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  296.654496] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  296.654532] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  296.672905] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  296.672939] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  296.674645] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  296.674680] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  296.676849] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  296.676885] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  296.679111] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  296.679147] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  296.681355] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  296.681390] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  296.683617] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  296.683653] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  296.685873] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  296.685910] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  296.688159] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  296.688200] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  296.706172] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  296.706207] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  296.708344] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  296.708380] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  296.710605] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  296.710641] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  296.712806] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  296.712842] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  296.715061] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  296.715096] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  296.717305] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  296.717341] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  296.719564] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  296.719599] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  296.721823] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  296.721858] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  296.739635] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  296.739669] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  296.741968] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  296.742004] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  296.744239] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  296.744275] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  296.746494] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  296.746531] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  296.748624] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  296.748661] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  296.750889] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  296.750925] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  296.753124] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  296.753160] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  296.755384] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  296.755420] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  296.772963] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  296.772999] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  296.773436] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  296.773471] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  296.775657] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  296.775693] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  296.777918] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  296.777955] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  296.780193] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  296.780230] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  296.782462] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  296.782498] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  296.784588] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  296.784623] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  296.786851] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  296.786887] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  296.789081] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  296.789117] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  296.806283] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  296.806317] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  296.807135] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  296.807170] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  296.809379] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  296.809415] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  296.811643] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  296.811678] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  296.813906] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  296.813943] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  296.816165] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  296.816201] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  296.818437] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  296.818473] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  296.820559] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  296.820594] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  296.822715] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  296.822750] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  296.839603] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  296.839637] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  296.840650] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  296.840687] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  296.842903] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  296.842940] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  296.845128] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  296.845164] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  296.847388] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  296.847424] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  296.849642] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  296.849678] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  296.851901] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  296.851937] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  296.854166] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  296.854203] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  296.872944] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  296.872980] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  296.874347] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  296.874383] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  296.876462] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  296.876498] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  296.878733] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  296.878769] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  296.880953] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  296.880989] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  296.883215] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  296.883250] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  296.885464] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  296.885500] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  296.887728] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  296.887764] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  296.906234] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  296.906268] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  296.908114] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  296.908158] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  296.910335] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  296.910372] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  296.912466] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  296.912502] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  296.914736] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  296.914772] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  296.916951] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  296.916987] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  296.919217] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  296.919253] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  296.921462] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  296.921498] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  296.939594] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  296.939628] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  296.941793] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  296.941829] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  296.944100] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  296.944146] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  296.946319] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  296.946355] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  296.948445] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  296.948480] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  296.950704] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  296.950740] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  296.952915] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  296.952951] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  296.955177] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  296.955213] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  296.972959] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  296.972994] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  296.973072] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  296.973097] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  296.975398] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  296.975434] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  296.977630] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  296.977665] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  296.979894] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  296.979931] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  296.982163] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  296.982200] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  296.984341] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  296.984378] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  296.986606] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  296.986642] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  296.988807] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  296.988844] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  297.006283] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  297.006318] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  297.006838] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  297.006874] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  297.009057] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  297.009094] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  297.011319] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  297.011356] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  297.013552] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  297.013589] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  297.015816] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  297.015852] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  297.018079] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  297.018115] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  297.020344] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  297.020380] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  297.022612] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  297.022648] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  297.039622] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  297.039657] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  297.040570] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  297.040606] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  297.042835] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  297.042871] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  297.045066] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  297.045102] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  297.047332] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  297.047368] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  297.049577] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  297.049613] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  297.051841] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  297.051877] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  297.054105] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  297.054141] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  297.072919] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  297.072953] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  297.074348] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  297.074385] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  297.076475] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  297.076511] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  297.078743] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  297.078779] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  297.080878] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  297.080914] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  297.083140] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  297.083175] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  297.085386] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  297.085422] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  297.087652] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  297.087687] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  297.106244] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  297.106278] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  297.107880] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  297.107917] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  297.110147] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  297.110184] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  297.112342] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  297.112377] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  297.114609] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  297.114645] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  297.116817] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  297.116853] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  297.119082] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  297.119118] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  297.121325] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  297.121360] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  297.139494] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  297.139528] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  297.141557] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  297.141594] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  297.143818] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  297.143854] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  297.146082] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  297.146118] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  297.148344] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  297.148380] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  297.150610] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  297.150646] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  297.152821] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  297.152856] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  297.155081] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  297.155117] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  297.172962] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  297.172997] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  297.175309] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  297.175345] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  297.177555] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  297.177591] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  297.179817] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  297.179853] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  297.182071] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  297.182108] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  297.184350] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  297.184386] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  297.186611] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  297.186647] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  297.188819] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  297.188855] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  297.206309] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  297.206344] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  297.206839] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  297.206876] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  297.209070] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  297.209107] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  297.211331] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  297.211366] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  297.213575] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  297.213611] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  297.215840] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  297.215876] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  297.218101] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  297.218136] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  297.220344] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  297.220381] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  297.222623] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  297.222659] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  297.239628] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  297.239663] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  297.240553] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  297.240589] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  297.242815] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  297.242851] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  297.244948] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  297.244985] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  297.247206] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  297.247241] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  297.249458] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  297.249494] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  297.251719] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  297.251754] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  297.253980] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  297.254016] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  297.272950] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  297.272985] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  297.274385] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  297.274420] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  297.276466] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  297.276501] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  297.278769] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  297.278805] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  297.280990] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  297.281026] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  297.283254] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  297.283290] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  297.285505] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  297.285541] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  297.287771] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  297.287807] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  297.306221] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  297.306255] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  297.308124] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  297.308163] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  297.310349] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  297.310385] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  297.312465] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  297.312501] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  297.314737] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  297.314772] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  297.316951] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  297.316986] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  297.319215] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  297.319251] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  297.321441] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  297.321476] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  297.339483] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  297.339518] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  297.341633] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  297.341669] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  297.343892] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  297.343928] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  297.346154] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  297.346190] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  297.348359] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  297.348395] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  297.350627] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  297.350664] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  297.352837] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  297.352873] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  297.355093] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  297.355128] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  297.372961] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  297.372999] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  297.373078] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  297.373104] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  297.375327] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  297.375364] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  297.377577] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  297.377614] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  297.379839] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  297.379875] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  297.382106] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  297.382142] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  297.384350] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  297.384389] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  297.386618] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  297.386654] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  297.388706] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  297.388742] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  297.406278] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  297.406312] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  297.406653] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  297.406689] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  297.408741] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  297.408777] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  297.411003] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  297.411038] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  297.413247] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  297.413283] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  297.415508] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  297.415544] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  297.417767] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  297.417803] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  297.420062] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  297.420105] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  297.422278] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  297.422314] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  297.439610] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  297.439644] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  297.440109] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  297.440149] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  297.442364] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  297.442400] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  297.444455] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  297.444490] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  297.446724] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  297.446760] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  297.448947] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  297.448983] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  297.451208] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  297.451245] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  297.453456] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  297.453493] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  297.455721] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  297.455757] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  297.472938] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  297.472973] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  297.473771] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  297.473807] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  297.476073] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  297.476115] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  297.478287] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  297.478323] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  297.480398] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  297.480435] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  297.482649] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  297.482685] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  297.484861] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  297.484898] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  297.487130] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  297.487165] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  297.489379] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  297.489414] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  297.506263] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  297.506298] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  297.507371] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  297.507407] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  297.509622] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  297.509659] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  297.511885] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  297.511921] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  297.514151] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  297.514187] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  297.516353] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  297.516389] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  297.518621] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  297.518657] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  297.520709] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  297.520745] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  297.539600] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  297.539636] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  297.540886] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  297.540922] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  297.543147] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  297.543182] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  297.545394] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  297.545429] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  297.547656] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  297.547692] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  297.549916] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  297.549952] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  297.552198] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  297.552235] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  297.554459] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  297.554496] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  297.572892] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  297.572926] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  297.574668] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  297.574704] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  297.576764] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  297.576799] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  297.579020] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  297.579056] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  297.581259] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  297.581295] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  297.583524] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  297.583561] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  297.585780] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  297.585815] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  297.588087] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  297.588129] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  297.606142] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  297.606176] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  297.608270] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  297.608306] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  297.610508] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  297.610544] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  297.612602] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  297.612637] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  297.614863] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  297.614899] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  297.617097] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  297.617133] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  297.619364] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  297.619400] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  297.621606] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  297.621643] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  297.639618] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  297.639652] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  297.641819] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  297.641855] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  297.644122] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  297.644161] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  297.646350] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  297.646386] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  297.648449] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  297.648485] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  297.650710] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  297.650746] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  297.652925] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  297.652961] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  297.655188] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  297.655224] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  297.672947] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  297.672981] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  297.673062] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  297.673087] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  297.675419] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  297.675455] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  297.677671] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  297.677707] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  297.679937] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  297.679973] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  297.682197] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  297.682233] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  297.684352] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  297.684390] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  297.686612] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  297.686649] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  297.688698] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  297.688734] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  297.706282] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  297.706317] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  297.706645] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  297.706682] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  297.708733] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  297.708768] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  297.710999] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  297.711035] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  297.713238] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  297.713274] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  297.715501] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  297.715536] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  297.717758] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  297.717794] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  297.720062] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  297.720108] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  297.722282] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  297.722317] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  297.739609] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  297.739643] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  297.739893] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  297.739926] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  297.742182] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  297.742217] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  297.744354] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  297.744391] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  297.746615] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  297.746651] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  297.748709] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  297.748745] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  297.750972] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  297.751007] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  297.753214] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  297.753250] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  297.755476] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  297.755513] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  297.772943] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  297.772977] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  297.773540] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  297.773575] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  297.775806] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  297.775842] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  297.778051] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  297.778086] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  297.780336] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  297.780373] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  297.782595] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  297.782630] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  297.784683] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  297.784720] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  297.786950] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  297.786986] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  297.789179] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  297.789215] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  297.806269] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  297.806304] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  297.807048] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  297.807085] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  297.809286] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  297.809323] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  297.811548] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  297.811584] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  297.813806] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  297.813842] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  297.816112] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  297.816151] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  297.818331] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  297.818366] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  297.820432] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  297.820468] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  297.822704] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  297.822739] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  297.839583] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  297.839617] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  297.840502] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  297.840536] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  297.842786] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  297.842822] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  297.845021] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  297.845058] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  297.847282] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  297.847318] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  297.849541] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  297.849576] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  297.851801] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  297.851837] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  297.854064] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  297.854100] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  297.872902] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  297.872936] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  297.874355] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  297.874390] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  297.876455] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  297.876490] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  297.878573] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  297.878609] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  297.880664] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  297.880699] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  297.882928] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  297.882963] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  297.885173] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  297.885209] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  297.887436] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  297.887473] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  297.906248] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  297.906283] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  297.907682] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  297.907719] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  297.909942] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  297.909978] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  297.912223] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  297.912259] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  297.914481] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  297.914517] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  297.916572] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  297.916607] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  297.918839] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  297.918875] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  297.921072] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  297.921108] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  297.939555] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  297.939589] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  297.941269] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  297.941305] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  297.943532] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  297.943567] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  297.945786] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  297.945821] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  297.948089] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  297.948147] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  297.950313] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  297.950349] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  297.952371] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  297.952407] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  297.954673] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  297.954709] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  297.972818] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  297.972852] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  297.975027] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  297.975063] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  297.977269] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  297.977305] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  297.979493] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  297.979528] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  297.981751] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  297.981787] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  297.984010] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  297.984088] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  297.986272] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  297.986309] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  297.988409] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  297.988447] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  298.006290] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  298.006326] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  298.008402] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  298.008438] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  298.010669] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  298.010704] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  298.012758] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  298.012794] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  298.015023] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  298.015059] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  298.017264] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  298.017299] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  298.019534] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  298.019569] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  298.021788] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  298.021824] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  298.039618] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  298.039652] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  298.041880] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  298.041917] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  298.044223] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  298.044260] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  298.046420] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  298.046456] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  298.048511] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  298.048546] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  298.050787] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  298.050822] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  298.053016] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  298.053052] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  298.055282] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  298.055318] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  298.072938] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  298.072973] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  298.073256] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  298.073290] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  298.075545] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  298.075581] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  298.077797] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  298.077833] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  298.080068] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  298.080110] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  298.082289] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  298.082325] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  298.084395] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  298.084432] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  298.086665] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  298.086701] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  298.088878] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  298.088915] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  298.106270] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  298.106305] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  298.106906] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  298.106943] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  298.109132] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  298.109167] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  298.111394] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  298.111431] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  298.113650] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  298.113686] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  298.115914] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  298.115949] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  298.118175] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  298.118212] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  298.120356] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  298.120392] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  298.122610] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  298.122646] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  298.139590] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  298.139626] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  298.140298] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  298.140332] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  298.142580] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  298.142615] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  298.144669] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  298.144706] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  298.146939] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  298.146974] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  298.149166] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  298.149201] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  298.151429] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  298.151465] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  298.153683] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  298.153720] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  298.155974] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  298.156010] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  298.172909] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  298.172944] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  298.173909] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  298.173944] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  298.176194] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  298.176232] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  298.178456] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  298.178491] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  298.180544] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  298.180581] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  298.182808] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  298.182844] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  298.185035] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  298.185071] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  298.187300] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  298.187336] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  298.206233] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  298.206268] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  298.207647] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  298.207683] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  298.209906] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  298.209942] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  298.212225] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  298.212262] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  298.214422] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  298.214458] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  298.216517] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  298.216552] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  298.218781] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  298.218817] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  298.221013] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  298.221049] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  298.239574] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  298.239607] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  298.241172] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  298.241208] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  298.243435] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  298.243471] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  298.245683] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  298.245719] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  298.247943] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  298.247978] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  298.250190] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  298.250226] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  298.252336] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  298.252372] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  298.254597] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  298.254632] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  298.272912] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  298.272947] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  298.274759] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  298.274795] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  298.276983] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  298.277020] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  298.279245] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  298.279281] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  298.281489] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  298.281525] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  298.283754] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  298.283790] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  298.286013] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  298.286048] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  298.288296] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  298.288332] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  298.306259] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  298.306294] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  298.308345] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  298.308382] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  298.310612] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  298.310649] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  298.312698] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  298.312734] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  298.314964] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  298.315000] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  298.317202] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  298.317239] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  298.319465] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  298.319500] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  298.321724] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  298.321760] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  298.339516] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  298.339551] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  298.341714] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  298.341750] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  298.343972] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  298.344009] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  298.346233] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  298.346268] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  298.348373] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  298.348409] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  298.350630] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  298.350665] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  298.352714] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  298.352749] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  298.354982] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  298.355018] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  298.372946] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  298.372981] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  298.375204] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  298.375240] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  298.377426] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  298.377463] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  298.379686] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  298.379723] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  298.381947] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  298.381984] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  298.384234] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  298.384269] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  298.386492] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  298.386528] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  298.388578] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  298.388614] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  298.406268] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  298.406303] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  298.406484] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  298.406518] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  298.408601] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  298.408636] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  298.410866] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  298.410902] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  298.413101] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  298.413137] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  298.415358] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  298.415393] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  298.417609] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  298.417646] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  298.419871] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  298.419906] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  298.422140] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  298.422176] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  298.439598] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  298.439632] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  298.439885] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  298.439919] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  298.442170] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  298.442206] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  298.444354] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  298.444390] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  298.446610] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  298.446647] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  298.448697] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  298.448734] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  298.450963] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  298.451000] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  298.453211] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  298.453247] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  298.455461] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  298.455497] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  298.472935] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  298.472969] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  298.473521] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  298.473556] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  298.475786] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  298.475821] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  298.478050] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  298.478086] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  298.480315] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  298.480351] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  298.482573] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  298.482609] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  298.484661] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  298.484697] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  298.486925] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  298.486960] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  298.489152] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  298.489188] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  298.506229] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  298.506264] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  298.507233] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  298.507269] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  298.509485] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  298.509521] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  298.511744] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  298.511781] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  298.514011] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  298.514048] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  298.516301] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  298.516338] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  298.518562] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  298.518597] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  298.520775] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  298.520811] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  298.539580] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  298.539614] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  298.540820] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  298.540856] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  298.543083] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  298.543118] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  298.545327] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  298.545363] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  298.547588] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  298.547626] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  298.549843] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  298.549879] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  298.552139] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  298.552180] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  298.554366] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  298.554402] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  298.572885] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  298.572919] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  298.574591] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  298.574627] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  298.576682] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  298.576718] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  298.578945] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  298.578981] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  298.581178] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  298.581214] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  298.583438] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  298.583474] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  298.585698] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  298.585733] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  298.587959] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  298.587995] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  298.606126] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  298.606160] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  298.608212] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  298.608249] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  298.610473] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  298.610510] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  298.612555] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  298.612590] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  298.614830] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  298.614867] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  298.617061] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  298.617098] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  298.619321] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  298.619357] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  298.621575] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  298.621611] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  298.639491] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  298.639525] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  298.641690] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  298.641727] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  298.643953] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  298.643989] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  298.646213] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  298.646249] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  298.648363] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  298.648400] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  298.650623] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  298.650659] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  298.652708] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  298.652744] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  298.654971] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  298.655008] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  298.672945] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  298.672980] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  298.675196] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  298.675231] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  298.677439] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  298.677475] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  298.679700] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  298.679736] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  298.681946] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  298.681982] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  298.684230] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  298.684267] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  298.686491] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  298.686527] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  298.688580] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  298.688616] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  298.706271] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  298.706307] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  298.708436] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  298.708472] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  298.710686] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  298.710723] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  298.712901] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  298.712937] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  298.715172] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  298.715208] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  298.717420] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  298.717456] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  298.719682] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  298.719719] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  298.721942] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  298.721978] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  298.739599] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  298.739633] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  298.739859] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  298.739892] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  298.742151] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  298.742187] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  298.744353] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  298.744390] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  298.746610] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  298.746645] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  298.748697] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  298.748734] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  298.750966] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  298.751002] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  298.753202] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  298.753238] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  298.755464] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  298.755500] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  298.772922] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  298.772957] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  298.773487] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  298.773524] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  298.775758] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  298.775794] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  298.778013] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  298.778050] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  298.780297] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  298.780333] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  298.782543] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  298.782579] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  298.784629] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  298.784664] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  298.786894] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  298.786930] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  298.789121] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  298.789158] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  298.806249] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  298.806284] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  298.807050] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  298.807086] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  298.809291] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  298.809328] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  298.811529] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  298.811566] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  298.813787] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  298.813823] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  298.816089] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  298.816131] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  298.818318] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  298.818353] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  298.820380] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  298.820418] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  298.822687] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  298.822722] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  298.839572] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  298.839606] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  298.840527] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  298.840561] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  298.842817] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  298.842854] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  298.845047] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  298.845082] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  298.847308] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  298.847344] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  298.849552] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  298.849588] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  298.851814] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  298.851849] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  298.854078] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  298.854115] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  298.872898] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  298.872932] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  298.874325] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  298.874361] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  298.876395] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  298.876433] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  298.878683] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  298.878718] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  298.880808] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  298.880843] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  298.883068] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  298.883103] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  298.885310] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  298.885345] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  298.887570] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  298.887605] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  298.906229] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  298.906263] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  298.907640] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  298.907676] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  298.909882] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  298.909917] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  298.912160] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  298.912196] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  298.914437] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  298.914472] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  298.916532] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  298.916568] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  298.918799] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  298.918835] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  298.921028] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  298.921064] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  298.939540] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  298.939575] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  298.941224] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  298.941261] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  298.943488] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  298.943524] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  298.945746] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  298.945782] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  298.948005] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  298.948081] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  298.950270] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  298.950306] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  298.952394] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  298.952430] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  298.954664] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  298.954699] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  298.972789] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  298.972826] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  298.974970] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  298.975006] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  298.977211] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  298.977247] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  298.979476] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  298.979512] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  298.981738] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  298.981775] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  298.984001] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  298.984077] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  298.986262] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  298.986297] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  298.988393] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  298.988430] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  299.006263] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  299.006298] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  299.008396] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  299.008432] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  299.010670] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  299.010706] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  299.012894] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  299.012930] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  299.015158] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  299.015194] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  299.017403] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  299.017439] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  299.019662] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  299.019696] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  299.021934] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  299.021971] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  299.039595] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  299.039630] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  299.041833] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  299.041869] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  299.044127] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  299.044168] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  299.046356] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  299.046393] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  299.048451] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  299.048486] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  299.050723] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  299.050759] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  299.052940] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  299.052977] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  299.055203] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  299.055240] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  299.072922] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  299.072956] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  299.073149] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  299.073183] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  299.075435] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  299.075471] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  299.077689] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  299.077725] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  299.079951] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  299.079986] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  299.082111] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  299.082147] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  299.084369] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  299.084412] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  299.086618] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  299.086654] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  299.088705] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  299.088741] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  299.106253] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  299.106288] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  299.106384] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  299.106409] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  299.108568] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  299.108604] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  299.110833] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  299.110869] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  299.113065] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  299.113102] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  299.115326] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  299.115361] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  299.117556] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  299.117592] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  299.119816] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  299.119853] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  299.122078] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  299.122115] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  299.139573] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  299.139608] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  299.140069] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  299.140109] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  299.142322] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  299.142357] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  299.144444] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  299.144480] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  299.146696] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  299.146732] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  299.148910] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  299.148946] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  299.151174] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  299.151211] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  299.153420] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  299.153457] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  299.155684] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  299.155721] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  299.172896] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  299.172930] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  299.173772] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  299.173808] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  299.176078] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  299.176120] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  299.178300] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  299.178337] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  299.180423] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  299.180459] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  299.182514] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  299.182550] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  299.184642] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  299.184677] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  299.186909] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  299.186944] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  299.189141] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  299.189177] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  299.206228] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  299.206263] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  299.207227] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  299.207262] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  299.209475] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  299.209510] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  299.211738] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  299.211774] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  299.214000] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  299.214035] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  299.216291] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  299.216336] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  299.218539] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  299.218575] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  299.220682] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  299.220717] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  299.228287] [drm:edp_panel_vdd_off_sync [i915]] Turning eDP port A VDD off
>[  299.228431] [drm:edp_panel_vdd_off_sync [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x00000067
>[  299.239571] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  299.239605] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  299.240713] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  299.240749] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  299.242975] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  299.243011] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  299.245213] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  299.245249] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  299.247482] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  299.247518] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  299.249733] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  299.249769] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  299.251995] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  299.252072] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  299.254260] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  299.254296] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  299.272910] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  299.272944] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  299.274488] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  299.274524] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  299.276610] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  299.276645] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  299.278876] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  299.278911] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  299.281110] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  299.281146] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  299.283319] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  299.283355] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  299.285564] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  299.285599] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  299.287829] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  299.287865] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  299.306210] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  299.306245] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  299.308122] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  299.308160] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  299.310213] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  299.310248] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  299.312345] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  299.312382] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  299.314613] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  299.314648] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  299.316814] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  299.316850] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  299.319081] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  299.319117] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  299.321310] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  299.321347] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  299.339539] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  299.339574] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  299.341295] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  299.341331] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  299.343557] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  299.343593] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  299.345814] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  299.345851] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  299.348112] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  299.348156] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  299.350335] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  299.350371] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  299.352464] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  299.352500] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  299.354734] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  299.354770] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  299.372872] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  299.372907] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  299.375091] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  299.375127] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  299.377333] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  299.377369] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  299.379596] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  299.379632] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  299.381857] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  299.381894] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  299.384126] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  299.384166] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  299.386358] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  299.386393] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  299.388471] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  299.388507] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  299.406246] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  299.406281] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  299.408466] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  299.408502] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  299.410729] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  299.410765] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  299.412945] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  299.412982] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  299.415204] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  299.415241] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  299.417453] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  299.417489] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  299.419715] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  299.419750] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  299.421976] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  299.422012] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  299.439573] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  299.439607] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  299.439865] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  299.439889] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  299.442186] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  299.442222] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  299.444362] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  299.444404] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  299.446609] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  299.446645] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  299.448809] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  299.448845] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  299.451080] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  299.451116] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  299.453319] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  299.453355] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  299.455588] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  299.455624] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  299.472907] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  299.472942] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  299.473658] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  299.473694] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  299.475926] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  299.475962] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  299.478189] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  299.478225] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  299.480375] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  299.480419] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  299.482620] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  299.482655] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  299.484820] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  299.484856] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  299.487087] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  299.487124] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  299.489336] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  299.489371] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  299.506216] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  299.506251] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  299.507421] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  299.507457] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  299.509676] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  299.509712] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  299.511937] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  299.511972] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  299.514202] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  299.514238] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  299.516369] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  299.516416] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  299.518620] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  299.518655] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  299.520840] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  299.520876] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  299.539553] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  299.539588] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  299.540830] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  299.540866] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  299.543091] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  299.543128] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  299.545336] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  299.545372] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  299.547600] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  299.547636] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  299.549851] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  299.549887] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  299.552143] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  299.552183] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  299.554375] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  299.554411] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  299.572858] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  299.572892] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  299.574631] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  299.574667] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  299.576841] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  299.576877] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  299.579101] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  299.579137] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  299.581349] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  299.581384] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  299.583612] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  299.583648] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  299.585873] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  299.585909] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  299.588157] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  299.588201] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  299.606154] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  299.606188] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  299.608360] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  299.608401] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  299.610606] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  299.610642] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  299.612808] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  299.612844] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  299.615075] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  299.615111] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  299.617320] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  299.617356] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  299.619577] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  299.619613] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  299.621834] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  299.621869] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  299.639575] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  299.639613] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  299.639691] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  299.639716] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  299.641947] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  299.641982] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  299.644245] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  299.644287] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  299.646484] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  299.646520] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  299.648620] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  299.648655] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  299.650886] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  299.650922] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  299.653116] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  299.653152] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  299.655375] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  299.655411] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  299.672915] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  299.672951] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  299.673201] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  299.673234] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  299.675491] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  299.675527] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  299.677735] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  299.677771] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  299.680000] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  299.680078] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  299.682261] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  299.682297] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  299.684387] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  299.684424] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  299.686650] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  299.686686] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  299.688851] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  299.688886] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  299.706228] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  299.706262] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  299.706901] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  299.706936] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  299.709137] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  299.709173] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  299.711396] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  299.711432] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  299.713650] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  299.713686] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  299.715912] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  299.715948] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  299.718168] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  299.718204] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  299.720368] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  299.720415] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  299.722629] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  299.722665] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  299.739563] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  299.739598] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  299.740361] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  299.740395] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  299.742652] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  299.742687] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  299.744822] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  299.744859] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  299.747093] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  299.747128] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  299.749336] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  299.749371] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  299.751600] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  299.751636] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  299.753857] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  299.753892] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  299.772886] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  299.772920] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  299.774255] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  299.774291] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  299.776388] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  299.776424] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  299.778649] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  299.778684] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  299.780864] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  299.780901] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  299.783125] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  299.783161] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  299.785372] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  299.785408] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  299.787637] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  299.787673] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  299.806190] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  299.806225] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  299.807899] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  299.807935] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  299.810162] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  299.810198] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  299.812360] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  299.812409] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  299.814612] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  299.814648] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  299.816819] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  299.816855] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  299.819085] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  299.819121] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  299.821335] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  299.821370] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  299.839440] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  299.839474] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  299.841540] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  299.841577] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  299.843802] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  299.843838] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  299.846060] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  299.846096] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  299.848364] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  299.848401] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  299.850600] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  299.850635] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  299.852806] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  299.852843] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  299.855072] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  299.855107] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  299.872908] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  299.872946] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  299.873023] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  299.873047] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  299.875278] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  299.875314] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  299.877520] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  299.877556] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  299.879783] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  299.879818] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  299.882046] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  299.882082] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  299.884337] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  299.884381] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  299.886587] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  299.886622] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  299.888788] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  299.888824] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  299.906233] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  299.906267] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  299.906823] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  299.906859] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  299.909053] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  299.909089] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  299.911314] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  299.911350] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  299.913457] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  299.913492] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  299.915717] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  299.915753] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  299.917976] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  299.918013] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  299.920267] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  299.920316] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  299.922512] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  299.922551] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  299.939569] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  299.939603] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  299.940296] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  299.940330] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  299.942583] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  299.942618] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  299.944726] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  299.944761] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  299.946988] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  299.947025] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  299.949223] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  299.949259] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  299.951488] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  299.951523] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  299.953741] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  299.953777] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  299.956002] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  299.956073] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  299.972874] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  299.972909] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  299.973931] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  299.973967] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  299.976223] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  299.976269] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  299.978469] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  299.978505] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  299.980590] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  299.980627] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  299.982861] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  299.982897] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  299.984985] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  299.985021] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  299.987255] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  299.987290] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  300.006213] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  300.006248] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  300.007520] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  300.007556] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  300.009773] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  300.009808] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  300.012082] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  300.012124] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  300.014303] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  300.014339] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  300.016396] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  300.016433] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  300.018695] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  300.018730] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  300.020923] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  300.020959] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  300.039536] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  300.039571] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  300.040943] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  300.040979] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  300.043213] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  300.043249] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  300.045457] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  300.045493] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  300.047722] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  300.047757] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  300.049981] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  300.050017] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  300.052276] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  300.052320] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  300.054522] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  300.054557] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  300.072766] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  300.072801] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  300.074850] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  300.074885] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  300.077083] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  300.077119] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  300.079344] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  300.079381] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  300.081580] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  300.081615] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  300.083838] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  300.083874] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  300.086075] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  300.086112] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  300.088397] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  300.088444] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  300.106240] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  300.106274] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  300.108353] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  300.108401] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  300.110605] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  300.110640] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  300.112805] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  300.112841] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  300.115066] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  300.115103] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  300.117312] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  300.117347] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  300.119573] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  300.119609] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  300.121831] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  300.121867] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  300.139575] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  300.139610] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  300.141800] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  300.141835] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  300.144101] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  300.144142] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  300.146330] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  300.146365] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  300.148457] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  300.148492] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  300.150725] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  300.150761] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  300.152943] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  300.152979] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  300.155205] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  300.155240] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  300.172850] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  300.172884] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  300.173070] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  300.173103] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  300.175358] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  300.175393] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  300.177606] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  300.177642] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  300.179870] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  300.179905] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  300.182139] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  300.182175] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  300.184369] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  300.184412] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  300.186584] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  300.186620] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  300.188795] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  300.188832] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  300.206234] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  300.206269] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  300.206818] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  300.206854] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  300.209048] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  300.209084] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  300.211312] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  300.211348] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  300.213565] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  300.213601] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  300.215830] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  300.215866] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  300.218096] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  300.218133] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  300.220363] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  300.220407] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  300.222627] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  300.222662] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  300.239557] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  300.239592] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  300.240492] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  300.240525] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  300.242779] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  300.242814] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  300.245008] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  300.245044] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  300.247275] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  300.247310] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  300.249524] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  300.249560] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  300.251790] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  300.251825] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  300.254053] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  300.254089] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  300.272868] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  300.272903] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  300.274317] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  300.274353] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  300.276447] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  300.276483] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  300.278712] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  300.278747] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  300.280918] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  300.280954] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  300.283184] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  300.283219] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  300.285404] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  300.285441] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  300.287661] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  300.287696] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  300.306226] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  300.306260] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  300.307659] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  300.307695] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  300.309798] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  300.309834] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  300.312105] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  300.312155] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  300.314320] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  300.314356] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  300.316413] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  300.316450] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  300.318709] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  300.318744] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  300.320832] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  300.320869] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  300.339540] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  300.339574] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  300.340812] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  300.340848] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  300.343076] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  300.343112] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  300.345170] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  300.345203] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  300.347453] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  300.347489] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  300.349704] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  300.349740] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  300.351967] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  300.352003] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  300.354229] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  300.354266] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  300.372863] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  300.372897] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  300.374265] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  300.374300] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  300.376406] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  300.376442] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  300.378667] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  300.378703] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  300.380887] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  300.380923] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  300.383152] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  300.383188] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  300.385397] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  300.385432] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  300.387643] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  300.387678] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  300.406172] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  300.406206] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  300.407983] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  300.408055] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  300.410244] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  300.410280] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  300.412397] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  300.412437] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  300.414648] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  300.414684] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  300.416864] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  300.416901] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  300.419129] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  300.419166] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  300.421373] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  300.421409] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  300.439431] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  300.439465] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  300.441527] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  300.441562] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  300.443789] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  300.443826] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  300.446055] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  300.446092] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  300.448357] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  300.448401] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  300.450601] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  300.450636] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  300.452804] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  300.452840] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  300.455068] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  300.455103] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  300.472894] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  300.472930] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  300.473006] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  300.473032] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  300.475307] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  300.475344] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  300.477552] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  300.477588] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  300.479809] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  300.479844] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  300.482073] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  300.482108] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  300.484374] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  300.484414] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  300.486611] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  300.486647] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  300.488829] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  300.488866] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  300.506223] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  300.506257] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  300.506898] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  300.506933] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  300.509126] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  300.509162] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  300.511387] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  300.511423] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  300.513640] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  300.513676] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  300.515903] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  300.515939] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  300.518163] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  300.518200] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  300.520364] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  300.520408] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  300.522623] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  300.522658] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  300.539546] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  300.539581] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  300.540552] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  300.540589] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  300.542818] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  300.542855] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  300.545052] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  300.545089] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  300.547313] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  300.547349] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  300.549564] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  300.549600] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  300.551825] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  300.551860] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  300.553964] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  300.553999] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  300.572872] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  300.572905] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  300.574301] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  300.574337] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  300.576401] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  300.576438] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  300.578696] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  300.578732] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  300.580911] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  300.580946] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  300.583175] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  300.583211] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  300.585425] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  300.585461] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  300.587651] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  300.587686] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  300.606176] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  300.606210] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  300.607919] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  300.607955] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  300.610178] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  300.610215] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  300.612359] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  300.612405] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  300.614613] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  300.614649] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  300.616822] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  300.616858] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  300.619086] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  300.619122] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  300.621331] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  300.621368] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  300.639428] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  300.639463] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  300.641591] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  300.641627] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  300.643855] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  300.643890] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  300.646118] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  300.646154] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  300.648365] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  300.648410] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  300.650619] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  300.650654] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  300.652823] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  300.652859] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  300.655088] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  300.655124] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  300.672890] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  300.672926] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  300.673006] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  300.673032] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  300.675356] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  300.675392] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  300.677601] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  300.677637] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  300.679867] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  300.679903] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  300.682002] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  300.682037] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  300.684296] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  300.684340] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  300.686543] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  300.686580] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  300.688688] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  300.688723] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  300.706218] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  300.706252] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  300.706709] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  300.706744] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  300.708931] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  300.708966] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  300.711196] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  300.711232] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  300.713448] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  300.713484] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  300.715708] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  300.715744] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  300.717969] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  300.718005] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  300.720263] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  300.720313] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  300.722517] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  300.722558] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  300.739543] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  300.739579] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  300.740309] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  300.740343] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  300.742600] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  300.742636] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  300.744751] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  300.744787] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  300.747008] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  300.747043] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  300.749252] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  300.749287] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  300.751518] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  300.751554] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  300.753773] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  300.753808] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  300.772862] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  300.772896] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  300.774164] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  300.774200] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  300.776360] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  300.776405] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  300.778607] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  300.778643] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  300.780816] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  300.780852] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  300.783082] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  300.783117] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  300.785327] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  300.785363] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  300.787591] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  300.787626] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  300.806179] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  300.806213] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  300.807849] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  300.807884] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  300.809981] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  300.810018] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  300.812271] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  300.812318] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  300.814522] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  300.814559] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  300.816646] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  300.816685] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  300.818913] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  300.818949] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  300.821158] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  300.821195] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  300.839510] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  300.839544] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  300.841165] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  300.841199] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  300.843447] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  300.843483] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  300.845699] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  300.845735] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  300.847959] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  300.847995] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  300.850216] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  300.850253] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  300.852371] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  300.852412] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  300.854616] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  300.854652] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  300.872834] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  300.872869] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  300.874610] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  300.874647] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  300.876744] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  300.876779] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  300.879013] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  300.879049] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  300.881254] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  300.881291] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  300.883518] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  300.883553] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  300.885779] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  300.885815] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  300.887965] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  300.888001] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  300.906086] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  300.906120] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  300.908234] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  300.908281] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  300.910481] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  300.910517] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  300.912605] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  300.912641] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  300.914872] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  300.914908] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  300.917107] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  300.917143] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  300.919380] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  300.919416] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  300.921630] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  300.921667] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  300.939451] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  300.939486] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  300.941096] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  300.941133] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  300.943254] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  300.943290] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  300.945418] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  300.945453] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  300.947578] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  300.947614] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  300.949741] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  300.949778] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  300.951898] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  300.951934] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  300.954061] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  300.954097] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  300.972781] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  300.972815] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  300.973446] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  300.973482] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  300.975599] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  300.975635] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  300.977761] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  300.977797] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  300.979925] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  300.979960] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  300.982091] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  300.982127] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  300.984249] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  300.984292] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  300.986395] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  300.986431] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  300.988521] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  300.988558] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  301.006100] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  301.006135] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  301.007946] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  301.007982] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  301.010109] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  301.010145] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  301.012261] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  301.012303] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  301.014404] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  301.014440] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  301.016527] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  301.016563] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  301.018682] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  301.018718] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  301.020775] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  301.020808] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  301.039456] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  301.039491] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  301.040092] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  301.040130] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  301.042240] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  301.042276] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  301.044337] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  301.044373] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  301.046499] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  301.046535] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  301.048641] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  301.048676] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  301.050794] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  301.050830] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  301.052893] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  301.052926] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  301.055067] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  301.055103] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  301.072775] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  301.072809] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  301.074468] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  301.074504] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  301.076593] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  301.076628] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  301.078757] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  301.078793] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  301.080920] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  301.080955] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  301.083075] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  301.083110] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  301.085240] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  301.085276] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  301.087397] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  301.087432] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  301.106112] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  301.106148] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  301.106716] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  301.106751] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  301.108878] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  301.108915] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  301.111032] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  301.111068] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  301.113194] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  301.113229] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  301.115351] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  301.115386] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  301.117517] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  301.117553] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  301.119674] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  301.119710] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  301.121836] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  301.121872] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  301.139436] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  301.139470] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  301.141238] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  301.141275] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  301.143352] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  301.143387] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  301.145518] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  301.145555] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  301.147675] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  301.147710] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  301.149843] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  301.149879] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  301.152000] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  301.152077] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  301.154165] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  301.154201] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  301.172783] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  301.172816] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  301.173554] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  301.173590] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  301.175708] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  301.175744] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  301.177865] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  301.177902] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  301.180062] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  301.180105] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  301.182184] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  301.182220] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  301.184279] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  301.184316] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  301.186471] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  301.186507] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  301.188618] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  301.188654] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  301.206102] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  301.206137] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  301.208059] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  301.208102] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  301.210181] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  301.210218] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  301.212279] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  301.212315] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  301.214468] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  301.214503] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  301.216615] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  301.216652] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  301.218766] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  301.218802] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  301.220925] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  301.220961] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  301.239393] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  301.239426] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  301.240241] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  301.240276] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  301.242450] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  301.242486] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  301.244593] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  301.244628] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  301.246747] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  301.246783] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  301.248909] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  301.248946] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  301.251070] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  301.251107] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  301.253230] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  301.253266] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  301.255385] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  301.255421] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  301.272750] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  301.272783] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  301.274819] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  301.274855] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  301.276991] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  301.277026] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  301.279147] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  301.279182] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  301.281310] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  301.281346] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  301.283465] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  301.283501] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  301.285630] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  301.285666] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  301.287789] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  301.287826] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  301.306108] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  301.306142] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  301.307163] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  301.307198] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  301.309326] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  301.309361] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  301.311482] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  301.311518] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  301.313642] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  301.313678] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  301.315801] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  301.315837] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  301.317968] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  301.318004] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  301.320161] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  301.320196] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  301.322301] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  301.322337] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  301.339488] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  301.339523] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  301.341638] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  301.341674] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  301.343794] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  301.343830] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  301.345961] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  301.345996] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  301.348156] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  301.348202] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  301.350271] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  301.350308] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  301.352366] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  301.352403] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  301.354561] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  301.354596] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  301.372786] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  301.372821] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  301.373964] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  301.373999] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  301.376152] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  301.376192] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  301.378303] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  301.378339] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  301.380421] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  301.380457] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  301.382583] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  301.382620] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  301.384743] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  301.384780] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  301.386902] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  301.386938] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  301.389065] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  301.389101] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  301.406109] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  301.406144] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  301.406229] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  301.406254] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  301.408398] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  301.408434] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  301.410564] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  301.410600] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  301.412724] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  301.412760] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  301.414883] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  301.414919] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  301.417040] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  301.417076] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  301.419196] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  301.419231] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  301.421365] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  301.421401] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  301.439442] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  301.439477] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  301.440786] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  301.440822] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  301.442952] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  301.442988] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  301.445117] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  301.445153] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  301.447273] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  301.447309] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  301.449408] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  301.449444] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  301.451566] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  301.451602] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  301.453730] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  301.453766] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  301.455916] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  301.455952] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  301.472777] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  301.472812] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  301.473110] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  301.473145] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  301.475291] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  301.475327] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  301.477454] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  301.477490] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  301.479608] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  301.479644] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  301.481773] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  301.481809] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  301.483931] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  301.483967] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  301.486092] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  301.486128] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  301.488260] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  301.488305] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  301.506105] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  301.506139] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  301.507625] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  301.507660] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  301.509791] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  301.509826] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  301.511950] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  301.511985] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  301.514106] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  301.514141] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  301.516263] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  301.516306] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  301.518408] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  301.518444] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  301.520530] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  301.520566] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  301.539438] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  301.539472] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  301.539919] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  301.539966] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  301.542119] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  301.542155] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  301.544269] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  301.544312] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  301.546413] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  301.546449] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  301.548539] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  301.548575] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  301.550694] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  301.550731] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  301.552845] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  301.552881] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  301.555000] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  301.555036] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  301.572766] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  301.572801] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  301.574415] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  301.574450] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  301.576540] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  301.576576] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  301.578702] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  301.578737] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  301.580842] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  301.580878] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  301.582996] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  301.583032] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  301.585159] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  301.585196] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  301.587318] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  301.587354] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  301.606101] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  301.606135] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  301.606717] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  301.606753] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  301.608882] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  301.608918] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  301.611039] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  301.611075] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  301.613205] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  301.613240] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  301.615361] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  301.615397] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  301.617527] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  301.617563] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  301.619686] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  301.619722] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  301.621847] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  301.621883] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  301.639433] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  301.639467] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  301.641278] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  301.641313] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  301.643435] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  301.643470] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  301.645597] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  301.645634] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  301.647757] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  301.647793] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  301.649922] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  301.649958] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  301.652120] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  301.652160] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  301.654245] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  301.654281] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  301.672776] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  301.672809] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  301.673629] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  301.673664] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  301.675789] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  301.675824] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  301.677954] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  301.677989] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  301.680141] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  301.680180] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  301.682270] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  301.682306] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  301.684389] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  301.684425] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  301.686555] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  301.686591] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  301.688712] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  301.688749] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  301.706078] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  301.706112] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  301.708159] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  301.708198] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  301.710320] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  301.710356] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  301.712445] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  301.712480] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  301.714605] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  301.714641] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  301.716763] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  301.716798] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  301.718928] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  301.718964] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  301.721097] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  301.721133] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  301.739436] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  301.739470] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  301.740467] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  301.740515] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  301.742634] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  301.742670] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  301.744798] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  301.744834] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  301.746959] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  301.746994] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  301.749117] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  301.749153] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  301.751274] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  301.751309] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  301.753446] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  301.753482] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  301.755598] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  301.755633] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  301.772769] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  301.772803] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  301.774984] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  301.775019] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  301.777148] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  301.777183] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  301.779303] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  301.779339] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  301.781467] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  301.781503] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  301.783623] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  301.783658] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  301.785788] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  301.785824] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  301.787944] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  301.787980] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  301.806100] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  301.806135] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  301.808339] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  301.808385] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  301.810581] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  301.810617] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  301.812802] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  301.812839] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  301.815068] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  301.815104] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  301.817312] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  301.817348] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  301.819575] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  301.819610] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  301.821834] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  301.821871] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  301.839539] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  301.839574] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  301.839655] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  301.839680] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  301.841948] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  301.841985] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  301.844232] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  301.844268] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  301.846491] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  301.846526] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  301.848618] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  301.848655] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  301.850887] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  301.850922] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  301.853121] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  301.853156] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  301.855379] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  301.855415] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  301.872827] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  301.872862] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  301.873350] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  301.873386] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  301.875619] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  301.875656] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  301.877878] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  301.877914] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  301.880198] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  301.880235] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  301.882453] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  301.882488] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  301.884578] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  301.884614] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  301.886845] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  301.886881] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  301.889079] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  301.889114] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  301.906185] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  301.906219] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  301.907134] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  301.907169] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  301.909378] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  301.909416] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  301.911644] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  301.911679] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  301.913895] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  301.913932] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  301.916159] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  301.916198] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  301.918429] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  301.918465] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  301.920555] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  301.920591] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  301.939513] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  301.939547] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  301.940800] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  301.940836] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  301.943055] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  301.943090] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  301.945298] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  301.945334] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  301.947564] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  301.947600] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  301.949821] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  301.949858] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  301.952123] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  301.952165] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  301.954347] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  301.954383] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  301.972808] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  301.972843] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  301.974606] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  301.974642] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  301.976749] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  301.976784] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  301.979012] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  301.979047] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  301.981254] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  301.981290] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  301.983516] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  301.983551] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  301.985775] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  301.985811] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  301.988077] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  301.988119] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  302.006074] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  302.006108] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  302.008296] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  302.008332] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  302.010562] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  302.010598] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  302.012704] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  302.012740] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  302.014968] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  302.015004] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  302.017211] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  302.017247] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  302.019473] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  302.019509] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  302.021733] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  302.021769] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  302.039534] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  302.039568] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  302.041588] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  302.041623] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  302.043876] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  302.043912] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  302.046141] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  302.046177] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  302.048343] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  302.048380] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  302.050615] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  302.050651] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  302.052828] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  302.052864] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  302.055092] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  302.055128] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  302.072874] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  302.072908] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  302.073025] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  302.073051] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  302.075361] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  302.075396] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  302.077614] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  302.077650] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  302.079871] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  302.079906] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  302.082127] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  302.082163] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  302.084344] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  302.084380] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  302.086611] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  302.086647] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  302.088818] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  302.088854] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  302.106189] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  302.106224] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  302.106898] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  302.106934] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  302.109127] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  302.109164] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  302.111390] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  302.111425] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  302.113645] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  302.113681] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  302.115907] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  302.115944] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  302.118174] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  302.118210] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  302.120348] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  302.120384] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  302.122615] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  302.122651] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  302.139512] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  302.139548] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  302.140565] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  302.140602] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  302.142800] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  302.142836] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  302.145027] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  302.145063] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  302.147291] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  302.147327] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  302.149541] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  302.149576] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  302.151806] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  302.151842] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  302.154072] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  302.154108] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  302.172838] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  302.172872] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  302.174329] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  302.174365] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  302.176451] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  302.176486] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  302.178721] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  302.178758] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  302.180937] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  302.180973] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  302.183162] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  302.183197] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  302.185407] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  302.185443] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  302.187673] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  302.187708] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  302.206145] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  302.206180] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  302.207969] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  302.208005] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  302.210234] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  302.210270] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  302.212372] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  302.212408] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  302.214637] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  302.214673] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  302.216850] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  302.216886] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  302.219105] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  302.219141] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  302.221357] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  302.221393] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  302.239499] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  302.239535] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  302.241700] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  302.241736] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  302.243955] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  302.243990] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  302.246222] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  302.246258] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  302.248348] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  302.248384] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  302.250616] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  302.250652] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  302.252825] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  302.252861] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  302.255088] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  302.255124] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  302.272858] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  302.272893] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  302.272994] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  302.273018] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  302.275346] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  302.275383] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  302.277591] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  302.277627] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  302.279858] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  302.279895] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  302.282125] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  302.282161] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  302.284344] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  302.284380] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  302.286609] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  302.286646] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  302.288818] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  302.288853] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  302.306184] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  302.306220] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  302.306869] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  302.306904] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  302.309102] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  302.309138] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  302.311369] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  302.311405] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  302.313621] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  302.313656] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  302.315884] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  302.315921] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  302.318148] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  302.318183] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  302.320355] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  302.320391] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  302.322621] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  302.322656] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  302.339504] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  302.339539] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  302.340531] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  302.340565] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  302.342719] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  302.342766] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  302.344952] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  302.344988] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  302.347215] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  302.347251] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  302.349469] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  302.349505] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  302.351737] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  302.351774] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  302.353997] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  302.354033] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  302.372809] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  302.372843] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  302.374172] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  302.374207] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  302.376342] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  302.376378] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  302.378609] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  302.378645] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  302.380758] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  302.380794] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  302.383018] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  302.383053] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  302.385248] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  302.385283] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  302.387512] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  302.387548] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  302.406153] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  302.406187] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  302.407760] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  302.407796] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  302.410029] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  302.410064] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  302.412297] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  302.412333] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  302.414562] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  302.414598] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  302.416707] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  302.416743] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  302.418970] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  302.419005] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  302.421206] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  302.421242] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  302.439396] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  302.439429] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  302.441537] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  302.441574] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  302.443746] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  302.443783] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  302.446014] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  302.446050] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  302.448284] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  302.448321] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  302.450552] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  302.450587] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  302.452703] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  302.452739] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  302.454970] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  302.455006] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  302.472876] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  302.472912] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  302.475205] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  302.475240] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  302.477452] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  302.477488] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  302.479716] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  302.479752] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  302.481975] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  302.482010] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  302.484248] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  302.484284] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  302.486518] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  302.486553] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  302.488643] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  302.488679] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  302.506192] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  302.506228] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  302.506666] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  302.506702] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  302.508802] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  302.508837] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  302.511062] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  302.511098] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  302.513305] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  302.513341] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  302.515565] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  302.515601] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  302.517828] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  302.517864] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  302.520125] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  302.520164] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  302.522350] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  302.522386] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  302.539525] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  302.539559] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  302.540185] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  302.540220] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  302.542466] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  302.542502] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  302.544595] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  302.544631] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  302.546863] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  302.546899] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  302.549080] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  302.549116] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  302.551344] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  302.551379] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  302.553597] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  302.553633] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  302.555869] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  302.555905] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  302.572841] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  302.572875] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  302.573967] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  302.574003] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  302.576242] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  302.576278] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  302.578508] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  302.578543] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  302.580647] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  302.580683] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  302.582916] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  302.582952] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  302.585147] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  302.585183] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  302.587417] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  302.587452] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  302.606158] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  302.606193] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  302.607616] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  302.607652] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  302.609825] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  302.609861] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  302.612124] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  302.612165] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  302.614349] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  302.614385] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  302.616465] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  302.616499] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  302.618734] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  302.618769] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  302.620946] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  302.620981] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  302.639469] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  302.639504] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  302.641161] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  302.641196] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  302.643428] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  302.643463] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  302.645684] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  302.645719] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  302.647949] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  302.647983] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  302.650217] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  302.650252] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  302.652349] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  302.652386] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  302.654611] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  302.654646] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  302.672772] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  302.672806] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  302.674954] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  302.674988] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  302.677194] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  302.677229] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  302.679459] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  302.679494] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  302.681713] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  302.681748] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  302.683978] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  302.684051] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  302.686243] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  302.686278] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  302.688380] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  302.688416] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  302.706212] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  302.706245] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  302.708344] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  302.708380] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  302.710621] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  302.710656] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  302.712746] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  302.712783] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  302.715012] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  302.715047] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  302.717254] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  302.717290] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  302.719522] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  302.719558] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  302.721785] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  302.721821] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  302.739535] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  302.739568] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  302.739646] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  302.739670] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  302.741852] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  302.741887] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  302.744157] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  302.744193] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  302.746421] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  302.746457] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  302.748546] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  302.748582] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  302.750815] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  302.750851] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  302.753043] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  302.753079] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  302.755306] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  302.755342] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  302.772853] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  302.772889] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  302.773100] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  302.773124] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  302.775414] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  302.775449] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  302.777666] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  302.777702] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  302.779932] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  302.779966] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  302.782176] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  302.782211] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  302.784348] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  302.784385] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  302.786618] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  302.786654] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  302.788830] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  302.788866] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  302.806187] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  302.806222] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  302.806438] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  302.806463] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  302.808694] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  302.808730] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  302.810958] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  302.810993] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  302.813200] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  302.813235] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  302.815471] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  302.815507] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  302.817731] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  302.817766] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  302.819997] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  302.820072] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  302.822259] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  302.822293] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  302.839518] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  302.839552] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  302.839961] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  302.839993] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  302.842245] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  302.842280] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  302.844397] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  302.844465] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  302.846645] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  302.846680] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  302.848860] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  302.848896] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  302.851121] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  302.851157] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  302.853340] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  302.853376] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  302.855604] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  302.855640] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  302.872840] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  302.872875] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  302.873623] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  302.873657] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  302.875890] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  302.875926] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  302.878154] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  302.878189] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  302.880353] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  302.880390] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  302.882616] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  302.882652] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  302.884831] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  302.884868] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  302.887096] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  302.887131] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  302.906164] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  302.906199] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  302.907289] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  302.907324] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  302.909537] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  302.909572] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  302.911805] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  302.911840] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  302.914069] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  302.914105] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  302.916353] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  302.916390] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  302.918616] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  302.918653] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  302.920828] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  302.920865] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  302.939482] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  302.939517] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  302.940937] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  302.940972] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  302.943202] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  302.943238] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  302.945429] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  302.945464] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  302.947694] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  302.947728] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  302.949956] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  302.949991] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  302.952280] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  302.952316] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  302.954545] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  302.954581] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  302.972808] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  302.972842] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  302.974583] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  302.974616] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  302.976724] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  302.976759] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  302.978990] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  302.979025] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  302.981238] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  302.981274] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  302.983503] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  302.983538] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  302.985719] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  302.985755] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  302.987991] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  302.988064] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  303.006024] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  303.006057] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  303.008215] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  303.008251] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  303.010481] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  303.010517] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  303.012604] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  303.012639] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  303.014868] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  303.014904] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  303.017107] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  303.017143] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  303.019368] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  303.019405] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  303.021624] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  303.021660] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  303.039538] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  303.039571] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  303.041786] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  303.041821] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  303.044091] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  303.044132] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  303.046296] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  303.046331] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  303.048388] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  303.048422] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  303.050656] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  303.050691] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  303.052874] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  303.052908] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  303.055145] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  303.055178] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  303.072853] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  303.072887] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  303.072997] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  303.073021] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  303.075309] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  303.075344] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  303.077560] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  303.077595] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  303.079825] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  303.079860] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  303.082090] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  303.082126] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  303.084354] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  303.084391] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  303.086615] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  303.086651] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  303.088816] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  303.088853] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  303.106180] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  303.106216] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  303.106778] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  303.106813] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  303.109010] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  303.109045] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  303.111275] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  303.111311] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  303.113412] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  303.113447] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  303.115678] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  303.115713] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  303.117941] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  303.117976] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  303.120260] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  303.120297] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  303.122540] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  303.122577] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  303.139493] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  303.139529] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  303.140295] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  303.140327] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  303.142588] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  303.142622] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  303.144737] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  303.144772] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  303.146989] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  303.147024] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  303.149229] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  303.149264] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  303.151494] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  303.151528] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  303.153754] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  303.153788] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  303.172825] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  303.172859] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  303.174160] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  303.174195] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  303.176352] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  303.176388] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  303.178612] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  303.178647] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  303.180821] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  303.180858] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  303.183085] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  303.183120] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  303.185332] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  303.185368] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  303.187600] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  303.187637] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  303.206138] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  303.206172] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  303.207838] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  303.207872] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  303.210090] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  303.210126] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  303.212350] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  303.212388] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  303.214619] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  303.214654] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  303.216832] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  303.216869] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  303.219096] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  303.219132] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  303.221342] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  303.221379] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  303.239483] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  303.239517] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  303.241543] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  303.241579] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  303.243807] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  303.243842] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  303.246068] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  303.246103] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  303.248359] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  303.248396] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  303.250621] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  303.250657] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  303.252824] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  303.252862] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  303.255089] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  303.255125] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  303.272844] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  303.272879] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  303.272983] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  303.273007] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  303.275299] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  303.275333] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  303.277551] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  303.277587] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  303.279816] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  303.279851] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  303.282074] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  303.282109] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  303.284351] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  303.284388] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  303.286625] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  303.286660] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  303.288835] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  303.288872] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  303.306169] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  303.306203] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  303.306774] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  303.306809] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  303.309007] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  303.309041] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  303.311272] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  303.311306] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  303.313515] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  303.313550] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  303.315783] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  303.315819] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  303.318049] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  303.318085] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  303.320354] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  303.320391] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  303.339489] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  303.339524] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  303.340557] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  303.340592] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  303.342826] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  303.342862] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  303.345063] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  303.345098] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  303.347293] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  303.347328] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  303.349547] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  303.349582] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  303.351812] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  303.351847] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  303.354080] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  303.354116] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  303.372785] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  303.372818] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  303.374125] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  303.374161] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  303.376352] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  303.376388] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  303.378615] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  303.378652] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  303.380828] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  303.380863] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  303.383096] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  303.383131] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  303.385343] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  303.385380] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  303.387606] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  303.387642] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  303.406112] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  303.406148] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  303.407906] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  303.407941] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  303.410180] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  303.410215] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  303.412358] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  303.412394] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  303.414614] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  303.414652] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  303.416831] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  303.416866] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  303.419093] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  303.419129] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  303.421340] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  303.421376] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  303.439446] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  303.439479] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  303.441623] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  303.441657] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  303.443889] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  303.443924] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  303.446159] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  303.446195] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  303.448341] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  303.448378] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  303.450605] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  303.450641] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  303.452807] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  303.452843] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  303.455072] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  303.455108] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  303.472851] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  303.472895] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  303.472979] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  303.473002] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  303.475252] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  303.475288] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  303.477491] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  303.477525] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  303.479757] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  303.479793] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  303.482019] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  303.482054] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  303.484333] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  303.484369] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  303.486607] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  303.486643] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  303.488814] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  303.488850] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  303.506173] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  303.506207] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  303.506764] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  303.506799] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  303.508995] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  303.509031] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  303.511261] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  303.511296] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  303.513506] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  303.513542] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  303.515770] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  303.515804] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  303.518033] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  303.518068] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  303.520353] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  303.520390] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  303.539485] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  303.539519] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  303.540556] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  303.540591] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  303.542821] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  303.542857] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  303.545056] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  303.545092] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  303.547280] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  303.547315] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  303.549526] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  303.549561] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  303.551789] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  303.551823] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  303.554049] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  303.554083] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  303.572805] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  303.572840] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  303.574283] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  303.574318] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  303.576378] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  303.576414] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  303.578642] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  303.578678] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  303.580857] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  303.580893] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  303.583127] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  303.583162] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  303.585372] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  303.585407] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  303.587643] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  303.587677] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  303.606111] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  303.606146] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  303.607924] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  303.607959] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  303.610190] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  303.610226] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  303.612348] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  303.612385] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  303.614607] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  303.614642] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  303.616809] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  303.616845] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  303.619073] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  303.619108] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  303.621316] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  303.621352] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  303.639412] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  303.639446] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  303.641582] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  303.641616] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  303.643850] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  303.643885] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  303.646114] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  303.646149] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  303.648305] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  303.648341] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  303.650566] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  303.650602] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  303.652710] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  303.652745] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  303.654974] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  303.655010] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  303.689588] [drm:drm_mode_addfb2 [drm]] [FB:72]
>[  303.689636] [drm:drm_mode_addfb2 [drm]] [FB:73]
>[  303.714017] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  303.714039] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  303.714066] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  303.714081] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[  303.714101] [drm:intel_edp_backlight_off [i915]] 
>[  303.920268] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0
>[  303.920399] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  303.923100] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[  303.923245] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b
>[  303.923537] [drm:intel_edp_panel_off.part.31 [i915]] Turn eDP port A panel power off
>[  303.923650] [drm:intel_edp_panel_off.part.31 [i915]] Wait for panel power off time
>[  303.923784] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000002 control 00000060
>[  303.975316] [drm:wait_panel_status [i915]] Wait complete
>[  303.975379] [drm:intel_power_well_disable [i915]] disabling DDI A/E IO power well
>[  303.975465] [drm:intel_disable_shared_dpll [i915]] disable DPLL 0 (active 2, on? 1) for crtc 47
>[  303.975540] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 0
>[  303.975632] [drm:intel_atomic_commit_tail [i915]] [ENCODER:48:DDI A]
>[  303.975704] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI B]
>[  303.975771] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  303.975835] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  303.975898] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DDI C]
>[  303.975959] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST A]
>[  303.976019] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST B]
>[  303.976114] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI D]
>[  303.976181] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[  303.976251] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[  303.976321] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:49:eDP-1]
>[  303.976397] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[  303.976469] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[  303.976538] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[  303.976601] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[  303.976671] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  303.976747] [drm:intel_atomic_commit_tail [i915]] [CRTC:47:pipe B]
>[  303.976808] [drm:intel_power_well_disable [i915]] disabling DC off
>[  303.976864] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  303.976918] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  303.977362] [drm:intel_power_well_disable [i915]] disabling always-on
>[  303.977429] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  303.977463] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  303.977562] [drm:intel_atomic_check [i915]] [CONNECTOR:57:DP-1] checking for sink bpp constrains
>[  303.977629] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  303.977705] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 148500KHz
>[  303.977780] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  303.977847] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 648000
>[  303.977918] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  303.977988] [drm:intel_dump_pipe_config [i915]] [CRTC:37:pipe A][modeset]
>[  303.978056] [drm:intel_dump_pipe_config [i915]] output_types: DP (0x80)
>[  303.978120] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[  303.978186] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5767168, gmch_n: 8388608, link_m: 240298, link_n: 262144, tu: 64
>[  303.978249] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  303.978310] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  303.978343] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  303.978406] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  303.978437] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  303.978503] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  303.978563] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1080, pixel rate 148500
>[  303.978624] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  303.978684] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  303.978745] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  303.978805] [drm:intel_dump_pipe_config [i915]] dpll_hw_state: ctrl1: 0x3, cfgcr1: 0x0, cfgcr2: 0x0
>[  303.978864] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  303.978922] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 1A] disabled, scaler_id = -1
>[  303.978982] [drm:intel_dump_pipe_config [i915]] [PLANE:31:plane 2A] disabled, scaler_id = -1
>[  303.979040] [drm:intel_dump_pipe_config [i915]] [PLANE:34:cursor A] disabled, scaler_id = -1
>[  303.979112] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  303.979177] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[  303.979254] [drm:intel_find_shared_dpll [i915]] [CRTC:37:pipe A] allocated DPLL 1
>[  303.979321] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[  303.982224] [drm:intel_power_well_enable [i915]] enabling always-on
>[  303.982280] [drm:intel_power_well_enable [i915]] enabling DC off
>[  303.982582] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  303.982656] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  303.982745] [drm:intel_atomic_commit_tail [i915]] [ENCODER:48:DDI A]
>[  303.982813] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI B]
>[  303.982872] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  303.982926] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  303.982980] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DDI C]
>[  303.983032] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST A]
>[  303.983083] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST B]
>[  303.983132] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI D]
>[  303.983185] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[  303.983254] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[  303.983319] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010
>[  303.983386] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  303.983453] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[  303.983522] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0
>[  303.983588] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[  303.983658] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[  303.983725] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  303.983790] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[  303.983864] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 37
>[  303.983935] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  303.984085] [drm:intel_power_well_enable [i915]] enabling DDI B IO power well
>[  303.984703] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  303.985828] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  303.986950] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  303.988088] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  303.989218] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  303.990347] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  303.991478] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  303.992135] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] too many retries, giving up
>[  303.992600] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  303.993726] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  303.994825] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  303.995960] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  303.997071] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  303.998199] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  303.999322] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  304.000030] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] too many retries, giving up
>[  304.001559] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  304.002686] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  304.003815] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  304.004921] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  304.006047] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  304.007180] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  304.008310] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  304.009009] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] too many retries, giving up
>[  304.009456] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  304.010581] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  304.011399] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  304.012582] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  304.013710] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  304.014837] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  304.015939] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  304.016637] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] too many retries, giving up
>[  304.018288] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  304.019564] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  304.020767] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  304.022050] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  304.022945] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  304.023930] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  304.023990] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  304.024073] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  304.024139] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  304.042929] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  304.042995] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  304.061698] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  304.061725] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  304.061750] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  304.080396] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  304.080723] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:57:DP-1] Link Training Passed at Link Rate = 162000, Lane count = 4
>[  304.081083] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  304.081123] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS
>[  304.081139] [drm:intel_fbc_enable [i915]] reserved 16588800 bytes of contiguous stolen space for FBC, threshold: 1
>[  304.081152] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  304.097929] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:57:DP-1]
>[  304.097947] [drm:intel_atomic_commit_tail [i915]] [CRTC:37:pipe A]
>[  304.097971] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[  304.114725] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  304.114733] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  304.116199] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  304.116206] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  304.118532] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  304.118541] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  304.120780] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  304.120789] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  304.123099] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  304.123108] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  304.125352] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  304.125361] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  304.127654] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  304.127665] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  304.129921] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  304.129932] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  304.147999] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  304.148022] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  304.150220] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  304.150236] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  304.152329] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  304.152344] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  304.154588] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  304.154603] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  304.156810] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  304.156828] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  304.159069] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  304.159087] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  304.161318] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  304.161340] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  304.163576] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  304.163597] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  304.181514] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  304.181550] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  304.181628] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  304.181652] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  304.183911] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  304.183946] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  304.186172] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  304.186209] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  304.188344] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  304.188382] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  304.190610] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  304.190646] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  304.192828] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  304.192865] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  304.195088] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  304.195124] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  304.197345] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  304.197381] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  304.214839] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  304.214875] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  304.215397] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  304.215433] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  304.217653] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  304.217690] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  304.219917] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  304.219952] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  304.222182] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  304.222219] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  304.224344] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  304.224382] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  304.226607] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  304.226644] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  304.228825] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  304.228862] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  304.231090] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  304.231127] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  304.248183] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  304.248218] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  304.249187] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  304.249223] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  304.251446] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  304.251481] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  304.253551] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  304.253584] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  304.255835] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  304.255872] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  304.258101] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  304.258136] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  304.260347] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  304.260385] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  304.262615] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  304.262650] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  304.281470] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  304.281505] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  304.282845] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  304.282881] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  304.285082] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  304.285117] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  304.287344] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  304.287379] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  304.289598] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  304.289634] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  304.291861] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  304.291897] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  304.294130] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  304.294166] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  304.296358] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  304.296395] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  304.314803] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  304.314838] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  304.316342] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  304.316378] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  304.318608] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  304.318645] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  304.320815] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  304.320852] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  304.323081] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  304.323117] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  304.325323] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  304.325361] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  304.327585] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  304.327622] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  304.329843] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  304.329879] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  304.348077] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  304.348111] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  304.350064] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  304.350100] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  304.352357] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  304.352393] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  304.354619] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  304.354655] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  304.356828] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  304.356864] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  304.359094] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  304.359130] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  304.361340] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  304.361376] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  304.363602] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  304.363638] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  304.381528] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  304.381562] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  304.383842] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  304.383878] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  304.386106] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  304.386142] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  304.388346] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  304.388383] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  304.390614] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  304.390649] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  304.392817] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  304.392855] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  304.395073] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  304.395109] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  304.397315] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  304.397352] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  304.414838] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  304.414873] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  304.415361] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  304.415397] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  304.417600] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  304.417636] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  304.419864] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  304.419900] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  304.422129] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  304.422165] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  304.424345] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  304.424383] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  304.426614] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  304.426651] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  304.428827] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  304.428864] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  304.431092] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  304.431127] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  304.448178] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  304.448213] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  304.449195] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  304.449230] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  304.451434] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  304.451470] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  304.453695] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  304.453731] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  304.455817] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  304.455853] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  304.457920] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  304.457954] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  304.460076] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  304.460119] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  304.462149] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  304.462183] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  304.464279] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  304.464313] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  304.481499] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  304.481533] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  304.482170] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  304.482206] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  304.484371] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  304.484408] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  304.486634] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  304.486671] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  304.488836] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  304.488873] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  304.491098] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  304.491134] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  304.493342] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  304.493379] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  304.495603] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  304.495639] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  304.497874] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  304.497910] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  304.514824] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  304.514859] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  304.515840] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  304.515874] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  304.518126] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  304.518162] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  304.520343] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  304.520380] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  304.522594] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  304.522630] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  304.524794] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  304.524830] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  304.527056] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  304.527092] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  304.529293] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  304.529330] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  304.548173] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  304.548207] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  304.549549] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  304.549586] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  304.551780] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  304.551816] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  304.554040] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  304.554076] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  304.556316] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  304.556353] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  304.558584] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  304.558621] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  304.560721] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  304.560757] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  304.562986] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  304.563021] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  304.581450] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  304.581484] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  304.583325] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  304.583360] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  304.585575] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  304.585612] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  304.587835] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  304.587871] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  304.590098] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  304.590134] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  304.592348] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  304.592384] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  304.594615] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  304.594651] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  304.596820] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  304.596856] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  304.614843] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  304.614878] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  304.616889] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  304.616922] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  304.619173] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  304.619208] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  304.621417] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  304.621453] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  304.623680] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  304.623715] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  304.625938] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  304.625975] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  304.628214] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  304.628251] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  304.630481] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  304.630518] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  304.648201] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  304.648236] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  304.648323] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  304.648348] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  304.650657] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  304.650694] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  304.652798] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  304.652835] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  304.655060] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  304.655096] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  304.657302] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  304.657339] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  304.659564] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  304.659600] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  304.661823] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  304.661860] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  304.664122] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  304.664163] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  304.681501] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  304.681536] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  304.681997] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  304.682032] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  304.684273] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  304.684310] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  304.686539] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  304.686575] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  304.688665] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  304.688700] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  304.690931] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  304.690968] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  304.693159] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  304.693195] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  304.695424] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  304.695459] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  304.697678] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  304.697714] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  304.714831] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  304.714867] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  304.715637] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  304.715671] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  304.717921] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  304.717957] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  304.720195] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  304.720231] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  304.722454] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  304.722490] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  304.724577] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  304.724613] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  304.726842] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  304.726879] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  304.729079] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  304.729116] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  304.748177] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  304.748212] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  304.749396] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  304.749432] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  304.751660] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  304.751696] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  304.753912] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  304.753949] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  304.756198] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  304.756235] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  304.758458] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  304.758494] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  304.760583] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  304.760619] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  304.762851] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  304.762886] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  304.781463] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  304.781499] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  304.783085] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  304.783120] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  304.785189] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  304.785222] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  304.787474] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  304.787511] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  304.789731] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  304.789767] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  304.791993] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  304.792069] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  304.794250] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  304.794286] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  304.796388] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  304.796424] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  304.814787] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  304.814823] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  304.816485] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  304.816519] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  304.818767] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  304.818803] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  304.820917] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  304.820953] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  304.823176] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  304.823212] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  304.825423] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  304.825459] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  304.827685] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  304.827721] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  304.829941] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  304.829978] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  304.848131] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  304.848165] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  304.849980] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  304.850015] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  304.852143] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  304.852183] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  304.854364] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  304.854399] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  304.856478] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  304.856515] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  304.858750] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  304.858787] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  304.860977] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  304.861012] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  304.863238] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  304.863273] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  304.881382] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  304.881416] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  304.883592] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  304.883628] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  304.885848] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  304.885885] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  304.888145] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  304.888184] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  304.890376] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  304.890412] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  304.892498] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  304.892534] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  304.894772] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  304.894808] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  304.896997] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  304.897032] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  304.914856] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  304.914891] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  304.917121] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  304.917159] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  304.919384] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  304.919419] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  304.921639] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  304.921675] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  304.923900] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  304.923936] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  304.926162] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  304.926198] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  304.928344] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  304.928380] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  304.930608] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  304.930644] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  304.948206] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  304.948241] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  304.948540] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  304.948575] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  304.950818] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  304.950854] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  304.953042] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  304.953078] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  304.955300] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  304.955336] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  304.957544] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  304.957581] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  304.959806] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  304.959843] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  304.962069] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  304.962106] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  304.964340] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  304.964377] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  304.981505] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  304.981540] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  304.982368] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  304.982404] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  304.984484] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  304.984521] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  304.986755] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  304.986791] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  304.988987] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  304.989023] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  304.991256] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  304.991292] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  304.993503] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  304.993539] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  304.995766] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  304.995802] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  305.014817] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  305.014852] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  305.015881] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  305.015915] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  305.018172] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  305.018208] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  305.020342] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  305.020379] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  305.022608] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  305.022644] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  305.024828] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  305.024864] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  305.027090] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  305.027125] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  305.029314] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  305.029351] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  305.048178] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  305.048213] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  305.049442] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  305.049477] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  305.051710] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  305.051746] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  305.053962] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  305.053999] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  305.056235] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  305.056273] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  305.058498] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  305.058535] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  305.060625] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  305.060661] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  305.062890] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  305.062927] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  305.081467] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  305.081501] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  305.083220] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  305.083255] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  305.085469] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  305.085505] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  305.087732] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  305.087769] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  305.089997] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  305.090032] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  305.092268] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  305.092306] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  305.094535] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  305.094571] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  305.096667] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  305.096703] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  305.114834] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  305.114870] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  305.115936] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  305.115969] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  305.118238] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  305.118270] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  305.120374] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  305.120411] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  305.122646] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  305.122682] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  305.124862] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  305.124899] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  305.127125] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  305.127161] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  305.129370] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  305.129407] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  305.148170] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  305.148205] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  305.149590] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  305.149626] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  305.151857] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  305.151893] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  305.154099] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  305.154134] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  305.156353] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  305.156392] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  305.158614] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  305.158651] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  305.160703] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  305.160740] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  305.162963] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  305.162999] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  305.181456] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  305.181491] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  305.183296] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  305.183331] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  305.185541] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  305.185576] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  305.187802] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  305.187838] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  305.190065] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  305.190102] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  305.192346] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  305.192383] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  305.194607] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  305.194643] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  305.196695] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  305.196732] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  305.214713] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  305.214747] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  305.216727] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  305.216764] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  305.218993] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  305.219029] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  305.221232] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  305.221269] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  305.223495] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  305.223530] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  305.225748] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  305.225786] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  305.228012] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  305.228089] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  305.230273] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  305.230307] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  305.248191] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  305.248226] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  305.250380] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  305.250416] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  305.252477] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  305.252512] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  305.254721] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  305.254757] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  305.256950] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  305.256986] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  305.259215] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  305.259251] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  305.261460] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  305.261496] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  305.263722] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  305.263758] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  305.281463] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  305.281497] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  305.281676] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  305.281710] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  305.283954] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  305.283990] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  305.286216] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  305.286252] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  305.288360] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  305.288397] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  305.290602] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  305.290638] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  305.292691] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  305.292727] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  305.294954] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  305.294990] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  305.297186] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  305.297223] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  305.314862] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  305.314897] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  305.317162] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  305.317197] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  305.319423] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  305.319458] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  305.321676] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  305.321711] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  305.323937] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  305.323973] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  305.326202] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  305.326239] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  305.328367] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  305.328404] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  305.330624] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  305.330661] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  305.348193] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  305.348228] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  305.348514] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  305.348548] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  305.350802] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  305.350838] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  305.353027] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  305.353063] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  305.355277] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  305.355313] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  305.357522] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  305.357559] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  305.359785] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  305.359821] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  305.362053] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  305.362090] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  305.364336] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  305.364372] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  305.381502] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  305.381537] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  305.382347] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  305.382383] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  305.384453] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  305.384489] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  305.386711] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  305.386746] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  305.388925] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  305.388962] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  305.391186] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  305.391223] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  305.393432] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  305.393468] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  305.395693] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  305.395729] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  305.397941] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  305.397977] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  305.414822] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  305.414857] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  305.416109] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  305.416148] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  305.418311] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  305.418347] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  305.420372] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  305.420410] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  305.422671] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  305.422707] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  305.424892] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  305.424927] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  305.427151] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  305.427187] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  305.429394] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  305.429431] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  305.448163] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  305.448197] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  305.449615] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  305.449650] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  305.451882] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  305.451917] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  305.454149] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  305.454186] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  305.456355] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  305.456393] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  305.458611] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  305.458647] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  305.460829] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  305.460865] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  305.463092] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  305.463128] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  305.481389] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  305.481425] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  305.483422] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  305.483458] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  305.485677] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  305.485713] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  305.487939] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  305.487975] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  305.490202] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  305.490239] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  305.492351] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  305.492389] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  305.494610] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  305.494647] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  305.496826] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  305.496863] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  305.514848] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  305.514884] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  305.517018] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  305.517054] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  305.519280] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  305.519315] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  305.521527] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  305.521564] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  305.523789] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  305.523825] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  305.526053] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  305.526090] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  305.528334] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  305.528373] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  305.530595] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  305.530631] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  305.548201] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  305.548236] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  305.548487] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  305.548520] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  305.550778] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  305.550814] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  305.553005] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  305.553042] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  305.555228] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  305.555264] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  305.557474] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  305.557509] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  305.559734] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  305.559769] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  305.561995] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  305.562032] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  305.564277] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  305.564313] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  305.581375] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  305.581410] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  305.581658] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  305.581691] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  305.583782] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  305.583816] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  305.585940] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  305.585976] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  305.588189] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  305.588226] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  305.590478] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  305.590514] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  305.592562] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  305.592598] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  305.594833] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  305.594869] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  305.597067] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  305.597104] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  305.614848] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  305.614883] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  305.614961] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  305.614985] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  305.617233] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  305.617269] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  305.619498] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  305.619533] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  305.621758] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  305.621793] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  305.624020] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  305.624097] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  305.626281] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  305.626317] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  305.628394] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  305.628432] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  305.630664] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  305.630700] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  305.648204] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  305.648239] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  305.648684] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  305.648719] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  305.650951] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  305.650987] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  305.653186] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  305.653223] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  305.655383] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  305.655420] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  305.657637] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  305.657673] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  305.659903] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  305.659939] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  305.662172] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  305.662208] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  305.664353] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  305.664391] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  305.681500] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  305.681534] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  305.682390] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  305.682426] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  305.684484] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  305.684520] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  305.686751] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  305.686787] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  305.688983] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  305.689019] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  305.691245] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  305.691282] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  305.693494] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  305.693530] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  305.695756] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  305.695792] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  305.714818] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  305.714854] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  305.715958] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  305.715992] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  305.718242] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  305.718278] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  305.720339] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  305.720375] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  305.722605] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  305.722641] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  305.724694] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  305.724729] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  305.726962] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  305.726998] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  305.729200] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  305.729237] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  305.748184] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  305.748219] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  305.749422] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  305.749458] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  305.751693] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  305.751729] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  305.753953] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  305.753989] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  305.756200] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  305.756237] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  305.758454] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  305.758491] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  305.760516] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  305.760550] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  305.762805] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  305.762841] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  305.781476] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  305.781512] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  305.783053] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  305.783089] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  305.785296] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  305.785332] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  305.787556] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  305.787593] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  305.789821] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  305.789857] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  305.792117] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  305.792158] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  305.794346] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  305.794382] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  305.796445] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  305.796481] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  305.814792] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  305.814825] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  305.816487] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  305.816521] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  305.818771] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  305.818807] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  305.820996] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  305.821032] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  305.823256] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  305.823291] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  305.825508] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  305.825543] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  305.827768] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  305.827804] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  305.830031] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  305.830067] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  305.848064] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  305.848100] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  305.850220] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  305.850257] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  305.852359] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  305.852396] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  305.854614] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  305.854650] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  305.856832] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  305.856868] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  305.859096] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  305.859132] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  305.861343] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  305.861380] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  305.863602] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  305.863638] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  305.881520] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  305.881555] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  305.883745] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  305.883781] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  305.886007] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  305.886044] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  305.888284] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  305.888323] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  305.890549] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  305.890584] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  305.892633] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  305.892670] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  305.894902] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  305.894938] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  305.897123] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  305.897160] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  305.914844] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  305.914879] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  305.914966] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  305.914991] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  305.917276] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  305.917312] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  305.919537] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  305.919573] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  305.921796] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  305.921831] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  305.924098] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  305.924138] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  305.926319] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  305.926355] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  305.928391] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  305.928430] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  305.930664] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  305.930700] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  305.948192] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  305.948226] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  305.948687] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  305.948723] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  305.950950] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  305.950986] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  305.953183] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  305.953220] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  305.955448] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  305.955484] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  305.957700] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  305.957736] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  305.959961] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  305.959996] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  305.962226] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  305.962262] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  305.964364] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  305.964401] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  305.981498] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  305.981533] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  305.982401] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  305.982437] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  305.984496] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  305.984532] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  305.986761] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  305.986798] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  305.988990] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  305.989027] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  305.991257] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  305.991293] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  305.993505] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  305.993542] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  305.995779] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  305.995815] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  306.014827] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  306.014862] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  306.016055] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  306.016097] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  306.018314] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  306.018350] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  306.020387] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  306.020426] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  306.022672] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  306.022708] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  306.024893] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  306.024929] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  306.027153] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  306.027189] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  306.029399] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  306.029435] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  306.048173] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  306.048207] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  306.049629] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  306.049665] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  306.051894] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  306.051930] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  306.054166] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  306.054201] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  306.056366] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  306.056403] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  306.058606] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  306.058642] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  306.060692] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  306.060729] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  306.062959] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  306.062995] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  306.081461] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  306.081497] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  306.083304] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  306.083340] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  306.085550] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  306.085586] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  306.087814] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  306.087850] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  306.090074] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  306.090111] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  306.092354] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  306.092392] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  306.094613] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  306.094649] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  306.096833] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  306.096869] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  306.114809] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  306.114844] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  306.116971] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  306.117007] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  306.119231] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  306.119266] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  306.121478] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  306.121514] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  306.123739] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  306.123776] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  306.126001] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  306.126038] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  306.128284] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  306.128321] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  306.130546] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  306.130582] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  306.148208] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  306.148244] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  306.148450] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  306.148483] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  306.150741] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  306.150778] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  306.152958] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  306.152994] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  306.155198] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  306.155234] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  306.157435] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  306.157472] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  306.159696] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  306.159732] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  306.161958] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  306.161994] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  306.164237] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  306.164274] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  306.181508] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  306.181544] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  306.182126] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  306.182162] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  306.184353] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  306.184391] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  306.186594] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  306.186631] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  306.188811] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  306.188849] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  306.191075] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  306.191111] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  306.193318] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  306.193355] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  306.195587] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  306.195623] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  306.197857] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  306.197894] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  306.214825] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  306.214859] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  306.215792] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  306.215826] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  306.218081] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  306.218117] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  306.220220] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  306.220258] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  306.222488] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  306.222525] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  306.224577] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  306.224613] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  306.226841] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  306.226878] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  306.229075] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  306.229111] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  306.248171] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  306.248207] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  306.249422] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  306.249458] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  306.251698] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  306.251734] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  306.253957] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  306.253993] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  306.256241] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  306.256277] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  306.258486] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  306.258521] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  306.260577] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  306.260613] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  306.262840] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  306.262876] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  306.281466] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  306.281500] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  306.283059] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  306.283095] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  306.285301] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  306.285337] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  306.287562] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  306.287598] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  306.289811] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  306.289846] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  306.292115] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  306.292155] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  306.294335] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  306.294372] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  306.296434] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  306.296471] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  306.314806] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  306.314841] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  306.316241] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  306.316276] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  306.318525] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  306.318561] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  306.320613] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  306.320649] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  306.322877] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  306.322914] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  306.325110] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  306.325146] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  306.327374] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  306.327410] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  306.329627] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  306.329663] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  306.348155] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  306.348190] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  306.349779] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  306.349815] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  306.352082] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  306.352124] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  306.354312] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  306.354348] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  306.356384] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  306.356421] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  306.358648] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  306.358685] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  306.360860] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  306.360896] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  306.363123] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  306.363158] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  306.381383] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  306.381417] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  306.383493] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  306.383529] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  306.385748] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  306.385784] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  306.388013] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  306.388091] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  306.390277] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  306.390313] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  306.392392] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  306.392428] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  306.394660] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  306.394696] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  306.396881] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  306.396918] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  306.414855] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  306.414890] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  306.417041] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  306.417077] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  306.419307] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  306.419343] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  306.421551] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  306.421587] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  306.423814] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  306.423849] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  306.426077] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  306.426114] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  306.428358] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  306.428394] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  306.430620] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  306.430656] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  306.448207] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  306.448241] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  306.448474] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  306.448507] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  306.450766] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  306.450801] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  306.452987] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  306.453023] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  306.455248] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  306.455283] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  306.457493] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  306.457530] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  306.459752] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  306.459788] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  306.462013] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  306.462049] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  306.464299] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  306.464336] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  306.481510] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  306.481546] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  306.482241] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  306.482278] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  306.484381] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  306.484417] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  306.486641] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  306.486677] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  306.488862] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  306.488899] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  306.491124] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  306.491160] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  306.493371] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  306.493407] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  306.495636] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  306.495672] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  306.497895] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  306.497932] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  306.514820] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  306.514855] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  306.515879] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  306.515912] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  306.518168] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  306.518204] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  306.520353] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  306.520390] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  306.522616] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  306.522652] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  306.524706] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  306.524742] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  306.526973] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  306.527009] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  306.529207] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  306.529244] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  306.548174] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  306.548209] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  306.549568] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  306.549603] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  306.551839] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  306.551875] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  306.554103] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  306.554138] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  306.556359] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  306.556395] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  306.558561] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  306.558597] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  306.560648] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  306.560684] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  306.562915] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  306.562951] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  306.581471] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  306.581507] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  306.583100] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  306.583136] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  306.585343] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  306.585379] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  306.587604] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  306.587640] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  306.589864] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  306.589900] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  306.592155] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  306.592194] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  306.594410] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  306.594446] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  306.596507] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  306.596542] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  306.614796] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  306.614832] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  306.616556] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  306.616592] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  306.618825] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  306.618861] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  306.621053] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  306.621089] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  306.623317] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  306.623353] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  306.625566] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  306.625602] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  306.627833] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  306.627869] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  306.630085] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  306.630122] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  306.648161] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  306.648195] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  306.650352] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  306.650389] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  306.652413] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  306.652449] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  306.654703] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  306.654739] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  306.656792] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  306.656827] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  306.659000] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  306.659036] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  306.661238] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  306.661274] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  306.663499] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  306.663535] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  306.681519] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  306.681554] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  306.683742] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  306.683778] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  306.686002] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  306.686039] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  306.688287] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  306.688327] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  306.690548] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  306.690585] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  306.692637] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  306.692674] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  306.694911] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  306.694947] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  306.697142] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  306.697177] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  306.714843] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  306.714878] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  306.714968] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  306.714994] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  306.717293] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  306.717329] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  306.719554] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  306.719589] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  306.721803] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  306.721839] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  306.724108] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  306.724161] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  306.726330] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  306.726367] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  306.728403] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  306.728438] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  306.730691] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  306.730727] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  306.748205] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  306.748239] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  306.748686] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  306.748722] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  306.750959] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  306.750994] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  306.753192] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  306.753229] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  306.755455] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  306.755492] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  306.757709] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  306.757744] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  306.759950] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  306.759986] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  306.762209] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  306.762245] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  306.764353] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  306.764389] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  306.781498] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  306.781533] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  306.782379] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  306.782415] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  306.784441] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  306.784476] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  306.786741] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  306.786777] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  306.788969] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  306.789004] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  306.791230] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  306.791266] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  306.793479] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  306.793516] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  306.795740] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  306.795776] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  306.814820] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  306.814854] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  306.815970] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  306.816003] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  306.818254] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  306.818289] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  306.820394] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  306.820430] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  306.822650] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  306.822686] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  306.824873] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  306.824910] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  306.827135] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  306.827170] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  306.829383] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  306.829419] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  306.848177] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  306.848210] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  306.849493] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  306.849529] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  306.851762] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  306.851798] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  306.854011] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  306.854048] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  306.856301] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  306.856337] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  306.858560] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  306.858596] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  306.860649] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  306.860685] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  306.862913] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  306.862950] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  306.881476] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  306.881512] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  306.883033] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  306.883069] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  306.885274] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  306.885310] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  306.887538] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  306.887574] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  306.889793] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  306.889828] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  306.892097] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  306.892139] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  306.894314] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  306.894350] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  306.896388] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  306.896424] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  306.914784] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  306.914819] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  306.916509] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  306.916545] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  306.918771] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  306.918807] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  306.920999] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  306.921035] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  306.923258] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  306.923293] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  306.925503] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  306.925538] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  306.927765] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  306.927801] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  306.930025] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  306.930061] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  306.948110] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  306.948145] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  306.950297] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  306.950334] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  306.952403] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  306.952440] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  306.954650] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  306.954687] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  306.956738] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  306.956774] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  306.959006] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  306.959041] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  306.961248] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  306.961285] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  306.963511] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  306.963548] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  306.981533] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  306.981568] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  306.983741] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  306.983778] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  306.986002] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  306.986039] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  306.988285] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  306.988322] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  306.990543] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  306.990578] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  306.992627] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  306.992664] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  306.994897] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  306.994934] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  306.997122] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  306.997160] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  307.014850] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  307.014885] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  307.014977] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  307.015003] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  307.017306] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  307.017342] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  307.019568] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  307.019604] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  307.021826] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  307.021863] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  307.024127] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  307.024177] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  307.026354] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  307.026391] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  307.028422] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  307.028457] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  307.030724] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  307.030760] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  307.048204] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  307.048238] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  307.048754] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  307.048791] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  307.051019] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  307.051054] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  307.053265] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  307.053301] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  307.055524] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  307.055561] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  307.057780] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  307.057817] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  307.060085] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  307.060129] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  307.062303] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  307.062339] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  307.064406] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  307.064442] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  307.081485] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  307.081520] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  307.082441] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  307.082476] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  307.084539] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  307.084575] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  307.086804] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  307.086841] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  307.089033] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  307.089069] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  307.091300] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  307.091336] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  307.093548] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  307.093584] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  307.095816] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  307.095851] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  307.114829] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  307.114865] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  307.115931] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  307.115964] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  307.118223] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  307.118259] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  307.120366] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  307.120403] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  307.122625] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  307.122662] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  307.124847] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  307.124883] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  307.127106] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  307.127142] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  307.129349] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  307.129386] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  307.148185] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  307.148221] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  307.149571] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  307.149606] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  307.151835] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  307.151870] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  307.154101] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  307.154137] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  307.156358] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  307.156396] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  307.158622] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  307.158658] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  307.160709] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  307.160744] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  307.162976] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  307.163012] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  307.181454] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  307.181489] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  307.183294] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  307.183330] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  307.185537] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  307.185573] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  307.187810] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  307.187846] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  307.190074] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  307.190109] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  307.192352] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  307.192392] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  307.194617] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  307.194653] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  307.196705] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  307.196741] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  307.214749] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  307.214784] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  307.216912] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  307.216949] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  307.219175] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  307.219210] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  307.221426] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  307.221462] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  307.223690] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  307.223726] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  307.225953] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  307.225989] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  307.228237] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  307.228274] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  307.230506] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  307.230544] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  307.248202] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  307.248238] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  307.250518] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  307.250554] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  307.252613] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  307.252649] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  307.254883] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  307.254919] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  307.257108] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  307.257143] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  307.259370] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  307.259406] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  307.261614] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  307.261650] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  307.263872] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  307.263908] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  307.281523] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  307.281558] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  307.281826] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  307.281860] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  307.284152] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  307.284204] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  307.286376] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  307.286413] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  307.288442] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  307.288477] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  307.290738] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  307.290774] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  307.292966] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  307.293003] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  307.295227] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  307.295263] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  307.297473] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  307.297510] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  307.314842] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  307.314877] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  307.315369] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  307.315403] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  307.317651] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  307.317687] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  307.319921] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  307.319958] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  307.322186] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  307.322221] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  307.324362] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  307.324400] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  307.326623] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  307.326659] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  307.328844] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  307.328880] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  307.331108] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  307.331145] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  307.348192] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  307.348227] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  307.348823] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  307.348858] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  307.351092] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  307.351126] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  307.353332] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  307.353368] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  307.355600] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  307.355636] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  307.357856] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  307.357892] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  307.360162] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  307.360214] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  307.362371] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  307.362407] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  307.364433] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  307.364469] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  307.381497] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  307.381532] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  307.382516] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  307.382552] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  307.384611] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  307.384646] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  307.386875] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  307.386911] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  307.389111] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  307.389148] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  307.391371] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  307.391408] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  307.393627] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  307.393662] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  307.395891] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  307.395926] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  307.414818] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  307.414854] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  307.416136] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  307.416179] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  307.418423] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  307.418459] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  307.420517] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  307.420552] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  307.422783] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  307.422819] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  307.425008] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  307.425043] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  307.427268] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  307.427305] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  307.429518] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  307.429554] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  307.448157] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  307.448192] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  307.449754] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  307.449790] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  307.452020] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  307.452096] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  307.454276] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  307.454312] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  307.456396] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  307.456433] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  307.458656] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  307.458693] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  307.460882] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  307.460920] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  307.463139] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  307.463175] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  307.481380] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  307.481415] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  307.483496] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  307.483532] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  307.485747] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  307.485784] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  307.488012] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  307.488089] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  307.490271] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  307.490309] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  307.492398] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  307.492434] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  307.494662] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  307.494697] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  307.496890] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  307.496927] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  307.514856] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  307.514891] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  307.517060] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  307.517096] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  307.519323] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  307.519358] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  307.521575] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  307.521611] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  307.523841] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  307.523878] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  307.526105] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  307.526141] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  307.528361] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  307.528398] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  307.530619] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  307.530655] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  307.548204] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  307.548239] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  307.548569] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  307.548604] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  307.550837] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  307.550872] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  307.553064] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  307.553100] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  307.555327] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  307.555363] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  307.557579] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  307.557615] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  307.559844] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  307.559879] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  307.561975] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  307.562011] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  307.564263] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  307.564299] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  307.581513] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  307.581549] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  307.582197] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  307.582232] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  307.584350] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  307.584387] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  307.586614] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  307.586650] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  307.588830] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  307.588867] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  307.591091] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  307.591127] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  307.593339] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  307.593375] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  307.595599] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  307.595635] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  307.597871] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  307.597908] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  307.614837] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  307.614872] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  307.615613] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  307.615647] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  307.617887] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  307.617923] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  307.620162] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  307.620208] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  307.622419] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  307.622455] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  307.624490] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  307.624526] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  307.626787] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  307.626822] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  307.629015] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  307.629052] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  307.631277] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  307.631312] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  307.648186] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  307.648221] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  307.649381] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  307.649417] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  307.651645] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  307.651681] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  307.653903] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  307.653939] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  307.656228] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  307.656264] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  307.658421] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  307.658458] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  307.660515] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  307.660551] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  307.662719] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  307.662756] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  307.681476] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  307.681513] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  307.682988] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  307.683024] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  307.685226] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  307.685263] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  307.687487] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  307.687523] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  307.689744] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  307.689781] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  307.692005] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  307.692081] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  307.694265] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  307.694300] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  307.696396] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  307.696433] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  307.714796] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  307.714830] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  307.716438] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  307.716473] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  307.718723] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  307.718759] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  307.720940] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  307.720977] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  307.723202] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  307.723239] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  307.725452] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  307.725488] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  307.727715] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  307.727750] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  307.729983] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  307.730018] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  307.748091] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  307.748126] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  307.750277] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  307.750313] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  307.752398] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  307.752435] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  307.754661] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  307.754697] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  307.756873] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  307.756909] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  307.759136] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  307.759172] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  307.761380] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  307.761416] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  307.763614] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  307.763650] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  307.781532] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  307.781568] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  307.783867] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  307.783902] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  307.786132] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  307.786169] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  307.788352] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  307.788390] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  307.790616] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  307.790652] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  307.792698] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  307.792734] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  307.794966] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  307.795002] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  307.797198] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  307.797234] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  307.814854] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  307.814890] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  307.817177] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  307.817214] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  307.819442] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  307.819478] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  307.821697] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  307.821733] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  307.823962] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  307.823999] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  307.826213] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  307.826249] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  307.828351] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  307.828388] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  307.830613] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  307.830648] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  307.848200] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  307.848236] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  307.848570] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  307.848606] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  307.850822] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  307.850857] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  307.853046] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  307.853081] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  307.855310] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  307.855346] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  307.857558] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  307.857594] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  307.859820] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  307.859854] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  307.862083] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  307.862119] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  307.864324] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  307.864363] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  307.881501] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  307.881536] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  307.882341] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  307.882377] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  307.884437] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  307.884474] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  307.886733] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  307.886768] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  307.888961] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  307.888998] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  307.891222] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  307.891258] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  307.893459] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  307.893494] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  307.895726] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  307.895762] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  307.914817] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  307.914851] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  307.915996] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  307.916066] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  307.918284] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  307.918321] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  307.920392] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  307.920428] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  307.922668] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  307.922703] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  307.924883] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  307.924920] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  307.927147] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  307.927183] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  307.929392] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  307.929428] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  307.948174] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  307.948208] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  307.949622] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  307.949658] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  307.951887] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  307.951922] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  307.954151] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  307.954187] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  307.956346] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  307.956383] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  307.958614] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  307.958651] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  307.960835] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  307.960871] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  307.963094] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  307.963129] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  307.981452] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  307.981487] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  307.983341] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  307.983377] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  307.985591] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  307.985627] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  307.987853] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  307.987889] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  307.990116] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  307.990152] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  307.992345] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  307.992382] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  307.994601] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  307.994638] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  307.996817] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  307.996853] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  308.014853] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  308.014888] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  308.017028] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  308.017064] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  308.019292] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  308.019329] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  308.021527] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  308.021563] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  308.023791] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  308.023827] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  308.026052] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  308.026088] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  308.028328] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  308.028365] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  308.030594] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  308.030630] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  308.048207] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  308.048242] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  308.048515] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  308.048549] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  308.050808] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  308.050843] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  308.053032] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  308.053069] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  308.055300] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  308.055336] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  308.057542] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  308.057578] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  308.059807] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  308.059843] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  308.062058] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  308.062095] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  308.064280] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  308.064317] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  308.081524] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  308.081559] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  308.082224] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  308.082259] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  308.084361] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  308.084398] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  308.086621] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  308.086657] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  308.088721] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  308.088755] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  308.091009] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  308.091045] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  308.093243] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  308.093278] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  308.095505] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  308.095542] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  308.097761] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  308.097797] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  308.114835] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  308.114870] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  308.115708] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  308.115742] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  308.117997] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  308.118034] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  308.120273] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  308.120310] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  308.122544] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  308.122581] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  308.124689] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  308.124726] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  308.126951] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  308.126987] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  308.129183] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  308.129219] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  308.148175] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  308.148210] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  308.149563] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  308.149598] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  308.151826] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  308.151861] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  308.154087] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  308.154123] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  308.156351] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  308.156388] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  308.158611] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  308.158647] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  308.160814] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  308.160851] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  308.163080] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  308.163117] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  308.181397] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  308.181432] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  308.183426] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  308.183462] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  308.185682] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  308.185717] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  308.187946] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  308.187981] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  308.190210] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  308.190246] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  308.192345] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  308.192382] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  308.194609] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  308.194646] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  308.196811] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  308.196847] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  308.214857] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  308.214892] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  308.217023] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  308.217060] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  308.219285] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  308.219322] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  308.221543] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  308.221578] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  308.223805] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  308.223840] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  308.226067] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  308.226103] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  308.228349] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  308.228386] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  308.230615] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  308.230651] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  308.248198] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  308.248234] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  308.248473] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  308.248507] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  308.250758] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  308.250793] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  308.252969] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  308.253005] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  308.255232] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  308.255268] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  308.257481] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  308.257516] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  308.259743] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  308.259778] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  308.262004] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  308.262040] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  308.264285] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  308.264332] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  308.281517] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  308.281552] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  308.282229] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  308.282265] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  308.284367] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  308.284403] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  308.286635] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  308.286671] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  308.288859] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  308.288895] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  308.290989] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  308.291024] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  308.293222] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  308.293259] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  308.295485] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  308.295522] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  308.297742] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  308.297779] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  308.314850] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  308.314884] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  308.315422] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  308.315455] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  308.317701] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  308.317737] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  308.319963] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  308.319998] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  308.322228] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  308.322265] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  308.324358] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  308.324394] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  308.326627] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  308.326663] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  308.328836] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  308.328873] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  308.331100] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  308.331137] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  308.348204] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  308.348239] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  308.348847] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  308.348883] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  308.351115] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  308.351152] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  308.353331] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  308.353366] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  308.355597] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  308.355633] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  308.357857] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  308.357893] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  308.360157] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  308.360204] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  308.362386] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  308.362422] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  308.364545] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  308.364581] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  308.381490] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  308.381525] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  308.382549] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  308.382585] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  308.384681] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  308.384718] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  308.386946] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  308.386981] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  308.389182] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  308.389218] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  308.391444] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  308.391480] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  308.393688] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  308.393724] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  308.395950] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  308.395986] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  308.414832] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  308.414867] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  308.416010] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  308.416079] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  308.418298] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  308.418334] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  308.420401] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  308.420437] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  308.422692] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  308.422729] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  308.424915] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  308.424950] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  308.427175] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  308.427211] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  308.429423] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  308.429459] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  308.448163] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  308.448197] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  308.449643] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  308.449679] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  308.451907] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  308.451943] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  308.454151] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  308.454187] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  308.456343] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  308.456380] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  308.458608] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  308.458645] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  308.460812] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  308.460849] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  308.463075] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  308.463111] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  308.481470] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  308.481506] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  308.483184] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  308.483220] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  308.485432] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  308.485468] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  308.487692] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  308.487728] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  308.489922] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  308.489958] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  308.492197] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  308.492234] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  308.494462] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  308.494498] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  308.496584] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  308.496620] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  308.514734] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  308.514769] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  308.516625] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  308.516660] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  308.518891] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  308.518926] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  308.521118] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  308.521154] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  308.523379] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  308.523414] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  308.525635] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  308.525671] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  308.527897] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  308.527932] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  308.530161] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  308.530197] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  308.548201] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  308.548236] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  308.550426] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  308.550462] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  308.552553] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  308.552589] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  308.554817] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  308.554852] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  308.557048] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  308.557084] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  308.559312] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  308.559347] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  308.561557] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  308.561593] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  308.563820] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  308.563856] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  308.581521] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  308.581556] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  308.581746] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  308.581779] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  308.584073] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  308.584116] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  308.586299] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  308.586334] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  308.588403] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  308.588439] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  308.590694] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  308.590730] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  308.592921] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  308.592957] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  308.595180] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  308.595216] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  308.597425] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  308.597462] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  308.614844] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  308.614879] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  308.615387] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  308.615420] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  308.617554] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  308.617590] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  308.619818] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  308.619855] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  308.622081] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  308.622118] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  308.624347] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  308.624386] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  308.626610] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  308.626647] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  308.628820] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  308.628856] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  308.631081] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  308.631117] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  308.648195] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  308.648230] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  308.649154] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  308.649189] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  308.651425] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  308.651461] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  308.653683] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  308.653720] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  308.655944] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  308.655980] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  308.658206] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  308.658242] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  308.660343] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  308.660380] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  308.662612] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  308.662647] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  308.681485] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  308.681522] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  308.682828] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  308.682864] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  308.685056] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  308.685093] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  308.687323] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  308.687359] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  308.689563] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  308.689599] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  308.691825] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  308.691861] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  308.694089] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  308.694126] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  308.696342] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  308.696379] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  308.714799] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  308.714833] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  308.716391] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  308.716427] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  308.718691] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  308.718727] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  308.720905] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  308.720942] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  308.723169] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  308.723204] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  308.725420] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  308.725456] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  308.727683] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  308.727719] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  308.729944] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  308.729981] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  308.748085] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  308.748120] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  308.750066] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  308.750103] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  308.752343] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  308.752379] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  308.754605] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  308.754641] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  308.756811] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  308.756848] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  308.759076] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  308.759111] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  308.761318] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  308.761354] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  308.763579] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  308.763615] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  308.781531] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  308.781566] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  308.783825] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  308.783861] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  308.786098] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  308.786135] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  308.788345] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  308.788384] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  308.790614] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  308.790650] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  308.792813] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  308.792850] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  308.795075] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  308.795111] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  308.797328] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  308.797365] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  308.814853] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  308.814888] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  308.814969] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  308.814994] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  308.817261] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  308.817297] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  308.819524] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  308.819559] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  308.821779] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  308.821816] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  308.824076] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  308.824118] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  308.826299] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  308.826335] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  308.828406] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  308.828459] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  308.830688] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  308.830724] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  308.848201] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  308.848236] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  308.848689] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  308.848724] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  308.850956] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  308.850993] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  308.853087] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  308.853122] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  308.855350] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  308.855386] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  308.857609] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  308.857645] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  308.859871] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  308.859908] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  308.862137] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  308.862174] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  308.864341] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  308.864379] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  308.881517] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  308.881551] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  308.882132] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  308.882167] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  308.884342] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  308.884379] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  308.886608] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  308.886645] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  308.888808] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  308.888845] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  308.891069] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  308.891106] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  308.893292] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  308.893329] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  308.895549] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  308.895585] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  308.897815] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  308.897854] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  308.914838] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  308.914874] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  308.915757] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  308.915791] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  308.918044] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  308.918080] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  308.920318] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  308.920355] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  308.922585] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  308.922621] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  308.924795] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  308.924832] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  308.927054] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  308.927090] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  308.929299] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  308.929336] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  308.948185] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  308.948219] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  308.949552] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  308.949587] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  308.951820] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  308.951855] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  308.954080] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  308.954116] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  308.956363] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  308.956401] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  308.958625] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  308.958661] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  308.960832] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  308.960868] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  308.963099] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  308.963135] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  308.981401] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  308.981437] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  308.983411] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  308.983447] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  308.985665] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  308.985701] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  308.987931] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  308.987966] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  308.990198] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  308.990236] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  308.992340] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  308.992377] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  308.994608] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  308.994644] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  308.996747] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  308.996784] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  309.014839] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  309.014874] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  309.017017] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  309.017053] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  309.019278] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  309.019313] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  309.021529] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  309.021565] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  309.023792] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  309.023827] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  309.026057] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  309.026094] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  309.028330] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  309.028367] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  309.030597] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  309.030634] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  309.048207] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  309.048241] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  309.048534] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  309.048570] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  309.050820] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  309.050856] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  309.053036] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  309.053073] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  309.055299] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  309.055335] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  309.057541] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  309.057577] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  309.059803] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  309.059839] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  309.062076] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  309.062112] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  309.064341] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  309.064379] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  309.081507] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  309.081542] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  309.082383] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  309.082418] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  309.084519] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  309.084555] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  309.086774] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  309.086811] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  309.089001] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  309.089037] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  309.091265] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  309.091301] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  309.093515] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  309.093551] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  309.095781] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  309.095817] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  309.114830] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  309.114864] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  309.115978] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  309.116047] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  309.118264] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  309.118301] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  309.120395] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  309.120433] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  309.122666] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  309.122702] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  309.124890] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  309.124927] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  309.127150] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  309.127186] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  309.129398] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  309.129434] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  309.148182] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  309.148216] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  309.149619] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  309.149655] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  309.151892] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  309.151929] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  309.154155] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  309.154191] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  309.156342] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  309.156378] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  309.158616] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  309.158652] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  309.160821] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  309.160858] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  309.163085] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  309.163121] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  309.181404] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  309.181439] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  309.183416] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  309.183452] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  309.185667] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  309.185703] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  309.187929] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  309.187965] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  309.190196] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  309.190232] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  309.192342] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  309.192378] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  309.194608] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  309.194644] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  309.196813] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  309.196849] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  309.214831] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  309.214865] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  309.216997] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  309.217033] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  309.219258] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  309.219294] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  309.221507] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  309.221543] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  309.223776] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  309.223811] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  309.226040] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  309.226076] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  309.228328] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  309.228364] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  309.230588] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  309.230623] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  309.248202] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  309.248239] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  309.248444] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  309.248477] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  309.250736] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  309.250772] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  309.252953] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  309.252989] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  309.255214] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  309.255249] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  309.257431] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  309.257467] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  309.259688] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  309.259724] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  309.261943] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  309.261979] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  309.264211] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  309.264248] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  309.281519] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  309.281555] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  309.282233] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  309.282268] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  309.284362] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  309.284400] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  309.286631] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  309.286667] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  309.288847] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  309.288883] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  309.291052] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  309.291088] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  309.293296] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  309.293332] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  309.295561] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  309.295597] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  309.297832] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  309.297870] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  309.314814] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  309.314849] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  309.315598] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  309.315631] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  309.317875] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  309.317911] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  309.320181] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  309.320229] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  309.322426] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  309.322462] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  309.324550] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  309.324586] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  309.326820] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  309.326856] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  309.329050] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  309.329085] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  309.348192] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  309.348226] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  309.349204] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  309.349240] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  309.351470] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  309.351506] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  309.353723] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  309.353759] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  309.355989] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  309.356063] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  309.358245] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  309.358281] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  309.360373] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  309.360409] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  309.362644] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  309.362680] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  309.381505] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  309.381539] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  309.382839] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  309.382874] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  309.385078] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  309.385113] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  309.387342] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  309.387377] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  309.389594] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  309.389630] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  309.391855] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  309.391891] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  309.394113] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  309.394149] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  309.396344] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  309.396381] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  309.414811] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  309.414846] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  309.416383] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  309.416424] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  309.418673] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  309.418709] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  309.420888] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  309.420924] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  309.423150] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  309.423186] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  309.425397] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  309.425434] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  309.427664] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  309.427699] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  309.429920] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  309.429956] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  309.448070] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  309.448105] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  309.450192] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  309.450228] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  309.452340] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  309.452379] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  309.454607] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  309.454643] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  309.456805] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  309.456841] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  309.459067] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  309.459103] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  309.461311] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  309.461347] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  309.463573] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  309.463608] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  309.481536] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  309.481571] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  309.483788] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  309.483824] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  309.486054] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  309.486090] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  309.488325] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  309.488361] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  309.490591] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  309.490627] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  309.492797] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  309.492834] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  309.495060] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  309.495097] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  309.497286] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  309.497321] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  309.514733] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  309.514767] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  309.515294] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  309.515330] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  309.517544] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  309.517580] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  309.519807] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  309.519843] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  309.522069] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  309.522105] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  309.524341] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  309.524378] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  309.526608] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  309.526644] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  309.528809] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  309.528845] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  309.531071] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  309.531107] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  309.548192] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  309.548228] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  309.549145] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  309.549181] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  309.551413] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  309.551449] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  309.553667] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  309.553704] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  309.555929] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  309.555965] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  309.558193] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  309.558229] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  309.560340] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  309.560379] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  309.562607] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  309.562643] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  309.581489] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  309.581524] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  309.582804] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  309.582840] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  309.584936] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  309.584973] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  309.587195] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  309.587230] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  309.589451] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  309.589487] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  309.591715] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  309.591751] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  309.593975] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  309.594011] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  309.596246] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  309.596283] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  309.614815] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  309.614851] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  309.616328] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  309.616364] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  309.618592] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  309.618628] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  309.620802] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  309.620838] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  309.623064] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  309.623101] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  309.625307] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  309.625343] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  309.627570] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  309.627607] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  309.629827] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  309.629863] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  309.648092] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  309.648127] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  309.650092] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  309.650128] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  309.652341] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  309.652380] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  309.654608] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  309.654644] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  309.656811] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  309.656848] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  309.659077] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  309.659113] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  309.661320] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  309.661356] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  309.663588] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  309.663624] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  309.681543] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  309.681578] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  309.683777] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  309.683814] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  309.686041] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  309.686077] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  309.688311] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  309.688348] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  309.690575] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  309.690611] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  309.692713] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  309.692749] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  309.694979] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  309.695014] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  309.697216] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  309.697253] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  309.714845] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  309.714879] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  309.715145] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  309.715178] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  309.717413] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  309.717449] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  309.719680] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  309.719716] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  309.721935] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  309.721971] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  309.724202] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  309.724238] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  309.726473] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  309.726509] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  309.728597] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  309.728633] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  309.730864] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  309.730901] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  309.748198] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  309.748233] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  309.748910] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  309.748945] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  309.751172] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  309.751208] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  309.753416] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  309.753452] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  309.755679] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  309.755713] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  309.757938] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  309.757974] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  309.760208] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  309.760245] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  309.762479] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  309.762515] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  309.764604] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  309.764640] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  309.781498] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  309.781533] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  309.782649] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  309.782684] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  309.784871] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  309.784908] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  309.787136] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  309.787171] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  309.789380] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  309.789416] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  309.791641] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  309.791677] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  309.793901] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  309.793936] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  309.796165] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  309.796215] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  309.814849] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  309.814885] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  309.816118] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  309.816160] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  309.818364] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  309.818400] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  309.820475] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  309.820511] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  309.822750] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  309.822786] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  309.824979] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  309.825015] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  309.827244] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  309.827280] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  309.829493] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  309.829529] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  309.848190] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  309.848224] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  309.849710] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  309.849746] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  309.851975] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  309.852050] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  309.854222] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  309.854257] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  309.856354] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  309.856390] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  309.858620] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  309.858656] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  309.860715] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  309.860752] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  309.862982] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  309.863018] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  309.881456] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  309.881491] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  309.883280] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  309.883316] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  309.885530] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  309.885565] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  309.887791] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  309.887827] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  309.890057] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  309.890093] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  309.892339] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  309.892376] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  309.894595] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  309.894631] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  309.896688] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  309.896723] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  309.914802] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  309.914837] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  309.916973] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  309.917009] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  309.919230] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  309.919266] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  309.921479] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  309.921514] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  309.923740] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  309.923776] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  309.926002] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  309.926039] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  309.928280] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  309.928317] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  309.930543] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  309.930578] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  309.948208] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  309.948243] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  309.948462] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  309.948496] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  309.950751] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  309.950786] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  309.952967] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  309.953004] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  309.955231] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  309.955268] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  309.957479] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  309.957516] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  309.959744] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  309.959779] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  309.962004] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  309.962040] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  309.964286] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  309.964324] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  309.981530] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  309.981564] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  309.982149] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  309.982186] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  309.984342] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  309.984379] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  309.986608] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  309.986644] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  309.988696] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  309.988733] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  309.990961] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  309.990997] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  309.993202] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  309.993238] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  309.995462] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  309.995498] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  309.997698] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  309.997734] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  310.014863] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  310.014897] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  310.015685] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  310.015718] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  310.017968] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  310.018003] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  310.020226] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  310.020263] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  310.022492] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  310.022527] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  310.024582] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  310.024618] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  310.026835] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  310.026870] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  310.029066] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  310.029103] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  310.048189] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  310.048223] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  310.049438] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  310.049474] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  310.051702] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  310.051738] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  310.053965] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  310.054000] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  310.056242] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  310.056279] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  310.058502] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  310.058538] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  310.060591] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  310.060628] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  310.062863] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  310.062899] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  310.081489] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  310.081522] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  310.083119] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  310.083155] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  310.085363] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  310.085398] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  310.087623] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  310.087659] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  310.089884] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  310.089920] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  310.092174] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  310.092223] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  310.094427] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  310.094463] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  310.096502] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  310.096536] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  310.114735] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  310.114769] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  310.116642] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  310.116677] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  310.118910] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  310.118944] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  310.121139] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  310.121176] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  310.123402] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  310.123438] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  310.125656] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  310.125692] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  310.127916] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  310.127952] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  310.130179] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  310.130216] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  310.148191] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  310.148226] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  310.150416] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  310.150451] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  310.152488] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  310.152538] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  310.154765] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  310.154801] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  310.156997] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  310.157032] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  310.159257] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  310.159293] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  310.161505] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  310.161541] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  310.163772] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  310.163808] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  310.181525] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  310.181560] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  310.181638] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  310.181663] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  310.183989] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  310.184073] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  310.186254] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  310.186290] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  310.188391] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  310.188428] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  310.190652] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  310.190688] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  310.192874] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  310.192910] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  310.195135] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  310.195172] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  310.197379] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  310.197415] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  310.214848] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  310.214883] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  310.215357] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  310.215390] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  310.217624] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  310.217660] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  310.219887] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  310.219923] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  310.222155] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  310.222191] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  310.224348] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  310.224386] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  310.226611] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  310.226647] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  310.228830] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  310.228866] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  310.231089] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  310.231126] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  310.248199] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  310.248234] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  310.249186] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  310.249222] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  310.251451] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  310.251487] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  310.253712] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  310.253748] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  310.255972] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  310.256008] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  310.258238] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  310.258274] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  310.260375] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  310.260411] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  310.262635] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  310.262672] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  310.281473] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  310.281508] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  310.282857] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  310.282894] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  310.285097] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  310.285132] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  310.287357] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  310.287394] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  310.289617] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  310.289654] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  310.291859] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  310.291895] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  310.294122] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  310.294158] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  310.296363] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  310.296399] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  310.314825] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  310.314859] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  310.316221] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  310.316256] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  310.318495] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  310.318531] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  310.320585] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  310.320621] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  310.322848] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  310.322884] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  310.325082] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  310.325119] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  310.327346] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  310.327383] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  310.329601] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  310.329637] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  310.348169] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  310.348204] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  310.349749] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  310.349785] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  310.352012] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  310.352092] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  310.354282] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  310.354317] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  310.356382] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  310.356432] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  310.358674] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  310.358710] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  310.360891] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  310.360928] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  310.363150] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  310.363185] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  310.381394] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  310.381429] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  310.383487] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  310.383524] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  310.385739] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  310.385775] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  310.388003] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  310.388091] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  310.390267] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  310.390302] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  310.392403] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  310.392439] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  310.394666] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  310.394702] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  310.396875] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  310.396912] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  310.414856] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  310.414891] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  310.417040] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  310.417076] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  310.419303] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  310.419339] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  310.421554] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  310.421590] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  310.423821] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  310.423857] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  310.426086] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  310.426122] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  310.428351] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  310.428388] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  310.430605] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  310.430642] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  310.448214] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  310.448249] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  310.448512] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  310.448545] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  310.450797] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  310.450833] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  310.453021] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  310.453057] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  310.455283] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  310.455320] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  310.457526] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  310.457562] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  310.459788] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  310.459823] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  310.462054] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  310.462091] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  310.464333] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  310.464369] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  310.481516] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  310.481550] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  310.482081] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  310.482118] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  310.484349] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  310.484386] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  310.486610] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  310.486647] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  310.488824] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  310.488860] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  310.491088] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  310.491124] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  310.493330] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  310.493366] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  310.495592] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  310.495629] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  310.497861] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  310.497899] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  310.514837] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  310.514873] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  310.515824] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  310.515857] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  310.518065] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  310.518102] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  310.520348] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  310.520385] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  310.522609] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  310.522645] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  310.524698] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  310.524734] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  310.526964] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  310.527001] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  310.529199] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  310.529236] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  310.548184] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  310.548220] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  310.549523] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  310.549559] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  310.551787] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  310.551823] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  310.554046] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  310.554082] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  310.556318] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  310.556357] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  310.558580] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  310.558616] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  310.560669] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  310.560705] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  310.562934] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  310.562970] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  310.581479] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  310.581514] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  310.583236] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  310.583272] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  310.585485] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  310.585521] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  310.587749] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  310.587785] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  310.590009] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  310.590045] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  310.592297] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  310.592334] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  310.594560] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  310.594596] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  310.596645] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  310.596682] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  310.614753] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  310.614788] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  310.616915] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  310.616951] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  310.619157] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  310.619193] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  310.621401] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  310.621437] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  310.623665] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  310.623700] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  310.625924] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  310.625962] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  310.628200] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  310.628236] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  310.630466] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  310.630503] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  310.648235] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  310.648270] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  310.650541] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  310.650577] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  310.652629] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  310.652664] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  310.654897] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  310.654934] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  310.657125] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  310.657161] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  310.659392] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  310.659428] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  310.661648] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  310.661685] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  310.663910] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  310.663946] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  310.681535] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  310.681571] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  310.681837] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  310.681871] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  310.684166] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  310.684211] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  310.686416] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  310.686451] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  310.688473] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  310.688509] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  310.690779] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  310.690815] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  310.693008] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  310.693045] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  310.695273] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  310.695309] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  310.697517] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  310.697554] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  310.714846] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  310.714881] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  310.715488] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  310.715522] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  310.717763] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  310.717799] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  310.720069] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  310.720128] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  310.722285] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  310.722320] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  310.724394] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  310.724445] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  310.726684] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  310.726721] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  310.728908] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  310.728944] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  310.731199] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  310.731236] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  310.748186] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  310.748221] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  310.749263] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  310.749299] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  310.751530] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  310.751566] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  310.753787] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  310.753823] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  310.756097] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  310.756151] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  310.758307] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  310.758343] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  310.760411] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  310.760459] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  310.762708] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  310.762744] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  310.781482] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  310.781518] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  310.782951] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  310.782986] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  310.785190] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  310.785226] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  310.787456] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  310.787492] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  310.789706] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  310.789742] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  310.791970] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  310.792006] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  310.794207] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  310.794243] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  310.796350] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  310.796387] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  310.814805] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  310.814840] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  310.816306] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  310.816340] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  310.818518] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  310.818553] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  310.820605] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  310.820641] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  310.822870] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  310.822906] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  310.825106] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  310.825142] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  310.827371] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  310.827407] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  310.829621] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  310.829658] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  310.848159] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  310.848193] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  310.849700] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  310.849736] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  310.851962] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  310.851998] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  310.854211] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  310.854247] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  310.856353] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  310.856390] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  310.858611] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  310.858648] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  310.860698] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  310.860735] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  310.862965] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  310.863001] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  310.881489] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  310.881524] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  310.883132] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  310.883168] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  310.885378] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  310.885414] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  310.887641] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  310.887676] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  310.889898] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  310.889935] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  310.892174] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  310.892219] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  310.894434] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  310.894470] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  310.896537] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  310.896574] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  310.914725] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  310.914759] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  310.916654] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  310.916690] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  310.918890] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  310.918926] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  310.921017] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  310.921054] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  310.923282] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  310.923318] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  310.925528] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  310.925563] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  310.927788] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  310.927824] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  310.930055] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  310.930091] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  310.948151] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  310.948186] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  310.950342] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  310.950378] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  310.952443] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  310.952494] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  310.954725] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  310.954761] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  310.956948] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  310.956984] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  310.959209] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  310.959245] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  310.961457] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  310.961493] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  310.963719] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  310.963755] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  310.981526] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  310.981561] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  310.983749] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  310.983785] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  310.986012] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  310.986048] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  310.988291] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  310.988329] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  310.990553] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  310.990590] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  310.992641] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  310.992677] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  310.994907] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  310.994942] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  310.997135] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  310.997172] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  311.014856] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  311.014890] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  311.015073] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  311.015107] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  311.017326] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  311.017362] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  311.019446] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  311.019481] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  311.021704] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  311.021740] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  311.023968] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  311.024004] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  311.026229] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  311.026265] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  311.028364] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  311.028401] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  311.030627] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  311.030663] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  311.048205] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  311.048242] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  311.048577] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  311.048613] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  311.050830] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  311.050866] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  311.053058] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  311.053094] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  311.055323] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  311.055360] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  311.057576] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  311.057612] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  311.059838] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  311.059873] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  311.062088] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  311.062124] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  311.064350] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  311.064387] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  311.081521] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  311.081556] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  311.082089] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  311.082125] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  311.084345] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  311.084382] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  311.086606] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  311.086641] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  311.088822] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  311.088858] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  311.091086] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  311.091123] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  311.093326] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  311.093362] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  311.095591] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  311.095627] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  311.097858] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  311.097895] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  311.114850] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  311.114884] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  311.115826] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  311.115860] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  311.118113] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  311.118149] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  311.120309] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  311.120346] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  311.122575] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  311.122612] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  311.124661] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  311.124697] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  311.126927] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  311.126963] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  311.129156] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  311.129193] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  311.148191] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  311.148226] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  311.149518] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  311.149554] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  311.151783] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  311.151819] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  311.154046] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  311.154082] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  311.156322] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  311.156359] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  311.158565] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  311.158601] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  311.160655] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  311.160691] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  311.162919] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  311.162956] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  311.181471] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  311.181507] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  311.183160] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  311.183196] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  311.185409] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  311.185445] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  311.187674] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  311.187709] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  311.189941] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  311.189978] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  311.192218] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  311.192255] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  311.194479] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  311.194515] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  311.196569] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  311.196605] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  311.214724] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  311.214759] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  311.216724] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  311.216759] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  311.218992] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  311.219028] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  311.221232] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  311.221268] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  311.223493] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  311.223529] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  311.225749] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  311.225785] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  311.228010] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  311.228096] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  311.230271] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  311.230307] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  311.248197] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  311.248232] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  311.250416] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  311.250451] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  311.252491] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  311.252542] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  311.254775] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  311.254812] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  311.257006] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  311.257042] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  311.259271] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  311.259307] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  311.261522] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  311.261557] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  311.263782] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  311.263818] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  311.281537] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  311.281572] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  311.281650] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  311.281674] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  311.283994] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  311.284079] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  311.286245] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  311.286282] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  311.288381] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  311.288418] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  311.290647] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  311.290683] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  311.292863] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  311.292900] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  311.295125] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  311.295161] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  311.297368] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  311.297403] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  311.314856] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  311.314891] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  311.315090] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  311.315123] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  311.317358] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  311.317394] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  311.319619] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  311.319655] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  311.321879] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  311.321914] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  311.324176] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  311.324222] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  311.326421] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  311.326457] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  311.328489] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  311.328524] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  311.330784] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  311.330820] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  311.348211] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  311.348245] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  311.348772] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  311.348807] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  311.351030] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  311.351065] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  311.353270] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  311.353306] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  311.355532] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  311.355568] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  311.357790] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  311.357826] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  311.360105] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  311.360153] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  311.362317] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  311.362353] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  311.364419] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  311.364467] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  311.381505] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  311.381540] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  311.382442] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  311.382477] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  311.384508] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  311.384544] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  311.386806] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  311.386842] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  311.389036] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  311.389072] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  311.391297] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  311.391332] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  311.393542] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  311.393578] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  311.395803] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  311.395838] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  311.414827] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  311.414861] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  311.416103] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  311.416151] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  311.418344] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  311.418380] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  311.420439] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  311.420475] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  311.422736] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  311.422773] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  311.424950] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  311.424986] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  311.427214] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  311.427250] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  311.429463] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  311.429500] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  311.448184] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  311.448218] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  311.449647] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  311.449683] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  311.451917] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  311.451953] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  311.454175] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  311.454212] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  311.456346] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  311.456384] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  311.458610] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  311.458646] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  311.460696] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  311.460732] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  311.462961] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  311.462998] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  311.481470] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  311.481505] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  311.483293] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  311.483330] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  311.485524] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  311.485561] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  311.487787] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  311.487822] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  311.490050] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  311.490086] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  311.492327] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  311.492365] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  311.494591] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  311.494628] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  311.496681] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  311.496716] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  311.514793] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  311.514829] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  311.516957] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  311.516993] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  311.519218] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  311.519254] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  311.521467] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  311.521503] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  311.523727] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  311.523764] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  311.525989] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  311.526025] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  311.528267] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  311.528305] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  311.530526] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  311.530562] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  311.548209] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  311.548246] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  311.548324] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  311.548349] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  311.550607] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  311.550642] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  311.552701] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  311.552737] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  311.554958] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  311.554994] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  311.557198] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  311.557234] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  311.559466] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  311.559502] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  311.561680] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  311.561716] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  311.563941] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  311.563977] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  311.581529] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  311.581563] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  311.581851] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  311.581884] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  311.584146] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  311.584191] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  311.586364] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  311.586399] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  311.588440] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  311.588475] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  311.590730] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  311.590766] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  311.592956] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  311.592992] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  311.595224] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  311.595260] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  311.597479] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  311.597515] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  311.631580] [drm:drm_mode_addfb2 [drm]] [FB:72]
>[  311.631628] [drm:drm_mode_addfb2 [drm]] [FB:73]
>[  311.658812] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  311.658845] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  311.658859] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[  311.658886] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  311.667039] [drm:intel_power_well_disable [i915]] disabling DDI B IO power well
>[  311.667112] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  311.667179] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 37
>[  311.667241] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  311.667320] [drm:intel_atomic_commit_tail [i915]] [ENCODER:48:DDI A]
>[  311.667378] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI B]
>[  311.667437] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  311.667492] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  311.667544] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DDI C]
>[  311.667596] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST A]
>[  311.667648] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST B]
>[  311.667698] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI D]
>[  311.667748] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[  311.667798] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[  311.667854] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:57:DP-1]
>[  311.667909] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[  311.667965] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[  311.668018] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[  311.668122] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[  311.668207] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  311.668289] [drm:intel_atomic_commit_tail [i915]] [CRTC:37:pipe A]
>[  311.668366] [drm:intel_power_well_disable [i915]] disabling DC off
>[  311.668430] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  311.668498] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  311.668956] [drm:intel_power_well_disable [i915]] disabling always-on
>[  311.669024] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  311.669116] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  311.669149] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  311.669256] [drm:intel_atomic_check [i915]] [CONNECTOR:57:DP-1] checking for sink bpp constrains
>[  311.669326] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  311.669409] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 148500KHz
>[  311.669482] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  311.669558] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 648000
>[  311.669629] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  311.669706] [drm:intel_dump_pipe_config [i915]] [CRTC:47:pipe B][modeset]
>[  311.669773] [drm:intel_dump_pipe_config [i915]] output_types: DP (0x80)
>[  311.669847] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  311.669911] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5767168, gmch_n: 8388608, link_m: 240298, link_n: 262144, tu: 64
>[  311.669983] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  311.670043] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  311.670084] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  311.670145] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  311.670178] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  311.670252] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  311.670317] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1080, pixel rate 148500
>[  311.670388] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  311.670448] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  311.670516] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  311.670576] [drm:intel_dump_pipe_config [i915]] dpll_hw_state: ctrl1: 0x3, cfgcr1: 0x0, cfgcr2: 0x0
>[  311.670643] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  311.670704] [drm:intel_dump_pipe_config [i915]] [PLANE:38:plane 1B] disabled, scaler_id = -1
>[  311.670773] [drm:intel_dump_pipe_config [i915]] [PLANE:41:plane 2B] disabled, scaler_id = -1
>[  311.670833] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor B] disabled, scaler_id = -1
>[  311.670912] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  311.670978] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[  311.671063] [drm:intel_find_shared_dpll [i915]] [CRTC:47:pipe B] allocated DPLL 1
>[  311.671131] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[  311.672586] [drm:intel_power_well_enable [i915]] enabling always-on
>[  311.672596] [drm:intel_power_well_enable [i915]] enabling DC off
>[  311.672854] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  311.672867] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  311.672886] [drm:intel_atomic_commit_tail [i915]] [ENCODER:48:DDI A]
>[  311.672900] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI B]
>[  311.672914] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  311.672928] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  311.672940] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DDI C]
>[  311.672951] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST A]
>[  311.672961] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST B]
>[  311.672972] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI D]
>[  311.672982] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[  311.672992] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[  311.673004] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[  311.673016] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[  311.673028] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[  311.673039] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[  311.673052] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 2, on? 0) for crtc 47
>[  311.673064] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  311.673149] [drm:intel_power_well_enable [i915]] enabling DDI B IO power well
>[  311.673709] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  311.675017] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  311.676323] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  311.677615] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  311.678922] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  311.679828] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  311.680745] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  311.680757] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  311.680769] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  311.680781] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  311.699584] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  311.699598] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  311.718386] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  311.718709] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:57:DP-1] Link Training Passed at Link Rate = 162000, Lane count = 4
>[  311.719079] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  311.719109] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS
>[  311.735943] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:57:DP-1]
>[  311.735961] [drm:intel_atomic_commit_tail [i915]] [CRTC:47:pipe B]
>[  311.735984] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[  311.752600] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  311.752608] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  311.754906] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  311.754915] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  311.757175] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  311.757184] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  311.759493] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  311.759503] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  311.761765] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  311.761775] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  311.764078] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  311.764089] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  311.766326] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  311.766337] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  311.768492] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  311.768502] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  311.786064] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  311.786080] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  311.786542] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  311.786558] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  311.788747] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  311.788764] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  311.791030] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  311.791050] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  311.793257] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  311.793276] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  311.795534] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  311.795558] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  311.797778] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  311.797801] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  311.799903] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  311.799926] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  311.802193] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  311.802223] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  311.819498] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  311.819532] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  311.819922] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  311.819955] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  311.822167] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  311.822203] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  311.824346] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  311.824383] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  311.826597] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  311.826634] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  311.828819] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  311.828856] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  311.831082] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  311.831118] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  311.833327] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  311.833365] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  311.835590] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  311.835625] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  311.852770] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  311.852804] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  311.853668] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  311.853704] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  311.855933] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  311.855970] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  311.858201] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  311.858236] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  311.860349] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  311.860386] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  311.862621] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  311.862657] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  311.864847] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  311.864884] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  311.867101] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  311.867137] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  311.886137] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  311.886171] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  311.887302] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  311.887338] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  311.889553] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  311.889590] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  311.891817] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  311.891853] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  311.894078] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  311.894114] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  311.896348] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  311.896386] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  311.898609] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  311.898646] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  311.900826] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  311.900863] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  311.919471] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  311.919507] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  311.921020] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  311.921056] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  311.923256] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  311.923292] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  311.925501] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  311.925537] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  311.927768] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  311.927804] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  311.930013] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  311.930049] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  311.932291] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  311.932328] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  311.934554] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  311.934590] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  311.952694] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  311.952729] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  311.954827] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  311.954864] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  311.957059] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  311.957095] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  311.959320] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  311.959355] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  311.961566] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  311.961602] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  311.963829] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  311.963865] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  311.966095] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  311.966131] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  311.968351] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  311.968389] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  311.986171] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  311.986205] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  311.988352] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  311.988389] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  311.990614] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  311.990649] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  311.992813] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  311.992850] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  311.995076] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  311.995112] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  311.997319] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  311.997355] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  311.999581] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  311.999617] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  312.001839] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  312.001875] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  312.019501] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  312.019536] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  312.019617] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  312.019642] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  312.021956] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  312.021993] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  312.024233] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  312.024271] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  312.026496] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  312.026532] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  312.028629] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  312.028666] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  312.030890] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  312.030927] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  312.033128] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  312.033165] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  312.035389] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  312.035425] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  312.052824] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  312.052860] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  312.053456] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  312.053492] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  312.055719] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  312.055755] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  312.057981] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  312.058017] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  312.060259] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  312.060296] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  312.062518] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  312.062555] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  312.064644] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  312.064681] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  312.066913] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  312.066949] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  312.069162] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  312.069199] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  312.086154] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  312.086190] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  312.087082] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  312.087118] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  312.089183] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  312.089216] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  312.091472] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  312.091507] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  312.093722] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  312.093759] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  312.095984] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  312.096060] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  312.098243] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  312.098280] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  312.100373] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  312.100413] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  312.119472] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  312.119507] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  312.120597] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  312.120634] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  312.122731] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  312.122767] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  312.124945] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  312.124981] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  312.127205] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  312.127240] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  312.129456] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  312.129492] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  312.131720] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  312.131756] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  312.133979] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  312.134015] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  312.152802] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  312.152837] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  312.154228] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  312.154264] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  312.156365] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  312.156401] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  312.158629] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  312.158666] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  312.160842] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  312.160878] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  312.163103] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  312.163139] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  312.165345] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  312.165381] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  312.167608] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  312.167645] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  312.186118] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  312.186153] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  312.187921] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  312.187957] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  312.190185] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  312.190220] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  312.192341] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  312.192378] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  312.194610] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  312.194646] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  312.196819] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  312.196855] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  312.199078] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  312.199115] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  312.201321] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  312.201357] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  312.219440] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  312.219475] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  312.221636] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  312.221673] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  312.223877] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  312.223914] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  312.226144] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  312.226179] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  312.228345] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  312.228382] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  312.230620] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  312.230656] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  312.232825] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  312.232861] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  312.235088] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  312.235124] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  312.252835] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  312.252872] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  312.253046] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  312.253080] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  312.255334] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  312.255370] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  312.257582] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  312.257618] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  312.259842] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  312.259878] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  312.262111] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  312.262147] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  312.264343] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  312.264380] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  312.266608] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  312.266644] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  312.268819] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  312.268855] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  312.286167] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  312.286202] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  312.286797] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  312.286832] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  312.289025] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  312.289061] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  312.291288] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  312.291324] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  312.293534] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  312.293570] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  312.295798] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  312.295834] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  312.298059] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  312.298096] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  312.300203] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  312.300239] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  312.302477] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  312.302513] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  312.319492] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  312.319529] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  312.320215] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  312.320252] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  312.322510] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  312.322547] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  312.324628] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  312.324664] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  312.326896] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  312.326932] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  312.329131] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  312.329167] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  312.331393] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  312.331429] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  312.333649] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  312.333686] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  312.335913] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  312.335948] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  312.352786] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  312.352820] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  312.353946] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  312.353981] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  312.356247] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  312.356283] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  312.358499] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  312.358535] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  312.360586] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  312.360623] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  312.362854] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  312.362890] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  312.365088] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  312.365125] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  312.367352] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  312.367388] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  312.386131] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  312.386166] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  312.387572] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  312.387608] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  312.389833] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  312.389870] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  312.392128] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  312.392167] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  312.394360] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  312.394396] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  312.396459] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  312.396495] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  312.398719] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  312.398755] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  312.400807] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  312.400843] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  312.419464] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  312.419497] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  312.420990] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  312.421026] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  312.423252] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  312.423287] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  312.425497] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  312.425533] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  312.427758] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  312.427794] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  312.430018] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  312.430055] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  312.432300] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  312.432338] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  312.434560] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  312.434596] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  312.452706] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  312.452741] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  312.454919] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  312.454955] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  312.457157] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  312.457193] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  312.459419] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  312.459455] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  312.461671] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  312.461707] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  312.463932] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  312.463968] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  312.466197] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  312.466232] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  312.468361] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  312.468399] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  312.486188] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  312.486223] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  312.488351] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  312.488390] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  312.490609] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  312.490645] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  312.492695] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  312.492731] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  312.494962] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  312.494998] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  312.497198] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  312.497235] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  312.499461] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  312.499497] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  312.501715] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  312.501752] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  312.519502] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  312.519538] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  312.519623] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  312.519648] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  312.521930] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  312.521965] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  312.524155] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  312.524192] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  312.526420] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  312.526456] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  312.528522] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  312.528557] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  312.530784] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  312.530820] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  312.532883] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  312.532919] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  312.535144] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  312.535180] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  312.552829] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  312.552864] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  312.553082] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  312.553116] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  312.555373] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  312.555409] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  312.557618] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  312.557654] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  312.559884] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  312.559920] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  312.562150] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  312.562187] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  312.564353] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  312.564391] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  312.566614] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  312.566650] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  312.568703] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  312.568740] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  312.586128] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  312.586163] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  312.586712] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  312.586749] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  312.588931] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  312.588967] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  312.591196] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  312.591233] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  312.593447] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  312.593482] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  312.595705] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  312.595741] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  312.597963] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  312.597999] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  312.600246] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  312.600283] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  312.602511] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  312.602547] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  312.619483] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  312.619517] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  312.620240] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  312.620275] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  312.622553] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  312.622589] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  312.624765] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  312.624800] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  312.627028] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  312.627064] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  312.629268] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  312.629304] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  312.631531] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  312.631566] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  312.633787] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  312.633823] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  312.652807] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  312.652841] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  312.654167] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  312.654203] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  312.656355] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  312.656391] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  312.658612] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  312.658647] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  312.660705] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  312.660741] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  312.662966] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  312.663002] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  312.665204] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  312.665240] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  312.667469] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  312.667506] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  312.686126] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  312.686161] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  312.687682] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  312.687718] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  312.689941] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  312.689978] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  312.692226] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  312.692263] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  312.694485] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  312.694522] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  312.696571] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  312.696607] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  312.698837] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  312.698873] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  312.701067] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  312.701104] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  312.719426] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  312.719460] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  312.721334] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  312.721370] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  312.723597] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  312.723634] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  312.725854] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  312.725890] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  312.728148] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  312.728188] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  312.730379] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  312.730416] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  312.732477] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  312.732513] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  312.734751] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  312.734786] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  312.752839] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  312.752874] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  312.755045] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  312.755081] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  312.757292] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  312.757328] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  312.759559] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  312.759596] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  312.761816] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  312.761852] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  312.764119] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  312.764159] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  312.766342] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  312.766378] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  312.768441] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  312.768477] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  312.786167] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  312.786203] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  312.786278] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  312.786303] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  312.788405] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  312.788441] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  312.790658] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  312.790694] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  312.792873] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  312.792910] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  312.795143] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  312.795179] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  312.797385] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  312.797422] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  312.799656] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  312.799691] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  312.801903] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  312.801939] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  312.819497] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  312.819531] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  312.819715] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  312.819747] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  312.821998] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  312.822034] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  312.824288] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  312.824325] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  312.826547] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  312.826583] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  312.828634] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  312.828671] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  312.830904] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  312.830940] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  312.833130] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  312.833166] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  312.835394] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  312.835430] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  312.852832] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  312.852868] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  312.853415] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  312.853452] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  312.855680] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  312.855716] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  312.857939] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  312.857975] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  312.860223] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  312.860258] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  312.862479] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  312.862515] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  312.864568] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  312.864605] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  312.866837] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  312.866874] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  312.869066] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  312.869102] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  312.886148] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  312.886184] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  312.887090] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  312.887126] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  312.889332] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  312.889368] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  312.891592] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  312.891628] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  312.893850] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  312.893887] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  312.896143] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  312.896182] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  312.898375] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  312.898411] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  312.900475] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  312.900510] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  312.919468] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  312.919503] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  312.920511] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  312.920545] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  312.922793] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  312.922830] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  312.924860] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  312.924894] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  312.927153] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  312.927189] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  312.929397] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  312.929434] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  312.931663] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  312.931699] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  312.933918] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  312.933954] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  312.952805] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  312.952840] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  312.954239] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  312.954275] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  312.956379] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  312.956416] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  312.958635] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  312.958671] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  312.960724] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  312.960760] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  312.962992] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  312.963028] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  312.965232] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  312.965268] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  312.967496] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  312.967531] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  312.986119] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  312.986154] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  312.987711] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  312.987747] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  312.989974] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  312.990010] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  312.992262] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  312.992298] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  312.994522] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  312.994557] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  312.996607] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  312.996643] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  312.998871] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  312.998907] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  313.001093] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  313.001129] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  313.019379] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  313.019415] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  313.021395] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  313.021431] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  313.023653] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  313.023687] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  313.025880] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  313.025916] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  313.028157] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  313.028193] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  313.030425] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  313.030460] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  313.032521] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  313.032557] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  313.034789] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  313.034824] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  313.052837] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  313.052871] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  313.055056] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  313.055092] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  313.057293] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  313.057329] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  313.059554] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  313.059590] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  313.061809] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  313.061845] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  313.064115] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  313.064154] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  313.066326] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  313.066362] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  313.068387] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  313.068423] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  313.086164] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  313.086199] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  313.086277] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  313.086302] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  313.088438] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  313.088474] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  313.090690] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  313.090725] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  313.092910] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  313.092947] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  313.095172] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  313.095208] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  313.097423] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  313.097459] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  313.099685] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  313.099721] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  313.101941] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  313.101977] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  313.119504] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  313.119538] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  313.119906] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  313.119939] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  313.122193] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  313.122229] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  313.124353] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  313.124392] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  313.126588] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  313.126624] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  313.128677] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  313.128713] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  313.130944] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  313.130979] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  313.133175] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  313.133212] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  313.135441] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  313.135477] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  313.152822] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  313.152857] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  313.153506] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  313.153541] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  313.155771] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  313.155806] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  313.158031] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  313.158067] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  313.160315] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  313.160352] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  313.162578] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  313.162614] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  313.164661] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  313.164696] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  313.166933] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  313.166970] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  313.169185] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  313.169222] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  313.186144] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  313.186179] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  313.187244] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  313.187280] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  313.189483] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  313.189518] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  313.191745] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  313.191781] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  313.194012] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  313.194048] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  313.196293] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  313.196330] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  313.198550] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  313.198586] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  313.200638] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  313.200675] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  313.219483] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  313.219517] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  313.220806] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  313.220842] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  313.223066] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  313.223103] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  313.225311] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  313.225346] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  313.227568] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  313.227604] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  313.229828] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  313.229865] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  313.232124] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  313.232164] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  313.234355] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  313.234392] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  313.252808] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  313.252843] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  313.254571] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  313.254608] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  313.256660] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  313.256697] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  313.258927] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  313.258963] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  313.261159] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  313.261196] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  313.263420] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  313.263456] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  313.265671] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  313.265707] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  313.267934] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  313.267970] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  313.286037] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  313.286071] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  313.288264] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  313.288303] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  313.290523] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  313.290560] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  313.292611] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  313.292647] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  313.294879] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  313.294916] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  313.297092] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  313.297128] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  313.299353] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  313.299388] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  313.301611] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  313.301647] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  313.319497] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  313.319533] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  313.321705] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  313.321742] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  313.323966] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  313.324001] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  313.326230] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  313.326266] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  313.328366] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  313.328403] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  313.330625] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  313.330661] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  313.332718] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  313.332755] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  313.334983] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  313.335019] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  313.352772] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  313.352807] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  313.355006] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  313.355041] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  313.357243] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  313.357280] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  313.359505] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  313.359541] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  313.361763] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  313.361799] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  313.364058] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  313.364100] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  313.366292] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  313.366328] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  313.368398] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  313.368435] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  313.386167] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  313.386204] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  313.386280] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  313.386305] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  313.388398] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  313.388433] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  313.390655] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  313.390691] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  313.392875] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  313.392912] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  313.395136] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  313.395171] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  313.397378] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  313.397413] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  313.399640] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  313.399676] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  313.401903] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  313.401940] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  313.419492] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  313.419527] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  313.419873] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  313.419907] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  313.422168] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  313.422203] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  313.424355] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  313.424392] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  313.426606] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  313.426642] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  313.428699] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  313.428735] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  313.430962] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  313.430999] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  313.433201] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  313.433236] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  313.435463] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  313.435500] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  313.452826] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  313.452860] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  313.453524] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  313.453560] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  313.455786] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  313.455822] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  313.458051] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  313.458088] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  313.460327] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  313.460365] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  313.462587] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  313.462623] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  313.464674] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  313.464710] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  313.466941] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  313.466978] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  313.469071] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  313.469105] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  313.486151] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  313.486186] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  313.487077] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  313.487112] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  313.489321] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  313.489357] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  313.491584] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  313.491620] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  313.493842] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  313.493878] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  313.496141] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  313.496181] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  313.498380] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  313.498416] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  313.500480] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  313.500515] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  313.519473] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  313.519507] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  313.520775] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  313.520812] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  313.523035] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  313.523071] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  313.525281] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  313.525317] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  313.527495] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  313.527531] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  313.529740] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  313.529777] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  313.532007] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  313.532084] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  313.534271] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  313.534306] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  313.552791] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  313.552826] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  313.554487] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  313.554523] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  313.556585] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  313.556620] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  313.558848] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  313.558885] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  313.561086] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  313.561121] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  313.563344] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  313.563381] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  313.565597] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  313.565634] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  313.567859] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  313.567894] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  313.586033] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  313.586067] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  313.588229] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  313.588266] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  313.590489] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  313.590526] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  313.592578] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  313.592614] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  313.594844] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  313.594880] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  313.597077] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  313.597113] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  313.599340] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  313.599376] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  313.601592] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  313.601629] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  313.619516] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  313.619550] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  313.621770] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  313.621806] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  313.624071] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  313.624113] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  313.626292] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  313.626329] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  313.628365] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  313.628403] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  313.630658] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  313.630693] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  313.632744] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  313.632781] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  313.635009] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  313.635045] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  313.652840] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  313.652878] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  313.652952] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  313.652977] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  313.655239] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  313.655274] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  313.657485] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  313.657521] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  313.659745] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  313.659781] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  313.662005] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  313.662041] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  313.664290] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  313.664328] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  313.666548] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  313.666585] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  313.668637] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  313.668673] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  313.686149] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  313.686183] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  313.686633] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  313.686668] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  313.688722] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  313.688757] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  313.690989] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  313.691025] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  313.693229] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  313.693265] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  313.695495] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  313.695531] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  313.697756] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  313.697792] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  313.699841] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  313.699873] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  313.702127] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  313.702163] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  313.719500] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  313.719535] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  313.719954] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  313.719988] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  313.722239] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  313.722274] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  313.724379] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  313.724416] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  313.726638] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  313.726674] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  313.728851] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  313.728887] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  313.731111] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  313.731147] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  313.733353] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  313.733389] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  313.735612] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  313.735649] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  313.752822] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  313.752858] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  313.753556] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  313.753591] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  313.755818] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  313.755855] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  313.758082] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  313.758119] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  313.760348] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  313.760385] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  313.762603] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  313.762640] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  313.764803] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  313.764840] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  313.767065] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  313.767101] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  313.786142] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  313.786179] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  313.787438] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  313.787474] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  313.789693] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  313.789729] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  313.791956] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  313.791993] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  313.794219] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  313.794254] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  313.796353] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  313.796390] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  313.798621] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  313.798657] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  313.800830] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  313.800866] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  313.819472] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  313.819506] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  313.820744] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  313.820780] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  313.823006] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  313.823040] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  313.825248] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  313.825285] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  313.827511] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  313.827547] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  313.829721] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  313.829758] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  313.831977] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  313.832053] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  313.834237] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  313.834274] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  313.852800] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  313.852836] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  313.854346] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  313.854382] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  313.856463] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  313.856500] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  313.858731] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  313.858766] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  313.860961] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  313.860996] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  313.863225] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  313.863261] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  313.865426] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  313.865462] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  313.867688] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  313.867724] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  313.886087] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  313.886121] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  313.887885] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  313.887921] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  313.890152] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  313.890188] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  313.892342] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  313.892379] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  313.894609] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  313.894646] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  313.896696] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  313.896733] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  313.898959] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  313.898995] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  313.901196] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  313.901233] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  313.919367] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  313.919402] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  313.921496] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  313.921533] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  313.923756] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  313.923793] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  313.926018] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  313.926054] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  313.928294] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  313.928331] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  313.930561] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  313.930597] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  313.932650] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  313.932686] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  313.934913] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  313.934950] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  313.952856] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  313.952891] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  313.955137] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  313.955173] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  313.957382] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  313.957419] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  313.959645] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  313.959682] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  313.961910] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  313.961946] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  313.964195] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  313.964232] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  313.966455] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  313.966492] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  313.968555] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  313.968591] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  313.986107] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  313.986141] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  313.986434] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  313.986468] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  313.988548] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  313.988584] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  313.990821] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  313.990857] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  313.993049] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  313.993085] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  313.995311] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  313.995346] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  313.997561] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  313.997598] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  313.999829] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  313.999865] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  314.002081] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  314.002117] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  314.019497] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  314.019532] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  314.020091] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  314.020126] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  314.022341] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  314.022377] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  314.024451] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  314.024487] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  314.026715] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  314.026751] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  314.028930] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  314.028965] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  314.031200] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  314.031236] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  314.033449] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  314.033485] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  314.035711] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  314.035747] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  314.052809] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  314.052843] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  314.053807] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  314.053842] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  314.056112] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  314.056157] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  314.058337] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  314.058374] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  314.060454] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  314.060490] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  314.062718] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  314.062754] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  314.064943] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  314.064980] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  314.067207] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  314.067243] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  314.086139] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  314.086174] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  314.087532] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  314.087569] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  314.089788] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  314.089824] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  314.092084] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  314.092127] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  314.094308] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  314.094344] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  314.096437] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  314.096473] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  314.098699] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  314.098735] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  314.100907] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  314.100943] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  314.119455] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  314.119489] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  314.121102] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  314.121137] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  314.123363] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  314.123399] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  314.125614] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  314.125651] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  314.127881] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  314.127917] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  314.130136] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  314.130172] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  314.132341] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  314.132378] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  314.134609] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  314.134645] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  314.152743] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  314.152779] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  314.154950] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  314.154986] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  314.157187] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  314.157223] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  314.159451] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  314.159486] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  314.161707] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  314.161744] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  314.163976] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  314.164051] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  314.166239] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  314.166275] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  314.168369] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  314.168404] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  314.186179] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  314.186213] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  314.188335] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  314.188372] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  314.190603] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  314.190639] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  314.192693] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  314.192728] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  314.194958] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  314.194994] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  314.197195] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  314.197232] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  314.199460] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  314.199496] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  314.201713] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  314.201750] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  314.219514] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  314.219550] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  314.221830] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  314.221866] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  314.224127] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  314.224167] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  314.226355] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  314.226391] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  314.228453] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  314.228489] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  314.230711] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  314.230748] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  314.232927] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  314.232962] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  314.235189] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  314.235224] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  314.252844] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  314.252879] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  314.253116] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  314.253150] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  314.255410] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  314.255445] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  314.257656] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  314.257692] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  314.259919] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  314.259954] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  314.262185] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  314.262220] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  314.264342] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  314.264379] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  314.266610] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  314.266646] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  314.268699] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  314.268735] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  314.286157] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  314.286192] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  314.286720] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  314.286756] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  314.288941] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  314.288978] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  314.291203] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  314.291239] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  314.293447] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  314.293483] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  314.295710] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  314.295746] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  314.297970] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  314.298007] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  314.300132] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  314.300173] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  314.302244] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  314.302280] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  314.319498] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  314.319533] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  314.319970] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  314.320003] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  314.322256] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  314.322291] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  314.324386] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  314.324423] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  314.326655] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  314.326691] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  314.328879] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  314.328915] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  314.331135] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  314.331171] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  314.333384] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  314.333422] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  314.335646] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  314.335683] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  314.352784] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  314.352820] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  314.353640] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  314.353676] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  314.355904] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  314.355940] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  314.358168] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  314.358205] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  314.360360] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  314.360397] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  314.362619] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  314.362655] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  314.364717] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  314.364753] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  314.366971] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  314.367006] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  314.369226] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  314.369262] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  314.386143] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  314.386178] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  314.387243] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  314.387280] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  314.389488] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  314.389524] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  314.391749] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  314.391785] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  314.394012] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  314.394049] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  314.396285] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  314.396322] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  314.398557] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  314.398593] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  314.400644] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  314.400680] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  314.419478] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  314.419512] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  314.420839] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  314.420876] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  314.423098] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  314.423134] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  314.425347] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  314.425382] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  314.427607] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  314.427643] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  314.429828] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  314.429865] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  314.432125] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  314.432165] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  314.434351] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  314.434387] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  314.452784] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  314.452818] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  314.454577] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  314.454613] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  314.456671] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  314.456707] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  314.458934] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  314.458969] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  314.461180] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  314.461216] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  314.463445] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  314.463480] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  314.465694] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  314.465730] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  314.467962] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  314.467998] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  314.486035] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  314.486070] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  314.488160] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  314.488201] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  314.490431] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  314.490467] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  314.492528] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  314.492565] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  314.494793] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  314.494829] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  314.497027] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  314.497063] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  314.499289] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  314.499325] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  314.501535] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  314.501571] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  314.519507] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  314.519542] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  314.521716] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  314.521753] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  314.523977] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  314.524053] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  314.526239] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  314.526276] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  314.528374] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  314.528412] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  314.530576] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  314.530611] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  314.532662] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  314.532698] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  314.534929] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  314.534965] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  314.552858] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  314.552894] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  314.555154] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  314.555190] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  314.557401] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  314.557436] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  314.559662] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  314.559698] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  314.561923] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  314.561959] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  314.564204] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  314.564241] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  314.566456] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  314.566493] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  314.568554] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  314.568589] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  314.586166] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  314.586201] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  314.586452] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  314.586486] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  314.588563] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  314.588599] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  314.590822] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  314.590858] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  314.593060] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  314.593096] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  314.595321] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  314.595358] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  314.597575] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  314.597610] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  314.599835] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  314.599871] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  314.602099] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  314.602136] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  314.619494] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  314.619529] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  314.620090] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  314.620128] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  314.622343] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  314.622379] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  314.624455] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  314.624490] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  314.626715] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  314.626752] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  314.628946] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  314.628983] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  314.631160] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  314.631195] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  314.633407] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  314.633442] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  314.635666] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  314.635702] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  314.652820] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  314.652855] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  314.653749] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  314.653785] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  314.656018] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  314.656099] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  314.658284] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  314.658320] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  314.660388] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  314.660427] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  314.662679] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  314.662715] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  314.664893] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  314.664930] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  314.667156] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  314.667192] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  314.686134] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  314.686169] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  314.687504] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  314.687540] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  314.689757] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  314.689793] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  314.692059] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  314.692103] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  314.694281] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  314.694317] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  314.696387] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  314.696423] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  314.698680] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  314.698716] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  314.700893] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  314.700929] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  314.719454] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  314.719489] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  314.721084] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  314.721119] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  314.723345] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  314.723381] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  314.725596] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  314.725632] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  314.727862] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  314.727898] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  314.730128] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  314.730164] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  314.732332] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  314.732368] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  314.734598] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  314.734634] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  314.752730] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  314.752765] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  314.754943] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  314.754979] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  314.757164] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  314.757200] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  314.759428] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  314.759464] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  314.761568] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  314.761603] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  314.763831] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  314.763867] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  314.766098] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  314.766134] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  314.768345] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  314.768381] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  314.786170] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  314.786205] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  314.788331] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  314.788368] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  314.790588] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  314.790623] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  314.792672] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  314.792708] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  314.794941] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  314.794977] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  314.797176] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  314.797213] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  314.799440] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  314.799476] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  314.801687] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  314.801724] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  314.819502] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  314.819539] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  314.819614] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  314.819639] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  314.821905] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  314.821941] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  314.824173] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  314.824226] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  314.826443] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  314.826480] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  314.828525] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  314.828562] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  314.830775] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  314.830811] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  314.832991] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  314.833028] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  314.835251] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  314.835287] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  314.852831] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  314.852866] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  314.853139] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  314.853171] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  314.855430] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  314.855467] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  314.857686] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  314.857723] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  314.859949] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  314.859985] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  314.862223] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  314.862259] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  314.864359] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  314.864395] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  314.866620] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  314.866655] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  314.868705] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  314.868742] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  314.886176] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  314.886210] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  314.886697] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  314.886732] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  314.888920] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  314.888956] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  314.891183] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  314.891218] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  314.893427] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  314.893464] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  314.895687] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  314.895723] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  314.897947] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  314.897983] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  314.900216] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  314.900254] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  314.902494] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  314.902531] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  314.919489] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  314.919524] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  314.920252] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  314.920287] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  314.922556] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  314.922591] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  314.924644] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  314.924679] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  314.926907] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  314.926942] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  314.929141] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  314.929177] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  314.931413] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  314.931450] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  314.933663] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  314.933698] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  314.935932] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  314.935967] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  314.952808] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  314.952842] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  314.954041] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  314.954077] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  314.956314] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  314.956351] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  314.958582] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  314.958618] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  314.960670] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  314.960706] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  314.962937] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  314.962973] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  314.965171] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  314.965207] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  314.967433] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  314.967469] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  314.986141] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  314.986175] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  314.987669] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  314.987706] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  314.989888] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  314.989925] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  314.992159] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  314.992199] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  314.994418] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  314.994455] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  314.996515] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  314.996551] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  314.998784] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  314.998821] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  315.001015] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  315.001051] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  315.019458] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  315.019492] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  315.021283] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  315.021319] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  315.023543] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  315.023580] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  315.025797] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  315.025833] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  315.028096] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  315.028138] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  315.030317] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  315.030353] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  315.032416] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  315.032452] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  315.034680] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  315.034716] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  315.052814] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  315.052848] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  315.055025] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  315.055062] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  315.057268] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  315.057305] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  315.059534] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  315.059570] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  315.061789] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  315.061825] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  315.064084] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  315.064127] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  315.066306] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  315.066342] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  315.068436] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  315.068473] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  315.086176] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  315.086211] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  315.086288] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  315.086312] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  315.088458] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  315.088495] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  315.090696] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  315.090732] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  315.092912] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  315.092949] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  315.095176] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  315.095212] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  315.097404] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  315.097441] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  315.099664] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  315.099699] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  315.101922] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  315.101958] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  315.119502] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  315.119537] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  315.119884] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  315.119917] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  315.122166] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  315.122202] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  315.124340] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  315.124376] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  315.126607] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  315.126643] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  315.128702] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  315.128738] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  315.130958] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  315.130994] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  315.133200] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  315.133236] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  315.135462] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  315.135498] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  315.152827] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  315.152862] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  315.153509] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  315.153544] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  315.155772] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  315.155808] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  315.158038] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  315.158073] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  315.160306] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  315.160343] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  315.162577] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  315.162613] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  315.164667] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  315.164703] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  315.166934] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  315.166969] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  315.169179] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  315.169215] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  315.186160] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  315.186195] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  315.187111] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  315.187147] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  315.189355] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  315.189392] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  315.191607] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  315.191643] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  315.193866] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  315.193902] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  315.196153] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  315.196194] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  315.198414] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  315.198450] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  315.200511] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  315.200547] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  315.219477] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  315.219511] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  315.220809] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  315.220845] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  315.223072] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  315.223107] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  315.225313] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  315.225350] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  315.227574] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  315.227610] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  315.229832] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  315.229868] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  315.232130] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  315.232171] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  315.234356] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  315.234392] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  315.252775] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  315.252811] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  315.254570] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  315.254606] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  315.256655] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  315.256690] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  315.258922] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  315.258958] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  315.261151] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  315.261186] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  315.263413] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  315.263449] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  315.265669] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  315.265705] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  315.267931] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  315.267968] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  315.286063] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  315.286097] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  315.288278] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  315.288316] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  315.290518] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  315.290564] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  315.292621] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  315.292657] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  315.294885] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  315.294921] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  315.297111] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  315.297148] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  315.299377] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  315.299412] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  315.301622] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  315.301659] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  315.319502] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  315.319537] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  315.321711] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  315.321746] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  315.323971] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  315.324007] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  315.326232] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  315.326268] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  315.328367] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  315.328406] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  315.330617] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  315.330653] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  315.332703] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  315.332739] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  315.334968] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  315.335004] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  315.352783] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  315.352817] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  315.355014] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  315.355050] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  315.357255] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  315.357292] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  315.359515] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  315.359550] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  315.361773] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  315.361809] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  315.364072] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  315.364115] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  315.366293] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  315.366328] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  315.368431] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  315.368467] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  315.386172] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  315.386209] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  315.386286] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  315.386311] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  315.388397] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  315.388433] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  315.390682] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  315.390718] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  315.392902] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  315.392938] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  315.395165] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  315.395201] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  315.397416] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  315.397453] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  315.399674] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  315.399711] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  315.401902] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  315.401939] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  315.419505] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  315.419539] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  315.419864] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  315.419899] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  315.422151] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  315.422187] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  315.424345] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  315.424382] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  315.426610] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  315.426646] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  315.428696] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  315.428732] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  315.430964] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  315.431000] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  315.433183] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  315.433220] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  315.435447] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  315.435483] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  315.452838] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  315.452873] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  315.453505] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  315.453542] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  315.455768] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  315.455803] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  315.458034] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  315.458071] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  315.460304] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  315.460341] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  315.462575] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  315.462611] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  315.464662] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  315.464700] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  315.466930] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  315.466966] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  315.469181] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  315.469218] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  315.486147] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  315.486184] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  315.487209] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  315.487246] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  315.489459] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  315.489495] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  315.491660] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  315.491695] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  315.493927] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  315.493963] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  315.496201] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  315.496239] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  315.498464] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  315.498500] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  315.500556] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  315.500592] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  315.519475] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  315.519512] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  315.520801] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  315.520837] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  315.523067] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  315.523103] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  315.525313] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  315.525349] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  315.527575] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  315.527611] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  315.529789] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  315.529825] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  315.532089] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  315.532132] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  315.534307] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  315.534343] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  315.552788] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  315.552823] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  315.554517] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  315.554554] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  315.556604] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  315.556640] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  315.558869] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  315.558906] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  315.561105] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  315.561141] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  315.563368] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  315.563405] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  315.565618] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  315.565654] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  315.567882] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  315.567919] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  315.586042] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  315.586077] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  315.588264] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  315.588301] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  315.590533] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  315.590568] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  315.592620] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  315.592656] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  315.594888] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  315.594925] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  315.597122] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  315.597158] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  315.599378] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  315.599414] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  315.601631] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  315.601667] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  315.619522] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  315.619557] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  315.621847] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  315.621883] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  315.624143] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  315.624183] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  315.626380] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  315.626416] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  315.628476] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  315.628512] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  315.630741] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  315.630777] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  315.632957] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  315.632993] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  315.635218] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  315.635254] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  315.652852] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  315.652887] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  315.653173] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  315.653206] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  315.655463] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  315.655499] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  315.657670] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  315.657706] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  315.659941] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  315.659977] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  315.662211] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  315.662247] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  315.664343] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  315.664380] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  315.666612] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  315.666647] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  315.668697] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  315.668735] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  315.686160] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  315.686194] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  315.686716] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  315.686752] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  315.688939] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  315.688976] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  315.691200] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  315.691236] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  315.693447] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  315.693483] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  315.695711] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  315.695747] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  315.697973] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  315.698010] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  315.700248] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  315.700286] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  315.702527] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  315.702563] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  315.719497] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  315.719532] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  315.720244] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  315.720279] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  315.722530] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  315.722566] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  315.724615] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  315.724652] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  315.726884] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  315.726920] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  315.729121] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  315.729157] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  315.731378] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  315.731414] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  315.733583] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  315.733619] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  315.735859] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  315.735895] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  315.752817] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  315.752851] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  315.753951] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  315.753987] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  315.756224] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  315.756260] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  315.758489] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  315.758524] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  315.760582] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  315.760618] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  315.762844] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  315.762880] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  315.765080] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  315.765117] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  315.767338] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  315.767374] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  315.786148] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  315.786183] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  315.787532] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  315.787568] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  315.789793] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  315.789829] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  315.792098] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  315.792141] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  315.794311] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  315.794347] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  315.796441] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  315.796477] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  315.798706] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  315.798742] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  315.800914] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  315.800950] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  315.819466] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  315.819500] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  315.821103] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  315.821138] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  315.823363] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  315.823399] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  315.825608] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  315.825645] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  315.827868] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  315.827904] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  315.830132] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  315.830168] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  315.832340] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  315.832377] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  315.834564] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  315.834600] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  315.852711] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  315.852746] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  315.854916] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  315.854952] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  315.857153] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  315.857189] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  315.859415] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  315.859451] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  315.861672] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  315.861708] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  315.863929] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  315.863965] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  315.866194] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  315.866230] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  315.868350] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  315.868386] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  315.886169] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  315.886204] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  315.888358] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  315.888397] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  315.890616] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  315.890652] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  315.892708] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  315.892744] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  315.894969] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  315.895005] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  315.897205] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  315.897243] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  315.899464] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  315.899501] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  315.901720] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  315.901757] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  315.919508] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  315.919544] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  315.919622] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  315.919647] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  315.921939] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  315.921975] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  315.924212] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  315.924249] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  315.926480] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  315.926515] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  315.928568] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  315.928605] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  315.930833] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  315.930870] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  315.933062] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  315.933098] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  315.935298] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  315.935335] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  315.952846] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  315.952881] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  315.953334] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  315.953370] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  315.955600] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  315.955636] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  315.957865] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  315.957901] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  315.960152] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  315.960192] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  315.962381] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  315.962417] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  315.964474] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  315.964510] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  315.966743] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  315.966779] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  315.968956] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  315.968992] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  315.986162] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  315.986197] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  315.987017] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  315.987052] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  315.989253] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  315.989289] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  315.991515] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  315.991551] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  315.993756] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  315.993793] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  315.996015] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  315.996092] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  315.998280] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  315.998316] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  316.000382] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  316.000418] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  316.019481] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  316.019515] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  316.020555] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  316.020588] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  316.022838] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  316.022874] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  316.025071] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  316.025107] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  316.027333] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  316.027369] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  316.029565] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  316.029601] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  316.031829] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  316.031865] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  316.034089] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  316.034125] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  316.052806] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  316.052840] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  316.054318] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  316.054355] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  316.056445] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  316.056481] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  316.058706] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  316.058742] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  316.060921] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  316.060958] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  316.063184] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  316.063220] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  316.065432] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  316.065469] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  316.067692] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  316.067728] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  316.086051] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  316.086086] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  316.088102] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  316.088148] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  316.090307] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  316.090343] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  316.092399] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  316.092436] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  316.094654] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  316.094690] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  316.096864] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  316.096901] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  316.099124] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  316.099160] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  316.101367] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  316.101404] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  316.119501] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  316.119537] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  316.121696] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  316.121732] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  316.123957] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  316.123993] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  316.126221] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  316.126258] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  316.128354] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  316.128391] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  316.130619] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  316.130655] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  316.132709] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  316.132745] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  316.134970] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  316.135006] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  316.152858] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  316.152893] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  316.155202] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  316.155237] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  316.157400] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  316.157438] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  316.159695] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  316.159731] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  316.161960] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  316.161996] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  316.164233] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  316.164270] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  316.166504] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  316.166540] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  316.168593] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  316.168629] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  316.186182] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  316.186217] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  316.186490] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  316.186523] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  316.188601] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  316.188636] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  316.190867] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  316.190902] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  316.193098] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  316.193135] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  316.195359] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  316.195395] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  316.197611] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  316.197647] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  316.199873] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  316.199909] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  316.202138] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  316.202174] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  316.219504] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  316.219538] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  316.220086] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  316.220124] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  316.222337] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  316.222373] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  316.224452] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  316.224487] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  316.226724] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  316.226761] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  316.228942] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  316.228977] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  316.231205] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  316.231241] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  316.233449] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  316.233485] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  316.235585] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  316.235621] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  316.252836] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  316.252870] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  316.253667] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  316.253703] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  316.255929] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  316.255965] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  316.258191] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  316.258226] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  316.260341] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  316.260378] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  316.262609] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  316.262645] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  316.264694] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  316.264730] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  316.266960] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  316.266996] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  316.269209] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  316.269246] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  316.286158] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  316.286193] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  316.287275] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  316.287310] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  316.289523] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  316.289558] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  316.291785] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  316.291821] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  316.293925] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  316.293960] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  316.296194] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  316.296234] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  316.298437] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  316.298474] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  316.300527] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  316.300563] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  316.319482] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  316.319518] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  316.320736] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  316.320772] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  316.322998] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  316.323033] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  316.325239] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  316.325276] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  316.327502] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  316.327538] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  316.329717] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  316.329754] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  316.331977] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  316.332055] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  316.334239] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  316.334274] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  316.352802] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  316.352837] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  316.354355] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  316.354391] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  316.356463] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  316.356499] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  316.358727] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  316.358763] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  316.360948] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  316.360985] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  316.363209] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  316.363245] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  316.365455] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  316.365492] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  316.367716] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  316.367752] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  316.386118] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  316.386153] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  316.387813] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  316.387849] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  316.390072] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  316.390109] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  316.392386] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  316.392422] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  316.394507] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  316.394543] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  316.396585] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  316.396621] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  316.398851] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  316.398886] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  316.400946] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  316.400980] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  316.419477] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  316.419513] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  316.420750] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  316.420783] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  316.423041] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  316.423076] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  316.425135] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  316.425168] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  316.427418] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  316.427454] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  316.429668] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  316.429705] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  316.431930] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  316.431966] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  316.434188] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  316.434224] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  316.452793] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  316.452829] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  316.454038] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  316.454073] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  316.456330] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  316.456367] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  316.458595] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  316.458632] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  316.460677] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  316.460713] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  316.462947] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  316.462983] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  316.465174] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  316.465211] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  316.467435] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  316.467471] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  316.486142] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  316.486177] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  316.487617] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  316.487652] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  316.489874] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  316.489911] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  316.492173] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  316.492210] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  316.494422] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  316.494458] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  316.496516] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  316.496551] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  316.498783] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  316.498819] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  316.501009] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  316.501045] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  316.519443] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  316.519477] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  316.521162] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  316.521196] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  316.523446] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  316.523483] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  316.525706] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  316.525743] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  316.527969] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  316.528005] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  316.530230] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  316.530266] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  316.532364] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  316.532401] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  316.534628] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  316.534664] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  316.552770] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  316.552805] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  316.554975] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  316.555011] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  316.557211] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  316.557246] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  316.559473] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  316.559509] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  316.561729] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  316.561765] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  316.563992] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  316.564068] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  316.566260] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  316.566296] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  316.568361] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  316.568399] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  316.586172] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  316.586210] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  316.586293] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  316.586318] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  316.588441] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  316.588478] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  316.590690] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  316.590726] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  316.592906] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  316.592943] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  316.595032] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  316.595068] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  316.597273] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  316.597309] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  316.599534] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  316.599570] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  316.601791] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  316.601827] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  316.619509] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  316.619543] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  316.619731] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  316.619764] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  316.622020] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  316.622056] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  316.624292] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  316.624331] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  316.626561] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  316.626597] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  316.628652] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  316.628688] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  316.630918] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  316.630955] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  316.633145] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  316.633182] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  316.635414] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  316.635451] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  316.652834] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  316.652870] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  316.653464] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  316.653499] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  316.655727] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  316.655763] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  316.657995] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  316.658030] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  316.660266] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  316.660303] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  316.662531] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  316.662567] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  316.664618] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  316.664654] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  316.666882] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  316.666919] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  316.669110] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  316.669147] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  316.686159] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  316.686194] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  316.687164] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  316.687200] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  316.689410] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  316.689447] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  316.691673] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  316.691708] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  316.693932] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  316.693969] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  316.696159] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  316.696200] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  316.698433] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  316.698469] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  316.700528] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  316.700565] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  316.719485] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  316.719520] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  316.720826] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  316.720861] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  316.723092] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  316.723127] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  316.725334] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  316.725370] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  316.727596] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  316.727632] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  316.729854] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  316.729890] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  316.732153] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  316.732193] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  316.734408] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  316.734444] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  316.752785] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  316.752820] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  316.754616] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  316.754652] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  316.756703] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  316.756739] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  316.758966] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  316.759003] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  316.761204] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  316.761240] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  316.763464] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  316.763500] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  316.765718] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  316.765753] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  316.767979] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  316.768055] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  316.786043] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  316.786077] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  316.788233] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  316.788270] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  316.790492] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  316.790528] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  316.792580] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  316.792615] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  316.794851] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  316.794887] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  316.796977] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  316.797013] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  316.799243] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  316.799278] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  316.801496] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  316.801533] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  316.819514] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  316.819549] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  316.821720] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  316.821756] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  316.823986] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  316.824061] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  316.826246] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  316.826281] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  316.828370] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  316.828407] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  316.830640] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  316.830676] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  316.832730] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  316.832766] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  316.834992] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  316.835027] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  316.852861] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  316.852896] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  316.855140] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  316.855176] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  316.857389] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  316.857425] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  316.859646] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  316.859682] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  316.861906] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  316.861941] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  316.864173] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  316.864222] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  316.866443] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  316.866479] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  316.868518] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  316.868554] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  316.886178] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  316.886212] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  316.886292] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  316.886317] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  316.888471] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  316.888508] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  316.890737] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  316.890773] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  316.892870] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  316.892906] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  316.894998] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  316.895033] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  316.897140] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  316.897175] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  316.899401] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  316.899437] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  316.901654] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  316.901690] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  316.919512] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  316.919547] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  316.921727] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  316.921763] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  316.923988] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  316.924065] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  316.926251] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  316.926287] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  316.928390] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  316.928428] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  316.930648] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  316.930684] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  316.932737] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  316.932774] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  316.935001] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  316.935037] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  316.952844] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  316.952881] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  316.952958] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  316.952983] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  316.955213] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  316.955249] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  316.957430] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  316.957467] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  316.959693] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  316.959729] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  316.961948] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  316.961983] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  316.964232] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  316.964271] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  316.966491] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  316.966527] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  316.968583] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  316.968619] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  316.986177] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  316.986212] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  316.986480] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  316.986513] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  316.988600] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  316.988636] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  316.990863] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  316.990899] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  316.993096] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  316.993132] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  316.995356] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  316.995392] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  316.997609] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  316.997645] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  316.999868] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  316.999904] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  317.002119] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  317.002155] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  317.019507] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  317.019542] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  317.020087] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  317.020121] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  317.022335] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  317.022370] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  317.024432] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  317.024469] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  317.026691] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  317.026727] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  317.028778] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  317.028814] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  317.031042] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  317.031077] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  317.033282] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  317.033319] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  317.035543] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  317.035579] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  317.052840] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  317.052874] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  317.053604] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  317.053640] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  317.055870] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  317.055906] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  317.058130] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  317.058166] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  317.060356] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  317.060393] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  317.062616] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  317.062653] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  317.064703] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  317.064739] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  317.066961] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  317.066997] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  317.069210] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  317.069246] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  317.086150] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  317.086185] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  317.087268] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  317.087304] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  317.089511] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  317.089547] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  317.091772] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  317.091807] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  317.094034] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  317.094069] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  317.096320] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  317.096366] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  317.098577] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  317.098613] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  317.100668] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  317.100704] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  317.119485] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  317.119520] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  317.120822] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  317.120858] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  317.123083] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  317.123120] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  317.125329] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  317.125365] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  317.127595] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  317.127631] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  317.129853] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  317.129889] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  317.132150] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  317.132190] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  317.134383] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  317.134418] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  317.152794] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  317.152829] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  317.154534] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  317.154570] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  317.156627] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  317.156663] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  317.158891] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  317.158926] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  317.161116] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  317.161152] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  317.163378] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  317.163413] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  317.165630] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  317.165667] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  317.167892] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  317.167928] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  317.186050] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  317.186084] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  317.188274] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  317.188312] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  317.190528] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  317.190565] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  317.192612] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  317.192647] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  317.194869] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  317.194905] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  317.196976] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  317.197012] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  317.199266] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  317.199303] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  317.201513] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  317.201550] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  317.219515] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  317.219551] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  317.221722] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  317.221758] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  317.223981] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  317.224058] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  317.226244] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  317.226280] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  317.228385] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  317.228422] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  317.230641] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  317.230679] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  317.232731] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  317.232767] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  317.234999] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  317.235035] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  317.252860] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  317.252897] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  317.255196] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  317.255232] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  317.257442] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  317.257479] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  317.259703] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  317.259740] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  317.261969] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  317.262006] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  317.264255] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  317.264295] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  317.266512] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  317.266548] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  317.268601] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  317.268637] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  317.286179] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  317.286214] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  317.286530] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  317.286565] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  317.288623] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  317.288658] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  317.290888] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  317.290924] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  317.293114] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  317.293151] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  317.295376] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  317.295412] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  317.297504] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  317.297540] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  317.299639] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  317.299675] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  317.301893] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  317.301929] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  317.319514] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  317.319549] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  317.319628] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  317.319653] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  317.321930] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  317.321966] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  317.324202] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  317.324240] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  317.326469] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  317.326505] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  317.328560] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  317.328596] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  317.330816] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  317.330852] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  317.333045] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  317.333081] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  317.335307] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  317.335343] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  317.352846] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  317.352880] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  317.353151] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  317.353185] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  317.355442] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  317.355478] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  317.357693] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  317.357728] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  317.359957] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  317.359994] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  317.362218] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  317.362254] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  317.364355] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  317.364392] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  317.366621] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  317.366657] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  317.368709] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  317.368746] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  317.386182] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  317.386216] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  317.386468] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  317.386501] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  317.388588] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  317.388623] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  317.390854] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  317.390889] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  317.393091] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  317.393128] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  317.395353] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  317.395389] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  317.397616] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  317.397652] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  317.399877] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  317.399912] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  317.402140] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  317.402176] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  317.419498] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  317.419533] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  317.420092] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  317.420130] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  317.422340] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  317.422377] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  317.424437] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  317.424473] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  317.426701] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  317.426736] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  317.428922] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  317.428958] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  317.431183] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  317.431219] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  317.433430] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  317.433467] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  317.435696] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  317.435732] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  317.452823] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  317.452858] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  317.453766] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  317.453802] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  317.456075] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  317.456118] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  317.458298] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  317.458334] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  317.460402] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  317.460439] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  317.462665] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  317.462701] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  317.464889] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  317.464925] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  317.467146] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  317.467182] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  317.486143] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  317.486179] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  317.487500] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  317.487537] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  317.489757] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  317.489792] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  317.492015] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  317.492092] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  317.494280] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  317.494316] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  317.496396] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  317.496433] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  317.498608] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  317.498644] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  317.500696] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  317.500732] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  317.519485] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  317.519520] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  317.520856] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  317.520893] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  317.523119] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  317.523155] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  317.525361] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  317.525397] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  317.527624] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  317.527659] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  317.529881] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  317.529917] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  317.532156] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  317.532192] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  317.534426] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  317.534462] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  317.552781] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  317.552816] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  317.554623] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  317.554659] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  317.556708] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  317.556745] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  317.558979] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  317.559015] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  317.561217] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  317.561253] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  317.563479] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  317.563515] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  317.565735] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  317.565772] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  317.567999] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  317.568075] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  317.586045] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  317.586079] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  317.588237] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  317.588274] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  317.590498] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  317.590535] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  317.592590] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  317.592628] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  317.594857] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  317.594894] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  317.597087] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  317.597124] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  317.599319] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  317.599355] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  317.601568] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  317.601604] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  317.619515] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  317.619551] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  317.621786] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  317.621822] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  317.624075] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  317.624117] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  317.626304] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  317.626340] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  317.628359] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  317.628398] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  317.630664] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  317.630699] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  317.632878] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  317.632914] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  317.635140] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  317.635177] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  317.652851] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  317.652885] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  317.653101] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  317.653134] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  317.655393] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  317.655429] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  317.657647] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  317.657682] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  317.659915] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  317.659951] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  317.662176] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  317.662213] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  317.664353] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  317.664392] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  317.666613] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  317.666650] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  317.668706] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  317.668743] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  317.686182] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  317.686216] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  317.686733] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  317.686769] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  317.688956] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  317.688993] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  317.691220] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  317.691256] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  317.693467] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  317.693505] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  317.695727] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  317.695764] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  317.697988] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  317.698023] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  317.700255] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  317.700292] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  317.702526] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  317.702562] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  317.719496] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  317.719531] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  317.720215] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  317.720249] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  317.722541] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  317.722577] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  317.724630] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  317.724666] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  317.726862] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  317.726899] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  317.729096] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  317.729133] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  317.731358] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  317.731394] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  317.733608] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  317.733645] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  317.735900] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  317.735936] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  317.752817] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  317.752851] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  317.753816] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  317.753852] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  317.756116] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  317.756156] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  317.758344] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  317.758381] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  317.760438] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  317.760473] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  317.762704] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  317.762740] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  317.764791] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  317.764827] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  317.767060] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  317.767095] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  317.786157] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  317.786191] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  317.787420] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  317.787456] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  317.789675] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  317.789712] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  317.791938] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  317.791975] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  317.794203] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  317.794239] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  317.796357] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  317.796393] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  317.798613] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  317.798650] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  317.800836] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  317.800872] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  317.819481] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  317.819516] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  317.820820] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  317.820856] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  317.823083] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  317.823119] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  317.825326] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  317.825362] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  317.827590] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  317.827626] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  317.829848] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  317.829885] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  317.832146] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  317.832186] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  317.834355] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  317.834391] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  317.852803] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  317.852838] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  317.854513] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  317.854549] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  317.856609] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  317.856644] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  317.858876] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  317.858911] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  317.861107] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  317.861144] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  317.863369] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  317.863406] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  317.865620] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  317.865657] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  317.867886] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  317.867922] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  317.886045] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  317.886080] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  317.888271] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  317.888311] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  317.890530] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  317.890566] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  317.892592] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  317.892626] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  317.894877] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  317.894913] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  317.897111] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  317.897148] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  317.899365] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  317.899412] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  317.901630] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  317.901667] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  317.919515] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  317.919551] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  317.921738] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  317.921774] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  317.923998] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  317.924075] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  317.926264] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  317.926300] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  317.928392] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  317.928428] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  317.930659] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  317.930695] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  317.932880] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  317.932916] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  317.935142] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  317.935178] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  317.952848] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  317.952883] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  317.953059] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  317.953093] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  317.955345] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  317.955381] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  317.957595] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  317.957631] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  317.959861] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  317.959897] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  317.962097] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  317.962133] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  317.964362] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  317.964399] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  317.966613] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  317.966649] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  317.968701] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  317.968738] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  317.986176] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  317.986211] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  317.986709] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  317.986744] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  317.988931] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  317.988967] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  317.991192] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  317.991228] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  317.993440] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  317.993476] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  317.995704] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  317.995740] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  317.997962] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  317.997999] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  318.000123] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  318.000164] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  318.002351] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  318.002387] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  318.019495] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  318.019530] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  318.020179] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  318.020214] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  318.022456] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  318.022492] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  318.024554] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  318.024590] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  318.026816] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  318.026853] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  318.029050] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  318.029086] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  318.031313] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  318.031350] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  318.033555] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  318.033591] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  318.035832] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  318.035868] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  318.052824] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  318.052860] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  318.053889] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  318.053925] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  318.056158] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  318.056195] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  318.058422] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  318.058458] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  318.060520] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  318.060556] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  318.062784] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  318.062820] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  318.065008] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  318.065046] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  318.067270] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  318.067305] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  318.086147] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  318.086180] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  318.087546] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  318.087582] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  318.089762] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  318.089798] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  318.092062] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  318.092105] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  318.094283] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  318.094320] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  318.096401] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  318.096438] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  318.098662] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  318.098698] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  318.100878] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  318.100913] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  318.119479] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  318.119514] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  318.121046] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  318.121082] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  318.123309] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  318.123345] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  318.125557] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  318.125593] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  318.127822] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  318.127858] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  318.130083] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  318.130120] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  318.132358] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  318.132397] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  318.134617] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  318.134654] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  318.152749] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  318.152784] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  318.154960] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  318.154997] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  318.157193] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  318.157229] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  318.159458] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  318.159494] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  318.161713] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  318.161748] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  318.163974] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  318.164052] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  318.166238] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  318.166274] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  318.168380] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  318.168416] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  318.186191] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  318.186226] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  318.188417] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  318.188454] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  318.190675] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  318.190711] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  318.192888] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  318.192925] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  318.195158] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  318.195194] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  318.197403] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  318.197440] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  318.199667] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  318.199703] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  318.201923] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  318.201959] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  318.219514] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  318.219549] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  318.219811] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  318.219844] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  318.222097] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  318.222133] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  318.224351] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  318.224389] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  318.226611] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  318.226648] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  318.228698] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  318.228735] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  318.230967] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  318.231002] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  318.233205] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  318.233241] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  318.235471] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  318.235507] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  318.252844] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  318.252878] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  318.253470] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  318.253506] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  318.255736] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  318.255772] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  318.257993] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  318.258030] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  318.260278] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  318.260317] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  318.262536] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  318.262571] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  318.264635] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  318.264671] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  318.266902] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  318.266938] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  318.269130] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  318.269174] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  318.286166] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  318.286201] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  318.287207] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  318.287243] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  318.289455] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  318.289491] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  318.291720] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  318.291756] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  318.293980] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  318.294016] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  318.296269] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  318.296305] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  318.298525] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  318.298562] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  318.300618] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  318.300657] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  318.319485] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  318.319521] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  318.320800] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  318.320837] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  318.323065] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  318.323100] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  318.325306] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  318.325343] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  318.327568] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  318.327604] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  318.329828] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  318.329864] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  318.332121] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  318.332161] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  318.334355] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  318.334391] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  318.352798] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  318.352832] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  318.354494] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  318.354530] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  318.356590] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  318.356626] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  318.358854] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  318.358889] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  318.361086] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  318.361121] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  318.363348] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  318.363385] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  318.365599] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  318.365636] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  318.367860] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  318.367895] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  318.386115] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  318.386150] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  318.387954] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  318.387990] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  318.390212] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  318.390247] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  318.392357] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  318.392394] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  318.394615] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  318.394651] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  318.396702] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  318.396739] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  318.398971] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  318.399007] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  318.401197] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  318.401245] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  318.419383] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  318.419418] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  318.421440] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  318.421475] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  318.423702] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  318.423738] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  318.425961] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  318.425998] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  318.428247] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  318.428284] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  318.430512] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  318.430547] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  318.432601] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  318.432637] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  318.434865] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  318.434901] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  318.452851] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  318.452885] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  318.455064] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  318.455100] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  318.457308] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  318.457344] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  318.459569] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  318.459606] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  318.461826] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  318.461863] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  318.464124] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  318.464163] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  318.466353] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  318.466390] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  318.468452] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  318.468489] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  318.486178] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  318.486213] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  318.486291] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  318.486316] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  318.488444] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  318.488481] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  318.490708] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  318.490745] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  318.492930] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  318.492967] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  318.495190] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  318.495226] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  318.497436] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  318.497473] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  318.499695] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  318.499730] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  318.501829] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  318.501866] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  318.519511] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  318.519546] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  318.519772] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  318.519805] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  318.522057] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  318.522094] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  318.524339] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  318.524378] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  318.526600] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  318.526636] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  318.528686] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  318.528722] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  318.530955] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  318.530992] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  318.533183] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  318.533219] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  318.535448] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  318.535484] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  318.552844] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  318.552879] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  318.553496] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  318.553532] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  318.555760] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  318.555796] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  318.558028] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  318.558063] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  318.560308] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  318.560347] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  318.562567] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  318.562604] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  318.564654] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  318.564690] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  318.566925] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  318.566962] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  318.569163] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  318.569200] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  318.586172] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  318.586207] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  318.587234] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  318.587270] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  318.589487] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  318.589524] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  318.591746] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  318.591781] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  318.594008] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  318.594043] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  318.596297] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  318.596334] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  318.598553] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  318.598589] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  318.600640] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  318.600677] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  318.619488] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  318.619522] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  318.620803] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  318.620840] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  318.623060] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  318.623096] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  318.625302] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  318.625338] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  318.627564] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  318.627600] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  318.629822] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  318.629859] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  318.632119] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  318.632159] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  318.634342] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  318.634378] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  318.652805] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  318.652839] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  318.654485] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  318.654521] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  318.656585] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  318.656622] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  318.658851] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  318.658886] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  318.661079] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  318.661115] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  318.663339] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  318.663374] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  318.665590] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  318.665626] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  318.667851] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  318.667886] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  318.686047] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  318.686081] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  318.688243] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  318.688282] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  318.690509] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  318.690546] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  318.692594] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  318.692631] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  318.694864] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  318.694899] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  318.697093] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  318.697129] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  318.699359] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  318.699395] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  318.701615] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  318.701651] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  318.719518] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  318.719554] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  318.721831] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  318.721867] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  318.724129] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  318.724169] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  318.726359] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  318.726395] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  318.728458] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  318.728494] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  318.730702] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  318.730738] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  318.732792] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  318.732828] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  318.735054] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  318.735090] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  318.752850] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  318.752886] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  318.752961] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  318.752986] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  318.755223] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  318.755259] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  318.757470] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  318.757505] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  318.759737] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  318.759773] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  318.761999] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  318.762034] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  318.764279] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  318.764318] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  318.766537] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  318.766574] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  318.768624] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  318.768660] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  318.786183] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  318.786219] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  318.786436] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  318.786470] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  318.788561] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  318.788596] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  318.790826] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  318.790862] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  318.793056] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  318.793093] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  318.795320] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  318.795356] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  318.797567] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  318.797603] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  318.799830] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  318.799865] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  318.802087] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  318.802123] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  318.819506] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  318.819541] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  318.819963] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  318.819997] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  318.822252] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  318.822288] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  318.824384] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  318.824419] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  318.826644] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  318.826679] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  318.828735] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  318.828771] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  318.831003] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  318.831038] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  318.833239] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  318.833276] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  318.835500] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  318.835536] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  318.852803] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  318.852837] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  318.853354] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  318.853390] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  318.855619] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  318.855655] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  318.857823] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  318.857859] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  318.860118] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  318.860159] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  318.862349] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  318.862385] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  318.864447] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  318.864482] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  318.866719] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  318.866755] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  318.868945] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  318.868981] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  318.886165] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  318.886199] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  318.886996] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  318.887031] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  318.889236] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  318.889272] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  318.891498] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  318.891535] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  318.893756] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  318.893792] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  318.896017] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  318.896093] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  318.898278] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  318.898314] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  318.900394] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  318.900431] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  318.919498] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  318.919533] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  318.920556] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  318.920589] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  318.922837] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  318.922873] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  318.925068] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  318.925104] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  318.927331] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  318.927367] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  318.929584] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  318.929620] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  318.931848] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  318.931884] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  318.934112] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  318.934148] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  318.952829] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  318.952864] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  318.953934] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  318.953970] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  318.956216] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  318.956252] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  318.958472] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  318.958508] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  318.960536] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  318.960571] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  318.962819] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  318.962856] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  318.965051] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  318.965088] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  318.967314] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  318.967350] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  318.986150] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  318.986185] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  318.987558] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  318.987593] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  318.989810] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  318.989846] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  318.992112] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  318.992152] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  318.994335] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  318.994370] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  318.996435] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  318.996470] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  318.998696] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  318.998731] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  319.000789] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  319.000824] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  319.019485] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  319.019520] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  319.020961] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  319.020998] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  319.023224] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  319.023259] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  319.025466] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  319.025503] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  319.027729] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  319.027765] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  319.029990] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  319.030026] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  319.032277] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  319.032314] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  319.034533] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  319.034569] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  319.052713] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  319.052748] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  319.054847] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  319.054883] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  319.057085] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  319.057120] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  319.059338] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  319.059374] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  319.061589] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  319.061625] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  319.063850] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  319.063886] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  319.066118] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  319.066154] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  319.068352] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  319.068390] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  319.086190] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  319.086226] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  319.088400] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  319.088436] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  319.090666] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  319.090703] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  319.092889] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  319.092925] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  319.095151] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  319.095187] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  319.097393] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  319.097430] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  319.099663] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  319.099699] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  319.101919] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  319.101956] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  319.119522] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  319.119557] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  319.119734] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  319.119767] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  319.122017] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  319.122054] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  319.124300] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  319.124338] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  319.126558] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  319.126595] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  319.128646] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  319.128682] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  319.130914] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  319.130950] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  319.133147] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  319.133183] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  319.135405] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  319.135441] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  319.152849] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  319.152883] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  319.153460] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  319.153496] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  319.155726] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  319.155761] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  319.157985] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  319.158021] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  319.160268] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  319.160306] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  319.162526] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  319.162562] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  319.164619] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  319.164655] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  319.166880] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  319.166916] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  319.169114] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  319.169150] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  319.186168] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  319.186203] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  319.187084] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  319.187120] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  319.189328] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  319.189364] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  319.191588] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  319.191625] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  319.193845] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  319.193880] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  319.196143] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  319.196183] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  319.198373] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  319.198408] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  319.200468] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  319.200503] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  319.219481] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  319.219516] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  319.220785] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  319.220821] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  319.223050] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  319.223086] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  319.225303] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  319.225338] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  319.227572] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  319.227608] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  319.229830] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  319.229866] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  319.232126] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  319.232165] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  319.234355] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  319.234391] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  319.270407] [IGT] kms_flip: exiting, ret=0
>[  319.314340] [drm:intel_atomic_check [i915]] [CONNECTOR:49:eDP-1] checking for sink bpp constrains
>[  319.314418] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  319.314457] [drm:drm_mode_debug_printmodeline [drm]] Modeline 52:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[  319.314537] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 138780KHz
>[  319.314627] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24
>[  319.314694] [drm:intel_dp_compute_config [i915]] DP link bw required 416340 available 540000
>[  319.314760] [drm:intel_dp_compute_config [i915]] PSR disable by flag
>[  319.314833] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  319.314904] [drm:intel_dump_pipe_config [i915]] [CRTC:37:pipe A][modeset]
>[  319.314972] [drm:intel_dump_pipe_config [i915]] output_types: EDP (0x100)
>[  319.315037] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0
>[  319.315102] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 6467616, gmch_n: 8388608, link_m: 269484, link_n: 524288, tu: 64
>[  319.315164] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  319.315225] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  319.315256] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[  319.315320] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  319.315349] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[  319.315415] [drm:intel_dump_pipe_config [i915]] crtc timings: 138780 1920 1966 1996 2080 1080 1082 1086 1112, type: 0x48 flags: 0xa
>[  319.315476] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 138780
>[  319.315537] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  319.315597] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  319.315655] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  319.315714] [drm:intel_dump_pipe_config [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  319.315772] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  319.315830] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 1A] disabled, scaler_id = -1
>[  319.315887] [drm:intel_dump_pipe_config [i915]] [PLANE:31:plane 2A] disabled, scaler_id = -1
>[  319.315943] [drm:intel_dump_pipe_config [i915]] [PLANE:34:cursor A] disabled, scaler_id = -1
>[  319.316016] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  319.316123] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[  319.316209] [drm:intel_find_shared_dpll [i915]] [CRTC:37:pipe A] allocated DPLL 0
>[  319.316287] [drm:intel_reference_shared_dpll [i915]] using DPLL 0 for pipe A
>[  319.316404] [drm:intel_disable_sagv [i915]] Disabling the SAGV
>[  319.316481] [drm:intel_atomic_commit_tail [i915]] [ENCODER:48:DDI A]
>[  319.316554] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI B]
>[  319.316622] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  319.316687] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  319.316748] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DDI C]
>[  319.316810] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST A]
>[  319.316869] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST B]
>[  319.316930] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI D]
>[  319.316991] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[  319.317052] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[  319.317117] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[  319.317186] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[  319.317250] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[  319.317313] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[  319.319409] [drm:intel_enable_shared_dpll [i915]] enable DPLL 0 (active 1, on? 0) for crtc 37
>[  319.319479] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 0
>[  319.319564] [drm:edp_panel_on [i915]] Turn eDP port A panel power on
>[  319.319642] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle
>[  319.319833] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 00000000 control 00000060
>[  319.319920] [drm:wait_panel_status [i915]] Wait complete
>[  319.320077] [drm:edp_panel_on [i915]] Wait for panel power on
>[  319.320205] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 00000063
>[  319.355357] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010
>[  319.355438] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  319.355512] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0
>[  319.355639] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  319.520802] [drm:wait_panel_status [i915]] Wait complete
>[  319.520868] [drm:intel_power_well_enable [i915]] enabling DDI A/E IO power well
>[  319.520971] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[  319.521123] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b
>[  319.522357] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  319.522430] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  319.522495] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  319.522559] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  319.523275] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  319.523334] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  319.524369] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  319.524432] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:49:eDP-1] Link Training Passed at Link Rate = 270000, Lane count = 2
>[  319.525087] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  319.525163] [drm:intel_edp_backlight_on [i915]] 
>[  319.525226] [drm:intel_panel_enable_backlight [i915]] pipe A
>[  319.525317] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 120000
>[  319.532203] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS
>[  319.532280] [drm:intel_fbc_enable [i915]] reserved 16588800 bytes of contiguous stolen space for FBC, threshold: 1
>[  319.532343] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  319.541974] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:49:eDP-1]
>[  319.542061] [drm:intel_atomic_commit_tail [i915]] [CRTC:37:pipe A]
>[  319.542158] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[  319.585118] [IGT] kms_frontbuffer_tracking: executing
>[  319.633964] [drm:drm_mode_addfb2 [drm]] [FB:90]
>[  319.634002] [drm:drm_mode_addfb2 [drm]] [FB:91]
>[  319.634034] [drm:drm_mode_addfb2 [drm]] [FB:92]
>[  319.634667] [drm:drm_mode_addfb2 [drm]] [FB:93]
>[  319.640448] [drm:drm_mode_addfb2 [drm]] [FB:94]
>[  319.641854] [drm:drm_mode_addfb2 [drm]] [FB:96]
>[  319.641886] [drm:drm_mode_addfb2 [drm]] [FB:98]
>[  319.641922] [drm:drm_mode_addfb2 [drm]] [FB:102]
>[  319.642163] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  319.642182] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  319.858943] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped
>[  319.859063] [IGT] kms_frontbuffer_tracking: starting subtest fbc-1p-offscren-pri-indfb-draw-blt
>[  319.859164] Setting dangerous option enable_fbc - tainting kernel
>[  319.859190] Setting dangerous option enable_psr - tainting kernel
>[  319.879314] [drm:drm_mode_addfb2 [drm]] [FB:72]
>[  319.879404] [drm:drm_mode_addfb2 [drm]] [FB:90]
>[  319.879497] [drm:drm_mode_addfb2 [drm]] [FB:91]
>[  319.880732] [drm:drm_mode_addfb2 [drm]] [FB:92]
>[  319.884487] [drm:drm_mode_addfb2 [drm]] [FB:93]
>[  319.885304] [drm:drm_mode_addfb2 [drm]] [FB:94]
>[  319.885322] [drm:drm_mode_addfb2 [drm]] [FB:96]
>[  319.885342] [drm:drm_mode_addfb2 [drm]] [FB:98]
>[  319.885451] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  319.885482] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  319.885496] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[  319.885526] [drm:intel_edp_backlight_off [i915]] 
>[  320.092378] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0
>[  320.092508] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  320.109492] [drm:intel_edp_panel_off.part.31 [i915]] Turn eDP port A panel power off
>[  320.109606] [drm:intel_edp_panel_off.part.31 [i915]] Wait for panel power off time
>[  320.109738] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000002 control 00000060
>[  320.162290] [drm:wait_panel_status [i915]] Wait complete
>[  320.162354] [drm:intel_power_well_disable [i915]] disabling DDI A/E IO power well
>[  320.162437] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  320.162517] [drm:intel_disable_shared_dpll [i915]] disable DPLL 0 (active 1, on? 1) for crtc 37
>[  320.162589] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 0
>[  320.162683] [drm:intel_atomic_commit_tail [i915]] [ENCODER:48:DDI A]
>[  320.162753] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI B]
>[  320.162820] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  320.162885] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  320.162947] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DDI C]
>[  320.163008] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST A]
>[  320.163068] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST B]
>[  320.163129] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI D]
>[  320.163189] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[  320.163247] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[  320.163312] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:49:eDP-1]
>[  320.163379] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[  320.163444] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[  320.163508] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[  320.163570] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[  320.169587] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010
>[  320.169669] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  320.169743] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1
>[  320.169870] [drm:intel_atomic_commit_tail [i915]] [CRTC:37:pipe A]
>[  320.169960] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  320.170036] [drm:intel_enable_sagv [i915]] Enabling the SAGV
>[  320.170139] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  320.170236] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  320.170305] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[  320.170407] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  320.187273] [drm:intel_power_well_disable [i915]] disabling DDI B IO power well
>[  320.187356] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 2, on? 1) for crtc 47
>[  320.187429] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  320.187519] [drm:intel_atomic_commit_tail [i915]] [ENCODER:48:DDI A]
>[  320.187585] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI B]
>[  320.187651] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  320.187712] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  320.187772] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DDI C]
>[  320.187831] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST A]
>[  320.187888] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST B]
>[  320.187946] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI D]
>[  320.188001] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[  320.188095] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[  320.188167] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:57:DP-1]
>[  320.188239] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[  320.188304] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[  320.188369] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[  320.188434] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[  320.188494] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  320.188573] [drm:intel_atomic_commit_tail [i915]] [CRTC:47:pipe B]
>[  320.188629] [drm:intel_power_well_disable [i915]] disabling DC off
>[  320.188681] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  320.188731] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  320.189171] [drm:intel_power_well_disable [i915]] disabling always-on
>[  320.193171] [drm:drm_mode_addfb2 [drm]] [FB:73]
>[  320.194834] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  320.194840] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  320.194861] [drm:intel_atomic_check [i915]] [CONNECTOR:49:eDP-1] checking for sink bpp constrains
>[  320.194874] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  320.194880] [drm:drm_mode_debug_printmodeline [drm]] Modeline 52:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[  320.194894] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 138780KHz
>[  320.194910] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24
>[  320.194922] [drm:intel_dp_compute_config [i915]] DP link bw required 416340 available 540000
>[  320.194933] [drm:intel_dp_compute_config [i915]] PSR disable by flag
>[  320.194946] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  320.194959] [drm:intel_dump_pipe_config [i915]] [CRTC:37:pipe A][modeset]
>[  320.194971] [drm:intel_dump_pipe_config [i915]] output_types: EDP (0x100)
>[  320.194982] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0
>[  320.194994] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 6467616, gmch_n: 8388608, link_m: 269484, link_n: 524288, tu: 64
>[  320.195005] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  320.195015] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  320.195021] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[  320.195032] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  320.195037] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[  320.195048] [drm:intel_dump_pipe_config [i915]] crtc timings: 138780 1920 1966 1996 2080 1080 1082 1086 1112, type: 0x48 flags: 0xa
>[  320.195059] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 138780
>[  320.195069] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  320.195080] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  320.195090] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  320.195100] [drm:intel_dump_pipe_config [i915]] dpll_hw_state: ctrl1: 0x3, cfgcr1: 0x0, cfgcr2: 0x0
>[  320.195110] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  320.195120] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 1A] disabled, scaler_id = -1
>[  320.195131] [drm:intel_dump_pipe_config [i915]] [PLANE:31:plane 2A] disabled, scaler_id = -1
>[  320.195141] [drm:intel_dump_pipe_config [i915]] [PLANE:34:cursor A] disabled, scaler_id = -1
>[  320.195153] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  320.195165] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[  320.195179] [drm:intel_find_shared_dpll [i915]] [CRTC:37:pipe A] allocated DPLL 0
>[  320.195190] [drm:intel_reference_shared_dpll [i915]] using DPLL 0 for pipe A
>[  320.195772] [drm:intel_power_well_enable [i915]] enabling always-on
>[  320.195783] [drm:intel_power_well_enable [i915]] enabling DC off
>[  320.196089] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  320.196130] [drm:intel_atomic_commit_tail [i915]] [ENCODER:48:DDI A]
>[  320.196149] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI B]
>[  320.196163] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  320.196174] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  320.196186] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DDI C]
>[  320.196197] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST A]
>[  320.196208] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST B]
>[  320.196219] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI D]
>[  320.196230] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[  320.196241] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[  320.196253] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[  320.196265] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[  320.196277] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[  320.196288] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[  320.196302] [drm:intel_enable_shared_dpll [i915]] enable DPLL 0 (active 1, on? 0) for crtc 37
>[  320.196313] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 0
>[  320.196333] [drm:edp_panel_on [i915]] Turn eDP port A panel power on
>[  320.196357] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle
>[  320.796571] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 00000000 control 00000060
>[  320.796677] [drm:wait_panel_status [i915]] Wait complete
>[  320.796818] [drm:edp_panel_on [i915]] Wait for panel power on
>[  320.796951] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 00000063
>[  320.830627] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010
>[  320.830708] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  320.830782] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0
>[  320.830898] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  320.998746] [drm:wait_panel_status [i915]] Wait complete
>[  320.998812] [drm:intel_power_well_enable [i915]] enabling DDI A/E IO power well
>[  320.998917] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[  320.999067] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b
>[  321.000305] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  321.000376] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  321.000443] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  321.000508] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  321.001229] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  321.001289] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  321.002288] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  321.002343] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:49:eDP-1] Link Training Passed at Link Rate = 270000, Lane count = 2
>[  321.002978] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  321.003045] [drm:intel_edp_backlight_on [i915]] 
>[  321.003101] [drm:intel_panel_enable_backlight [i915]] pipe A
>[  321.003184] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 120000
>[  321.008143] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS
>[  321.019856] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:49:eDP-1]
>[  321.019935] [drm:intel_atomic_commit_tail [i915]] [CRTC:37:pipe A]
>[  321.020023] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[  321.270119] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped
>[  321.270198] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  321.270293] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  321.270354] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[  321.270457] [drm:intel_edp_backlight_off [i915]] 
>[  321.476327] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0
>[  321.476458] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  321.487943] [drm:intel_edp_panel_off.part.31 [i915]] Turn eDP port A panel power off
>[  321.488103] [drm:intel_edp_panel_off.part.31 [i915]] Wait for panel power off time
>[  321.488247] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000002 control 00000060
>[  321.538265] [drm:wait_panel_status [i915]] Wait complete
>[  321.538329] [drm:intel_power_well_disable [i915]] disabling DDI A/E IO power well
>[  321.538414] [drm:intel_disable_shared_dpll [i915]] disable DPLL 0 (active 1, on? 1) for crtc 37
>[  321.538489] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 0
>[  321.538580] [drm:intel_atomic_commit_tail [i915]] [ENCODER:48:DDI A]
>[  321.538651] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI B]
>[  321.538719] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  321.538783] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  321.538845] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DDI C]
>[  321.538907] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST A]
>[  321.538967] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST B]
>[  321.539028] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI D]
>[  321.539088] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[  321.539146] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[  321.539211] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:49:eDP-1]
>[  321.539278] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[  321.539343] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[  321.539407] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[  321.539467] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[  321.539545] [drm:intel_atomic_commit_tail [i915]] [CRTC:37:pipe A]
>[  321.539610] [drm:intel_power_well_disable [i915]] disabling DC off
>[  321.539665] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  321.539718] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  321.540200] [drm:intel_power_well_disable [i915]] disabling always-on
>[  321.540306] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  321.544369] [drm:drm_mode_addfb2 [drm]] [FB:73]
>[  321.545229] [drm:drm_mode_addfb2 [drm]] [FB:102]
>[  321.546388] [drm:drm_mode_addfb2 [drm]] [FB:103]
>[  321.547220] [drm:drm_mode_addfb2 [drm]] [FB:104]
>[  321.548179] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010
>[  321.548194] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  321.548207] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1
>[  321.548275] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  321.618670] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  321.618677] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  321.618702] [drm:intel_atomic_check [i915]] [CONNECTOR:49:eDP-1] checking for sink bpp constrains
>[  321.618716] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  321.618723] [drm:drm_mode_debug_printmodeline [drm]] Modeline 52:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[  321.618737] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 138780KHz
>[  321.618754] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24
>[  321.618767] [drm:intel_dp_compute_config [i915]] DP link bw required 416340 available 540000
>[  321.618779] [drm:intel_dp_compute_config [i915]] PSR disable by flag
>[  321.618793] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  321.618806] [drm:intel_dump_pipe_config [i915]] [CRTC:37:pipe A][modeset]
>[  321.618819] [drm:intel_dump_pipe_config [i915]] output_types: EDP (0x100)
>[  321.618831] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0
>[  321.618844] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 6467616, gmch_n: 8388608, link_m: 269484, link_n: 524288, tu: 64
>[  321.618855] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  321.618867] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  321.618873] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[  321.618885] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  321.618890] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[  321.618903] [drm:intel_dump_pipe_config [i915]] crtc timings: 138780 1920 1966 1996 2080 1080 1082 1086 1112, type: 0x48 flags: 0xa
>[  321.618914] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 138780
>[  321.618926] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  321.618937] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  321.618948] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  321.618960] [drm:intel_dump_pipe_config [i915]] dpll_hw_state: ctrl1: 0x3, cfgcr1: 0x0, cfgcr2: 0x0
>[  321.618970] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  321.618982] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 1A] disabled, scaler_id = -1
>[  321.618993] [drm:intel_dump_pipe_config [i915]] [PLANE:31:plane 2A] disabled, scaler_id = -1
>[  321.619004] [drm:intel_dump_pipe_config [i915]] [PLANE:34:cursor A] disabled, scaler_id = -1
>[  321.619017] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  321.619029] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[  321.619044] [drm:intel_find_shared_dpll [i915]] [CRTC:37:pipe A] allocated DPLL 0
>[  321.619057] [drm:intel_reference_shared_dpll [i915]] using DPLL 0 for pipe A
>[  321.620038] [drm:intel_power_well_enable [i915]] enabling always-on
>[  321.620066] [drm:intel_power_well_enable [i915]] enabling DC off
>[  321.620343] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  321.620361] [drm:intel_atomic_commit_tail [i915]] [ENCODER:48:DDI A]
>[  321.620373] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI B]
>[  321.620386] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  321.620414] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  321.620426] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DDI C]
>[  321.620438] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST A]
>[  321.620449] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST B]
>[  321.620460] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI D]
>[  321.620471] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[  321.620482] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[  321.620495] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[  321.620508] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[  321.620520] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[  321.620532] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[  321.620546] [drm:intel_enable_shared_dpll [i915]] enable DPLL 0 (active 1, on? 0) for crtc 37
>[  321.620558] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 0
>[  321.620578] [drm:edp_panel_on [i915]] Turn eDP port A panel power on
>[  321.620602] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle
>[  322.172269] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 00000000 control 00000060
>[  322.172367] [drm:wait_panel_status [i915]] Wait complete
>[  322.172496] [drm:edp_panel_on [i915]] Wait for panel power on
>[  322.172618] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 00000063
>[  322.204444] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010
>[  322.204515] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  322.204580] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0
>[  322.204710] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  322.372917] [drm:wait_panel_status [i915]] Wait complete
>[  322.372975] [drm:intel_power_well_enable [i915]] enabling DDI A/E IO power well
>[  322.373067] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[  322.373212] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b
>[  322.374389] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  322.374445] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  322.374498] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  322.374551] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  322.375255] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  322.375307] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  322.376334] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  322.376389] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:49:eDP-1] Link Training Passed at Link Rate = 270000, Lane count = 2
>[  322.377029] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  322.377123] [drm:intel_edp_backlight_on [i915]] 
>[  322.377180] [drm:intel_panel_enable_backlight [i915]] pipe A
>[  322.377263] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 120000
>[  322.384205] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS
>[  322.393933] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:49:eDP-1]
>[  322.394010] [drm:intel_atomic_commit_tail [i915]] [CRTC:37:pipe A]
>[  322.394098] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[  322.644211] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped
>[  322.644256] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  322.644286] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  322.910862] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped
>[  322.910901] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  322.910930] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  323.177526] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped
>[  323.177576] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  323.177606] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  323.444188] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped
>[  323.444317] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  323.444411] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  323.444473] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[  323.444576] [drm:intel_edp_backlight_off [i915]] 
>[  323.652167] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0
>[  323.652298] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  323.660715] [drm:intel_edp_panel_off.part.31 [i915]] Turn eDP port A panel power off
>[  323.660828] [drm:intel_edp_panel_off.part.31 [i915]] Wait for panel power off time
>[  323.660960] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000002 control 00000060
>[  323.711149] [drm:wait_panel_status [i915]] Wait complete
>[  323.711212] [drm:intel_power_well_disable [i915]] disabling DDI A/E IO power well
>[  323.711299] [drm:intel_disable_shared_dpll [i915]] disable DPLL 0 (active 1, on? 1) for crtc 37
>[  323.711390] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 0
>[  323.711474] [drm:intel_atomic_commit_tail [i915]] [ENCODER:48:DDI A]
>[  323.711539] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI B]
>[  323.711600] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  323.711658] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  323.711714] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DDI C]
>[  323.711769] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST A]
>[  323.711824] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST B]
>[  323.711878] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI D]
>[  323.711932] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[  323.711985] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[  323.712077] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:49:eDP-1]
>[  323.712146] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[  323.712212] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[  323.712273] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[  323.712334] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[  323.712410] [drm:intel_atomic_commit_tail [i915]] [CRTC:37:pipe A]
>[  323.712469] [drm:intel_power_well_disable [i915]] disabling DC off
>[  323.712525] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  323.712573] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  323.713013] [drm:intel_power_well_disable [i915]] disabling always-on
>[  323.713102] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  323.713264] Setting dangerous option enable_fbc - tainting kernel
>[  323.714264] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  323.714290] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  323.714378] [drm:intel_atomic_check [i915]] [CONNECTOR:49:eDP-1] checking for sink bpp constrains
>[  323.714430] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  323.714436] [drm:drm_mode_debug_printmodeline [drm]] Modeline 52:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[  323.714450] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 138780KHz
>[  323.714467] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24
>[  323.714480] [drm:intel_dp_compute_config [i915]] DP link bw required 416340 available 540000
>[  323.714492] [drm:intel_dp_compute_config [i915]] PSR disable by flag
>[  323.714505] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  323.714518] [drm:intel_dump_pipe_config [i915]] [CRTC:37:pipe A][modeset]
>[  323.714531] [drm:intel_dump_pipe_config [i915]] output_types: EDP (0x100)
>[  323.714543] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0
>[  323.714555] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 6467616, gmch_n: 8388608, link_m: 269484, link_n: 524288, tu: 64
>[  323.714567] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  323.714578] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  323.714584] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[  323.714595] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  323.714601] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[  323.714613] [drm:intel_dump_pipe_config [i915]] crtc timings: 138780 1920 1966 1996 2080 1080 1082 1086 1112, type: 0x48 flags: 0xa
>[  323.714624] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 138780
>[  323.714636] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  323.714647] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  323.714657] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  323.714669] [drm:intel_dump_pipe_config [i915]] dpll_hw_state: ctrl1: 0x3, cfgcr1: 0x0, cfgcr2: 0x0
>[  323.714679] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  323.714690] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 1A] disabled, scaler_id = -1
>[  323.714701] [drm:intel_dump_pipe_config [i915]] [PLANE:31:plane 2A] disabled, scaler_id = -1
>[  323.714711] [drm:intel_dump_pipe_config [i915]] [PLANE:34:cursor A] disabled, scaler_id = -1
>[  323.714725] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  323.714737] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[  323.714752] [drm:intel_find_shared_dpll [i915]] [CRTC:37:pipe A] allocated DPLL 0
>[  323.714765] [drm:intel_reference_shared_dpll [i915]] using DPLL 0 for pipe A
>[  323.716842] [drm:intel_power_well_enable [i915]] enabling always-on
>[  323.716854] [drm:intel_power_well_enable [i915]] enabling DC off
>[  323.717112] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  323.717130] [drm:intel_atomic_commit_tail [i915]] [ENCODER:48:DDI A]
>[  323.717144] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI B]
>[  323.717158] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  323.717171] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  323.717184] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DDI C]
>[  323.717196] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST A]
>[  323.717208] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST B]
>[  323.717221] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI D]
>[  323.717233] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[  323.717245] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[  323.717258] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[  323.717272] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[  323.717285] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[  323.717298] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[  323.717313] [drm:intel_enable_shared_dpll [i915]] enable DPLL 0 (active 1, on? 0) for crtc 37
>[  323.717327] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 0
>[  323.717348] [drm:edp_panel_on [i915]] Turn eDP port A panel power on
>[  323.717373] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle
>[  323.720495] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010
>[  323.720512] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  323.720528] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0
>[  323.720549] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  324.348451] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 00000000 control 00000060
>[  324.348558] [drm:wait_panel_status [i915]] Wait complete
>[  324.348697] [drm:edp_panel_on [i915]] Wait for panel power on
>[  324.348828] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 00000063
>[  324.381995] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010
>[  324.382077] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  324.382150] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1
>[  324.382293] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  324.549087] [drm:wait_panel_status [i915]] Wait complete
>[  324.549152] [drm:intel_power_well_enable [i915]] enabling DDI A/E IO power well
>[  324.549255] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[  324.549406] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b
>[  324.550610] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  324.550672] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  324.550732] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  324.550791] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  324.551492] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  324.551544] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  324.552505] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  324.552530] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:49:eDP-1] Link Training Passed at Link Rate = 270000, Lane count = 2
>[  324.552908] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  324.552943] [drm:intel_edp_backlight_on [i915]] 
>[  324.552955] [drm:intel_panel_enable_backlight [i915]] pipe A
>[  324.552993] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 120000
>[  324.560136] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS
>[  324.560152] [drm:intel_fbc_enable [i915]] reserved 16588800 bytes of contiguous stolen space for FBC, threshold: 1
>[  324.560166] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  324.569749] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:49:eDP-1]
>[  324.569772] [drm:intel_atomic_commit_tail [i915]] [CRTC:37:pipe A]
>[  324.569801] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[  324.820273] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped
>[  325.070052] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped
>[  325.320058] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped
>[  325.570049] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped
>[  325.820046] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped
>[  325.836499] [IGT] kms_frontbuffer_tracking: exiting, ret=0
>[  325.836553] Setting dangerous option enable_psr - tainting kernel
>[  325.836564] Setting dangerous option enable_fbc - tainting kernel
>[  325.888320] [drm:intel_atomic_check [i915]] [CONNECTOR:57:DP-1] checking for sink bpp constrains
>[  325.888340] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  325.888358] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 148500KHz
>[  325.888377] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  325.888393] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 648000
>[  325.888410] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  325.888427] [drm:intel_dump_pipe_config [i915]] [CRTC:47:pipe B][modeset]
>[  325.888443] [drm:intel_dump_pipe_config [i915]] output_types: DP (0x80)
>[  325.888458] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  325.888474] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5767168, gmch_n: 8388608, link_m: 240298, link_n: 262144, tu: 64
>[  325.888488] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  325.888503] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  325.888512] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  325.888527] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  325.888535] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  325.888550] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  325.888564] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1080, pixel rate 148500
>[  325.888579] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  325.888593] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  325.888607] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  325.888621] [drm:intel_dump_pipe_config [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  325.888634] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  325.888649] [drm:intel_dump_pipe_config [i915]] [PLANE:38:plane 1B] disabled, scaler_id = -1
>[  325.888662] [drm:intel_dump_pipe_config [i915]] [PLANE:41:plane 2B] disabled, scaler_id = -1
>[  325.888676] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor B] disabled, scaler_id = -1
>[  325.888694] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  325.888709] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[  325.888729] [drm:intel_find_shared_dpll [i915]] [CRTC:47:pipe B] allocated DPLL 1
>[  325.888744] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[  325.888770] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  325.888788] [drm:intel_disable_sagv [i915]] Disabling the SAGV
>[  325.888807] [drm:intel_atomic_commit_tail [i915]] [ENCODER:48:DDI A]
>[  325.888840] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI B]
>[  325.888854] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  325.888869] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  325.888883] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DDI C]
>[  325.888898] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST A]
>[  325.888912] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST B]
>[  325.888926] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI D]
>[  325.888939] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[  325.888953] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[  325.888968] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[  325.888984] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[  325.888999] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[  325.889014] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[  325.903182] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 2, on? 0) for crtc 47
>[  325.903207] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  325.903307] [drm:intel_power_well_enable [i915]] enabling DDI B IO power well
>[  325.903875] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  325.904986] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  325.906079] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  325.907166] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  325.908252] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  325.909339] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  325.910423] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  325.911094] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] too many retries, giving up
>[  325.911516] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  325.912541] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  325.913626] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  325.914711] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  325.915798] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  325.916887] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  325.917976] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  325.918641] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] too many retries, giving up
>[  325.920082] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  325.921167] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  325.922257] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  325.923347] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  325.924453] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  325.925544] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  325.926635] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  325.927305] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] too many retries, giving up
>[  325.927749] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  325.928856] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  325.929779] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  325.930887] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  325.931991] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  325.933118] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  325.934226] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  325.934903] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] too many retries, giving up
>[  325.936606] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  325.937883] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  325.939128] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  325.940392] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  325.941264] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  325.942250] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  325.942310] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  325.942365] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  325.942419] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  325.961198] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  325.961263] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  325.979030] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  325.979374] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:57:DP-1] Link Training Passed at Link Rate = 162000, Lane count = 4
>[  325.979810] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  325.979869] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS
>[  325.996618] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:57:DP-1]
>[  325.996653] [drm:intel_atomic_commit_tail [i915]] [CRTC:47:pipe B]
>[  325.996694] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[  326.037006] [IGT] kms_frontbuffer_tracking: executing
>[  326.090938] [drm:drm_mode_addfb2 [drm]] [FB:90]
>[  326.090999] [drm:drm_mode_addfb2 [drm]] [FB:91]
>[  326.091060] [drm:drm_mode_addfb2 [drm]] [FB:92]
>[  326.092338] [drm:drm_mode_addfb2 [drm]] [FB:93]
>[  326.104435] [drm:drm_mode_addfb2 [drm]] [FB:94]
>[  326.107412] [drm:drm_mode_addfb2 [drm]] [FB:96]
>[  326.107476] [drm:drm_mode_addfb2 [drm]] [FB:98]
>[  326.107550] [drm:drm_mode_addfb2 [drm]] [FB:102]
>[  326.107892] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  326.107913] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  326.320012] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped
>[  326.320161] [IGT] kms_frontbuffer_tracking: starting subtest fbc-1p-offscren-pri-indfb-draw-mmap-cpu
>[  326.320236] Setting dangerous option enable_fbc - tainting kernel
>[  326.320258] Setting dangerous option enable_psr - tainting kernel
>[  326.340370] [drm:drm_mode_addfb2 [drm]] [FB:72]
>[  326.340462] [drm:drm_mode_addfb2 [drm]] [FB:90]
>[  326.340560] [drm:drm_mode_addfb2 [drm]] [FB:91]
>[  326.342496] [drm:drm_mode_addfb2 [drm]] [FB:92]
>[  326.358500] [drm:drm_mode_addfb2 [drm]] [FB:93]
>[  326.362264] [drm:drm_mode_addfb2 [drm]] [FB:94]
>[  326.362345] [drm:drm_mode_addfb2 [drm]] [FB:96]
>[  326.362437] [drm:drm_mode_addfb2 [drm]] [FB:98]
>[  326.362655] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  326.362764] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  326.362833] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[  326.362955] [drm:intel_edp_backlight_off [i915]] 
>[  326.568146] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0
>[  326.568268] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  326.569954] [drm:intel_edp_panel_off.part.31 [i915]] Turn eDP port A panel power off
>[  326.570059] [drm:intel_edp_panel_off.part.31 [i915]] Wait for panel power off time
>[  326.570185] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000002 control 00000060
>[  326.620494] [drm:wait_panel_status [i915]] Wait complete
>[  326.620551] [drm:intel_power_well_disable [i915]] disabling DDI A/E IO power well
>[  326.620625] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  326.620695] [drm:intel_disable_shared_dpll [i915]] disable DPLL 0 (active 1, on? 1) for crtc 37
>[  326.620760] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 0
>[  326.620844] [drm:intel_atomic_commit_tail [i915]] [ENCODER:48:DDI A]
>[  326.620908] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI B]
>[  326.620968] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  326.621025] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  326.621080] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DDI C]
>[  326.621134] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST A]
>[  326.621188] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST B]
>[  326.621241] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI D]
>[  326.621294] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[  326.621347] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[  326.621405] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:49:eDP-1]
>[  326.621464] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[  326.621521] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[  326.621579] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[  326.621634] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[  326.629797] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010
>[  326.629868] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  326.629935] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0
>[  326.630054] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  326.630142] [drm:intel_atomic_commit_tail [i915]] [CRTC:37:pipe A]
>[  326.630207] [drm:intel_enable_sagv [i915]] Enabling the SAGV
>[  326.630298] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  326.630391] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  326.630457] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[  326.630555] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  326.647434] [drm:intel_power_well_disable [i915]] disabling DDI B IO power well
>[  326.647510] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 2, on? 1) for crtc 47
>[  326.647575] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  326.647657] [drm:intel_atomic_commit_tail [i915]] [ENCODER:48:DDI A]
>[  326.647717] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI B]
>[  326.647774] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  326.647827] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  326.647879] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DDI C]
>[  326.647929] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST A]
>[  326.647979] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST B]
>[  326.648028] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI D]
>[  326.648108] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[  326.648164] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[  326.648229] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:57:DP-1]
>[  326.648290] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[  326.648351] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[  326.648415] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[  326.648492] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[  326.648580] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  326.648664] [drm:intel_atomic_commit_tail [i915]] [CRTC:47:pipe B]
>[  326.648714] [drm:intel_power_well_disable [i915]] disabling DC off
>[  326.648762] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  326.648807] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  326.649243] [drm:intel_power_well_disable [i915]] disabling always-on
>[  326.652697] [drm:drm_mode_addfb2 [drm]] [FB:73]
>[  326.654363] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  326.654370] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  326.654391] [drm:intel_atomic_check [i915]] [CONNECTOR:49:eDP-1] checking for sink bpp constrains
>[  326.654404] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  326.654410] [drm:drm_mode_debug_printmodeline [drm]] Modeline 52:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[  326.654424] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 138780KHz
>[  326.654440] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24
>[  326.654452] [drm:intel_dp_compute_config [i915]] DP link bw required 416340 available 540000
>[  326.654463] [drm:intel_dp_compute_config [i915]] PSR disable by flag
>[  326.654475] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  326.654488] [drm:intel_dump_pipe_config [i915]] [CRTC:37:pipe A][modeset]
>[  326.654499] [drm:intel_dump_pipe_config [i915]] output_types: EDP (0x100)
>[  326.654511] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0
>[  326.654522] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 6467616, gmch_n: 8388608, link_m: 269484, link_n: 524288, tu: 64
>[  326.654533] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  326.654544] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  326.654550] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[  326.654560] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  326.654566] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[  326.654577] [drm:intel_dump_pipe_config [i915]] crtc timings: 138780 1920 1966 1996 2080 1080 1082 1086 1112, type: 0x48 flags: 0xa
>[  326.654588] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 138780
>[  326.654598] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  326.654609] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  326.654619] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  326.654629] [drm:intel_dump_pipe_config [i915]] dpll_hw_state: ctrl1: 0x3, cfgcr1: 0x0, cfgcr2: 0x0
>[  326.654640] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  326.654650] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 1A] disabled, scaler_id = -1
>[  326.654660] [drm:intel_dump_pipe_config [i915]] [PLANE:31:plane 2A] disabled, scaler_id = -1
>[  326.654670] [drm:intel_dump_pipe_config [i915]] [PLANE:34:cursor A] disabled, scaler_id = -1
>[  326.654683] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  326.654694] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[  326.654708] [drm:intel_find_shared_dpll [i915]] [CRTC:37:pipe A] allocated DPLL 0
>[  326.654720] [drm:intel_reference_shared_dpll [i915]] using DPLL 0 for pipe A
>[  326.655237] [drm:intel_power_well_enable [i915]] enabling always-on
>[  326.655246] [drm:intel_power_well_enable [i915]] enabling DC off
>[  326.655521] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  326.655539] [drm:intel_atomic_commit_tail [i915]] [ENCODER:48:DDI A]
>[  326.655552] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI B]
>[  326.655565] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  326.655578] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  326.655590] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DDI C]
>[  326.655604] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST A]
>[  326.655621] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST B]
>[  326.655639] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI D]
>[  326.655656] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[  326.655690] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[  326.655703] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[  326.655715] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[  326.655727] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[  326.655738] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[  326.655752] [drm:intel_enable_shared_dpll [i915]] enable DPLL 0 (active 1, on? 0) for crtc 37
>[  326.655763] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 0
>[  326.655783] [drm:edp_panel_on [i915]] Turn eDP port A panel power on
>[  326.655807] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle
>[  327.228564] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 00000000 control 00000060
>[  327.228672] [drm:wait_panel_status [i915]] Wait complete
>[  327.228811] [drm:edp_panel_on [i915]] Wait for panel power on
>[  327.228946] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 00000063
>[  327.262682] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010
>[  327.262764] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  327.262839] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1
>[  327.262988] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  327.429210] [drm:wait_panel_status [i915]] Wait complete
>[  327.429275] [drm:intel_power_well_enable [i915]] enabling DDI A/E IO power well
>[  327.429378] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[  327.429526] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b
>[  327.430726] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  327.430788] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  327.430846] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  327.430906] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  327.431614] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  327.431672] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  327.432691] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  327.432753] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:49:eDP-1] Link Training Passed at Link Rate = 270000, Lane count = 2
>[  327.433420] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  327.433509] [drm:intel_edp_backlight_on [i915]] 
>[  327.433566] [drm:intel_panel_enable_backlight [i915]] pipe A
>[  327.433649] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 120000
>[  327.440152] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS
>[  327.450299] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:49:eDP-1]
>[  327.450376] [drm:intel_atomic_commit_tail [i915]] [CRTC:37:pipe A]
>[  327.450463] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[  327.700588] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped
>[  327.700670] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  327.700764] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  327.700826] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[  327.700928] [drm:intel_edp_backlight_off [i915]] 
>[  327.908169] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0
>[  327.908299] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  327.919780] [drm:intel_edp_panel_off.part.31 [i915]] Turn eDP port A panel power off
>[  327.919892] [drm:intel_edp_panel_off.part.31 [i915]] Wait for panel power off time
>[  327.920023] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000002 control 00000060
>[  327.971454] [drm:wait_panel_status [i915]] Wait complete
>[  327.971517] [drm:intel_power_well_disable [i915]] disabling DDI A/E IO power well
>[  327.971603] [drm:intel_disable_shared_dpll [i915]] disable DPLL 0 (active 1, on? 1) for crtc 37
>[  327.971678] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 0
>[  327.971771] [drm:intel_atomic_commit_tail [i915]] [ENCODER:48:DDI A]
>[  327.971843] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI B]
>[  327.971909] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  327.971973] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  327.972037] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DDI C]
>[  327.972135] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST A]
>[  327.972204] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST B]
>[  327.972275] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI D]
>[  327.972342] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[  327.972407] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[  327.972481] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:49:eDP-1]
>[  327.972552] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[  327.972618] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[  327.972687] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[  327.972754] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[  327.972834] [drm:intel_atomic_commit_tail [i915]] [CRTC:37:pipe A]
>[  327.972899] [drm:intel_power_well_disable [i915]] disabling DC off
>[  327.972956] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  327.973011] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  327.973456] [drm:intel_power_well_disable [i915]] disabling always-on
>[  327.973554] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  327.976148] [drm:drm_mode_addfb2 [drm]] [FB:73]
>[  327.977015] [drm:drm_mode_addfb2 [drm]] [FB:102]
>[  327.978164] [drm:drm_mode_addfb2 [drm]] [FB:103]
>[  327.979002] [drm:drm_mode_addfb2 [drm]] [FB:104]
>[  327.979994] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010
>[  327.980025] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  327.980040] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0
>[  327.980447] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  328.051307] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  328.051314] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  328.051338] [drm:intel_atomic_check [i915]] [CONNECTOR:49:eDP-1] checking for sink bpp constrains
>[  328.051352] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  328.051359] [drm:drm_mode_debug_printmodeline [drm]] Modeline 52:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[  328.051374] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 138780KHz
>[  328.051391] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24
>[  328.051404] [drm:intel_dp_compute_config [i915]] DP link bw required 416340 available 540000
>[  328.051416] [drm:intel_dp_compute_config [i915]] PSR disable by flag
>[  328.051430] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  328.051443] [drm:intel_dump_pipe_config [i915]] [CRTC:37:pipe A][modeset]
>[  328.051456] [drm:intel_dump_pipe_config [i915]] output_types: EDP (0x100)
>[  328.051468] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0
>[  328.051480] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 6467616, gmch_n: 8388608, link_m: 269484, link_n: 524288, tu: 64
>[  328.051491] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  328.051503] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  328.051509] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[  328.051520] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  328.051526] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[  328.051538] [drm:intel_dump_pipe_config [i915]] crtc timings: 138780 1920 1966 1996 2080 1080 1082 1086 1112, type: 0x48 flags: 0xa
>[  328.051550] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 138780
>[  328.051561] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  328.051572] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  328.051583] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  328.051594] [drm:intel_dump_pipe_config [i915]] dpll_hw_state: ctrl1: 0x3, cfgcr1: 0x0, cfgcr2: 0x0
>[  328.051605] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  328.051616] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 1A] disabled, scaler_id = -1
>[  328.051627] [drm:intel_dump_pipe_config [i915]] [PLANE:31:plane 2A] disabled, scaler_id = -1
>[  328.051638] [drm:intel_dump_pipe_config [i915]] [PLANE:34:cursor A] disabled, scaler_id = -1
>[  328.051651] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  328.051663] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[  328.051679] [drm:intel_find_shared_dpll [i915]] [CRTC:37:pipe A] allocated DPLL 0
>[  328.051692] [drm:intel_reference_shared_dpll [i915]] using DPLL 0 for pipe A
>[  328.052726] [drm:intel_power_well_enable [i915]] enabling always-on
>[  328.052736] [drm:intel_power_well_enable [i915]] enabling DC off
>[  328.052994] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  328.053012] [drm:intel_atomic_commit_tail [i915]] [ENCODER:48:DDI A]
>[  328.053024] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI B]
>[  328.053036] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  328.053048] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  328.053059] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DDI C]
>[  328.053071] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST A]
>[  328.053082] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST B]
>[  328.053093] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI D]
>[  328.053104] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[  328.053115] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[  328.053127] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[  328.053139] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[  328.053151] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[  328.053162] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[  328.053176] [drm:intel_enable_shared_dpll [i915]] enable DPLL 0 (active 1, on? 0) for crtc 37
>[  328.053188] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 0
>[  328.053208] [drm:edp_panel_on [i915]] Turn eDP port A panel power on
>[  328.053232] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle
>[  328.604272] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 00000000 control 00000060
>[  328.604371] [drm:wait_panel_status [i915]] Wait complete
>[  328.604503] [drm:edp_panel_on [i915]] Wait for panel power on
>[  328.604627] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 00000063
>[  328.636429] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010
>[  328.636501] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  328.636569] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1
>[  328.636669] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  328.807013] [drm:wait_panel_status [i915]] Wait complete
>[  328.807071] [drm:intel_power_well_enable [i915]] enabling DDI A/E IO power well
>[  328.807163] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[  328.807306] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b
>[  328.808518] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  328.808584] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  328.808643] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  328.808700] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  328.809403] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  328.809456] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  328.810455] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  328.810510] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:49:eDP-1] Link Training Passed at Link Rate = 270000, Lane count = 2
>[  328.811146] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  328.811213] [drm:intel_edp_backlight_on [i915]] 
>[  328.811269] [drm:intel_panel_enable_backlight [i915]] pipe A
>[  328.811352] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 120000
>[  328.816206] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS
>[  328.828021] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:49:eDP-1]
>[  328.828121] [drm:intel_atomic_commit_tail [i915]] [CRTC:37:pipe A]
>[  328.828223] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[  329.078284] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped
>[  329.078333] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  329.078363] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  329.344930] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped
>[  329.344968] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  329.344996] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  329.611598] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped
>[  329.611648] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  329.611679] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  329.878431] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped
>[  329.878568] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  329.878663] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  329.878725] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[  329.878828] [drm:intel_edp_backlight_off [i915]] 
>[  330.084323] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0
>[  330.084455] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  330.095648] [drm:intel_edp_panel_off.part.31 [i915]] Turn eDP port A panel power off
>[  330.095762] [drm:intel_edp_panel_off.part.31 [i915]] Wait for panel power off time
>[  330.095895] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000003 control 00000060
>[  330.146356] [drm:wait_panel_status [i915]] Wait complete
>[  330.146420] [drm:intel_power_well_disable [i915]] disabling DDI A/E IO power well
>[  330.146507] [drm:intel_disable_shared_dpll [i915]] disable DPLL 0 (active 1, on? 1) for crtc 37
>[  330.146582] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 0
>[  330.146675] [drm:intel_atomic_commit_tail [i915]] [ENCODER:48:DDI A]
>[  330.146746] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI B]
>[  330.146812] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  330.146875] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  330.146937] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DDI C]
>[  330.146998] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST A]
>[  330.147058] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST B]
>[  330.147117] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI D]
>[  330.147178] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[  330.147236] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[  330.147302] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:49:eDP-1]
>[  330.147368] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[  330.147432] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[  330.147495] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[  330.147556] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[  330.147634] [drm:intel_atomic_commit_tail [i915]] [CRTC:37:pipe A]
>[  330.147699] [drm:intel_power_well_disable [i915]] disabling DC off
>[  330.147755] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  330.147808] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  330.148300] [drm:intel_power_well_disable [i915]] disabling always-on
>[  330.148415] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  330.148590] Setting dangerous option enable_fbc - tainting kernel
>[  330.149585] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  330.149590] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  330.149610] [drm:intel_atomic_check [i915]] [CONNECTOR:49:eDP-1] checking for sink bpp constrains
>[  330.149623] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  330.149630] [drm:drm_mode_debug_printmodeline [drm]] Modeline 52:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[  330.149644] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 138780KHz
>[  330.149661] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24
>[  330.149673] [drm:intel_dp_compute_config [i915]] DP link bw required 416340 available 540000
>[  330.149686] [drm:intel_dp_compute_config [i915]] PSR disable by flag
>[  330.149699] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  330.149712] [drm:intel_dump_pipe_config [i915]] [CRTC:37:pipe A][modeset]
>[  330.149724] [drm:intel_dump_pipe_config [i915]] output_types: EDP (0x100)
>[  330.149736] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0
>[  330.149749] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 6467616, gmch_n: 8388608, link_m: 269484, link_n: 524288, tu: 64
>[  330.149760] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  330.149771] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  330.149777] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[  330.149789] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  330.149795] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[  330.149807] [drm:intel_dump_pipe_config [i915]] crtc timings: 138780 1920 1966 1996 2080 1080 1082 1086 1112, type: 0x48 flags: 0xa
>[  330.149818] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 138780
>[  330.149830] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  330.149841] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  330.149852] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  330.149863] [drm:intel_dump_pipe_config [i915]] dpll_hw_state: ctrl1: 0x3, cfgcr1: 0x0, cfgcr2: 0x0
>[  330.149874] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  330.149885] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 1A] disabled, scaler_id = -1
>[  330.149896] [drm:intel_dump_pipe_config [i915]] [PLANE:31:plane 2A] disabled, scaler_id = -1
>[  330.149907] [drm:intel_dump_pipe_config [i915]] [PLANE:34:cursor A] disabled, scaler_id = -1
>[  330.149920] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  330.149932] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[  330.149947] [drm:intel_find_shared_dpll [i915]] [CRTC:37:pipe A] allocated DPLL 0
>[  330.149960] [drm:intel_reference_shared_dpll [i915]] using DPLL 0 for pipe A
>[  330.152324] [drm:intel_power_well_enable [i915]] enabling always-on
>[  330.152334] [drm:intel_power_well_enable [i915]] enabling DC off
>[  330.152591] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  330.152609] [drm:intel_atomic_commit_tail [i915]] [ENCODER:48:DDI A]
>[  330.152622] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI B]
>[  330.152634] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  330.152645] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  330.152657] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DDI C]
>[  330.152668] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST A]
>[  330.152678] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST B]
>[  330.152689] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI D]
>[  330.152699] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[  330.152709] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[  330.152721] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[  330.152733] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[  330.152744] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[  330.152755] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[  330.152768] [drm:intel_enable_shared_dpll [i915]] enable DPLL 0 (active 1, on? 0) for crtc 37
>[  330.152779] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 0
>[  330.152798] [drm:edp_panel_on [i915]] Turn eDP port A panel power on
>[  330.152822] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle
>[  330.156317] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010
>[  330.156334] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  330.156349] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0
>[  330.156403] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  330.780478] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 00000000 control 00000060
>[  330.780584] [drm:wait_panel_status [i915]] Wait complete
>[  330.780722] [drm:edp_panel_on [i915]] Wait for panel power on
>[  330.780852] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 00000063
>[  330.814588] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010
>[  330.814669] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  330.814743] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1
>[  330.814886] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  330.981107] [drm:wait_panel_status [i915]] Wait complete
>[  330.981173] [drm:intel_power_well_enable [i915]] enabling DDI A/E IO power well
>[  330.981275] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[  330.981423] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b
>[  330.982637] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  330.982692] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  330.982744] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  330.982797] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  330.983485] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  330.983510] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  330.984492] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  330.984518] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:49:eDP-1] Link Training Passed at Link Rate = 270000, Lane count = 2
>[  330.984896] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  330.984931] [drm:intel_edp_backlight_on [i915]] 
>[  330.984943] [drm:intel_panel_enable_backlight [i915]] pipe A
>[  330.984981] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 120000
>[  330.992147] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS
>[  330.992210] [drm:intel_fbc_enable [i915]] reserved 16588800 bytes of contiguous stolen space for FBC, threshold: 1
>[  330.992266] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  331.001779] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:49:eDP-1]
>[  331.001855] [drm:intel_atomic_commit_tail [i915]] [CRTC:37:pipe A]
>[  331.001941] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[  331.252260] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped
>[  331.502051] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped
>[  331.752036] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped
>[  332.002037] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped
>[  332.252023] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped
>[  332.268500] [IGT] kms_frontbuffer_tracking: exiting, ret=0
>[  332.268559] Setting dangerous option enable_psr - tainting kernel
>[  332.268572] Setting dangerous option enable_fbc - tainting kernel
>[  332.328326] [drm:intel_atomic_check [i915]] [CONNECTOR:57:DP-1] checking for sink bpp constrains
>[  332.328349] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  332.328371] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 148500KHz
>[  332.328394] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  332.328413] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 648000
>[  332.328434] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  332.328454] [drm:intel_dump_pipe_config [i915]] [CRTC:47:pipe B][modeset]
>[  332.328473] [drm:intel_dump_pipe_config [i915]] output_types: DP (0x80)
>[  332.328492] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  332.328511] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5767168, gmch_n: 8388608, link_m: 240298, link_n: 262144, tu: 64
>[  332.328529] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  332.328546] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  332.328558] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  332.328576] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  332.328584] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  332.328603] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  332.328621] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1080, pixel rate 148500
>[  332.328638] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  332.328656] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  332.328672] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  332.328689] [drm:intel_dump_pipe_config [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  332.328706] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  332.328723] [drm:intel_dump_pipe_config [i915]] [PLANE:38:plane 1B] disabled, scaler_id = -1
>[  332.328740] [drm:intel_dump_pipe_config [i915]] [PLANE:41:plane 2B] disabled, scaler_id = -1
>[  332.328756] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor B] disabled, scaler_id = -1
>[  332.328777] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  332.328796] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[  332.328819] [drm:intel_find_shared_dpll [i915]] [CRTC:47:pipe B] allocated DPLL 1
>[  332.328838] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[  332.328869] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  332.328891] [drm:intel_disable_sagv [i915]] Disabling the SAGV
>[  332.328913] [drm:intel_atomic_commit_tail [i915]] [ENCODER:48:DDI A]
>[  332.328958] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI B]
>[  332.328976] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  332.328994] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  332.329011] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DDI C]
>[  332.329028] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST A]
>[  332.329045] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST B]
>[  332.329061] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI D]
>[  332.329078] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[  332.329094] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[  332.329113] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[  332.329132] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[  332.329150] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[  332.329168] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[  332.335152] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 2, on? 0) for crtc 47
>[  332.335180] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  332.335284] [drm:intel_power_well_enable [i915]] enabling DDI B IO power well
>[  332.335855] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  332.336944] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  332.338030] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  332.339098] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  332.340185] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  332.341271] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  332.342356] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  332.343023] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] too many retries, giving up
>[  332.343448] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  332.344532] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  332.345616] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  332.346702] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  332.347789] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  332.348877] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  332.349968] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  332.350635] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] too many retries, giving up
>[  332.352088] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  332.353186] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  332.354277] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  332.355379] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  332.356514] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  332.357619] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  332.358724] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  332.359419] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] too many retries, giving up
>[  332.359865] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  332.360974] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  332.362083] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  332.363189] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  332.364294] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  332.365401] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  332.366507] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  332.367180] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] too many retries, giving up
>[  332.368748] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  332.370003] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  332.371250] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  332.372528] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  332.373400] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  332.374386] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  332.374446] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  332.374501] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  332.374555] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  332.393310] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  332.393377] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  332.411146] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  332.411490] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:57:DP-1] Link Training Passed at Link Rate = 162000, Lane count = 4
>[  332.411926] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  332.411986] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS
>[  332.428761] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:57:DP-1]
>[  332.428791] [drm:intel_atomic_commit_tail [i915]] [CRTC:47:pipe B]
>[  332.428827] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[  332.467711] [IGT] kms_frontbuffer_tracking: executing
>[  332.524451] [drm:drm_mode_addfb2 [drm]] [FB:90]
>[  332.524545] [drm:drm_mode_addfb2 [drm]] [FB:91]
>[  332.524640] [drm:drm_mode_addfb2 [drm]] [FB:92]
>[  332.526563] [drm:drm_mode_addfb2 [drm]] [FB:93]
>[  332.542254] [drm:drm_mode_addfb2 [drm]] [FB:94]
>[  332.546004] [drm:drm_mode_addfb2 [drm]] [FB:96]
>[  332.546084] [drm:drm_mode_addfb2 [drm]] [FB:98]
>[  332.546180] [drm:drm_mode_addfb2 [drm]] [FB:102]
>[  332.546580] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  332.546608] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  332.752003] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped
>[  332.752156] [IGT] kms_frontbuffer_tracking: starting subtest fbc-1p-offscren-pri-indfb-draw-mmap-gtt
>[  332.752230] Setting dangerous option enable_fbc - tainting kernel
>[  332.752252] Setting dangerous option enable_psr - tainting kernel
>[  332.772271] [drm:drm_mode_addfb2 [drm]] [FB:72]
>[  332.772364] [drm:drm_mode_addfb2 [drm]] [FB:90]
>[  332.772462] [drm:drm_mode_addfb2 [drm]] [FB:91]
>[  332.774391] [drm:drm_mode_addfb2 [drm]] [FB:92]
>[  332.790373] [drm:drm_mode_addfb2 [drm]] [FB:93]
>[  332.794140] [drm:drm_mode_addfb2 [drm]] [FB:94]
>[  332.794222] [drm:drm_mode_addfb2 [drm]] [FB:96]
>[  332.794314] [drm:drm_mode_addfb2 [drm]] [FB:98]
>[  332.794533] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  332.794642] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  332.794710] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[  332.794833] [drm:intel_edp_backlight_off [i915]] 
>[  333.000163] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0
>[  333.000286] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  333.001975] [drm:intel_edp_panel_off.part.31 [i915]] Turn eDP port A panel power off
>[  333.002080] [drm:intel_edp_panel_off.part.31 [i915]] Wait for panel power off time
>[  333.002204] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000003 control 00000060
>[  333.052401] [drm:wait_panel_status [i915]] Wait complete
>[  333.052458] [drm:intel_power_well_disable [i915]] disabling DDI A/E IO power well
>[  333.052531] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  333.052604] [drm:intel_disable_shared_dpll [i915]] disable DPLL 0 (active 1, on? 1) for crtc 37
>[  333.052668] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 0
>[  333.052751] [drm:intel_atomic_commit_tail [i915]] [ENCODER:48:DDI A]
>[  333.052814] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI B]
>[  333.052873] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  333.052930] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  333.052985] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DDI C]
>[  333.053040] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST A]
>[  333.053094] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST B]
>[  333.053148] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI D]
>[  333.053202] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[  333.053255] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[  333.053313] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:49:eDP-1]
>[  333.053373] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[  333.053430] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[  333.053487] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[  333.053542] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[  333.062040] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010
>[  333.062113] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  333.062179] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0
>[  333.062307] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  333.062396] [drm:intel_atomic_commit_tail [i915]] [CRTC:37:pipe A]
>[  333.062460] [drm:intel_enable_sagv [i915]] Enabling the SAGV
>[  333.062551] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  333.062644] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  333.062710] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[  333.062805] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  333.079569] [drm:intel_power_well_disable [i915]] disabling DDI B IO power well
>[  333.079645] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 2, on? 1) for crtc 47
>[  333.079711] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  333.079791] [drm:intel_atomic_commit_tail [i915]] [ENCODER:48:DDI A]
>[  333.079849] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI B]
>[  333.079906] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  333.079958] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  333.080009] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DDI C]
>[  333.080093] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST A]
>[  333.080152] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST B]
>[  333.080211] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI D]
>[  333.080266] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[  333.080320] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[  333.080387] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:57:DP-1]
>[  333.080471] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[  333.080557] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[  333.080615] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[  333.080669] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[  333.080723] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  333.080788] [drm:intel_atomic_commit_tail [i915]] [CRTC:47:pipe B]
>[  333.080838] [drm:intel_power_well_disable [i915]] disabling DC off
>[  333.080885] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  333.080930] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  333.081365] [drm:intel_power_well_disable [i915]] disabling always-on
>[  333.083832] [drm:drm_mode_addfb2 [drm]] [FB:73]
>[  333.085560] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  333.085566] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  333.085588] [drm:intel_atomic_check [i915]] [CONNECTOR:49:eDP-1] checking for sink bpp constrains
>[  333.085601] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  333.085607] [drm:drm_mode_debug_printmodeline [drm]] Modeline 52:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[  333.085621] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 138780KHz
>[  333.085636] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24
>[  333.085648] [drm:intel_dp_compute_config [i915]] DP link bw required 416340 available 540000
>[  333.085659] [drm:intel_dp_compute_config [i915]] PSR disable by flag
>[  333.085672] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  333.085684] [drm:intel_dump_pipe_config [i915]] [CRTC:37:pipe A][modeset]
>[  333.085696] [drm:intel_dump_pipe_config [i915]] output_types: EDP (0x100)
>[  333.085707] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0
>[  333.085718] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 6467616, gmch_n: 8388608, link_m: 269484, link_n: 524288, tu: 64
>[  333.085729] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  333.085739] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  333.085745] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[  333.085756] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  333.085761] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[  333.085772] [drm:intel_dump_pipe_config [i915]] crtc timings: 138780 1920 1966 1996 2080 1080 1082 1086 1112, type: 0x48 flags: 0xa
>[  333.085783] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 138780
>[  333.085793] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  333.085803] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  333.085813] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  333.085824] [drm:intel_dump_pipe_config [i915]] dpll_hw_state: ctrl1: 0x3, cfgcr1: 0x0, cfgcr2: 0x0
>[  333.085834] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  333.085844] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 1A] disabled, scaler_id = -1
>[  333.085854] [drm:intel_dump_pipe_config [i915]] [PLANE:31:plane 2A] disabled, scaler_id = -1
>[  333.085864] [drm:intel_dump_pipe_config [i915]] [PLANE:34:cursor A] disabled, scaler_id = -1
>[  333.085876] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  333.085888] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[  333.085902] [drm:intel_find_shared_dpll [i915]] [CRTC:37:pipe A] allocated DPLL 0
>[  333.085913] [drm:intel_reference_shared_dpll [i915]] using DPLL 0 for pipe A
>[  333.086436] [drm:intel_power_well_enable [i915]] enabling always-on
>[  333.086446] [drm:intel_power_well_enable [i915]] enabling DC off
>[  333.086720] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  333.086737] [drm:intel_atomic_commit_tail [i915]] [ENCODER:48:DDI A]
>[  333.086751] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI B]
>[  333.086764] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  333.086776] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  333.086788] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DDI C]
>[  333.086800] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST A]
>[  333.086815] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST B]
>[  333.086831] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI D]
>[  333.086847] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[  333.086864] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[  333.086899] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[  333.086917] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[  333.086928] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[  333.086939] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[  333.086953] [drm:intel_enable_shared_dpll [i915]] enable DPLL 0 (active 1, on? 0) for crtc 37
>[  333.086964] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 0
>[  333.086983] [drm:edp_panel_on [i915]] Turn eDP port A panel power on
>[  333.087007] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle
>[  333.660559] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 00000000 control 00000060
>[  333.660666] [drm:wait_panel_status [i915]] Wait complete
>[  333.660804] [drm:edp_panel_on [i915]] Wait for panel power on
>[  333.660936] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 00000063
>[  333.694285] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010
>[  333.694366] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  333.694441] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1
>[  333.694578] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  333.863268] [drm:wait_panel_status [i915]] Wait complete
>[  333.863334] [drm:intel_power_well_enable [i915]] enabling DDI A/E IO power well
>[  333.863436] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[  333.863587] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b
>[  333.864794] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  333.864857] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  333.864917] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  333.864977] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  333.865688] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  333.865746] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  333.866743] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  333.866797] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:49:eDP-1] Link Training Passed at Link Rate = 270000, Lane count = 2
>[  333.867431] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  333.867499] [drm:intel_edp_backlight_on [i915]] 
>[  333.867556] [drm:intel_panel_enable_backlight [i915]] pipe A
>[  333.867639] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 120000
>[  333.876133] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS
>[  333.884271] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:49:eDP-1]
>[  333.884349] [drm:intel_atomic_commit_tail [i915]] [CRTC:37:pipe A]
>[  333.884434] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[  334.134577] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped
>[  334.134655] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  334.134748] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  334.134810] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[  334.134911] [drm:intel_edp_backlight_off [i915]] 
>[  334.340154] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0
>[  334.340287] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  334.351418] [drm:intel_edp_panel_off.part.31 [i915]] Turn eDP port A panel power off
>[  334.351524] [drm:intel_edp_panel_off.part.31 [i915]] Wait for panel power off time
>[  334.351647] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000003 control 00000060
>[  334.404282] [drm:wait_panel_status [i915]] Wait complete
>[  334.404340] [drm:intel_power_well_disable [i915]] disabling DDI A/E IO power well
>[  334.404417] [drm:intel_disable_shared_dpll [i915]] disable DPLL 0 (active 1, on? 1) for crtc 37
>[  334.404483] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 0
>[  334.404567] [drm:intel_atomic_commit_tail [i915]] [ENCODER:48:DDI A]
>[  334.404631] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI B]
>[  334.404690] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  334.404749] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  334.404805] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DDI C]
>[  334.404860] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST A]
>[  334.404915] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST B]
>[  334.404969] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI D]
>[  334.405021] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[  334.405073] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[  334.405132] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:49:eDP-1]
>[  334.405192] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[  334.405251] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[  334.405308] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[  334.405363] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[  334.405433] [drm:intel_atomic_commit_tail [i915]] [CRTC:37:pipe A]
>[  334.405491] [drm:intel_power_well_disable [i915]] disabling DC off
>[  334.405540] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  334.405587] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  334.406025] [drm:intel_power_well_disable [i915]] disabling always-on
>[  334.406119] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  334.410716] [drm:drm_mode_addfb2 [drm]] [FB:73]
>[  334.411755] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010
>[  334.411827] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  334.412177] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0
>[  334.412225] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  334.413096] [drm:drm_mode_addfb2 [drm]] [FB:102]
>[  334.413933] [drm:drm_mode_addfb2 [drm]] [FB:103]
>[  334.415103] [drm:drm_mode_addfb2 [drm]] [FB:104]
>[  334.486858] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  334.486865] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  334.486893] [drm:intel_atomic_check [i915]] [CONNECTOR:49:eDP-1] checking for sink bpp constrains
>[  334.486907] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  334.486914] [drm:drm_mode_debug_printmodeline [drm]] Modeline 52:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[  334.486929] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 138780KHz
>[  334.486946] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24
>[  334.486958] [drm:intel_dp_compute_config [i915]] DP link bw required 416340 available 540000
>[  334.486971] [drm:intel_dp_compute_config [i915]] PSR disable by flag
>[  334.486984] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  334.486997] [drm:intel_dump_pipe_config [i915]] [CRTC:37:pipe A][modeset]
>[  334.487010] [drm:intel_dump_pipe_config [i915]] output_types: EDP (0x100)
>[  334.487023] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0
>[  334.487035] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 6467616, gmch_n: 8388608, link_m: 269484, link_n: 524288, tu: 64
>[  334.487047] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  334.487058] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  334.487064] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[  334.487076] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  334.487081] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[  334.487094] [drm:intel_dump_pipe_config [i915]] crtc timings: 138780 1920 1966 1996 2080 1080 1082 1086 1112, type: 0x48 flags: 0xa
>[  334.487105] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 138780
>[  334.487116] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  334.487128] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  334.487139] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  334.487150] [drm:intel_dump_pipe_config [i915]] dpll_hw_state: ctrl1: 0x3, cfgcr1: 0x0, cfgcr2: 0x0
>[  334.487161] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  334.487172] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 1A] disabled, scaler_id = -1
>[  334.487183] [drm:intel_dump_pipe_config [i915]] [PLANE:31:plane 2A] disabled, scaler_id = -1
>[  334.487194] [drm:intel_dump_pipe_config [i915]] [PLANE:34:cursor A] disabled, scaler_id = -1
>[  334.487207] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  334.487219] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[  334.487235] [drm:intel_find_shared_dpll [i915]] [CRTC:37:pipe A] allocated DPLL 0
>[  334.487247] [drm:intel_reference_shared_dpll [i915]] using DPLL 0 for pipe A
>[  334.488255] [drm:intel_power_well_enable [i915]] enabling always-on
>[  334.488265] [drm:intel_power_well_enable [i915]] enabling DC off
>[  334.488523] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  334.488541] [drm:intel_atomic_commit_tail [i915]] [ENCODER:48:DDI A]
>[  334.488553] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI B]
>[  334.488566] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  334.488578] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  334.488589] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DDI C]
>[  334.488600] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST A]
>[  334.488612] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST B]
>[  334.488623] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI D]
>[  334.488634] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[  334.488645] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[  334.488657] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[  334.488670] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[  334.488682] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[  334.488693] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[  334.488707] [drm:intel_enable_shared_dpll [i915]] enable DPLL 0 (active 1, on? 0) for crtc 37
>[  334.488719] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 0
>[  334.488739] [drm:edp_panel_on [i915]] Turn eDP port A panel power on
>[  334.488765] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle
>[  335.036549] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 00000000 control 00000060
>[  335.036657] [drm:wait_panel_status [i915]] Wait complete
>[  335.036796] [drm:edp_panel_on [i915]] Wait for panel power on
>[  335.036926] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 00000063
>[  335.070629] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010
>[  335.070710] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  335.070784] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1
>[  335.070897] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  335.237607] [drm:wait_panel_status [i915]] Wait complete
>[  335.237673] [drm:intel_power_well_enable [i915]] enabling DDI A/E IO power well
>[  335.237777] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[  335.237927] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b
>[  335.239165] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  335.239237] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  335.239302] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  335.239366] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  335.240130] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  335.240211] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  335.241248] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  335.241316] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:49:eDP-1] Link Training Passed at Link Rate = 270000, Lane count = 2
>[  335.241976] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  335.242068] [drm:intel_edp_backlight_on [i915]] 
>[  335.242125] [drm:intel_panel_enable_backlight [i915]] pipe A
>[  335.242208] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 120000
>[  335.248204] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS
>[  335.258873] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:49:eDP-1]
>[  335.258950] [drm:intel_atomic_commit_tail [i915]] [CRTC:37:pipe A]
>[  335.259037] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[  335.509131] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped
>[  335.509180] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  335.509211] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  335.775794] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped
>[  335.775843] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  335.775874] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  336.042462] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped
>[  336.042512] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  336.042543] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  336.309115] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped
>[  336.309248] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  336.309343] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  336.309404] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[  336.309505] [drm:intel_edp_backlight_off [i915]] 
>[  336.516421] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0
>[  336.516552] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  336.527722] [drm:intel_edp_panel_off.part.31 [i915]] Turn eDP port A panel power off
>[  336.527834] [drm:intel_edp_panel_off.part.31 [i915]] Wait for panel power off time
>[  336.527965] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000003 control 00000060
>[  336.578445] [drm:wait_panel_status [i915]] Wait complete
>[  336.578509] [drm:intel_power_well_disable [i915]] disabling DDI A/E IO power well
>[  336.578595] [drm:intel_disable_shared_dpll [i915]] disable DPLL 0 (active 1, on? 1) for crtc 37
>[  336.578670] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 0
>[  336.578761] [drm:intel_atomic_commit_tail [i915]] [ENCODER:48:DDI A]
>[  336.578833] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI B]
>[  336.578898] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  336.578962] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  336.579025] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DDI C]
>[  336.579086] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST A]
>[  336.579146] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST B]
>[  336.579206] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI D]
>[  336.579264] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[  336.579322] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[  336.579387] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:49:eDP-1]
>[  336.579453] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[  336.579518] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[  336.579581] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[  336.579642] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[  336.579718] [drm:intel_atomic_commit_tail [i915]] [CRTC:37:pipe A]
>[  336.579782] [drm:intel_power_well_disable [i915]] disabling DC off
>[  336.579838] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  336.579891] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  336.580369] [drm:intel_power_well_disable [i915]] disabling always-on
>[  336.580481] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  336.580711] Setting dangerous option enable_fbc - tainting kernel
>[  336.581724] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  336.581750] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  336.581836] [drm:intel_atomic_check [i915]] [CONNECTOR:49:eDP-1] checking for sink bpp constrains
>[  336.581896] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  336.581925] [drm:drm_mode_debug_printmodeline [drm]] Modeline 52:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[  336.581987] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 138780KHz
>[  336.582061] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24
>[  336.582117] [drm:intel_dp_compute_config [i915]] DP link bw required 416340 available 540000
>[  336.582170] [drm:intel_dp_compute_config [i915]] PSR disable by flag
>[  336.582229] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  336.582288] [drm:intel_dump_pipe_config [i915]] [CRTC:37:pipe A][modeset]
>[  336.582344] [drm:intel_dump_pipe_config [i915]] output_types: EDP (0x100)
>[  336.582398] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0
>[  336.582452] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 6467616, gmch_n: 8388608, link_m: 269484, link_n: 524288, tu: 64
>[  336.582504] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  336.582555] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  336.582582] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[  336.582633] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  336.582658] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[  336.582712] [drm:intel_dump_pipe_config [i915]] crtc timings: 138780 1920 1966 1996 2080 1080 1082 1086 1112, type: 0x48 flags: 0xa
>[  336.582764] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 138780
>[  336.582815] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  336.582865] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  336.582922] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  336.582972] [drm:intel_dump_pipe_config [i915]] dpll_hw_state: ctrl1: 0x3, cfgcr1: 0x0, cfgcr2: 0x0
>[  336.583021] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  336.583070] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 1A] disabled, scaler_id = -1
>[  336.583119] [drm:intel_dump_pipe_config [i915]] [PLANE:31:plane 2A] disabled, scaler_id = -1
>[  336.583168] [drm:intel_dump_pipe_config [i915]] [PLANE:34:cursor A] disabled, scaler_id = -1
>[  336.583228] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  336.583284] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[  336.583349] [drm:intel_find_shared_dpll [i915]] [CRTC:37:pipe A] allocated DPLL 0
>[  336.583405] [drm:intel_reference_shared_dpll [i915]] using DPLL 0 for pipe A
>[  336.584956] [drm:intel_power_well_enable [i915]] enabling always-on
>[  336.585025] [drm:intel_power_well_enable [i915]] enabling DC off
>[  336.585336] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  336.585437] [drm:intel_atomic_commit_tail [i915]] [ENCODER:48:DDI A]
>[  336.585510] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI B]
>[  336.585591] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  336.585659] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  336.585733] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DDI C]
>[  336.585798] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST A]
>[  336.585871] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST B]
>[  336.585933] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI D]
>[  336.586004] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[  336.586065] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[  336.586141] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[  336.586209] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[  336.586284] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[  336.586348] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[  336.586431] [drm:intel_enable_shared_dpll [i915]] enable DPLL 0 (active 1, on? 0) for crtc 37
>[  336.586498] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 0
>[  336.586592] [drm:edp_panel_on [i915]] Turn eDP port A panel power on
>[  336.586681] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle
>[  336.588195] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010
>[  336.588291] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  336.588389] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0
>[  336.588478] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  337.212517] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 00000000 control 00000060
>[  337.212607] [drm:wait_panel_status [i915]] Wait complete
>[  337.212732] [drm:edp_panel_on [i915]] Wait for panel power on
>[  337.212865] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 00000063
>[  337.246283] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010
>[  337.246364] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  337.246438] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1
>[  337.246559] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  337.415067] [drm:wait_panel_status [i915]] Wait complete
>[  337.415133] [drm:intel_power_well_enable [i915]] enabling DDI A/E IO power well
>[  337.415235] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[  337.415384] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b
>[  337.416627] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  337.416701] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  337.416767] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  337.416831] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  337.417546] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  337.417607] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  337.418604] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  337.418660] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:49:eDP-1] Link Training Passed at Link Rate = 270000, Lane count = 2
>[  337.419295] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  337.419360] [drm:intel_edp_backlight_on [i915]] 
>[  337.419417] [drm:intel_panel_enable_backlight [i915]] pipe A
>[  337.419500] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 120000
>[  337.424131] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS
>[  337.424195] [drm:intel_fbc_enable [i915]] reserved 16588800 bytes of contiguous stolen space for FBC, threshold: 1
>[  337.424252] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  337.436192] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:49:eDP-1]
>[  337.436269] [drm:intel_atomic_commit_tail [i915]] [CRTC:37:pipe A]
>[  337.436356] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[  337.686436] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped
>[  337.936419] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped
>[  338.186423] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped
>[  338.436427] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped
>[  338.686411] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped
>[  338.703062] [IGT] kms_frontbuffer_tracking: exiting, ret=0
>[  338.703122] Setting dangerous option enable_psr - tainting kernel
>[  338.703134] Setting dangerous option enable_fbc - tainting kernel
>[  338.760303] [drm:intel_atomic_check [i915]] [CONNECTOR:57:DP-1] checking for sink bpp constrains
>[  338.760322] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  338.760341] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 148500KHz
>[  338.760360] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  338.760375] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 648000
>[  338.760393] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  338.760410] [drm:intel_dump_pipe_config [i915]] [CRTC:47:pipe B][modeset]
>[  338.760426] [drm:intel_dump_pipe_config [i915]] output_types: DP (0x80)
>[  338.760441] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  338.760456] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5767168, gmch_n: 8388608, link_m: 240298, link_n: 262144, tu: 64
>[  338.760471] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  338.760485] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  338.760494] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  338.760509] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  338.760516] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  338.760532] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  338.760546] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1080, pixel rate 148500
>[  338.760560] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  338.760574] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  338.760587] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  338.760601] [drm:intel_dump_pipe_config [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  338.760615] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  338.760629] [drm:intel_dump_pipe_config [i915]] [PLANE:38:plane 1B] disabled, scaler_id = -1
>[  338.760642] [drm:intel_dump_pipe_config [i915]] [PLANE:41:plane 2B] disabled, scaler_id = -1
>[  338.760656] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor B] disabled, scaler_id = -1
>[  338.760673] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  338.760689] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[  338.760709] [drm:intel_find_shared_dpll [i915]] [CRTC:47:pipe B] allocated DPLL 1
>[  338.760725] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[  338.760755] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  338.760773] [drm:intel_disable_sagv [i915]] Disabling the SAGV
>[  338.760792] [drm:intel_atomic_commit_tail [i915]] [ENCODER:48:DDI A]
>[  338.760808] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI B]
>[  338.760826] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  338.760843] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  338.760856] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DDI C]
>[  338.760870] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST A]
>[  338.760883] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST B]
>[  338.760896] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI D]
>[  338.760909] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[  338.760922] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[  338.760936] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[  338.760951] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[  338.760966] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[  338.760980] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[  338.769522] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 2, on? 0) for crtc 47
>[  338.769545] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  338.769641] [drm:intel_power_well_enable [i915]] enabling DDI B IO power well
>[  338.770208] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  338.771298] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  338.772392] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  338.773455] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  338.774546] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  338.775632] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  338.776659] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  338.777347] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] too many retries, giving up
>[  338.777770] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  338.778855] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  338.779941] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  338.781034] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  338.782119] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  338.783207] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  338.784294] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  338.784961] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] too many retries, giving up
>[  338.786448] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  338.787536] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  338.788495] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  338.789580] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  338.790667] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  338.791755] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  338.792848] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  338.793515] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] too many retries, giving up
>[  338.793950] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  338.795041] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  338.796106] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  338.797199] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  338.798301] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  338.799408] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  338.800551] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  338.801226] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] too many retries, giving up
>[  338.802903] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  338.804181] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  338.805431] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  338.806686] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  338.807559] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  338.808555] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  338.808616] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  338.808672] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  338.808727] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  338.827474] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  338.827541] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  338.846281] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  338.846635] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:57:DP-1] Link Training Passed at Link Rate = 162000, Lane count = 4
>[  338.847112] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  338.847177] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS
>[  338.863918] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:57:DP-1]
>[  338.863946] [drm:intel_atomic_commit_tail [i915]] [CRTC:47:pipe B]
>[  338.863981] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[  338.935935] [IGT] kms_frontbuffer_tracking: executing
>[  338.969879] [drm:drm_mode_addfb2 [drm]] [FB:90]
>[  338.969914] [drm:drm_mode_addfb2 [drm]] [FB:91]
>[  338.969944] [drm:drm_mode_addfb2 [drm]] [FB:92]
>[  338.970532] [drm:drm_mode_addfb2 [drm]] [FB:93]
>[  338.975313] [drm:drm_mode_addfb2 [drm]] [FB:94]
>[  338.976266] [drm:drm_mode_addfb2 [drm]] [FB:96]
>[  338.976287] [drm:drm_mode_addfb2 [drm]] [FB:98]
>[  338.976309] [drm:drm_mode_addfb2 [drm]] [FB:102]
>[  338.976477] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  338.976484] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  339.186417] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped
>[  339.186553] [IGT] kms_frontbuffer_tracking: starting subtest fbc-1p-offscren-pri-indfb-draw-mmap-wc
>[  339.186628] Setting dangerous option enable_fbc - tainting kernel
>[  339.186650] Setting dangerous option enable_psr - tainting kernel
>[  339.206846] [drm:drm_mode_addfb2 [drm]] [FB:72]
>[  339.206937] [drm:drm_mode_addfb2 [drm]] [FB:90]
>[  339.207035] [drm:drm_mode_addfb2 [drm]] [FB:91]
>[  339.209108] [drm:drm_mode_addfb2 [drm]] [FB:92]
>[  339.225039] [drm:drm_mode_addfb2 [drm]] [FB:93]
>[  339.228833] [drm:drm_mode_addfb2 [drm]] [FB:94]
>[  339.228915] [drm:drm_mode_addfb2 [drm]] [FB:96]
>[  339.229003] [drm:drm_mode_addfb2 [drm]] [FB:98]
>[  339.229231] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  339.229334] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  339.229399] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[  339.229515] [drm:intel_edp_backlight_off [i915]] 
>[  339.436170] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0
>[  339.436301] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  339.453302] [drm:intel_edp_panel_off.part.31 [i915]] Turn eDP port A panel power off
>[  339.453415] [drm:intel_edp_panel_off.part.31 [i915]] Wait for panel power off time
>[  339.453550] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000002 control 00000060
>[  339.506073] [drm:wait_panel_status [i915]] Wait complete
>[  339.506137] [drm:intel_power_well_disable [i915]] disabling DDI A/E IO power well
>[  339.506220] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  339.506300] [drm:intel_disable_shared_dpll [i915]] disable DPLL 0 (active 1, on? 1) for crtc 37
>[  339.506372] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 0
>[  339.506465] [drm:intel_atomic_commit_tail [i915]] [ENCODER:48:DDI A]
>[  339.506536] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI B]
>[  339.506602] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  339.506667] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  339.506729] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DDI C]
>[  339.506790] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST A]
>[  339.506851] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST B]
>[  339.506911] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI D]
>[  339.506971] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[  339.507030] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[  339.507095] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:49:eDP-1]
>[  339.507162] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[  339.507225] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[  339.507287] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[  339.507347] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[  339.513420] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010
>[  339.513500] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  339.513575] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0
>[  339.513698] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  339.513959] [drm:intel_atomic_commit_tail [i915]] [CRTC:37:pipe A]
>[  339.514048] [drm:intel_enable_sagv [i915]] Enabling the SAGV
>[  339.514162] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  339.514277] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  339.514354] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[  339.514472] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  339.531457] [drm:intel_power_well_disable [i915]] disabling DDI B IO power well
>[  339.531540] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 2, on? 1) for crtc 47
>[  339.531613] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  339.531702] [drm:intel_atomic_commit_tail [i915]] [ENCODER:48:DDI A]
>[  339.531768] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI B]
>[  339.531833] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  339.531894] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  339.531954] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DDI C]
>[  339.532011] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST A]
>[  339.532123] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST B]
>[  339.532213] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI D]
>[  339.532305] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[  339.532371] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[  339.532454] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:57:DP-1]
>[  339.532536] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[  339.532602] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[  339.532683] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[  339.532747] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[  339.532823] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  339.532908] [drm:intel_atomic_commit_tail [i915]] [CRTC:47:pipe B]
>[  339.532982] [drm:intel_power_well_disable [i915]] disabling DC off
>[  339.533043] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  339.533109] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  339.533567] [drm:intel_power_well_disable [i915]] disabling always-on
>[  339.538289] [drm:drm_mode_addfb2 [drm]] [FB:73]
>[  339.540824] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  339.540830] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  339.540852] [drm:intel_atomic_check [i915]] [CONNECTOR:49:eDP-1] checking for sink bpp constrains
>[  339.540865] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  339.540871] [drm:drm_mode_debug_printmodeline [drm]] Modeline 52:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[  339.540885] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 138780KHz
>[  339.540901] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24
>[  339.540912] [drm:intel_dp_compute_config [i915]] DP link bw required 416340 available 540000
>[  339.540924] [drm:intel_dp_compute_config [i915]] PSR disable by flag
>[  339.540936] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  339.540949] [drm:intel_dump_pipe_config [i915]] [CRTC:37:pipe A][modeset]
>[  339.540960] [drm:intel_dump_pipe_config [i915]] output_types: EDP (0x100)
>[  339.540972] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0
>[  339.540983] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 6467616, gmch_n: 8388608, link_m: 269484, link_n: 524288, tu: 64
>[  339.540994] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  339.541005] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  339.541010] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[  339.541021] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  339.541026] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[  339.541038] [drm:intel_dump_pipe_config [i915]] crtc timings: 138780 1920 1966 1996 2080 1080 1082 1086 1112, type: 0x48 flags: 0xa
>[  339.541049] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 138780
>[  339.541059] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  339.541070] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  339.541080] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  339.541091] [drm:intel_dump_pipe_config [i915]] dpll_hw_state: ctrl1: 0x3, cfgcr1: 0x0, cfgcr2: 0x0
>[  339.541101] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  339.541111] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 1A] disabled, scaler_id = -1
>[  339.541121] [drm:intel_dump_pipe_config [i915]] [PLANE:31:plane 2A] disabled, scaler_id = -1
>[  339.541131] [drm:intel_dump_pipe_config [i915]] [PLANE:34:cursor A] disabled, scaler_id = -1
>[  339.541143] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  339.541155] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[  339.541169] [drm:intel_find_shared_dpll [i915]] [CRTC:37:pipe A] allocated DPLL 0
>[  339.541181] [drm:intel_reference_shared_dpll [i915]] using DPLL 0 for pipe A
>[  339.541782] [drm:intel_power_well_enable [i915]] enabling always-on
>[  339.541795] [drm:intel_power_well_enable [i915]] enabling DC off
>[  339.542075] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  339.542100] [drm:intel_atomic_commit_tail [i915]] [ENCODER:48:DDI A]
>[  339.542119] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI B]
>[  339.542133] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  339.542145] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  339.542157] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DDI C]
>[  339.542168] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST A]
>[  339.542179] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST B]
>[  339.542189] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI D]
>[  339.542201] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[  339.542211] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[  339.542223] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[  339.542235] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[  339.542247] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[  339.542259] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[  339.542272] [drm:intel_enable_shared_dpll [i915]] enable DPLL 0 (active 1, on? 0) for crtc 37
>[  339.542284] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 0
>[  339.542303] [drm:edp_panel_on [i915]] Turn eDP port A panel power on
>[  339.542327] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle
>[  340.124574] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 00000000 control 00000060
>[  340.124681] [drm:wait_panel_status [i915]] Wait complete
>[  340.124819] [drm:edp_panel_on [i915]] Wait for panel power on
>[  340.124951] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 00000063
>[  340.158696] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010
>[  340.158777] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  340.158853] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1
>[  340.158975] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  340.325307] [drm:wait_panel_status [i915]] Wait complete
>[  340.325373] [drm:intel_power_well_enable [i915]] enabling DDI A/E IO power well
>[  340.325476] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[  340.325627] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b
>[  340.326864] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  340.326936] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  340.327001] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  340.327064] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  340.327772] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  340.327825] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  340.328885] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  340.328951] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:49:eDP-1] Link Training Passed at Link Rate = 270000, Lane count = 2
>[  340.329612] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  340.329706] [drm:intel_edp_backlight_on [i915]] 
>[  340.329763] [drm:intel_panel_enable_backlight [i915]] pipe A
>[  340.329847] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 120000
>[  340.336201] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS
>[  340.346513] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:49:eDP-1]
>[  340.346590] [drm:intel_atomic_commit_tail [i915]] [CRTC:37:pipe A]
>[  340.346678] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[  340.596774] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped
>[  340.596852] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  340.596945] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  340.597007] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[  340.597108] [drm:intel_edp_backlight_off [i915]] 
>[  340.804147] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0
>[  340.804266] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  340.815294] [drm:intel_edp_panel_off.part.31 [i915]] Turn eDP port A panel power off
>[  340.815399] [drm:intel_edp_panel_off.part.31 [i915]] Wait for panel power off time
>[  340.815526] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000002 control 00000060
>[  340.865840] [drm:wait_panel_status [i915]] Wait complete
>[  340.865897] [drm:intel_power_well_disable [i915]] disabling DDI A/E IO power well
>[  340.865974] [drm:intel_disable_shared_dpll [i915]] disable DPLL 0 (active 1, on? 1) for crtc 37
>[  340.866039] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 0
>[  340.866122] [drm:intel_atomic_commit_tail [i915]] [ENCODER:48:DDI A]
>[  340.866186] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI B]
>[  340.866245] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  340.866301] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  340.866356] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DDI C]
>[  340.866411] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST A]
>[  340.866465] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST B]
>[  340.866518] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI D]
>[  340.866571] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[  340.866623] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[  340.866681] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:49:eDP-1]
>[  340.866740] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[  340.866797] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[  340.866852] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[  340.866906] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[  340.866974] [drm:intel_atomic_commit_tail [i915]] [CRTC:37:pipe A]
>[  340.867031] [drm:intel_power_well_disable [i915]] disabling DC off
>[  340.867081] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  340.867128] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  340.867567] [drm:intel_power_well_disable [i915]] disabling always-on
>[  340.867658] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  340.870524] [drm:drm_mode_addfb2 [drm]] [FB:73]
>[  340.871341] [drm:drm_mode_addfb2 [drm]] [FB:102]
>[  340.872577] [drm:drm_mode_addfb2 [drm]] [FB:103]
>[  340.873403] [drm:drm_mode_addfb2 [drm]] [FB:104]
>[  340.875472] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010
>[  340.875486] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  340.875499] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0
>[  340.875569] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  340.944353] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  340.944360] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  340.944382] [drm:intel_atomic_check [i915]] [CONNECTOR:49:eDP-1] checking for sink bpp constrains
>[  340.944395] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  340.944402] [drm:drm_mode_debug_printmodeline [drm]] Modeline 52:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[  340.944415] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 138780KHz
>[  340.944431] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24
>[  340.944443] [drm:intel_dp_compute_config [i915]] DP link bw required 416340 available 540000
>[  340.944454] [drm:intel_dp_compute_config [i915]] PSR disable by flag
>[  340.944467] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  340.944480] [drm:intel_dump_pipe_config [i915]] [CRTC:37:pipe A][modeset]
>[  340.944492] [drm:intel_dump_pipe_config [i915]] output_types: EDP (0x100)
>[  340.944503] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0
>[  340.944514] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 6467616, gmch_n: 8388608, link_m: 269484, link_n: 524288, tu: 64
>[  340.944525] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  340.944536] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  340.944541] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[  340.944552] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  340.944557] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[  340.944568] [drm:intel_dump_pipe_config [i915]] crtc timings: 138780 1920 1966 1996 2080 1080 1082 1086 1112, type: 0x48 flags: 0xa
>[  340.944579] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 138780
>[  340.944589] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  340.944600] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  340.944610] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  340.944621] [drm:intel_dump_pipe_config [i915]] dpll_hw_state: ctrl1: 0x3, cfgcr1: 0x0, cfgcr2: 0x0
>[  340.944630] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  340.944641] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 1A] disabled, scaler_id = -1
>[  340.944651] [drm:intel_dump_pipe_config [i915]] [PLANE:31:plane 2A] disabled, scaler_id = -1
>[  340.944661] [drm:intel_dump_pipe_config [i915]] [PLANE:34:cursor A] disabled, scaler_id = -1
>[  340.944674] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  340.944685] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[  340.944700] [drm:intel_find_shared_dpll [i915]] [CRTC:37:pipe A] allocated DPLL 0
>[  340.944711] [drm:intel_reference_shared_dpll [i915]] using DPLL 0 for pipe A
>[  340.945667] [drm:intel_power_well_enable [i915]] enabling always-on
>[  340.945676] [drm:intel_power_well_enable [i915]] enabling DC off
>[  340.945972] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  340.945990] [drm:intel_atomic_commit_tail [i915]] [ENCODER:48:DDI A]
>[  340.946004] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI B]
>[  340.946017] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  340.946030] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  340.946042] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DDI C]
>[  340.946073] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST A]
>[  340.946085] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST B]
>[  340.946096] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI D]
>[  340.946108] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[  340.946120] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[  340.946132] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[  340.946146] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[  340.946175] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[  340.946203] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[  340.946216] [drm:intel_enable_shared_dpll [i915]] enable DPLL 0 (active 1, on? 0) for crtc 37
>[  340.946228] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 0
>[  340.946247] [drm:edp_panel_on [i915]] Turn eDP port A panel power on
>[  340.946271] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle
>[  341.500571] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 00000000 control 00000060
>[  341.500678] [drm:wait_panel_status [i915]] Wait complete
>[  341.500817] [drm:edp_panel_on [i915]] Wait for panel power on
>[  341.500950] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 00000063
>[  341.534659] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010
>[  341.534740] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  341.534815] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1
>[  341.534955] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  341.701785] [drm:wait_panel_status [i915]] Wait complete
>[  341.701851] [drm:intel_power_well_enable [i915]] enabling DDI A/E IO power well
>[  341.701952] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[  341.702103] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b
>[  341.703299] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  341.703361] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  341.703420] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  341.703480] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  341.704231] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  341.704306] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  341.705339] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  341.705403] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:49:eDP-1] Link Training Passed at Link Rate = 270000, Lane count = 2
>[  341.706058] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  341.706134] [drm:intel_edp_backlight_on [i915]] 
>[  341.706198] [drm:intel_panel_enable_backlight [i915]] pipe A
>[  341.706302] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 120000
>[  341.712164] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS
>[  341.722900] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:49:eDP-1]
>[  341.722977] [drm:intel_atomic_commit_tail [i915]] [CRTC:37:pipe A]
>[  341.723062] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[  341.973197] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped
>[  341.973247] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  341.973278] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  342.239855] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped
>[  342.239905] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  342.239935] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  342.506521] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped
>[  342.506567] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  342.506597] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  342.773186] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped
>[  342.773314] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  342.773407] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  342.773470] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[  342.773572] [drm:intel_edp_backlight_off [i915]] 
>[  342.980328] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0
>[  342.980460] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  342.991652] [drm:intel_edp_panel_off.part.31 [i915]] Turn eDP port A panel power off
>[  342.991764] [drm:intel_edp_panel_off.part.31 [i915]] Wait for panel power off time
>[  342.991896] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000003 control 00000060
>[  343.042218] [drm:wait_panel_status [i915]] Wait complete
>[  343.042282] [drm:intel_power_well_disable [i915]] disabling DDI A/E IO power well
>[  343.042369] [drm:intel_disable_shared_dpll [i915]] disable DPLL 0 (active 1, on? 1) for crtc 37
>[  343.042443] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 0
>[  343.042537] [drm:intel_atomic_commit_tail [i915]] [ENCODER:48:DDI A]
>[  343.042606] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI B]
>[  343.042672] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  343.042736] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  343.042799] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DDI C]
>[  343.042862] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST A]
>[  343.042923] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST B]
>[  343.042983] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI D]
>[  343.043043] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[  343.043103] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[  343.043169] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:49:eDP-1]
>[  343.043236] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[  343.043301] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[  343.043365] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[  343.043427] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[  343.043506] [drm:intel_atomic_commit_tail [i915]] [CRTC:37:pipe A]
>[  343.043570] [drm:intel_power_well_disable [i915]] disabling DC off
>[  343.043626] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  343.043679] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  343.044165] [drm:intel_power_well_disable [i915]] disabling always-on
>[  343.044272] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  343.044500] Setting dangerous option enable_fbc - tainting kernel
>[  343.045540] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  343.045569] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  343.045657] [drm:intel_atomic_check [i915]] [CONNECTOR:49:eDP-1] checking for sink bpp constrains
>[  343.045669] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  343.045676] [drm:drm_mode_debug_printmodeline [drm]] Modeline 52:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[  343.045689] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 138780KHz
>[  343.045705] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24
>[  343.045717] [drm:intel_dp_compute_config [i915]] DP link bw required 416340 available 540000
>[  343.045728] [drm:intel_dp_compute_config [i915]] PSR disable by flag
>[  343.045740] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  343.045753] [drm:intel_dump_pipe_config [i915]] [CRTC:37:pipe A][modeset]
>[  343.045764] [drm:intel_dump_pipe_config [i915]] output_types: EDP (0x100)
>[  343.045776] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0
>[  343.045787] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 6467616, gmch_n: 8388608, link_m: 269484, link_n: 524288, tu: 64
>[  343.045798] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  343.045808] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  343.045814] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[  343.045825] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  343.045830] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[  343.045841] [drm:intel_dump_pipe_config [i915]] crtc timings: 138780 1920 1966 1996 2080 1080 1082 1086 1112, type: 0x48 flags: 0xa
>[  343.045852] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 138780
>[  343.045862] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  343.045872] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  343.045883] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  343.045893] [drm:intel_dump_pipe_config [i915]] dpll_hw_state: ctrl1: 0x3, cfgcr1: 0x0, cfgcr2: 0x0
>[  343.045903] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  343.045913] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 1A] disabled, scaler_id = -1
>[  343.045923] [drm:intel_dump_pipe_config [i915]] [PLANE:31:plane 2A] disabled, scaler_id = -1
>[  343.045933] [drm:intel_dump_pipe_config [i915]] [PLANE:34:cursor A] disabled, scaler_id = -1
>[  343.045946] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  343.045958] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[  343.045972] [drm:intel_find_shared_dpll [i915]] [CRTC:37:pipe A] allocated DPLL 0
>[  343.045984] [drm:intel_reference_shared_dpll [i915]] using DPLL 0 for pipe A
>[  343.049336] [drm:intel_power_well_enable [i915]] enabling always-on
>[  343.049406] [drm:intel_power_well_enable [i915]] enabling DC off
>[  343.049721] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  343.049819] [drm:intel_atomic_commit_tail [i915]] [ENCODER:48:DDI A]
>[  343.049896] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI B]
>[  343.049976] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  343.050043] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  343.050118] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DDI C]
>[  343.050182] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST A]
>[  343.050254] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST B]
>[  343.050316] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI D]
>[  343.050388] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[  343.050452] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[  343.050528] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[  343.050596] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[  343.050673] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[  343.050738] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[  343.050822] [drm:intel_enable_shared_dpll [i915]] enable DPLL 0 (active 1, on? 0) for crtc 37
>[  343.050891] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 0
>[  343.050983] [drm:edp_panel_on [i915]] Turn eDP port A panel power on
>[  343.051073] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle
>[  343.051491] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010
>[  343.051561] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  343.051637] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0
>[  343.051726] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  343.676500] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 00000000 control 00000060
>[  343.676608] [drm:wait_panel_status [i915]] Wait complete
>[  343.676748] [drm:edp_panel_on [i915]] Wait for panel power on
>[  343.676880] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 00000063
>[  343.710374] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010
>[  343.710455] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  343.710530] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1
>[  343.710682] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  343.877132] [drm:wait_panel_status [i915]] Wait complete
>[  343.877198] [drm:intel_power_well_enable [i915]] enabling DDI A/E IO power well
>[  343.877300] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[  343.877452] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b
>[  343.878657] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  343.878720] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  343.878781] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  343.878842] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  343.879545] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  343.879598] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  343.880607] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  343.880664] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:49:eDP-1] Link Training Passed at Link Rate = 270000, Lane count = 2
>[  343.881299] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  343.881366] [drm:intel_edp_backlight_on [i915]] 
>[  343.881424] [drm:intel_panel_enable_backlight [i915]] pipe A
>[  343.881494] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 120000
>[  343.892147] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS
>[  343.892163] [drm:intel_fbc_enable [i915]] reserved 16588800 bytes of contiguous stolen space for FBC, threshold: 1
>[  343.892177] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  343.898123] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:49:eDP-1]
>[  343.898144] [drm:intel_atomic_commit_tail [i915]] [CRTC:37:pipe A]
>[  343.898171] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[  344.148444] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped
>[  344.398417] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped
>[  344.648422] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped
>[  344.898430] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped
>[  345.148433] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped
>[  345.165012] [IGT] kms_frontbuffer_tracking: exiting, ret=0
>[  345.165071] Setting dangerous option enable_psr - tainting kernel
>[  345.165083] Setting dangerous option enable_fbc - tainting kernel
>[  345.228293] [drm:intel_atomic_check [i915]] [CONNECTOR:57:DP-1] checking for sink bpp constrains
>[  345.228316] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  345.228339] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 148500KHz
>[  345.228361] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  345.228380] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 648000
>[  345.228402] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  345.228422] [drm:intel_dump_pipe_config [i915]] [CRTC:47:pipe B][modeset]
>[  345.228442] [drm:intel_dump_pipe_config [i915]] output_types: DP (0x80)
>[  345.228460] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  345.228479] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5767168, gmch_n: 8388608, link_m: 240298, link_n: 262144, tu: 64
>[  345.228497] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  345.228514] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  345.228525] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  345.228543] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  345.228552] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  345.228571] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  345.228588] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1080, pixel rate 148500
>[  345.228606] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  345.228622] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  345.228639] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  345.228656] [drm:intel_dump_pipe_config [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  345.228672] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  345.228689] [drm:intel_dump_pipe_config [i915]] [PLANE:38:plane 1B] disabled, scaler_id = -1
>[  345.228706] [drm:intel_dump_pipe_config [i915]] [PLANE:41:plane 2B] disabled, scaler_id = -1
>[  345.228722] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor B] disabled, scaler_id = -1
>[  345.228743] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  345.228761] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[  345.228785] [drm:intel_find_shared_dpll [i915]] [CRTC:47:pipe B] allocated DPLL 1
>[  345.228805] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[  345.228835] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  345.228857] [drm:intel_disable_sagv [i915]] Disabling the SAGV
>[  345.228880] [drm:intel_atomic_commit_tail [i915]] [ENCODER:48:DDI A]
>[  345.228918] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI B]
>[  345.228937] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  345.228954] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  345.228971] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DDI C]
>[  345.228988] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST A]
>[  345.229005] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST B]
>[  345.229022] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI D]
>[  345.229039] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[  345.229056] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[  345.229074] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[  345.229093] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[  345.229111] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[  345.229128] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[  345.231515] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 2, on? 0) for crtc 47
>[  345.231540] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  345.231640] [drm:intel_power_well_enable [i915]] enabling DDI B IO power well
>[  345.232212] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  345.233233] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  345.234258] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  345.235349] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  345.236446] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  345.237531] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  345.238622] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  345.239290] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] too many retries, giving up
>[  345.239714] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  345.240746] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  345.241832] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  345.242917] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  345.244013] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  345.245109] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  345.246198] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  345.246862] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] too many retries, giving up
>[  345.248374] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  345.249464] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  345.250556] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  345.251646] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  345.252691] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  345.253783] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  345.254888] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  345.255562] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] too many retries, giving up
>[  345.256023] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  345.257133] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  345.258093] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  345.259198] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  345.260302] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  345.261401] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  345.262501] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  345.263180] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] too many retries, giving up
>[  345.264716] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  345.265989] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  345.267239] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  345.268514] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  345.269381] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  345.270366] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  345.270425] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  345.270481] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  345.270536] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  345.289287] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  345.289354] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  345.308045] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  345.308388] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:57:DP-1] Link Training Passed at Link Rate = 162000, Lane count = 4
>[  345.308824] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  345.308884] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS
>[  345.325664] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:57:DP-1]
>[  345.325694] [drm:intel_atomic_commit_tail [i915]] [CRTC:47:pipe B]
>[  345.325730] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[  345.365861] [IGT] kms_frontbuffer_tracking: executing
>[  345.422267] [drm:drm_mode_addfb2 [drm]] [FB:90]
>[  345.422309] [drm:drm_mode_addfb2 [drm]] [FB:91]
>[  345.422351] [drm:drm_mode_addfb2 [drm]] [FB:92]
>[  345.423140] [drm:drm_mode_addfb2 [drm]] [FB:93]
>[  345.427908] [drm:drm_mode_addfb2 [drm]] [FB:94]
>[  345.428826] [drm:drm_mode_addfb2 [drm]] [FB:96]
>[  345.428846] [drm:drm_mode_addfb2 [drm]] [FB:98]
>[  345.428867] [drm:drm_mode_addfb2 [drm]] [FB:102]
>[  345.429035] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  345.429042] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  345.648407] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped
>[  345.648546] [IGT] kms_frontbuffer_tracking: starting subtest fbc-1p-offscren-pri-indfb-draw-pwrite
>[  345.648620] Setting dangerous option enable_fbc - tainting kernel
>[  345.648642] Setting dangerous option enable_psr - tainting kernel
>[  345.668788] [drm:drm_mode_addfb2 [drm]] [FB:72]
>[  345.668880] [drm:drm_mode_addfb2 [drm]] [FB:90]
>[  345.668977] [drm:drm_mode_addfb2 [drm]] [FB:91]
>[  345.670576] [drm:drm_mode_addfb2 [drm]] [FB:92]
>[  345.674313] [drm:drm_mode_addfb2 [drm]] [FB:93]
>[  345.675150] [drm:drm_mode_addfb2 [drm]] [FB:94]
>[  345.675170] [drm:drm_mode_addfb2 [drm]] [FB:96]
>[  345.675189] [drm:drm_mode_addfb2 [drm]] [FB:98]
>[  345.675291] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  345.675322] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  345.675336] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[  345.675369] [drm:intel_edp_backlight_off [i915]] 
>[  345.880341] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0
>[  345.880473] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  345.882173] [drm:intel_edp_panel_off.part.31 [i915]] Turn eDP port A panel power off
>[  345.882285] [drm:intel_edp_panel_off.part.31 [i915]] Wait for panel power off time
>[  345.882417] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000003 control 00000060
>[  345.934691] [drm:wait_panel_status [i915]] Wait complete
>[  345.934749] [drm:intel_power_well_disable [i915]] disabling DDI A/E IO power well
>[  345.934854] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  345.934933] [drm:intel_disable_shared_dpll [i915]] disable DPLL 0 (active 1, on? 1) for crtc 37
>[  345.935001] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 0
>[  345.935091] [drm:intel_atomic_commit_tail [i915]] [ENCODER:48:DDI A]
>[  345.935158] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI B]
>[  345.935219] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  345.935287] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  345.935361] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DDI C]
>[  345.935418] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST A]
>[  345.935489] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST B]
>[  345.935554] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI D]
>[  345.935623] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[  345.935678] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[  345.935758] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:49:eDP-1]
>[  345.935837] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[  345.935898] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[  345.935997] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[  345.936106] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[  345.942013] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010
>[  345.942071] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  345.942128] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0
>[  345.942196] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  345.942349] [drm:intel_atomic_commit_tail [i915]] [CRTC:37:pipe A]
>[  345.942412] [drm:intel_enable_sagv [i915]] Enabling the SAGV
>[  345.942512] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  345.942604] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  345.942668] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[  345.942770] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  345.959252] [drm:intel_power_well_disable [i915]] disabling DDI B IO power well
>[  345.959326] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 2, on? 1) for crtc 47
>[  345.959390] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  345.959471] [drm:intel_atomic_commit_tail [i915]] [ENCODER:48:DDI A]
>[  345.959529] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI B]
>[  345.959586] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  345.959641] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  345.959693] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DDI C]
>[  345.959744] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST A]
>[  345.959793] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST B]
>[  345.959842] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI D]
>[  345.959890] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[  345.959939] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[  345.959998] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:57:DP-1]
>[  345.960091] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[  345.960154] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[  345.960217] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[  345.960274] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[  345.960334] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  345.960399] [drm:intel_atomic_commit_tail [i915]] [CRTC:47:pipe B]
>[  345.960454] [drm:intel_power_well_disable [i915]] disabling DC off
>[  345.960502] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  345.960546] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  345.960982] [drm:intel_power_well_disable [i915]] disabling always-on
>[  345.965140] [drm:drm_mode_addfb2 [drm]] [FB:73]
>[  345.966805] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  345.966812] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  345.966833] [drm:intel_atomic_check [i915]] [CONNECTOR:49:eDP-1] checking for sink bpp constrains
>[  345.966846] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  345.966852] [drm:drm_mode_debug_printmodeline [drm]] Modeline 52:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[  345.966865] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 138780KHz
>[  345.966881] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24
>[  345.966893] [drm:intel_dp_compute_config [i915]] DP link bw required 416340 available 540000
>[  345.966904] [drm:intel_dp_compute_config [i915]] PSR disable by flag
>[  345.966916] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  345.966929] [drm:intel_dump_pipe_config [i915]] [CRTC:37:pipe A][modeset]
>[  345.966941] [drm:intel_dump_pipe_config [i915]] output_types: EDP (0x100)
>[  345.966952] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0
>[  345.966964] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 6467616, gmch_n: 8388608, link_m: 269484, link_n: 524288, tu: 64
>[  345.966975] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  345.966985] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  345.966991] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[  345.967002] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  345.967007] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[  345.967019] [drm:intel_dump_pipe_config [i915]] crtc timings: 138780 1920 1966 1996 2080 1080 1082 1086 1112, type: 0x48 flags: 0xa
>[  345.967029] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 138780
>[  345.967040] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  345.967051] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  345.967061] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  345.967072] [drm:intel_dump_pipe_config [i915]] dpll_hw_state: ctrl1: 0x3, cfgcr1: 0x0, cfgcr2: 0x0
>[  345.967083] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  345.967093] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 1A] disabled, scaler_id = -1
>[  345.967103] [drm:intel_dump_pipe_config [i915]] [PLANE:31:plane 2A] disabled, scaler_id = -1
>[  345.967113] [drm:intel_dump_pipe_config [i915]] [PLANE:34:cursor A] disabled, scaler_id = -1
>[  345.967126] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  345.967137] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[  345.967151] [drm:intel_find_shared_dpll [i915]] [CRTC:37:pipe A] allocated DPLL 0
>[  345.967163] [drm:intel_reference_shared_dpll [i915]] using DPLL 0 for pipe A
>[  345.967680] [drm:intel_power_well_enable [i915]] enabling always-on
>[  345.967689] [drm:intel_power_well_enable [i915]] enabling DC off
>[  345.967964] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  345.967982] [drm:intel_atomic_commit_tail [i915]] [ENCODER:48:DDI A]
>[  345.968024] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI B]
>[  345.968038] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  345.968067] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  345.968079] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DDI C]
>[  345.968092] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST A]
>[  345.968103] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST B]
>[  345.968113] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI D]
>[  345.968125] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[  345.968138] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[  345.968150] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[  345.968163] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[  345.968191] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[  345.968202] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[  345.968216] [drm:intel_enable_shared_dpll [i915]] enable DPLL 0 (active 1, on? 0) for crtc 37
>[  345.968227] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 0
>[  345.968246] [drm:edp_panel_on [i915]] Turn eDP port A panel power on
>[  345.968269] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle
>[  346.556564] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 00000000 control 00000060
>[  346.556670] [drm:wait_panel_status [i915]] Wait complete
>[  346.556808] [drm:edp_panel_on [i915]] Wait for panel power on
>[  346.556937] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 00000063
>[  346.590696] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010
>[  346.590778] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  346.590854] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1
>[  346.590996] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  346.758054] [drm:wait_panel_status [i915]] Wait complete
>[  346.758119] [drm:intel_power_well_enable [i915]] enabling DDI A/E IO power well
>[  346.758221] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[  346.758371] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b
>[  346.759561] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  346.759617] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  346.759669] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  346.759722] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  346.760451] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  346.760527] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  346.761487] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  346.761512] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:49:eDP-1] Link Training Passed at Link Rate = 270000, Lane count = 2
>[  346.761904] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  346.761926] [drm:intel_edp_backlight_on [i915]] 
>[  346.761938] [drm:intel_panel_enable_backlight [i915]] pipe A
>[  346.761976] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 120000
>[  346.768155] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS
>[  346.778703] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:49:eDP-1]
>[  346.778724] [drm:intel_atomic_commit_tail [i915]] [CRTC:37:pipe A]
>[  346.778750] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[  347.029038] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped
>[  347.029117] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  347.029210] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  347.029273] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[  347.029374] [drm:intel_edp_backlight_off [i915]] 
>[  347.236168] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0
>[  347.236298] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  347.247746] [drm:intel_edp_panel_off.part.31 [i915]] Turn eDP port A panel power off
>[  347.247860] [drm:intel_edp_panel_off.part.31 [i915]] Wait for panel power off time
>[  347.247991] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000003 control 00000060
>[  347.299627] [drm:wait_panel_status [i915]] Wait complete
>[  347.299684] [drm:intel_power_well_disable [i915]] disabling DDI A/E IO power well
>[  347.299762] [drm:intel_disable_shared_dpll [i915]] disable DPLL 0 (active 1, on? 1) for crtc 37
>[  347.299829] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 0
>[  347.299912] [drm:intel_atomic_commit_tail [i915]] [ENCODER:48:DDI A]
>[  347.299977] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI B]
>[  347.300036] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  347.300136] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  347.300200] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DDI C]
>[  347.300265] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST A]
>[  347.300327] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST B]
>[  347.300386] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI D]
>[  347.300446] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[  347.300505] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[  347.300576] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:49:eDP-1]
>[  347.300658] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[  347.300749] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[  347.300812] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[  347.300867] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[  347.300935] [drm:intel_atomic_commit_tail [i915]] [CRTC:37:pipe A]
>[  347.300989] [drm:intel_power_well_disable [i915]] disabling DC off
>[  347.301037] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  347.301082] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  347.301517] [drm:intel_power_well_disable [i915]] disabling always-on
>[  347.301607] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  347.303651] [drm:drm_mode_addfb2 [drm]] [FB:73]
>[  347.305048] [drm:drm_mode_addfb2 [drm]] [FB:102]
>[  347.305878] [drm:drm_mode_addfb2 [drm]] [FB:103]
>[  347.306711] [drm:drm_mode_addfb2 [drm]] [FB:104]
>[  347.308054] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010
>[  347.308072] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  347.308091] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0
>[  347.308148] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  347.378545] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  347.378553] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  347.378576] [drm:intel_atomic_check [i915]] [CONNECTOR:49:eDP-1] checking for sink bpp constrains
>[  347.378589] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  347.378595] [drm:drm_mode_debug_printmodeline [drm]] Modeline 52:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[  347.378609] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 138780KHz
>[  347.378625] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24
>[  347.378637] [drm:intel_dp_compute_config [i915]] DP link bw required 416340 available 540000
>[  347.378648] [drm:intel_dp_compute_config [i915]] PSR disable by flag
>[  347.378661] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  347.378673] [drm:intel_dump_pipe_config [i915]] [CRTC:37:pipe A][modeset]
>[  347.378686] [drm:intel_dump_pipe_config [i915]] output_types: EDP (0x100)
>[  347.378697] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0
>[  347.378709] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 6467616, gmch_n: 8388608, link_m: 269484, link_n: 524288, tu: 64
>[  347.378720] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  347.378731] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  347.378737] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[  347.378748] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  347.378753] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[  347.378764] [drm:intel_dump_pipe_config [i915]] crtc timings: 138780 1920 1966 1996 2080 1080 1082 1086 1112, type: 0x48 flags: 0xa
>[  347.378775] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 138780
>[  347.378786] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  347.378797] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  347.378807] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  347.378818] [drm:intel_dump_pipe_config [i915]] dpll_hw_state: ctrl1: 0x3, cfgcr1: 0x0, cfgcr2: 0x0
>[  347.378828] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  347.378838] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 1A] disabled, scaler_id = -1
>[  347.378849] [drm:intel_dump_pipe_config [i915]] [PLANE:31:plane 2A] disabled, scaler_id = -1
>[  347.378859] [drm:intel_dump_pipe_config [i915]] [PLANE:34:cursor A] disabled, scaler_id = -1
>[  347.378872] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  347.378883] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[  347.378898] [drm:intel_find_shared_dpll [i915]] [CRTC:37:pipe A] allocated DPLL 0
>[  347.378909] [drm:intel_reference_shared_dpll [i915]] using DPLL 0 for pipe A
>[  347.379866] [drm:intel_power_well_enable [i915]] enabling always-on
>[  347.379875] [drm:intel_power_well_enable [i915]] enabling DC off
>[  347.380189] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  347.380208] [drm:intel_atomic_commit_tail [i915]] [ENCODER:48:DDI A]
>[  347.380241] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI B]
>[  347.380296] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  347.380313] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  347.380332] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DDI C]
>[  347.380349] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST A]
>[  347.380377] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST B]
>[  347.380388] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI D]
>[  347.380399] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[  347.380409] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[  347.380421] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[  347.380433] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[  347.380444] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[  347.380456] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[  347.380469] [drm:intel_enable_shared_dpll [i915]] enable DPLL 0 (active 1, on? 0) for crtc 37
>[  347.380481] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 0
>[  347.380500] [drm:edp_panel_on [i915]] Turn eDP port A panel power on
>[  347.380524] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle
>[  347.932421] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 00000000 control 00000060
>[  347.932528] [drm:wait_panel_status [i915]] Wait complete
>[  347.932666] [drm:edp_panel_on [i915]] Wait for panel power on
>[  347.932796] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 00000063
>[  347.966223] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010
>[  347.966304] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  347.966380] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1
>[  347.966513] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  348.132829] [drm:wait_panel_status [i915]] Wait complete
>[  348.132894] [drm:intel_power_well_enable [i915]] enabling DDI A/E IO power well
>[  348.132996] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[  348.133149] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b
>[  348.134387] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  348.134460] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  348.134525] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  348.134589] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  348.135304] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  348.135364] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  348.136431] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  348.136500] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:49:eDP-1] Link Training Passed at Link Rate = 270000, Lane count = 2
>[  348.137144] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  348.137221] [drm:intel_edp_backlight_on [i915]] 
>[  348.137278] [drm:intel_panel_enable_backlight [i915]] pipe A
>[  348.137362] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 120000
>[  348.144184] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS
>[  348.154025] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:49:eDP-1]
>[  348.154102] [drm:intel_atomic_commit_tail [i915]] [CRTC:37:pipe A]
>[  348.154190] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[  348.404289] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped
>[  348.404334] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  348.404365] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  348.670959] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped
>[  348.671009] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  348.671040] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  348.937618] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped
>[  348.937667] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  348.937697] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  349.204280] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped
>[  349.204409] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  349.204503] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  349.204564] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[  349.204666] [drm:intel_edp_backlight_off [i915]] 
>[  349.412235] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0
>[  349.412367] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  349.423417] [drm:intel_edp_panel_off.part.31 [i915]] Turn eDP port A panel power off
>[  349.423529] [drm:intel_edp_panel_off.part.31 [i915]] Wait for panel power off time
>[  349.423661] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000003 control 00000060
>[  349.473921] [drm:wait_panel_status [i915]] Wait complete
>[  349.473984] [drm:intel_power_well_disable [i915]] disabling DDI A/E IO power well
>[  349.474071] [drm:intel_disable_shared_dpll [i915]] disable DPLL 0 (active 1, on? 1) for crtc 37
>[  349.474147] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 0
>[  349.474239] [drm:intel_atomic_commit_tail [i915]] [ENCODER:48:DDI A]
>[  349.474328] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI B]
>[  349.474387] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  349.474445] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  349.474501] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DDI C]
>[  349.474556] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST A]
>[  349.474610] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST B]
>[  349.474664] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI D]
>[  349.474718] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[  349.474771] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[  349.474830] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:49:eDP-1]
>[  349.474890] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[  349.474948] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[  349.475005] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[  349.475061] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[  349.475131] [drm:intel_atomic_commit_tail [i915]] [CRTC:37:pipe A]
>[  349.475190] [drm:intel_power_well_disable [i915]] disabling DC off
>[  349.475240] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  349.475288] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  349.475726] [drm:intel_power_well_disable [i915]] disabling always-on
>[  349.475820] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  349.476022] Setting dangerous option enable_fbc - tainting kernel
>[  349.477007] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  349.477013] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  349.477031] [drm:intel_atomic_check [i915]] [CONNECTOR:49:eDP-1] checking for sink bpp constrains
>[  349.477044] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  349.477050] [drm:drm_mode_debug_printmodeline [drm]] Modeline 52:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[  349.477063] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 138780KHz
>[  349.477080] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24
>[  349.477091] [drm:intel_dp_compute_config [i915]] DP link bw required 416340 available 540000
>[  349.477103] [drm:intel_dp_compute_config [i915]] PSR disable by flag
>[  349.477115] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  349.477128] [drm:intel_dump_pipe_config [i915]] [CRTC:37:pipe A][modeset]
>[  349.477139] [drm:intel_dump_pipe_config [i915]] output_types: EDP (0x100)
>[  349.477151] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0
>[  349.477162] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 6467616, gmch_n: 8388608, link_m: 269484, link_n: 524288, tu: 64
>[  349.477173] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  349.477184] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  349.477190] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[  349.477200] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  349.477206] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[  349.477217] [drm:intel_dump_pipe_config [i915]] crtc timings: 138780 1920 1966 1996 2080 1080 1082 1086 1112, type: 0x48 flags: 0xa
>[  349.477228] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 138780
>[  349.477238] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  349.477248] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  349.477259] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  349.477269] [drm:intel_dump_pipe_config [i915]] dpll_hw_state: ctrl1: 0x3, cfgcr1: 0x0, cfgcr2: 0x0
>[  349.477279] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  349.477290] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 1A] disabled, scaler_id = -1
>[  349.477300] [drm:intel_dump_pipe_config [i915]] [PLANE:31:plane 2A] disabled, scaler_id = -1
>[  349.477310] [drm:intel_dump_pipe_config [i915]] [PLANE:34:cursor A] disabled, scaler_id = -1
>[  349.477323] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  349.477334] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[  349.477348] [drm:intel_find_shared_dpll [i915]] [CRTC:37:pipe A] allocated DPLL 0
>[  349.477360] [drm:intel_reference_shared_dpll [i915]] using DPLL 0 for pipe A
>[  349.480157] [drm:intel_power_well_enable [i915]] enabling always-on
>[  349.480173] [drm:intel_power_well_enable [i915]] enabling DC off
>[  349.480434] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  349.480457] [drm:intel_atomic_commit_tail [i915]] [ENCODER:48:DDI A]
>[  349.480474] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI B]
>[  349.480491] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  349.480506] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  349.480523] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DDI C]
>[  349.480538] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST A]
>[  349.480554] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST B]
>[  349.480567] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI D]
>[  349.480583] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[  349.480597] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[  349.480614] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[  349.480630] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[  349.480647] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[  349.480661] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[  349.480680] [drm:intel_enable_shared_dpll [i915]] enable DPLL 0 (active 1, on? 0) for crtc 37
>[  349.480695] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 0
>[  349.480719] [drm:edp_panel_on [i915]] Turn eDP port A panel power on
>[  349.480749] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle
>[  349.484337] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010
>[  349.484354] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  349.484370] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0
>[  349.484427] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  350.108554] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 00000000 control 00000060
>[  350.108661] [drm:wait_panel_status [i915]] Wait complete
>[  350.108801] [drm:edp_panel_on [i915]] Wait for panel power on
>[  350.108932] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 00000063
>[  350.142663] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010
>[  350.142744] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  350.142819] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1
>[  350.142970] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  350.309878] [drm:wait_panel_status [i915]] Wait complete
>[  350.309943] [drm:intel_power_well_enable [i915]] enabling DDI A/E IO power well
>[  350.310045] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[  350.310194] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b
>[  350.311386] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  350.311441] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  350.311494] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  350.311548] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  350.312297] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  350.312361] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  350.313316] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  350.313342] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:49:eDP-1] Link Training Passed at Link Rate = 270000, Lane count = 2
>[  350.313721] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  350.313755] [drm:intel_edp_backlight_on [i915]] 
>[  350.313767] [drm:intel_panel_enable_backlight [i915]] pipe A
>[  350.313805] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 120000
>[  350.320163] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS
>[  350.320179] [drm:intel_fbc_enable [i915]] reserved 16588800 bytes of contiguous stolen space for FBC, threshold: 1
>[  350.320192] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  350.330560] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:49:eDP-1]
>[  350.330581] [drm:intel_atomic_commit_tail [i915]] [CRTC:37:pipe A]
>[  350.330608] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[  350.580877] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped
>[  350.830864] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped
>[  351.080866] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped
>[  351.330858] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped
>[  351.580855] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped
>[  351.597473] [IGT] kms_frontbuffer_tracking: exiting, ret=0
>[  351.597532] Setting dangerous option enable_psr - tainting kernel
>[  351.597544] Setting dangerous option enable_fbc - tainting kernel
>[  351.644307] [drm:intel_atomic_check [i915]] [CONNECTOR:57:DP-1] checking for sink bpp constrains
>[  351.644325] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  351.644342] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 148500KHz
>[  351.644359] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  351.644373] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 648000
>[  351.644389] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  351.644405] [drm:intel_dump_pipe_config [i915]] [CRTC:47:pipe B][modeset]
>[  351.644420] [drm:intel_dump_pipe_config [i915]] output_types: DP (0x80)
>[  351.644434] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  351.644448] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5767168, gmch_n: 8388608, link_m: 240298, link_n: 262144, tu: 64
>[  351.644462] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  351.644475] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  351.644484] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  351.644498] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  351.644505] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  351.644519] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  351.644532] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1080, pixel rate 148500
>[  351.644546] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  351.644559] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  351.644571] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  351.644585] [drm:intel_dump_pipe_config [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  351.644597] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  351.644610] [drm:intel_dump_pipe_config [i915]] [PLANE:38:plane 1B] disabled, scaler_id = -1
>[  351.644623] [drm:intel_dump_pipe_config [i915]] [PLANE:41:plane 2B] disabled, scaler_id = -1
>[  351.644635] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor B] disabled, scaler_id = -1
>[  351.644651] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  351.644665] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[  351.644683] [drm:intel_find_shared_dpll [i915]] [CRTC:47:pipe B] allocated DPLL 1
>[  351.644698] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[  351.644721] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  351.644738] [drm:intel_disable_sagv [i915]] Disabling the SAGV
>[  351.644758] [drm:intel_atomic_commit_tail [i915]] [ENCODER:48:DDI A]
>[  351.644772] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI B]
>[  351.644806] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  351.644820] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  351.644833] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DDI C]
>[  351.644846] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST A]
>[  351.644859] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST B]
>[  351.644872] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI D]
>[  351.644885] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[  351.644897] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[  351.644911] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[  351.644926] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[  351.644940] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[  351.644953] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[  351.647325] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 2, on? 0) for crtc 47
>[  351.647344] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  351.647436] [drm:intel_power_well_enable [i915]] enabling DDI B IO power well
>[  351.648004] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  351.649139] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  351.650246] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  351.651362] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  351.652465] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  351.653562] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  351.654660] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  351.655344] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] too many retries, giving up
>[  351.655762] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  351.656858] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  351.657948] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  351.659043] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  351.660134] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  351.661223] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  351.662310] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  351.662980] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] too many retries, giving up
>[  351.664507] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  351.665594] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  351.666683] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  351.667771] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  351.668859] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  351.669948] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  351.671031] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  351.671697] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] too many retries, giving up
>[  351.672125] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  351.673209] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  351.674294] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  351.675385] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  351.676519] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  351.677610] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  351.678697] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  351.679365] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] too many retries, giving up
>[  351.680685] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  351.681939] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  351.683170] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  351.684411] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  351.685259] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  351.686214] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  351.686256] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  351.686295] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  351.686333] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  351.705022] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  351.705069] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  351.723720] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  351.724056] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:57:DP-1] Link Training Passed at Link Rate = 162000, Lane count = 4
>[  351.724477] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  351.724557] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS
>[  351.741334] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:57:DP-1]
>[  351.741360] [drm:intel_atomic_commit_tail [i915]] [CRTC:47:pipe B]
>[  351.741391] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[  351.782663] [IGT] kms_frontbuffer_tracking: executing
>[  351.829848] [drm:drm_mode_addfb2 [drm]] [FB:90]
>[  351.829885] [drm:drm_mode_addfb2 [drm]] [FB:91]
>[  351.829917] [drm:drm_mode_addfb2 [drm]] [FB:92]
>[  351.830546] [drm:drm_mode_addfb2 [drm]] [FB:93]
>[  351.836154] [drm:drm_mode_addfb2 [drm]] [FB:94]
>[  351.837534] [drm:drm_mode_addfb2 [drm]] [FB:96]
>[  351.837564] [drm:drm_mode_addfb2 [drm]] [FB:98]
>[  351.837601] [drm:drm_mode_addfb2 [drm]] [FB:102]
>[  351.837824] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  351.837834] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  352.047517] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped
>[  352.048057] [IGT] kms_frontbuffer_tracking: starting subtest fbc-2p-shrfb-fliptrack
>[  352.048158] Setting dangerous option enable_fbc - tainting kernel
>[  352.048192] Setting dangerous option enable_psr - tainting kernel
>[  352.067933] [drm:drm_mode_addfb2 [drm]] [FB:72]
>[  352.068065] [drm:drm_mode_addfb2 [drm]] [FB:90]
>[  352.068172] [drm:drm_mode_addfb2 [drm]] [FB:91]
>[  352.069355] [drm:drm_mode_addfb2 [drm]] [FB:92]
>[  352.073121] [drm:drm_mode_addfb2 [drm]] [FB:93]
>[  352.073954] [drm:drm_mode_addfb2 [drm]] [FB:94]
>[  352.073974] [drm:drm_mode_addfb2 [drm]] [FB:96]
>[  352.073995] [drm:drm_mode_addfb2 [drm]] [FB:98]
>[  352.074001] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  352.074035] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  352.074050] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[  352.074083] [drm:intel_edp_backlight_off [i915]] 
>[  352.280421] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0
>[  352.280554] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  352.300105] [drm:intel_edp_panel_off.part.31 [i915]] Turn eDP port A panel power off
>[  352.300218] [drm:intel_edp_panel_off.part.31 [i915]] Wait for panel power off time
>[  352.300349] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000003 control 00000060
>[  352.350654] [drm:wait_panel_status [i915]] Wait complete
>[  352.350717] [drm:intel_power_well_disable [i915]] disabling DDI A/E IO power well
>[  352.350798] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  352.350877] [drm:intel_disable_shared_dpll [i915]] disable DPLL 0 (active 1, on? 1) for crtc 37
>[  352.350947] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 0
>[  352.351038] [drm:intel_atomic_commit_tail [i915]] [ENCODER:48:DDI A]
>[  352.351109] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI B]
>[  352.351175] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  352.351239] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  352.351302] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DDI C]
>[  352.351364] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST A]
>[  352.351425] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST B]
>[  352.351486] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI D]
>[  352.351545] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[  352.351604] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[  352.351669] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:49:eDP-1]
>[  352.351735] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[  352.351798] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[  352.351860] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[  352.351920] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[  352.358326] [drm:intel_atomic_commit_tail [i915]] [CRTC:37:pipe A]
>[  352.358398] [drm:intel_enable_sagv [i915]] Enabling the SAGV
>[  352.358510] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  352.358611] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  352.358683] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[  352.358793] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  352.359972] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010
>[  352.360051] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  352.360124] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0
>[  352.360257] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  352.375363] [drm:intel_power_well_disable [i915]] disabling DDI B IO power well
>[  352.375447] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 2, on? 1) for crtc 47
>[  352.375521] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  352.375609] [drm:intel_atomic_commit_tail [i915]] [ENCODER:48:DDI A]
>[  352.375674] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI B]
>[  352.375738] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  352.375797] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  352.375856] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DDI C]
>[  352.375913] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST A]
>[  352.375970] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST B]
>[  352.376025] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI D]
>[  352.376140] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[  352.376222] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[  352.376297] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:57:DP-1]
>[  352.376383] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[  352.376465] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[  352.376532] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[  352.376606] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[  352.376682] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  352.376768] [drm:intel_atomic_commit_tail [i915]] [CRTC:47:pipe B]
>[  352.376832] [drm:intel_power_well_disable [i915]] disabling DC off
>[  352.376901] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  352.376959] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  352.377417] [drm:intel_power_well_disable [i915]] disabling always-on
>[  352.382203] [drm:drm_mode_addfb2 [drm]] [FB:73]
>[  352.384689] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  352.384695] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  352.384717] [drm:intel_atomic_check [i915]] [CONNECTOR:49:eDP-1] checking for sink bpp constrains
>[  352.384730] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  352.384736] [drm:drm_mode_debug_printmodeline [drm]] Modeline 52:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[  352.384749] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 138780KHz
>[  352.384765] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24
>[  352.384777] [drm:intel_dp_compute_config [i915]] DP link bw required 416340 available 540000
>[  352.384788] [drm:intel_dp_compute_config [i915]] PSR disable by flag
>[  352.384801] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  352.384813] [drm:intel_dump_pipe_config [i915]] [CRTC:37:pipe A][modeset]
>[  352.384825] [drm:intel_dump_pipe_config [i915]] output_types: EDP (0x100)
>[  352.384837] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0
>[  352.384849] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 6467616, gmch_n: 8388608, link_m: 269484, link_n: 524288, tu: 64
>[  352.384860] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  352.384870] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  352.384876] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[  352.384887] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  352.384893] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[  352.384904] [drm:intel_dump_pipe_config [i915]] crtc timings: 138780 1920 1966 1996 2080 1080 1082 1086 1112, type: 0x48 flags: 0xa
>[  352.384915] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 138780
>[  352.384925] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  352.384936] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  352.384946] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  352.384956] [drm:intel_dump_pipe_config [i915]] dpll_hw_state: ctrl1: 0x3, cfgcr1: 0x0, cfgcr2: 0x0
>[  352.384966] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  352.384977] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 1A] disabled, scaler_id = -1
>[  352.384987] [drm:intel_dump_pipe_config [i915]] [PLANE:31:plane 2A] disabled, scaler_id = -1
>[  352.384997] [drm:intel_dump_pipe_config [i915]] [PLANE:34:cursor A] disabled, scaler_id = -1
>[  352.385009] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  352.385021] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[  352.385035] [drm:intel_find_shared_dpll [i915]] [CRTC:37:pipe A] allocated DPLL 0
>[  352.385047] [drm:intel_reference_shared_dpll [i915]] using DPLL 0 for pipe A
>[  352.385579] [drm:intel_power_well_enable [i915]] enabling always-on
>[  352.385593] [drm:intel_power_well_enable [i915]] enabling DC off
>[  352.385872] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  352.385909] [drm:intel_atomic_commit_tail [i915]] [ENCODER:48:DDI A]
>[  352.385924] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI B]
>[  352.385939] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  352.385953] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  352.385968] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DDI C]
>[  352.385981] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST A]
>[  352.385996] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST B]
>[  352.386009] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI D]
>[  352.386024] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[  352.386037] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[  352.386052] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[  352.386066] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[  352.386082] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[  352.386096] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[  352.386113] [drm:intel_enable_shared_dpll [i915]] enable DPLL 0 (active 1, on? 0) for crtc 37
>[  352.386128] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 0
>[  352.386149] [drm:edp_panel_on [i915]] Turn eDP port A panel power on
>[  352.386177] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle
>[  352.988582] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 00000000 control 00000060
>[  352.988690] [drm:wait_panel_status [i915]] Wait complete
>[  352.988828] [drm:edp_panel_on [i915]] Wait for panel power on
>[  352.988960] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 00000063
>[  353.022384] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010
>[  353.022465] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  353.022541] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1
>[  353.022687] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  353.191545] [drm:wait_panel_status [i915]] Wait complete
>[  353.191610] [drm:intel_power_well_enable [i915]] enabling DDI A/E IO power well
>[  353.191712] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[  353.191863] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b
>[  353.193120] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  353.193192] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  353.193258] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  353.193323] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  353.194036] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  353.194097] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  353.195104] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  353.195166] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:49:eDP-1] Link Training Passed at Link Rate = 270000, Lane count = 2
>[  353.195818] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  353.195897] [drm:intel_edp_backlight_on [i915]] 
>[  353.195960] [drm:intel_panel_enable_backlight [i915]] pipe A
>[  353.196051] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 120000
>[  353.196277] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS
>[  353.212633] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:49:eDP-1]
>[  353.212699] [drm:intel_atomic_commit_tail [i915]] [CRTC:37:pipe A]
>[  353.212778] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[  353.462963] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped
>[  353.463047] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  353.463139] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  353.463201] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[  353.463303] [drm:intel_edp_backlight_off [i915]] 
>[  353.668330] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0
>[  353.668474] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  353.679937] [drm:intel_edp_panel_off.part.31 [i915]] Turn eDP port A panel power off
>[  353.680049] [drm:intel_edp_panel_off.part.31 [i915]] Wait for panel power off time
>[  353.680240] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000002 control 00000060
>[  353.730329] [drm:wait_panel_status [i915]] Wait complete
>[  353.730392] [drm:intel_power_well_disable [i915]] disabling DDI A/E IO power well
>[  353.730479] [drm:intel_disable_shared_dpll [i915]] disable DPLL 0 (active 1, on? 1) for crtc 37
>[  353.730554] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 0
>[  353.730646] [drm:intel_atomic_commit_tail [i915]] [ENCODER:48:DDI A]
>[  353.730716] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI B]
>[  353.730782] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  353.730845] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  353.730907] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DDI C]
>[  353.730967] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST A]
>[  353.731027] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST B]
>[  353.731086] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI D]
>[  353.731146] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[  353.731205] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[  353.731271] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:49:eDP-1]
>[  353.731337] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[  353.731402] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[  353.731464] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[  353.731526] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[  353.731601] [drm:intel_atomic_commit_tail [i915]] [CRTC:37:pipe A]
>[  353.731665] [drm:intel_power_well_disable [i915]] disabling DC off
>[  353.731721] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  353.731774] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  353.732272] [drm:intel_power_well_disable [i915]] disabling always-on
>[  353.732398] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  353.736548] [drm:drm_mode_addfb2 [drm]] [FB:73]
>[  353.737457] [drm:drm_mode_addfb2 [drm]] [FB:102]
>[  353.738645] [drm:drm_mode_addfb2 [drm]] [FB:103]
>[  353.739523] [drm:drm_mode_addfb2 [drm]] [FB:104]
>[  353.740152] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010
>[  353.740166] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  353.740180] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0
>[  353.740242] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  353.811856] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  353.811864] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  353.811887] [drm:intel_atomic_check [i915]] [CONNECTOR:49:eDP-1] checking for sink bpp constrains
>[  353.811900] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  353.811906] [drm:drm_mode_debug_printmodeline [drm]] Modeline 52:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[  353.811920] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 138780KHz
>[  353.811936] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24
>[  353.811947] [drm:intel_dp_compute_config [i915]] DP link bw required 416340 available 540000
>[  353.811959] [drm:intel_dp_compute_config [i915]] PSR disable by flag
>[  353.811972] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  353.811985] [drm:intel_dump_pipe_config [i915]] [CRTC:37:pipe A][modeset]
>[  353.812002] [drm:intel_dump_pipe_config [i915]] output_types: EDP (0x100)
>[  353.812017] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0
>[  353.812033] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 6467616, gmch_n: 8388608, link_m: 269484, link_n: 524288, tu: 64
>[  353.812048] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  353.812064] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  353.812072] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[  353.812088] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  353.812095] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[  353.812112] [drm:intel_dump_pipe_config [i915]] crtc timings: 138780 1920 1966 1996 2080 1080 1082 1086 1112, type: 0x48 flags: 0xa
>[  353.812126] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 138780
>[  353.812158] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  353.812184] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  353.812199] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  353.812212] [drm:intel_dump_pipe_config [i915]] dpll_hw_state: ctrl1: 0x3, cfgcr1: 0x0, cfgcr2: 0x0
>[  353.812226] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  353.812239] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 1A] disabled, scaler_id = -1
>[  353.812254] [drm:intel_dump_pipe_config [i915]] [PLANE:31:plane 2A] disabled, scaler_id = -1
>[  353.812266] [drm:intel_dump_pipe_config [i915]] [PLANE:34:cursor A] disabled, scaler_id = -1
>[  353.812283] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  353.812297] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[  353.812316] [drm:intel_find_shared_dpll [i915]] [CRTC:37:pipe A] allocated DPLL 0
>[  353.812330] [drm:intel_reference_shared_dpll [i915]] using DPLL 0 for pipe A
>[  353.813292] [drm:intel_power_well_enable [i915]] enabling always-on
>[  353.813302] [drm:intel_power_well_enable [i915]] enabling DC off
>[  353.813594] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  353.813630] [drm:intel_atomic_commit_tail [i915]] [ENCODER:48:DDI A]
>[  353.813645] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI B]
>[  353.813661] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  353.813675] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  353.813690] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DDI C]
>[  353.813703] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST A]
>[  353.813718] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST B]
>[  353.813731] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI D]
>[  353.813745] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[  353.813758] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[  353.813774] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[  353.813788] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[  353.813804] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[  353.813817] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[  353.813834] [drm:intel_enable_shared_dpll [i915]] enable DPLL 0 (active 1, on? 0) for crtc 37
>[  353.813848] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 0
>[  353.813870] [drm:edp_panel_on [i915]] Turn eDP port A panel power on
>[  353.813900] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle
>[  354.364391] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 00000000 control 00000060
>[  354.364484] [drm:wait_panel_status [i915]] Wait complete
>[  354.364622] [drm:edp_panel_on [i915]] Wait for panel power on
>[  354.364753] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 00000063
>[  354.397929] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010
>[  354.398010] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  354.398086] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1
>[  354.398229] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  354.567530] [drm:wait_panel_status [i915]] Wait complete
>[  354.567596] [drm:intel_power_well_enable [i915]] enabling DDI A/E IO power well
>[  354.567699] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[  354.567851] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b
>[  354.569107] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  354.569179] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  354.569243] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  354.569306] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  354.570023] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  354.570082] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  354.571091] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  354.571153] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:49:eDP-1] Link Training Passed at Link Rate = 270000, Lane count = 2
>[  354.571805] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  354.571883] [drm:intel_edp_backlight_on [i915]] 
>[  354.571946] [drm:intel_panel_enable_backlight [i915]] pipe A
>[  354.572035] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 120000
>[  354.572244] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS
>[  354.588624] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:49:eDP-1]
>[  354.588689] [drm:intel_atomic_commit_tail [i915]] [CRTC:37:pipe A]
>[  354.588769] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[  354.838961] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped
>[  354.839010] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  354.839041] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  355.105616] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped
>[  355.105665] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  355.105696] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  355.372261] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped
>[  355.372310] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  355.372342] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  355.638933] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped
>[  355.639068] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  355.639162] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  355.639223] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[  355.639327] [drm:intel_edp_backlight_off [i915]] 
>[  355.844327] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0
>[  355.844458] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  355.855611] [drm:intel_edp_panel_off.part.31 [i915]] Turn eDP port A panel power off
>[  355.855724] [drm:intel_edp_panel_off.part.31 [i915]] Wait for panel power off time
>[  355.855856] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000002 control 00000060
>[  355.906292] [drm:wait_panel_status [i915]] Wait complete
>[  355.906356] [drm:intel_power_well_disable [i915]] disabling DDI A/E IO power well
>[  355.906441] [drm:intel_disable_shared_dpll [i915]] disable DPLL 0 (active 1, on? 1) for crtc 37
>[  355.906515] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 0
>[  355.906606] [drm:intel_atomic_commit_tail [i915]] [ENCODER:48:DDI A]
>[  355.906677] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI B]
>[  355.906741] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  355.906804] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  355.906865] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DDI C]
>[  355.906926] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST A]
>[  355.906984] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST B]
>[  355.907042] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI D]
>[  355.907100] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[  355.907158] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[  355.907223] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:49:eDP-1]
>[  355.907290] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[  355.907354] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[  355.907416] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[  355.907476] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[  355.907551] [drm:intel_atomic_commit_tail [i915]] [CRTC:37:pipe A]
>[  355.907614] [drm:intel_power_well_disable [i915]] disabling DC off
>[  355.907670] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  355.907723] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  355.908217] [drm:intel_power_well_disable [i915]] disabling always-on
>[  355.908341] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  355.908572] Setting dangerous option enable_fbc - tainting kernel
>[  355.909785] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  355.909793] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  355.909817] [drm:intel_atomic_check [i915]] [CONNECTOR:49:eDP-1] checking for sink bpp constrains
>[  355.909832] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  355.909841] [drm:drm_mode_debug_printmodeline [drm]] Modeline 52:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[  355.909857] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 138780KHz
>[  355.909878] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24
>[  355.909892] [drm:intel_dp_compute_config [i915]] DP link bw required 416340 available 540000
>[  355.909908] [drm:intel_dp_compute_config [i915]] PSR disable by flag
>[  355.909922] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  355.909939] [drm:intel_dump_pipe_config [i915]] [CRTC:37:pipe A][modeset]
>[  355.909954] [drm:intel_dump_pipe_config [i915]] output_types: EDP (0x100)
>[  355.909970] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0
>[  355.909983] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 6467616, gmch_n: 8388608, link_m: 269484, link_n: 524288, tu: 64
>[  355.909999] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  355.910011] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  355.910020] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[  355.910033] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  355.910039] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[  355.910055] [drm:intel_dump_pipe_config [i915]] crtc timings: 138780 1920 1966 1996 2080 1080 1082 1086 1112, type: 0x48 flags: 0xa
>[  355.910069] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 138780
>[  355.910084] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  355.910097] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  355.910111] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  355.910124] [drm:intel_dump_pipe_config [i915]] dpll_hw_state: ctrl1: 0x3, cfgcr1: 0x0, cfgcr2: 0x0
>[  355.910138] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  355.910151] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 1A] disabled, scaler_id = -1
>[  355.910165] [drm:intel_dump_pipe_config [i915]] [PLANE:31:plane 2A] disabled, scaler_id = -1
>[  355.910178] [drm:intel_dump_pipe_config [i915]] [PLANE:34:cursor A] disabled, scaler_id = -1
>[  355.910195] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  355.910209] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[  355.910228] [drm:intel_find_shared_dpll [i915]] [CRTC:37:pipe A] allocated DPLL 0
>[  355.910242] [drm:intel_reference_shared_dpll [i915]] using DPLL 0 for pipe A
>[  355.913011] [drm:intel_power_well_enable [i915]] enabling always-on
>[  355.913021] [drm:intel_power_well_enable [i915]] enabling DC off
>[  355.913277] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  355.913294] [drm:intel_atomic_commit_tail [i915]] [ENCODER:48:DDI A]
>[  355.913307] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI B]
>[  355.913319] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  355.913331] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  355.913343] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DDI C]
>[  355.913354] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST A]
>[  355.913365] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST B]
>[  355.913376] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI D]
>[  355.913387] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[  355.913398] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[  355.913410] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[  355.913423] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[  355.913435] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[  355.913447] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[  355.913461] [drm:intel_enable_shared_dpll [i915]] enable DPLL 0 (active 1, on? 0) for crtc 37
>[  355.913473] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 0
>[  355.913493] [drm:edp_panel_on [i915]] Turn eDP port A panel power on
>[  355.913518] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle
>[  355.916318] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010
>[  355.916339] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  355.916359] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0
>[  355.916416] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  356.540404] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 00000000 control 00000060
>[  356.540511] [drm:wait_panel_status [i915]] Wait complete
>[  356.540652] [drm:edp_panel_on [i915]] Wait for panel power on
>[  356.540781] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 00000063
>[  356.574170] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010
>[  356.574251] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  356.574326] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1
>[  356.574468] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  356.741373] [drm:wait_panel_status [i915]] Wait complete
>[  356.741439] [drm:intel_power_well_enable [i915]] enabling DDI A/E IO power well
>[  356.741541] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[  356.741694] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b
>[  356.742884] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  356.742940] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  356.742993] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  356.743047] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  356.743749] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  356.743801] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  356.744807] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  356.744864] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:49:eDP-1] Link Training Passed at Link Rate = 270000, Lane count = 2
>[  356.745506] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  356.745597] [drm:intel_edp_backlight_on [i915]] 
>[  356.745653] [drm:intel_panel_enable_backlight [i915]] pipe A
>[  356.745709] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 120000
>[  356.752147] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS
>[  356.752162] [drm:intel_fbc_enable [i915]] reserved 10506240 bytes of contiguous stolen space for FBC, threshold: 1
>[  356.752175] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  356.762356] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:49:eDP-1]
>[  356.762378] [drm:intel_atomic_commit_tail [i915]] [CRTC:37:pipe A]
>[  356.762404] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[  357.012656] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped
>[  357.262663] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped
>[  357.263097] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  357.263127] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:57:DP-1]
>[  357.263223] [drm:intel_atomic_check [i915]] [CONNECTOR:57:DP-1] checking for sink bpp constrains
>[  357.263287] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  357.263350] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 148500KHz
>[  357.263412] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  357.263467] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 648000
>[  357.263528] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  357.263587] [drm:intel_dump_pipe_config [i915]] [CRTC:47:pipe B][modeset]
>[  357.263643] [drm:intel_dump_pipe_config [i915]] output_types: DP (0x80)
>[  357.263698] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  357.263754] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5767168, gmch_n: 8388608, link_m: 240298, link_n: 262144, tu: 64
>[  357.263806] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  357.263856] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  357.263883] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  357.263934] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  357.263959] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  357.264012] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  357.264119] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1080, pixel rate 148500
>[  357.264199] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  357.264268] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  357.264334] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  357.264410] [drm:intel_dump_pipe_config [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  357.264474] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  357.264549] [drm:intel_dump_pipe_config [i915]] [PLANE:38:plane 1B] disabled, scaler_id = -1
>[  357.264613] [drm:intel_dump_pipe_config [i915]] [PLANE:41:plane 2B] disabled, scaler_id = -1
>[  357.264687] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor B] disabled, scaler_id = -1
>[  357.264773] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  357.264842] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[  357.264930] [drm:intel_find_shared_dpll [i915]] [CRTC:47:pipe B] allocated DPLL 1
>[  357.265001] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[  357.265134] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  357.265212] [drm:intel_disable_sagv [i915]] Disabling the SAGV
>[  357.265328] [drm:intel_atomic_commit_tail [i915]] [ENCODER:48:DDI A]
>[  357.265393] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI B]
>[  357.265467] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  357.265530] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  357.265601] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DDI C]
>[  357.265663] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST A]
>[  357.265733] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST B]
>[  357.265795] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI D]
>[  357.265865] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[  357.265925] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[  357.266000] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[  357.266067] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[  357.266141] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[  357.266205] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[  357.279179] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 2, on? 0) for crtc 47
>[  357.279248] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  357.279401] [drm:intel_power_well_enable [i915]] enabling DDI B IO power well
>[  357.280050] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  357.281181] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  357.282286] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  357.283393] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  357.284555] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  357.285660] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  357.286766] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  357.287443] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] too many retries, giving up
>[  357.287890] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  357.288995] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  357.290100] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  357.291205] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  357.292314] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  357.293420] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  357.294525] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  357.295203] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] too many retries, giving up
>[  357.296574] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  357.297682] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  357.298787] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  357.299896] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  357.301004] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  357.302113] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  357.303217] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  357.303890] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] too many retries, giving up
>[  357.304340] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  357.305447] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  357.306426] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  357.307533] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  357.308595] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  357.309697] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  357.310802] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  357.311482] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] too many retries, giving up
>[  357.312732] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  357.313995] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  357.315248] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  357.316525] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  357.317398] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  357.318383] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  357.318443] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  357.318500] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  357.318555] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  357.337309] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  357.337376] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  357.356046] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  357.356073] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  357.356098] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  357.374694] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  357.375020] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:57:DP-1] Link Training Passed at Link Rate = 162000, Lane count = 4
>[  357.375387] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  357.375420] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS
>[  357.392165] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:57:DP-1]
>[  357.392184] [drm:intel_atomic_commit_tail [i915]] [CRTC:47:pipe B]
>[  357.392207] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[  357.629324] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped
>[  357.879514] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped
>[  357.887040] [drm:drm_mode_addfb2 [drm]] [FB:73]
>[  358.145955] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped
>[  358.395979] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped
>[  358.645987] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped
>[  358.895967] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped
>[  359.162636] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped
>[  359.412604] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped
>[  359.662627] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped
>[  359.912645] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped
>[  360.179254] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped
>[  360.429244] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped
>[  360.679241] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped
>[  360.929240] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped
>[  361.195933] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped
>[  361.445905] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped
>[  361.695928] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped
>[  361.946073] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped
>[  361.962547] [IGT] kms_frontbuffer_tracking: exiting, ret=0
>[  361.962607] Setting dangerous option enable_psr - tainting kernel
>[  361.962619] Setting dangerous option enable_fbc - tainting kernel
>[  362.073713] [IGT] kms_frontbuffer_tracking: executing
>[  362.158992] [drm:drm_mode_addfb2 [drm]] [FB:90]
>[  362.159016] [drm:drm_mode_addfb2 [drm]] [FB:91]
>[  362.159037] [drm:drm_mode_addfb2 [drm]] [FB:92]
>[  362.159459] [drm:drm_mode_addfb2 [drm]] [FB:93]
>[  362.163353] [drm:drm_mode_addfb2 [drm]] [FB:94]
>[  362.164275] [drm:drm_mode_addfb2 [drm]] [FB:96]
>[  362.164295] [drm:drm_mode_addfb2 [drm]] [FB:98]
>[  362.164317] [drm:drm_mode_addfb2 [drm]] [FB:102]
>[  362.164482] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  362.164489] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  362.379224] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped
>[  362.379971] [IGT] kms_frontbuffer_tracking: starting subtest fbcpsr-slowdraw
>[  362.380111] Setting dangerous option enable_fbc - tainting kernel
>[  362.380143] Setting dangerous option enable_psr - tainting kernel
>[  362.398842] [drm:drm_mode_addfb2 [drm]] [FB:72]
>[  362.398864] [drm:drm_mode_addfb2 [drm]] [FB:90]
>[  362.398886] [drm:drm_mode_addfb2 [drm]] [FB:91]
>[  362.399307] [drm:drm_mode_addfb2 [drm]] [FB:92]
>[  362.403058] [drm:drm_mode_addfb2 [drm]] [FB:93]
>[  362.403901] [drm:drm_mode_addfb2 [drm]] [FB:94]
>[  362.403920] [drm:drm_mode_addfb2 [drm]] [FB:96]
>[  362.403940] [drm:drm_mode_addfb2 [drm]] [FB:98]
>[  362.403946] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  362.403980] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  362.403994] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[  362.404105] [drm:intel_edp_backlight_off [i915]] 
>[  362.612142] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0
>[  362.612265] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  362.629280] [drm:intel_edp_panel_off.part.31 [i915]] Turn eDP port A panel power off
>[  362.629385] [drm:intel_edp_panel_off.part.31 [i915]] Wait for panel power off time
>[  362.629513] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000003 control 00000060
>[  362.682305] [drm:wait_panel_status [i915]] Wait complete
>[  362.682369] [drm:intel_power_well_disable [i915]] disabling DDI A/E IO power well
>[  362.682451] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  362.682529] [drm:intel_disable_shared_dpll [i915]] disable DPLL 0 (active 1, on? 1) for crtc 37
>[  362.682600] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 0
>[  362.682693] [drm:intel_atomic_commit_tail [i915]] [ENCODER:48:DDI A]
>[  362.682763] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI B]
>[  362.682830] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  362.682894] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  362.682956] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DDI C]
>[  362.683019] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST A]
>[  362.683080] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST B]
>[  362.683140] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI D]
>[  362.683200] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[  362.683259] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[  362.683325] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:49:eDP-1]
>[  362.683391] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[  362.683457] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[  362.683521] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[  362.683582] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[  362.689442] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010
>[  362.689524] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  362.689598] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0
>[  362.689722] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  362.692361] [drm:intel_atomic_commit_tail [i915]] [CRTC:37:pipe A]
>[  362.692450] [drm:intel_enable_sagv [i915]] Enabling the SAGV
>[  362.692554] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  362.692645] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  362.692709] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[  362.692812] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  362.709813] [drm:intel_power_well_disable [i915]] disabling DDI B IO power well
>[  362.709897] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 2, on? 1) for crtc 47
>[  362.709971] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  362.710060] [drm:intel_atomic_commit_tail [i915]] [ENCODER:48:DDI A]
>[  362.710126] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI B]
>[  362.710190] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  362.710249] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  362.710308] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DDI C]
>[  362.710366] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST A]
>[  362.710424] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST B]
>[  362.710480] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI D]
>[  362.710535] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[  362.710590] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[  362.710671] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:57:DP-1]
>[  362.710727] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[  362.710780] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[  362.710833] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[  362.710885] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[  362.710938] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  362.711002] [drm:intel_atomic_commit_tail [i915]] [CRTC:47:pipe B]
>[  362.711051] [drm:intel_power_well_disable [i915]] disabling DC off
>[  362.711097] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  362.711140] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  362.711574] [drm:intel_power_well_disable [i915]] disabling always-on
>[  362.715707] [drm:drm_mode_addfb2 [drm]] [FB:73]
>[  362.717724] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  362.717731] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  362.717754] [drm:intel_atomic_check [i915]] [CONNECTOR:49:eDP-1] checking for sink bpp constrains
>[  362.717767] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  362.717774] [drm:drm_mode_debug_printmodeline [drm]] Modeline 52:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[  362.717789] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 138780KHz
>[  362.717806] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24
>[  362.717818] [drm:intel_dp_compute_config [i915]] DP link bw required 416340 available 540000
>[  362.717831] [drm:intel_dp_compute_config [i915]] PSR disable by flag
>[  362.717844] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  362.717858] [drm:intel_dump_pipe_config [i915]] [CRTC:37:pipe A][modeset]
>[  362.717870] [drm:intel_dump_pipe_config [i915]] output_types: EDP (0x100)
>[  362.717883] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0
>[  362.717895] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 6467616, gmch_n: 8388608, link_m: 269484, link_n: 524288, tu: 64
>[  362.717906] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  362.717918] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  362.717923] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[  362.717935] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  362.717941] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[  362.717953] [drm:intel_dump_pipe_config [i915]] crtc timings: 138780 1920 1966 1996 2080 1080 1082 1086 1112, type: 0x48 flags: 0xa
>[  362.717965] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 138780
>[  362.717976] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  362.717988] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  362.717999] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  362.718010] [drm:intel_dump_pipe_config [i915]] dpll_hw_state: ctrl1: 0x3, cfgcr1: 0x0, cfgcr2: 0x0
>[  362.718021] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  362.718032] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 1A] disabled, scaler_id = -1
>[  362.718043] [drm:intel_dump_pipe_config [i915]] [PLANE:31:plane 2A] disabled, scaler_id = -1
>[  362.718054] [drm:intel_dump_pipe_config [i915]] [PLANE:34:cursor A] disabled, scaler_id = -1
>[  362.718067] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  362.718079] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[  362.718095] [drm:intel_find_shared_dpll [i915]] [CRTC:37:pipe A] allocated DPLL 0
>[  362.718107] [drm:intel_reference_shared_dpll [i915]] using DPLL 0 for pipe A
>[  362.718699] [drm:intel_power_well_enable [i915]] enabling always-on
>[  362.718710] [drm:intel_power_well_enable [i915]] enabling DC off
>[  362.718970] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  362.718990] [drm:intel_atomic_commit_tail [i915]] [ENCODER:48:DDI A]
>[  362.719004] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI B]
>[  362.719019] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  362.719032] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  362.719045] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DDI C]
>[  362.719058] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST A]
>[  362.719071] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST B]
>[  362.719083] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI D]
>[  362.719095] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[  362.719108] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[  362.719121] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[  362.719135] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[  362.719148] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[  362.719162] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[  362.719177] [drm:intel_enable_shared_dpll [i915]] enable DPLL 0 (active 1, on? 0) for crtc 37
>[  362.719190] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 0
>[  362.719211] [drm:edp_panel_on [i915]] Turn eDP port A panel power on
>[  362.719237] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle
>[  363.292561] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 00000000 control 00000060
>[  363.292669] [drm:wait_panel_status [i915]] Wait complete
>[  363.292807] [drm:edp_panel_on [i915]] Wait for panel power on
>[  363.292937] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 00000063
>[  363.326675] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010
>[  363.326757] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  363.326832] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1
>[  363.326953] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  363.495372] [drm:wait_panel_status [i915]] Wait complete
>[  363.495438] [drm:intel_power_well_enable [i915]] enabling DDI A/E IO power well
>[  363.495541] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[  363.495690] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b
>[  363.496929] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  363.497002] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  363.497068] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  363.497131] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  363.497846] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  363.497908] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  363.498918] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  363.498980] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:49:eDP-1] Link Training Passed at Link Rate = 270000, Lane count = 2
>[  363.499630] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  363.499712] [drm:intel_edp_backlight_on [i915]] 
>[  363.499775] [drm:intel_panel_enable_backlight [i915]] pipe A
>[  363.499866] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 120000
>[  363.504203] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS
>[  363.516524] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:49:eDP-1]
>[  363.516613] [drm:intel_atomic_commit_tail [i915]] [CRTC:37:pipe A]
>[  363.516711] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[  363.766762] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped
>[  363.766841] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  363.766934] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  363.766996] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[  363.767100] [drm:intel_edp_backlight_off [i915]] 
>[  363.972318] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0
>[  363.972449] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  363.983376] [drm:intel_edp_panel_off.part.31 [i915]] Turn eDP port A panel power off
>[  363.983488] [drm:intel_edp_panel_off.part.31 [i915]] Wait for panel power off time
>[  363.983619] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000002 control 00000060
>[  364.034023] [drm:wait_panel_status [i915]] Wait complete
>[  364.034087] [drm:intel_power_well_disable [i915]] disabling DDI A/E IO power well
>[  364.034173] [drm:intel_disable_shared_dpll [i915]] disable DPLL 0 (active 1, on? 1) for crtc 37
>[  364.034247] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 0
>[  364.034340] [drm:intel_atomic_commit_tail [i915]] [ENCODER:48:DDI A]
>[  364.034411] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI B]
>[  364.034479] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  364.034543] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  364.034605] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DDI C]
>[  364.034666] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST A]
>[  364.034726] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST B]
>[  364.034785] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI D]
>[  364.034844] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[  364.034902] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[  364.034966] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:49:eDP-1]
>[  364.035033] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[  364.035097] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[  364.035160] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[  364.035221] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[  364.035297] [drm:intel_atomic_commit_tail [i915]] [CRTC:37:pipe A]
>[  364.035361] [drm:intel_power_well_disable [i915]] disabling DC off
>[  364.035417] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  364.035470] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  364.035912] [drm:intel_power_well_disable [i915]] disabling always-on
>[  364.036011] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  364.040150] [drm:drm_mode_addfb2 [drm]] [FB:73]
>[  364.041012] [drm:drm_mode_addfb2 [drm]] [FB:102]
>[  364.042152] [drm:drm_mode_addfb2 [drm]] [FB:103]
>[  364.042997] [drm:drm_mode_addfb2 [drm]] [FB:104]
>[  364.043562] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010
>[  364.043578] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  364.043592] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0
>[  364.044028] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  364.115702] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  364.115709] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  364.115733] [drm:intel_atomic_check [i915]] [CONNECTOR:49:eDP-1] checking for sink bpp constrains
>[  364.115746] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  364.115752] [drm:drm_mode_debug_printmodeline [drm]] Modeline 52:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[  364.115766] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 138780KHz
>[  364.115781] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24
>[  364.115793] [drm:intel_dp_compute_config [i915]] DP link bw required 416340 available 540000
>[  364.115805] [drm:intel_dp_compute_config [i915]] PSR disable by flag
>[  364.115817] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  364.115829] [drm:intel_dump_pipe_config [i915]] [CRTC:37:pipe A][modeset]
>[  364.115841] [drm:intel_dump_pipe_config [i915]] output_types: EDP (0x100)
>[  364.115853] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0
>[  364.115865] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 6467616, gmch_n: 8388608, link_m: 269484, link_n: 524288, tu: 64
>[  364.115876] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  364.115887] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  364.115892] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[  364.115903] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  364.115908] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[  364.115920] [drm:intel_dump_pipe_config [i915]] crtc timings: 138780 1920 1966 1996 2080 1080 1082 1086 1112, type: 0x48 flags: 0xa
>[  364.115930] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 138780
>[  364.115941] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  364.115951] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  364.115962] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  364.115972] [drm:intel_dump_pipe_config [i915]] dpll_hw_state: ctrl1: 0x3, cfgcr1: 0x0, cfgcr2: 0x0
>[  364.115982] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  364.115996] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 1A] disabled, scaler_id = -1
>[  364.116007] [drm:intel_dump_pipe_config [i915]] [PLANE:31:plane 2A] disabled, scaler_id = -1
>[  364.116017] [drm:intel_dump_pipe_config [i915]] [PLANE:34:cursor A] disabled, scaler_id = -1
>[  364.116030] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  364.116043] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[  364.116060] [drm:intel_find_shared_dpll [i915]] [CRTC:37:pipe A] allocated DPLL 0
>[  364.116073] [drm:intel_reference_shared_dpll [i915]] using DPLL 0 for pipe A
>[  364.117031] [drm:intel_power_well_enable [i915]] enabling always-on
>[  364.117040] [drm:intel_power_well_enable [i915]] enabling DC off
>[  364.117332] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  364.117366] [drm:intel_atomic_commit_tail [i915]] [ENCODER:48:DDI A]
>[  364.117378] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI B]
>[  364.117390] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  364.117401] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  364.117413] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DDI C]
>[  364.117423] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST A]
>[  364.117434] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST B]
>[  364.117445] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI D]
>[  364.117456] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[  364.117466] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[  364.117478] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[  364.117490] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[  364.117502] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[  364.117513] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[  364.117526] [drm:intel_enable_shared_dpll [i915]] enable DPLL 0 (active 1, on? 0) for crtc 37
>[  364.117537] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 0
>[  364.117556] [drm:edp_panel_on [i915]] Turn eDP port A panel power on
>[  364.117580] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle
>[  364.668460] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 00000000 control 00000060
>[  364.668552] [drm:wait_panel_status [i915]] Wait complete
>[  364.668662] [drm:edp_panel_on [i915]] Wait for panel power on
>[  364.668793] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 00000063
>[  364.702481] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010
>[  364.702563] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  364.702637] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1
>[  364.702757] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  364.869470] [drm:wait_panel_status [i915]] Wait complete
>[  364.869536] [drm:intel_power_well_enable [i915]] enabling DDI A/E IO power well
>[  364.869640] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[  364.869791] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b
>[  364.871025] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  364.871099] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  364.871165] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  364.871229] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  364.871943] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  364.872003] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  364.873051] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  364.873116] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:49:eDP-1] Link Training Passed at Link Rate = 270000, Lane count = 2
>[  364.873769] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  364.873849] [drm:intel_edp_backlight_on [i915]] 
>[  364.873912] [drm:intel_panel_enable_backlight [i915]] pipe A
>[  364.874002] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 120000
>[  364.880137] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS
>[  364.890616] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:49:eDP-1]
>[  364.890692] [drm:intel_atomic_commit_tail [i915]] [CRTC:37:pipe A]
>[  364.890778] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[  365.140911] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped
>[  365.140961] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  365.140993] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  365.407572] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped
>[  365.407621] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  365.407652] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  365.674235] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped
>[  365.674285] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  365.674316] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  365.940898] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped
>[  365.941031] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  365.941126] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  365.941188] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[  365.941291] [drm:intel_edp_backlight_off [i915]] 
>[  366.148168] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0
>[  366.148300] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  366.159485] [drm:intel_edp_panel_off.part.31 [i915]] Turn eDP port A panel power off
>[  366.159598] [drm:intel_edp_panel_off.part.31 [i915]] Wait for panel power off time
>[  366.159732] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000002 control 00000060
>[  366.210142] [drm:wait_panel_status [i915]] Wait complete
>[  366.210205] [drm:intel_power_well_disable [i915]] disabling DDI A/E IO power well
>[  366.210292] [drm:intel_disable_shared_dpll [i915]] disable DPLL 0 (active 1, on? 1) for crtc 37
>[  366.210367] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 0
>[  366.210459] [drm:intel_atomic_commit_tail [i915]] [ENCODER:48:DDI A]
>[  366.210530] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI B]
>[  366.210596] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  366.210661] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  366.210723] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DDI C]
>[  366.210785] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST A]
>[  366.210846] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST B]
>[  366.210906] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI D]
>[  366.210965] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[  366.211025] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[  366.211090] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:49:eDP-1]
>[  366.211156] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[  366.211220] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[  366.211284] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[  366.211344] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[  366.211420] [drm:intel_atomic_commit_tail [i915]] [CRTC:37:pipe A]
>[  366.211485] [drm:intel_power_well_disable [i915]] disabling DC off
>[  366.211540] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  366.211593] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  366.212091] [drm:intel_power_well_disable [i915]] disabling always-on
>[  366.212213] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  366.212447] Setting dangerous option enable_fbc - tainting kernel
>[  366.212471] Setting dangerous option enable_psr - tainting kernel
>[  366.213576] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  366.213585] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  366.213608] [drm:intel_atomic_check [i915]] [CONNECTOR:49:eDP-1] checking for sink bpp constrains
>[  366.213623] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  366.213632] [drm:drm_mode_debug_printmodeline [drm]] Modeline 52:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[  366.213648] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 138780KHz
>[  366.213669] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24
>[  366.213683] [drm:intel_dp_compute_config [i915]] DP link bw required 416340 available 540000
>[  366.213700] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  366.213715] [drm:intel_dump_pipe_config [i915]] [CRTC:37:pipe A][modeset]
>[  366.213731] [drm:intel_dump_pipe_config [i915]] output_types: EDP (0x100)
>[  366.213745] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0
>[  366.213761] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 6467616, gmch_n: 8388608, link_m: 269484, link_n: 524288, tu: 64
>[  366.213774] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  366.213789] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  366.213796] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[  366.213811] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  366.213817] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[  366.213833] [drm:intel_dump_pipe_config [i915]] crtc timings: 138780 1920 1966 1996 2080 1080 1082 1086 1112, type: 0x48 flags: 0xa
>[  366.213846] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 138780
>[  366.213861] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  366.213874] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  366.213889] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  366.213902] [drm:intel_dump_pipe_config [i915]] dpll_hw_state: ctrl1: 0x3, cfgcr1: 0x0, cfgcr2: 0x0
>[  366.213916] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  366.213929] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 1A] disabled, scaler_id = -1
>[  366.213944] [drm:intel_dump_pipe_config [i915]] [PLANE:31:plane 2A] disabled, scaler_id = -1
>[  366.213956] [drm:intel_dump_pipe_config [i915]] [PLANE:34:cursor A] disabled, scaler_id = -1
>[  366.213973] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  366.213987] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[  366.214006] [drm:intel_find_shared_dpll [i915]] [CRTC:37:pipe A] allocated DPLL 0
>[  366.214020] [drm:intel_reference_shared_dpll [i915]] using DPLL 0 for pipe A
>[  366.216122] [drm:intel_power_well_enable [i915]] enabling always-on
>[  366.216132] [drm:intel_power_well_enable [i915]] enabling DC off
>[  366.216387] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  366.216404] [drm:intel_atomic_commit_tail [i915]] [ENCODER:48:DDI A]
>[  366.216417] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI B]
>[  366.216429] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  366.216441] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  366.216453] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DDI C]
>[  366.216464] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST A]
>[  366.216475] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST B]
>[  366.216486] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI D]
>[  366.216497] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[  366.216508] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[  366.216520] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[  366.216532] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[  366.216544] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[  366.216556] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[  366.216570] [drm:intel_enable_shared_dpll [i915]] enable DPLL 0 (active 1, on? 0) for crtc 37
>[  366.216583] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 0
>[  366.216602] [drm:edp_panel_on [i915]] Turn eDP port A panel power on
>[  366.216627] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle
>[  366.220320] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010
>[  366.220341] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  366.220361] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0
>[  366.220416] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  366.844567] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 00000000 control 00000060
>[  366.844690] [drm:wait_panel_status [i915]] Wait complete
>[  366.844828] [drm:edp_panel_on [i915]] Wait for panel power on
>[  366.844961] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 00000063
>[  366.878641] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010
>[  366.878722] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  366.878797] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1
>[  366.878944] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  367.045446] [drm:wait_panel_status [i915]] Wait complete
>[  367.045512] [drm:intel_power_well_enable [i915]] enabling DDI A/E IO power well
>[  367.045616] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[  367.045767] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b
>[  367.046970] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  367.047032] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  367.047092] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  367.047153] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  367.047862] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  367.047918] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  367.047975] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  367.048735] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  367.048785] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  367.049731] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  367.049756] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:49:eDP-1] Link Training Passed at Link Rate = 270000, Lane count = 2
>[  367.050135] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  367.050168] [drm:intel_edp_backlight_on [i915]] 
>[  367.050180] [drm:intel_panel_enable_backlight [i915]] pipe A
>[  367.050220] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 120000
>[  367.056292] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS
>[  367.056308] [drm:intel_fbc_enable [i915]] reserved 8294400 bytes of contiguous stolen space for FBC, threshold: 1
>[  367.056322] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  367.066976] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:49:eDP-1]
>[  367.066998] [drm:intel_atomic_commit_tail [i915]] [CRTC:37:pipe A]
>[  367.067025] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[  367.317292] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped
>[  367.567290] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped
>[  370.652448] [drm:edp_panel_vdd_off_sync [i915]] Turning eDP port A VDD off
>[  370.652594] [drm:edp_panel_vdd_off_sync [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x00000067
>[  370.652651] [drm:intel_power_well_disable [i915]] disabling DC off
>[  370.652709] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  370.652762] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  373.604921] [drm:intel_power_well_enable [i915]] enabling DC off
>[  373.604981] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  373.605079] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[  373.605231] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006f
>[  373.804892] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped
>[  374.054876] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped
>[  377.308345] [drm:edp_panel_vdd_off_sync [i915]] Turning eDP port A VDD off
>[  377.308489] [drm:edp_panel_vdd_off_sync [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x00000067
>[  377.308547] [drm:intel_power_well_disable [i915]] disabling DC off
>[  377.308604] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  377.308657] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  378.091561] [drm:intel_power_well_enable [i915]] enabling DC off
>[  378.091621] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  378.091720] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[  378.091875] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006f
>[  378.291526] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped
>[  378.541512] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped
>[  381.660300] [drm:edp_panel_vdd_off_sync [i915]] Turning eDP port A VDD off
>[  381.660446] [drm:edp_panel_vdd_off_sync [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x00000067
>[  381.660503] [drm:intel_power_well_disable [i915]] disabling DC off
>[  381.660560] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  381.660613] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  382.577512] [drm:intel_power_well_enable [i915]] enabling DC off
>[  382.577565] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  382.577653] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[  382.577801] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006f
>[  382.777794] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped
>[  383.027791] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped
>[  383.437989] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[  383.438062] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[  383.438178] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[  383.438250] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  383.438754] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 00 00 04 00 0f 00 04
>[  383.439102] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  383.439177] [drm:i915_hotplug_work_func [i915]] running encoder hotplug functions
>[  383.439239] [drm:i915_hotplug_work_func [i915]] Connector DP-1 (pin 5) received hotplug event.
>[  383.439298] [drm:intel_dp_detect [i915]] [CONNECTOR:57:DP-1]
>[  383.439343] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  383.439720] [drm:lspcon_wake_native_aux_ch [i915]] Native AUX CH up, DPCD version: 1.2
>[  383.439789] [drm:lspcon_resume [i915]] LSPCON recovering in PCON mode after 0 ms
>[  383.440236] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  383.441358] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  383.442478] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  383.443600] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  383.444663] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  383.445788] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  383.446911] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  383.447610] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] too many retries, giving up
>[  383.448092] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  383.449225] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  383.450319] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  383.451448] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  383.452579] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  383.453705] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  383.454827] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  383.455522] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] too many retries, giving up
>[  383.456583] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  383.457713] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  383.458831] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  383.459955] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  383.461080] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  383.462205] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  383.463327] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  383.464050] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] too many retries, giving up
>[  383.464501] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  383.465636] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  383.466753] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  383.467877] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  383.469002] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  383.470129] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  383.471259] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  383.471950] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] too many retries, giving up
>[  383.473622] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  383.474893] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  383.476164] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  383.477432] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  383.478321] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  383.478793] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 00 00 04 00 0f 00 04
>[  383.479140] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  383.479211] [drm:i915_hotplug_work_func [i915]] [CONNECTOR:57:DP-1] status updated from connected to disconnected
>[  383.685563] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[  383.685635] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[  383.685733] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[  383.685792] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  383.686286] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 00 00 04 00 0f 00 04
>[  383.687042] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  383.687114] [drm:i915_hotplug_work_func [i915]] running encoder hotplug functions
>[  383.687174] [drm:i915_hotplug_work_func [i915]] Connector DP-1 (pin 5) received hotplug event.
>[  383.687232] [drm:intel_dp_detect [i915]] [CONNECTOR:57:DP-1]
>[  383.687277] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  383.687652] [drm:lspcon_wake_native_aux_ch [i915]] Native AUX CH up, DPCD version: 1.2
>[  383.687721] [drm:lspcon_resume [i915]] LSPCON recovering in PCON mode after 0 ms
>[  383.688160] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  383.689430] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  383.690702] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  383.691967] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  383.693242] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  383.694132] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  383.694606] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 00 00 04 00 0f 00 04
>[  383.695378] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>[  383.695436] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000
>[  383.695490] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000
>[  383.695890] [drm:drm_dp_read_desc [drm_kms_helper]] DP branch: OUI 00-60-ad dev-ID MC2800 HW-rev 2.2 SW-rev 1.70 quirks 0x0000
>[  383.696297] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  383.697072] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  383.698317] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  383.699595] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  383.700783] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  383.702052] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  383.703314] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  383.704613] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  383.705880] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  383.707142] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  383.708542] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  383.709940] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  383.711343] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  383.712759] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  383.714155] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  383.715552] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  383.716883] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  383.718273] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  383.719530] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  383.720718] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  383.721989] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  383.723252] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  383.724651] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  383.726053] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  383.727446] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  383.728840] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  383.730238] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  383.731636] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  383.732968] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  383.734350] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  383.735511] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  383.735579] [drm:i915_hotplug_work_func [i915]] [CONNECTOR:57:DP-1] status updated from disconnected to connected
>[  386.268339] [drm:edp_panel_vdd_off_sync [i915]] Turning eDP port A VDD off
>[  386.268484] [drm:edp_panel_vdd_off_sync [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x00000067
>[  386.268541] [drm:intel_power_well_disable [i915]] disabling DC off
>[  386.268598] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  386.268651] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  387.064494] [drm:intel_power_well_enable [i915]] enabling DC off
>[  387.064554] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  387.064650] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[  387.064806] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006f
>[  387.264453] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped
>[  387.514670] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped
>[  388.450310] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[  388.450391] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[  388.450516] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[  388.450583] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  388.712576] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[  388.712658] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[  390.620335] [drm:edp_panel_vdd_off_sync [i915]] Turning eDP port A VDD off
>[  390.620481] [drm:edp_panel_vdd_off_sync [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x00000067
>[  394.290964] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[  394.291046] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[  394.552228] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[  394.552308] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[  397.532200] [drm:drm_atomic_helper_wait_for_flip_done [drm_kms_helper]] *ERROR* [CRTC:37:pipe A] flip_done timed out
>[  397.532479] [IGT] kms_frontbuffer_tracking: exiting, ret=0
>[  397.532550] Setting dangerous option enable_psr - tainting kernel
>[  397.532565] Setting dangerous option enable_fbc - tainting kernel
>[  397.532811] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 00 00 04 00 0f 00 04
>[  397.534449] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  397.534507] [drm:intel_power_well_disable [i915]] disabling DC off
>[  397.534558] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  397.534607] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  397.534684] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[  397.534732] [drm:intel_power_well_enable [i915]] enabling DC off
>[  397.534780] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  397.534832] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  397.535316] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 00 00 04 00 0f 00 04
>[  397.536744] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  397.536797] [drm:intel_power_well_disable [i915]] disabling DC off
>[  397.536846] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  397.536895] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  397.564049] [drm:intel_atomic_check [i915]] [CONNECTOR:57:DP-1] checking for sink bpp constrains
>[  397.564063] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  397.564077] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 148500KHz
>[  397.564091] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  397.564103] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 648000
>[  397.564116] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  397.564129] [drm:intel_dump_pipe_config [i915]] [CRTC:47:pipe B][modeset]
>[  397.564141] [drm:intel_dump_pipe_config [i915]] output_types: DP (0x80)
>[  397.564153] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  397.564164] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5767168, gmch_n: 8388608, link_m: 240298, link_n: 262144, tu: 64
>[  397.564175] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  397.564185] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  397.564192] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  397.564203] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  397.564208] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  397.564220] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  397.564230] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1080, pixel rate 148500
>[  397.564241] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  397.564251] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  397.564262] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  397.564272] [drm:intel_dump_pipe_config [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  397.564283] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  397.564293] [drm:intel_dump_pipe_config [i915]] [PLANE:38:plane 1B] disabled, scaler_id = -1
>[  397.564304] [drm:intel_dump_pipe_config [i915]] [PLANE:41:plane 2B] disabled, scaler_id = -1
>[  397.564314] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor B] disabled, scaler_id = -1
>[  397.564326] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  397.564338] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[  397.564353] [drm:intel_find_shared_dpll [i915]] [CRTC:47:pipe B] allocated DPLL 1
>[  397.564364] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[  400.127090] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[  400.127171] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[  400.127297] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[  400.127361] [drm:intel_power_well_enable [i915]] enabling DC off
>[  400.127427] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  400.127489] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  400.387465] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[  400.387546] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[  405.957829] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[  405.957910] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[  406.218831] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[  406.218913] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[  407.772287] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [CRTC:37:pipe A] flip_done timed out
>[  411.794020] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[  411.794101] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[  412.055347] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[  412.055428] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[  417.623851] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[  417.623931] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[  417.883452] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[  417.883534] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[  418.012252] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [PLANE:28:plane 1A] flip_done timed out
>[  418.012345] [drm:intel_disable_sagv [i915]] Disabling the SAGV
>[  418.012432] [drm:intel_atomic_commit_tail [i915]] [ENCODER:48:DDI A]
>[  418.012507] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI B]
>[  418.012576] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  418.012643] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  418.012706] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DDI C]
>[  418.012768] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST A]
>[  418.012828] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST B]
>[  418.012888] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI D]
>[  418.012947] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[  418.013005] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[  418.013071] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[  418.013139] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[  418.013203] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[  418.013266] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[  418.013627] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 2, on? 0) for crtc 47
>[  418.013696] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  418.013850] [drm:intel_power_well_enable [i915]] enabling DDI B IO power well
>[  418.014459] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  418.015713] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  418.016914] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  418.018161] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  418.019416] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  418.020318] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  418.021305] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  418.021365] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  418.021421] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  418.021476] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  418.040153] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  418.040180] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  418.057916] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  418.058239] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:57:DP-1] Link Training Passed at Link Rate = 162000, Lane count = 4
>[  418.058623] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  418.058690] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS
>[  428.252250] [drm:drm_atomic_helper_wait_for_flip_done [drm_kms_helper]] *ERROR* [CRTC:37:pipe A] flip_done timed out
>[  428.252384] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:57:DP-1]
>[  428.252470] [drm:intel_atomic_commit_tail [i915]] [CRTC:47:pipe B]
>[  428.252567] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[  428.252620] [drm:drm_fb_helper_hotplug_event.part.30 [drm_kms_helper]] 
>[  428.252632] [drm:drm_setup_crtcs [drm_kms_helper]] 
>[  428.252647] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:49:eDP-1]
>[  428.253149] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 00 00 04 00 0f 00 04
>[  428.254568] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[  428.254643] [drm:intel_dp_detect [i915]] [CONNECTOR:49:eDP-1]
>[  428.254712] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>[  428.254772] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[  428.254828] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[  428.254897] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[  428.255029] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006f
>[  428.255467] [drm:drm_dp_read_desc [drm_kms_helper]] DP sink: OUI 00-1c-f8 dev-ID  HW-rev 0.1 SW-rev 1.22 quirks 0x0000
>[  428.256217] [drm:drm_add_edid_modes [drm]] ELD: no CEA Extension found
>[  428.256265] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:49:eDP-1] probed modes :
>[  428.256292] [drm:drm_mode_debug_printmodeline [drm]] Modeline 50:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[  428.256306] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:57:DP-1]
>[  428.256776] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 00 00 04 00 0f 00 04
>[  428.258085] [drm:intel_dp_detect [i915]] [CONNECTOR:57:DP-1]
>[  428.258401] [drm:lspcon_wake_native_aux_ch [i915]] Native AUX CH up, DPCD version: 1.2
>[  428.258441] [drm:lspcon_resume [i915]] LSPCON recovering in PCON mode after 0 ms
>[  428.258854] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  428.260124] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  428.261407] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  428.262683] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  428.263927] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  428.264772] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  428.265170] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 00 00 04 00 0f 00 04
>[  428.265849] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>[  428.265863] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000
>[  428.265877] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000
>[  428.266239] [drm:drm_dp_read_desc [drm_kms_helper]] DP branch: OUI 00-60-ad dev-ID MC2800 HW-rev 2.2 SW-rev 1.70 quirks 0x0000
>[  428.266527] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[  428.267252] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  428.268497] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  428.269746] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  428.270988] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  428.272231] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  428.273453] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  428.274691] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  428.275926] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  428.277156] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  428.278517] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  428.279880] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  428.281241] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  428.282604] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  428.283967] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  428.285332] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  428.286696] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  428.288052] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  428.289283] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  428.290520] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  428.291755] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  428.292976] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  428.294337] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  428.295701] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  428.297054] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  428.298415] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  428.299775] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  428.301140] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  428.302502] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  428.303854] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  428.304946] [drm:drm_add_edid_modes [drm]] ELD monitor HP E232
>[  428.304954] [drm:drm_add_edid_modes [drm]] HDMI: latency present 0 0, video latency 0 0, audio latency 0 0
>[  428.304959] [drm:drm_add_edid_modes [drm]] ELD size 28, SAD count 0
>[  428.304965] [drm:drm_add_edid_modes [drm]] HDMI: DVI dual 0, max TMDS clock 170000 kHz
>[  428.305046] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:57:DP-1] probed modes :
>[  428.305053] [drm:drm_mode_debug_printmodeline [drm]] Modeline 74:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  428.305059] [drm:drm_mode_debug_printmodeline [drm]] Modeline 97:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[  428.305065] [drm:drm_mode_debug_printmodeline [drm]] Modeline 76:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[  428.305070] [drm:drm_mode_debug_printmodeline [drm]] Modeline 81:"1680x1050" 60 119000 1680 1728 1760 1840 1050 1053 1059 1080 0x40 0x9
>[  428.305076] [drm:drm_mode_debug_printmodeline [drm]] Modeline 80:"1600x900" 60 108000 1600 1624 1704 1800 900 901 904 1000 0x40 0x5
>[  428.305081] [drm:drm_mode_debug_printmodeline [drm]] Modeline 84:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[  428.305086] [drm:drm_mode_debug_printmodeline [drm]] Modeline 82:"1440x900" 60 88750 1440 1488 1520 1600 900 903 909 926 0x40 0x9
>[  428.305091] [drm:drm_mode_debug_printmodeline [drm]] Modeline 83:"1280x800" 60 71000 1280 1328 1360 1440 800 803 809 823 0x40 0x9
>[  428.305096] [drm:drm_mode_debug_printmodeline [drm]] Modeline 77:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  428.305102] [drm:drm_mode_debug_printmodeline [drm]] Modeline 99:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[  428.305107] [drm:drm_mode_debug_printmodeline [drm]] Modeline 78:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[  428.305112] [drm:drm_mode_debug_printmodeline [drm]] Modeline 87:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[  428.305117] [drm:drm_mode_debug_printmodeline [drm]] Modeline 85:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[  428.305122] [drm:drm_mode_debug_printmodeline [drm]] Modeline 95:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[  428.305127] [drm:drm_mode_debug_printmodeline [drm]] Modeline 100:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[  428.305132] [drm:drm_mode_debug_printmodeline [drm]] Modeline 79:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[  428.305137] [drm:drm_mode_debug_printmodeline [drm]] Modeline 101:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[  428.305142] [drm:drm_mode_debug_printmodeline [drm]] Modeline 86:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[  428.305146] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:61:DP-2]
>[  428.305165] [drm:intel_dp_detect [i915]] [CONNECTOR:61:DP-2]
>[  428.305181] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:61:DP-2] disconnected
>[  428.305184] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:64:HDMI-A-1]
>[  428.305203] [drm:intel_hdmi_detect [i915]] [CONNECTOR:64:HDMI-A-1]
>[  428.305525] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  428.305541] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  428.305857] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[  428.305865] [drm:drm_do_probe_ddc_edid [drm]] drm: skipping non-existent adapter i915 gmbus dpc
>[  428.306196] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  428.306211] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[  428.306526] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[  428.306530] [drm:drm_dp_dual_mode_detect [drm_kms_helper]] DP dual mode HDMI ID:  (err -6)
>[  428.306533] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:64:HDMI-A-1] disconnected
>[  428.306536] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:67:DP-3]
>[  428.306552] [drm:intel_dp_detect [i915]] [CONNECTOR:67:DP-3]
>[  428.306567] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:67:DP-3] disconnected
>[  428.306570] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:70:HDMI-A-2]
>[  428.306585] [drm:intel_hdmi_detect [i915]] [CONNECTOR:70:HDMI-A-2]
>[  428.316334] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0050 w(1)
>[  428.316403] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK on first message, retry
>[  428.326164] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0050 w(1)
>[  428.326195] [drm:drm_do_probe_ddc_edid [drm]] drm: skipping non-existent adapter i915 gmbus dpd
>[  428.335339] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0040 w(1)
>[  428.335404] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK on first message, retry
>[  428.344533] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0040 w(1)
>[  428.344550] [drm:drm_dp_dual_mode_detect [drm_kms_helper]] DP dual mode HDMI ID:  (err -6)
>[  428.344563] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:70:HDMI-A-2] disconnected
>[  428.344576] [drm:drm_setup_crtcs [drm_kms_helper]] connector 49 enabled? yes
>[  428.344586] [drm:drm_setup_crtcs [drm_kms_helper]] connector 57 enabled? yes
>[  428.344594] [drm:drm_setup_crtcs [drm_kms_helper]] connector 61 enabled? no
>[  428.344603] [drm:drm_setup_crtcs [drm_kms_helper]] connector 64 enabled? no
>[  428.344612] [drm:drm_setup_crtcs [drm_kms_helper]] connector 67 enabled? no
>[  428.344621] [drm:drm_setup_crtcs [drm_kms_helper]] connector 70 enabled? no
>[  428.344689] [drm:intel_fb_initial_config [i915]] Not using firmware configuration
>[  428.344701] [drm:drm_setup_crtcs [drm_kms_helper]] looking for cmdline mode on connector 49
>[  428.344710] [drm:drm_setup_crtcs [drm_kms_helper]] looking for preferred mode on connector 49 0
>[  428.344719] [drm:drm_setup_crtcs [drm_kms_helper]] found mode 1920x1080
>[  428.344728] [drm:drm_setup_crtcs [drm_kms_helper]] looking for cmdline mode on connector 57
>[  428.344737] [drm:drm_setup_crtcs [drm_kms_helper]] looking for preferred mode on connector 57 0
>[  428.344745] [drm:drm_setup_crtcs [drm_kms_helper]] found mode 1920x1080
>[  428.344755] [drm:drm_setup_crtcs [drm_kms_helper]] picking CRTCs for 1920x1080 config
>[  428.344772] [drm:drm_setup_crtcs [drm_kms_helper]] desired mode 1920x1080 set on crtc 37 (0,0)
>[  428.344783] [drm:drm_setup_crtcs [drm_kms_helper]] desired mode 1920x1080 set on crtc 47 (0,0)
>[  431.324338] [drm:edp_panel_vdd_off_sync [i915]] Turning eDP port A VDD off
>[  431.324483] [drm:edp_panel_vdd_off_sync [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x00000067
>[  438.492261] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [CRTC:37:pipe A] flip_done timed out
>[  448.732221] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [CONNECTOR:49:eDP-1] flip_done timed out
>[  458.972246] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [PLANE:28:plane 1A] flip_done timed out
>[  469.212356] [drm:drm_atomic_helper_wait_for_flip_done [drm_kms_helper]] *ERROR* [CRTC:37:pipe A] flip_done timed out
>[  469.260221] [IGT] kms_frontbuffer_tracking: executing
>[  469.297689] [drm:drm_mode_addfb2 [drm]] [FB:72]
>[  469.297723] [drm:drm_mode_addfb2 [drm]] [FB:73]
>[  469.297752] [drm:drm_mode_addfb2 [drm]] [FB:92]
>[  469.298319] [drm:drm_mode_addfb2 [drm]] [FB:93]
>[  469.302567] [drm:drm_mode_addfb2 [drm]] [FB:94]
>[  469.303403] [drm:drm_mode_addfb2 [drm]] [FB:96]
>[  469.303422] [drm:drm_mode_addfb2 [drm]] [FB:98]
>[  469.303443] [drm:drm_mode_addfb2 [drm]] [FB:102]
>[  469.303611] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  469.303618] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  479.452347] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [CRTC:37:pipe A] flip_done timed out
>[  489.692260] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [CONNECTOR:49:eDP-1] flip_done timed out
>[  499.932229] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [PLANE:28:plane 1A] flip_done timed out
>[  510.172352] [drm:drm_atomic_helper_wait_for_flip_done [drm_kms_helper]] *ERROR* [CRTC:37:pipe A] flip_done timed out
>[  510.172550] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[  510.172706] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006f
>[  510.362318] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped
>[  510.362555] [IGT] kms_frontbuffer_tracking: starting subtest psr-1p-offscren-pri-indfb-draw-blt
>[  510.362632] Setting dangerous option enable_fbc - tainting kernel
>[  510.362654] Setting dangerous option enable_psr - tainting kernel
>[  513.500324] [drm:edp_panel_vdd_off_sync [i915]] Turning eDP port A VDD off
>[  513.500470] [drm:edp_panel_vdd_off_sync [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x00000067
>[  520.412065] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [CRTC:37:pipe A] flip_done timed out
>[  530.652347] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [PLANE:28:plane 1A] flip_done timed out
>[  540.892243] [drm:drm_atomic_helper_wait_for_flip_done [drm_kms_helper]] *ERROR* [CRTC:37:pipe A] flip_done timed out
>[  540.896645] [drm:drm_mode_addfb2 [drm]] [FB:72]
>[  540.896746] [drm:drm_mode_addfb2 [drm]] [FB:73]
>[  540.896849] [drm:drm_mode_addfb2 [drm]] [FB:75]
>[  540.897970] [drm:drm_mode_addfb2 [drm]] [FB:92]
>[  540.901699] [drm:drm_mode_addfb2 [drm]] [FB:93]
>[  540.902536] [drm:drm_mode_addfb2 [drm]] [FB:94]
>[  540.902556] [drm:drm_mode_addfb2 [drm]] [FB:96]
>[  540.902575] [drm:drm_mode_addfb2 [drm]] [FB:98]
>[  540.902682] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  540.902716] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  540.902730] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[  551.132323] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [CRTC:37:pipe A] flip_done timed out
>[  561.372345] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [CONNECTOR:49:eDP-1] flip_done timed out
>[  571.612203] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [PLANE:28:plane 1A] flip_done timed out
>[  571.612328] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[  571.612484] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006f
>[  571.612761] [drm:intel_edp_backlight_off [i915]] 
>[  571.820411] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0
>[  571.820549] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  571.829214] [drm:intel_edp_panel_off.part.31 [i915]] Turn eDP port A panel power off
>[  571.829328] [drm:intel_edp_panel_off.part.31 [i915]] Wait for panel power off time
>[  571.829460] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000003 control 00000060
>[  571.879530] [drm:wait_panel_status [i915]] Wait complete
>[  571.879593] [drm:intel_power_well_disable [i915]] disabling DDI A/E IO power well
>[  571.879676] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  571.879756] [drm:intel_disable_shared_dpll [i915]] disable DPLL 0 (active 1, on? 1) for crtc 37
>[  571.879831] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 0
>[  571.879924] [drm:intel_atomic_commit_tail [i915]] [ENCODER:48:DDI A]
>[  571.879995] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI B]
>[  571.880098] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  571.880168] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  571.880242] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DDI C]
>[  571.880310] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST A]
>[  571.880378] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST B]
>[  571.880449] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI D]
>[  571.880512] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[  571.880580] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[  571.880647] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:49:eDP-1]
>[  571.880718] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[  571.880784] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[  571.880849] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[  571.880912] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[  571.889213] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010
>[  571.889294] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  571.889369] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0
>[  571.889487] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  571.892660] [drm:intel_atomic_commit_tail [i915]] [CRTC:37:pipe A]
>[  571.892731] [drm:intel_enable_sagv [i915]] Enabling the SAGV
>[  571.892843] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  571.892944] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  571.893017] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[  571.893128] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  571.910089] [drm:intel_power_well_disable [i915]] disabling DDI B IO power well
>[  571.910172] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 2, on? 1) for crtc 47
>[  571.910245] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  571.910333] [drm:intel_atomic_commit_tail [i915]] [ENCODER:48:DDI A]
>[  571.910398] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI B]
>[  571.910463] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  571.910523] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  571.910582] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DDI C]
>[  571.910639] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST A]
>[  571.910697] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST B]
>[  571.910753] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI D]
>[  571.910807] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[  571.910862] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[  571.910923] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:57:DP-1]
>[  571.910985] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[  571.911046] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[  571.911104] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[  571.911162] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[  571.911222] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  571.911292] [drm:intel_atomic_commit_tail [i915]] [CRTC:47:pipe B]
>[  571.911346] [drm:intel_power_well_disable [i915]] disabling DC off
>[  571.911397] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  571.911445] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  571.911882] [drm:intel_power_well_disable [i915]] disabling always-on
>[  571.914021] [drm:drm_mode_addfb2 [drm]] [FB:91]
>[  571.915710] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  571.915716] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  571.915738] [drm:intel_atomic_check [i915]] [CONNECTOR:49:eDP-1] checking for sink bpp constrains
>[  571.915752] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  571.915759] [drm:drm_mode_debug_printmodeline [drm]] Modeline 52:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[  571.915773] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 138780KHz
>[  571.915790] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24
>[  571.915802] [drm:intel_dp_compute_config [i915]] DP link bw required 416340 available 540000
>[  571.915814] [drm:intel_dp_compute_config [i915]] PSR disable by flag
>[  571.915827] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  571.915841] [drm:intel_dump_pipe_config [i915]] [CRTC:37:pipe A][modeset]
>[  571.915854] [drm:intel_dump_pipe_config [i915]] output_types: EDP (0x100)
>[  571.915866] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0
>[  571.915879] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 6467616, gmch_n: 8388608, link_m: 269484, link_n: 524288, tu: 64
>[  571.915891] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  571.915902] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  571.915908] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[  571.915920] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  571.915925] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[  571.915937] [drm:intel_dump_pipe_config [i915]] crtc timings: 138780 1920 1966 1996 2080 1080 1082 1086 1112, type: 0x48 flags: 0xa
>[  571.915949] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 138780
>[  571.915960] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  571.915972] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  571.915983] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  571.915999] [drm:intel_dump_pipe_config [i915]] dpll_hw_state: ctrl1: 0x3, cfgcr1: 0x0, cfgcr2: 0x0
>[  571.916010] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  571.916021] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 1A] disabled, scaler_id = -1
>[  571.916032] [drm:intel_dump_pipe_config [i915]] [PLANE:31:plane 2A] disabled, scaler_id = -1
>[  571.916043] [drm:intel_dump_pipe_config [i915]] [PLANE:34:cursor A] disabled, scaler_id = -1
>[  571.916058] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  571.916073] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[  571.916089] [drm:intel_find_shared_dpll [i915]] [CRTC:37:pipe A] allocated DPLL 0
>[  571.916103] [drm:intel_reference_shared_dpll [i915]] using DPLL 0 for pipe A
>[  571.916641] [drm:intel_power_well_enable [i915]] enabling always-on
>[  571.916651] [drm:intel_power_well_enable [i915]] enabling DC off
>[  571.916905] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  571.916922] [drm:intel_atomic_commit_tail [i915]] [ENCODER:48:DDI A]
>[  571.916935] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI B]
>[  571.916947] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  571.916959] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  571.916970] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DDI C]
>[  571.916981] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST A]
>[  571.916993] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST B]
>[  571.917004] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI D]
>[  571.917014] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[  571.917025] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[  571.917038] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[  571.917050] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[  571.917062] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[  571.917073] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[  571.917087] [drm:intel_enable_shared_dpll [i915]] enable DPLL 0 (active 1, on? 0) for crtc 37
>[  571.917100] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 0
>[  571.917120] [drm:edp_panel_on [i915]] Turn eDP port A panel power on
>[  571.917146] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle
>[  572.508488] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 00000000 control 00000060
>[  572.508580] [drm:wait_panel_status [i915]] Wait complete
>[  572.508689] [drm:edp_panel_on [i915]] Wait for panel power on
>[  572.508819] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 00000063
>[  572.542189] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010
>[  572.542270] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  572.542345] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1
>[  572.542489] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  572.711210] [drm:wait_panel_status [i915]] Wait complete
>[  572.711275] [drm:intel_power_well_enable [i915]] enabling DDI A/E IO power well
>[  572.711378] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[  572.711530] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b
>[  572.712732] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  572.712795] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  572.712854] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  572.712914] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  572.713627] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  572.713686] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  572.714647] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  572.714673] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:49:eDP-1] Link Training Passed at Link Rate = 270000, Lane count = 2
>[  572.715051] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  572.715086] [drm:intel_edp_backlight_on [i915]] 
>[  572.715098] [drm:intel_panel_enable_backlight [i915]] pipe A
>[  572.715135] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 120000
>[  572.720135] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS
>[  575.964328] [drm:edp_panel_vdd_off_sync [i915]] Turning eDP port A VDD off
>[  575.964469] [drm:edp_panel_vdd_off_sync [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x00000067
>[  582.876263] [drm:drm_atomic_helper_wait_for_flip_done [drm_kms_helper]] *ERROR* [CRTC:37:pipe A] flip_done timed out
>[  582.876381] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:49:eDP-1]
>[  582.876466] [drm:intel_atomic_commit_tail [i915]] [CRTC:37:pipe A]
>[  582.876561] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[  582.876625] [drm:intel_power_well_disable [i915]] disabling DC off
>[  582.876680] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  582.876733] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  582.915295] [drm:intel_power_well_enable [i915]] enabling DC off
>[  582.915355] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  582.915453] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[  582.915604] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006f
>[  583.115345] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped
>[  583.115430] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  583.115525] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  583.115587] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[  586.204318] [drm:edp_panel_vdd_off_sync [i915]] Turning eDP port A VDD off
>[  586.204463] [drm:edp_panel_vdd_off_sync [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x00000067
>[  586.204520] [drm:intel_power_well_disable [i915]] disabling DC off
>[  586.204577] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  586.204630] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  592.636564] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[  592.636646] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[  592.636771] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[  592.636837] [drm:intel_power_well_enable [i915]] enabling DC off
>[  592.636901] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  592.636961] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  592.905756] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[  592.905837] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[  593.116102] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [CRTC:37:pipe A] flip_done timed out
>[  597.666653] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[  597.666734] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[  597.949716] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[  597.949799] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[  603.356349] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [CONNECTOR:49:eDP-1] flip_done timed out
>[  603.523414] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[  603.523496] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[  603.806162] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[  603.806243] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[  609.379802] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[  609.379884] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[  609.648955] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[  609.649038] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[  613.596346] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [PLANE:28:plane 1A] flip_done timed out
>[  613.596452] [drm:intel_edp_backlight_off [i915]] 
>[  613.804401] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0
>[  613.804536] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  613.815530] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[  613.815690] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b
>[  613.815962] [drm:intel_edp_panel_off.part.31 [i915]] Turn eDP port A panel power off
>[  613.816101] [drm:intel_edp_panel_off.part.31 [i915]] Wait for panel power off time
>[  613.816238] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000003 control 00000060
>[  613.866439] [drm:wait_panel_status [i915]] Wait complete
>[  613.866502] [drm:intel_power_well_disable [i915]] disabling DDI A/E IO power well
>[  613.866587] [drm:intel_disable_shared_dpll [i915]] disable DPLL 0 (active 1, on? 1) for crtc 37
>[  613.866660] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 0
>[  613.866752] [drm:intel_atomic_commit_tail [i915]] [ENCODER:48:DDI A]
>[  613.866822] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI B]
>[  613.866886] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  613.866949] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  613.867011] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DDI C]
>[  613.867072] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST A]
>[  613.867132] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST B]
>[  613.867192] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI D]
>[  613.867252] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[  613.867311] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[  613.867376] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:49:eDP-1]
>[  613.867443] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[  613.867507] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[  613.867569] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[  613.867630] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[  613.867706] [drm:intel_atomic_commit_tail [i915]] [CRTC:37:pipe A]
>[  613.867810] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  613.868289] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 00 00 04 00 0f 00 04
>[  613.875783] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010
>[  613.875800] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  613.875815] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0
>[  613.896929] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  613.896948] [drm:intel_power_well_disable [i915]] disabling DC off
>[  613.896963] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  613.896977] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  613.896993] [drm:intel_power_well_disable [i915]] disabling always-on
>[  613.897014] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  613.897034] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[  613.897048] [drm:intel_power_well_enable [i915]] enabling always-on
>[  613.897061] [drm:intel_power_well_enable [i915]] enabling DC off
>[  613.897380] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  613.897396] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  613.897805] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 00 00 04 00 0f 00 04
>[  613.898458] [drm:drm_mode_addfb2 [drm]] [FB:91]
>[  613.899076] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  613.899092] [drm:intel_power_well_disable [i915]] disabling DC off
>[  613.899106] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  613.899120] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  613.899135] [drm:intel_power_well_disable [i915]] disabling always-on
>[  613.899741] [drm:drm_mode_addfb2 [drm]] [FB:102]
>[  613.901293] [drm:drm_mode_addfb2 [drm]] [FB:103]
>[  613.902360] [drm:drm_mode_addfb2 [drm]] [FB:104]
>[  613.972429] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  613.972437] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  613.972463] [drm:intel_atomic_check [i915]] [CONNECTOR:49:eDP-1] checking for sink bpp constrains
>[  613.972476] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  613.972483] [drm:drm_mode_debug_printmodeline [drm]] Modeline 52:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[  613.972497] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 138780KHz
>[  613.972513] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24
>[  613.972524] [drm:intel_dp_compute_config [i915]] DP link bw required 416340 available 540000
>[  613.972536] [drm:intel_dp_compute_config [i915]] PSR disable by flag
>[  613.972549] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  613.972562] [drm:intel_dump_pipe_config [i915]] [CRTC:37:pipe A][modeset]
>[  613.972574] [drm:intel_dump_pipe_config [i915]] output_types: EDP (0x100)
>[  613.972585] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0
>[  613.972597] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 6467616, gmch_n: 8388608, link_m: 269484, link_n: 524288, tu: 64
>[  613.972608] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  613.972619] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  613.972624] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[  613.972635] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  613.972641] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[  613.972652] [drm:intel_dump_pipe_config [i915]] crtc timings: 138780 1920 1966 1996 2080 1080 1082 1086 1112, type: 0x48 flags: 0xa
>[  613.972663] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 138780
>[  613.972674] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  613.972684] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  613.972695] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  613.972705] [drm:intel_dump_pipe_config [i915]] dpll_hw_state: ctrl1: 0x3, cfgcr1: 0x0, cfgcr2: 0x0
>[  613.972716] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  613.972726] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 1A] disabled, scaler_id = -1
>[  613.972736] [drm:intel_dump_pipe_config [i915]] [PLANE:31:plane 2A] disabled, scaler_id = -1
>[  613.972746] [drm:intel_dump_pipe_config [i915]] [PLANE:34:cursor A] disabled, scaler_id = -1
>[  613.972759] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  613.972771] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[  613.972785] [drm:intel_find_shared_dpll [i915]] [CRTC:37:pipe A] allocated DPLL 0
>[  613.972797] [drm:intel_reference_shared_dpll [i915]] using DPLL 0 for pipe A
>[  613.973756] [drm:intel_power_well_enable [i915]] enabling always-on
>[  613.973765] [drm:intel_power_well_enable [i915]] enabling DC off
>[  613.974060] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  613.974079] [drm:intel_atomic_commit_tail [i915]] [ENCODER:48:DDI A]
>[  613.974093] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI B]
>[  613.974106] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  613.974118] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  613.974131] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DDI C]
>[  613.974143] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST A]
>[  613.974156] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST B]
>[  613.974168] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI D]
>[  613.974180] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[  613.974191] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[  613.974204] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[  613.974218] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[  613.974230] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[  613.974242] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[  613.974256] [drm:intel_enable_shared_dpll [i915]] enable DPLL 0 (active 1, on? 0) for crtc 37
>[  613.974286] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 0
>[  613.974305] [drm:edp_panel_on [i915]] Turn eDP port A panel power on
>[  613.974329] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle
>[  614.492232] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 00000000 control 00000060
>[  614.492331] [drm:wait_panel_status [i915]] Wait complete
>[  614.492462] [drm:edp_panel_on [i915]] Wait for panel power on
>[  614.492590] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 00000063
>[  614.526204] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010
>[  614.526276] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  614.526341] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1
>[  614.526444] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  614.695367] [drm:wait_panel_status [i915]] Wait complete
>[  614.695434] [drm:intel_power_well_enable [i915]] enabling DDI A/E IO power well
>[  614.695538] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[  614.695686] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b
>[  614.696923] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  614.696995] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  614.697060] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  614.697125] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  614.697837] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  614.697897] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  614.698907] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  614.698970] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:49:eDP-1] Link Training Passed at Link Rate = 270000, Lane count = 2
>[  614.699630] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  614.699695] [drm:intel_edp_backlight_on [i915]] 
>[  614.699751] [drm:intel_panel_enable_backlight [i915]] pipe A
>[  614.699833] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 120000
>[  614.704171] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS
>[  615.204296] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[  615.204377] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[  615.204494] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[  615.204558] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  615.463560] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[  615.463642] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[  617.948430] [drm:edp_panel_vdd_off_sync [i915]] Turning eDP port A VDD off
>[  617.948575] [drm:edp_panel_vdd_off_sync [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x00000067
>[  621.037715] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[  621.037797] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[  621.298719] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[  621.298801] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[  624.860247] [drm:drm_atomic_helper_wait_for_flip_done [drm_kms_helper]] *ERROR* [CRTC:37:pipe A] flip_done timed out
>[  624.860369] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:49:eDP-1]
>[  624.860451] [drm:intel_atomic_commit_tail [i915]] [CRTC:37:pipe A]
>[  624.860548] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[  624.861127] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 00 00 04 00 0f 00 04
>[  624.862523] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  624.862574] [drm:intel_power_well_disable [i915]] disabling DC off
>[  624.862619] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  624.862663] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  624.862728] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[  624.862771] [drm:intel_power_well_enable [i915]] enabling DC off
>[  624.862812] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  624.862859] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  624.863330] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 00 00 04 00 0f 00 04
>[  624.864767] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  624.864820] [drm:intel_power_well_disable [i915]] disabling DC off
>[  624.864870] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  624.864919] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  624.899647] [drm:intel_power_well_enable [i915]] enabling DC off
>[  624.899700] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  624.899788] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[  624.899935] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006f
>[  625.099915] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped
>[  625.099958] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  625.099987] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  626.873821] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[  626.873902] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[  626.874023] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[  626.874090] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  627.134485] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[  627.134566] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[  628.188315] [drm:edp_panel_vdd_off_sync [i915]] Turning eDP port A VDD off
>[  628.188459] [drm:edp_panel_vdd_off_sync [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x00000067
>[  632.702889] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[  632.702971] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[  632.963441] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[  632.963522] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[  635.356397] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [CRTC:37:pipe A] flip_done timed out
>[  638.536901] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[  638.536982] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[  638.796675] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[  638.796757] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[  644.373167] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[  644.373248] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[  644.633366] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[  644.633447] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[  645.596246] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [CONNECTOR:49:eDP-1] flip_done timed out
>[  650.202672] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[  650.202754] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[  650.460936] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[  650.461018] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[  655.836237] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [PLANE:28:plane 1A] flip_done timed out
>[  656.033613] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[  656.033694] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[  656.294749] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[  656.294830] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[  661.865940] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[  661.866021] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[  662.127111] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[  662.127192] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[  666.076251] [drm:drm_atomic_helper_wait_for_flip_done [drm_kms_helper]] *ERROR* [CRTC:37:pipe A] flip_done timed out
>[  666.076845] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 00 00 04 00 0f 00 04
>[  666.078251] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  666.078307] [drm:intel_power_well_disable [i915]] disabling DC off
>[  666.078375] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  666.078419] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  666.078487] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[  666.078530] [drm:intel_power_well_enable [i915]] enabling DC off
>[  666.078572] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  666.078619] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  666.079093] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 00 00 04 00 0f 00 04
>[  666.080497] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  666.080544] [drm:intel_power_well_disable [i915]] disabling DC off
>[  666.080588] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  666.080632] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  666.115782] [drm:intel_power_well_enable [i915]] enabling DC off
>[  666.115835] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  666.115922] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[  666.116108] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006f
>[  666.315882] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped
>[  666.315932] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  666.315963] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  667.699069] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[  667.699151] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[  667.699269] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[  667.699335] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  667.957738] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[  667.957819] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[  669.404323] [drm:edp_panel_vdd_off_sync [i915]] Turning eDP port A VDD off
>[  669.404469] [drm:edp_panel_vdd_off_sync [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x00000067
>[  673.536536] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[  673.536616] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[  673.794988] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[  673.795069] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[  676.572345] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [CRTC:37:pipe A] flip_done timed out
>[  679.363287] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[  679.363368] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[  679.625408] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[  679.625467] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[  685.194742] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[  685.194823] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[  685.455176] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[  685.455256] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[  686.812231] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [CONNECTOR:49:eDP-1] flip_done timed out
>[  691.022835] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[  691.022916] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[  691.282096] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[  691.282178] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[  696.851994] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[  696.852075] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[  697.052227] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [PLANE:28:plane 1A] flip_done timed out
>[  697.113081] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[  697.113162] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[  702.688360] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[  702.688441] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[  702.949540] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[  702.949621] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[  707.292227] [drm:drm_atomic_helper_wait_for_flip_done [drm_kms_helper]] *ERROR* [CRTC:37:pipe A] flip_done timed out
>[  707.292829] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 00 00 04 00 0f 00 04
>[  707.294234] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  707.294291] [drm:intel_power_well_disable [i915]] disabling DC off
>[  707.294342] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  707.294407] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  707.294474] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[  707.294517] [drm:intel_power_well_enable [i915]] enabling DC off
>[  707.294559] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  707.294605] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  707.295078] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 00 00 04 00 0f 00 04
>[  707.296482] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  707.296529] [drm:intel_power_well_disable [i915]] disabling DC off
>[  707.296573] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  707.296617] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  707.331755] [drm:intel_power_well_enable [i915]] enabling DC off
>[  707.331810] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  707.331898] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[  707.332085] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006f
>[  707.531829] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped
>[  707.531879] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  707.531910] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  708.513771] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[  708.513852] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[  708.513974] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[  708.514041] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  708.775167] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[  708.775249] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[  710.620322] [drm:edp_panel_vdd_off_sync [i915]] Turning eDP port A VDD off
>[  710.620472] [drm:edp_panel_vdd_off_sync [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x00000067
>[  714.346464] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[  714.346546] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[  714.607681] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[  714.607763] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[  717.788343] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [CRTC:37:pipe A] flip_done timed out
>[  720.174687] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[  720.174768] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[  720.436551] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[  720.436632] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[  726.011283] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[  726.011356] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[  726.272513] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[  726.272594] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[  728.028244] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [CONNECTOR:49:eDP-1] flip_done timed out
>[  731.840920] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[  731.841001] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[  732.100528] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[  732.100610] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[  737.664114] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[  737.664196] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[  737.925103] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[  737.925183] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[  738.268229] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [PLANE:28:plane 1A] flip_done timed out
>[  743.492705] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[  743.492787] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[  743.753665] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[  743.753746] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[  748.508241] [drm:drm_atomic_helper_wait_for_flip_done [drm_kms_helper]] *ERROR* [CRTC:37:pipe A] flip_done timed out
>[  748.508833] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 00 00 04 00 0f 00 04
>[  748.510240] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  748.510297] [drm:intel_power_well_disable [i915]] disabling DC off
>[  748.510348] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  748.510396] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  748.510472] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[  748.510520] [drm:intel_power_well_enable [i915]] enabling DC off
>[  748.510568] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  748.510619] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  748.511104] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 00 00 04 00 0f 00 04
>[  748.512539] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  748.512591] [drm:intel_power_well_disable [i915]] disabling DC off
>[  748.512641] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  748.512690] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  748.547513] [drm:intel_power_well_enable [i915]] enabling DC off
>[  748.547565] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  748.547652] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[  748.547795] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006f
>[  748.747769] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped
>[  748.747874] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  748.747962] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  748.748023] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[  749.322549] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[  749.322630] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[  749.322754] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[  749.322821] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  749.585394] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[  749.585475] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[  751.836309] [drm:edp_panel_vdd_off_sync [i915]] Turning eDP port A VDD off
>[  751.836455] [drm:edp_panel_vdd_off_sync [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x00000067
>[  755.157054] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[  755.157135] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[  755.416400] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[  755.416481] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[  759.004342] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [CRTC:37:pipe A] flip_done timed out
>[  760.988408] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[  760.988490] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[  761.251465] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[  761.251546] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[  766.818434] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[  766.818515] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[  767.080636] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[  767.080717] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[  769.244243] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [CONNECTOR:49:eDP-1] flip_done timed out
>[  772.654372] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[  772.654454] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[  772.917073] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[  772.917156] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[  778.488324] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[  778.488405] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[  778.747994] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[  778.748075] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[  779.484224] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [PLANE:28:plane 1A] flip_done timed out
>[  779.484329] [drm:intel_edp_backlight_off [i915]] 
>[  779.692308] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0
>[  779.692445] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  779.697910] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[  779.698068] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b
>[  779.698343] [drm:intel_edp_panel_off.part.31 [i915]] Turn eDP port A panel power off
>[  779.698444] [drm:intel_edp_panel_off.part.31 [i915]] Wait for panel power off time
>[  779.698570] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000003 control 00000060
>[  779.748815] [drm:wait_panel_status [i915]] Wait complete
>[  779.748878] [drm:intel_power_well_disable [i915]] disabling DDI A/E IO power well
>[  779.748965] [drm:intel_disable_shared_dpll [i915]] disable DPLL 0 (active 1, on? 1) for crtc 37
>[  779.749040] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 0
>[  779.749133] [drm:intel_atomic_commit_tail [i915]] [ENCODER:48:DDI A]
>[  779.749206] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI B]
>[  779.749272] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  779.749337] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  779.749400] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DDI C]
>[  779.749462] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST A]
>[  779.749522] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST B]
>[  779.749583] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI D]
>[  779.749643] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[  779.749701] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[  779.749766] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:49:eDP-1]
>[  779.749831] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[  779.749896] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[  779.749958] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[  779.750019] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[  779.750096] [drm:intel_atomic_commit_tail [i915]] [CRTC:37:pipe A]
>[  779.750218] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  779.750688] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 00 00 04 00 0f 00 04
>[  779.752125] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  779.752180] [drm:intel_power_well_disable [i915]] disabling DC off
>[  779.752229] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  779.752274] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  779.752281] Setting dangerous option enable_psr - tainting kernel
>[  779.753209] [drm:intel_power_well_disable [i915]] disabling always-on
>[  779.753290] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[  779.753333] [drm:intel_power_well_enable [i915]] enabling always-on
>[  779.753361] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  779.753403] [drm:intel_power_well_enable [i915]] enabling DC off
>[  779.753424] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  779.753521] [drm:intel_atomic_check [i915]] [CONNECTOR:49:eDP-1] checking for sink bpp constrains
>[  779.753588] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  779.753618] [drm:drm_mode_debug_printmodeline [drm]] Modeline 52:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[  779.753683] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 138780KHz
>[  779.753724] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  779.753769] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  779.753830] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24
>[  779.753887] [drm:intel_dp_compute_config [i915]] DP link bw required 416340 available 540000
>[  779.753952] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  779.754029] [drm:intel_dump_pipe_config [i915]] [CRTC:37:pipe A][modeset]
>[  779.754087] [drm:intel_dump_pipe_config [i915]] output_types: EDP (0x100)
>[  779.754142] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0
>[  779.754196] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 6467616, gmch_n: 8388608, link_m: 269484, link_n: 524288, tu: 64
>[  779.754247] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  779.754298] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  779.754324] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[  779.754376] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  779.754401] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[  779.754455] [drm:intel_dump_pipe_config [i915]] crtc timings: 138780 1920 1966 1996 2080 1080 1082 1086 1112, type: 0x48 flags: 0xa
>[  779.754506] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 138780
>[  779.754556] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  779.754606] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  779.754655] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  779.754704] [drm:intel_dump_pipe_config [i915]] dpll_hw_state: ctrl1: 0x3, cfgcr1: 0x0, cfgcr2: 0x0
>[  779.754760] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  779.754809] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 1A] disabled, scaler_id = -1
>[  779.754858] [drm:intel_dump_pipe_config [i915]] [PLANE:31:plane 2A] disabled, scaler_id = -1
>[  779.754906] [drm:intel_dump_pipe_config [i915]] [PLANE:34:cursor A] disabled, scaler_id = -1
>[  779.754967] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  779.755022] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[  779.755087] [drm:intel_find_shared_dpll [i915]] [CRTC:37:pipe A] allocated DPLL 0
>[  779.755143] [drm:intel_reference_shared_dpll [i915]] using DPLL 0 for pipe A
>[  779.756313] [drm:intel_atomic_commit_tail [i915]] [ENCODER:48:DDI A]
>[  779.756382] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI B]
>[  779.756447] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  779.756506] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  779.756565] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DDI C]
>[  779.756621] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST A]
>[  779.756678] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST B]
>[  779.756732] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI D]
>[  779.756787] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[  779.756841] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[  779.756901] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[  779.756965] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[  779.757023] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[  779.757080] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[  779.757147] [drm:intel_enable_shared_dpll [i915]] enable DPLL 0 (active 1, on? 0) for crtc 37
>[  779.757207] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 0
>[  779.757288] [drm:edp_panel_on [i915]] Turn eDP port A panel power on
>[  779.757364] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle
>[  779.758065] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010
>[  779.758128] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  779.758188] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0
>[  780.380591] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 00000000 control 00000060
>[  780.380689] [drm:wait_panel_status [i915]] Wait complete
>[  780.380820] [drm:edp_panel_on [i915]] Wait for panel power on
>[  780.380945] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 00000063
>[  780.415064] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010
>[  780.415136] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  780.415202] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1
>[  780.582801] [drm:wait_panel_status [i915]] Wait complete
>[  780.582866] [drm:intel_power_well_enable [i915]] enabling DDI A/E IO power well
>[  780.582968] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[  780.583121] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b
>[  780.584345] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  780.584410] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  780.584470] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  780.584527] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  780.585262] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  780.585320] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  780.586331] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  780.586392] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:49:eDP-1] Link Training Passed at Link Rate = 270000, Lane count = 2
>[  780.587047] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  780.587125] [drm:intel_edp_backlight_on [i915]] 
>[  780.587189] [drm:intel_panel_enable_backlight [i915]] pipe A
>[  780.587277] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 120000
>[  780.592375] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS
>[  783.836388] [drm:edp_panel_vdd_off_sync [i915]] Turning eDP port A VDD off
>[  783.836533] [drm:edp_panel_vdd_off_sync [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x00000067
>[  784.319944] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[  784.320025] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[  784.580747] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[  784.580829] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[  790.154057] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[  790.154139] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[  790.411411] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[  790.411492] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[  790.748240] [drm:drm_atomic_helper_wait_for_flip_done [drm_kms_helper]] *ERROR* [CRTC:37:pipe A] flip_done timed out
>[  790.748363] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:49:eDP-1]
>[  790.748447] [drm:intel_atomic_commit_tail [i915]] [CRTC:37:pipe A]
>[  790.748545] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[  790.749132] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 00 00 04 00 0f 00 04
>[  790.750534] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  790.750590] [drm:intel_power_well_disable [i915]] disabling DC off
>[  790.750641] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  790.750689] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  790.750762] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  790.750825] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[  790.750874] [drm:intel_power_well_enable [i915]] enabling DC off
>[  790.750922] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  790.750973] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  790.751446] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 00 00 04 00 0f 00 04
>[  790.752837] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  790.752884] [drm:intel_power_well_disable [i915]] disabling DC off
>[  790.752928] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  790.752974] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  790.787042] [drm:intel_power_well_enable [i915]] enabling DC off
>[  790.787095] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  790.787181] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[  790.787325] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006f
>[  790.987351] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped
>[  791.237355] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped
>[  791.487331] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped
>[  791.737338] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped
>[  791.987331] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped
>[  795.100319] [drm:edp_panel_vdd_off_sync [i915]] Turning eDP port A VDD off
>[  795.100465] [drm:edp_panel_vdd_off_sync [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x00000067
>[  795.100522] [drm:intel_power_well_disable [i915]] disabling DC off
>[  795.100580] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  795.100633] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  795.985325] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[  795.985406] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[  795.985530] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[  795.985597] [drm:intel_power_well_enable [i915]] enabling DC off
>[  795.985662] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  795.985721] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  796.245703] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[  796.245785] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[  801.816269] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[  801.816351] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[  802.012240] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [CRTC:37:pipe A] flip_done timed out
>[  802.079813] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[  802.079895] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[  807.650216] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[  807.650297] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[  807.910223] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[  807.910305] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[  812.252344] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [PLANE:28:plane 1A] flip_done timed out
>[  813.471095] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[  813.471177] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[  813.730656] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[  813.730736] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[  819.300829] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[  819.300911] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[  819.561091] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[  819.561172] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[  822.492086] [drm:drm_atomic_helper_wait_for_flip_done [drm_kms_helper]] *ERROR* [CRTC:37:pipe A] flip_done timed out
>[  822.492364] [IGT] kms_frontbuffer_tracking: exiting, ret=0
>[  822.492433] Setting dangerous option enable_psr - tainting kernel
>[  822.492449] Setting dangerous option enable_fbc - tainting kernel
>[  822.492695] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 00 00 04 00 0f 00 04
>[  822.494221] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  822.494278] [drm:intel_power_well_disable [i915]] disabling DC off
>[  822.494330] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  822.494379] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  822.494454] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[  822.494502] [drm:intel_power_well_enable [i915]] enabling DC off
>[  822.494550] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  822.494601] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  822.495084] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 00 00 04 00 0f 00 04
>[  822.496505] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  822.496557] [drm:intel_power_well_disable [i915]] disabling DC off
>[  822.496606] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  822.496655] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  822.536266] [drm:intel_atomic_check [i915]] [CONNECTOR:57:DP-1] checking for sink bpp constrains
>[  822.536280] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  822.536296] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 148500KHz
>[  822.536310] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[  822.536323] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 648000
>[  822.536337] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  822.536351] [drm:intel_dump_pipe_config [i915]] [CRTC:47:pipe B][modeset]
>[  822.536363] [drm:intel_dump_pipe_config [i915]] output_types: DP (0x80)
>[  822.536375] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[  822.536386] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5767168, gmch_n: 8388608, link_m: 240298, link_n: 262144, tu: 64
>[  822.536397] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  822.536408] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  822.536415] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  822.536426] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  822.536431] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[  822.536443] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[  822.536454] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1080, pixel rate 148500
>[  822.536464] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  822.536475] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  822.536485] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  822.536496] [drm:intel_dump_pipe_config [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[  822.536506] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  822.536516] [drm:intel_dump_pipe_config [i915]] [PLANE:38:plane 1B] disabled, scaler_id = -1
>[  822.536527] [drm:intel_dump_pipe_config [i915]] [PLANE:41:plane 2B] disabled, scaler_id = -1
>[  822.536537] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor B] disabled, scaler_id = -1
>[  822.536549] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  822.536561] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[  822.536576] [drm:intel_find_shared_dpll [i915]] [CRTC:47:pipe B] allocated DPLL 1
>[  822.536588] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[  825.131855] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[  825.131935] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[  825.132061] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[  825.132138] [drm:intel_power_well_enable [i915]] enabling DC off
>[  825.132222] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  825.132279] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  825.392641] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[  825.392722] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[  830.962344] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[  830.962426] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[  831.224634] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[  831.224716] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[  832.732330] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [CRTC:37:pipe A] flip_done timed out
>[  836.795864] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[  836.795946] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[  837.054987] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[  837.055069] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[  842.630846] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[  842.630927] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[  842.891914] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[  842.891994] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[  842.972214] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [CONNECTOR:49:eDP-1] flip_done timed out
>[  848.464238] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[  848.464318] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[  848.724086] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[  848.724167] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[  853.212298] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [PLANE:28:plane 1A] flip_done timed out
>[  853.212392] [drm:intel_disable_sagv [i915]] Disabling the SAGV
>[  853.212478] [drm:intel_atomic_commit_tail [i915]] [ENCODER:48:DDI A]
>[  853.212552] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI B]
>[  853.212623] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  853.212689] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  853.212752] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DDI C]
>[  853.212814] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST A]
>[  853.212874] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST B]
>[  853.212934] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI D]
>[  853.212994] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[  853.213052] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[  853.213118] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[  853.213186] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[  853.213250] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[  853.213313] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[  853.213389] [drm:intel_fbc_enable [i915]] reserved 16588800 bytes of contiguous stolen space for FBC, threshold: 1
>[  853.213457] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[  853.219452] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 2, on? 0) for crtc 47
>[  853.219529] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[  853.219645] [drm:intel_power_well_enable [i915]] enabling DDI B IO power well
>[  853.220265] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  853.221522] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  853.222780] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  853.224051] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  853.225329] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[  853.226208] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[  853.227204] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  853.227272] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  853.227335] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  853.227397] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  853.246066] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  853.246094] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[  853.264823] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  853.265146] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:57:DP-1] Link Training Passed at Link Rate = 162000, Lane count = 4
>[  853.265515] [drm:intel_enable_pipe [i915]] enabling pipe B
>[  853.265546] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS
>[  854.291004] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[  854.291086] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[  854.549694] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[  854.549775] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[  863.452361] [drm:drm_atomic_helper_wait_for_flip_done [drm_kms_helper]] *ERROR* [CRTC:37:pipe A] flip_done timed out
>[  863.452496] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:57:DP-1]
>[  863.452582] [drm:intel_atomic_commit_tail [i915]] [CRTC:47:pipe B]
>[  863.452682] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[  863.453279] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 00 00 04 00 0f 00 04
>[  863.454722] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[  863.455189] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 00 00 04 00 0f 00 04
>[  863.497543] [IGT] kms_frontbuffer_tracking: executing
>[  863.554240] [drm:drm_mode_addfb2 [drm]] [FB:75]
>[  863.554281] [drm:drm_mode_addfb2 [drm]] [FB:91]
>[  863.554320] [drm:drm_mode_addfb2 [drm]] [FB:92]
>[  863.555103] [drm:drm_mode_addfb2 [drm]] [FB:93]
>[  863.562569] [drm:drm_mode_addfb2 [drm]] [FB:94]
>[  863.564434] [drm:drm_mode_addfb2 [drm]] [FB:96]
>[  863.564472] [drm:drm_mode_addfb2 [drm]] [FB:98]
>[  863.564517] [drm:drm_mode_addfb2 [drm]] [FB:102]
>[  863.564761] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  863.564774] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  873.692335] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [CRTC:37:pipe A] flip_done timed out
>[  883.932347] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [CONNECTOR:49:eDP-1] flip_done timed out
>[  894.172216] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [PLANE:28:plane 1A] flip_done timed out
>[  904.416003] [drm:drm_atomic_helper_wait_for_flip_done [drm_kms_helper]] *ERROR* [CRTC:37:pipe A] flip_done timed out
>[  904.416172] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[  904.416343] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006f
>[  904.602040] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped
>[  904.602274] [IGT] kms_frontbuffer_tracking: starting subtest psr-1p-offscren-pri-indfb-draw-mmap-cpu
>[  904.602351] Setting dangerous option enable_fbc - tainting kernel
>[  904.602374] Setting dangerous option enable_psr - tainting kernel
>[  907.740311] [drm:edp_panel_vdd_off_sync [i915]] Turning eDP port A VDD off
>[  907.740458] [drm:edp_panel_vdd_off_sync [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x00000067
>[  914.652058] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [CRTC:37:pipe A] flip_done timed out
>[  924.892334] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [PLANE:28:plane 1A] flip_done timed out
>[  935.132210] [drm:drm_atomic_helper_wait_for_flip_done [drm_kms_helper]] *ERROR* [CRTC:37:pipe A] flip_done timed out
>[  935.136612] [drm:drm_mode_addfb2 [drm]] [FB:72]
>[  935.136714] [drm:drm_mode_addfb2 [drm]] [FB:75]
>[  935.136817] [drm:drm_mode_addfb2 [drm]] [FB:91]
>[  935.138250] [drm:drm_mode_addfb2 [drm]] [FB:92]
>[  935.141989] [drm:drm_mode_addfb2 [drm]] [FB:93]
>[  935.142832] [drm:drm_mode_addfb2 [drm]] [FB:94]
>[  935.142851] [drm:drm_mode_addfb2 [drm]] [FB:96]
>[  935.142871] [drm:drm_mode_addfb2 [drm]] [FB:98]
>[  935.142975] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  935.143008] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  935.143022] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[  945.372314] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [CRTC:37:pipe A] flip_done timed out
>[  955.612213] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [CONNECTOR:49:eDP-1] flip_done timed out
>[  965.852178] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [PLANE:28:plane 1A] flip_done timed out
>[  965.852304] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[  965.852459] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006f
>[  965.852733] [drm:intel_edp_backlight_off [i915]] 
>[  966.060384] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0
>[  966.060522] [drm:intel_disable_pipe [i915]] disabling pipe A
>[  966.069194] [drm:intel_edp_panel_off.part.31 [i915]] Turn eDP port A panel power off
>[  966.069308] [drm:intel_edp_panel_off.part.31 [i915]] Wait for panel power off time
>[  966.069441] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000003 control 00000060
>[  966.121984] [drm:wait_panel_status [i915]] Wait complete
>[  966.122047] [drm:intel_power_well_disable [i915]] disabling DDI A/E IO power well
>[  966.122130] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[  966.122209] [drm:intel_disable_shared_dpll [i915]] disable DPLL 0 (active 1, on? 1) for crtc 37
>[  966.122280] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 0
>[  966.122372] [drm:intel_atomic_commit_tail [i915]] [ENCODER:48:DDI A]
>[  966.122443] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI B]
>[  966.122511] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  966.122575] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  966.122637] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DDI C]
>[  966.122698] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST A]
>[  966.122759] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST B]
>[  966.122820] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI D]
>[  966.122880] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[  966.122939] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[  966.123005] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:49:eDP-1]
>[  966.123072] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[  966.123137] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[  966.123200] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[  966.123261] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[  966.129130] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010
>[  966.129211] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  966.129286] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0
>[  966.129404] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  966.132755] [drm:intel_atomic_commit_tail [i915]] [CRTC:37:pipe A]
>[  966.132826] [drm:intel_enable_sagv [i915]] Enabling the SAGV
>[  966.132922] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[  966.133020] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  966.133093] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[  966.133196] [drm:intel_disable_pipe [i915]] disabling pipe B
>[  966.149988] [drm:intel_power_well_disable [i915]] disabling DDI B IO power well
>[  966.150072] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 2, on? 1) for crtc 47
>[  966.150144] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[  966.150235] [drm:intel_atomic_commit_tail [i915]] [ENCODER:48:DDI A]
>[  966.150300] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI B]
>[  966.150364] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  966.150423] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  966.150482] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DDI C]
>[  966.150539] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST A]
>[  966.150594] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST B]
>[  966.150648] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI D]
>[  966.150702] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[  966.150756] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[  966.150817] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:57:DP-1]
>[  966.150880] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[  966.150940] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[  966.150999] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[  966.151057] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[  966.151117] [drm:intel_power_well_disable [i915]] disabling power well 2
>[  966.151186] [drm:intel_atomic_commit_tail [i915]] [CRTC:47:pipe B]
>[  966.151241] [drm:intel_power_well_disable [i915]] disabling DC off
>[  966.151292] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  966.151340] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  966.151778] [drm:intel_power_well_disable [i915]] disabling always-on
>[  966.154538] [drm:drm_mode_addfb2 [drm]] [FB:73]
>[  966.156254] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  966.156260] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[  966.156282] [drm:intel_atomic_check [i915]] [CONNECTOR:49:eDP-1] checking for sink bpp constrains
>[  966.156295] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[  966.156302] [drm:drm_mode_debug_printmodeline [drm]] Modeline 52:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[  966.156315] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 138780KHz
>[  966.156331] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24
>[  966.156343] [drm:intel_dp_compute_config [i915]] DP link bw required 416340 available 540000
>[  966.156354] [drm:intel_dp_compute_config [i915]] PSR disable by flag
>[  966.156367] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[  966.156379] [drm:intel_dump_pipe_config [i915]] [CRTC:37:pipe A][modeset]
>[  966.156391] [drm:intel_dump_pipe_config [i915]] output_types: EDP (0x100)
>[  966.156403] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0
>[  966.156414] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 6467616, gmch_n: 8388608, link_m: 269484, link_n: 524288, tu: 64
>[  966.156425] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[  966.156436] [drm:intel_dump_pipe_config [i915]] requested mode:
>[  966.156441] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[  966.156452] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[  966.156457] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[  966.156469] [drm:intel_dump_pipe_config [i915]] crtc timings: 138780 1920 1966 1996 2080 1080 1082 1086 1112, type: 0x48 flags: 0xa
>[  966.156480] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 138780
>[  966.156490] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[  966.156501] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[  966.156511] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[  966.156522] [drm:intel_dump_pipe_config [i915]] dpll_hw_state: ctrl1: 0x3, cfgcr1: 0x0, cfgcr2: 0x0
>[  966.156532] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[  966.156542] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 1A] disabled, scaler_id = -1
>[  966.156552] [drm:intel_dump_pipe_config [i915]] [PLANE:31:plane 2A] disabled, scaler_id = -1
>[  966.156563] [drm:intel_dump_pipe_config [i915]] [PLANE:34:cursor A] disabled, scaler_id = -1
>[  966.156575] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  966.156587] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[  966.156601] [drm:intel_find_shared_dpll [i915]] [CRTC:37:pipe A] allocated DPLL 0
>[  966.156612] [drm:intel_reference_shared_dpll [i915]] using DPLL 0 for pipe A
>[  966.157130] [drm:intel_power_well_enable [i915]] enabling always-on
>[  966.157139] [drm:intel_power_well_enable [i915]] enabling DC off
>[  966.157416] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  966.157434] [drm:intel_atomic_commit_tail [i915]] [ENCODER:48:DDI A]
>[  966.157448] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI B]
>[  966.157461] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[  966.157473] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[  966.157485] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DDI C]
>[  966.157498] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST A]
>[  966.157510] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST B]
>[  966.157522] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI D]
>[  966.157533] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[  966.157545] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[  966.157558] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[  966.157571] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[  966.157582] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[  966.157594] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[  966.157609] [drm:intel_enable_shared_dpll [i915]] enable DPLL 0 (active 1, on? 0) for crtc 37
>[  966.157621] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 0
>[  966.157640] [drm:edp_panel_on [i915]] Turn eDP port A panel power on
>[  966.157681] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle
>[  966.748529] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 00000000 control 00000060
>[  966.748636] [drm:wait_panel_status [i915]] Wait complete
>[  966.748774] [drm:edp_panel_on [i915]] Wait for panel power on
>[  966.748903] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 00000063
>[  966.782576] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010
>[  966.782657] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[  966.782732] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1
>[  966.782874] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[  966.949433] [drm:wait_panel_status [i915]] Wait complete
>[  966.949499] [drm:intel_power_well_enable [i915]] enabling DDI A/E IO power well
>[  966.949602] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[  966.949755] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b
>[  966.950956] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[  966.951018] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[  966.951077] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[  966.951137] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[  966.951850] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[  966.951908] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[  966.952981] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[  966.953056] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:49:eDP-1] Link Training Passed at Link Rate = 270000, Lane count = 2
>[  966.953716] [drm:intel_enable_pipe [i915]] enabling pipe A
>[  966.953812] [drm:intel_edp_backlight_on [i915]] 
>[  966.953877] [drm:intel_panel_enable_backlight [i915]] pipe A
>[  966.953969] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 120000
>[  966.960178] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS
>[  970.204141] [drm:edp_panel_vdd_off_sync [i915]] Turning eDP port A VDD off
>[  970.204285] [drm:edp_panel_vdd_off_sync [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x00000067
>[  977.116216] [drm:drm_atomic_helper_wait_for_flip_done [drm_kms_helper]] *ERROR* [CRTC:37:pipe A] flip_done timed out
>[  977.116336] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:49:eDP-1]
>[  977.116421] [drm:intel_atomic_commit_tail [i915]] [CRTC:37:pipe A]
>[  977.116519] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[  977.116583] [drm:intel_power_well_disable [i915]] disabling DC off
>[  977.116638] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  977.116691] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  977.153902] [drm:intel_power_well_enable [i915]] enabling DC off
>[  977.153962] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  977.154061] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[  977.154212] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006f
>[  977.354041] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped
>[  977.354124] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[  977.354218] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[  977.354280] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[  980.444416] [drm:edp_panel_vdd_off_sync [i915]] Turning eDP port A VDD off
>[  980.444562] [drm:edp_panel_vdd_off_sync [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x00000067
>[  980.444619] [drm:intel_power_well_disable [i915]] disabling DC off
>[  980.444676] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[  980.444729] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[  986.881581] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[  986.881663] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[  986.881787] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[  986.881852] [drm:intel_power_well_enable [i915]] enabling DC off
>[  986.881918] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[  986.881978] [drm:intel_power_well_enable [i915]] enabling power well 2
>[  987.150632] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[  987.150714] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[  987.356199] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [CRTC:37:pipe A] flip_done timed out
>[  991.925904] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[  991.925985] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[  992.195003] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[  992.195085] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[  997.596331] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [CONNECTOR:49:eDP-1] flip_done timed out
>[  997.768646] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[  997.768726] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[  998.037840] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[  998.037921] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 1003.597481] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 1003.597562] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 1003.880214] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 1003.880296] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 1007.836230] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [PLANE:28:plane 1A] flip_done timed out
>[ 1007.836334] [drm:intel_edp_backlight_off [i915]] 
>[ 1008.044299] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0
>[ 1008.044434] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1008.055426] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[ 1008.055584] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b
>[ 1008.055856] [drm:intel_edp_panel_off.part.31 [i915]] Turn eDP port A panel power off
>[ 1008.055958] [drm:intel_edp_panel_off.part.31 [i915]] Wait for panel power off time
>[ 1008.056120] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000002 control 00000060
>[ 1008.107670] [drm:wait_panel_status [i915]] Wait complete
>[ 1008.107733] [drm:intel_power_well_disable [i915]] disabling DDI A/E IO power well
>[ 1008.107818] [drm:intel_disable_shared_dpll [i915]] disable DPLL 0 (active 1, on? 1) for crtc 37
>[ 1008.107893] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 0
>[ 1008.107984] [drm:intel_atomic_commit_tail [i915]] [ENCODER:48:DDI A]
>[ 1008.108096] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI B]
>[ 1008.108170] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[ 1008.108245] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[ 1008.108313] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DDI C]
>[ 1008.108382] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST A]
>[ 1008.108450] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST B]
>[ 1008.108511] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI D]
>[ 1008.108576] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[ 1008.108637] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[ 1008.108705] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:49:eDP-1]
>[ 1008.108770] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[ 1008.108837] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[ 1008.108901] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[ 1008.108965] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[ 1008.109043] [drm:intel_atomic_commit_tail [i915]] [CRTC:37:pipe A]
>[ 1008.109146] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[ 1008.109619] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 00 00 04 00 0f 00 04
>[ 1008.115614] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010
>[ 1008.115691] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[ 1008.115767] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0
>[ 1008.138000] [drm:intel_power_well_disable [i915]] disabling power well 2
>[ 1008.138054] [drm:intel_power_well_disable [i915]] disabling DC off
>[ 1008.138101] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[ 1008.138145] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[ 1008.138580] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1008.138646] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[ 1008.138708] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[ 1008.138752] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1008.138795] [drm:intel_power_well_enable [i915]] enabling DC off
>[ 1008.139084] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[ 1008.139130] [drm:intel_power_well_enable [i915]] enabling power well 2
>[ 1008.139615] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 00 00 04 00 0f 00 04
>[ 1008.141049] [drm:intel_power_well_disable [i915]] disabling power well 2
>[ 1008.141097] [drm:intel_power_well_disable [i915]] disabling DC off
>[ 1008.141142] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[ 1008.141184] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[ 1008.141620] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1008.142737] [drm:drm_mode_addfb2 [drm]] [FB:73]
>[ 1008.143595] [drm:drm_mode_addfb2 [drm]] [FB:102]
>[ 1008.144851] [drm:drm_mode_addfb2 [drm]] [FB:103]
>[ 1008.145675] [drm:drm_mode_addfb2 [drm]] [FB:104]
>[ 1008.215772] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[ 1008.215779] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[ 1008.215805] [drm:intel_atomic_check [i915]] [CONNECTOR:49:eDP-1] checking for sink bpp constrains
>[ 1008.215818] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1008.215825] [drm:drm_mode_debug_printmodeline [drm]] Modeline 52:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[ 1008.215839] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 138780KHz
>[ 1008.215855] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24
>[ 1008.215867] [drm:intel_dp_compute_config [i915]] DP link bw required 416340 available 540000
>[ 1008.215878] [drm:intel_dp_compute_config [i915]] PSR disable by flag
>[ 1008.215891] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1008.215904] [drm:intel_dump_pipe_config [i915]] [CRTC:37:pipe A][modeset]
>[ 1008.215915] [drm:intel_dump_pipe_config [i915]] output_types: EDP (0x100)
>[ 1008.215927] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0
>[ 1008.215938] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 6467616, gmch_n: 8388608, link_m: 269484, link_n: 524288, tu: 64
>[ 1008.215949] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[ 1008.215959] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1008.215969] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[ 1008.215979] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1008.215985] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[ 1008.216012] [drm:intel_dump_pipe_config [i915]] crtc timings: 138780 1920 1966 1996 2080 1080 1082 1086 1112, type: 0x48 flags: 0xa
>[ 1008.216038] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 138780
>[ 1008.216051] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[ 1008.216063] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1008.216075] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1008.216087] [drm:intel_dump_pipe_config [i915]] dpll_hw_state: ctrl1: 0x3, cfgcr1: 0x0, cfgcr2: 0x0
>[ 1008.216099] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1008.216111] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 1A] disabled, scaler_id = -1
>[ 1008.216123] [drm:intel_dump_pipe_config [i915]] [PLANE:31:plane 2A] disabled, scaler_id = -1
>[ 1008.216135] [drm:intel_dump_pipe_config [i915]] [PLANE:34:cursor A] disabled, scaler_id = -1
>[ 1008.216165] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1008.216177] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[ 1008.216207] [drm:intel_find_shared_dpll [i915]] [CRTC:37:pipe A] allocated DPLL 0
>[ 1008.216219] [drm:intel_reference_shared_dpll [i915]] using DPLL 0 for pipe A
>[ 1008.217178] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1008.217187] [drm:intel_power_well_enable [i915]] enabling DC off
>[ 1008.217499] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[ 1008.217533] [drm:intel_atomic_commit_tail [i915]] [ENCODER:48:DDI A]
>[ 1008.217546] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI B]
>[ 1008.217575] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[ 1008.217586] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[ 1008.217597] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DDI C]
>[ 1008.217608] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST A]
>[ 1008.217619] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST B]
>[ 1008.217630] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI D]
>[ 1008.217641] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[ 1008.217651] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[ 1008.217663] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[ 1008.217676] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[ 1008.217687] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[ 1008.217699] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[ 1008.217712] [drm:intel_enable_shared_dpll [i915]] enable DPLL 0 (active 1, on? 0) for crtc 37
>[ 1008.217724] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 0
>[ 1008.217742] [drm:edp_panel_on [i915]] Turn eDP port A panel power on
>[ 1008.217766] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle
>[ 1008.732204] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 00000000 control 00000060
>[ 1008.732302] [drm:wait_panel_status [i915]] Wait complete
>[ 1008.732434] [drm:edp_panel_on [i915]] Wait for panel power on
>[ 1008.732555] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 00000063
>[ 1008.764377] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010
>[ 1008.764450] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[ 1008.764517] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1
>[ 1008.764614] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[ 1008.935260] [drm:wait_panel_status [i915]] Wait complete
>[ 1008.935319] [drm:intel_power_well_enable [i915]] enabling DDI A/E IO power well
>[ 1008.935412] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[ 1008.935554] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b
>[ 1008.936772] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1008.936837] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1008.936895] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1008.936951] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1008.937653] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1008.937706] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1008.938700] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1008.938755] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:49:eDP-1] Link Training Passed at Link Rate = 270000, Lane count = 2
>[ 1008.939389] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1008.939458] [drm:intel_edp_backlight_on [i915]] 
>[ 1008.939513] [drm:intel_panel_enable_backlight [i915]] pipe A
>[ 1008.939597] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 120000
>[ 1008.944098] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS
>[ 1009.434280] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 1009.434361] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 1009.434486] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[ 1009.434552] [drm:intel_power_well_enable [i915]] enabling power well 2
>[ 1009.696007] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 1009.696088] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 1012.188289] [drm:edp_panel_vdd_off_sync [i915]] Turning eDP port A VDD off
>[ 1012.188434] [drm:edp_panel_vdd_off_sync [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x00000067
>[ 1015.274628] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 1015.274710] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 1015.534638] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 1015.534720] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 1019.100231] [drm:drm_atomic_helper_wait_for_flip_done [drm_kms_helper]] *ERROR* [CRTC:37:pipe A] flip_done timed out
>[ 1019.100352] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:49:eDP-1]
>[ 1019.100434] [drm:intel_atomic_commit_tail [i915]] [CRTC:37:pipe A]
>[ 1019.100531] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[ 1019.101116] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 00 00 04 00 0f 00 04
>[ 1019.102533] [drm:intel_power_well_disable [i915]] disabling power well 2
>[ 1019.102583] [drm:intel_power_well_disable [i915]] disabling DC off
>[ 1019.102629] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[ 1019.102672] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[ 1019.102738] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[ 1019.102781] [drm:intel_power_well_enable [i915]] enabling DC off
>[ 1019.102824] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[ 1019.102871] [drm:intel_power_well_enable [i915]] enabling power well 2
>[ 1019.103355] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 00 00 04 00 0f 00 04
>[ 1019.104783] [drm:intel_power_well_disable [i915]] disabling power well 2
>[ 1019.104836] [drm:intel_power_well_disable [i915]] disabling DC off
>[ 1019.104885] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[ 1019.104932] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[ 1019.139381] [drm:intel_power_well_enable [i915]] enabling DC off
>[ 1019.139433] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[ 1019.139521] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[ 1019.139666] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006f
>[ 1019.339698] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped
>[ 1019.339748] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[ 1019.339780] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[ 1021.104275] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 1021.104354] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 1021.104476] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[ 1021.104541] [drm:intel_power_well_enable [i915]] enabling power well 2
>[ 1021.364219] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 1021.364300] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 1022.428307] [drm:edp_panel_vdd_off_sync [i915]] Turning eDP port A VDD off
>[ 1022.428453] [drm:edp_panel_vdd_off_sync [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x00000067
>[ 1026.935502] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 1026.935583] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 1027.195826] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 1027.195907] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 1029.596328] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [CRTC:37:pipe A] flip_done timed out
>[ 1032.766520] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 1032.766602] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 1033.030174] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 1033.030255] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 1038.598713] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 1038.598794] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 1038.861819] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 1038.861900] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 1039.836329] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [CONNECTOR:49:eDP-1] flip_done timed out
>[ 1044.436966] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 1044.437048] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 1044.700001] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 1044.700083] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 1050.076209] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [PLANE:28:plane 1A] flip_done timed out
>[ 1050.266914] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 1050.266997] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 1050.527125] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 1050.527206] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 1056.097372] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 1056.097452] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 1056.356853] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 1056.356934] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 1060.316226] [drm:drm_atomic_helper_wait_for_flip_done [drm_kms_helper]] *ERROR* [CRTC:37:pipe A] flip_done timed out
>[ 1060.316829] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 00 00 04 00 0f 00 04
>[ 1060.318235] [drm:intel_power_well_disable [i915]] disabling power well 2
>[ 1060.318292] [drm:intel_power_well_disable [i915]] disabling DC off
>[ 1060.318343] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[ 1060.318391] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[ 1060.318466] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[ 1060.318514] [drm:intel_power_well_enable [i915]] enabling DC off
>[ 1060.318578] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[ 1060.318625] [drm:intel_power_well_enable [i915]] enabling power well 2
>[ 1060.319099] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 00 00 04 00 0f 00 04
>[ 1060.320392] [drm:intel_power_well_disable [i915]] disabling power well 2
>[ 1060.320417] [drm:intel_power_well_disable [i915]] disabling DC off
>[ 1060.320426] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[ 1060.320435] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[ 1060.355294] [drm:intel_power_well_enable [i915]] enabling DC off
>[ 1060.355310] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[ 1060.355349] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[ 1060.355449] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006f
>[ 1060.555613] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped
>[ 1060.555654] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[ 1060.555683] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[ 1061.925174] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 1061.925256] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 1061.925377] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[ 1061.925442] [drm:intel_power_well_enable [i915]] enabling power well 2
>[ 1062.185373] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 1062.185454] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 1063.644289] [drm:edp_panel_vdd_off_sync [i915]] Turning eDP port A VDD off
>[ 1063.644436] [drm:edp_panel_vdd_off_sync [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x00000067
>[ 1067.761342] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 1067.761423] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 1068.022643] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 1068.022724] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 1070.812324] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [CRTC:37:pipe A] flip_done timed out
>[ 1073.598752] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 1073.598834] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 1073.858610] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 1073.858692] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 1079.421962] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 1079.422043] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 1079.682213] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 1079.682294] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 1081.052324] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [CONNECTOR:49:eDP-1] flip_done timed out
>[ 1085.260268] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 1085.260349] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 1085.520283] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 1085.520365] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 1091.097396] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 1091.097478] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 1091.292208] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [PLANE:28:plane 1A] flip_done timed out
>[ 1091.356705] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 1091.356786] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 1096.928213] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 1096.928294] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 1097.186852] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 1097.186933] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 1101.532223] [drm:drm_atomic_helper_wait_for_flip_done [drm_kms_helper]] *ERROR* [CRTC:37:pipe A] flip_done timed out
>[ 1101.532825] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 00 00 04 00 0f 00 04
>[ 1101.534229] [drm:intel_power_well_disable [i915]] disabling power well 2
>[ 1101.534287] [drm:intel_power_well_disable [i915]] disabling DC off
>[ 1101.534337] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[ 1101.534385] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[ 1101.534461] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[ 1101.534508] [drm:intel_power_well_enable [i915]] enabling DC off
>[ 1101.534555] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[ 1101.534606] [drm:intel_power_well_enable [i915]] enabling power well 2
>[ 1101.535091] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 00 00 04 00 0f 00 04
>[ 1101.536532] [drm:intel_power_well_disable [i915]] disabling power well 2
>[ 1101.536585] [drm:intel_power_well_disable [i915]] disabling DC off
>[ 1101.536635] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[ 1101.536683] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[ 1101.571598] [drm:intel_power_well_enable [i915]] enabling DC off
>[ 1101.571653] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[ 1101.571742] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[ 1101.571888] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006f
>[ 1101.771587] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped
>[ 1101.771636] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[ 1101.771667] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[ 1102.752807] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 1102.752888] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 1102.753008] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[ 1102.753074] [drm:intel_power_well_enable [i915]] enabling power well 2
>[ 1103.011004] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 1103.011086] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 1104.860304] [drm:edp_panel_vdd_off_sync [i915]] Turning eDP port A VDD off
>[ 1104.860449] [drm:edp_panel_vdd_off_sync [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x00000067
>[ 1108.574663] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 1108.574744] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 1108.836278] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 1108.836360] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 1112.028223] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [CRTC:37:pipe A] flip_done timed out
>[ 1114.404596] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 1114.404678] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 1114.665529] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 1114.665610] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 1120.233276] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 1120.233357] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 1120.495584] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 1120.495665] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 1122.268305] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [CONNECTOR:49:eDP-1] flip_done timed out
>[ 1126.065285] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 1126.065366] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 1126.327057] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 1126.327138] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 1131.896535] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 1131.896617] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 1132.158344] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 1132.158426] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 1132.508207] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [PLANE:28:plane 1A] flip_done timed out
>[ 1137.730837] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 1137.730918] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 1137.989569] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 1137.989650] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 1142.748247] [drm:drm_atomic_helper_wait_for_flip_done [drm_kms_helper]] *ERROR* [CRTC:37:pipe A] flip_done timed out
>[ 1142.748842] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 00 00 04 00 0f 00 04
>[ 1142.750244] [drm:intel_power_well_disable [i915]] disabling power well 2
>[ 1142.750295] [drm:intel_power_well_disable [i915]] disabling DC off
>[ 1142.750340] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[ 1142.750383] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[ 1142.750450] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[ 1142.750493] [drm:intel_power_well_enable [i915]] enabling DC off
>[ 1142.750534] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[ 1142.750581] [drm:intel_power_well_enable [i915]] enabling power well 2
>[ 1142.751055] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 00 00 04 00 0f 00 04
>[ 1142.752416] [drm:intel_power_well_disable [i915]] disabling power well 2
>[ 1142.752454] [drm:intel_power_well_disable [i915]] disabling DC off
>[ 1142.752464] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[ 1142.752473] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[ 1142.787401] [drm:intel_power_well_enable [i915]] enabling DC off
>[ 1142.787417] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[ 1142.787453] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[ 1142.787552] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006f
>[ 1142.987527] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped
>[ 1142.987646] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[ 1142.987735] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1142.987795] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[ 1143.567294] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 1143.567376] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 1143.567501] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[ 1143.567568] [drm:intel_power_well_enable [i915]] enabling power well 2
>[ 1143.825456] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 1143.825538] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 1146.076302] [drm:edp_panel_vdd_off_sync [i915]] Turning eDP port A VDD off
>[ 1146.076447] [drm:edp_panel_vdd_off_sync [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x00000067
>[ 1149.388698] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 1149.388779] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 1149.651247] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 1149.651329] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 1152.988071] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [CRTC:37:pipe A] flip_done timed out
>[ 1155.215637] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 1155.215718] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 1155.476865] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 1155.476947] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 1161.044428] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 1161.044509] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 1161.306250] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 1161.306332] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 1163.228321] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [CONNECTOR:49:eDP-1] flip_done timed out
>[ 1166.881807] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 1166.881887] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 1167.141438] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 1167.141517] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 1172.708547] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 1172.708628] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 1172.968986] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 1172.969067] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 1173.468236] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [PLANE:28:plane 1A] flip_done timed out
>[ 1173.468342] [drm:intel_edp_backlight_off [i915]] 
>[ 1173.676383] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0
>[ 1173.676521] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1173.687509] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[ 1173.687667] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b
>[ 1173.687942] [drm:intel_edp_panel_off.part.31 [i915]] Turn eDP port A panel power off
>[ 1173.688079] [drm:intel_edp_panel_off.part.31 [i915]] Wait for panel power off time
>[ 1173.688221] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000002 control 00000060
>[ 1173.740782] [drm:wait_panel_status [i915]] Wait complete
>[ 1173.740845] [drm:intel_power_well_disable [i915]] disabling DDI A/E IO power well
>[ 1173.740931] [drm:intel_disable_shared_dpll [i915]] disable DPLL 0 (active 1, on? 1) for crtc 37
>[ 1173.741006] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 0
>[ 1173.741097] [drm:intel_atomic_commit_tail [i915]] [ENCODER:48:DDI A]
>[ 1173.741168] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI B]
>[ 1173.741234] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[ 1173.741298] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[ 1173.741360] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DDI C]
>[ 1173.741422] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST A]
>[ 1173.741483] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST B]
>[ 1173.741542] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI D]
>[ 1173.741602] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[ 1173.741661] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[ 1173.741726] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:49:eDP-1]
>[ 1173.741793] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[ 1173.741857] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[ 1173.741919] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[ 1173.741979] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[ 1173.742054] [drm:intel_atomic_commit_tail [i915]] [CRTC:37:pipe A]
>[ 1173.742176] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[ 1173.742636] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 00 00 04 00 0f 00 04
>[ 1173.744069] [drm:intel_power_well_disable [i915]] disabling power well 2
>[ 1173.744083] [drm:intel_power_well_disable [i915]] disabling DC off
>[ 1173.744099] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[ 1173.744115] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[ 1173.744117] Setting dangerous option enable_psr - tainting kernel
>[ 1173.744133] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1173.744168] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[ 1173.744183] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1173.744193] [drm:intel_power_well_enable [i915]] enabling DC off
>[ 1173.745008] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[ 1173.745075] [drm:intel_power_well_enable [i915]] enabling power well 2
>[ 1173.745083] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[ 1173.745496] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 00 00 04 00 0f 00 04
>[ 1173.746754] [drm:intel_power_well_disable [i915]] disabling power well 2
>[ 1173.746761] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[ 1173.746774] [drm:intel_power_well_disable [i915]] disabling DC off
>[ 1173.746792] [drm:intel_atomic_check [i915]] [CONNECTOR:49:eDP-1] checking for sink bpp constrains
>[ 1173.746807] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1173.746818] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[ 1173.746828] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[ 1173.746835] [drm:drm_mode_debug_printmodeline [drm]] Modeline 52:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[ 1173.746851] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 138780KHz
>[ 1173.746861] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1173.746880] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24
>[ 1173.746893] [drm:intel_dp_compute_config [i915]] DP link bw required 416340 available 540000
>[ 1173.746908] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1173.746923] [drm:intel_dump_pipe_config [i915]] [CRTC:37:pipe A][modeset]
>[ 1173.746937] [drm:intel_dump_pipe_config [i915]] output_types: EDP (0x100)
>[ 1173.746950] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0
>[ 1173.746964] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 6467616, gmch_n: 8388608, link_m: 269484, link_n: 524288, tu: 64
>[ 1173.746976] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[ 1173.746988] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1173.746995] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[ 1173.747007] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1173.747013] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[ 1173.747026] [drm:intel_dump_pipe_config [i915]] crtc timings: 138780 1920 1966 1996 2080 1080 1082 1086 1112, type: 0x48 flags: 0xa
>[ 1173.747039] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 138780
>[ 1173.747051] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[ 1173.747063] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1173.747075] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1173.747088] [drm:intel_dump_pipe_config [i915]] dpll_hw_state: ctrl1: 0x3, cfgcr1: 0x0, cfgcr2: 0x0
>[ 1173.747099] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1173.747111] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 1A] disabled, scaler_id = -1
>[ 1173.747123] [drm:intel_dump_pipe_config [i915]] [PLANE:31:plane 2A] disabled, scaler_id = -1
>[ 1173.747134] [drm:intel_dump_pipe_config [i915]] [PLANE:34:cursor A] disabled, scaler_id = -1
>[ 1173.747149] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1173.747162] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[ 1173.747178] [drm:intel_find_shared_dpll [i915]] [CRTC:37:pipe A] allocated DPLL 0
>[ 1173.747192] [drm:intel_reference_shared_dpll [i915]] using DPLL 0 for pipe A
>[ 1173.747551] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1173.747561] [drm:intel_power_well_enable [i915]] enabling DC off
>[ 1173.747816] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[ 1173.747873] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010
>[ 1173.747887] [drm:intel_atomic_commit_tail [i915]] [ENCODER:48:DDI A]
>[ 1173.747901] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI B]
>[ 1173.747914] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[ 1173.747929] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[ 1173.747944] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0
>[ 1173.747966] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[ 1173.747980] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DDI C]
>[ 1173.747998] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[ 1173.748011] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST A]
>[ 1173.748025] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST B]
>[ 1173.748039] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI D]
>[ 1173.748053] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[ 1173.748067] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[ 1173.748082] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[ 1173.748097] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[ 1173.748111] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[ 1173.748126] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[ 1173.748142] [drm:intel_enable_shared_dpll [i915]] enable DPLL 0 (active 1, on? 0) for crtc 37
>[ 1173.748157] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 0
>[ 1173.748179] [drm:edp_panel_on [i915]] Turn eDP port A panel power on
>[ 1173.748206] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle
>[ 1174.364185] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 00000000 control 00000060
>[ 1174.364282] [drm:wait_panel_status [i915]] Wait complete
>[ 1174.364414] [drm:edp_panel_on [i915]] Wait for panel power on
>[ 1174.364537] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 00000063
>[ 1174.396727] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010
>[ 1174.396787] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[ 1174.396845] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1
>[ 1174.396923] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[ 1174.566034] [drm:wait_panel_status [i915]] Wait complete
>[ 1174.566094] [drm:intel_power_well_enable [i915]] enabling DDI A/E IO power well
>[ 1174.566188] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[ 1174.566333] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b
>[ 1174.567553] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1174.567618] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1174.567676] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1174.567733] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1174.568438] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1174.568492] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1174.569489] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1174.569544] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:49:eDP-1] Link Training Passed at Link Rate = 270000, Lane count = 2
>[ 1174.570180] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1174.570245] [drm:intel_edp_backlight_on [i915]] 
>[ 1174.570301] [drm:intel_panel_enable_backlight [i915]] pipe A
>[ 1174.570383] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 120000
>[ 1174.576277] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS
>[ 1177.820434] [drm:edp_panel_vdd_off_sync [i915]] Turning eDP port A VDD off
>[ 1177.820581] [drm:edp_panel_vdd_off_sync [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x00000067
>[ 1178.538121] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 1178.538203] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 1178.538327] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[ 1178.538394] [drm:intel_power_well_enable [i915]] enabling power well 2
>[ 1178.801588] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 1178.801670] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 1184.377253] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 1184.377334] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 1184.637953] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 1184.638034] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 1184.732231] [drm:drm_atomic_helper_wait_for_flip_done [drm_kms_helper]] *ERROR* [CRTC:37:pipe A] flip_done timed out
>[ 1184.732355] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:49:eDP-1]
>[ 1184.732438] [drm:intel_atomic_commit_tail [i915]] [CRTC:37:pipe A]
>[ 1184.732535] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[ 1184.733123] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 00 00 04 00 0f 00 04
>[ 1184.734528] [drm:intel_power_well_disable [i915]] disabling power well 2
>[ 1184.734584] [drm:intel_power_well_disable [i915]] disabling DC off
>[ 1184.734636] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[ 1184.734684] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[ 1184.734756] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[ 1184.734804] [drm:intel_power_well_enable [i915]] enabling DC off
>[ 1184.734851] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[ 1184.734903] [drm:intel_power_well_enable [i915]] enabling power well 2
>[ 1184.735386] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 00 00 04 00 0f 00 04
>[ 1184.736810] [drm:intel_power_well_disable [i915]] disabling power well 2
>[ 1184.736863] [drm:intel_power_well_disable [i915]] disabling DC off
>[ 1184.736912] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[ 1184.736959] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[ 1184.770198] [drm:intel_power_well_enable [i915]] enabling DC off
>[ 1184.770250] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[ 1184.770339] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[ 1184.770486] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006f
>[ 1184.970481] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped
>[ 1185.220483] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped
>[ 1185.470626] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped
>[ 1185.720465] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped
>[ 1185.970465] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped
>[ 1189.084302] [drm:edp_panel_vdd_off_sync [i915]] Turning eDP port A VDD off
>[ 1189.084447] [drm:edp_panel_vdd_off_sync [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x00000067
>[ 1189.084504] [drm:intel_power_well_disable [i915]] disabling DC off
>[ 1189.084561] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[ 1189.084614] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[ 1190.208770] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 1190.208852] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 1190.208977] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[ 1190.209043] [drm:intel_power_well_enable [i915]] enabling DC off
>[ 1190.209108] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[ 1190.209168] [drm:intel_power_well_enable [i915]] enabling power well 2
>[ 1190.470842] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 1190.470925] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 1195.996321] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [CRTC:37:pipe A] flip_done timed out
>[ 1196.042268] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 1196.042349] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 1196.302298] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 1196.302380] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 1201.865481] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 1201.865562] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 1202.125936] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 1202.126017] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 1206.236320] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [PLANE:28:plane 1A] flip_done timed out
>[ 1207.685820] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 1207.685902] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 1207.946590] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 1207.946671] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 1213.515980] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 1213.516061] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 1213.776423] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 1213.776504] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 1216.476306] [drm:drm_atomic_helper_wait_for_flip_done [drm_kms_helper]] *ERROR* [CRTC:37:pipe A] flip_done timed out
>[ 1216.476587] [IGT] kms_frontbuffer_tracking: exiting, ret=0
>[ 1216.476657] Setting dangerous option enable_psr - tainting kernel
>[ 1216.476671] Setting dangerous option enable_fbc - tainting kernel
>[ 1216.476916] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 00 00 04 00 0f 00 04
>[ 1216.478498] [drm:intel_power_well_disable [i915]] disabling power well 2
>[ 1216.478550] [drm:intel_power_well_disable [i915]] disabling DC off
>[ 1216.478596] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[ 1216.478639] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[ 1216.478707] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[ 1216.478750] [drm:intel_power_well_enable [i915]] enabling DC off
>[ 1216.478793] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[ 1216.478839] [drm:intel_power_well_enable [i915]] enabling power well 2
>[ 1216.479317] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 00 00 04 00 0f 00 04
>[ 1216.480710] [drm:intel_power_well_disable [i915]] disabling power well 2
>[ 1216.480762] [drm:intel_power_well_disable [i915]] disabling DC off
>[ 1216.480810] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[ 1216.480857] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[ 1216.516097] [drm:intel_atomic_check [i915]] [CONNECTOR:57:DP-1] checking for sink bpp constrains
>[ 1216.516113] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1216.516129] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 148500KHz
>[ 1216.516145] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1216.516158] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 648000
>[ 1216.516173] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1216.516188] [drm:intel_dump_pipe_config [i915]] [CRTC:47:pipe B][modeset]
>[ 1216.516202] [drm:intel_dump_pipe_config [i915]] output_types: DP (0x80)
>[ 1216.516215] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1216.516229] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5767168, gmch_n: 8388608, link_m: 240298, link_n: 262144, tu: 64
>[ 1216.516242] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[ 1216.516254] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1216.516262] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[ 1216.516274] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1216.516281] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[ 1216.516294] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[ 1216.516306] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1080, pixel rate 148500
>[ 1216.516318] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[ 1216.516331] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1216.516342] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1216.516355] [drm:intel_dump_pipe_config [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[ 1216.516366] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1216.516378] [drm:intel_dump_pipe_config [i915]] [PLANE:38:plane 1B] disabled, scaler_id = -1
>[ 1216.516390] [drm:intel_dump_pipe_config [i915]] [PLANE:41:plane 2B] disabled, scaler_id = -1
>[ 1216.516402] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor B] disabled, scaler_id = -1
>[ 1216.516417] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1216.516430] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[ 1216.516448] [drm:intel_find_shared_dpll [i915]] [CRTC:47:pipe B] allocated DPLL 1
>[ 1216.516461] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[ 1219.352153] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 1219.352233] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 1219.352356] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[ 1219.352421] [drm:intel_power_well_enable [i915]] enabling DC off
>[ 1219.352485] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[ 1219.352545] [drm:intel_power_well_enable [i915]] enabling power well 2
>[ 1219.613563] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 1219.613644] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 1225.184176] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 1225.184257] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 1225.445618] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 1225.445699] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 1226.716305] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [CRTC:37:pipe A] flip_done timed out
>[ 1231.011629] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 1231.011720] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 1231.275444] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 1231.275525] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 1236.851187] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 1236.851268] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 1236.956292] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [CONNECTOR:49:eDP-1] flip_done timed out
>[ 1237.109563] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 1237.109644] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 1242.675710] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 1242.675791] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 1242.937168] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 1242.937249] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 1247.196302] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [PLANE:28:plane 1A] flip_done timed out
>[ 1247.196395] [drm:intel_disable_sagv [i915]] Disabling the SAGV
>[ 1247.196487] [drm:intel_atomic_commit_tail [i915]] [ENCODER:48:DDI A]
>[ 1247.196562] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI B]
>[ 1247.196632] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[ 1247.196698] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[ 1247.196763] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DDI C]
>[ 1247.196826] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST A]
>[ 1247.196888] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST B]
>[ 1247.196949] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI D]
>[ 1247.197009] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[ 1247.197068] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[ 1247.197135] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[ 1247.197205] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[ 1247.197269] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[ 1247.197333] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[ 1247.197410] [drm:intel_fbc_enable [i915]] reserved 16588800 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1247.197476] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1247.202562] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 2, on? 0) for crtc 47
>[ 1247.202639] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[ 1247.202755] [drm:intel_power_well_enable [i915]] enabling DDI B IO power well
>[ 1247.203367] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 1247.204655] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 1247.205913] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 1247.207160] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 1247.208441] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 1247.209326] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[ 1247.210323] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1247.210391] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1247.210455] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1247.210518] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1247.229198] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1247.229226] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[ 1247.246961] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1247.247284] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:57:DP-1] Link Training Passed at Link Rate = 162000, Lane count = 4
>[ 1247.247653] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1247.247684] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS
>[ 1248.510576] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 1248.510658] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 1248.773737] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 1248.773818] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 1257.436047] [drm:drm_atomic_helper_wait_for_flip_done [drm_kms_helper]] *ERROR* [CRTC:37:pipe A] flip_done timed out
>[ 1257.436180] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:57:DP-1]
>[ 1257.436264] [drm:intel_atomic_commit_tail [i915]] [CRTC:47:pipe B]
>[ 1257.436362] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[ 1257.436964] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 00 00 04 00 0f 00 04
>[ 1257.438423] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[ 1257.438908] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 00 00 04 00 0f 00 04
>[ 1257.485373] [IGT] kms_frontbuffer_tracking: executing
>[ 1257.521385] [drm:drm_mode_addfb2 [drm]] [FB:75]
>[ 1257.521410] [drm:drm_mode_addfb2 [drm]] [FB:91]
>[ 1257.521435] [drm:drm_mode_addfb2 [drm]] [FB:92]
>[ 1257.521998] [drm:drm_mode_addfb2 [drm]] [FB:93]
>[ 1257.526911] [drm:drm_mode_addfb2 [drm]] [FB:94]
>[ 1257.528109] [drm:drm_mode_addfb2 [drm]] [FB:96]
>[ 1257.528134] [drm:drm_mode_addfb2 [drm]] [FB:98]
>[ 1257.528163] [drm:drm_mode_addfb2 [drm]] [FB:102]
>[ 1257.528346] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[ 1257.528355] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[ 1267.676311] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [CRTC:37:pipe A] flip_done timed out
>[ 1277.916023] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [CONNECTOR:49:eDP-1] flip_done timed out
>[ 1288.156299] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [PLANE:28:plane 1A] flip_done timed out
>[ 1298.396306] [drm:drm_atomic_helper_wait_for_flip_done [drm_kms_helper]] *ERROR* [CRTC:37:pipe A] flip_done timed out
>[ 1298.396493] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[ 1298.396647] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006f
>[ 1298.585166] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped
>[ 1298.585399] [IGT] kms_frontbuffer_tracking: starting subtest psr-1p-offscren-pri-indfb-draw-mmap-gtt
>[ 1298.585475] Setting dangerous option enable_fbc - tainting kernel
>[ 1298.585496] Setting dangerous option enable_psr - tainting kernel
>[ 1301.724387] [drm:edp_panel_vdd_off_sync [i915]] Turning eDP port A VDD off
>[ 1301.724532] [drm:edp_panel_vdd_off_sync [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x00000067
>[ 1308.636164] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [CRTC:37:pipe A] flip_done timed out
>[ 1318.876312] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [PLANE:28:plane 1A] flip_done timed out
>[ 1329.116300] [drm:drm_atomic_helper_wait_for_flip_done [drm_kms_helper]] *ERROR* [CRTC:37:pipe A] flip_done timed out
>[ 1329.120680] [drm:drm_mode_addfb2 [drm]] [FB:72]
>[ 1329.120780] [drm:drm_mode_addfb2 [drm]] [FB:75]
>[ 1329.120883] [drm:drm_mode_addfb2 [drm]] [FB:91]
>[ 1329.122088] [drm:drm_mode_addfb2 [drm]] [FB:92]
>[ 1329.125830] [drm:drm_mode_addfb2 [drm]] [FB:93]
>[ 1329.126670] [drm:drm_mode_addfb2 [drm]] [FB:94]
>[ 1329.126691] [drm:drm_mode_addfb2 [drm]] [FB:96]
>[ 1329.126711] [drm:drm_mode_addfb2 [drm]] [FB:98]
>[ 1329.126817] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[ 1329.126851] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1329.126866] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[ 1339.356300] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [CRTC:37:pipe A] flip_done timed out
>[ 1349.596198] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [CONNECTOR:49:eDP-1] flip_done timed out
>[ 1359.836275] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [PLANE:28:plane 1A] flip_done timed out
>[ 1359.836417] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[ 1359.836571] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006f
>[ 1359.836852] [drm:intel_edp_backlight_off [i915]] 
>[ 1360.044367] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0
>[ 1360.044506] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1360.053172] [drm:intel_edp_panel_off.part.31 [i915]] Turn eDP port A panel power off
>[ 1360.053283] [drm:intel_edp_panel_off.part.31 [i915]] Wait for panel power off time
>[ 1360.053414] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000003 control 00000060
>[ 1360.104591] [drm:wait_panel_status [i915]] Wait complete
>[ 1360.104654] [drm:intel_power_well_disable [i915]] disabling DDI A/E IO power well
>[ 1360.104737] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1360.104817] [drm:intel_disable_shared_dpll [i915]] disable DPLL 0 (active 1, on? 1) for crtc 37
>[ 1360.104889] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 0
>[ 1360.104982] [drm:intel_atomic_commit_tail [i915]] [ENCODER:48:DDI A]
>[ 1360.105054] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI B]
>[ 1360.105121] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[ 1360.105187] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[ 1360.105250] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DDI C]
>[ 1360.105312] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST A]
>[ 1360.105373] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST B]
>[ 1360.105435] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI D]
>[ 1360.105495] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[ 1360.105555] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[ 1360.105620] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:49:eDP-1]
>[ 1360.105687] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[ 1360.105751] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[ 1360.105815] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[ 1360.105876] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[ 1360.113084] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010
>[ 1360.113166] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[ 1360.113240] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0
>[ 1360.113358] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[ 1360.114925] [drm:intel_atomic_commit_tail [i915]] [CRTC:37:pipe A]
>[ 1360.114997] [drm:intel_enable_sagv [i915]] Enabling the SAGV
>[ 1360.115097] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[ 1360.115197] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1360.115270] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[ 1360.115372] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1360.132231] [drm:intel_power_well_disable [i915]] disabling DDI B IO power well
>[ 1360.132315] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 2, on? 1) for crtc 47
>[ 1360.132388] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[ 1360.132477] [drm:intel_atomic_commit_tail [i915]] [ENCODER:48:DDI A]
>[ 1360.132543] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI B]
>[ 1360.132608] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[ 1360.132669] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[ 1360.132728] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DDI C]
>[ 1360.132787] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST A]
>[ 1360.132845] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST B]
>[ 1360.132902] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI D]
>[ 1360.132960] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[ 1360.133017] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[ 1360.133079] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:57:DP-1]
>[ 1360.133142] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[ 1360.133202] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[ 1360.133262] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[ 1360.133321] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[ 1360.133379] [drm:intel_power_well_disable [i915]] disabling power well 2
>[ 1360.133451] [drm:intel_atomic_commit_tail [i915]] [CRTC:47:pipe B]
>[ 1360.133507] [drm:intel_power_well_disable [i915]] disabling DC off
>[ 1360.133558] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[ 1360.133607] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[ 1360.134045] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1360.138156] [drm:drm_mode_addfb2 [drm]] [FB:73]
>[ 1360.139820] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[ 1360.139826] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[ 1360.139848] [drm:intel_atomic_check [i915]] [CONNECTOR:49:eDP-1] checking for sink bpp constrains
>[ 1360.139860] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1360.139867] [drm:drm_mode_debug_printmodeline [drm]] Modeline 52:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[ 1360.139880] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 138780KHz
>[ 1360.139896] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24
>[ 1360.139907] [drm:intel_dp_compute_config [i915]] DP link bw required 416340 available 540000
>[ 1360.139919] [drm:intel_dp_compute_config [i915]] PSR disable by flag
>[ 1360.139931] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1360.139944] [drm:intel_dump_pipe_config [i915]] [CRTC:37:pipe A][modeset]
>[ 1360.139960] [drm:intel_dump_pipe_config [i915]] output_types: EDP (0x100)
>[ 1360.139971] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0
>[ 1360.139983] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 6467616, gmch_n: 8388608, link_m: 269484, link_n: 524288, tu: 64
>[ 1360.140018] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[ 1360.140030] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1360.140038] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[ 1360.140050] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1360.140056] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[ 1360.140069] [drm:intel_dump_pipe_config [i915]] crtc timings: 138780 1920 1966 1996 2080 1080 1082 1086 1112, type: 0x48 flags: 0xa
>[ 1360.140082] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 138780
>[ 1360.140094] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[ 1360.140106] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1360.140120] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1360.140137] [drm:intel_dump_pipe_config [i915]] dpll_hw_state: ctrl1: 0x3, cfgcr1: 0x0, cfgcr2: 0x0
>[ 1360.140154] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1360.140184] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 1A] disabled, scaler_id = -1
>[ 1360.140195] [drm:intel_dump_pipe_config [i915]] [PLANE:31:plane 2A] disabled, scaler_id = -1
>[ 1360.140206] [drm:intel_dump_pipe_config [i915]] [PLANE:34:cursor A] disabled, scaler_id = -1
>[ 1360.140219] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1360.140230] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[ 1360.140244] [drm:intel_find_shared_dpll [i915]] [CRTC:37:pipe A] allocated DPLL 0
>[ 1360.140256] [drm:intel_reference_shared_dpll [i915]] using DPLL 0 for pipe A
>[ 1360.140775] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1360.140784] [drm:intel_power_well_enable [i915]] enabling DC off
>[ 1360.141061] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[ 1360.141100] [drm:intel_atomic_commit_tail [i915]] [ENCODER:48:DDI A]
>[ 1360.141112] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI B]
>[ 1360.141124] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[ 1360.141135] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[ 1360.141146] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DDI C]
>[ 1360.141157] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST A]
>[ 1360.141168] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST B]
>[ 1360.141178] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI D]
>[ 1360.141189] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[ 1360.141199] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[ 1360.141211] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[ 1360.141223] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[ 1360.141234] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[ 1360.141245] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[ 1360.141258] [drm:intel_enable_shared_dpll [i915]] enable DPLL 0 (active 1, on? 0) for crtc 37
>[ 1360.141270] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 0
>[ 1360.141289] [drm:edp_panel_on [i915]] Turn eDP port A panel power on
>[ 1360.141313] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle
>[ 1360.732413] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 00000000 control 00000060
>[ 1360.732521] [drm:wait_panel_status [i915]] Wait complete
>[ 1360.732659] [drm:edp_panel_on [i915]] Wait for panel power on
>[ 1360.732790] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 00000063
>[ 1360.766430] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010
>[ 1360.766512] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[ 1360.766585] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1
>[ 1360.766729] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[ 1360.933105] [drm:wait_panel_status [i915]] Wait complete
>[ 1360.933172] [drm:intel_power_well_enable [i915]] enabling DDI A/E IO power well
>[ 1360.933274] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[ 1360.933425] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b
>[ 1360.934624] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1360.934687] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1360.934746] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1360.934807] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1360.935516] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1360.935575] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1360.936546] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1360.936572] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:49:eDP-1] Link Training Passed at Link Rate = 270000, Lane count = 2
>[ 1360.936963] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1360.936984] [drm:intel_edp_backlight_on [i915]] 
>[ 1360.936996] [drm:intel_panel_enable_backlight [i915]] pipe A
>[ 1360.937034] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 120000
>[ 1360.944087] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS
>[ 1364.188145] [drm:edp_panel_vdd_off_sync [i915]] Turning eDP port A VDD off
>[ 1364.188293] [drm:edp_panel_vdd_off_sync [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x00000067
>[ 1371.100041] [drm:drm_atomic_helper_wait_for_flip_done [drm_kms_helper]] *ERROR* [CRTC:37:pipe A] flip_done timed out
>[ 1371.100161] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:49:eDP-1]
>[ 1371.100245] [drm:intel_atomic_commit_tail [i915]] [CRTC:37:pipe A]
>[ 1371.100342] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[ 1371.100406] [drm:intel_power_well_disable [i915]] disabling DC off
>[ 1371.100463] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[ 1371.100516] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[ 1371.137297] [drm:intel_power_well_enable [i915]] enabling DC off
>[ 1371.137356] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[ 1371.137452] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[ 1371.137605] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006f
>[ 1371.337270] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped
>[ 1371.337354] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[ 1371.337448] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1371.337510] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[ 1374.428392] [drm:edp_panel_vdd_off_sync [i915]] Turning eDP port A VDD off
>[ 1374.428538] [drm:edp_panel_vdd_off_sync [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x00000067
>[ 1374.428595] [drm:intel_power_well_disable [i915]] disabling DC off
>[ 1374.428652] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[ 1374.428705] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[ 1380.870909] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 1380.870991] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 1380.871115] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[ 1380.871180] [drm:intel_power_well_enable [i915]] enabling DC off
>[ 1380.871252] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[ 1380.871332] [drm:intel_power_well_enable [i915]] enabling power well 2
>[ 1381.140012] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 1381.140094] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 1381.340193] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [CRTC:37:pipe A] flip_done timed out
>[ 1385.915394] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 1385.915476] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 1386.184425] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 1386.184506] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 1391.580309] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [CONNECTOR:49:eDP-1] flip_done timed out
>[ 1391.757900] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 1391.757982] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 1392.040762] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 1392.040843] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 1397.614423] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 1397.614505] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 1397.883751] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 1397.883831] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 1401.819998] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [PLANE:28:plane 1A] flip_done timed out
>[ 1401.820103] [drm:intel_edp_backlight_off [i915]] 
>[ 1402.028368] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0
>[ 1402.028503] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1402.036736] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[ 1402.036894] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b
>[ 1402.037167] [drm:intel_edp_panel_off.part.31 [i915]] Turn eDP port A panel power off
>[ 1402.037269] [drm:intel_edp_panel_off.part.31 [i915]] Wait for panel power off time
>[ 1402.037394] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000002 control 00000060
>[ 1402.090030] [drm:wait_panel_status [i915]] Wait complete
>[ 1402.090094] [drm:intel_power_well_disable [i915]] disabling DDI A/E IO power well
>[ 1402.090181] [drm:intel_disable_shared_dpll [i915]] disable DPLL 0 (active 1, on? 1) for crtc 37
>[ 1402.090256] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 0
>[ 1402.090349] [drm:intel_atomic_commit_tail [i915]] [ENCODER:48:DDI A]
>[ 1402.090421] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI B]
>[ 1402.090488] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[ 1402.090552] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[ 1402.090614] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DDI C]
>[ 1402.090675] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST A]
>[ 1402.090737] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST B]
>[ 1402.090797] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI D]
>[ 1402.090857] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[ 1402.090916] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[ 1402.090981] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:49:eDP-1]
>[ 1402.091049] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[ 1402.091114] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[ 1402.091179] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[ 1402.091241] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[ 1402.091319] [drm:intel_atomic_commit_tail [i915]] [CRTC:37:pipe A]
>[ 1402.091441] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[ 1402.091910] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 00 00 04 00 0f 00 04
>[ 1402.096798] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010
>[ 1402.096816] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[ 1402.096833] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0
>[ 1402.120489] [drm:intel_power_well_disable [i915]] disabling power well 2
>[ 1402.120507] [drm:intel_power_well_disable [i915]] disabling DC off
>[ 1402.120523] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[ 1402.120537] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[ 1402.120552] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1402.120574] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[ 1402.120593] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[ 1402.120607] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1402.120621] [drm:intel_power_well_enable [i915]] enabling DC off
>[ 1402.120941] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[ 1402.120957] [drm:intel_power_well_enable [i915]] enabling power well 2
>[ 1402.121365] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 00 00 04 00 0f 00 04
>[ 1402.122018] [drm:drm_mode_addfb2 [drm]] [FB:73]
>[ 1402.122641] [drm:intel_power_well_disable [i915]] disabling power well 2
>[ 1402.122660] [drm:intel_power_well_disable [i915]] disabling DC off
>[ 1402.122676] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[ 1402.122692] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[ 1402.122709] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1402.123418] [drm:drm_mode_addfb2 [drm]] [FB:102]
>[ 1402.125119] [drm:drm_mode_addfb2 [drm]] [FB:103]
>[ 1402.126490] [drm:drm_mode_addfb2 [drm]] [FB:104]
>[ 1402.209003] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[ 1402.209011] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[ 1402.209037] [drm:intel_atomic_check [i915]] [CONNECTOR:49:eDP-1] checking for sink bpp constrains
>[ 1402.209050] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1402.209057] [drm:drm_mode_debug_printmodeline [drm]] Modeline 52:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[ 1402.209071] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 138780KHz
>[ 1402.209087] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24
>[ 1402.209098] [drm:intel_dp_compute_config [i915]] DP link bw required 416340 available 540000
>[ 1402.209110] [drm:intel_dp_compute_config [i915]] PSR disable by flag
>[ 1402.209122] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1402.209135] [drm:intel_dump_pipe_config [i915]] [CRTC:37:pipe A][modeset]
>[ 1402.209147] [drm:intel_dump_pipe_config [i915]] output_types: EDP (0x100)
>[ 1402.209159] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0
>[ 1402.209170] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 6467616, gmch_n: 8388608, link_m: 269484, link_n: 524288, tu: 64
>[ 1402.209181] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[ 1402.209191] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1402.209197] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[ 1402.209207] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1402.209213] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[ 1402.209224] [drm:intel_dump_pipe_config [i915]] crtc timings: 138780 1920 1966 1996 2080 1080 1082 1086 1112, type: 0x48 flags: 0xa
>[ 1402.209234] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 138780
>[ 1402.209245] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[ 1402.209255] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1402.209265] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1402.209276] [drm:intel_dump_pipe_config [i915]] dpll_hw_state: ctrl1: 0x3, cfgcr1: 0x0, cfgcr2: 0x0
>[ 1402.209285] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1402.209295] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 1A] disabled, scaler_id = -1
>[ 1402.209306] [drm:intel_dump_pipe_config [i915]] [PLANE:31:plane 2A] disabled, scaler_id = -1
>[ 1402.209316] [drm:intel_dump_pipe_config [i915]] [PLANE:34:cursor A] disabled, scaler_id = -1
>[ 1402.209328] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1402.209339] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[ 1402.209354] [drm:intel_find_shared_dpll [i915]] [CRTC:37:pipe A] allocated DPLL 0
>[ 1402.209366] [drm:intel_reference_shared_dpll [i915]] using DPLL 0 for pipe A
>[ 1402.210324] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1402.210334] [drm:intel_power_well_enable [i915]] enabling DC off
>[ 1402.210629] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[ 1402.210647] [drm:intel_atomic_commit_tail [i915]] [ENCODER:48:DDI A]
>[ 1402.210660] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI B]
>[ 1402.210673] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[ 1402.210686] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[ 1402.210698] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DDI C]
>[ 1402.210710] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST A]
>[ 1402.210722] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST B]
>[ 1402.210734] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI D]
>[ 1402.210746] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[ 1402.210758] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[ 1402.210771] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[ 1402.210784] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[ 1402.210796] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[ 1402.210808] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[ 1402.210821] [drm:intel_enable_shared_dpll [i915]] enable DPLL 0 (active 1, on? 0) for crtc 37
>[ 1402.210835] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 0
>[ 1402.210856] [drm:edp_panel_on [i915]] Turn eDP port A panel power on
>[ 1402.210897] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle
>[ 1402.716196] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 00000000 control 00000060
>[ 1402.716281] [drm:wait_panel_status [i915]] Wait complete
>[ 1402.716403] [drm:edp_panel_on [i915]] Wait for panel power on
>[ 1402.716521] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 00000063
>[ 1402.748489] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010
>[ 1402.748561] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[ 1402.748626] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1
>[ 1402.748720] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[ 1402.918388] [drm:wait_panel_status [i915]] Wait complete
>[ 1402.918455] [drm:intel_power_well_enable [i915]] enabling DDI A/E IO power well
>[ 1402.918558] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[ 1402.918718] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b
>[ 1402.919942] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1402.920028] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1402.920091] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1402.920158] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1402.920874] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1402.920928] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1402.921926] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1402.921981] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:49:eDP-1] Link Training Passed at Link Rate = 270000, Lane count = 2
>[ 1402.922618] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1402.922684] [drm:intel_edp_backlight_on [i915]] 
>[ 1402.922740] [drm:intel_panel_enable_backlight [i915]] pipe A
>[ 1402.922823] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 120000
>[ 1402.928082] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS
>[ 1403.442206] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 1403.442288] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 1403.442411] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[ 1403.442478] [drm:intel_power_well_enable [i915]] enabling power well 2
>[ 1403.703698] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 1403.703779] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 1406.172380] [drm:edp_panel_vdd_off_sync [i915]] Turning eDP port A VDD off
>[ 1406.172526] [drm:edp_panel_vdd_off_sync [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x00000067
>[ 1409.281260] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 1409.281341] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 1409.542344] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 1409.542424] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 1413.084213] [drm:drm_atomic_helper_wait_for_flip_done [drm_kms_helper]] *ERROR* [CRTC:37:pipe A] flip_done timed out
>[ 1413.084334] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:49:eDP-1]
>[ 1413.084417] [drm:intel_atomic_commit_tail [i915]] [CRTC:37:pipe A]
>[ 1413.084513] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[ 1413.085099] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 00 00 04 00 0f 00 04
>[ 1413.086507] [drm:intel_power_well_disable [i915]] disabling power well 2
>[ 1413.086564] [drm:intel_power_well_disable [i915]] disabling DC off
>[ 1413.086615] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[ 1413.086663] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[ 1413.086737] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[ 1413.086785] [drm:intel_power_well_enable [i915]] enabling DC off
>[ 1413.086833] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[ 1413.086884] [drm:intel_power_well_enable [i915]] enabling power well 2
>[ 1413.087376] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 00 00 04 00 0f 00 04
>[ 1413.088802] [drm:intel_power_well_disable [i915]] disabling power well 2
>[ 1413.088855] [drm:intel_power_well_disable [i915]] disabling DC off
>[ 1413.088905] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[ 1413.088952] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[ 1413.122611] [drm:intel_power_well_enable [i915]] enabling DC off
>[ 1413.122663] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[ 1413.122750] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[ 1413.122897] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006f
>[ 1413.322920] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped
>[ 1413.322970] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[ 1413.323001] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[ 1415.119182] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 1415.119264] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 1415.119382] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[ 1415.119449] [drm:intel_power_well_enable [i915]] enabling power well 2
>[ 1415.379561] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 1415.379642] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 1416.412291] [drm:edp_panel_vdd_off_sync [i915]] Turning eDP port A VDD off
>[ 1416.412436] [drm:edp_panel_vdd_off_sync [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x00000067
>[ 1420.950165] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 1420.950246] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 1421.210118] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 1421.210198] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 1423.580304] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [CRTC:37:pipe A] flip_done timed out
>[ 1426.783400] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 1426.783482] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 1427.044586] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 1427.044667] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 1432.616533] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 1432.616613] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 1432.879003] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 1432.879085] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 1433.820312] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [CONNECTOR:49:eDP-1] flip_done timed out
>[ 1438.446258] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 1438.446339] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 1438.704607] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 1438.704689] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 1444.059985] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [PLANE:28:plane 1A] flip_done timed out
>[ 1444.282136] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 1444.282217] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 1444.542607] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 1444.542688] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 1450.120338] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 1450.120419] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 1450.378591] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 1450.378672] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 1454.300313] [drm:drm_atomic_helper_wait_for_flip_done [drm_kms_helper]] *ERROR* [CRTC:37:pipe A] flip_done timed out
>[ 1454.300917] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 00 00 04 00 0f 00 04
>[ 1454.302325] [drm:intel_power_well_disable [i915]] disabling power well 2
>[ 1454.302382] [drm:intel_power_well_disable [i915]] disabling DC off
>[ 1454.302434] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[ 1454.302497] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[ 1454.302566] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[ 1454.302608] [drm:intel_power_well_enable [i915]] enabling DC off
>[ 1454.302650] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[ 1454.302697] [drm:intel_power_well_enable [i915]] enabling power well 2
>[ 1454.303171] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 00 00 04 00 0f 00 04
>[ 1454.304588] [drm:intel_power_well_disable [i915]] disabling power well 2
>[ 1454.304640] [drm:intel_power_well_disable [i915]] disabling DC off
>[ 1454.304689] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[ 1454.304736] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[ 1454.338791] [drm:intel_power_well_enable [i915]] enabling DC off
>[ 1454.338851] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[ 1454.338948] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[ 1454.339099] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006f
>[ 1454.538844] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped
>[ 1454.538887] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[ 1454.538917] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[ 1455.941643] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 1455.941724] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 1455.941843] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[ 1455.941910] [drm:intel_power_well_enable [i915]] enabling power well 2
>[ 1456.201953] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 1456.202034] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 1457.628367] [drm:edp_panel_vdd_off_sync [i915]] Turning eDP port A VDD off
>[ 1457.628513] [drm:edp_panel_vdd_off_sync [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x00000067
>[ 1461.763332] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 1461.763413] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 1462.023075] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 1462.023156] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 1464.796303] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [CRTC:37:pipe A] flip_done timed out
>[ 1467.590259] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 1467.590341] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 1467.850853] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 1467.850934] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 1473.426047] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 1473.426128] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 1473.687119] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 1473.687200] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 1475.036302] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [CONNECTOR:49:eDP-1] flip_done timed out
>[ 1479.258227] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 1479.258308] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 1479.518249] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 1479.518329] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 1485.078527] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 1485.078607] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 1485.276297] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [PLANE:28:plane 1A] flip_done timed out
>[ 1485.338211] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 1485.338293] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 1490.906426] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 1490.906507] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 1491.166360] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 1491.166442] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 1495.516028] [drm:drm_atomic_helper_wait_for_flip_done [drm_kms_helper]] *ERROR* [CRTC:37:pipe A] flip_done timed out
>[ 1495.516628] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 00 00 04 00 0f 00 04
>[ 1495.518032] [drm:intel_power_well_disable [i915]] disabling power well 2
>[ 1495.518089] [drm:intel_power_well_disable [i915]] disabling DC off
>[ 1495.518140] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[ 1495.518189] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[ 1495.518264] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[ 1495.518313] [drm:intel_power_well_enable [i915]] enabling DC off
>[ 1495.518361] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[ 1495.518412] [drm:intel_power_well_enable [i915]] enabling power well 2
>[ 1495.518898] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 00 00 04 00 0f 00 04
>[ 1495.520332] [drm:intel_power_well_disable [i915]] disabling power well 2
>[ 1495.520385] [drm:intel_power_well_disable [i915]] disabling DC off
>[ 1495.520435] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[ 1495.520484] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[ 1495.554513] [drm:intel_power_well_enable [i915]] enabling DC off
>[ 1495.554566] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[ 1495.554652] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[ 1495.554798] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006f
>[ 1495.754810] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped
>[ 1495.754860] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[ 1495.754891] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[ 1496.733590] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 1496.733671] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 1496.733791] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[ 1496.733858] [drm:intel_power_well_enable [i915]] enabling power well 2
>[ 1496.993397] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 1496.993478] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 1498.844286] [drm:edp_panel_vdd_off_sync [i915]] Turning eDP port A VDD off
>[ 1498.844432] [drm:edp_panel_vdd_off_sync [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x00000067
>[ 1502.565868] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 1502.565949] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 1502.825916] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 1502.825989] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 1506.012039] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [CRTC:37:pipe A] flip_done timed out
>[ 1508.396437] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 1508.396518] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 1508.657235] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 1508.657316] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 1514.230424] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 1514.230505] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 1514.493317] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 1514.493398] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 1516.252305] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [CONNECTOR:49:eDP-1] flip_done timed out
>[ 1520.062529] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 1520.062610] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 1520.325092] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 1520.325174] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 1525.900845] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 1525.900927] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 1526.160875] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 1526.160956] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 1526.492196] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [PLANE:28:plane 1A] flip_done timed out
>[ 1531.729893] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 1531.729974] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 1531.989833] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 1531.989913] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 1536.732307] [drm:drm_atomic_helper_wait_for_flip_done [drm_kms_helper]] *ERROR* [CRTC:37:pipe A] flip_done timed out
>[ 1536.732911] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 00 00 04 00 0f 00 04
>[ 1536.734321] [drm:intel_power_well_disable [i915]] disabling power well 2
>[ 1536.734378] [drm:intel_power_well_disable [i915]] disabling DC off
>[ 1536.734446] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[ 1536.734489] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[ 1536.734557] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[ 1536.734600] [drm:intel_power_well_enable [i915]] enabling DC off
>[ 1536.734642] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[ 1536.734689] [drm:intel_power_well_enable [i915]] enabling power well 2
>[ 1536.735164] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 00 00 04 00 0f 00 04
>[ 1536.736583] [drm:intel_power_well_disable [i915]] disabling power well 2
>[ 1536.736636] [drm:intel_power_well_disable [i915]] disabling DC off
>[ 1536.736685] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[ 1536.736733] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[ 1536.770477] [drm:intel_power_well_enable [i915]] enabling DC off
>[ 1536.770530] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[ 1536.770619] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[ 1536.770763] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006f
>[ 1536.970779] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped
>[ 1536.970911] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[ 1536.971005] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1536.971067] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[ 1537.562311] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 1537.562393] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 1537.562518] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[ 1537.562583] [drm:intel_power_well_enable [i915]] enabling power well 2
>[ 1537.822512] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 1537.822593] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 1540.060283] [drm:edp_panel_vdd_off_sync [i915]] Turning eDP port A VDD off
>[ 1540.060429] [drm:edp_panel_vdd_off_sync [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x00000067
>[ 1543.400223] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 1543.400305] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 1543.661079] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 1543.661160] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 1546.972157] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [CRTC:37:pipe A] flip_done timed out
>[ 1549.232841] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 1549.232922] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 1549.493341] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 1549.493423] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 1555.062577] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 1555.062658] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 1555.324811] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 1555.324893] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 1557.212295] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [CONNECTOR:49:eDP-1] flip_done timed out
>[ 1560.891872] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 1560.891953] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 1561.153492] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 1561.153572] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 1566.716560] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 1566.716642] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 1566.977318] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 1566.977399] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 1567.452305] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [PLANE:28:plane 1A] flip_done timed out
>[ 1567.452410] [drm:intel_edp_backlight_off [i915]] 
>[ 1567.660296] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0
>[ 1567.660436] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1567.671425] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[ 1567.671583] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b
>[ 1567.671856] [drm:intel_edp_panel_off.part.31 [i915]] Turn eDP port A panel power off
>[ 1567.671958] [drm:intel_edp_panel_off.part.31 [i915]] Wait for panel power off time
>[ 1567.672121] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000003 control 00000060
>[ 1567.724904] [drm:wait_panel_status [i915]] Wait complete
>[ 1567.724967] [drm:intel_power_well_disable [i915]] disabling DDI A/E IO power well
>[ 1567.725054] [drm:intel_disable_shared_dpll [i915]] disable DPLL 0 (active 1, on? 1) for crtc 37
>[ 1567.725128] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 0
>[ 1567.725220] [drm:intel_atomic_commit_tail [i915]] [ENCODER:48:DDI A]
>[ 1567.725291] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI B]
>[ 1567.725357] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[ 1567.725421] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[ 1567.725485] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DDI C]
>[ 1567.725547] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST A]
>[ 1567.725607] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST B]
>[ 1567.725667] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI D]
>[ 1567.725726] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[ 1567.725786] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[ 1567.725851] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:49:eDP-1]
>[ 1567.725918] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[ 1567.725982] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[ 1567.726045] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[ 1567.726106] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[ 1567.726182] [drm:intel_atomic_commit_tail [i915]] [CRTC:37:pipe A]
>[ 1567.726306] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[ 1567.726763] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 00 00 04 00 0f 00 04
>[ 1567.728214] [drm:intel_power_well_disable [i915]] disabling power well 2
>[ 1567.728240] [drm:intel_power_well_disable [i915]] disabling DC off
>[ 1567.728251] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[ 1567.728274] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[ 1567.728275] Setting dangerous option enable_psr - tainting kernel
>[ 1567.728285] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1567.728299] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[ 1567.728308] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1567.728317] [drm:intel_power_well_enable [i915]] enabling DC off
>[ 1567.729166] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[ 1567.729233] [drm:intel_power_well_enable [i915]] enabling power well 2
>[ 1567.729242] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[ 1567.729631] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 00 00 04 00 0f 00 04
>[ 1567.730883] [drm:intel_power_well_disable [i915]] disabling power well 2
>[ 1567.730890] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[ 1567.730901] [drm:intel_power_well_disable [i915]] disabling DC off
>[ 1567.730917] [drm:intel_atomic_check [i915]] [CONNECTOR:49:eDP-1] checking for sink bpp constrains
>[ 1567.730932] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1567.730939] [drm:drm_mode_debug_printmodeline [drm]] Modeline 52:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[ 1567.730948] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[ 1567.730958] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[ 1567.730972] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 138780KHz
>[ 1567.730983] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1567.730997] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24
>[ 1567.731010] [drm:intel_dp_compute_config [i915]] DP link bw required 416340 available 540000
>[ 1567.731024] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1567.731038] [drm:intel_dump_pipe_config [i915]] [CRTC:37:pipe A][modeset]
>[ 1567.731051] [drm:intel_dump_pipe_config [i915]] output_types: EDP (0x100)
>[ 1567.731063] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0
>[ 1567.731076] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 6467616, gmch_n: 8388608, link_m: 269484, link_n: 524288, tu: 64
>[ 1567.731087] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[ 1567.731098] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1567.731104] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[ 1567.731116] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1567.731122] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[ 1567.731134] [drm:intel_dump_pipe_config [i915]] crtc timings: 138780 1920 1966 1996 2080 1080 1082 1086 1112, type: 0x48 flags: 0xa
>[ 1567.731145] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 138780
>[ 1567.731157] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[ 1567.731168] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1567.731179] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1567.731190] [drm:intel_dump_pipe_config [i915]] dpll_hw_state: ctrl1: 0x3, cfgcr1: 0x0, cfgcr2: 0x0
>[ 1567.731201] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1567.731212] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 1A] disabled, scaler_id = -1
>[ 1567.731223] [drm:intel_dump_pipe_config [i915]] [PLANE:31:plane 2A] disabled, scaler_id = -1
>[ 1567.731233] [drm:intel_dump_pipe_config [i915]] [PLANE:34:cursor A] disabled, scaler_id = -1
>[ 1567.731247] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1567.731259] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[ 1567.731274] [drm:intel_find_shared_dpll [i915]] [CRTC:37:pipe A] allocated DPLL 0
>[ 1567.731286] [drm:intel_reference_shared_dpll [i915]] using DPLL 0 for pipe A
>[ 1567.731534] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010
>[ 1567.731548] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[ 1567.731561] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0
>[ 1567.731667] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1567.731680] [drm:intel_power_well_enable [i915]] enabling DC off
>[ 1567.731944] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[ 1567.731954] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[ 1567.731974] [drm:intel_atomic_commit_tail [i915]] [ENCODER:48:DDI A]
>[ 1567.731989] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI B]
>[ 1567.732003] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[ 1567.732032] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[ 1567.732044] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DDI C]
>[ 1567.732056] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST A]
>[ 1567.732067] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST B]
>[ 1567.732079] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI D]
>[ 1567.732090] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[ 1567.732119] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[ 1567.732133] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[ 1567.732147] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[ 1567.732160] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[ 1567.732173] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[ 1567.732189] [drm:intel_enable_shared_dpll [i915]] enable DPLL 0 (active 1, on? 0) for crtc 37
>[ 1567.732202] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 0
>[ 1567.732223] [drm:edp_panel_on [i915]] Turn eDP port A panel power on
>[ 1567.732250] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle
>[ 1568.348496] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 00000000 control 00000060
>[ 1568.348595] [drm:wait_panel_status [i915]] Wait complete
>[ 1568.348725] [drm:edp_panel_on [i915]] Wait for panel power on
>[ 1568.348847] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 00000063
>[ 1568.380651] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010
>[ 1568.380724] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[ 1568.380791] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1
>[ 1568.380893] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[ 1568.549699] [drm:wait_panel_status [i915]] Wait complete
>[ 1568.549765] [drm:intel_power_well_enable [i915]] enabling DDI A/E IO power well
>[ 1568.549867] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[ 1568.550018] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b
>[ 1568.551255] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1568.551328] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1568.551394] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1568.551458] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1568.552209] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1568.552272] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1568.553282] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1568.553344] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:49:eDP-1] Link Training Passed at Link Rate = 270000, Lane count = 2
>[ 1568.554001] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1568.554068] [drm:intel_edp_backlight_on [i915]] 
>[ 1568.554125] [drm:intel_panel_enable_backlight [i915]] pipe A
>[ 1568.554206] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 120000
>[ 1568.560250] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS
>[ 1571.804446] [drm:edp_panel_vdd_off_sync [i915]] Turning eDP port A VDD off
>[ 1571.804593] [drm:edp_panel_vdd_off_sync [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x00000067
>[ 1572.548557] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 1572.548638] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 1572.548762] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[ 1572.548826] [drm:intel_power_well_enable [i915]] enabling power well 2
>[ 1572.811030] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 1572.811111] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 1578.387451] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 1578.387533] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 1578.645484] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 1578.645566] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 1578.716166] [drm:drm_atomic_helper_wait_for_flip_done [drm_kms_helper]] *ERROR* [CRTC:37:pipe A] flip_done timed out
>[ 1578.716291] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:49:eDP-1]
>[ 1578.716374] [drm:intel_atomic_commit_tail [i915]] [CRTC:37:pipe A]
>[ 1578.716471] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[ 1578.717054] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 00 00 04 00 0f 00 04
>[ 1578.718463] [drm:intel_power_well_disable [i915]] disabling power well 2
>[ 1578.718519] [drm:intel_power_well_disable [i915]] disabling DC off
>[ 1578.718569] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[ 1578.718617] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[ 1578.718689] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[ 1578.718751] [drm:intel_power_well_enable [i915]] enabling DC off
>[ 1578.718793] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[ 1578.718839] [drm:intel_power_well_enable [i915]] enabling power well 2
>[ 1578.719311] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 00 00 04 00 0f 00 04
>[ 1578.720601] [drm:intel_power_well_disable [i915]] disabling power well 2
>[ 1578.720626] [drm:intel_power_well_disable [i915]] disabling DC off
>[ 1578.720636] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[ 1578.720644] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[ 1578.754005] [drm:intel_power_well_enable [i915]] enabling DC off
>[ 1578.754019] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[ 1578.754051] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[ 1578.754146] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006f
>[ 1578.954308] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped
>[ 1579.204297] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped
>[ 1579.454296] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped
>[ 1579.704294] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped
>[ 1579.954284] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped
>[ 1583.068287] [drm:edp_panel_vdd_off_sync [i915]] Turning eDP port A VDD off
>[ 1583.068432] [drm:edp_panel_vdd_off_sync [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x00000067
>[ 1583.068489] [drm:intel_power_well_disable [i915]] disabling DC off
>[ 1583.068546] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[ 1583.068599] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[ 1584.218338] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 1584.218420] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 1584.218545] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[ 1584.218612] [drm:intel_power_well_enable [i915]] enabling DC off
>[ 1584.218676] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[ 1584.218736] [drm:intel_power_well_enable [i915]] enabling power well 2
>[ 1584.479060] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 1584.479142] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 1589.980302] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [CRTC:37:pipe A] flip_done timed out
>[ 1590.048086] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 1590.048166] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 1590.308093] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 1590.308174] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 1595.876912] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 1595.876994] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 1596.137349] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 1596.137430] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 1600.220320] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [PLANE:28:plane 1A] flip_done timed out
>[ 1601.713811] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 1601.713892] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 1601.974295] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 1601.974376] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 1607.545177] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 1607.545258] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 1607.805414] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 1607.805495] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 1610.460189] [drm:drm_atomic_helper_wait_for_flip_done [drm_kms_helper]] *ERROR* [CRTC:37:pipe A] flip_done timed out
>[ 1610.460473] [IGT] kms_frontbuffer_tracking: exiting, ret=0
>[ 1610.460542] Setting dangerous option enable_psr - tainting kernel
>[ 1610.460557] Setting dangerous option enable_fbc - tainting kernel
>[ 1610.460804] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 00 00 04 00 0f 00 04
>[ 1610.462335] [drm:intel_power_well_disable [i915]] disabling power well 2
>[ 1610.462392] [drm:intel_power_well_disable [i915]] disabling DC off
>[ 1610.462444] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[ 1610.462492] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[ 1610.462570] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[ 1610.462619] [drm:intel_power_well_enable [i915]] enabling DC off
>[ 1610.462667] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[ 1610.462718] [drm:intel_power_well_enable [i915]] enabling power well 2
>[ 1610.463211] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 00 00 04 00 0f 00 04
>[ 1610.464642] [drm:intel_power_well_disable [i915]] disabling power well 2
>[ 1610.464695] [drm:intel_power_well_disable [i915]] disabling DC off
>[ 1610.464744] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[ 1610.464790] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[ 1610.508012] [drm:intel_atomic_check [i915]] [CONNECTOR:57:DP-1] checking for sink bpp constrains
>[ 1610.508029] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1610.508047] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 148500KHz
>[ 1610.508064] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 1610.508079] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 648000
>[ 1610.508094] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1610.508110] [drm:intel_dump_pipe_config [i915]] [CRTC:47:pipe B][modeset]
>[ 1610.508125] [drm:intel_dump_pipe_config [i915]] output_types: DP (0x80)
>[ 1610.508139] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 1610.508153] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5767168, gmch_n: 8388608, link_m: 240298, link_n: 262144, tu: 64
>[ 1610.508166] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[ 1610.508179] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1610.508188] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[ 1610.508202] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1610.508208] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[ 1610.508222] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[ 1610.508235] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1080, pixel rate 148500
>[ 1610.508248] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[ 1610.508261] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1610.508274] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1610.508287] [drm:intel_dump_pipe_config [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[ 1610.508299] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1610.508312] [drm:intel_dump_pipe_config [i915]] [PLANE:38:plane 1B] disabled, scaler_id = -1
>[ 1610.508324] [drm:intel_dump_pipe_config [i915]] [PLANE:41:plane 2B] disabled, scaler_id = -1
>[ 1610.508337] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor B] disabled, scaler_id = -1
>[ 1610.508352] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1610.508366] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[ 1610.508385] [drm:intel_find_shared_dpll [i915]] [CRTC:47:pipe B] allocated DPLL 1
>[ 1610.508399] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[ 1613.378196] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 1613.378278] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 1613.378394] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[ 1613.378460] [drm:intel_power_well_enable [i915]] enabling DC off
>[ 1613.378526] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[ 1613.378584] [drm:intel_power_well_enable [i915]] enabling power well 2
>[ 1613.638388] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 1613.638469] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 1619.200433] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 1619.200513] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 1619.461489] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 1619.461571] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 1620.700198] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [CRTC:37:pipe A] flip_done timed out
>[ 1625.030161] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 1625.030242] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 1625.292818] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 1625.292899] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 1630.862229] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 1630.862310] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 1630.940179] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [CONNECTOR:49:eDP-1] flip_done timed out
>[ 1631.120030] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 1631.120112] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 1636.686521] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 1636.686603] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 1636.945711] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 1636.945793] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 1641.180297] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [PLANE:28:plane 1A] flip_done timed out
>[ 1641.180389] [drm:intel_disable_sagv [i915]] Disabling the SAGV
>[ 1641.180474] [drm:intel_atomic_commit_tail [i915]] [ENCODER:48:DDI A]
>[ 1641.180549] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI B]
>[ 1641.180619] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[ 1641.180686] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[ 1641.180750] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DDI C]
>[ 1641.180812] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST A]
>[ 1641.180874] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST B]
>[ 1641.180935] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI D]
>[ 1641.180996] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[ 1641.181057] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[ 1641.181123] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[ 1641.181192] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[ 1641.181256] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[ 1641.181318] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[ 1641.181395] [drm:intel_fbc_enable [i915]] reserved 16588800 bytes of contiguous stolen space for FBC, threshold: 1
>[ 1641.181462] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 1641.186485] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 2, on? 0) for crtc 47
>[ 1641.186562] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[ 1641.186676] [drm:intel_power_well_enable [i915]] enabling DDI B IO power well
>[ 1641.187290] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 1641.188582] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 1641.189841] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 1641.191091] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 1641.192352] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 1641.193233] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[ 1641.194218] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1641.194278] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1641.194335] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1641.194391] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1641.213072] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1641.213101] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[ 1641.231837] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1641.232161] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:57:DP-1] Link Training Passed at Link Rate = 162000, Lane count = 4
>[ 1641.232545] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 1641.232611] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS
>[ 1642.519453] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 1642.519533] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 1642.782797] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 1642.782878] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 1651.420023] [drm:drm_atomic_helper_wait_for_flip_done [drm_kms_helper]] *ERROR* [CRTC:37:pipe A] flip_done timed out
>[ 1651.420157] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:57:DP-1]
>[ 1651.420243] [drm:intel_atomic_commit_tail [i915]] [CRTC:47:pipe B]
>[ 1651.420341] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[ 1651.420948] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 00 00 04 00 0f 00 04
>[ 1651.422402] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[ 1651.422882] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 00 00 04 00 0f 00 04
>[ 1651.469846] [IGT] kms_frontbuffer_tracking: executing
>[ 1651.526267] [drm:drm_mode_addfb2 [drm]] [FB:75]
>[ 1651.526310] [drm:drm_mode_addfb2 [drm]] [FB:91]
>[ 1651.526354] [drm:drm_mode_addfb2 [drm]] [FB:92]
>[ 1651.527173] [drm:drm_mode_addfb2 [drm]] [FB:93]
>[ 1651.535068] [drm:drm_mode_addfb2 [drm]] [FB:94]
>[ 1651.537044] [drm:drm_mode_addfb2 [drm]] [FB:96]
>[ 1651.537086] [drm:drm_mode_addfb2 [drm]] [FB:98]
>[ 1651.537135] [drm:drm_mode_addfb2 [drm]] [FB:102]
>[ 1651.537384] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[ 1651.537398] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[ 1661.660294] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [CRTC:37:pipe A] flip_done timed out
>[ 1671.900293] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [CONNECTOR:49:eDP-1] flip_done timed out
>[ 1682.140278] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [PLANE:28:plane 1A] flip_done timed out
>[ 1692.380295] [drm:drm_atomic_helper_wait_for_flip_done [drm_kms_helper]] *ERROR* [CRTC:37:pipe A] flip_done timed out
>[ 1692.380485] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[ 1692.380639] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006f
>[ 1692.568995] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped
>[ 1692.569229] [IGT] kms_frontbuffer_tracking: starting subtest psr-1p-offscren-pri-indfb-draw-mmap-wc
>[ 1692.569305] Setting dangerous option enable_fbc - tainting kernel
>[ 1692.569329] Setting dangerous option enable_psr - tainting kernel
>[ 1695.708378] [drm:edp_panel_vdd_off_sync [i915]] Turning eDP port A VDD off
>[ 1695.708523] [drm:edp_panel_vdd_off_sync [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x00000067
>[ 1702.620140] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [CRTC:37:pipe A] flip_done timed out
>[ 1712.860293] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [PLANE:28:plane 1A] flip_done timed out
>[ 1723.100186] [drm:drm_atomic_helper_wait_for_flip_done [drm_kms_helper]] *ERROR* [CRTC:37:pipe A] flip_done timed out
>[ 1723.104560] [drm:drm_mode_addfb2 [drm]] [FB:72]
>[ 1723.104660] [drm:drm_mode_addfb2 [drm]] [FB:75]
>[ 1723.104765] [drm:drm_mode_addfb2 [drm]] [FB:91]
>[ 1723.105780] [drm:drm_mode_addfb2 [drm]] [FB:92]
>[ 1723.109601] [drm:drm_mode_addfb2 [drm]] [FB:93]
>[ 1723.110441] [drm:drm_mode_addfb2 [drm]] [FB:94]
>[ 1723.110460] [drm:drm_mode_addfb2 [drm]] [FB:96]
>[ 1723.110480] [drm:drm_mode_addfb2 [drm]] [FB:98]
>[ 1723.110584] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[ 1723.110618] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1723.110632] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[ 1733.340184] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [CRTC:37:pipe A] flip_done timed out
>[ 1743.580287] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [CONNECTOR:49:eDP-1] flip_done timed out
>[ 1753.820246] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [PLANE:28:plane 1A] flip_done timed out
>[ 1753.820373] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[ 1753.820528] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006f
>[ 1753.820801] [drm:intel_edp_backlight_off [i915]] 
>[ 1754.028241] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0
>[ 1754.028380] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1754.037064] [drm:intel_edp_panel_off.part.31 [i915]] Turn eDP port A panel power off
>[ 1754.037176] [drm:intel_edp_panel_off.part.31 [i915]] Wait for panel power off time
>[ 1754.037308] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000002 control 00000060
>[ 1754.089887] [drm:wait_panel_status [i915]] Wait complete
>[ 1754.089950] [drm:intel_power_well_disable [i915]] disabling DDI A/E IO power well
>[ 1754.090032] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 1754.090111] [drm:intel_disable_shared_dpll [i915]] disable DPLL 0 (active 1, on? 1) for crtc 37
>[ 1754.090183] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 0
>[ 1754.090275] [drm:intel_atomic_commit_tail [i915]] [ENCODER:48:DDI A]
>[ 1754.090346] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI B]
>[ 1754.090412] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[ 1754.090476] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[ 1754.090538] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DDI C]
>[ 1754.090600] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST A]
>[ 1754.090661] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST B]
>[ 1754.090722] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI D]
>[ 1754.090782] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[ 1754.090841] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[ 1754.090908] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:49:eDP-1]
>[ 1754.090975] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[ 1754.091041] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[ 1754.091105] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[ 1754.091167] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[ 1754.096970] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010
>[ 1754.097051] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[ 1754.097126] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0
>[ 1754.097244] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[ 1754.099869] [drm:intel_atomic_commit_tail [i915]] [CRTC:37:pipe A]
>[ 1754.099939] [drm:intel_enable_sagv [i915]] Enabling the SAGV
>[ 1754.100076] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[ 1754.100182] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1754.100256] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[ 1754.100359] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 1754.117178] [drm:intel_power_well_disable [i915]] disabling DDI B IO power well
>[ 1754.117260] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 2, on? 1) for crtc 47
>[ 1754.117334] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[ 1754.117423] [drm:intel_atomic_commit_tail [i915]] [ENCODER:48:DDI A]
>[ 1754.117488] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI B]
>[ 1754.117555] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[ 1754.117616] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[ 1754.117676] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DDI C]
>[ 1754.117735] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST A]
>[ 1754.117793] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST B]
>[ 1754.117849] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI D]
>[ 1754.117905] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[ 1754.117960] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[ 1754.118023] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:57:DP-1]
>[ 1754.118085] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[ 1754.118146] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[ 1754.118206] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[ 1754.118264] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[ 1754.118323] [drm:intel_power_well_disable [i915]] disabling power well 2
>[ 1754.118394] [drm:intel_atomic_commit_tail [i915]] [CRTC:47:pipe B]
>[ 1754.118448] [drm:intel_power_well_disable [i915]] disabling DC off
>[ 1754.118500] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[ 1754.118549] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[ 1754.118987] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1754.123201] [drm:drm_mode_addfb2 [drm]] [FB:73]
>[ 1754.125232] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[ 1754.125239] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[ 1754.125261] [drm:intel_atomic_check [i915]] [CONNECTOR:49:eDP-1] checking for sink bpp constrains
>[ 1754.125275] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1754.125282] [drm:drm_mode_debug_printmodeline [drm]] Modeline 52:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[ 1754.125297] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 138780KHz
>[ 1754.125314] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24
>[ 1754.125327] [drm:intel_dp_compute_config [i915]] DP link bw required 416340 available 540000
>[ 1754.125340] [drm:intel_dp_compute_config [i915]] PSR disable by flag
>[ 1754.125354] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1754.125367] [drm:intel_dump_pipe_config [i915]] [CRTC:37:pipe A][modeset]
>[ 1754.125380] [drm:intel_dump_pipe_config [i915]] output_types: EDP (0x100)
>[ 1754.125392] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0
>[ 1754.125405] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 6467616, gmch_n: 8388608, link_m: 269484, link_n: 524288, tu: 64
>[ 1754.125417] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[ 1754.125428] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1754.125434] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[ 1754.125447] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1754.125452] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[ 1754.125465] [drm:intel_dump_pipe_config [i915]] crtc timings: 138780 1920 1966 1996 2080 1080 1082 1086 1112, type: 0x48 flags: 0xa
>[ 1754.125477] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 138780
>[ 1754.125488] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[ 1754.125500] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1754.125511] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1754.125523] [drm:intel_dump_pipe_config [i915]] dpll_hw_state: ctrl1: 0x3, cfgcr1: 0x0, cfgcr2: 0x0
>[ 1754.125534] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1754.125545] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 1A] disabled, scaler_id = -1
>[ 1754.125556] [drm:intel_dump_pipe_config [i915]] [PLANE:31:plane 2A] disabled, scaler_id = -1
>[ 1754.125567] [drm:intel_dump_pipe_config [i915]] [PLANE:34:cursor A] disabled, scaler_id = -1
>[ 1754.125581] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1754.125594] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[ 1754.125609] [drm:intel_find_shared_dpll [i915]] [CRTC:37:pipe A] allocated DPLL 0
>[ 1754.125622] [drm:intel_reference_shared_dpll [i915]] using DPLL 0 for pipe A
>[ 1754.126171] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1754.126182] [drm:intel_power_well_enable [i915]] enabling DC off
>[ 1754.126440] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[ 1754.126458] [drm:intel_atomic_commit_tail [i915]] [ENCODER:48:DDI A]
>[ 1754.126472] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI B]
>[ 1754.126485] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[ 1754.126497] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[ 1754.126510] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DDI C]
>[ 1754.126522] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST A]
>[ 1754.126534] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST B]
>[ 1754.126545] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI D]
>[ 1754.126557] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[ 1754.126569] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[ 1754.126582] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[ 1754.126595] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[ 1754.126608] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[ 1754.126620] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[ 1754.126635] [drm:intel_enable_shared_dpll [i915]] enable DPLL 0 (active 1, on? 0) for crtc 37
>[ 1754.126648] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 0
>[ 1754.126668] [drm:edp_panel_on [i915]] Turn eDP port A panel power on
>[ 1754.126694] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle
>[ 1754.716491] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 00000000 control 00000060
>[ 1754.716599] [drm:wait_panel_status [i915]] Wait complete
>[ 1754.716738] [drm:edp_panel_on [i915]] Wait for panel power on
>[ 1754.716873] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 00000063
>[ 1754.750547] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010
>[ 1754.750629] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[ 1754.750705] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1
>[ 1754.750845] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[ 1754.917074] [drm:wait_panel_status [i915]] Wait complete
>[ 1754.917140] [drm:intel_power_well_enable [i915]] enabling DDI A/E IO power well
>[ 1754.917243] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[ 1754.917392] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b
>[ 1754.918578] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1754.918640] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1754.918699] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1754.918758] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1754.919469] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1754.919526] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1754.920476] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1754.920501] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:49:eDP-1] Link Training Passed at Link Rate = 270000, Lane count = 2
>[ 1754.920896] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1754.920913] [drm:intel_edp_backlight_on [i915]] 
>[ 1754.920925] [drm:intel_panel_enable_backlight [i915]] pipe A
>[ 1754.920978] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 120000
>[ 1754.928066] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS
>[ 1758.172126] [drm:edp_panel_vdd_off_sync [i915]] Turning eDP port A VDD off
>[ 1758.172271] [drm:edp_panel_vdd_off_sync [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x00000067
>[ 1765.084296] [drm:drm_atomic_helper_wait_for_flip_done [drm_kms_helper]] *ERROR* [CRTC:37:pipe A] flip_done timed out
>[ 1765.084416] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:49:eDP-1]
>[ 1765.084501] [drm:intel_atomic_commit_tail [i915]] [CRTC:37:pipe A]
>[ 1765.084599] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[ 1765.084663] [drm:intel_power_well_disable [i915]] disabling DC off
>[ 1765.084718] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[ 1765.084771] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[ 1765.121233] [drm:intel_power_well_enable [i915]] enabling DC off
>[ 1765.121293] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[ 1765.121389] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[ 1765.121543] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006f
>[ 1765.321198] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped
>[ 1765.321281] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[ 1765.321375] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1765.321436] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[ 1768.412379] [drm:edp_panel_vdd_off_sync [i915]] Turning eDP port A VDD off
>[ 1768.412524] [drm:edp_panel_vdd_off_sync [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x00000067
>[ 1768.412581] [drm:intel_power_well_disable [i915]] disabling DC off
>[ 1768.412638] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[ 1768.412692] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[ 1774.842649] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 1774.842731] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 1774.842854] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[ 1774.842919] [drm:intel_power_well_enable [i915]] enabling DC off
>[ 1774.842984] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[ 1774.843042] [drm:intel_power_well_enable [i915]] enabling power well 2
>[ 1775.125516] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 1775.125597] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 1775.324166] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [CRTC:37:pipe A] flip_done timed out
>[ 1779.886359] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 1779.886440] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 1780.155710] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 1780.155792] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 1785.564294] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [CONNECTOR:49:eDP-1] flip_done timed out
>[ 1785.729324] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 1785.729406] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 1785.998614] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 1785.998696] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 1791.558122] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 1791.558203] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 1791.827313] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 1791.827396] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 1795.803980] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [PLANE:28:plane 1A] flip_done timed out
>[ 1795.804085] [drm:intel_edp_backlight_off [i915]] 
>[ 1796.012360] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0
>[ 1796.012494] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1796.020725] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[ 1796.020883] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b
>[ 1796.021156] [drm:intel_edp_panel_off.part.31 [i915]] Turn eDP port A panel power off
>[ 1796.021259] [drm:intel_edp_panel_off.part.31 [i915]] Wait for panel power off time
>[ 1796.021386] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000003 control 00000060
>[ 1796.074115] [drm:wait_panel_status [i915]] Wait complete
>[ 1796.074178] [drm:intel_power_well_disable [i915]] disabling DDI A/E IO power well
>[ 1796.074265] [drm:intel_disable_shared_dpll [i915]] disable DPLL 0 (active 1, on? 1) for crtc 37
>[ 1796.074340] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 0
>[ 1796.074432] [drm:intel_atomic_commit_tail [i915]] [ENCODER:48:DDI A]
>[ 1796.074502] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI B]
>[ 1796.074568] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[ 1796.074632] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[ 1796.074695] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DDI C]
>[ 1796.074755] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST A]
>[ 1796.074815] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST B]
>[ 1796.074875] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI D]
>[ 1796.074934] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[ 1796.074992] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[ 1796.075059] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:49:eDP-1]
>[ 1796.075126] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[ 1796.075191] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[ 1796.075254] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[ 1796.075316] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[ 1796.075393] [drm:intel_atomic_commit_tail [i915]] [CRTC:37:pipe A]
>[ 1796.075515] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[ 1796.075987] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 00 00 04 00 0f 00 04
>[ 1796.080847] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010
>[ 1796.080866] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[ 1796.080883] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0
>[ 1796.104599] [drm:intel_power_well_disable [i915]] disabling power well 2
>[ 1796.104618] [drm:intel_power_well_disable [i915]] disabling DC off
>[ 1796.104633] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[ 1796.104647] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[ 1796.104662] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1796.104684] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[ 1796.104704] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[ 1796.104718] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1796.104731] [drm:intel_power_well_enable [i915]] enabling DC off
>[ 1796.105052] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[ 1796.105068] [drm:intel_power_well_enable [i915]] enabling power well 2
>[ 1796.105481] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 00 00 04 00 0f 00 04
>[ 1796.106124] [drm:drm_mode_addfb2 [drm]] [FB:73]
>[ 1796.106757] [drm:intel_power_well_disable [i915]] disabling power well 2
>[ 1796.106775] [drm:intel_power_well_disable [i915]] disabling DC off
>[ 1796.106792] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[ 1796.106807] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[ 1796.106824] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1796.107548] [drm:drm_mode_addfb2 [drm]] [FB:102]
>[ 1796.109249] [drm:drm_mode_addfb2 [drm]] [FB:103]
>[ 1796.110623] [drm:drm_mode_addfb2 [drm]] [FB:104]
>[ 1796.193074] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[ 1796.193081] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[ 1796.193107] [drm:intel_atomic_check [i915]] [CONNECTOR:49:eDP-1] checking for sink bpp constrains
>[ 1796.193121] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1796.193127] [drm:drm_mode_debug_printmodeline [drm]] Modeline 52:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[ 1796.193141] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 138780KHz
>[ 1796.193157] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24
>[ 1796.193169] [drm:intel_dp_compute_config [i915]] DP link bw required 416340 available 540000
>[ 1796.193181] [drm:intel_dp_compute_config [i915]] PSR disable by flag
>[ 1796.193193] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1796.193206] [drm:intel_dump_pipe_config [i915]] [CRTC:37:pipe A][modeset]
>[ 1796.193218] [drm:intel_dump_pipe_config [i915]] output_types: EDP (0x100)
>[ 1796.193230] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0
>[ 1796.193241] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 6467616, gmch_n: 8388608, link_m: 269484, link_n: 524288, tu: 64
>[ 1796.193252] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[ 1796.193263] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1796.193268] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[ 1796.193279] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1796.193284] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[ 1796.193296] [drm:intel_dump_pipe_config [i915]] crtc timings: 138780 1920 1966 1996 2080 1080 1082 1086 1112, type: 0x48 flags: 0xa
>[ 1796.193307] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 138780
>[ 1796.193317] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[ 1796.193328] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1796.193338] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1796.193349] [drm:intel_dump_pipe_config [i915]] dpll_hw_state: ctrl1: 0x3, cfgcr1: 0x0, cfgcr2: 0x0
>[ 1796.193359] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1796.193370] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 1A] disabled, scaler_id = -1
>[ 1796.193380] [drm:intel_dump_pipe_config [i915]] [PLANE:31:plane 2A] disabled, scaler_id = -1
>[ 1796.193391] [drm:intel_dump_pipe_config [i915]] [PLANE:34:cursor A] disabled, scaler_id = -1
>[ 1796.193404] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1796.193415] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[ 1796.193430] [drm:intel_find_shared_dpll [i915]] [CRTC:37:pipe A] allocated DPLL 0
>[ 1796.193442] [drm:intel_reference_shared_dpll [i915]] using DPLL 0 for pipe A
>[ 1796.194400] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1796.194409] [drm:intel_power_well_enable [i915]] enabling DC off
>[ 1796.194704] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[ 1796.194722] [drm:intel_atomic_commit_tail [i915]] [ENCODER:48:DDI A]
>[ 1796.194735] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI B]
>[ 1796.194749] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[ 1796.194761] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[ 1796.194774] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DDI C]
>[ 1796.194804] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST A]
>[ 1796.194815] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST B]
>[ 1796.194826] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI D]
>[ 1796.194839] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[ 1796.194850] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[ 1796.194880] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[ 1796.194909] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[ 1796.194920] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[ 1796.194932] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[ 1796.194945] [drm:intel_enable_shared_dpll [i915]] enable DPLL 0 (active 1, on? 0) for crtc 37
>[ 1796.194956] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 0
>[ 1796.194975] [drm:edp_panel_on [i915]] Turn eDP port A panel power on
>[ 1796.194999] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle
>[ 1796.700469] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 00000000 control 00000060
>[ 1796.700569] [drm:wait_panel_status [i915]] Wait complete
>[ 1796.700701] [drm:edp_panel_on [i915]] Wait for panel power on
>[ 1796.700827] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 00000063
>[ 1796.734367] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010
>[ 1796.734439] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[ 1796.734505] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1
>[ 1796.734605] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[ 1796.903180] [drm:wait_panel_status [i915]] Wait complete
>[ 1796.903246] [drm:intel_power_well_enable [i915]] enabling DDI A/E IO power well
>[ 1796.903349] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[ 1796.903501] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b
>[ 1796.904739] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1796.904813] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1796.904879] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1796.904944] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1796.905662] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1796.905722] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1796.906749] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1796.906804] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:49:eDP-1] Link Training Passed at Link Rate = 270000, Lane count = 2
>[ 1796.907440] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1796.907505] [drm:intel_edp_backlight_on [i915]] 
>[ 1796.907561] [drm:intel_panel_enable_backlight [i915]] pipe A
>[ 1796.907644] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 120000
>[ 1796.912061] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS
>[ 1797.383550] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 1797.383631] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 1797.383755] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[ 1797.383821] [drm:intel_power_well_enable [i915]] enabling power well 2
>[ 1797.645667] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 1797.645748] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 1800.156376] [drm:edp_panel_vdd_off_sync [i915]] Turning eDP port A VDD off
>[ 1800.156522] [drm:edp_panel_vdd_off_sync [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x00000067
>[ 1803.219351] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 1803.219432] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 1803.479207] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 1803.479287] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 1807.068195] [drm:drm_atomic_helper_wait_for_flip_done [drm_kms_helper]] *ERROR* [CRTC:37:pipe A] flip_done timed out
>[ 1807.068318] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:49:eDP-1]
>[ 1807.068401] [drm:intel_atomic_commit_tail [i915]] [CRTC:37:pipe A]
>[ 1807.068498] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[ 1807.069083] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 00 00 04 00 0f 00 04
>[ 1807.070486] [drm:intel_power_well_disable [i915]] disabling power well 2
>[ 1807.070536] [drm:intel_power_well_disable [i915]] disabling DC off
>[ 1807.070581] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[ 1807.070624] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[ 1807.070689] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[ 1807.070732] [drm:intel_power_well_enable [i915]] enabling DC off
>[ 1807.070774] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[ 1807.070820] [drm:intel_power_well_enable [i915]] enabling power well 2
>[ 1807.071294] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 00 00 04 00 0f 00 04
>[ 1807.072715] [drm:intel_power_well_disable [i915]] disabling power well 2
>[ 1807.072767] [drm:intel_power_well_disable [i915]] disabling DC off
>[ 1807.072816] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[ 1807.072863] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[ 1807.107657] [drm:intel_power_well_enable [i915]] enabling DC off
>[ 1807.107717] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[ 1807.107814] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[ 1807.107969] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006f
>[ 1807.307712] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped
>[ 1807.307756] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[ 1807.307786] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[ 1809.052187] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 1809.052268] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 1809.052388] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[ 1809.052455] [drm:intel_power_well_enable [i915]] enabling power well 2
>[ 1809.312988] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 1809.313070] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 1810.396260] [drm:edp_panel_vdd_off_sync [i915]] Turning eDP port A VDD off
>[ 1810.396407] [drm:edp_panel_vdd_off_sync [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x00000067
>[ 1814.888386] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 1814.888467] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 1815.146980] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 1815.147062] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 1817.564172] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [CRTC:37:pipe A] flip_done timed out
>[ 1820.714779] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 1820.714860] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 1820.976331] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 1820.976413] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 1826.550284] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 1826.550366] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 1826.810053] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 1826.810134] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 1827.804299] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [CONNECTOR:49:eDP-1] flip_done timed out
>[ 1832.386145] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 1832.386226] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 1832.644758] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 1832.644839] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 1838.044170] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [PLANE:28:plane 1A] flip_done timed out
>[ 1838.220147] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 1838.220229] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 1838.481117] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 1838.481199] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 1844.058818] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 1844.058900] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 1844.317418] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 1844.317500] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 1848.284188] [drm:drm_atomic_helper_wait_for_flip_done [drm_kms_helper]] *ERROR* [CRTC:37:pipe A] flip_done timed out
>[ 1848.284789] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 00 00 04 00 0f 00 04
>[ 1848.286194] [drm:intel_power_well_disable [i915]] disabling power well 2
>[ 1848.286251] [drm:intel_power_well_disable [i915]] disabling DC off
>[ 1848.286318] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[ 1848.286361] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[ 1848.286429] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[ 1848.286471] [drm:intel_power_well_enable [i915]] enabling DC off
>[ 1848.286514] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[ 1848.286560] [drm:intel_power_well_enable [i915]] enabling power well 2
>[ 1848.287034] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 00 00 04 00 0f 00 04
>[ 1848.288445] [drm:intel_power_well_disable [i915]] disabling power well 2
>[ 1848.288498] [drm:intel_power_well_disable [i915]] disabling DC off
>[ 1848.288547] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[ 1848.288596] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[ 1848.323606] [drm:intel_power_well_enable [i915]] enabling DC off
>[ 1848.323666] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[ 1848.323763] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[ 1848.323915] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006f
>[ 1848.523702] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped
>[ 1848.523752] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[ 1848.523783] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[ 1849.889417] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 1849.889498] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 1849.889619] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[ 1849.889685] [drm:intel_power_well_enable [i915]] enabling power well 2
>[ 1850.150853] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 1850.150933] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 1851.612260] [drm:edp_panel_vdd_off_sync [i915]] Turning eDP port A VDD off
>[ 1851.612405] [drm:edp_panel_vdd_off_sync [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x00000067
>[ 1855.720499] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 1855.720580] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 1855.979349] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 1855.979430] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 1858.780290] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [CRTC:37:pipe A] flip_done timed out
>[ 1861.548644] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 1861.548725] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 1861.810133] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 1861.810215] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 1867.380303] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 1867.380384] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 1867.642314] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 1867.642395] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 1869.020287] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [CONNECTOR:49:eDP-1] flip_done timed out
>[ 1873.214915] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 1873.214998] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 1873.475433] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 1873.475514] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 1879.052063] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 1879.052145] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 1879.260168] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [PLANE:28:plane 1A] flip_done timed out
>[ 1879.310909] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 1879.310990] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 1884.884271] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 1884.884354] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 1885.145713] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 1885.145795] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 1889.500164] [drm:drm_atomic_helper_wait_for_flip_done [drm_kms_helper]] *ERROR* [CRTC:37:pipe A] flip_done timed out
>[ 1889.500763] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 00 00 04 00 0f 00 04
>[ 1889.502168] [drm:intel_power_well_disable [i915]] disabling power well 2
>[ 1889.502226] [drm:intel_power_well_disable [i915]] disabling DC off
>[ 1889.502294] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[ 1889.502338] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[ 1889.502406] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[ 1889.502449] [drm:intel_power_well_enable [i915]] enabling DC off
>[ 1889.502491] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[ 1889.502538] [drm:intel_power_well_enable [i915]] enabling power well 2
>[ 1889.503013] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 00 00 04 00 0f 00 04
>[ 1889.504303] [drm:intel_power_well_disable [i915]] disabling power well 2
>[ 1889.504314] [drm:intel_power_well_disable [i915]] disabling DC off
>[ 1889.504338] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[ 1889.504348] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[ 1889.539246] [drm:intel_power_well_enable [i915]] enabling DC off
>[ 1889.539266] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[ 1889.539309] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[ 1889.539428] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006f
>[ 1889.739630] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped
>[ 1889.739673] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[ 1889.739702] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[ 1890.707638] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 1890.707720] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 1890.707840] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[ 1890.707906] [drm:intel_power_well_enable [i915]] enabling power well 2
>[ 1890.968767] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 1890.968850] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 1892.828266] [drm:edp_panel_vdd_off_sync [i915]] Turning eDP port A VDD off
>[ 1892.828414] [drm:edp_panel_vdd_off_sync [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x00000067
>[ 1896.540129] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 1896.540211] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 1896.801691] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 1896.801773] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 1899.996286] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [CRTC:37:pipe A] flip_done timed out
>[ 1902.371784] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 1902.371866] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 1902.633634] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 1902.633715] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 1908.201139] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 1908.201220] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 1908.460341] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 1908.460423] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 1910.236185] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [CONNECTOR:49:eDP-1] flip_done timed out
>[ 1914.025606] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 1914.025687] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 1914.285900] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 1914.285980] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 1919.857347] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 1919.857428] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 1920.118342] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 1920.118423] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 1920.476177] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [PLANE:28:plane 1A] flip_done timed out
>[ 1925.686440] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 1925.686522] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 1925.948279] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 1925.948360] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 1930.716183] [drm:drm_atomic_helper_wait_for_flip_done [drm_kms_helper]] *ERROR* [CRTC:37:pipe A] flip_done timed out
>[ 1930.716782] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 00 00 04 00 0f 00 04
>[ 1930.718193] [drm:intel_power_well_disable [i915]] disabling power well 2
>[ 1930.718250] [drm:intel_power_well_disable [i915]] disabling DC off
>[ 1930.718315] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[ 1930.718358] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[ 1930.718425] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[ 1930.718467] [drm:intel_power_well_enable [i915]] enabling DC off
>[ 1930.718509] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[ 1930.718555] [drm:intel_power_well_enable [i915]] enabling power well 2
>[ 1930.719029] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 00 00 04 00 0f 00 04
>[ 1930.720439] [drm:intel_power_well_disable [i915]] disabling power well 2
>[ 1930.720493] [drm:intel_power_well_disable [i915]] disabling DC off
>[ 1930.720541] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[ 1930.720590] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[ 1930.755298] [drm:intel_power_well_enable [i915]] enabling DC off
>[ 1930.755350] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[ 1930.755437] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[ 1930.755581] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006f
>[ 1930.955587] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped
>[ 1930.955716] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[ 1930.955811] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1930.955872] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[ 1931.523742] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 1931.523824] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 1931.523943] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[ 1931.524025] [drm:intel_power_well_enable [i915]] enabling power well 2
>[ 1931.783655] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 1931.783737] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 1934.044260] [drm:edp_panel_vdd_off_sync [i915]] Turning eDP port A VDD off
>[ 1934.044406] [drm:edp_panel_vdd_off_sync [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x00000067
>[ 1937.348459] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 1937.348541] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 1937.607372] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 1937.607454] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 1941.212149] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [CRTC:37:pipe A] flip_done timed out
>[ 1943.185558] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 1943.185640] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 1943.445202] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 1943.445283] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 1949.004087] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 1949.004167] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 1949.267050] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 1949.267131] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 1951.452281] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [CONNECTOR:49:eDP-1] flip_done timed out
>[ 1954.839871] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 1954.839953] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 1955.100731] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 1955.100813] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 1960.675267] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 1960.675349] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 1960.933936] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 1960.934016] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 1961.692163] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [PLANE:28:plane 1A] flip_done timed out
>[ 1961.692270] [drm:intel_edp_backlight_off [i915]] 
>[ 1961.900248] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0
>[ 1961.900388] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 1961.905853] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[ 1961.906012] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b
>[ 1961.906285] [drm:intel_edp_panel_off.part.31 [i915]] Turn eDP port A panel power off
>[ 1961.906387] [drm:intel_edp_panel_off.part.31 [i915]] Wait for panel power off time
>[ 1961.906513] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000002 control 00000060
>[ 1961.956967] [drm:wait_panel_status [i915]] Wait complete
>[ 1961.957023] [drm:intel_power_well_disable [i915]] disabling DDI A/E IO power well
>[ 1961.957100] [drm:intel_disable_shared_dpll [i915]] disable DPLL 0 (active 1, on? 1) for crtc 37
>[ 1961.957168] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 0
>[ 1961.957252] [drm:intel_atomic_commit_tail [i915]] [ENCODER:48:DDI A]
>[ 1961.957315] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI B]
>[ 1961.957375] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[ 1961.957431] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[ 1961.957487] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DDI C]
>[ 1961.957542] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST A]
>[ 1961.957595] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST B]
>[ 1961.957649] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI D]
>[ 1961.957703] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[ 1961.957756] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[ 1961.957815] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:49:eDP-1]
>[ 1961.957875] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[ 1961.957934] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[ 1961.957991] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[ 1961.958046] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[ 1961.958116] [drm:intel_atomic_commit_tail [i915]] [CRTC:37:pipe A]
>[ 1961.958225] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[ 1961.958622] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 00 00 04 00 0f 00 04
>[ 1961.960038] [drm:intel_power_well_disable [i915]] disabling power well 2
>[ 1961.960093] [drm:intel_power_well_disable [i915]] disabling DC off
>[ 1961.960144] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[ 1961.960148] Setting dangerous option enable_psr - tainting kernel
>[ 1961.960194] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[ 1961.961122] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 1961.961203] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[ 1961.961247] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 1961.961276] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[ 1961.961319] [drm:intel_power_well_enable [i915]] enabling DC off
>[ 1961.961340] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[ 1961.961433] [drm:intel_atomic_check [i915]] [CONNECTOR:49:eDP-1] checking for sink bpp constrains
>[ 1961.961498] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 1961.961528] [drm:drm_mode_debug_printmodeline [drm]] Modeline 52:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[ 1961.961592] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 138780KHz
>[ 1961.961634] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[ 1961.961680] [drm:intel_power_well_enable [i915]] enabling power well 2
>[ 1961.961740] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24
>[ 1961.961797] [drm:intel_dp_compute_config [i915]] DP link bw required 416340 available 540000
>[ 1961.961860] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 1961.961920] [drm:intel_dump_pipe_config [i915]] [CRTC:37:pipe A][modeset]
>[ 1961.961977] [drm:intel_dump_pipe_config [i915]] output_types: EDP (0x100)
>[ 1961.962031] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0
>[ 1961.962087] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 6467616, gmch_n: 8388608, link_m: 269484, link_n: 524288, tu: 64
>[ 1961.962139] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[ 1961.962190] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 1961.962218] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[ 1961.962229] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 1961.962235] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[ 1961.962246] [drm:intel_dump_pipe_config [i915]] crtc timings: 138780 1920 1966 1996 2080 1080 1082 1086 1112, type: 0x48 flags: 0xa
>[ 1961.962257] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 138780
>[ 1961.962268] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[ 1961.962278] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 1961.962289] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 1961.962299] [drm:intel_dump_pipe_config [i915]] dpll_hw_state: ctrl1: 0x3, cfgcr1: 0x0, cfgcr2: 0x0
>[ 1961.962310] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 1961.962320] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 1A] disabled, scaler_id = -1
>[ 1961.962331] [drm:intel_dump_pipe_config [i915]] [PLANE:31:plane 2A] disabled, scaler_id = -1
>[ 1961.962341] [drm:intel_dump_pipe_config [i915]] [PLANE:34:cursor A] disabled, scaler_id = -1
>[ 1961.962354] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 1961.962365] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[ 1961.962380] [drm:intel_find_shared_dpll [i915]] [CRTC:37:pipe A] allocated DPLL 0
>[ 1961.962392] [drm:intel_reference_shared_dpll [i915]] using DPLL 0 for pipe A
>[ 1961.963370] [drm:intel_atomic_commit_tail [i915]] [ENCODER:48:DDI A]
>[ 1961.963385] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI B]
>[ 1961.963398] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[ 1961.963411] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[ 1961.963423] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DDI C]
>[ 1961.963435] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST A]
>[ 1961.963447] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST B]
>[ 1961.963459] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI D]
>[ 1961.963470] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[ 1961.963482] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[ 1961.963494] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[ 1961.963507] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[ 1961.963520] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[ 1961.963532] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[ 1961.963546] [drm:intel_enable_shared_dpll [i915]] enable DPLL 0 (active 1, on? 0) for crtc 37
>[ 1961.963559] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 0
>[ 1961.963578] [drm:edp_panel_on [i915]] Turn eDP port A panel power on
>[ 1961.963603] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle
>[ 1961.965962] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010
>[ 1961.965977] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[ 1961.965991] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0
>[ 1962.588379] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 00000000 control 00000060
>[ 1962.588477] [drm:wait_panel_status [i915]] Wait complete
>[ 1962.588608] [drm:edp_panel_on [i915]] Wait for panel power on
>[ 1962.588730] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 00000063
>[ 1962.622413] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010
>[ 1962.622487] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[ 1962.622554] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1
>[ 1962.791274] [drm:wait_panel_status [i915]] Wait complete
>[ 1962.791339] [drm:intel_power_well_enable [i915]] enabling DDI A/E IO power well
>[ 1962.791442] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[ 1962.791591] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b
>[ 1962.792795] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 1962.792859] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 1962.792920] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 1962.792981] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 1962.793690] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 1962.793748] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 1962.794712] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 1962.794738] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:49:eDP-1] Link Training Passed at Link Rate = 270000, Lane count = 2
>[ 1962.795116] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 1962.795150] [drm:intel_edp_backlight_on [i915]] 
>[ 1962.795162] [drm:intel_panel_enable_backlight [i915]] pipe A
>[ 1962.795201] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 120000
>[ 1962.800221] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS
>[ 1966.044270] [drm:edp_panel_vdd_off_sync [i915]] Turning eDP port A VDD off
>[ 1966.044418] [drm:edp_panel_vdd_off_sync [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x00000067
>[ 1966.495850] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 1966.495932] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 1966.757261] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 1966.757342] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 1972.328058] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 1972.328140] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 1972.587912] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 1972.587994] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 1972.956182] [drm:drm_atomic_helper_wait_for_flip_done [drm_kms_helper]] *ERROR* [CRTC:37:pipe A] flip_done timed out
>[ 1972.956307] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:49:eDP-1]
>[ 1972.956390] [drm:intel_atomic_commit_tail [i915]] [CRTC:37:pipe A]
>[ 1972.956488] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[ 1972.957069] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 00 00 04 00 0f 00 04
>[ 1972.958474] [drm:intel_power_well_disable [i915]] disabling power well 2
>[ 1972.958530] [drm:intel_power_well_disable [i915]] disabling DC off
>[ 1972.958581] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[ 1972.958629] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[ 1972.958702] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[ 1972.958767] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[ 1972.958815] [drm:intel_power_well_enable [i915]] enabling DC off
>[ 1972.958862] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[ 1972.958914] [drm:intel_power_well_enable [i915]] enabling power well 2
>[ 1972.959386] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 00 00 04 00 0f 00 04
>[ 1972.960784] [drm:intel_power_well_disable [i915]] disabling power well 2
>[ 1972.960836] [drm:intel_power_well_disable [i915]] disabling DC off
>[ 1972.960885] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[ 1972.960932] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[ 1972.995137] [drm:intel_power_well_enable [i915]] enabling DC off
>[ 1972.995189] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[ 1972.995276] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[ 1972.995423] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006f
>[ 1973.195418] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped
>[ 1973.445418] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped
>[ 1973.695417] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped
>[ 1973.945415] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped
>[ 1974.195407] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped
>[ 1977.308251] [drm:edp_panel_vdd_off_sync [i915]] Turning eDP port A VDD off
>[ 1977.308397] [drm:edp_panel_vdd_off_sync [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x00000067
>[ 1977.308455] [drm:intel_power_well_disable [i915]] disabling DC off
>[ 1977.308511] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[ 1977.308564] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[ 1978.160692] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 1978.160773] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 1978.160901] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[ 1978.160967] [drm:intel_power_well_enable [i915]] enabling DC off
>[ 1978.161029] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[ 1978.161089] [drm:intel_power_well_enable [i915]] enabling power well 2
>[ 1978.422278] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 1978.422359] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 1983.993027] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 1983.993108] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 1984.220001] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [CRTC:37:pipe A] flip_done timed out
>[ 1984.254610] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 1984.254691] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 1989.825231] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 1989.825312] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 1990.086367] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 1990.086449] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 1994.460177] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [PLANE:28:plane 1A] flip_done timed out
>[ 1995.655524] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 1995.655597] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 1995.916509] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 1995.916590] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 2001.491787] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 2001.491868] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 2001.752931] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 2001.753012] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 2004.700136] [drm:drm_atomic_helper_wait_for_flip_done [drm_kms_helper]] *ERROR* [CRTC:37:pipe A] flip_done timed out
>[ 2004.700421] [IGT] kms_frontbuffer_tracking: exiting, ret=0
>[ 2004.700491] Setting dangerous option enable_psr - tainting kernel
>[ 2004.700506] Setting dangerous option enable_fbc - tainting kernel
>[ 2004.700740] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 00 00 04 00 0f 00 04
>[ 2004.702314] [drm:intel_power_well_disable [i915]] disabling power well 2
>[ 2004.702373] [drm:intel_power_well_disable [i915]] disabling DC off
>[ 2004.702424] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[ 2004.702473] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[ 2004.702549] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[ 2004.702596] [drm:intel_power_well_enable [i915]] enabling DC off
>[ 2004.702644] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[ 2004.702696] [drm:intel_power_well_enable [i915]] enabling power well 2
>[ 2004.703182] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 00 00 04 00 0f 00 04
>[ 2004.704579] [drm:intel_power_well_disable [i915]] disabling power well 2
>[ 2004.704632] [drm:intel_power_well_disable [i915]] disabling DC off
>[ 2004.704681] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[ 2004.704730] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[ 2004.740049] [drm:intel_atomic_check [i915]] [CONNECTOR:57:DP-1] checking for sink bpp constrains
>[ 2004.740064] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 2004.740079] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 148500KHz
>[ 2004.740094] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 2004.740107] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 648000
>[ 2004.740121] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 2004.740135] [drm:intel_dump_pipe_config [i915]] [CRTC:47:pipe B][modeset]
>[ 2004.740148] [drm:intel_dump_pipe_config [i915]] output_types: DP (0x80)
>[ 2004.740160] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 2004.740172] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5767168, gmch_n: 8388608, link_m: 240298, link_n: 262144, tu: 64
>[ 2004.740184] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[ 2004.740196] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 2004.740203] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[ 2004.740228] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 2004.740234] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[ 2004.740248] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[ 2004.740260] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1080, pixel rate 148500
>[ 2004.740272] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[ 2004.740284] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 2004.740296] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 2004.740308] [drm:intel_dump_pipe_config [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[ 2004.740320] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 2004.740332] [drm:intel_dump_pipe_config [i915]] [PLANE:38:plane 1B] disabled, scaler_id = -1
>[ 2004.740344] [drm:intel_dump_pipe_config [i915]] [PLANE:41:plane 2B] disabled, scaler_id = -1
>[ 2004.740356] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor B] disabled, scaler_id = -1
>[ 2004.740371] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 2004.740384] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[ 2004.740402] [drm:intel_find_shared_dpll [i915]] [CRTC:47:pipe B] allocated DPLL 1
>[ 2004.740416] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[ 2007.322850] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 2007.322931] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 2007.323054] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[ 2007.323118] [drm:intel_power_well_enable [i915]] enabling DC off
>[ 2007.323184] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[ 2007.323243] [drm:intel_power_well_enable [i915]] enabling power well 2
>[ 2007.584151] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 2007.584232] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 2013.157079] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 2013.157161] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 2013.416499] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 2013.416580] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 2014.940278] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [CRTC:37:pipe A] flip_done timed out
>[ 2018.977015] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 2018.977097] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 2019.239459] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 2019.239540] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 2024.817622] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 2024.817704] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 2025.077838] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 2025.077920] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 2025.180234] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [CONNECTOR:49:eDP-1] flip_done timed out
>[ 2030.648169] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 2030.648251] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 2030.906844] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 2030.906926] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 2035.420273] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [PLANE:28:plane 1A] flip_done timed out
>[ 2035.420365] [drm:intel_disable_sagv [i915]] Disabling the SAGV
>[ 2035.420454] [drm:intel_atomic_commit_tail [i915]] [ENCODER:48:DDI A]
>[ 2035.420527] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI B]
>[ 2035.420596] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[ 2035.420662] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[ 2035.420725] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DDI C]
>[ 2035.420787] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST A]
>[ 2035.420848] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST B]
>[ 2035.420908] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI D]
>[ 2035.420967] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[ 2035.421025] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[ 2035.421091] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[ 2035.421159] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[ 2035.421224] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[ 2035.421287] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[ 2035.421364] [drm:intel_fbc_enable [i915]] reserved 16588800 bytes of contiguous stolen space for FBC, threshold: 1
>[ 2035.421430] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 2035.427624] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 2, on? 0) for crtc 47
>[ 2035.427701] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[ 2035.427816] [drm:intel_power_well_enable [i915]] enabling DDI B IO power well
>[ 2035.428453] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 2035.429713] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 2035.430972] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 2035.432228] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 2035.433490] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 2035.434373] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[ 2035.435371] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 2035.435440] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 2035.435504] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 2035.435566] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 2035.454245] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 2035.454273] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[ 2035.472085] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 2035.472409] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:57:DP-1] Link Training Passed at Link Rate = 162000, Lane count = 4
>[ 2035.472793] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 2035.472859] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS
>[ 2036.477206] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 2036.477289] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 2036.740744] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 2036.740826] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 2045.660279] [drm:drm_atomic_helper_wait_for_flip_done [drm_kms_helper]] *ERROR* [CRTC:37:pipe A] flip_done timed out
>[ 2045.660420] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:57:DP-1]
>[ 2045.660521] [drm:intel_atomic_commit_tail [i915]] [CRTC:47:pipe B]
>[ 2045.660620] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[ 2045.661216] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 00 00 04 00 0f 00 04
>[ 2045.662661] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[ 2045.663143] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 00 00 04 00 0f 00 04
>[ 2045.711170] [IGT] kms_frontbuffer_tracking: executing
>[ 2045.745455] [drm:drm_mode_addfb2 [drm]] [FB:75]
>[ 2045.745485] [drm:drm_mode_addfb2 [drm]] [FB:91]
>[ 2045.745517] [drm:drm_mode_addfb2 [drm]] [FB:92]
>[ 2045.746152] [drm:drm_mode_addfb2 [drm]] [FB:93]
>[ 2045.751734] [drm:drm_mode_addfb2 [drm]] [FB:94]
>[ 2045.753125] [drm:drm_mode_addfb2 [drm]] [FB:96]
>[ 2045.753154] [drm:drm_mode_addfb2 [drm]] [FB:98]
>[ 2045.753189] [drm:drm_mode_addfb2 [drm]] [FB:102]
>[ 2045.753392] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[ 2045.753402] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[ 2055.900277] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [CRTC:37:pipe A] flip_done timed out
>[ 2066.140165] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [CONNECTOR:49:eDP-1] flip_done timed out
>[ 2076.380215] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [PLANE:28:plane 1A] flip_done timed out
>[ 2086.620180] [drm:drm_atomic_helper_wait_for_flip_done [drm_kms_helper]] *ERROR* [CRTC:37:pipe A] flip_done timed out
>[ 2086.620365] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[ 2086.620522] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006f
>[ 2086.810112] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped
>[ 2086.810334] [IGT] kms_frontbuffer_tracking: starting subtest psr-1p-offscren-pri-indfb-draw-pwrite
>[ 2086.810408] Setting dangerous option enable_fbc - tainting kernel
>[ 2086.810430] Setting dangerous option enable_psr - tainting kernel
>[ 2089.948258] [drm:edp_panel_vdd_off_sync [i915]] Turning eDP port A VDD off
>[ 2089.948405] [drm:edp_panel_vdd_off_sync [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x00000067
>[ 2096.859970] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [CRTC:37:pipe A] flip_done timed out
>[ 2107.100279] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [PLANE:28:plane 1A] flip_done timed out
>[ 2117.340162] [drm:drm_atomic_helper_wait_for_flip_done [drm_kms_helper]] *ERROR* [CRTC:37:pipe A] flip_done timed out
>[ 2117.344532] [drm:drm_mode_addfb2 [drm]] [FB:72]
>[ 2117.344632] [drm:drm_mode_addfb2 [drm]] [FB:75]
>[ 2117.344737] [drm:drm_mode_addfb2 [drm]] [FB:91]
>[ 2117.346003] [drm:drm_mode_addfb2 [drm]] [FB:92]
>[ 2117.349768] [drm:drm_mode_addfb2 [drm]] [FB:93]
>[ 2117.350607] [drm:drm_mode_addfb2 [drm]] [FB:94]
>[ 2117.350627] [drm:drm_mode_addfb2 [drm]] [FB:96]
>[ 2117.350650] [drm:drm_mode_addfb2 [drm]] [FB:98]
>[ 2117.350756] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[ 2117.350790] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 2117.350804] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[ 2127.580249] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [CRTC:37:pipe A] flip_done timed out
>[ 2137.820262] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [CONNECTOR:49:eDP-1] flip_done timed out
>[ 2148.060213] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [PLANE:28:plane 1A] flip_done timed out
>[ 2148.060338] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[ 2148.060494] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006f
>[ 2148.060768] [drm:intel_edp_backlight_off [i915]] 
>[ 2148.268227] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0
>[ 2148.268367] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 2148.276715] [drm:intel_edp_panel_off.part.31 [i915]] Turn eDP port A panel power off
>[ 2148.276825] [drm:intel_edp_panel_off.part.31 [i915]] Wait for panel power off time
>[ 2148.276958] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000003 control 00000060
>[ 2148.327091] [drm:wait_panel_status [i915]] Wait complete
>[ 2148.327155] [drm:intel_power_well_disable [i915]] disabling DDI A/E IO power well
>[ 2148.327239] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 2148.327319] [drm:intel_disable_shared_dpll [i915]] disable DPLL 0 (active 1, on? 1) for crtc 37
>[ 2148.327392] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 0
>[ 2148.327486] [drm:intel_atomic_commit_tail [i915]] [ENCODER:48:DDI A]
>[ 2148.327556] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI B]
>[ 2148.327622] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[ 2148.327686] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[ 2148.327749] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DDI C]
>[ 2148.327811] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST A]
>[ 2148.327872] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST B]
>[ 2148.327932] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI D]
>[ 2148.328031] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[ 2148.328097] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[ 2148.328173] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:49:eDP-1]
>[ 2148.328245] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[ 2148.328316] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[ 2148.328386] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[ 2148.328455] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[ 2148.336660] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010
>[ 2148.336741] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[ 2148.336816] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0
>[ 2148.336935] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[ 2148.340180] [drm:intel_atomic_commit_tail [i915]] [CRTC:37:pipe A]
>[ 2148.340252] [drm:intel_enable_sagv [i915]] Enabling the SAGV
>[ 2148.340363] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[ 2148.340464] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 2148.340537] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[ 2148.340651] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 2148.357586] [drm:intel_power_well_disable [i915]] disabling DDI B IO power well
>[ 2148.357669] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 2, on? 1) for crtc 47
>[ 2148.357743] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[ 2148.357834] [drm:intel_atomic_commit_tail [i915]] [ENCODER:48:DDI A]
>[ 2148.357900] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI B]
>[ 2148.357965] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[ 2148.358025] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[ 2148.358084] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DDI C]
>[ 2148.358143] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST A]
>[ 2148.358200] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST B]
>[ 2148.358256] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI D]
>[ 2148.358312] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[ 2148.358368] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[ 2148.358430] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:57:DP-1]
>[ 2148.358492] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[ 2148.358554] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[ 2148.358615] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[ 2148.358674] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[ 2148.358734] [drm:intel_power_well_disable [i915]] disabling power well 2
>[ 2148.358806] [drm:intel_atomic_commit_tail [i915]] [CRTC:47:pipe B]
>[ 2148.358861] [drm:intel_power_well_disable [i915]] disabling DC off
>[ 2148.358912] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[ 2148.358961] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[ 2148.359400] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 2148.362093] [drm:drm_mode_addfb2 [drm]] [FB:73]
>[ 2148.363757] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[ 2148.363763] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[ 2148.363784] [drm:intel_atomic_check [i915]] [CONNECTOR:49:eDP-1] checking for sink bpp constrains
>[ 2148.363797] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 2148.363803] [drm:drm_mode_debug_printmodeline [drm]] Modeline 52:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[ 2148.363817] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 138780KHz
>[ 2148.363833] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24
>[ 2148.363844] [drm:intel_dp_compute_config [i915]] DP link bw required 416340 available 540000
>[ 2148.363856] [drm:intel_dp_compute_config [i915]] PSR disable by flag
>[ 2148.363868] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 2148.363881] [drm:intel_dump_pipe_config [i915]] [CRTC:37:pipe A][modeset]
>[ 2148.363892] [drm:intel_dump_pipe_config [i915]] output_types: EDP (0x100)
>[ 2148.363904] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0
>[ 2148.363920] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 6467616, gmch_n: 8388608, link_m: 269484, link_n: 524288, tu: 64
>[ 2148.363931] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[ 2148.363960] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 2148.363967] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[ 2148.363980] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 2148.363987] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[ 2148.364000] [drm:intel_dump_pipe_config [i915]] crtc timings: 138780 1920 1966 1996 2080 1080 1082 1086 1112, type: 0x48 flags: 0xa
>[ 2148.364013] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 138780
>[ 2148.364025] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[ 2148.364037] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 2148.364049] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 2148.364060] [drm:intel_dump_pipe_config [i915]] dpll_hw_state: ctrl1: 0x3, cfgcr1: 0x0, cfgcr2: 0x0
>[ 2148.364088] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 2148.364099] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 1A] disabled, scaler_id = -1
>[ 2148.364110] [drm:intel_dump_pipe_config [i915]] [PLANE:31:plane 2A] disabled, scaler_id = -1
>[ 2148.364122] [drm:intel_dump_pipe_config [i915]] [PLANE:34:cursor A] disabled, scaler_id = -1
>[ 2148.364150] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 2148.364162] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[ 2148.364189] [drm:intel_find_shared_dpll [i915]] [CRTC:37:pipe A] allocated DPLL 0
>[ 2148.364201] [drm:intel_reference_shared_dpll [i915]] using DPLL 0 for pipe A
>[ 2148.364715] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 2148.364724] [drm:intel_power_well_enable [i915]] enabling DC off
>[ 2148.365016] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[ 2148.365050] [drm:intel_atomic_commit_tail [i915]] [ENCODER:48:DDI A]
>[ 2148.365062] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI B]
>[ 2148.365091] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[ 2148.365101] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[ 2148.365112] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DDI C]
>[ 2148.365123] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST A]
>[ 2148.365134] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST B]
>[ 2148.365145] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI D]
>[ 2148.365155] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[ 2148.365166] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[ 2148.365177] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[ 2148.365189] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[ 2148.365200] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[ 2148.365212] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[ 2148.365225] [drm:intel_enable_shared_dpll [i915]] enable DPLL 0 (active 1, on? 0) for crtc 37
>[ 2148.365236] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 0
>[ 2148.365255] [drm:edp_panel_on [i915]] Turn eDP port A panel power on
>[ 2148.365280] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle
>[ 2148.956435] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 00000000 control 00000060
>[ 2148.956544] [drm:wait_panel_status [i915]] Wait complete
>[ 2148.956682] [drm:edp_panel_on [i915]] Wait for panel power on
>[ 2148.956814] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 00000063
>[ 2148.990473] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010
>[ 2148.990554] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[ 2148.990627] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1
>[ 2148.990770] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[ 2149.156869] [drm:wait_panel_status [i915]] Wait complete
>[ 2149.156934] [drm:intel_power_well_enable [i915]] enabling DDI A/E IO power well
>[ 2149.157037] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[ 2149.157186] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b
>[ 2149.158386] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 2149.158448] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 2149.158506] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 2149.158566] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 2149.159276] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 2149.159333] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 2149.160328] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 2149.160353] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:49:eDP-1] Link Training Passed at Link Rate = 270000, Lane count = 2
>[ 2149.160732] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 2149.160766] [drm:intel_edp_backlight_on [i915]] 
>[ 2149.160778] [drm:intel_panel_enable_backlight [i915]] pipe A
>[ 2149.160816] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 120000
>[ 2149.168050] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS
>[ 2152.412106] [drm:edp_panel_vdd_off_sync [i915]] Turning eDP port A VDD off
>[ 2152.412252] [drm:edp_panel_vdd_off_sync [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x00000067
>[ 2159.324174] [drm:drm_atomic_helper_wait_for_flip_done [drm_kms_helper]] *ERROR* [CRTC:37:pipe A] flip_done timed out
>[ 2159.324294] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:49:eDP-1]
>[ 2159.324380] [drm:intel_atomic_commit_tail [i915]] [CRTC:37:pipe A]
>[ 2159.324476] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[ 2159.324540] [drm:intel_power_well_disable [i915]] disabling DC off
>[ 2159.324595] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[ 2159.324649] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[ 2159.361090] [drm:intel_power_well_enable [i915]] enabling DC off
>[ 2159.361150] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[ 2159.361247] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[ 2159.361400] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006f
>[ 2159.561033] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped
>[ 2159.561110] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[ 2159.561201] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 2159.561263] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[ 2162.652356] [drm:edp_panel_vdd_off_sync [i915]] Turning eDP port A VDD off
>[ 2162.652502] [drm:edp_panel_vdd_off_sync [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x00000067
>[ 2162.652559] [drm:intel_power_well_disable [i915]] disabling DC off
>[ 2162.652616] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[ 2162.652669] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[ 2169.096427] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 2169.096509] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 2169.096636] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[ 2169.096701] [drm:intel_power_well_enable [i915]] enabling DC off
>[ 2169.096765] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[ 2169.096825] [drm:intel_power_well_enable [i915]] enabling power well 2
>[ 2169.365628] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 2169.365710] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 2169.564154] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [CRTC:37:pipe A] flip_done timed out
>[ 2174.140822] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 2174.140903] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 2174.409915] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 2174.409996] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 2179.804186] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [CONNECTOR:49:eDP-1] flip_done timed out
>[ 2179.983560] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 2179.983641] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 2180.266274] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 2180.266355] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 2185.840088] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 2185.840170] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 2186.109398] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 2186.109480] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 2190.044009] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [PLANE:28:plane 1A] flip_done timed out
>[ 2190.044114] [drm:intel_edp_backlight_off [i915]] 
>[ 2190.252333] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0
>[ 2190.252468] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 2190.260990] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[ 2190.261149] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b
>[ 2190.261420] [drm:intel_edp_panel_off.part.31 [i915]] Turn eDP port A panel power off
>[ 2190.261522] [drm:intel_edp_panel_off.part.31 [i915]] Wait for panel power off time
>[ 2190.261647] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000003 control 00000060
>[ 2190.314045] [drm:wait_panel_status [i915]] Wait complete
>[ 2190.314108] [drm:intel_power_well_disable [i915]] disabling DDI A/E IO power well
>[ 2190.314194] [drm:intel_disable_shared_dpll [i915]] disable DPLL 0 (active 1, on? 1) for crtc 37
>[ 2190.314268] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 0
>[ 2190.314359] [drm:intel_atomic_commit_tail [i915]] [ENCODER:48:DDI A]
>[ 2190.314431] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI B]
>[ 2190.314497] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[ 2190.314561] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[ 2190.314624] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DDI C]
>[ 2190.314684] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST A]
>[ 2190.314745] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST B]
>[ 2190.314804] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI D]
>[ 2190.314864] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[ 2190.314924] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[ 2190.314989] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:49:eDP-1]
>[ 2190.315055] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[ 2190.315120] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[ 2190.315183] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[ 2190.315244] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[ 2190.315320] [drm:intel_atomic_commit_tail [i915]] [CRTC:37:pipe A]
>[ 2190.315442] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[ 2190.315913] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 00 00 04 00 0f 00 04
>[ 2190.321742] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010
>[ 2190.321758] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[ 2190.321773] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0
>[ 2190.344621] [drm:intel_power_well_disable [i915]] disabling power well 2
>[ 2190.344639] [drm:intel_power_well_disable [i915]] disabling DC off
>[ 2190.344655] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[ 2190.344669] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[ 2190.344684] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 2190.344705] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[ 2190.344725] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[ 2190.344739] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 2190.344752] [drm:intel_power_well_enable [i915]] enabling DC off
>[ 2190.345074] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[ 2190.345090] [drm:intel_power_well_enable [i915]] enabling power well 2
>[ 2190.345498] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 00 00 04 00 0f 00 04
>[ 2190.346145] [drm:drm_mode_addfb2 [drm]] [FB:73]
>[ 2190.346781] [drm:intel_power_well_disable [i915]] disabling power well 2
>[ 2190.346799] [drm:intel_power_well_disable [i915]] disabling DC off
>[ 2190.346816] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[ 2190.346831] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[ 2190.346848] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 2190.347576] [drm:drm_mode_addfb2 [drm]] [FB:102]
>[ 2190.349268] [drm:drm_mode_addfb2 [drm]] [FB:103]
>[ 2190.350646] [drm:drm_mode_addfb2 [drm]] [FB:104]
>[ 2190.433048] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[ 2190.433055] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[ 2190.433082] [drm:intel_atomic_check [i915]] [CONNECTOR:49:eDP-1] checking for sink bpp constrains
>[ 2190.433095] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 2190.433102] [drm:drm_mode_debug_printmodeline [drm]] Modeline 52:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[ 2190.433116] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 138780KHz
>[ 2190.433132] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24
>[ 2190.433144] [drm:intel_dp_compute_config [i915]] DP link bw required 416340 available 540000
>[ 2190.433155] [drm:intel_dp_compute_config [i915]] PSR disable by flag
>[ 2190.433168] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 2190.433181] [drm:intel_dump_pipe_config [i915]] [CRTC:37:pipe A][modeset]
>[ 2190.433193] [drm:intel_dump_pipe_config [i915]] output_types: EDP (0x100)
>[ 2190.433205] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0
>[ 2190.433216] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 6467616, gmch_n: 8388608, link_m: 269484, link_n: 524288, tu: 64
>[ 2190.433227] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[ 2190.433238] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 2190.433243] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[ 2190.433254] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 2190.433260] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[ 2190.433271] [drm:intel_dump_pipe_config [i915]] crtc timings: 138780 1920 1966 1996 2080 1080 1082 1086 1112, type: 0x48 flags: 0xa
>[ 2190.433282] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 138780
>[ 2190.433293] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[ 2190.433303] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 2190.433314] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 2190.433324] [drm:intel_dump_pipe_config [i915]] dpll_hw_state: ctrl1: 0x3, cfgcr1: 0x0, cfgcr2: 0x0
>[ 2190.433334] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 2190.433345] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 1A] disabled, scaler_id = -1
>[ 2190.433355] [drm:intel_dump_pipe_config [i915]] [PLANE:31:plane 2A] disabled, scaler_id = -1
>[ 2190.433365] [drm:intel_dump_pipe_config [i915]] [PLANE:34:cursor A] disabled, scaler_id = -1
>[ 2190.433378] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 2190.433390] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[ 2190.433404] [drm:intel_find_shared_dpll [i915]] [CRTC:37:pipe A] allocated DPLL 0
>[ 2190.433416] [drm:intel_reference_shared_dpll [i915]] using DPLL 0 for pipe A
>[ 2190.434374] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 2190.434384] [drm:intel_power_well_enable [i915]] enabling DC off
>[ 2190.434676] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[ 2190.434731] [drm:intel_atomic_commit_tail [i915]] [ENCODER:48:DDI A]
>[ 2190.434743] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI B]
>[ 2190.434757] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[ 2190.434786] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[ 2190.434815] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DDI C]
>[ 2190.434843] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST A]
>[ 2190.434854] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST B]
>[ 2190.434864] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI D]
>[ 2190.434875] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[ 2190.434885] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[ 2190.434897] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[ 2190.434909] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[ 2190.434921] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[ 2190.434932] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[ 2190.434945] [drm:intel_enable_shared_dpll [i915]] enable DPLL 0 (active 1, on? 0) for crtc 37
>[ 2190.434957] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 0
>[ 2190.434976] [drm:edp_panel_on [i915]] Turn eDP port A panel power on
>[ 2190.435000] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle
>[ 2190.940186] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 00000000 control 00000060
>[ 2190.940284] [drm:wait_panel_status [i915]] Wait complete
>[ 2190.940414] [drm:edp_panel_on [i915]] Wait for panel power on
>[ 2190.940537] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 00000063
>[ 2190.972728] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010
>[ 2190.972791] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[ 2190.972849] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1
>[ 2190.972927] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[ 2191.140680] [drm:wait_panel_status [i915]] Wait complete
>[ 2191.140746] [drm:intel_power_well_enable [i915]] enabling DDI A/E IO power well
>[ 2191.140850] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[ 2191.141004] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b
>[ 2191.142227] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 2191.142292] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 2191.142349] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 2191.142405] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 2191.143107] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 2191.143161] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 2191.144212] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 2191.144286] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:49:eDP-1] Link Training Passed at Link Rate = 270000, Lane count = 2
>[ 2191.144929] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 2191.145000] [drm:intel_edp_backlight_on [i915]] 
>[ 2191.145056] [drm:intel_panel_enable_backlight [i915]] pipe A
>[ 2191.145137] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 120000
>[ 2191.152043] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS
>[ 2191.667734] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 2191.667806] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 2191.667906] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[ 2191.667977] [drm:intel_power_well_enable [i915]] enabling power well 2
>[ 2191.928196] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 2191.928267] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 2194.396106] [drm:edp_panel_vdd_off_sync [i915]] Turning eDP port A VDD off
>[ 2194.396253] [drm:edp_panel_vdd_off_sync [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x00000067
>[ 2197.503928] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 2197.504010] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 2197.763061] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 2197.763143] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 2201.308173] [drm:drm_atomic_helper_wait_for_flip_done [drm_kms_helper]] *ERROR* [CRTC:37:pipe A] flip_done timed out
>[ 2201.308293] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:49:eDP-1]
>[ 2201.308376] [drm:intel_atomic_commit_tail [i915]] [CRTC:37:pipe A]
>[ 2201.308472] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[ 2201.309057] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 00 00 04 00 0f 00 04
>[ 2201.310457] [drm:intel_power_well_disable [i915]] disabling power well 2
>[ 2201.310507] [drm:intel_power_well_disable [i915]] disabling DC off
>[ 2201.310552] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[ 2201.310595] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[ 2201.310659] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[ 2201.310702] [drm:intel_power_well_enable [i915]] enabling DC off
>[ 2201.310744] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[ 2201.310791] [drm:intel_power_well_enable [i915]] enabling power well 2
>[ 2201.311264] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 00 00 04 00 0f 00 04
>[ 2201.312678] [drm:intel_power_well_disable [i915]] disabling power well 2
>[ 2201.312726] [drm:intel_power_well_disable [i915]] disabling DC off
>[ 2201.312771] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[ 2201.312813] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[ 2201.345145] [drm:intel_power_well_enable [i915]] enabling DC off
>[ 2201.345199] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[ 2201.345287] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[ 2201.345434] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006f
>[ 2201.545237] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped
>[ 2201.545287] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[ 2201.545318] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[ 2203.325148] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 2203.325230] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 2203.325349] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[ 2203.325415] [drm:intel_power_well_enable [i915]] enabling power well 2
>[ 2203.585408] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 2203.585489] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 2204.636117] [drm:edp_panel_vdd_off_sync [i915]] Turning eDP port A VDD off
>[ 2204.636263] [drm:edp_panel_vdd_off_sync [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x00000067
>[ 2209.157843] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 2209.157925] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 2209.418106] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 2209.418187] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 2211.548146] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [CRTC:37:pipe A] flip_done timed out
>[ 2214.991989] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 2214.992070] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 2215.252045] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 2215.252126] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 2220.822576] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 2220.822657] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 2221.085395] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 2221.085476] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 2221.788153] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [CONNECTOR:49:eDP-1] flip_done timed out
>[ 2226.653079] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 2226.653161] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 2226.913331] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 2226.913412] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 2232.027997] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [PLANE:28:plane 1A] flip_done timed out
>[ 2232.489591] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 2232.489673] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 2232.749562] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 2232.749643] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 2238.325258] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 2238.325339] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 2238.587033] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 2238.587114] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 2242.268266] [drm:drm_atomic_helper_wait_for_flip_done [drm_kms_helper]] *ERROR* [CRTC:37:pipe A] flip_done timed out
>[ 2242.268868] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 00 00 04 00 0f 00 04
>[ 2242.270274] [drm:intel_power_well_disable [i915]] disabling power well 2
>[ 2242.270331] [drm:intel_power_well_disable [i915]] disabling DC off
>[ 2242.270381] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[ 2242.270430] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[ 2242.270505] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[ 2242.270553] [drm:intel_power_well_enable [i915]] enabling DC off
>[ 2242.270600] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[ 2242.270651] [drm:intel_power_well_enable [i915]] enabling power well 2
>[ 2242.271135] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 00 00 04 00 0f 00 04
>[ 2242.272560] [drm:intel_power_well_disable [i915]] disabling power well 2
>[ 2242.272613] [drm:intel_power_well_disable [i915]] disabling DC off
>[ 2242.272662] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[ 2242.272709] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[ 2242.311063] [drm:intel_power_well_enable [i915]] enabling DC off
>[ 2242.311122] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[ 2242.311220] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[ 2242.311373] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006f
>[ 2242.511195] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped
>[ 2242.511240] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[ 2242.511269] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[ 2244.165579] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 2244.165660] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 2244.165781] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[ 2244.165846] [drm:intel_power_well_enable [i915]] enabling power well 2
>[ 2244.426413] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 2244.426493] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 2245.596212] [drm:edp_panel_vdd_off_sync [i915]] Turning eDP port A VDD off
>[ 2245.596358] [drm:edp_panel_vdd_off_sync [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x00000067
>[ 2250.002330] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 2250.002411] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 2250.262285] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 2250.262366] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 2252.764248] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [CRTC:37:pipe A] flip_done timed out
>[ 2255.832976] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 2255.833057] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 2256.092887] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 2256.092968] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 2261.657983] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 2261.658064] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 2261.921174] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 2261.921255] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 2263.004269] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [CONNECTOR:49:eDP-1] flip_done timed out
>[ 2267.492030] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 2267.492111] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 2267.750409] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 2267.750490] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 2273.243991] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [PLANE:28:plane 1A] flip_done timed out
>[ 2273.314568] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 2273.314649] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 2273.574422] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 2273.574503] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 2279.148881] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 2279.148962] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 2279.411861] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 2279.411942] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 2283.484151] [drm:drm_atomic_helper_wait_for_flip_done [drm_kms_helper]] *ERROR* [CRTC:37:pipe A] flip_done timed out
>[ 2283.484750] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 00 00 04 00 0f 00 04
>[ 2283.486158] [drm:intel_power_well_disable [i915]] disabling power well 2
>[ 2283.486215] [drm:intel_power_well_disable [i915]] disabling DC off
>[ 2283.486267] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[ 2283.486316] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[ 2283.486391] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[ 2283.486439] [drm:intel_power_well_enable [i915]] enabling DC off
>[ 2283.486486] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[ 2283.486538] [drm:intel_power_well_enable [i915]] enabling power well 2
>[ 2283.487021] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 00 00 04 00 0f 00 04
>[ 2283.488470] [drm:intel_power_well_disable [i915]] disabling power well 2
>[ 2283.488523] [drm:intel_power_well_disable [i915]] disabling DC off
>[ 2283.488572] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[ 2283.488621] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[ 2283.527068] [drm:intel_power_well_enable [i915]] enabling DC off
>[ 2283.527122] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[ 2283.527210] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[ 2283.527358] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006f
>[ 2283.727146] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped
>[ 2283.727194] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[ 2283.727225] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[ 2284.980779] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 2284.980860] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 2284.980981] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[ 2284.981046] [drm:intel_power_well_enable [i915]] enabling power well 2
>[ 2285.242068] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 2285.242150] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 2286.812208] [drm:edp_panel_vdd_off_sync [i915]] Turning eDP port A VDD off
>[ 2286.812353] [drm:edp_panel_vdd_off_sync [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x00000067
>[ 2290.820337] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 2290.820419] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 2291.077741] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 2291.077823] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 2293.980244] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [CRTC:37:pipe A] flip_done timed out
>[ 2296.642588] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 2296.642670] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 2296.903087] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 2296.903168] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 2302.476482] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 2302.476554] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 2302.736666] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 2302.736747] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 2304.220267] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [CONNECTOR:49:eDP-1] flip_done timed out
>[ 2308.310029] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 2308.310110] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 2308.570642] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 2308.570724] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 2314.144365] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 2314.144446] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 2314.403042] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 2314.403123] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 2314.460022] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [PLANE:28:plane 1A] flip_done timed out
>[ 2319.970559] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 2319.970631] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 2320.231067] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 2320.231150] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 2324.700262] [drm:drm_atomic_helper_wait_for_flip_done [drm_kms_helper]] *ERROR* [CRTC:37:pipe A] flip_done timed out
>[ 2324.700860] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 00 00 04 00 0f 00 04
>[ 2324.702267] [drm:intel_power_well_disable [i915]] disabling power well 2
>[ 2324.702324] [drm:intel_power_well_disable [i915]] disabling DC off
>[ 2324.702374] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[ 2324.702427] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[ 2324.702502] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[ 2324.702550] [drm:intel_power_well_enable [i915]] enabling DC off
>[ 2324.702597] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[ 2324.702648] [drm:intel_power_well_enable [i915]] enabling power well 2
>[ 2324.703135] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 00 00 04 00 0f 00 04
>[ 2324.704578] [drm:intel_power_well_disable [i915]] disabling power well 2
>[ 2324.704631] [drm:intel_power_well_disable [i915]] disabling DC off
>[ 2324.704680] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[ 2324.704728] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[ 2324.742818] [drm:intel_power_well_enable [i915]] enabling DC off
>[ 2324.742871] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[ 2324.742958] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[ 2324.743101] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006f
>[ 2324.943090] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped
>[ 2324.943209] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[ 2324.943298] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 2324.943359] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[ 2325.800388] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 2325.800469] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 2325.800594] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[ 2325.800661] [drm:intel_power_well_enable [i915]] enabling power well 2
>[ 2326.060614] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 2326.060696] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 2328.028203] [drm:edp_panel_vdd_off_sync [i915]] Turning eDP port A VDD off
>[ 2328.028348] [drm:edp_panel_vdd_off_sync [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x00000067
>[ 2331.635855] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 2331.635936] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 2331.896249] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 2331.896331] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 2335.196143] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [CRTC:37:pipe A] flip_done timed out
>[ 2337.468336] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 2337.468416] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 2337.729384] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 2337.729465] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 2343.297321] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 2343.297393] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 2343.557581] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 2343.557653] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 2345.436267] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [CONNECTOR:49:eDP-1] flip_done timed out
>[ 2349.134833] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 2349.134915] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 2349.392656] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 2349.392738] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 2354.956649] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 2354.956731] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 2355.216702] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 2355.216783] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 2355.676022] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [PLANE:28:plane 1A] flip_done timed out
>[ 2355.676125] [drm:intel_edp_backlight_off [i915]] 
>[ 2355.884320] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0
>[ 2355.884460] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 2355.892979] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[ 2355.893136] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b
>[ 2355.893410] [drm:intel_edp_panel_off.part.31 [i915]] Turn eDP port A panel power off
>[ 2355.893511] [drm:intel_edp_panel_off.part.31 [i915]] Wait for panel power off time
>[ 2355.893636] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000002 control 00000060
>[ 2355.945871] [drm:wait_panel_status [i915]] Wait complete
>[ 2355.945936] [drm:intel_power_well_disable [i915]] disabling DDI A/E IO power well
>[ 2355.946022] [drm:intel_disable_shared_dpll [i915]] disable DPLL 0 (active 1, on? 1) for crtc 37
>[ 2355.946097] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 0
>[ 2355.946189] [drm:intel_atomic_commit_tail [i915]] [ENCODER:48:DDI A]
>[ 2355.946261] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI B]
>[ 2355.946328] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[ 2355.946392] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[ 2355.946456] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DDI C]
>[ 2355.946517] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST A]
>[ 2355.946578] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST B]
>[ 2355.946638] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI D]
>[ 2355.946698] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[ 2355.946757] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[ 2355.946822] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:49:eDP-1]
>[ 2355.946889] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[ 2355.946954] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[ 2355.947017] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[ 2355.947078] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[ 2355.947155] [drm:intel_atomic_commit_tail [i915]] [CRTC:37:pipe A]
>[ 2355.947278] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[ 2355.947742] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 00 00 04 00 0f 00 04
>[ 2355.949191] [drm:intel_power_well_disable [i915]] disabling power well 2
>[ 2355.949243] [drm:intel_power_well_disable [i915]] disabling DC off
>[ 2355.949289] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[ 2355.949333] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[ 2355.949335] Setting dangerous option enable_psr - tainting kernel
>[ 2355.950263] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 2355.950346] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[ 2355.950389] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 2355.950415] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[ 2355.950456] [drm:intel_power_well_enable [i915]] enabling DC off
>[ 2355.950475] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[ 2355.950563] [drm:intel_atomic_check [i915]] [CONNECTOR:49:eDP-1] checking for sink bpp constrains
>[ 2355.950621] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 2355.950650] [drm:drm_mode_debug_printmodeline [drm]] Modeline 52:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[ 2355.950715] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 138780KHz
>[ 2355.950765] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[ 2355.950825] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24
>[ 2355.950881] [drm:intel_dp_compute_config [i915]] DP link bw required 416340 available 540000
>[ 2355.950941] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 2355.950999] [drm:intel_dump_pipe_config [i915]] [CRTC:37:pipe A][modeset]
>[ 2355.951055] [drm:intel_dump_pipe_config [i915]] output_types: EDP (0x100)
>[ 2355.951109] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0
>[ 2355.951163] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 6467616, gmch_n: 8388608, link_m: 269484, link_n: 524288, tu: 64
>[ 2355.951215] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[ 2355.951265] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 2355.951305] [drm:intel_power_well_enable [i915]] enabling power well 2
>[ 2355.951333] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[ 2355.951383] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 2355.951409] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[ 2355.951462] [drm:intel_dump_pipe_config [i915]] crtc timings: 138780 1920 1966 1996 2080 1080 1082 1086 1112, type: 0x48 flags: 0xa
>[ 2355.951513] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 138780
>[ 2355.951563] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[ 2355.951612] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 2355.951661] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 2355.951710] [drm:intel_dump_pipe_config [i915]] dpll_hw_state: ctrl1: 0x3, cfgcr1: 0x0, cfgcr2: 0x0
>[ 2355.951758] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 2355.951812] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 1A] disabled, scaler_id = -1
>[ 2355.951860] [drm:intel_dump_pipe_config [i915]] [PLANE:31:plane 2A] disabled, scaler_id = -1
>[ 2355.951908] [drm:intel_dump_pipe_config [i915]] [PLANE:34:cursor A] disabled, scaler_id = -1
>[ 2355.951999] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 2355.952060] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[ 2355.952133] [drm:intel_find_shared_dpll [i915]] [CRTC:37:pipe A] allocated DPLL 0
>[ 2355.952196] [drm:intel_reference_shared_dpll [i915]] using DPLL 0 for pipe A
>[ 2355.953099] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010
>[ 2355.953163] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[ 2355.953224] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0
>[ 2355.953305] [drm:intel_atomic_commit_tail [i915]] [ENCODER:48:DDI A]
>[ 2355.953367] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI B]
>[ 2355.953427] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[ 2355.953480] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[ 2355.953534] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DDI C]
>[ 2355.953586] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST A]
>[ 2355.953638] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST B]
>[ 2355.953688] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI D]
>[ 2355.953740] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[ 2355.953790] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[ 2355.953846] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[ 2355.953902] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[ 2355.953957] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[ 2355.954009] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[ 2355.954073] [drm:intel_enable_shared_dpll [i915]] enable DPLL 0 (active 1, on? 0) for crtc 37
>[ 2355.954128] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 0
>[ 2355.954205] [drm:edp_panel_on [i915]] Turn eDP port A panel power on
>[ 2355.954275] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle
>[ 2356.572407] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 00000000 control 00000060
>[ 2356.572498] [drm:wait_panel_status [i915]] Wait complete
>[ 2356.572607] [drm:edp_panel_on [i915]] Wait for panel power on
>[ 2356.572741] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 00000063
>[ 2356.606053] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010
>[ 2356.606135] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[ 2356.606211] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1
>[ 2356.775463] [drm:wait_panel_status [i915]] Wait complete
>[ 2356.775529] [drm:intel_power_well_enable [i915]] enabling DDI A/E IO power well
>[ 2356.775631] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[ 2356.775783] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b
>[ 2356.777024] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 2356.777096] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 2356.777160] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 2356.777223] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 2356.777945] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 2356.777999] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 2356.779006] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 2356.779067] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:49:eDP-1] Link Training Passed at Link Rate = 270000, Lane count = 2
>[ 2356.779721] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 2356.779800] [drm:intel_edp_backlight_on [i915]] 
>[ 2356.779862] [drm:intel_panel_enable_backlight [i915]] pipe A
>[ 2356.779952] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 120000
>[ 2356.780333] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS
>[ 2360.028258] [drm:edp_panel_vdd_off_sync [i915]] Turning eDP port A VDD off
>[ 2360.028403] [drm:edp_panel_vdd_off_sync [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x00000067
>[ 2360.792492] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 2360.792573] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 2361.054964] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 2361.055046] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 2366.623783] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 2366.623864] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 2366.885871] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 2366.885953] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 2366.940263] [drm:drm_atomic_helper_wait_for_flip_done [drm_kms_helper]] *ERROR* [CRTC:37:pipe A] flip_done timed out
>[ 2366.940387] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:49:eDP-1]
>[ 2366.940471] [drm:intel_atomic_commit_tail [i915]] [CRTC:37:pipe A]
>[ 2366.940569] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[ 2366.941154] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 00 00 04 00 0f 00 04
>[ 2366.942562] [drm:intel_power_well_disable [i915]] disabling power well 2
>[ 2366.942617] [drm:intel_power_well_disable [i915]] disabling DC off
>[ 2366.942669] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[ 2366.942718] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[ 2366.942791] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[ 2366.942855] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[ 2366.942905] [drm:intel_power_well_enable [i915]] enabling DC off
>[ 2366.942953] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[ 2366.943005] [drm:intel_power_well_enable [i915]] enabling power well 2
>[ 2366.943485] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 00 00 04 00 0f 00 04
>[ 2366.944905] [drm:intel_power_well_disable [i915]] disabling power well 2
>[ 2366.944953] [drm:intel_power_well_disable [i915]] disabling DC off
>[ 2366.944997] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[ 2366.945039] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[ 2366.980035] [drm:intel_power_well_enable [i915]] enabling DC off
>[ 2366.980088] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[ 2366.980177] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[ 2366.980323] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006f
>[ 2367.180031] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped
>[ 2367.430021] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped
>[ 2367.696692] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped
>[ 2367.946685] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped
>[ 2368.230021] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped
>[ 2371.292257] [drm:edp_panel_vdd_off_sync [i915]] Turning eDP port A VDD off
>[ 2371.292404] [drm:edp_panel_vdd_off_sync [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x00000067
>[ 2371.292461] [drm:intel_power_well_disable [i915]] disabling DC off
>[ 2371.292518] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[ 2371.292570] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[ 2372.457898] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 2372.457979] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 2372.458103] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[ 2372.458170] [drm:intel_power_well_enable [i915]] enabling DC off
>[ 2372.458238] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[ 2372.458318] [drm:intel_power_well_enable [i915]] enabling power well 2
>[ 2372.720725] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 2372.720807] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 2378.292741] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 2378.292822] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 2378.460157] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [CRTC:37:pipe A] flip_done timed out
>[ 2378.552473] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 2378.552555] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 2384.116372] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 2384.116453] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 2384.377649] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 2384.377730] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 2388.700145] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [PLANE:28:plane 1A] flip_done timed out
>[ 2389.946178] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 2389.946260] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 2390.205767] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 2390.205849] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 2395.778492] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 2395.778573] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 2396.038979] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 2396.039060] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 2398.940153] [drm:drm_atomic_helper_wait_for_flip_done [drm_kms_helper]] *ERROR* [CRTC:37:pipe A] flip_done timed out
>[ 2398.940435] [IGT] kms_frontbuffer_tracking: exiting, ret=0
>[ 2398.940504] Setting dangerous option enable_psr - tainting kernel
>[ 2398.940519] Setting dangerous option enable_fbc - tainting kernel
>[ 2398.940762] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 00 00 04 00 0f 00 04
>[ 2398.942334] [drm:intel_power_well_disable [i915]] disabling power well 2
>[ 2398.942391] [drm:intel_power_well_disable [i915]] disabling DC off
>[ 2398.942443] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[ 2398.942492] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[ 2398.942566] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[ 2398.942614] [drm:intel_power_well_enable [i915]] enabling DC off
>[ 2398.942661] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[ 2398.942712] [drm:intel_power_well_enable [i915]] enabling power well 2
>[ 2398.943195] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 00 00 04 00 0f 00 04
>[ 2398.944616] [drm:intel_power_well_disable [i915]] disabling power well 2
>[ 2398.944663] [drm:intel_power_well_disable [i915]] disabling DC off
>[ 2398.944707] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[ 2398.944749] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[ 2398.980176] [drm:intel_atomic_check [i915]] [CONNECTOR:57:DP-1] checking for sink bpp constrains
>[ 2398.980191] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 2398.980206] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 148500KHz
>[ 2398.980221] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 2398.980233] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 648000
>[ 2398.980247] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 2398.980261] [drm:intel_dump_pipe_config [i915]] [CRTC:47:pipe B][modeset]
>[ 2398.980273] [drm:intel_dump_pipe_config [i915]] output_types: DP (0x80)
>[ 2398.980286] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 2398.980298] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5767168, gmch_n: 8388608, link_m: 240298, link_n: 262144, tu: 64
>[ 2398.980309] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[ 2398.980321] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 2398.980329] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[ 2398.980340] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 2398.980346] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[ 2398.980359] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[ 2398.980370] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1080, pixel rate 148500
>[ 2398.980382] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[ 2398.980393] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 2398.980404] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 2398.980415] [drm:intel_dump_pipe_config [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[ 2398.980426] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 2398.980438] [drm:intel_dump_pipe_config [i915]] [PLANE:38:plane 1B] disabled, scaler_id = -1
>[ 2398.980449] [drm:intel_dump_pipe_config [i915]] [PLANE:41:plane 2B] disabled, scaler_id = -1
>[ 2398.980460] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor B] disabled, scaler_id = -1
>[ 2398.980473] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 2398.980486] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[ 2398.980502] [drm:intel_find_shared_dpll [i915]] [CRTC:47:pipe B] allocated DPLL 1
>[ 2398.980514] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[ 2401.607896] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 2401.607978] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 2401.608100] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[ 2401.608165] [drm:intel_power_well_enable [i915]] enabling DC off
>[ 2401.608236] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[ 2401.608316] [drm:intel_power_well_enable [i915]] enabling power well 2
>[ 2401.868938] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 2401.869020] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 2407.443312] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 2407.443394] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 2407.703382] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 2407.703463] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 2409.180180] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [CRTC:37:pipe A] flip_done timed out
>[ 2413.271031] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 2413.271112] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 2413.532570] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 2413.532652] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 2419.099899] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 2419.099981] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 2419.360730] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 2419.360811] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 2419.420254] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [CONNECTOR:49:eDP-1] flip_done timed out
>[ 2424.933357] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 2424.933438] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 2425.193351] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 2425.193432] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 2429.660225] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [PLANE:28:plane 1A] flip_done timed out
>[ 2429.660319] [drm:intel_disable_sagv [i915]] Disabling the SAGV
>[ 2429.660407] [drm:intel_atomic_commit_tail [i915]] [ENCODER:48:DDI A]
>[ 2429.660481] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI B]
>[ 2429.660550] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[ 2429.660616] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[ 2429.660679] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DDI C]
>[ 2429.660740] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST A]
>[ 2429.660800] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST B]
>[ 2429.660860] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI D]
>[ 2429.660920] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[ 2429.660978] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[ 2429.661044] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[ 2429.661111] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[ 2429.661176] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[ 2429.661238] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[ 2429.661313] [drm:intel_fbc_enable [i915]] reserved 16588800 bytes of contiguous stolen space for FBC, threshold: 1
>[ 2429.661380] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 2429.662074] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 2, on? 0) for crtc 47
>[ 2429.662151] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[ 2429.662266] [drm:intel_power_well_enable [i915]] enabling DDI B IO power well
>[ 2429.662882] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 2429.664148] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 2429.665411] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 2429.666661] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 2429.667950] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 2429.668853] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[ 2429.669853] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 2429.669921] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 2429.669984] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 2429.670046] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 2429.688666] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 2429.688680] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[ 2429.706415] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 2429.706752] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:57:DP-1] Link Training Passed at Link Rate = 162000, Lane count = 4
>[ 2429.707134] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 2429.707189] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS
>[ 2430.781750] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 2430.781831] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 2431.045082] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 2431.045163] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 2439.900158] [drm:drm_atomic_helper_wait_for_flip_done [drm_kms_helper]] *ERROR* [CRTC:37:pipe A] flip_done timed out
>[ 2439.900321] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:57:DP-1]
>[ 2439.900416] [drm:intel_atomic_commit_tail [i915]] [CRTC:47:pipe B]
>[ 2439.900511] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[ 2439.901108] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 00 00 04 00 0f 00 04
>[ 2439.902489] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[ 2439.902884] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 00 00 04 00 0f 00 04
>[ 2439.981255] [IGT] kms_frontbuffer_tracking: executing
>[ 2440.029898] [drm:drm_mode_addfb2 [drm]] [FB:75]
>[ 2440.029939] [drm:drm_mode_addfb2 [drm]] [FB:91]
>[ 2440.029977] [drm:drm_mode_addfb2 [drm]] [FB:92]
>[ 2440.030511] [drm:drm_mode_addfb2 [drm]] [FB:93]
>[ 2440.034327] [drm:drm_mode_addfb2 [drm]] [FB:94]
>[ 2440.035185] [drm:drm_mode_addfb2 [drm]] [FB:96]
>[ 2440.035205] [drm:drm_mode_addfb2 [drm]] [FB:98]
>[ 2440.035227] [drm:drm_mode_addfb2 [drm]] [FB:102]
>[ 2440.035392] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[ 2440.035398] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[ 2450.140254] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [CRTC:37:pipe A] flip_done timed out
>[ 2460.380122] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [CONNECTOR:49:eDP-1] flip_done timed out
>[ 2470.620253] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [PLANE:28:plane 1A] flip_done timed out
>[ 2480.859979] [drm:drm_atomic_helper_wait_for_flip_done [drm_kms_helper]] *ERROR* [CRTC:37:pipe A] flip_done timed out
>[ 2480.860181] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[ 2480.860341] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006f
>[ 2481.061378] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped
>[ 2481.061603] [IGT] kms_frontbuffer_tracking: starting subtest psr-1p-offscren-pri-indfb-draw-render
>[ 2481.061678] Setting dangerous option enable_fbc - tainting kernel
>[ 2481.061700] Setting dangerous option enable_psr - tainting kernel
>[ 2484.188249] [drm:edp_panel_vdd_off_sync [i915]] Turning eDP port A VDD off
>[ 2484.188392] [drm:edp_panel_vdd_off_sync [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x00000067
>[ 2491.100144] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [CRTC:37:pipe A] flip_done timed out
>[ 2501.340163] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [PLANE:28:plane 1A] flip_done timed out
>[ 2511.580124] [drm:drm_atomic_helper_wait_for_flip_done [drm_kms_helper]] *ERROR* [CRTC:37:pipe A] flip_done timed out
>[ 2511.584518] [drm:drm_mode_addfb2 [drm]] [FB:72]
>[ 2511.584622] [drm:drm_mode_addfb2 [drm]] [FB:75]
>[ 2511.584728] [drm:drm_mode_addfb2 [drm]] [FB:91]
>[ 2511.585638] [drm:drm_mode_addfb2 [drm]] [FB:92]
>[ 2511.589366] [drm:drm_mode_addfb2 [drm]] [FB:93]
>[ 2511.590209] [drm:drm_mode_addfb2 [drm]] [FB:94]
>[ 2511.590230] [drm:drm_mode_addfb2 [drm]] [FB:96]
>[ 2511.590250] [drm:drm_mode_addfb2 [drm]] [FB:98]
>[ 2511.590358] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[ 2511.590392] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 2511.590407] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[ 2521.820273] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [CRTC:37:pipe A] flip_done timed out
>[ 2532.060131] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [CONNECTOR:49:eDP-1] flip_done timed out
>[ 2542.300151] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [PLANE:28:plane 1A] flip_done timed out
>[ 2542.300276] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[ 2542.300430] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006f
>[ 2542.300706] [drm:intel_edp_backlight_off [i915]] 
>[ 2542.508214] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0
>[ 2542.508354] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 2542.511231] [drm:intel_edp_panel_off.part.31 [i915]] Turn eDP port A panel power off
>[ 2542.511339] [drm:intel_edp_panel_off.part.31 [i915]] Wait for panel power off time
>[ 2542.511469] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000003 control 00000060
>[ 2542.561710] [drm:wait_panel_status [i915]] Wait complete
>[ 2542.561773] [drm:intel_power_well_disable [i915]] disabling DDI A/E IO power well
>[ 2542.561856] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 2542.561936] [drm:intel_disable_shared_dpll [i915]] disable DPLL 0 (active 1, on? 1) for crtc 37
>[ 2542.562009] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 0
>[ 2542.562102] [drm:intel_atomic_commit_tail [i915]] [ENCODER:48:DDI A]
>[ 2542.562172] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI B]
>[ 2542.562239] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[ 2542.562303] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[ 2542.562365] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DDI C]
>[ 2542.562427] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST A]
>[ 2542.562489] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST B]
>[ 2542.562549] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI D]
>[ 2542.562609] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[ 2542.562668] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[ 2542.562734] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:49:eDP-1]
>[ 2542.562800] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[ 2542.562865] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[ 2542.562928] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[ 2542.562991] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[ 2542.571311] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010
>[ 2542.571392] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[ 2542.571468] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0
>[ 2542.571589] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[ 2542.574547] [drm:intel_atomic_commit_tail [i915]] [CRTC:37:pipe A]
>[ 2542.574618] [drm:intel_enable_sagv [i915]] Enabling the SAGV
>[ 2542.574730] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[ 2542.574830] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 2542.574903] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[ 2542.575014] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 2542.591963] [drm:intel_power_well_disable [i915]] disabling DDI B IO power well
>[ 2542.592046] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 2, on? 1) for crtc 47
>[ 2542.592118] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[ 2542.592208] [drm:intel_atomic_commit_tail [i915]] [ENCODER:48:DDI A]
>[ 2542.592274] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI B]
>[ 2542.592339] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[ 2542.592400] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[ 2542.592460] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DDI C]
>[ 2542.592518] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST A]
>[ 2542.592574] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST B]
>[ 2542.592630] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI D]
>[ 2542.592686] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[ 2542.592741] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[ 2542.592804] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:57:DP-1]
>[ 2542.592867] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[ 2542.592928] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[ 2542.592988] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[ 2542.593046] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[ 2542.593106] [drm:intel_power_well_disable [i915]] disabling power well 2
>[ 2542.593178] [drm:intel_atomic_commit_tail [i915]] [CRTC:47:pipe B]
>[ 2542.593232] [drm:intel_power_well_disable [i915]] disabling DC off
>[ 2542.593283] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[ 2542.593331] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[ 2542.593771] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 2542.596471] [drm:drm_mode_addfb2 [drm]] [FB:73]
>[ 2542.598195] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[ 2542.598201] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[ 2542.598222] [drm:intel_atomic_check [i915]] [CONNECTOR:49:eDP-1] checking for sink bpp constrains
>[ 2542.598235] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 2542.598241] [drm:drm_mode_debug_printmodeline [drm]] Modeline 52:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[ 2542.598255] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 138780KHz
>[ 2542.598271] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24
>[ 2542.598282] [drm:intel_dp_compute_config [i915]] DP link bw required 416340 available 540000
>[ 2542.598294] [drm:intel_dp_compute_config [i915]] PSR disable by flag
>[ 2542.598306] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 2542.598319] [drm:intel_dump_pipe_config [i915]] [CRTC:37:pipe A][modeset]
>[ 2542.598331] [drm:intel_dump_pipe_config [i915]] output_types: EDP (0x100)
>[ 2542.598342] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0
>[ 2542.598354] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 6467616, gmch_n: 8388608, link_m: 269484, link_n: 524288, tu: 64
>[ 2542.598365] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[ 2542.598375] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 2542.598381] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[ 2542.598392] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 2542.598397] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[ 2542.598408] [drm:intel_dump_pipe_config [i915]] crtc timings: 138780 1920 1966 1996 2080 1080 1082 1086 1112, type: 0x48 flags: 0xa
>[ 2542.598419] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 138780
>[ 2542.598430] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[ 2542.598440] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 2542.598451] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 2542.598461] [drm:intel_dump_pipe_config [i915]] dpll_hw_state: ctrl1: 0x3, cfgcr1: 0x0, cfgcr2: 0x0
>[ 2542.598471] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 2542.598482] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 1A] disabled, scaler_id = -1
>[ 2542.598492] [drm:intel_dump_pipe_config [i915]] [PLANE:31:plane 2A] disabled, scaler_id = -1
>[ 2542.598502] [drm:intel_dump_pipe_config [i915]] [PLANE:34:cursor A] disabled, scaler_id = -1
>[ 2542.598515] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 2542.598527] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[ 2542.598541] [drm:intel_find_shared_dpll [i915]] [CRTC:37:pipe A] allocated DPLL 0
>[ 2542.598553] [drm:intel_reference_shared_dpll [i915]] using DPLL 0 for pipe A
>[ 2542.599068] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 2542.599077] [drm:intel_power_well_enable [i915]] enabling DC off
>[ 2542.599352] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[ 2542.599369] [drm:intel_atomic_commit_tail [i915]] [ENCODER:48:DDI A]
>[ 2542.599382] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI B]
>[ 2542.599395] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[ 2542.599407] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[ 2542.599420] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DDI C]
>[ 2542.599434] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST A]
>[ 2542.599452] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST B]
>[ 2542.599487] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI D]
>[ 2542.599503] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[ 2542.599519] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[ 2542.599532] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[ 2542.599544] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[ 2542.599555] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[ 2542.599567] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[ 2542.599580] [drm:intel_enable_shared_dpll [i915]] enable DPLL 0 (active 1, on? 0) for crtc 37
>[ 2542.599592] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 0
>[ 2542.599611] [drm:edp_panel_on [i915]] Turn eDP port A panel power on
>[ 2542.599636] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle
>[ 2543.196399] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 00000000 control 00000060
>[ 2543.196506] [drm:wait_panel_status [i915]] Wait complete
>[ 2543.196645] [drm:edp_panel_on [i915]] Wait for panel power on
>[ 2543.196776] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 00000063
>[ 2543.230276] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010
>[ 2543.230357] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[ 2543.230431] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1
>[ 2543.230575] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[ 2543.396839] [drm:wait_panel_status [i915]] Wait complete
>[ 2543.396905] [drm:intel_power_well_enable [i915]] enabling DDI A/E IO power well
>[ 2543.397007] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[ 2543.397157] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b
>[ 2543.398354] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 2543.398416] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 2543.398476] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 2543.398536] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 2543.399248] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 2543.399306] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 2543.400287] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 2543.400313] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:49:eDP-1] Link Training Passed at Link Rate = 270000, Lane count = 2
>[ 2543.400692] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 2543.400725] [drm:intel_edp_backlight_on [i915]] 
>[ 2543.400737] [drm:intel_panel_enable_backlight [i915]] pipe A
>[ 2543.400776] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 120000
>[ 2543.408029] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS
>[ 2546.652090] [drm:edp_panel_vdd_off_sync [i915]] Turning eDP port A VDD off
>[ 2546.652238] [drm:edp_panel_vdd_off_sync [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x00000067
>[ 2553.564228] [drm:drm_atomic_helper_wait_for_flip_done [drm_kms_helper]] *ERROR* [CRTC:37:pipe A] flip_done timed out
>[ 2553.564348] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:49:eDP-1]
>[ 2553.564433] [drm:intel_atomic_commit_tail [i915]] [CRTC:37:pipe A]
>[ 2553.564529] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[ 2553.564593] [drm:intel_power_well_disable [i915]] disabling DC off
>[ 2553.564649] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[ 2553.564702] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[ 2553.601043] [drm:intel_power_well_enable [i915]] enabling DC off
>[ 2553.601103] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[ 2553.601200] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[ 2553.601353] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006f
>[ 2553.801017] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped
>[ 2553.801096] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[ 2553.801189] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 2553.801251] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[ 2556.892234] [drm:edp_panel_vdd_off_sync [i915]] Turning eDP port A VDD off
>[ 2556.892379] [drm:edp_panel_vdd_off_sync [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x00000067
>[ 2556.892437] [drm:intel_power_well_disable [i915]] disabling DC off
>[ 2556.892494] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[ 2556.892547] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[ 2563.328888] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 2563.328969] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 2563.329095] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[ 2563.329162] [drm:intel_power_well_enable [i915]] enabling DC off
>[ 2563.329232] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[ 2563.329314] [drm:intel_power_well_enable [i915]] enabling power well 2
>[ 2563.598060] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 2563.598142] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 2563.804136] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [CRTC:37:pipe A] flip_done timed out
>[ 2568.358951] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 2568.359034] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 2568.641852] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 2568.641933] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 2574.044153] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [CONNECTOR:49:eDP-1] flip_done timed out
>[ 2574.201457] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 2574.201539] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 2574.470610] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 2574.470692] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 2580.044134] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 2580.044215] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 2580.313401] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 2580.313482] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 2584.284008] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [PLANE:28:plane 1A] flip_done timed out
>[ 2584.284113] [drm:intel_edp_backlight_off [i915]] 
>[ 2584.492206] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0
>[ 2584.492340] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 2584.500501] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[ 2584.500658] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b
>[ 2584.500932] [drm:intel_edp_panel_off.part.31 [i915]] Turn eDP port A panel power off
>[ 2584.501035] [drm:intel_edp_panel_off.part.31 [i915]] Wait for panel power off time
>[ 2584.501161] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000003 control 00000060
>[ 2584.551317] [drm:wait_panel_status [i915]] Wait complete
>[ 2584.551381] [drm:intel_power_well_disable [i915]] disabling DDI A/E IO power well
>[ 2584.551467] [drm:intel_disable_shared_dpll [i915]] disable DPLL 0 (active 1, on? 1) for crtc 37
>[ 2584.551543] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 0
>[ 2584.551635] [drm:intel_atomic_commit_tail [i915]] [ENCODER:48:DDI A]
>[ 2584.551708] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI B]
>[ 2584.551775] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[ 2584.551839] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[ 2584.551901] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DDI C]
>[ 2584.552005] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST A]
>[ 2584.552073] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST B]
>[ 2584.552145] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI D]
>[ 2584.552209] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[ 2584.552276] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[ 2584.552351] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:49:eDP-1]
>[ 2584.552424] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[ 2584.552491] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[ 2584.552563] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[ 2584.552626] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[ 2584.552706] [drm:intel_atomic_commit_tail [i915]] [CRTC:37:pipe A]
>[ 2584.552825] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[ 2584.553282] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 00 00 04 00 0f 00 04
>[ 2584.561214] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010
>[ 2584.561286] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[ 2584.561352] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0
>[ 2584.581754] [drm:intel_power_well_disable [i915]] disabling power well 2
>[ 2584.581808] [drm:intel_power_well_disable [i915]] disabling DC off
>[ 2584.581854] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[ 2584.581898] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[ 2584.582333] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 2584.582399] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[ 2584.582461] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[ 2584.582505] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 2584.582547] [drm:intel_power_well_enable [i915]] enabling DC off
>[ 2584.582835] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[ 2584.582881] [drm:intel_power_well_enable [i915]] enabling power well 2
>[ 2584.583357] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 00 00 04 00 0f 00 04
>[ 2584.584755] [drm:intel_power_well_disable [i915]] disabling power well 2
>[ 2584.584804] [drm:intel_power_well_disable [i915]] disabling DC off
>[ 2584.584848] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[ 2584.584890] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[ 2584.585328] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 2584.586500] [drm:drm_mode_addfb2 [drm]] [FB:73]
>[ 2584.587473] [drm:drm_mode_addfb2 [drm]] [FB:102]
>[ 2584.588651] [drm:drm_mode_addfb2 [drm]] [FB:103]
>[ 2584.589487] [drm:drm_mode_addfb2 [drm]] [FB:104]
>[ 2584.660586] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[ 2584.660594] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[ 2584.660620] [drm:intel_atomic_check [i915]] [CONNECTOR:49:eDP-1] checking for sink bpp constrains
>[ 2584.660633] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 2584.660640] [drm:drm_mode_debug_printmodeline [drm]] Modeline 52:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[ 2584.660654] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 138780KHz
>[ 2584.660670] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24
>[ 2584.660681] [drm:intel_dp_compute_config [i915]] DP link bw required 416340 available 540000
>[ 2584.660693] [drm:intel_dp_compute_config [i915]] PSR disable by flag
>[ 2584.660706] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 2584.660718] [drm:intel_dump_pipe_config [i915]] [CRTC:37:pipe A][modeset]
>[ 2584.660730] [drm:intel_dump_pipe_config [i915]] output_types: EDP (0x100)
>[ 2584.660742] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0
>[ 2584.660753] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 6467616, gmch_n: 8388608, link_m: 269484, link_n: 524288, tu: 64
>[ 2584.660764] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[ 2584.660775] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 2584.660780] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[ 2584.660791] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 2584.660797] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[ 2584.660808] [drm:intel_dump_pipe_config [i915]] crtc timings: 138780 1920 1966 1996 2080 1080 1082 1086 1112, type: 0x48 flags: 0xa
>[ 2584.660819] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 138780
>[ 2584.660829] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[ 2584.660840] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 2584.660850] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 2584.660861] [drm:intel_dump_pipe_config [i915]] dpll_hw_state: ctrl1: 0x3, cfgcr1: 0x0, cfgcr2: 0x0
>[ 2584.660871] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 2584.660881] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 1A] disabled, scaler_id = -1
>[ 2584.660891] [drm:intel_dump_pipe_config [i915]] [PLANE:31:plane 2A] disabled, scaler_id = -1
>[ 2584.660901] [drm:intel_dump_pipe_config [i915]] [PLANE:34:cursor A] disabled, scaler_id = -1
>[ 2584.660914] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 2584.660926] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[ 2584.660940] [drm:intel_find_shared_dpll [i915]] [CRTC:37:pipe A] allocated DPLL 0
>[ 2584.660952] [drm:intel_reference_shared_dpll [i915]] using DPLL 0 for pipe A
>[ 2584.661911] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 2584.661921] [drm:intel_power_well_enable [i915]] enabling DC off
>[ 2584.662213] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[ 2584.662231] [drm:intel_atomic_commit_tail [i915]] [ENCODER:48:DDI A]
>[ 2584.662245] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI B]
>[ 2584.662258] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[ 2584.662271] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[ 2584.662283] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DDI C]
>[ 2584.662294] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST A]
>[ 2584.662306] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST B]
>[ 2584.662317] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI D]
>[ 2584.662328] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[ 2584.662341] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[ 2584.662354] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[ 2584.662367] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[ 2584.662395] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[ 2584.662406] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[ 2584.662420] [drm:intel_enable_shared_dpll [i915]] enable DPLL 0 (active 1, on? 0) for crtc 37
>[ 2584.662431] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 0
>[ 2584.662451] [drm:edp_panel_on [i915]] Turn eDP port A panel power on
>[ 2584.662475] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle
>[ 2585.180083] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 00000000 control 00000060
>[ 2585.180167] [drm:wait_panel_status [i915]] Wait complete
>[ 2585.180290] [drm:edp_panel_on [i915]] Wait for panel power on
>[ 2585.180409] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 00000063
>[ 2585.213664] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010
>[ 2585.213736] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[ 2585.213802] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1
>[ 2585.213901] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[ 2585.382405] [drm:wait_panel_status [i915]] Wait complete
>[ 2585.382471] [drm:intel_power_well_enable [i915]] enabling DDI A/E IO power well
>[ 2585.382574] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[ 2585.382724] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b
>[ 2585.383987] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 2585.384066] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 2585.384142] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 2585.384210] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 2585.384943] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 2585.385005] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 2585.386015] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 2585.386077] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:49:eDP-1] Link Training Passed at Link Rate = 270000, Lane count = 2
>[ 2585.386731] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 2585.386826] [drm:intel_edp_backlight_on [i915]] 
>[ 2585.386882] [drm:intel_panel_enable_backlight [i915]] pipe A
>[ 2585.386965] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 120000
>[ 2585.392024] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS
>[ 2585.872237] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 2585.872319] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 2585.872444] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[ 2585.872509] [drm:intel_power_well_enable [i915]] enabling power well 2
>[ 2586.131854] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 2586.131937] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 2588.636343] [drm:edp_panel_vdd_off_sync [i915]] Turning eDP port A VDD off
>[ 2588.636488] [drm:edp_panel_vdd_off_sync [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x00000067
>[ 2591.703833] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 2591.703915] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 2591.963763] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 2591.963844] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 2595.548151] [drm:drm_atomic_helper_wait_for_flip_done [drm_kms_helper]] *ERROR* [CRTC:37:pipe A] flip_done timed out
>[ 2595.548273] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:49:eDP-1]
>[ 2595.548355] [drm:intel_atomic_commit_tail [i915]] [CRTC:37:pipe A]
>[ 2595.548452] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[ 2595.549036] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 00 00 04 00 0f 00 04
>[ 2595.550458] [drm:intel_power_well_disable [i915]] disabling power well 2
>[ 2595.550508] [drm:intel_power_well_disable [i915]] disabling DC off
>[ 2595.550554] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[ 2595.550597] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[ 2595.550664] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[ 2595.550706] [drm:intel_power_well_enable [i915]] enabling DC off
>[ 2595.550749] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[ 2595.550795] [drm:intel_power_well_enable [i915]] enabling power well 2
>[ 2595.551268] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 00 00 04 00 0f 00 04
>[ 2595.552677] [drm:intel_power_well_disable [i915]] disabling power well 2
>[ 2595.552724] [drm:intel_power_well_disable [i915]] disabling DC off
>[ 2595.552769] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[ 2595.552811] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[ 2595.586970] [drm:intel_power_well_enable [i915]] enabling DC off
>[ 2595.587030] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[ 2595.587127] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[ 2595.587280] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006f
>[ 2595.787033] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped
>[ 2595.787084] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[ 2595.787114] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[ 2597.539681] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 2597.539762] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 2597.539882] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[ 2597.539967] [drm:intel_power_well_enable [i915]] enabling power well 2
>[ 2597.801882] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 2597.801964] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 2598.876194] [drm:edp_panel_vdd_off_sync [i915]] Turning eDP port A VDD off
>[ 2598.876338] [drm:edp_panel_vdd_off_sync [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x00000067
>[ 2603.372162] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 2603.372244] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 2603.631562] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 2603.631644] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 2606.044253] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [CRTC:37:pipe A] flip_done timed out
>[ 2609.195299] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 2609.195380] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 2609.456582] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 2609.456664] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 2615.029618] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 2615.029698] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 2615.290607] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 2615.290689] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 2616.284245] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [CONNECTOR:49:eDP-1] flip_done timed out
>[ 2620.866727] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 2620.866808] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 2621.129392] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 2621.129473] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 2626.524133] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [PLANE:28:plane 1A] flip_done timed out
>[ 2626.698159] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 2626.698240] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 2626.961286] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 2626.961367] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 2632.531450] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 2632.531531] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 2632.792414] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 2632.792495] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 2636.763944] [drm:drm_atomic_helper_wait_for_flip_done [drm_kms_helper]] *ERROR* [CRTC:37:pipe A] flip_done timed out
>[ 2636.764532] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 00 00 04 00 0f 00 04
>[ 2636.765929] [drm:intel_power_well_disable [i915]] disabling power well 2
>[ 2636.765980] [drm:intel_power_well_disable [i915]] disabling DC off
>[ 2636.766026] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[ 2636.766070] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[ 2636.766137] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[ 2636.766180] [drm:intel_power_well_enable [i915]] enabling DC off
>[ 2636.766223] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[ 2636.766269] [drm:intel_power_well_enable [i915]] enabling power well 2
>[ 2636.766742] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 00 00 04 00 0f 00 04
>[ 2636.768173] [drm:intel_power_well_disable [i915]] disabling power well 2
>[ 2636.768221] [drm:intel_power_well_disable [i915]] disabling DC off
>[ 2636.768266] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[ 2636.768310] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[ 2636.802894] [drm:intel_power_well_enable [i915]] enabling DC off
>[ 2636.802947] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[ 2636.803037] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[ 2636.803181] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006f
>[ 2637.002984] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped
>[ 2637.003034] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[ 2637.003065] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[ 2638.353745] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 2638.353826] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 2638.353946] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[ 2638.354013] [drm:intel_power_well_enable [i915]] enabling power well 2
>[ 2638.613442] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 2638.613523] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 2640.092230] [drm:edp_panel_vdd_off_sync [i915]] Turning eDP port A VDD off
>[ 2640.092372] [drm:edp_panel_vdd_off_sync [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x00000067
>[ 2644.176606] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 2644.176687] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 2644.436909] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 2644.436991] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 2647.260248] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [CRTC:37:pipe A] flip_done timed out
>[ 2650.006685] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 2650.006766] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 2650.266882] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 2650.266963] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 2655.839064] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 2655.839145] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 2656.098909] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 2656.098992] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 2657.500247] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [CONNECTOR:49:eDP-1] flip_done timed out
>[ 2661.660427] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 2661.660508] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 2661.919970] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 2661.920052] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 2667.479617] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 2667.479698] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 2667.740134] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [PLANE:28:plane 1A] flip_done timed out
>[ 2667.741251] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 2667.741331] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 2673.309822] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 2673.309903] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 2673.570800] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 2673.570882] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 2677.980159] [drm:drm_atomic_helper_wait_for_flip_done [drm_kms_helper]] *ERROR* [CRTC:37:pipe A] flip_done timed out
>[ 2677.980756] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 00 00 04 00 0f 00 04
>[ 2677.982161] [drm:intel_power_well_disable [i915]] disabling power well 2
>[ 2677.982219] [drm:intel_power_well_disable [i915]] disabling DC off
>[ 2677.982270] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[ 2677.982319] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[ 2677.982394] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[ 2677.982441] [drm:intel_power_well_enable [i915]] enabling DC off
>[ 2677.982489] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[ 2677.982540] [drm:intel_power_well_enable [i915]] enabling power well 2
>[ 2677.983025] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 00 00 04 00 0f 00 04
>[ 2677.984470] [drm:intel_power_well_disable [i915]] disabling power well 2
>[ 2677.984523] [drm:intel_power_well_disable [i915]] disabling DC off
>[ 2677.984571] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[ 2677.984618] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[ 2678.018660] [drm:intel_power_well_enable [i915]] enabling DC off
>[ 2678.018713] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[ 2678.018801] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[ 2678.018945] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006f
>[ 2678.218930] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped
>[ 2678.218980] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[ 2678.219011] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[ 2679.145404] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 2679.145485] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 2679.145607] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[ 2679.145674] [drm:intel_power_well_enable [i915]] enabling power well 2
>[ 2679.406093] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 2679.406174] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 2681.308327] [drm:edp_panel_vdd_off_sync [i915]] Turning eDP port A VDD off
>[ 2681.308473] [drm:edp_panel_vdd_off_sync [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x00000067
>[ 2684.976250] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 2684.976332] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 2685.237040] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 2685.237121] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 2688.476151] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [CRTC:37:pipe A] flip_done timed out
>[ 2690.799851] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 2690.799932] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 2691.059488] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 2691.059569] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 2696.627556] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 2696.627637] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 2696.888600] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 2696.888682] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 2698.716250] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [CONNECTOR:49:eDP-1] flip_done timed out
>[ 2702.458825] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 2702.458906] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 2702.720787] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 2702.720868] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 2708.285562] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 2708.285645] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 2708.544996] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 2708.545077] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 2708.956237] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [PLANE:28:plane 1A] flip_done timed out
>[ 2714.115300] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 2714.115381] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 2714.376389] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 2714.376470] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 2719.196246] [drm:drm_atomic_helper_wait_for_flip_done [drm_kms_helper]] *ERROR* [CRTC:37:pipe A] flip_done timed out
>[ 2719.196844] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 00 00 04 00 0f 00 04
>[ 2719.198250] [drm:intel_power_well_disable [i915]] disabling power well 2
>[ 2719.198307] [drm:intel_power_well_disable [i915]] disabling DC off
>[ 2719.198373] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[ 2719.198416] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[ 2719.198484] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[ 2719.198527] [drm:intel_power_well_enable [i915]] enabling DC off
>[ 2719.198569] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[ 2719.198615] [drm:intel_power_well_enable [i915]] enabling power well 2
>[ 2719.199088] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 00 00 04 00 0f 00 04
>[ 2719.200503] [drm:intel_power_well_disable [i915]] disabling power well 2
>[ 2719.200555] [drm:intel_power_well_disable [i915]] disabling DC off
>[ 2719.200603] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[ 2719.200650] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[ 2719.234618] [drm:intel_power_well_enable [i915]] enabling DC off
>[ 2719.234670] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[ 2719.234757] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[ 2719.234904] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006f
>[ 2719.434892] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped
>[ 2719.435023] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[ 2719.435118] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 2719.435181] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[ 2719.949037] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 2719.949118] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 2719.949237] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[ 2719.949304] [drm:intel_power_well_enable [i915]] enabling power well 2
>[ 2720.207986] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 2720.208067] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 2722.524329] [drm:edp_panel_vdd_off_sync [i915]] Turning eDP port A VDD off
>[ 2722.524472] [drm:edp_panel_vdd_off_sync [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x00000067
>[ 2725.771528] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 2725.771610] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 2726.033903] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 2726.033984] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 2729.436102] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [CRTC:37:pipe A] flip_done timed out
>[ 2731.610783] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 2731.610865] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 2731.871062] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 2731.871143] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 2737.431267] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 2737.431348] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 2737.693457] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 2737.693539] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 2739.675973] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [CONNECTOR:49:eDP-1] flip_done timed out
>[ 2743.266833] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 2743.266913] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 2743.526507] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 2743.526590] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 2749.088416] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 2749.088498] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 2749.348468] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 2749.348549] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 2749.916146] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [PLANE:28:plane 1A] flip_done timed out
>[ 2749.916253] [drm:intel_edp_backlight_off [i915]] 
>[ 2750.124300] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0
>[ 2750.124440] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 2750.135712] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[ 2750.135871] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b
>[ 2750.136180] [drm:intel_edp_panel_off.part.31 [i915]] Turn eDP port A panel power off
>[ 2750.136283] [drm:intel_edp_panel_off.part.31 [i915]] Wait for panel power off time
>[ 2750.136409] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000003 control 00000060
>[ 2750.186700] [drm:wait_panel_status [i915]] Wait complete
>[ 2750.186764] [drm:intel_power_well_disable [i915]] disabling DDI A/E IO power well
>[ 2750.186851] [drm:intel_disable_shared_dpll [i915]] disable DPLL 0 (active 1, on? 1) for crtc 37
>[ 2750.186924] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 0
>[ 2750.187015] [drm:intel_atomic_commit_tail [i915]] [ENCODER:48:DDI A]
>[ 2750.187086] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI B]
>[ 2750.187152] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[ 2750.187217] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[ 2750.187280] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DDI C]
>[ 2750.187341] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST A]
>[ 2750.187402] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST B]
>[ 2750.187461] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI D]
>[ 2750.187521] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[ 2750.187580] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[ 2750.187646] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:49:eDP-1]
>[ 2750.187713] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[ 2750.187777] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[ 2750.187839] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[ 2750.187900] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[ 2750.188013] [drm:intel_atomic_commit_tail [i915]] [CRTC:37:pipe A]
>[ 2750.188139] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[ 2750.188601] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 00 00 04 00 0f 00 04
>[ 2750.189927] [drm:intel_power_well_disable [i915]] disabling power well 2
>[ 2750.189939] [drm:intel_power_well_disable [i915]] disabling DC off
>[ 2750.189963] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[ 2750.189972] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[ 2750.189982] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 2750.189983] Setting dangerous option enable_psr - tainting kernel
>[ 2750.189995] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[ 2750.190004] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 2750.190012] [drm:intel_power_well_enable [i915]] enabling DC off
>[ 2750.190372] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[ 2750.190929] [drm:intel_power_well_enable [i915]] enabling power well 2
>[ 2750.190940] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[ 2750.191327] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 00 00 04 00 0f 00 04
>[ 2750.192598] [drm:intel_power_well_disable [i915]] disabling power well 2
>[ 2750.192604] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[ 2750.192633] [drm:intel_power_well_disable [i915]] disabling DC off
>[ 2750.192648] [drm:intel_atomic_check [i915]] [CONNECTOR:49:eDP-1] checking for sink bpp constrains
>[ 2750.192662] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 2750.192669] [drm:drm_mode_debug_printmodeline [drm]] Modeline 52:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[ 2750.192677] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[ 2750.192686] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[ 2750.192700] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 138780KHz
>[ 2750.192710] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 2750.192723] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24
>[ 2750.192735] [drm:intel_dp_compute_config [i915]] DP link bw required 416340 available 540000
>[ 2750.192748] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 2750.192760] [drm:intel_dump_pipe_config [i915]] [CRTC:37:pipe A][modeset]
>[ 2750.192772] [drm:intel_dump_pipe_config [i915]] output_types: EDP (0x100)
>[ 2750.192784] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0
>[ 2750.192795] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 6467616, gmch_n: 8388608, link_m: 269484, link_n: 524288, tu: 64
>[ 2750.192806] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[ 2750.192817] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 2750.192823] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[ 2750.192834] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 2750.192839] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[ 2750.192850] [drm:intel_dump_pipe_config [i915]] crtc timings: 138780 1920 1966 1996 2080 1080 1082 1086 1112, type: 0x48 flags: 0xa
>[ 2750.192861] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 138780
>[ 2750.192872] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[ 2750.192883] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 2750.192893] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 2750.192904] [drm:intel_dump_pipe_config [i915]] dpll_hw_state: ctrl1: 0x3, cfgcr1: 0x0, cfgcr2: 0x0
>[ 2750.192914] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 2750.192925] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 1A] disabled, scaler_id = -1
>[ 2750.192935] [drm:intel_dump_pipe_config [i915]] [PLANE:31:plane 2A] disabled, scaler_id = -1
>[ 2750.192946] [drm:intel_dump_pipe_config [i915]] [PLANE:34:cursor A] disabled, scaler_id = -1
>[ 2750.192958] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 2750.192970] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[ 2750.192984] [drm:intel_find_shared_dpll [i915]] [CRTC:37:pipe A] allocated DPLL 0
>[ 2750.192996] [drm:intel_reference_shared_dpll [i915]] using DPLL 0 for pipe A
>[ 2750.193382] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 2750.193392] [drm:intel_power_well_enable [i915]] enabling DC off
>[ 2750.193685] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[ 2750.193703] [drm:intel_atomic_commit_tail [i915]] [ENCODER:48:DDI A]
>[ 2750.193717] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI B]
>[ 2750.193731] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[ 2750.193744] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[ 2750.193757] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DDI C]
>[ 2750.193772] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST A]
>[ 2750.193789] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST B]
>[ 2750.193806] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI D]
>[ 2750.193825] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[ 2750.193842] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[ 2750.193857] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[ 2750.193872] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[ 2750.193888] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[ 2750.193906] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[ 2750.193920] [drm:intel_enable_shared_dpll [i915]] enable DPLL 0 (active 1, on? 0) for crtc 37
>[ 2750.193933] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 0
>[ 2750.193953] [drm:edp_panel_on [i915]] Turn eDP port A panel power on
>[ 2750.193977] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle
>[ 2750.196067] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010
>[ 2750.196084] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[ 2750.196099] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0
>[ 2750.196119] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[ 2750.812371] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 00000000 control 00000060
>[ 2750.812479] [drm:wait_panel_status [i915]] Wait complete
>[ 2750.812617] [drm:edp_panel_on [i915]] Wait for panel power on
>[ 2750.812748] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 00000063
>[ 2750.846295] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010
>[ 2750.846376] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[ 2750.846451] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1
>[ 2750.846561] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[ 2751.014243] [drm:wait_panel_status [i915]] Wait complete
>[ 2751.014309] [drm:intel_power_well_enable [i915]] enabling DDI A/E IO power well
>[ 2751.014411] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[ 2751.014563] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b
>[ 2751.015805] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 2751.015879] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 2751.015975] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 2751.016048] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 2751.016774] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 2751.016834] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 2751.017829] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 2751.017884] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:49:eDP-1] Link Training Passed at Link Rate = 270000, Lane count = 2
>[ 2751.018519] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 2751.018586] [drm:intel_edp_backlight_on [i915]] 
>[ 2751.018642] [drm:intel_panel_enable_backlight [i915]] pipe A
>[ 2751.018725] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 120000
>[ 2751.028189] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS
>[ 2754.268326] [drm:edp_panel_vdd_off_sync [i915]] Turning eDP port A VDD off
>[ 2754.268472] [drm:edp_panel_vdd_off_sync [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x00000067
>[ 2754.923690] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 2754.923772] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 2754.923895] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[ 2754.923979] [drm:intel_power_well_enable [i915]] enabling power well 2
>[ 2755.183600] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 2755.183683] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 2760.752625] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 2760.752708] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 2761.012635] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 2761.012717] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 2761.180140] [drm:drm_atomic_helper_wait_for_flip_done [drm_kms_helper]] *ERROR* [CRTC:37:pipe A] flip_done timed out
>[ 2761.180265] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:49:eDP-1]
>[ 2761.180348] [drm:intel_atomic_commit_tail [i915]] [CRTC:37:pipe A]
>[ 2761.180445] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[ 2761.181032] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 00 00 04 00 0f 00 04
>[ 2761.182431] [drm:intel_power_well_disable [i915]] disabling power well 2
>[ 2761.182481] [drm:intel_power_well_disable [i915]] disabling DC off
>[ 2761.182526] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[ 2761.182569] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[ 2761.182634] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[ 2761.182676] [drm:intel_power_well_enable [i915]] enabling DC off
>[ 2761.182718] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[ 2761.182764] [drm:intel_power_well_enable [i915]] enabling power well 2
>[ 2761.183238] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 00 00 04 00 0f 00 04
>[ 2761.184656] [drm:intel_power_well_disable [i915]] disabling power well 2
>[ 2761.184709] [drm:intel_power_well_disable [i915]] disabling DC off
>[ 2761.184758] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[ 2761.184804] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[ 2761.218728] [drm:intel_power_well_enable [i915]] enabling DC off
>[ 2761.218782] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[ 2761.218869] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[ 2761.219013] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006f
>[ 2761.418819] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped
>[ 2761.668814] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped
>[ 2761.918825] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped
>[ 2762.168792] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped
>[ 2762.418815] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped
>[ 2765.532325] [drm:edp_panel_vdd_off_sync [i915]] Turning eDP port A VDD off
>[ 2765.532470] [drm:edp_panel_vdd_off_sync [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x00000067
>[ 2765.532527] [drm:intel_power_well_disable [i915]] disabling DC off
>[ 2765.532585] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[ 2765.532638] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[ 2766.591034] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 2766.591116] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 2766.591239] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[ 2766.591306] [drm:intel_power_well_enable [i915]] enabling DC off
>[ 2766.591371] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[ 2766.591431] [drm:intel_power_well_enable [i915]] enabling power well 2
>[ 2766.852025] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 2766.852106] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 2772.426236] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 2772.426318] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 2772.444243] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [CRTC:37:pipe A] flip_done timed out
>[ 2772.686873] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 2772.686954] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 2778.251920] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 2778.252001] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 2778.512250] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 2778.512333] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 2782.684244] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [PLANE:28:plane 1A] flip_done timed out
>[ 2784.081545] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 2784.081627] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 2784.339722] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 2784.339803] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 2789.909861] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 2789.909942] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 2790.171762] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 2790.171835] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 2792.924129] [drm:drm_atomic_helper_wait_for_flip_done [drm_kms_helper]] *ERROR* [CRTC:37:pipe A] flip_done timed out
>[ 2792.924412] [IGT] kms_frontbuffer_tracking: exiting, ret=0
>[ 2792.924482] Setting dangerous option enable_psr - tainting kernel
>[ 2792.924497] Setting dangerous option enable_fbc - tainting kernel
>[ 2792.924739] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 00 00 04 00 0f 00 04
>[ 2792.926332] [drm:intel_power_well_disable [i915]] disabling power well 2
>[ 2792.926390] [drm:intel_power_well_disable [i915]] disabling DC off
>[ 2792.926440] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[ 2792.926489] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[ 2792.926566] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[ 2792.926614] [drm:intel_power_well_enable [i915]] enabling DC off
>[ 2792.926660] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[ 2792.926711] [drm:intel_power_well_enable [i915]] enabling power well 2
>[ 2792.927198] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 00 00 04 00 0f 00 04
>[ 2792.928606] [drm:intel_power_well_disable [i915]] disabling power well 2
>[ 2792.928658] [drm:intel_power_well_disable [i915]] disabling DC off
>[ 2792.928706] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[ 2792.928753] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[ 2792.960004] [drm:intel_atomic_check [i915]] [CONNECTOR:57:DP-1] checking for sink bpp constrains
>[ 2792.960019] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 2792.960034] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 148500KHz
>[ 2792.960049] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 2792.960062] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 648000
>[ 2792.960076] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 2792.960089] [drm:intel_dump_pipe_config [i915]] [CRTC:47:pipe B][modeset]
>[ 2792.960102] [drm:intel_dump_pipe_config [i915]] output_types: DP (0x80)
>[ 2792.960115] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 2792.960127] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5767168, gmch_n: 8388608, link_m: 240298, link_n: 262144, tu: 64
>[ 2792.960139] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[ 2792.960151] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 2792.960158] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[ 2792.960170] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 2792.960176] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[ 2792.960188] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[ 2792.960200] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1080, pixel rate 148500
>[ 2792.960211] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[ 2792.960222] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 2792.960234] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 2792.960245] [drm:intel_dump_pipe_config [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[ 2792.960256] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 2792.960267] [drm:intel_dump_pipe_config [i915]] [PLANE:38:plane 1B] disabled, scaler_id = -1
>[ 2792.960278] [drm:intel_dump_pipe_config [i915]] [PLANE:41:plane 2B] disabled, scaler_id = -1
>[ 2792.960289] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor B] disabled, scaler_id = -1
>[ 2792.960303] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 2792.960315] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[ 2792.960332] [drm:intel_find_shared_dpll [i915]] [CRTC:47:pipe B] allocated DPLL 1
>[ 2792.960345] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[ 2795.743936] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 2795.744017] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 2795.744144] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[ 2795.744209] [drm:intel_power_well_enable [i915]] enabling DC off
>[ 2795.744275] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[ 2795.744334] [drm:intel_power_well_enable [i915]] enabling power well 2
>[ 2796.004001] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 2796.004082] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 2801.574611] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 2801.574692] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 2801.836748] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 2801.836830] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 2803.164228] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [CRTC:37:pipe A] flip_done timed out
>[ 2807.405343] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 2807.405424] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 2807.666165] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 2807.666246] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 2813.244228] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 2813.244309] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 2813.404201] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [CONNECTOR:49:eDP-1] flip_done timed out
>[ 2813.504225] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 2813.504307] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 2819.074585] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 2819.074665] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 2819.333430] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 2819.333511] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 2823.643986] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [PLANE:28:plane 1A] flip_done timed out
>[ 2823.644079] [drm:intel_disable_sagv [i915]] Disabling the SAGV
>[ 2823.644166] [drm:intel_atomic_commit_tail [i915]] [ENCODER:48:DDI A]
>[ 2823.644242] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI B]
>[ 2823.644312] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[ 2823.644379] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[ 2823.644443] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DDI C]
>[ 2823.644505] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST A]
>[ 2823.644566] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST B]
>[ 2823.644627] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI D]
>[ 2823.644688] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[ 2823.644748] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[ 2823.644815] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[ 2823.644884] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[ 2823.644949] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[ 2823.645011] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[ 2823.645086] [drm:intel_fbc_enable [i915]] reserved 16588800 bytes of contiguous stolen space for FBC, threshold: 1
>[ 2823.645153] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 2823.650922] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 2, on? 0) for crtc 47
>[ 2823.650998] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[ 2823.651115] [drm:intel_power_well_enable [i915]] enabling DDI B IO power well
>[ 2823.651731] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 2823.652993] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 2823.654250] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 2823.655499] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 2823.656714] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 2823.657594] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[ 2823.658590] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 2823.658656] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 2823.658719] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 2823.658780] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 2823.677459] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 2823.677486] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[ 2823.695329] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 2823.695652] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:57:DP-1] Link Training Passed at Link Rate = 162000, Lane count = 4
>[ 2823.696070] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 2823.696102] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS
>[ 2824.913043] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 2824.913125] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 2825.176310] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 2825.176391] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 2833.884145] [drm:drm_atomic_helper_wait_for_flip_done [drm_kms_helper]] *ERROR* [CRTC:37:pipe A] flip_done timed out
>[ 2833.884278] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:57:DP-1]
>[ 2833.884363] [drm:intel_atomic_commit_tail [i915]] [CRTC:47:pipe B]
>[ 2833.884460] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[ 2833.885059] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 00 00 04 00 0f 00 04
>[ 2833.886504] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[ 2833.886985] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 00 00 04 00 0f 00 04
>[ 2833.970504] [IGT] kms_frontbuffer_tracking: executing
>[ 2834.017472] [drm:drm_mode_addfb2 [drm]] [FB:75]
>[ 2834.017501] [drm:drm_mode_addfb2 [drm]] [FB:91]
>[ 2834.017531] [drm:drm_mode_addfb2 [drm]] [FB:92]
>[ 2834.018143] [drm:drm_mode_addfb2 [drm]] [FB:93]
>[ 2834.023823] [drm:drm_mode_addfb2 [drm]] [FB:94]
>[ 2834.025162] [drm:drm_mode_addfb2 [drm]] [FB:96]
>[ 2834.025191] [drm:drm_mode_addfb2 [drm]] [FB:98]
>[ 2834.025225] [drm:drm_mode_addfb2 [drm]] [FB:102]
>[ 2834.025430] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[ 2834.025440] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[ 2844.124135] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [CRTC:37:pipe A] flip_done timed out
>[ 2854.364249] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [CONNECTOR:49:eDP-1] flip_done timed out
>[ 2864.604225] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [PLANE:28:plane 1A] flip_done timed out
>[ 2874.844246] [drm:drm_atomic_helper_wait_for_flip_done [drm_kms_helper]] *ERROR* [CRTC:37:pipe A] flip_done timed out
>[ 2874.844425] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[ 2874.844574] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006f
>[ 2875.033503] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped
>[ 2875.033748] [IGT] kms_frontbuffer_tracking: starting subtest psr-1p-offscren-pri-shrfb-draw-blt
>[ 2875.033825] Setting dangerous option enable_fbc - tainting kernel
>[ 2875.033847] Setting dangerous option enable_psr - tainting kernel
>[ 2878.172209] [drm:edp_panel_vdd_off_sync [i915]] Turning eDP port A VDD off
>[ 2878.172354] [drm:edp_panel_vdd_off_sync [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x00000067
>[ 2885.083967] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [CRTC:37:pipe A] flip_done timed out
>[ 2895.324232] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [PLANE:28:plane 1A] flip_done timed out
>[ 2905.564124] [drm:drm_atomic_helper_wait_for_flip_done [drm_kms_helper]] *ERROR* [CRTC:37:pipe A] flip_done timed out
>[ 2905.565826] [drm:drm_mode_addfb2 [drm]] [FB:72]
>[ 2905.565866] [drm:drm_mode_addfb2 [drm]] [FB:75]
>[ 2905.565902] [drm:drm_mode_addfb2 [drm]] [FB:91]
>[ 2905.566597] [drm:drm_mode_addfb2 [drm]] [FB:92]
>[ 2905.571796] [drm:drm_mode_addfb2 [drm]] [FB:93]
>[ 2905.572769] [drm:drm_mode_addfb2 [drm]] [FB:94]
>[ 2905.572789] [drm:drm_mode_addfb2 [drm]] [FB:96]
>[ 2905.572809] [drm:drm_mode_addfb2 [drm]] [FB:98]
>[ 2905.572925] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[ 2905.572956] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 2905.572969] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[ 2915.804227] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [CRTC:37:pipe A] flip_done timed out
>[ 2926.044233] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [CONNECTOR:49:eDP-1] flip_done timed out
>[ 2936.284098] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [PLANE:28:plane 1A] flip_done timed out
>[ 2936.284236] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[ 2936.284389] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006f
>[ 2936.284667] [drm:intel_edp_backlight_off [i915]] 
>[ 2936.492293] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0
>[ 2936.492433] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 2936.500851] [drm:intel_edp_panel_off.part.31 [i915]] Turn eDP port A panel power off
>[ 2936.500965] [drm:intel_edp_panel_off.part.31 [i915]] Wait for panel power off time
>[ 2936.501097] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000002 control 00000060
>[ 2936.551283] [drm:wait_panel_status [i915]] Wait complete
>[ 2936.551347] [drm:intel_power_well_disable [i915]] disabling DDI A/E IO power well
>[ 2936.551429] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 2936.551509] [drm:intel_disable_shared_dpll [i915]] disable DPLL 0 (active 1, on? 1) for crtc 37
>[ 2936.551581] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 0
>[ 2936.551675] [drm:intel_atomic_commit_tail [i915]] [ENCODER:48:DDI A]
>[ 2936.551746] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI B]
>[ 2936.551812] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[ 2936.551876] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[ 2936.551983] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DDI C]
>[ 2936.552051] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST A]
>[ 2936.552122] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST B]
>[ 2936.552189] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI D]
>[ 2936.552255] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[ 2936.552322] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[ 2936.552401] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:49:eDP-1]
>[ 2936.552495] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[ 2936.552591] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[ 2936.552661] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[ 2936.552722] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[ 2936.560776] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010
>[ 2936.560857] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[ 2936.560931] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0
>[ 2936.561050] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[ 2936.563362] [drm:intel_atomic_commit_tail [i915]] [CRTC:37:pipe A]
>[ 2936.563433] [drm:intel_enable_sagv [i915]] Enabling the SAGV
>[ 2936.563532] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[ 2936.563631] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 2936.563703] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[ 2936.563817] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 2936.580780] [drm:intel_power_well_disable [i915]] disabling DDI B IO power well
>[ 2936.580864] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 2, on? 1) for crtc 47
>[ 2936.580936] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[ 2936.581025] [drm:intel_atomic_commit_tail [i915]] [ENCODER:48:DDI A]
>[ 2936.581091] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI B]
>[ 2936.581155] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[ 2936.581215] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[ 2936.581274] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DDI C]
>[ 2936.581331] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST A]
>[ 2936.581388] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST B]
>[ 2936.581445] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI D]
>[ 2936.581500] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[ 2936.581556] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[ 2936.581618] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:57:DP-1]
>[ 2936.581681] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[ 2936.581743] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[ 2936.581803] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[ 2936.581861] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[ 2936.581919] [drm:intel_power_well_disable [i915]] disabling power well 2
>[ 2936.581992] [drm:intel_atomic_commit_tail [i915]] [CRTC:47:pipe B]
>[ 2936.582046] [drm:intel_power_well_disable [i915]] disabling DC off
>[ 2936.582097] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[ 2936.582146] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[ 2936.582585] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 2936.586700] [drm:drm_mode_addfb2 [drm]] [FB:73]
>[ 2936.588623] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[ 2936.588629] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[ 2936.588650] [drm:intel_atomic_check [i915]] [CONNECTOR:49:eDP-1] checking for sink bpp constrains
>[ 2936.588663] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 2936.588669] [drm:drm_mode_debug_printmodeline [drm]] Modeline 52:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[ 2936.588683] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 138780KHz
>[ 2936.588699] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24
>[ 2936.588710] [drm:intel_dp_compute_config [i915]] DP link bw required 416340 available 540000
>[ 2936.588722] [drm:intel_dp_compute_config [i915]] PSR disable by flag
>[ 2936.588734] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 2936.588747] [drm:intel_dump_pipe_config [i915]] [CRTC:37:pipe A][modeset]
>[ 2936.588759] [drm:intel_dump_pipe_config [i915]] output_types: EDP (0x100)
>[ 2936.588770] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0
>[ 2936.588782] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 6467616, gmch_n: 8388608, link_m: 269484, link_n: 524288, tu: 64
>[ 2936.588792] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[ 2936.588803] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 2936.588808] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[ 2936.588819] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 2936.588824] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[ 2936.588836] [drm:intel_dump_pipe_config [i915]] crtc timings: 138780 1920 1966 1996 2080 1080 1082 1086 1112, type: 0x48 flags: 0xa
>[ 2936.588846] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 138780
>[ 2936.588857] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[ 2936.588867] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 2936.588877] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 2936.588888] [drm:intel_dump_pipe_config [i915]] dpll_hw_state: ctrl1: 0x3, cfgcr1: 0x0, cfgcr2: 0x0
>[ 2936.588898] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 2936.588908] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 1A] disabled, scaler_id = -1
>[ 2936.588919] [drm:intel_dump_pipe_config [i915]] [PLANE:31:plane 2A] disabled, scaler_id = -1
>[ 2936.588929] [drm:intel_dump_pipe_config [i915]] [PLANE:34:cursor A] disabled, scaler_id = -1
>[ 2936.588941] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 2936.588953] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[ 2936.588966] [drm:intel_find_shared_dpll [i915]] [CRTC:37:pipe A] allocated DPLL 0
>[ 2936.588978] [drm:intel_reference_shared_dpll [i915]] using DPLL 0 for pipe A
>[ 2936.589495] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 2936.589505] [drm:intel_power_well_enable [i915]] enabling DC off
>[ 2936.589782] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[ 2936.589800] [drm:intel_atomic_commit_tail [i915]] [ENCODER:48:DDI A]
>[ 2936.589813] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI B]
>[ 2936.589826] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[ 2936.589839] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[ 2936.589851] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DDI C]
>[ 2936.589863] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST A]
>[ 2936.589875] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST B]
>[ 2936.589887] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI D]
>[ 2936.589899] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[ 2936.589910] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[ 2936.589923] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[ 2936.589936] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[ 2936.589948] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[ 2936.589960] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[ 2936.589973] [drm:intel_enable_shared_dpll [i915]] enable DPLL 0 (active 1, on? 0) for crtc 37
>[ 2936.589987] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 0
>[ 2936.590007] [drm:edp_panel_on [i915]] Turn eDP port A panel power on
>[ 2936.590048] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle
>[ 2937.180423] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 00000000 control 00000060
>[ 2937.180522] [drm:wait_panel_status [i915]] Wait complete
>[ 2937.180654] [drm:edp_panel_on [i915]] Wait for panel power on
>[ 2937.180778] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 00000063
>[ 2937.214091] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010
>[ 2937.214172] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[ 2937.214247] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1
>[ 2937.214389] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[ 2937.383062] [drm:wait_panel_status [i915]] Wait complete
>[ 2937.383127] [drm:intel_power_well_enable [i915]] enabling DDI A/E IO power well
>[ 2937.383229] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[ 2937.383377] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b
>[ 2937.384582] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 2937.384645] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 2937.384705] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 2937.384765] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 2937.385478] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 2937.385536] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 2937.386497] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 2937.386523] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:49:eDP-1] Link Training Passed at Link Rate = 270000, Lane count = 2
>[ 2937.386902] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 2937.386934] [drm:intel_edp_backlight_on [i915]] 
>[ 2937.386946] [drm:intel_panel_enable_backlight [i915]] pipe A
>[ 2937.386986] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 120000
>[ 2937.392021] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS
>[ 2940.636317] [drm:edp_panel_vdd_off_sync [i915]] Turning eDP port A VDD off
>[ 2940.636461] [drm:edp_panel_vdd_off_sync [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x00000067
>[ 2947.548135] [drm:drm_atomic_helper_wait_for_flip_done [drm_kms_helper]] *ERROR* [CRTC:37:pipe A] flip_done timed out
>[ 2947.548255] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:49:eDP-1]
>[ 2947.548339] [drm:intel_atomic_commit_tail [i915]] [CRTC:37:pipe A]
>[ 2947.548436] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[ 2947.548500] [drm:intel_power_well_disable [i915]] disabling DC off
>[ 2947.548557] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[ 2947.548609] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[ 2947.587266] [drm:intel_power_well_enable [i915]] enabling DC off
>[ 2947.587326] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[ 2947.587423] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[ 2947.587574] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006f
>[ 2947.787217] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped
>[ 2947.787301] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[ 2947.787394] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 2947.787457] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[ 2950.876213] [drm:edp_panel_vdd_off_sync [i915]] Turning eDP port A VDD off
>[ 2950.876358] [drm:edp_panel_vdd_off_sync [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x00000067
>[ 2950.876415] [drm:intel_power_well_disable [i915]] disabling DC off
>[ 2950.876471] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[ 2950.876524] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[ 2957.319974] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 2957.320056] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 2957.320191] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[ 2957.320257] [drm:intel_power_well_enable [i915]] enabling DC off
>[ 2957.320322] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[ 2957.320385] [drm:intel_power_well_enable [i915]] enabling power well 2
>[ 2957.589106] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 2957.589188] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 2957.788084] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [CRTC:37:pipe A] flip_done timed out
>[ 2962.364440] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 2962.364521] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 2962.633704] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 2962.633786] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 2968.028231] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [CONNECTOR:49:eDP-1] flip_done timed out
>[ 2968.207255] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 2968.207337] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 2968.476299] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 2968.476380] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 2974.035917] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 2974.035999] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 2974.318515] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 2974.318597] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 2978.268235] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [PLANE:28:plane 1A] flip_done timed out
>[ 2978.268340] [drm:intel_edp_backlight_off [i915]] 
>[ 2978.476292] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0
>[ 2978.476426] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 2978.487420] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[ 2978.487579] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b
>[ 2978.487852] [drm:intel_edp_panel_off.part.31 [i915]] Turn eDP port A panel power off
>[ 2978.487990] [drm:intel_edp_panel_off.part.31 [i915]] Wait for panel power off time
>[ 2978.488127] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000002 control 00000060
>[ 2978.538477] [drm:wait_panel_status [i915]] Wait complete
>[ 2978.538541] [drm:intel_power_well_disable [i915]] disabling DDI A/E IO power well
>[ 2978.538627] [drm:intel_disable_shared_dpll [i915]] disable DPLL 0 (active 1, on? 1) for crtc 37
>[ 2978.538702] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 0
>[ 2978.538794] [drm:intel_atomic_commit_tail [i915]] [ENCODER:48:DDI A]
>[ 2978.538865] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI B]
>[ 2978.538932] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[ 2978.538998] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[ 2978.539063] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DDI C]
>[ 2978.539125] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST A]
>[ 2978.539187] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST B]
>[ 2978.539248] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI D]
>[ 2978.539309] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[ 2978.539368] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[ 2978.539435] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:49:eDP-1]
>[ 2978.539502] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[ 2978.539566] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[ 2978.539629] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[ 2978.539691] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[ 2978.539768] [drm:intel_atomic_commit_tail [i915]] [CRTC:37:pipe A]
>[ 2978.539883] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[ 2978.540373] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 00 00 04 00 0f 00 04
>[ 2978.547522] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010
>[ 2978.547540] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[ 2978.547557] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0
>[ 2978.568859] [drm:intel_power_well_disable [i915]] disabling power well 2
>[ 2978.568878] [drm:intel_power_well_disable [i915]] disabling DC off
>[ 2978.568893] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[ 2978.568907] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[ 2978.568922] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 2978.568944] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[ 2978.568963] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[ 2978.568977] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 2978.568991] [drm:intel_power_well_enable [i915]] enabling DC off
>[ 2978.569312] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[ 2978.569327] [drm:intel_power_well_enable [i915]] enabling power well 2
>[ 2978.569752] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 00 00 04 00 0f 00 04
>[ 2978.570463] [drm:drm_mode_addfb2 [drm]] [FB:73]
>[ 2978.571030] [drm:intel_power_well_disable [i915]] disabling power well 2
>[ 2978.571048] [drm:intel_power_well_disable [i915]] disabling DC off
>[ 2978.571065] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[ 2978.571081] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[ 2978.571099] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 2978.571899] [drm:drm_mode_addfb2 [drm]] [FB:102]
>[ 2978.573617] [drm:drm_mode_addfb2 [drm]] [FB:103]
>[ 2978.574538] [drm:drm_mode_addfb2 [drm]] [FB:104]
>[ 2978.644724] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[ 2978.644731] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[ 2978.644757] [drm:intel_atomic_check [i915]] [CONNECTOR:49:eDP-1] checking for sink bpp constrains
>[ 2978.644770] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 2978.644776] [drm:drm_mode_debug_printmodeline [drm]] Modeline 52:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[ 2978.644791] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 138780KHz
>[ 2978.644807] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24
>[ 2978.644818] [drm:intel_dp_compute_config [i915]] DP link bw required 416340 available 540000
>[ 2978.644830] [drm:intel_dp_compute_config [i915]] PSR disable by flag
>[ 2978.644842] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 2978.644855] [drm:intel_dump_pipe_config [i915]] [CRTC:37:pipe A][modeset]
>[ 2978.644867] [drm:intel_dump_pipe_config [i915]] output_types: EDP (0x100)
>[ 2978.644878] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0
>[ 2978.644890] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 6467616, gmch_n: 8388608, link_m: 269484, link_n: 524288, tu: 64
>[ 2978.644900] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[ 2978.644911] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 2978.644917] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[ 2978.644927] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 2978.644933] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[ 2978.644944] [drm:intel_dump_pipe_config [i915]] crtc timings: 138780 1920 1966 1996 2080 1080 1082 1086 1112, type: 0x48 flags: 0xa
>[ 2978.644955] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 138780
>[ 2978.644966] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[ 2978.644976] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 2978.644986] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 2978.644997] [drm:intel_dump_pipe_config [i915]] dpll_hw_state: ctrl1: 0x3, cfgcr1: 0x0, cfgcr2: 0x0
>[ 2978.645007] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 2978.645017] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 1A] disabled, scaler_id = -1
>[ 2978.645027] [drm:intel_dump_pipe_config [i915]] [PLANE:31:plane 2A] disabled, scaler_id = -1
>[ 2978.645037] [drm:intel_dump_pipe_config [i915]] [PLANE:34:cursor A] disabled, scaler_id = -1
>[ 2978.645050] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 2978.645062] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[ 2978.645076] [drm:intel_find_shared_dpll [i915]] [CRTC:37:pipe A] allocated DPLL 0
>[ 2978.645088] [drm:intel_reference_shared_dpll [i915]] using DPLL 0 for pipe A
>[ 2978.646047] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 2978.646056] [drm:intel_power_well_enable [i915]] enabling DC off
>[ 2978.646349] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[ 2978.646367] [drm:intel_atomic_commit_tail [i915]] [ENCODER:48:DDI A]
>[ 2978.646381] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI B]
>[ 2978.646394] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[ 2978.646407] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[ 2978.646421] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DDI C]
>[ 2978.646438] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST A]
>[ 2978.646472] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST B]
>[ 2978.646489] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI D]
>[ 2978.646505] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[ 2978.646515] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[ 2978.646527] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[ 2978.646540] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[ 2978.646551] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[ 2978.646562] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[ 2978.646576] [drm:intel_enable_shared_dpll [i915]] enable DPLL 0 (active 1, on? 0) for crtc 37
>[ 2978.646587] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 0
>[ 2978.646606] [drm:edp_panel_on [i915]] Turn eDP port A panel power on
>[ 2978.646630] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle
>[ 2979.164283] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 00000000 control 00000060
>[ 2979.164382] [drm:wait_panel_status [i915]] Wait complete
>[ 2979.164515] [drm:edp_panel_on [i915]] Wait for panel power on
>[ 2979.164636] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 00000063
>[ 2979.198255] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010
>[ 2979.198328] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[ 2979.198394] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1
>[ 2979.198494] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[ 2979.366899] [drm:wait_panel_status [i915]] Wait complete
>[ 2979.366964] [drm:intel_power_well_enable [i915]] enabling DDI A/E IO power well
>[ 2979.367066] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[ 2979.367217] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b
>[ 2979.368454] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 2979.368526] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 2979.368591] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 2979.368654] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 2979.369367] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 2979.369425] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 2979.370434] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 2979.370495] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:49:eDP-1] Link Training Passed at Link Rate = 270000, Lane count = 2
>[ 2979.371147] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 2979.371226] [drm:intel_edp_backlight_on [i915]] 
>[ 2979.371290] [drm:intel_panel_enable_backlight [i915]] pipe A
>[ 2979.371378] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 120000
>[ 2979.376004] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS
>[ 2979.869536] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 2979.869617] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 2979.869741] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[ 2979.869805] [drm:intel_power_well_enable [i915]] enabling power well 2
>[ 2980.130326] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 2980.130407] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 2982.620313] [drm:edp_panel_vdd_off_sync [i915]] Turning eDP port A VDD off
>[ 2982.620460] [drm:edp_panel_vdd_off_sync [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x00000067
>[ 2985.693184] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 2985.693266] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 2985.954816] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 2985.954897] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 2989.532134] [drm:drm_atomic_helper_wait_for_flip_done [drm_kms_helper]] *ERROR* [CRTC:37:pipe A] flip_done timed out
>[ 2989.532257] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:49:eDP-1]
>[ 2989.532340] [drm:intel_atomic_commit_tail [i915]] [CRTC:37:pipe A]
>[ 2989.532436] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[ 2989.533023] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 00 00 04 00 0f 00 04
>[ 2989.534421] [drm:intel_power_well_disable [i915]] disabling power well 2
>[ 2989.534471] [drm:intel_power_well_disable [i915]] disabling DC off
>[ 2989.534517] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[ 2989.534561] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[ 2989.534626] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[ 2989.534669] [drm:intel_power_well_enable [i915]] enabling DC off
>[ 2989.534711] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[ 2989.534757] [drm:intel_power_well_enable [i915]] enabling power well 2
>[ 2989.535230] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 00 00 04 00 0f 00 04
>[ 2989.536647] [drm:intel_power_well_disable [i915]] disabling power well 2
>[ 2989.536699] [drm:intel_power_well_disable [i915]] disabling DC off
>[ 2989.536748] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[ 2989.536794] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[ 2989.571180] [drm:intel_power_well_enable [i915]] enabling DC off
>[ 2989.571232] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[ 2989.571322] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[ 2989.571464] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006f
>[ 2989.771455] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped
>[ 2989.771505] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[ 2989.771536] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[ 2991.531866] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 2991.531948] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 2991.532069] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[ 2991.532136] [drm:intel_power_well_enable [i915]] enabling power well 2
>[ 2991.790507] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 2991.790589] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 2992.860211] [drm:edp_panel_vdd_off_sync [i915]] Turning eDP port A VDD off
>[ 2992.860357] [drm:edp_panel_vdd_off_sync [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x00000067
>[ 2997.367635] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 2997.367717] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 2997.627557] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 2997.627638] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 3000.028240] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [CRTC:37:pipe A] flip_done timed out
>[ 3003.203520] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 3003.203601] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 3003.464009] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 3003.464091] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 3009.029391] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 3009.029472] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 3009.290320] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 3009.290402] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 3010.268232] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [CONNECTOR:49:eDP-1] flip_done timed out
>[ 3014.866268] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 3014.866349] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 3015.128557] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 3015.128638] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 3020.508117] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [PLANE:28:plane 1A] flip_done timed out
>[ 3020.692854] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 3020.692936] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 3020.954289] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 3020.954371] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 3026.522613] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 3026.522695] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 3026.782685] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 3026.782768] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 3030.748133] [drm:drm_atomic_helper_wait_for_flip_done [drm_kms_helper]] *ERROR* [CRTC:37:pipe A] flip_done timed out
>[ 3030.748736] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 00 00 04 00 0f 00 04
>[ 3030.750145] [drm:intel_power_well_disable [i915]] disabling power well 2
>[ 3030.750201] [drm:intel_power_well_disable [i915]] disabling DC off
>[ 3030.750269] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[ 3030.750313] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[ 3030.750379] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[ 3030.750422] [drm:intel_power_well_enable [i915]] enabling DC off
>[ 3030.750464] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[ 3030.750511] [drm:intel_power_well_enable [i915]] enabling power well 2
>[ 3030.750983] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 00 00 04 00 0f 00 04
>[ 3030.752389] [drm:intel_power_well_disable [i915]] disabling power well 2
>[ 3030.752436] [drm:intel_power_well_disable [i915]] disabling DC off
>[ 3030.752480] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[ 3030.752523] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[ 3030.787134] [drm:intel_power_well_enable [i915]] enabling DC off
>[ 3030.787186] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[ 3030.787274] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[ 3030.787421] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006f
>[ 3030.987412] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped
>[ 3030.987456] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[ 3030.987486] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[ 3032.353798] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 3032.353880] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 3032.354001] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[ 3032.354067] [drm:intel_power_well_enable [i915]] enabling power well 2
>[ 3032.615797] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 3032.615878] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 3034.076210] [drm:edp_panel_vdd_off_sync [i915]] Turning eDP port A VDD off
>[ 3034.076357] [drm:edp_panel_vdd_off_sync [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x00000067
>[ 3038.181824] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 3038.181906] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 3038.445267] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 3038.445348] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 3041.244233] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [CRTC:37:pipe A] flip_done timed out
>[ 3044.018821] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 3044.018903] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 3044.279497] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 3044.279578] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 3049.846039] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 3049.846120] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 3050.106489] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 3050.106571] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 3051.484251] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [CONNECTOR:49:eDP-1] flip_done timed out
>[ 3055.677218] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 3055.677300] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 3055.938392] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 3055.938473] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 3061.507137] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 3061.507218] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 3061.724117] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [PLANE:28:plane 1A] flip_done timed out
>[ 3061.768980] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 3061.769061] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 3067.343133] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 3067.343215] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 3067.605770] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 3067.605852] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 3071.964132] [drm:drm_atomic_helper_wait_for_flip_done [drm_kms_helper]] *ERROR* [CRTC:37:pipe A] flip_done timed out
>[ 3071.964732] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 00 00 04 00 0f 00 04
>[ 3071.966136] [drm:intel_power_well_disable [i915]] disabling power well 2
>[ 3071.966193] [drm:intel_power_well_disable [i915]] disabling DC off
>[ 3071.966245] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[ 3071.966293] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[ 3071.966369] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[ 3071.966417] [drm:intel_power_well_enable [i915]] enabling DC off
>[ 3071.966464] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[ 3071.966515] [drm:intel_power_well_enable [i915]] enabling power well 2
>[ 3071.966920] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 00 00 04 00 0f 00 04
>[ 3071.968181] [drm:intel_power_well_disable [i915]] disabling power well 2
>[ 3071.968206] [drm:intel_power_well_disable [i915]] disabling DC off
>[ 3071.968229] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[ 3071.968238] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[ 3072.003036] [drm:intel_power_well_enable [i915]] enabling DC off
>[ 3072.003050] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[ 3072.003083] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[ 3072.003179] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006f
>[ 3072.203360] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped
>[ 3072.203412] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[ 3072.203442] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[ 3073.173586] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 3073.173667] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 3073.173796] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[ 3073.173855] [drm:intel_power_well_enable [i915]] enabling power well 2
>[ 3073.435422] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 3073.435504] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 3075.292204] [drm:edp_panel_vdd_off_sync [i915]] Turning eDP port A VDD off
>[ 3075.292349] [drm:edp_panel_vdd_off_sync [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x00000067
>[ 3079.008371] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 3079.008453] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 3079.266947] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 3079.267028] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 3082.460111] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [CRTC:37:pipe A] flip_done timed out
>[ 3084.831460] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 3084.831542] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 3085.092039] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 3085.092119] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 3090.663048] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 3090.663128] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 3090.923795] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 3090.923876] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 3092.700129] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [CONNECTOR:49:eDP-1] flip_done timed out
>[ 3096.494099] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 3096.494181] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 3096.755374] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 3096.755456] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 3102.332527] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 3102.332608] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 3102.592734] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 3102.592814] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 3102.940182] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [PLANE:28:plane 1A] flip_done timed out
>[ 3108.158348] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 3108.158430] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 3108.418834] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 3108.418916] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 3113.180126] [drm:drm_atomic_helper_wait_for_flip_done [drm_kms_helper]] *ERROR* [CRTC:37:pipe A] flip_done timed out
>[ 3113.180727] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 00 00 04 00 0f 00 04
>[ 3113.182132] [drm:intel_power_well_disable [i915]] disabling power well 2
>[ 3113.182190] [drm:intel_power_well_disable [i915]] disabling DC off
>[ 3113.182254] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[ 3113.182298] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[ 3113.182366] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[ 3113.182409] [drm:intel_power_well_enable [i915]] enabling DC off
>[ 3113.182451] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[ 3113.182498] [drm:intel_power_well_enable [i915]] enabling power well 2
>[ 3113.182976] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 00 00 04 00 0f 00 04
>[ 3113.184389] [drm:intel_power_well_disable [i915]] disabling power well 2
>[ 3113.184443] [drm:intel_power_well_disable [i915]] disabling DC off
>[ 3113.184492] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[ 3113.184541] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[ 3113.219216] [drm:intel_power_well_enable [i915]] enabling DC off
>[ 3113.219270] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[ 3113.219359] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[ 3113.219509] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006f
>[ 3113.419300] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped
>[ 3113.419416] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[ 3113.419511] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 3113.419572] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[ 3113.995456] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 3113.995537] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 3113.995661] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[ 3113.995727] [drm:intel_power_well_enable [i915]] enabling power well 2
>[ 3114.256281] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 3114.256362] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 3116.508206] [drm:edp_panel_vdd_off_sync [i915]] Turning eDP port A VDD off
>[ 3116.508354] [drm:edp_panel_vdd_off_sync [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x00000067
>[ 3119.829909] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 3119.829990] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 3120.089919] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 3120.090001] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 3123.420074] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [CRTC:37:pipe A] flip_done timed out
>[ 3125.655027] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 3125.655108] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 3125.917771] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 3125.917852] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 3131.490822] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 3131.490903] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 3131.753244] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 3131.753325] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 3133.660222] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [CONNECTOR:49:eDP-1] flip_done timed out
>[ 3137.327411] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 3137.327492] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 3137.589236] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 3137.589318] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 3143.164368] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 3143.164449] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 3143.427068] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 3143.427149] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 3143.900228] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [PLANE:28:plane 1A] flip_done timed out
>[ 3143.900334] [drm:intel_edp_backlight_off [i915]] 
>[ 3144.108289] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0
>[ 3144.108428] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 3144.119419] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[ 3144.119578] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b
>[ 3144.119849] [drm:intel_edp_panel_off.part.31 [i915]] Turn eDP port A panel power off
>[ 3144.119987] [drm:intel_edp_panel_off.part.31 [i915]] Wait for panel power off time
>[ 3144.120118] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000003 control 00000060
>[ 3144.172905] [drm:wait_panel_status [i915]] Wait complete
>[ 3144.172969] [drm:intel_power_well_disable [i915]] disabling DDI A/E IO power well
>[ 3144.173056] [drm:intel_disable_shared_dpll [i915]] disable DPLL 0 (active 1, on? 1) for crtc 37
>[ 3144.173130] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 0
>[ 3144.173221] [drm:intel_atomic_commit_tail [i915]] [ENCODER:48:DDI A]
>[ 3144.173292] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI B]
>[ 3144.173358] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[ 3144.173423] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[ 3144.173486] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DDI C]
>[ 3144.173548] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST A]
>[ 3144.173608] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST B]
>[ 3144.173667] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI D]
>[ 3144.173727] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[ 3144.173786] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[ 3144.173851] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:49:eDP-1]
>[ 3144.173917] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[ 3144.173981] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[ 3144.174045] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[ 3144.174107] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[ 3144.174184] [drm:intel_atomic_commit_tail [i915]] [CRTC:37:pipe A]
>[ 3144.174306] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[ 3144.174768] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 00 00 04 00 0f 00 04
>[ 3144.176193] [drm:intel_power_well_disable [i915]] disabling power well 2
>[ 3144.176244] [drm:intel_power_well_disable [i915]] disabling DC off
>[ 3144.176290] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[ 3144.176335] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[ 3144.176338] Setting dangerous option enable_psr - tainting kernel
>[ 3144.177267] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 3144.177350] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[ 3144.177393] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 3144.177422] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[ 3144.177464] [drm:intel_power_well_enable [i915]] enabling DC off
>[ 3144.177485] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[ 3144.177582] [drm:intel_atomic_check [i915]] [CONNECTOR:49:eDP-1] checking for sink bpp constrains
>[ 3144.177648] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 3144.177677] [drm:drm_mode_debug_printmodeline [drm]] Modeline 52:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[ 3144.177743] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 138780KHz
>[ 3144.177786] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[ 3144.177832] [drm:intel_power_well_enable [i915]] enabling power well 2
>[ 3144.177894] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24
>[ 3144.177952] [drm:intel_dp_compute_config [i915]] DP link bw required 416340 available 540000
>[ 3144.178016] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 3144.178106] [drm:intel_dump_pipe_config [i915]] [CRTC:37:pipe A][modeset]
>[ 3144.178163] [drm:intel_dump_pipe_config [i915]] output_types: EDP (0x100)
>[ 3144.178219] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0
>[ 3144.178275] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 6467616, gmch_n: 8388608, link_m: 269484, link_n: 524288, tu: 64
>[ 3144.178327] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[ 3144.178379] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 3144.178406] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[ 3144.178457] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 3144.178483] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[ 3144.178536] [drm:intel_dump_pipe_config [i915]] crtc timings: 138780 1920 1966 1996 2080 1080 1082 1086 1112, type: 0x48 flags: 0xa
>[ 3144.178587] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 138780
>[ 3144.178637] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[ 3144.178686] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 3144.178735] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 3144.178792] [drm:intel_dump_pipe_config [i915]] dpll_hw_state: ctrl1: 0x3, cfgcr1: 0x0, cfgcr2: 0x0
>[ 3144.178839] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 3144.178888] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 1A] disabled, scaler_id = -1
>[ 3144.178937] [drm:intel_dump_pipe_config [i915]] [PLANE:31:plane 2A] disabled, scaler_id = -1
>[ 3144.178985] [drm:intel_dump_pipe_config [i915]] [PLANE:34:cursor A] disabled, scaler_id = -1
>[ 3144.179046] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 3144.179100] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[ 3144.179166] [drm:intel_find_shared_dpll [i915]] [CRTC:37:pipe A] allocated DPLL 0
>[ 3144.179222] [drm:intel_reference_shared_dpll [i915]] using DPLL 0 for pipe A
>[ 3144.179641] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010
>[ 3144.179712] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[ 3144.179778] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0
>[ 3144.183172] [drm:intel_atomic_commit_tail [i915]] [ENCODER:48:DDI A]
>[ 3144.183187] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI B]
>[ 3144.183200] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[ 3144.183213] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[ 3144.183225] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DDI C]
>[ 3144.183236] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST A]
>[ 3144.183248] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST B]
>[ 3144.183259] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI D]
>[ 3144.183270] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[ 3144.183281] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[ 3144.183293] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[ 3144.183306] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[ 3144.183318] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[ 3144.183330] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[ 3144.183344] [drm:intel_enable_shared_dpll [i915]] enable DPLL 0 (active 1, on? 0) for crtc 37
>[ 3144.183356] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 0
>[ 3144.183376] [drm:edp_panel_on [i915]] Turn eDP port A panel power on
>[ 3144.183402] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle
>[ 3144.796358] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 00000000 control 00000060
>[ 3144.796451] [drm:wait_panel_status [i915]] Wait complete
>[ 3144.796562] [drm:edp_panel_on [i915]] Wait for panel power on
>[ 3144.796693] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 00000063
>[ 3144.828594] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010
>[ 3144.828675] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[ 3144.828750] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1
>[ 3144.999262] [drm:wait_panel_status [i915]] Wait complete
>[ 3144.999327] [drm:intel_power_well_enable [i915]] enabling DDI A/E IO power well
>[ 3144.999429] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[ 3144.999579] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b
>[ 3145.000813] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 3145.000886] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 3145.000952] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 3145.001015] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 3145.001732] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 3145.001791] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 3145.002798] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 3145.002861] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:49:eDP-1] Link Training Passed at Link Rate = 270000, Lane count = 2
>[ 3145.003515] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 3145.003592] [drm:intel_edp_backlight_on [i915]] 
>[ 3145.003656] [drm:intel_panel_enable_backlight [i915]] pipe A
>[ 3145.003746] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 120000
>[ 3145.008256] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS
>[ 3148.252309] [drm:edp_panel_vdd_off_sync [i915]] Turning eDP port A VDD off
>[ 3148.252454] [drm:edp_panel_vdd_off_sync [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x00000067
>[ 3148.996665] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 3148.996747] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 3149.257367] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 3149.257448] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 3154.818294] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 3154.818376] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 3155.080140] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 3155.080222] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 3155.164126] [drm:drm_atomic_helper_wait_for_flip_done [drm_kms_helper]] *ERROR* [CRTC:37:pipe A] flip_done timed out
>[ 3155.164250] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:49:eDP-1]
>[ 3155.164332] [drm:intel_atomic_commit_tail [i915]] [CRTC:37:pipe A]
>[ 3155.164428] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[ 3155.165012] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 00 00 04 00 0f 00 04
>[ 3155.166418] [drm:intel_power_well_disable [i915]] disabling power well 2
>[ 3155.166474] [drm:intel_power_well_disable [i915]] disabling DC off
>[ 3155.166525] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[ 3155.166574] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[ 3155.166646] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[ 3155.166708] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[ 3155.166758] [drm:intel_power_well_enable [i915]] enabling DC off
>[ 3155.166806] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[ 3155.166858] [drm:intel_power_well_enable [i915]] enabling power well 2
>[ 3155.167329] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 00 00 04 00 0f 00 04
>[ 3155.168662] [drm:intel_power_well_disable [i915]] disabling power well 2
>[ 3155.168687] [drm:intel_power_well_disable [i915]] disabling DC off
>[ 3155.168697] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[ 3155.168705] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[ 3155.203503] [drm:intel_power_well_enable [i915]] enabling DC off
>[ 3155.203517] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[ 3155.203550] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[ 3155.203648] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006f
>[ 3155.403832] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped
>[ 3155.653822] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped
>[ 3157.137336] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped
>[ 3159.037075] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped
>[ 3160.646989] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 3160.647069] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 3160.647211] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[ 3160.647270] [drm:intel_power_well_enable [i915]] enabling power well 2
>[ 3160.647798] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 00 00 04 00 0f 00 04
>[ 3160.648155] [drm:intel_power_well_disable [i915]] disabling power well 2
>[ 3160.648245] [drm:i915_hotplug_work_func [i915]] running encoder hotplug functions
>[ 3160.648328] [drm:i915_hotplug_work_func [i915]] Connector DP-1 (pin 5) received hotplug event.
>[ 3160.648398] [drm:intel_dp_detect [i915]] [CONNECTOR:57:DP-1]
>[ 3160.648451] [drm:intel_power_well_enable [i915]] enabling power well 2
>[ 3160.648843] [drm:lspcon_wake_native_aux_ch [i915]] Native AUX CH up, DPCD version: 1.2
>[ 3160.648919] [drm:lspcon_resume [i915]] LSPCON recovering in PCON mode after 0 ms
>[ 3160.649361] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 3160.650583] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 3160.651834] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 3160.653077] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 3160.654337] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 3160.655186] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[ 3160.655667] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 00 00 04 00 0f 00 04
>[ 3160.656026] [drm:intel_power_well_disable [i915]] disabling power well 2
>[ 3160.656106] [drm:i915_hotplug_work_func [i915]] [CONNECTOR:57:DP-1] status updated from connected to disconnected
>[ 3160.907445] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 3160.907515] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 3160.907609] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[ 3160.907663] [drm:intel_power_well_enable [i915]] enabling power well 2
>[ 3161.053721] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped
>[ 3161.054265] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 00 00 04 00 0f 00 04
>[ 3161.055028] [drm:intel_power_well_disable [i915]] disabling power well 2
>[ 3161.055107] [drm:i915_hotplug_work_func [i915]] running encoder hotplug functions
>[ 3161.055170] [drm:i915_hotplug_work_func [i915]] Connector DP-1 (pin 5) received hotplug event.
>[ 3161.055230] [drm:intel_dp_detect [i915]] [CONNECTOR:57:DP-1]
>[ 3161.055275] [drm:intel_power_well_enable [i915]] enabling power well 2
>[ 3161.055652] [drm:lspcon_wake_native_aux_ch [i915]] Native AUX CH up, DPCD version: 1.2
>[ 3161.055722] [drm:lspcon_resume [i915]] LSPCON recovering in PCON mode after 0 ms
>[ 3161.056164] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 3161.057414] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 3161.058668] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 3161.059940] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 3161.061055] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 3161.061836] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[ 3161.062310] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 00 00 04 00 0f 00 04
>[ 3161.063099] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>[ 3161.063158] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000
>[ 3161.063213] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000
>[ 3161.063614] [drm:drm_dp_read_desc [drm_kms_helper]] DP branch: OUI 00-60-ad dev-ID MC2800 HW-rev 2.2 SW-rev 1.70 quirks 0x0000
>[ 3161.063972] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[ 3161.064744] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 3161.065966] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 3161.067217] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 3161.068477] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 3161.069740] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 3161.070990] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 3161.072236] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 3161.073482] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 3161.074718] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 3161.076102] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 3161.077478] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 3161.078857] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 3161.080235] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 3161.081609] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 3161.082988] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 3161.084386] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 3161.085754] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 3161.087012] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 3161.088264] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 3161.089514] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 3161.090761] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 3161.092144] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 3161.093513] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 3161.094889] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 3161.096268] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 3161.097643] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 3161.099011] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 3161.100388] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 3161.101765] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 3161.102910] [drm:intel_power_well_disable [i915]] disabling power well 2
>[ 3161.102986] [drm:i915_hotplug_work_func [i915]] [CONNECTOR:57:DP-1] status updated from disconnected to connected
>[ 3164.124193] [drm:edp_panel_vdd_off_sync [i915]] Turning eDP port A VDD off
>[ 3164.124329] [drm:edp_panel_vdd_off_sync [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x00000067
>[ 3164.124381] [drm:intel_power_well_disable [i915]] disabling DC off
>[ 3164.124432] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[ 3164.124479] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[ 3166.479597] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 3166.479677] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 3166.479802] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[ 3166.479868] [drm:intel_power_well_enable [i915]] enabling DC off
>[ 3166.479951] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[ 3166.480011] [drm:intel_power_well_enable [i915]] enabling power well 2
>[ 3166.738489] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 3166.738571] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 3172.304227] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 3172.304309] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 3172.566452] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 3172.566533] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 3172.828217] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [CRTC:37:pipe A] flip_done timed out
>[ 3178.135188] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 3178.135270] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 3178.395857] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 3178.395938] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 3183.068201] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [PLANE:28:plane 1A] flip_done timed out
>[ 3183.969769] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 3183.969851] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 3184.230848] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 3184.230928] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 3189.796522] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 3189.796603] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 3190.058899] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 3190.058982] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 3193.308203] [drm:drm_atomic_helper_wait_for_flip_done [drm_kms_helper]] *ERROR* [CRTC:37:pipe A] flip_done timed out
>[ 3193.308481] [IGT] kms_frontbuffer_tracking: exiting, ret=0
>[ 3193.308549] Setting dangerous option enable_psr - tainting kernel
>[ 3193.308564] Setting dangerous option enable_fbc - tainting kernel
>[ 3193.308802] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 00 00 04 00 0f 00 04
>[ 3193.310423] [drm:intel_power_well_disable [i915]] disabling power well 2
>[ 3193.310480] [drm:intel_power_well_disable [i915]] disabling DC off
>[ 3193.310530] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[ 3193.310579] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[ 3193.310655] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[ 3193.310703] [drm:intel_power_well_enable [i915]] enabling DC off
>[ 3193.310751] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[ 3193.310802] [drm:intel_power_well_enable [i915]] enabling power well 2
>[ 3193.311287] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 00 00 04 00 0f 00 04
>[ 3193.312705] [drm:intel_power_well_disable [i915]] disabling power well 2
>[ 3193.312757] [drm:intel_power_well_disable [i915]] disabling DC off
>[ 3193.312805] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[ 3193.312852] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[ 3193.335921] [drm:intel_atomic_check [i915]] [CONNECTOR:57:DP-1] checking for sink bpp constrains
>[ 3193.335936] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 3193.335950] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 148500KHz
>[ 3193.335965] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 3193.335978] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 648000
>[ 3193.335991] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 3193.336005] [drm:intel_dump_pipe_config [i915]] [CRTC:47:pipe B][modeset]
>[ 3193.336017] [drm:intel_dump_pipe_config [i915]] output_types: DP (0x80)
>[ 3193.336045] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 3193.336057] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5767168, gmch_n: 8388608, link_m: 240298, link_n: 262144, tu: 64
>[ 3193.336082] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[ 3193.336094] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 3193.336102] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[ 3193.336114] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 3193.336120] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[ 3193.336132] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[ 3193.336144] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1080, pixel rate 148500
>[ 3193.336155] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[ 3193.336166] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 3193.336177] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 3193.336188] [drm:intel_dump_pipe_config [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[ 3193.336199] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 3193.336210] [drm:intel_dump_pipe_config [i915]] [PLANE:38:plane 1B] disabled, scaler_id = -1
>[ 3193.336221] [drm:intel_dump_pipe_config [i915]] [PLANE:41:plane 2B] disabled, scaler_id = -1
>[ 3193.336232] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor B] disabled, scaler_id = -1
>[ 3193.336246] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 3193.336258] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[ 3193.336274] [drm:intel_find_shared_dpll [i915]] [CRTC:47:pipe B] allocated DPLL 1
>[ 3193.336286] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[ 3195.628978] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 3195.629060] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 3195.629183] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[ 3195.629249] [drm:intel_power_well_enable [i915]] enabling DC off
>[ 3195.629313] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[ 3195.629371] [drm:intel_power_well_enable [i915]] enabling power well 2
>[ 3195.890766] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 3195.890848] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 3201.458583] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 3201.458664] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 3201.721649] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 3201.721730] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 3203.548163] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [CRTC:37:pipe A] flip_done timed out
>[ 3207.295188] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 3207.295269] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 3207.557321] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 3207.557403] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 3213.121219] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 3213.121300] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 3213.384337] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 3213.384419] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 3213.788077] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [CONNECTOR:49:eDP-1] flip_done timed out
>[ 3218.954877] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 3218.954957] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 3219.213205] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 3219.213287] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 3224.028210] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [PLANE:28:plane 1A] flip_done timed out
>[ 3224.028304] [drm:intel_disable_sagv [i915]] Disabling the SAGV
>[ 3224.028390] [drm:intel_atomic_commit_tail [i915]] [ENCODER:48:DDI A]
>[ 3224.028465] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI B]
>[ 3224.028536] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[ 3224.028603] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[ 3224.028667] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DDI C]
>[ 3224.028729] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST A]
>[ 3224.028790] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST B]
>[ 3224.028851] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI D]
>[ 3224.028911] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[ 3224.028969] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[ 3224.029035] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[ 3224.029104] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[ 3224.029168] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[ 3224.029231] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[ 3224.029307] [drm:intel_fbc_enable [i915]] reserved 16588800 bytes of contiguous stolen space for FBC, threshold: 1
>[ 3224.029373] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 3224.035687] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 2, on? 0) for crtc 47
>[ 3224.035764] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[ 3224.035880] [drm:intel_power_well_enable [i915]] enabling DDI B IO power well
>[ 3224.036536] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 3224.037793] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 3224.039054] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 3224.040332] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 3224.041589] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 3224.042472] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[ 3224.043469] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 3224.043536] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 3224.043598] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 3224.043660] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 3224.062348] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 3224.062376] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[ 3224.081134] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 3224.081471] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:57:DP-1] Link Training Passed at Link Rate = 162000, Lane count = 4
>[ 3224.081854] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 3224.081907] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS
>[ 3224.801233] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 3224.801315] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 3225.064752] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 3225.064833] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 3234.268213] [drm:drm_atomic_helper_wait_for_flip_done [drm_kms_helper]] *ERROR* [CRTC:37:pipe A] flip_done timed out
>[ 3234.268347] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:57:DP-1]
>[ 3234.268431] [drm:intel_atomic_commit_tail [i915]] [CRTC:47:pipe B]
>[ 3234.268530] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[ 3234.268581] [drm:drm_fb_helper_hotplug_event.part.30 [drm_kms_helper]] 
>[ 3234.268594] [drm:drm_setup_crtcs [drm_kms_helper]] 
>[ 3234.268609] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:49:eDP-1]
>[ 3234.268685] [drm:intel_dp_detect [i915]] [CONNECTOR:49:eDP-1]
>[ 3234.268776] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>[ 3234.268844] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[ 3234.268908] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[ 3234.268988] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[ 3234.269132] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006f
>[ 3234.269583] [drm:drm_dp_read_desc [drm_kms_helper]] DP sink: OUI 00-1c-f8 dev-ID  HW-rev 0.1 SW-rev 1.22 quirks 0x0000
>[ 3234.270317] [drm:drm_add_edid_modes [drm]] ELD: no CEA Extension found
>[ 3234.270369] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:49:eDP-1] probed modes :
>[ 3234.270398] [drm:drm_mode_debug_printmodeline [drm]] Modeline 50:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[ 3234.270410] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:57:DP-1]
>[ 3234.270892] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 00 00 04 00 0f 00 04
>[ 3234.272336] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[ 3234.272420] [drm:intel_dp_detect [i915]] [CONNECTOR:57:DP-1]
>[ 3234.272810] [drm:lspcon_wake_native_aux_ch [i915]] Native AUX CH up, DPCD version: 1.2
>[ 3234.272886] [drm:lspcon_resume [i915]] LSPCON recovering in PCON mode after 0 ms
>[ 3234.273328] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 3234.274583] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 3234.275841] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 3234.277121] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 3234.278381] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 3234.279252] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[ 3234.279727] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 00 00 04 00 0f 00 04
>[ 3234.280532] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>[ 3234.280591] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000
>[ 3234.280646] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000
>[ 3234.281049] [drm:drm_dp_read_desc [drm_kms_helper]] DP branch: OUI 00-60-ad dev-ID MC2800 HW-rev 2.2 SW-rev 1.70 quirks 0x0000
>[ 3234.281402] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[ 3234.282177] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 3234.283402] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 3234.284599] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 3234.285827] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 3234.287082] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 3234.288344] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 3234.289610] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 3234.290868] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 3234.292120] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 3234.293500] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 3234.294849] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 3234.296201] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 3234.297553] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 3234.298938] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 3234.300344] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 3234.301727] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 3234.303088] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 3234.304352] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 3234.305610] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 3234.306868] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 3234.308125] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 3234.309512] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 3234.310898] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 3234.312314] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 3234.313694] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 3234.315078] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 3234.316463] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 3234.317842] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 3234.319218] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 3234.320379] [drm:drm_add_edid_modes [drm]] ELD monitor HP E232
>[ 3234.320405] [drm:drm_add_edid_modes [drm]] HDMI: latency present 0 0, video latency 0 0, audio latency 0 0
>[ 3234.320424] [drm:drm_add_edid_modes [drm]] ELD size 28, SAD count 0
>[ 3234.320442] [drm:drm_add_edid_modes [drm]] HDMI: DVI dual 0, max TMDS clock 170000 kHz
>[ 3234.320726] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:57:DP-1] probed modes :
>[ 3234.320750] [drm:drm_mode_debug_printmodeline [drm]] Modeline 74:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[ 3234.320776] [drm:drm_mode_debug_printmodeline [drm]] Modeline 97:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[ 3234.320802] [drm:drm_mode_debug_printmodeline [drm]] Modeline 76:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[ 3234.320827] [drm:drm_mode_debug_printmodeline [drm]] Modeline 81:"1680x1050" 60 119000 1680 1728 1760 1840 1050 1053 1059 1080 0x40 0x9
>[ 3234.320853] [drm:drm_mode_debug_printmodeline [drm]] Modeline 80:"1600x900" 60 108000 1600 1624 1704 1800 900 901 904 1000 0x40 0x5
>[ 3234.320876] [drm:drm_mode_debug_printmodeline [drm]] Modeline 84:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[ 3234.320898] [drm:drm_mode_debug_printmodeline [drm]] Modeline 82:"1440x900" 60 88750 1440 1488 1520 1600 900 903 909 926 0x40 0x9
>[ 3234.320931] [drm:drm_mode_debug_printmodeline [drm]] Modeline 83:"1280x800" 60 71000 1280 1328 1360 1440 800 803 809 823 0x40 0x9
>[ 3234.320956] [drm:drm_mode_debug_printmodeline [drm]] Modeline 77:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[ 3234.320981] [drm:drm_mode_debug_printmodeline [drm]] Modeline 99:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[ 3234.321006] [drm:drm_mode_debug_printmodeline [drm]] Modeline 78:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[ 3234.321031] [drm:drm_mode_debug_printmodeline [drm]] Modeline 87:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[ 3234.321056] [drm:drm_mode_debug_printmodeline [drm]] Modeline 85:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[ 3234.321082] [drm:drm_mode_debug_printmodeline [drm]] Modeline 95:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[ 3234.321106] [drm:drm_mode_debug_printmodeline [drm]] Modeline 100:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[ 3234.321131] [drm:drm_mode_debug_printmodeline [drm]] Modeline 79:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[ 3234.321157] [drm:drm_mode_debug_printmodeline [drm]] Modeline 101:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[ 3234.321182] [drm:drm_mode_debug_printmodeline [drm]] Modeline 86:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[ 3234.321205] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:61:DP-2]
>[ 3234.321279] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 00 00 04 00 0f 00 04
>[ 3234.322706] [drm:intel_dp_detect [i915]] [CONNECTOR:61:DP-2]
>[ 3234.322734] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:61:DP-2] disconnected
>[ 3234.322746] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:64:HDMI-A-1]
>[ 3234.322807] [drm:intel_hdmi_detect [i915]] [CONNECTOR:64:HDMI-A-1]
>[ 3234.323185] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[ 3234.323241] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[ 3234.323611] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[ 3234.323639] [drm:drm_do_probe_ddc_edid [drm]] drm: skipping non-existent adapter i915 gmbus dpc
>[ 3234.324020] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[ 3234.324079] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[ 3234.324506] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[ 3234.324528] [drm:drm_dp_dual_mode_detect [drm_kms_helper]] DP dual mode HDMI ID:  (err -6)
>[ 3234.324548] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:64:HDMI-A-1] disconnected
>[ 3234.324565] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:67:DP-3]
>[ 3234.324627] [drm:intel_dp_detect [i915]] [CONNECTOR:67:DP-3]
>[ 3234.324655] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:67:DP-3] disconnected
>[ 3234.324665] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:70:HDMI-A-2]
>[ 3234.324720] [drm:intel_hdmi_detect [i915]] [CONNECTOR:70:HDMI-A-2]
>[ 3234.335548] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0050 w(1)
>[ 3234.335611] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK on first message, retry
>[ 3234.346621] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0050 w(1)
>[ 3234.346647] [drm:drm_do_probe_ddc_edid [drm]] drm: skipping non-existent adapter i915 gmbus dpd
>[ 3234.357356] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0040 w(1)
>[ 3234.357412] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK on first message, retry
>[ 3234.368021] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0040 w(1)
>[ 3234.368036] [drm:drm_dp_dual_mode_detect [drm_kms_helper]] DP dual mode HDMI ID:  (err -6)
>[ 3234.368048] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:70:HDMI-A-2] disconnected
>[ 3234.368061] [drm:drm_setup_crtcs [drm_kms_helper]] connector 49 enabled? yes
>[ 3234.368071] [drm:drm_setup_crtcs [drm_kms_helper]] connector 57 enabled? yes
>[ 3234.368080] [drm:drm_setup_crtcs [drm_kms_helper]] connector 61 enabled? no
>[ 3234.368089] [drm:drm_setup_crtcs [drm_kms_helper]] connector 64 enabled? no
>[ 3234.368098] [drm:drm_setup_crtcs [drm_kms_helper]] connector 67 enabled? no
>[ 3234.368107] [drm:drm_setup_crtcs [drm_kms_helper]] connector 70 enabled? no
>[ 3234.368169] [drm:intel_fb_initial_config [i915]] Not using firmware configuration
>[ 3234.368181] [drm:drm_setup_crtcs [drm_kms_helper]] looking for cmdline mode on connector 49
>[ 3234.368191] [drm:drm_setup_crtcs [drm_kms_helper]] looking for preferred mode on connector 49 0
>[ 3234.368200] [drm:drm_setup_crtcs [drm_kms_helper]] found mode 1920x1080
>[ 3234.368209] [drm:drm_setup_crtcs [drm_kms_helper]] looking for cmdline mode on connector 57
>[ 3234.368218] [drm:drm_setup_crtcs [drm_kms_helper]] looking for preferred mode on connector 57 0
>[ 3234.368227] [drm:drm_setup_crtcs [drm_kms_helper]] found mode 1920x1080
>[ 3234.368237] [drm:drm_setup_crtcs [drm_kms_helper]] picking CRTCs for 1920x1080 config
>[ 3234.368253] [drm:drm_setup_crtcs [drm_kms_helper]] desired mode 1920x1080 set on crtc 37 (0,0)
>[ 3234.368263] [drm:drm_setup_crtcs [drm_kms_helper]] desired mode 1920x1080 set on crtc 47 (0,0)
>[ 3237.340193] [drm:edp_panel_vdd_off_sync [i915]] Turning eDP port A VDD off
>[ 3237.340337] [drm:edp_panel_vdd_off_sync [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x00000067
>[ 3244.508117] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [CRTC:37:pipe A] flip_done timed out
>[ 3254.748119] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [CONNECTOR:49:eDP-1] flip_done timed out
>[ 3264.988102] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [PLANE:28:plane 1A] flip_done timed out
>[ 3275.228217] [drm:drm_atomic_helper_wait_for_flip_done [drm_kms_helper]] *ERROR* [CRTC:37:pipe A] flip_done timed out
>[ 3275.285868] [IGT] kms_frontbuffer_tracking: executing
>[ 3275.346131] [drm:drm_mode_addfb2 [drm]] [FB:72]
>[ 3275.346175] [drm:drm_mode_addfb2 [drm]] [FB:73]
>[ 3275.346216] [drm:drm_mode_addfb2 [drm]] [FB:92]
>[ 3275.347015] [drm:drm_mode_addfb2 [drm]] [FB:93]
>[ 3275.350915] [drm:drm_mode_addfb2 [drm]] [FB:94]
>[ 3275.351769] [drm:drm_mode_addfb2 [drm]] [FB:96]
>[ 3275.351789] [drm:drm_mode_addfb2 [drm]] [FB:98]
>[ 3275.351811] [drm:drm_mode_addfb2 [drm]] [FB:102]
>[ 3275.352137] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[ 3275.352144] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[ 3285.468136] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [CRTC:37:pipe A] flip_done timed out
>[ 3295.708178] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [CONNECTOR:49:eDP-1] flip_done timed out
>[ 3305.948216] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [PLANE:28:plane 1A] flip_done timed out
>[ 3316.188194] [drm:drm_atomic_helper_wait_for_flip_done [drm_kms_helper]] *ERROR* [CRTC:37:pipe A] flip_done timed out
>[ 3316.188385] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[ 3316.188539] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006f
>[ 3316.384359] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped
>[ 3316.384601] [IGT] kms_frontbuffer_tracking: starting subtest psr-1p-offscren-pri-shrfb-draw-mmap-cpu
>[ 3316.384677] Setting dangerous option enable_fbc - tainting kernel
>[ 3316.384701] Setting dangerous option enable_psr - tainting kernel
>[ 3319.516301] [drm:edp_panel_vdd_off_sync [i915]] Turning eDP port A VDD off
>[ 3319.516447] [drm:edp_panel_vdd_off_sync [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x00000067
>[ 3326.428106] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [CRTC:37:pipe A] flip_done timed out
>[ 3336.667941] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [PLANE:28:plane 1A] flip_done timed out
>[ 3346.908194] [drm:drm_atomic_helper_wait_for_flip_done [drm_kms_helper]] *ERROR* [CRTC:37:pipe A] flip_done timed out
>[ 3346.912608] [drm:drm_mode_addfb2 [drm]] [FB:72]
>[ 3346.912712] [drm:drm_mode_addfb2 [drm]] [FB:73]
>[ 3346.912816] [drm:drm_mode_addfb2 [drm]] [FB:89]
>[ 3346.913603] [drm:drm_mode_addfb2 [drm]] [FB:92]
>[ 3346.917344] [drm:drm_mode_addfb2 [drm]] [FB:93]
>[ 3346.918186] [drm:drm_mode_addfb2 [drm]] [FB:94]
>[ 3346.918205] [drm:drm_mode_addfb2 [drm]] [FB:96]
>[ 3346.918225] [drm:drm_mode_addfb2 [drm]] [FB:98]
>[ 3346.918337] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[ 3346.918370] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 3346.918383] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[ 3357.148209] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [CRTC:37:pipe A] flip_done timed out
>[ 3367.388102] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [CONNECTOR:49:eDP-1] flip_done timed out
>[ 3377.628191] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [PLANE:28:plane 1A] flip_done timed out
>[ 3377.628318] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[ 3377.628474] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006f
>[ 3377.628758] [drm:intel_edp_backlight_off [i915]] 
>[ 3377.836152] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0
>[ 3377.836292] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 3377.850233] [drm:intel_edp_panel_off.part.31 [i915]] Turn eDP port A panel power off
>[ 3377.850346] [drm:intel_edp_panel_off.part.31 [i915]] Wait for panel power off time
>[ 3377.850477] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000002 control 00000060
>[ 3377.900733] [drm:wait_panel_status [i915]] Wait complete
>[ 3377.900797] [drm:intel_power_well_disable [i915]] disabling DDI A/E IO power well
>[ 3377.900880] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 3377.900962] [drm:intel_disable_shared_dpll [i915]] disable DPLL 0 (active 1, on? 1) for crtc 37
>[ 3377.901034] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 0
>[ 3377.901126] [drm:intel_atomic_commit_tail [i915]] [ENCODER:48:DDI A]
>[ 3377.901197] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI B]
>[ 3377.901264] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[ 3377.901328] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[ 3377.901391] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DDI C]
>[ 3377.901453] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST A]
>[ 3377.901513] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST B]
>[ 3377.901574] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI D]
>[ 3377.901633] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[ 3377.901692] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[ 3377.901757] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:49:eDP-1]
>[ 3377.901824] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[ 3377.901887] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[ 3377.901951] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[ 3377.902013] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[ 3377.910166] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010
>[ 3377.910238] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[ 3377.910305] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0
>[ 3377.910413] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[ 3377.915968] [drm:intel_atomic_commit_tail [i915]] [CRTC:37:pipe A]
>[ 3377.916032] [drm:intel_enable_sagv [i915]] Enabling the SAGV
>[ 3377.916123] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[ 3377.916211] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 3377.916275] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[ 3377.916368] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 3377.933063] [drm:intel_power_well_disable [i915]] disabling DDI B IO power well
>[ 3377.933146] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 2, on? 1) for crtc 47
>[ 3377.933220] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[ 3377.933310] [drm:intel_atomic_commit_tail [i915]] [ENCODER:48:DDI A]
>[ 3377.933377] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI B]
>[ 3377.933442] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[ 3377.933502] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[ 3377.933560] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DDI C]
>[ 3377.933617] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST A]
>[ 3377.933674] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST B]
>[ 3377.933730] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI D]
>[ 3377.933786] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[ 3377.933841] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[ 3377.933903] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:57:DP-1]
>[ 3377.933966] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[ 3377.934026] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[ 3377.934086] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[ 3377.934144] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[ 3377.934202] [drm:intel_power_well_disable [i915]] disabling power well 2
>[ 3377.934273] [drm:intel_atomic_commit_tail [i915]] [CRTC:47:pipe B]
>[ 3377.934327] [drm:intel_power_well_disable [i915]] disabling DC off
>[ 3377.934378] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[ 3377.934426] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[ 3377.934865] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 3377.938959] [drm:drm_mode_addfb2 [drm]] [FB:91]
>[ 3377.940866] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[ 3377.940872] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[ 3377.940893] [drm:intel_atomic_check [i915]] [CONNECTOR:49:eDP-1] checking for sink bpp constrains
>[ 3377.940906] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 3377.940912] [drm:drm_mode_debug_printmodeline [drm]] Modeline 52:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[ 3377.940925] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 138780KHz
>[ 3377.940941] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24
>[ 3377.940952] [drm:intel_dp_compute_config [i915]] DP link bw required 416340 available 540000
>[ 3377.940964] [drm:intel_dp_compute_config [i915]] PSR disable by flag
>[ 3377.940976] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 3377.940989] [drm:intel_dump_pipe_config [i915]] [CRTC:37:pipe A][modeset]
>[ 3377.941001] [drm:intel_dump_pipe_config [i915]] output_types: EDP (0x100)
>[ 3377.941012] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0
>[ 3377.941024] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 6467616, gmch_n: 8388608, link_m: 269484, link_n: 524288, tu: 64
>[ 3377.941035] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[ 3377.941046] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 3377.941051] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[ 3377.941062] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 3377.941067] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[ 3377.941078] [drm:intel_dump_pipe_config [i915]] crtc timings: 138780 1920 1966 1996 2080 1080 1082 1086 1112, type: 0x48 flags: 0xa
>[ 3377.941089] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 138780
>[ 3377.941100] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[ 3377.941110] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 3377.941121] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 3377.941131] [drm:intel_dump_pipe_config [i915]] dpll_hw_state: ctrl1: 0x3, cfgcr1: 0x0, cfgcr2: 0x0
>[ 3377.941141] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 3377.941151] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 1A] disabled, scaler_id = -1
>[ 3377.941162] [drm:intel_dump_pipe_config [i915]] [PLANE:31:plane 2A] disabled, scaler_id = -1
>[ 3377.941172] [drm:intel_dump_pipe_config [i915]] [PLANE:34:cursor A] disabled, scaler_id = -1
>[ 3377.941185] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 3377.941196] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[ 3377.941211] [drm:intel_find_shared_dpll [i915]] [CRTC:37:pipe A] allocated DPLL 0
>[ 3377.941222] [drm:intel_reference_shared_dpll [i915]] using DPLL 0 for pipe A
>[ 3377.941805] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 3377.941818] [drm:intel_power_well_enable [i915]] enabling DC off
>[ 3377.942098] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[ 3377.942122] [drm:intel_atomic_commit_tail [i915]] [ENCODER:48:DDI A]
>[ 3377.942141] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI B]
>[ 3377.942156] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[ 3377.942168] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[ 3377.942179] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DDI C]
>[ 3377.942190] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST A]
>[ 3377.942201] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST B]
>[ 3377.942212] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI D]
>[ 3377.942222] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[ 3377.942232] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[ 3377.942244] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[ 3377.942256] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[ 3377.942268] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[ 3377.942279] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[ 3377.942292] [drm:intel_enable_shared_dpll [i915]] enable DPLL 0 (active 1, on? 0) for crtc 37
>[ 3377.942303] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 0
>[ 3377.942322] [drm:edp_panel_on [i915]] Turn eDP port A panel power on
>[ 3377.942346] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle
>[ 3378.524421] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 00000000 control 00000060
>[ 3378.524530] [drm:wait_panel_status [i915]] Wait complete
>[ 3378.524668] [drm:edp_panel_on [i915]] Wait for panel power on
>[ 3378.524802] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 00000063
>[ 3378.558339] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010
>[ 3378.558420] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[ 3378.558495] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1
>[ 3378.558609] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[ 3378.724934] [drm:wait_panel_status [i915]] Wait complete
>[ 3378.725001] [drm:intel_power_well_enable [i915]] enabling DDI A/E IO power well
>[ 3378.725102] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[ 3378.725254] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b
>[ 3378.726489] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 3378.726563] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 3378.726631] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 3378.726696] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 3378.727410] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 3378.727470] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 3378.728491] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 3378.728555] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:49:eDP-1] Link Training Passed at Link Rate = 270000, Lane count = 2
>[ 3378.729207] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 3378.729285] [drm:intel_edp_backlight_on [i915]] 
>[ 3378.729348] [drm:intel_panel_enable_backlight [i915]] pipe A
>[ 3378.729437] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 120000
>[ 3378.739985] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS
>[ 3381.980044] [drm:edp_panel_vdd_off_sync [i915]] Turning eDP port A VDD off
>[ 3381.980189] [drm:edp_panel_vdd_off_sync [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x00000067
>[ 3388.892112] [drm:drm_atomic_helper_wait_for_flip_done [drm_kms_helper]] *ERROR* [CRTC:37:pipe A] flip_done timed out
>[ 3388.892230] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:49:eDP-1]
>[ 3388.892315] [drm:intel_atomic_commit_tail [i915]] [CRTC:37:pipe A]
>[ 3388.892411] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[ 3388.892475] [drm:intel_power_well_disable [i915]] disabling DC off
>[ 3388.892532] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[ 3388.892585] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[ 3388.929450] [drm:intel_power_well_enable [i915]] enabling DC off
>[ 3388.929510] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[ 3388.929607] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[ 3388.929760] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006f
>[ 3389.129717] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped
>[ 3389.129803] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[ 3389.129897] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 3389.129958] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[ 3392.220297] [drm:edp_panel_vdd_off_sync [i915]] Turning eDP port A VDD off
>[ 3392.220442] [drm:edp_panel_vdd_off_sync [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x00000067
>[ 3392.220499] [drm:intel_power_well_disable [i915]] disabling DC off
>[ 3392.220556] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[ 3392.220608] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[ 3398.670336] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 3398.670417] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 3398.670544] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[ 3398.670609] [drm:intel_power_well_enable [i915]] enabling DC off
>[ 3398.670675] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[ 3398.670735] [drm:intel_power_well_enable [i915]] enabling power well 2
>[ 3398.939526] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 3398.939608] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 3399.132048] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [CRTC:37:pipe A] flip_done timed out
>[ 3403.714530] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 3403.714611] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 3403.983774] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 3403.983855] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 3409.372116] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [CONNECTOR:49:eDP-1] flip_done timed out
>[ 3409.557217] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 3409.557298] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 3409.839994] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 3409.840075] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 3415.413517] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 3415.413594] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 3415.682668] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 3415.682749] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 3419.612222] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [PLANE:28:plane 1A] flip_done timed out
>[ 3419.612328] [drm:intel_edp_backlight_off [i915]] 
>[ 3419.820156] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0
>[ 3419.820291] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 3419.831217] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[ 3419.831375] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b
>[ 3419.831652] [drm:intel_edp_panel_off.part.31 [i915]] Turn eDP port A panel power off
>[ 3419.831756] [drm:intel_edp_panel_off.part.31 [i915]] Wait for panel power off time
>[ 3419.831882] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000002 control 00000060
>[ 3419.884477] [drm:wait_panel_status [i915]] Wait complete
>[ 3419.884539] [drm:intel_power_well_disable [i915]] disabling DDI A/E IO power well
>[ 3419.884625] [drm:intel_disable_shared_dpll [i915]] disable DPLL 0 (active 1, on? 1) for crtc 37
>[ 3419.884700] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 0
>[ 3419.884791] [drm:intel_atomic_commit_tail [i915]] [ENCODER:48:DDI A]
>[ 3419.884863] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI B]
>[ 3419.884930] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[ 3419.884993] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[ 3419.885056] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DDI C]
>[ 3419.885118] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST A]
>[ 3419.885178] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST B]
>[ 3419.885238] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI D]
>[ 3419.885298] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[ 3419.885358] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[ 3419.885424] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:49:eDP-1]
>[ 3419.885491] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[ 3419.885555] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[ 3419.885618] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[ 3419.885679] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[ 3419.885755] [drm:intel_atomic_commit_tail [i915]] [CRTC:37:pipe A]
>[ 3419.885873] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[ 3419.886342] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 00 00 04 00 0f 00 04
>[ 3419.891261] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010
>[ 3419.891278] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[ 3419.891295] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0
>[ 3419.914958] [drm:intel_power_well_disable [i915]] disabling power well 2
>[ 3419.914976] [drm:intel_power_well_disable [i915]] disabling DC off
>[ 3419.914991] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[ 3419.915005] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[ 3419.915020] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 3419.915042] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[ 3419.915061] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[ 3419.915076] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 3419.915089] [drm:intel_power_well_enable [i915]] enabling DC off
>[ 3419.915410] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[ 3419.915425] [drm:intel_power_well_enable [i915]] enabling power well 2
>[ 3419.915834] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 00 00 04 00 0f 00 04
>[ 3419.916508] [drm:drm_mode_addfb2 [drm]] [FB:91]
>[ 3419.917118] [drm:intel_power_well_disable [i915]] disabling power well 2
>[ 3419.917134] [drm:intel_power_well_disable [i915]] disabling DC off
>[ 3419.917150] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[ 3419.917163] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[ 3419.917178] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 3419.917800] [drm:drm_mode_addfb2 [drm]] [FB:102]
>[ 3419.919326] [drm:drm_mode_addfb2 [drm]] [FB:103]
>[ 3419.920408] [drm:drm_mode_addfb2 [drm]] [FB:104]
>[ 3419.992556] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[ 3419.992563] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[ 3419.992589] [drm:intel_atomic_check [i915]] [CONNECTOR:49:eDP-1] checking for sink bpp constrains
>[ 3419.992603] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 3419.992609] [drm:drm_mode_debug_printmodeline [drm]] Modeline 52:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[ 3419.992623] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 138780KHz
>[ 3419.992640] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24
>[ 3419.992651] [drm:intel_dp_compute_config [i915]] DP link bw required 416340 available 540000
>[ 3419.992663] [drm:intel_dp_compute_config [i915]] PSR disable by flag
>[ 3419.992676] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 3419.992689] [drm:intel_dump_pipe_config [i915]] [CRTC:37:pipe A][modeset]
>[ 3419.992702] [drm:intel_dump_pipe_config [i915]] output_types: EDP (0x100)
>[ 3419.992714] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0
>[ 3419.992725] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 6467616, gmch_n: 8388608, link_m: 269484, link_n: 524288, tu: 64
>[ 3419.992736] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[ 3419.992747] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 3419.992753] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[ 3419.992764] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 3419.992770] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[ 3419.992781] [drm:intel_dump_pipe_config [i915]] crtc timings: 138780 1920 1966 1996 2080 1080 1082 1086 1112, type: 0x48 flags: 0xa
>[ 3419.992792] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 138780
>[ 3419.992803] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[ 3419.992814] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 3419.992824] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 3419.992835] [drm:intel_dump_pipe_config [i915]] dpll_hw_state: ctrl1: 0x3, cfgcr1: 0x0, cfgcr2: 0x0
>[ 3419.992846] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 3419.992856] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 1A] disabled, scaler_id = -1
>[ 3419.992867] [drm:intel_dump_pipe_config [i915]] [PLANE:31:plane 2A] disabled, scaler_id = -1
>[ 3419.992878] [drm:intel_dump_pipe_config [i915]] [PLANE:34:cursor A] disabled, scaler_id = -1
>[ 3419.992891] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 3419.992902] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[ 3419.992917] [drm:intel_find_shared_dpll [i915]] [CRTC:37:pipe A] allocated DPLL 0
>[ 3419.992929] [drm:intel_reference_shared_dpll [i915]] using DPLL 0 for pipe A
>[ 3419.993892] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 3419.993920] [drm:intel_power_well_enable [i915]] enabling DC off
>[ 3419.994196] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[ 3419.994215] [drm:intel_atomic_commit_tail [i915]] [ENCODER:48:DDI A]
>[ 3419.994229] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI B]
>[ 3419.994243] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[ 3419.994256] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[ 3419.994269] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DDI C]
>[ 3419.994281] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST A]
>[ 3419.994296] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST B]
>[ 3419.994313] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI D]
>[ 3419.994331] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[ 3419.994365] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[ 3419.994384] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[ 3419.994399] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[ 3419.994411] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[ 3419.994423] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[ 3419.994437] [drm:intel_enable_shared_dpll [i915]] enable DPLL 0 (active 1, on? 0) for crtc 37
>[ 3419.994449] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 0
>[ 3419.994469] [drm:edp_panel_on [i915]] Turn eDP port A panel power on
>[ 3419.994495] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle
>[ 3420.508304] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 00000000 control 00000060
>[ 3420.508402] [drm:wait_panel_status [i915]] Wait complete
>[ 3420.508532] [drm:edp_panel_on [i915]] Wait for panel power on
>[ 3420.508657] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 00000063
>[ 3420.542195] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010
>[ 3420.542267] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[ 3420.542333] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1
>[ 3420.542435] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[ 3420.708971] [drm:wait_panel_status [i915]] Wait complete
>[ 3420.709038] [drm:intel_power_well_enable [i915]] enabling DDI A/E IO power well
>[ 3420.709140] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[ 3420.709291] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b
>[ 3420.710527] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 3420.710600] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 3420.710663] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 3420.710727] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 3420.711452] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 3420.711505] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 3420.712504] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 3420.712559] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:49:eDP-1] Link Training Passed at Link Rate = 270000, Lane count = 2
>[ 3420.713195] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 3420.713260] [drm:intel_edp_backlight_on [i915]] 
>[ 3420.713316] [drm:intel_panel_enable_backlight [i915]] pipe A
>[ 3420.713399] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 120000
>[ 3420.719983] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS
>[ 3421.234731] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 3421.234813] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 3421.234938] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[ 3421.235003] [drm:intel_power_well_enable [i915]] enabling power well 2
>[ 3421.493549] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 3421.493630] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 3423.964036] [drm:edp_panel_vdd_off_sync [i915]] Turning eDP port A VDD off
>[ 3423.964181] [drm:edp_panel_vdd_off_sync [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x00000067
>[ 3427.063524] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 3427.063605] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 3427.326012] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 3427.326094] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 3430.876110] [drm:drm_atomic_helper_wait_for_flip_done [drm_kms_helper]] *ERROR* [CRTC:37:pipe A] flip_done timed out
>[ 3430.876233] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:49:eDP-1]
>[ 3430.876317] [drm:intel_atomic_commit_tail [i915]] [CRTC:37:pipe A]
>[ 3430.876414] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[ 3430.876999] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 00 00 04 00 0f 00 04
>[ 3430.878399] [drm:intel_power_well_disable [i915]] disabling power well 2
>[ 3430.878450] [drm:intel_power_well_disable [i915]] disabling DC off
>[ 3430.878495] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[ 3430.878539] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[ 3430.878603] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[ 3430.878645] [drm:intel_power_well_enable [i915]] enabling DC off
>[ 3430.878687] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[ 3430.878733] [drm:intel_power_well_enable [i915]] enabling power well 2
>[ 3430.879209] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 00 00 04 00 0f 00 04
>[ 3430.880623] [drm:intel_power_well_disable [i915]] disabling power well 2
>[ 3430.880676] [drm:intel_power_well_disable [i915]] disabling DC off
>[ 3430.880725] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[ 3430.880771] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[ 3430.913397] [drm:intel_power_well_enable [i915]] enabling DC off
>[ 3430.913450] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[ 3430.913540] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[ 3430.913685] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006f
>[ 3431.113485] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped
>[ 3431.113530] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[ 3431.113560] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[ 3432.901791] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 3432.901872] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 3432.901992] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[ 3432.902058] [drm:intel_power_well_enable [i915]] enabling power well 2
>[ 3433.161228] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 3433.161309] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 3434.204288] [drm:edp_panel_vdd_off_sync [i915]] Turning eDP port A VDD off
>[ 3434.204434] [drm:edp_panel_vdd_off_sync [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x00000067
>[ 3438.736927] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 3438.737008] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 3438.998948] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 3438.999030] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 3441.116081] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [CRTC:37:pipe A] flip_done timed out
>[ 3444.573471] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 3444.573552] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 3444.835312] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 3444.835393] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 3450.411397] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 3450.411479] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 3450.671352] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 3450.671433] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 3451.356209] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [CONNECTOR:49:eDP-1] flip_done timed out
>[ 3456.247427] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 3456.247508] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 3456.505812] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 3456.505895] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 3461.596231] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [PLANE:28:plane 1A] flip_done timed out
>[ 3462.082346] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 3462.082428] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 3462.342750] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 3462.342831] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 3467.909543] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 3467.909624] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 3468.169179] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 3468.169260] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 3471.836093] [drm:drm_atomic_helper_wait_for_flip_done [drm_kms_helper]] *ERROR* [CRTC:37:pipe A] flip_done timed out
>[ 3471.836695] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 00 00 04 00 0f 00 04
>[ 3471.838107] [drm:intel_power_well_disable [i915]] disabling power well 2
>[ 3471.838165] [drm:intel_power_well_disable [i915]] disabling DC off
>[ 3471.838216] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[ 3471.838264] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[ 3471.838339] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[ 3471.838388] [drm:intel_power_well_enable [i915]] enabling DC off
>[ 3471.838435] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[ 3471.838487] [drm:intel_power_well_enable [i915]] enabling power well 2
>[ 3471.838972] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 00 00 04 00 0f 00 04
>[ 3471.840398] [drm:intel_power_well_disable [i915]] disabling power well 2
>[ 3471.840450] [drm:intel_power_well_disable [i915]] disabling DC off
>[ 3471.840499] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[ 3471.840547] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[ 3471.879177] [drm:intel_power_well_enable [i915]] enabling DC off
>[ 3471.879229] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[ 3471.879317] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[ 3471.879463] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006f
>[ 3472.079454] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped
>[ 3472.079503] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[ 3472.079534] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[ 3473.741516] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 3473.741597] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 3473.741717] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[ 3473.741784] [drm:intel_power_well_enable [i915]] enabling power well 2
>[ 3474.002162] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 3474.002243] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 3475.164144] [drm:edp_panel_vdd_off_sync [i915]] Turning eDP port A VDD off
>[ 3475.164290] [drm:edp_panel_vdd_off_sync [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x00000067
>[ 3479.573014] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 3479.573095] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 3479.833895] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 3479.833976] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 3482.332085] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [CRTC:37:pipe A] flip_done timed out
>[ 3485.399566] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 3485.399648] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 3485.661117] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 3485.661199] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 3491.234936] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 3491.235017] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 3491.494056] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 3491.494137] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 3492.572208] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [CONNECTOR:49:eDP-1] flip_done timed out
>[ 3497.061147] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 3497.061229] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 3497.320103] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 3497.320184] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 3502.812178] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [PLANE:28:plane 1A] flip_done timed out
>[ 3502.888859] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 3502.888940] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 3503.150173] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 3503.150255] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 3508.716916] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 3508.716997] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 3508.977960] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 3508.978041] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 3513.052111] [drm:drm_atomic_helper_wait_for_flip_done [drm_kms_helper]] *ERROR* [CRTC:37:pipe A] flip_done timed out
>[ 3513.052703] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 00 00 04 00 0f 00 04
>[ 3513.054109] [drm:intel_power_well_disable [i915]] disabling power well 2
>[ 3513.054167] [drm:intel_power_well_disable [i915]] disabling DC off
>[ 3513.054218] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[ 3513.054267] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[ 3513.054343] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[ 3513.054391] [drm:intel_power_well_enable [i915]] enabling DC off
>[ 3513.054438] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[ 3513.054490] [drm:intel_power_well_enable [i915]] enabling power well 2
>[ 3513.054973] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 00 00 04 00 0f 00 04
>[ 3513.056404] [drm:intel_power_well_disable [i915]] disabling power well 2
>[ 3513.056457] [drm:intel_power_well_disable [i915]] disabling DC off
>[ 3513.056506] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[ 3513.056555] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[ 3513.095123] [drm:intel_power_well_enable [i915]] enabling DC off
>[ 3513.095176] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[ 3513.095262] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[ 3513.095408] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006f
>[ 3513.295404] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped
>[ 3513.295453] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[ 3513.295484] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[ 3514.552095] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 3514.552175] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 3514.552298] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[ 3514.552362] [drm:intel_power_well_enable [i915]] enabling power well 2
>[ 3514.813756] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 3514.813838] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 3516.380145] [drm:edp_panel_vdd_off_sync [i915]] Turning eDP port A VDD off
>[ 3516.380290] [drm:edp_panel_vdd_off_sync [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x00000067
>[ 3520.383701] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 3520.383783] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 3520.645017] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 3520.645098] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 3523.548081] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [CRTC:37:pipe A] flip_done timed out
>[ 3526.215257] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 3526.215338] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 3526.475819] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 3526.475900] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 3532.049936] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 3532.050018] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 3532.311252] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 3532.311333] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 3533.788211] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [CONNECTOR:49:eDP-1] flip_done timed out
>[ 3537.875339] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 3537.875422] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 3538.137135] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 3538.137217] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 3543.701969] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 3543.702051] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 3543.961246] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 3543.961327] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 3544.028125] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [PLANE:28:plane 1A] flip_done timed out
>[ 3549.530833] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 3549.530914] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 3549.791655] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 3549.791735] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 3554.268205] [drm:drm_atomic_helper_wait_for_flip_done [drm_kms_helper]] *ERROR* [CRTC:37:pipe A] flip_done timed out
>[ 3554.268804] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 00 00 04 00 0f 00 04
>[ 3554.270206] [drm:intel_power_well_disable [i915]] disabling power well 2
>[ 3554.270263] [drm:intel_power_well_disable [i915]] disabling DC off
>[ 3554.270313] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[ 3554.270361] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[ 3554.270437] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[ 3554.270485] [drm:intel_power_well_enable [i915]] enabling DC off
>[ 3554.270532] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[ 3554.270583] [drm:intel_power_well_enable [i915]] enabling power well 2
>[ 3554.271067] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 00 00 04 00 0f 00 04
>[ 3554.272502] [drm:intel_power_well_disable [i915]] disabling power well 2
>[ 3554.272554] [drm:intel_power_well_disable [i915]] disabling DC off
>[ 3554.272603] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[ 3554.272649] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[ 3554.311070] [drm:intel_power_well_enable [i915]] enabling DC off
>[ 3554.311122] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[ 3554.311209] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[ 3554.311353] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006f
>[ 3554.511360] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped
>[ 3554.511491] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[ 3554.511584] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 3554.511647] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[ 3555.361687] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 3555.361768] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 3555.361893] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[ 3555.361960] [drm:intel_power_well_enable [i915]] enabling power well 2
>[ 3555.624412] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 3555.624489] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 3557.596035] [drm:edp_panel_vdd_off_sync [i915]] Turning eDP port A VDD off
>[ 3557.596179] [drm:edp_panel_vdd_off_sync [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x00000067
>[ 3561.200734] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 3561.200815] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 3561.463204] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 3561.463285] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 3564.764076] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [CRTC:37:pipe A] flip_done timed out
>[ 3567.034794] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 3567.034875] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 3567.294582] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 3567.294664] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 3572.854455] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 3572.854536] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 3573.115495] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 3573.115576] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 3575.004092] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [CONNECTOR:49:eDP-1] flip_done timed out
>[ 3578.685753] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 3578.685835] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 3578.947938] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 3578.948019] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 3584.518004] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 3584.518086] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 3584.777971] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 3584.778052] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 3585.244089] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [PLANE:28:plane 1A] flip_done timed out
>[ 3585.244194] [drm:intel_edp_backlight_off [i915]] 
>[ 3585.452259] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0
>[ 3585.452398] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 3585.460913] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[ 3585.461072] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b
>[ 3585.461346] [drm:intel_edp_panel_off.part.31 [i915]] Turn eDP port A panel power off
>[ 3585.461448] [drm:intel_edp_panel_off.part.31 [i915]] Wait for panel power off time
>[ 3585.461574] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000003 control 00000060
>[ 3585.513897] [drm:wait_panel_status [i915]] Wait complete
>[ 3585.513961] [drm:intel_power_well_disable [i915]] disabling DDI A/E IO power well
>[ 3585.514046] [drm:intel_disable_shared_dpll [i915]] disable DPLL 0 (active 1, on? 1) for crtc 37
>[ 3585.514120] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 0
>[ 3585.514213] [drm:intel_atomic_commit_tail [i915]] [ENCODER:48:DDI A]
>[ 3585.514284] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI B]
>[ 3585.514351] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[ 3585.514415] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[ 3585.514477] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DDI C]
>[ 3585.514539] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST A]
>[ 3585.514599] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST B]
>[ 3585.514660] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI D]
>[ 3585.514719] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[ 3585.514778] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[ 3585.514844] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:49:eDP-1]
>[ 3585.514912] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[ 3585.514977] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[ 3585.515041] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[ 3585.515103] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[ 3585.515181] [drm:intel_atomic_commit_tail [i915]] [CRTC:37:pipe A]
>[ 3585.515305] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[ 3585.515773] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 00 00 04 00 0f 00 04
>[ 3585.517167] [drm:intel_power_well_disable [i915]] disabling power well 2
>[ 3585.517180] [drm:intel_power_well_disable [i915]] disabling DC off
>[ 3585.517204] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[ 3585.517213] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[ 3585.517223] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 3585.517224] Setting dangerous option enable_psr - tainting kernel
>[ 3585.517238] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[ 3585.517247] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 3585.517256] [drm:intel_power_well_enable [i915]] enabling DC off
>[ 3585.518104] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[ 3585.518180] [drm:intel_power_well_enable [i915]] enabling power well 2
>[ 3585.518188] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[ 3585.518577] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 00 00 04 00 0f 00 04
>[ 3585.519859] [drm:intel_power_well_disable [i915]] disabling power well 2
>[ 3585.519866] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[ 3585.519882] [drm:intel_power_well_disable [i915]] disabling DC off
>[ 3585.519898] [drm:intel_atomic_check [i915]] [CONNECTOR:49:eDP-1] checking for sink bpp constrains
>[ 3585.519913] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 3585.519924] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[ 3585.519930] [drm:drm_mode_debug_printmodeline [drm]] Modeline 52:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[ 3585.519945] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 138780KHz
>[ 3585.519955] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[ 3585.519966] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 3585.519979] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24
>[ 3585.519993] [drm:intel_dp_compute_config [i915]] DP link bw required 416340 available 540000
>[ 3585.520007] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 3585.520038] [drm:intel_dump_pipe_config [i915]] [CRTC:37:pipe A][modeset]
>[ 3585.520051] [drm:intel_dump_pipe_config [i915]] output_types: EDP (0x100)
>[ 3585.520063] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0
>[ 3585.520076] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 6467616, gmch_n: 8388608, link_m: 269484, link_n: 524288, tu: 64
>[ 3585.520087] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[ 3585.520099] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 3585.520105] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[ 3585.520116] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 3585.520122] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[ 3585.520134] [drm:intel_dump_pipe_config [i915]] crtc timings: 138780 1920 1966 1996 2080 1080 1082 1086 1112, type: 0x48 flags: 0xa
>[ 3585.520145] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 138780
>[ 3585.520157] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[ 3585.520167] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 3585.520179] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 3585.520190] [drm:intel_dump_pipe_config [i915]] dpll_hw_state: ctrl1: 0x3, cfgcr1: 0x0, cfgcr2: 0x0
>[ 3585.520200] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 3585.520211] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 1A] disabled, scaler_id = -1
>[ 3585.520222] [drm:intel_dump_pipe_config [i915]] [PLANE:31:plane 2A] disabled, scaler_id = -1
>[ 3585.520233] [drm:intel_dump_pipe_config [i915]] [PLANE:34:cursor A] disabled, scaler_id = -1
>[ 3585.520247] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 3585.520259] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[ 3585.520274] [drm:intel_find_shared_dpll [i915]] [CRTC:37:pipe A] allocated DPLL 0
>[ 3585.520287] [drm:intel_reference_shared_dpll [i915]] using DPLL 0 for pipe A
>[ 3585.521266] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010
>[ 3585.521281] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[ 3585.521295] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0
>[ 3585.521313] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[ 3585.521365] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 3585.521377] [drm:intel_power_well_enable [i915]] enabling DC off
>[ 3585.521704] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[ 3585.521724] [drm:intel_atomic_commit_tail [i915]] [ENCODER:48:DDI A]
>[ 3585.521740] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI B]
>[ 3585.521754] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[ 3585.521768] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[ 3585.521781] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DDI C]
>[ 3585.521793] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST A]
>[ 3585.521806] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST B]
>[ 3585.521818] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI D]
>[ 3585.521830] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[ 3585.521842] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[ 3585.521856] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[ 3585.521870] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[ 3585.521884] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[ 3585.521897] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[ 3585.521912] [drm:intel_enable_shared_dpll [i915]] enable DPLL 0 (active 1, on? 0) for crtc 37
>[ 3585.521926] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 0
>[ 3585.521946] [drm:edp_panel_on [i915]] Turn eDP port A panel power on
>[ 3585.521972] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle
>[ 3586.140031] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 00000000 control 00000060
>[ 3586.140112] [drm:wait_panel_status [i915]] Wait complete
>[ 3586.140226] [drm:edp_panel_on [i915]] Wait for panel power on
>[ 3586.140349] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 00000063
>[ 3586.172161] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010
>[ 3586.172233] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[ 3586.172299] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1
>[ 3586.172394] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[ 3586.342700] [drm:wait_panel_status [i915]] Wait complete
>[ 3586.342756] [drm:intel_power_well_enable [i915]] enabling DDI A/E IO power well
>[ 3586.342848] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[ 3586.342992] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b
>[ 3586.344201] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 3586.344265] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 3586.344324] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 3586.344381] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 3586.345085] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 3586.345139] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 3586.346141] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 3586.346196] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:49:eDP-1] Link Training Passed at Link Rate = 270000, Lane count = 2
>[ 3586.346830] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 3586.346897] [drm:intel_edp_backlight_on [i915]] 
>[ 3586.346954] [drm:intel_panel_enable_backlight [i915]] pipe A
>[ 3586.347037] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 120000
>[ 3586.352155] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS
>[ 3589.596184] [drm:edp_panel_vdd_off_sync [i915]] Turning eDP port A VDD off
>[ 3589.596328] [drm:edp_panel_vdd_off_sync [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x00000067
>[ 3590.349961] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 3590.350042] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 3590.350166] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[ 3590.350233] [drm:intel_power_well_enable [i915]] enabling power well 2
>[ 3590.610224] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 3590.610305] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 3596.171492] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 3596.171574] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 3596.432255] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 3596.432337] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 3596.508088] [drm:drm_atomic_helper_wait_for_flip_done [drm_kms_helper]] *ERROR* [CRTC:37:pipe A] flip_done timed out
>[ 3596.508211] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:49:eDP-1]
>[ 3596.508294] [drm:intel_atomic_commit_tail [i915]] [CRTC:37:pipe A]
>[ 3596.508392] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[ 3596.508978] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 00 00 04 00 0f 00 04
>[ 3596.510384] [drm:intel_power_well_disable [i915]] disabling power well 2
>[ 3596.510441] [drm:intel_power_well_disable [i915]] disabling DC off
>[ 3596.510491] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[ 3596.510540] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[ 3596.510612] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[ 3596.510661] [drm:intel_power_well_enable [i915]] enabling DC off
>[ 3596.510708] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[ 3596.510759] [drm:intel_power_well_enable [i915]] enabling power well 2
>[ 3596.511254] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 00 00 04 00 0f 00 04
>[ 3596.512668] [drm:intel_power_well_disable [i915]] disabling power well 2
>[ 3596.512720] [drm:intel_power_well_disable [i915]] disabling DC off
>[ 3596.512768] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[ 3596.512815] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[ 3596.546956] [drm:intel_power_well_enable [i915]] enabling DC off
>[ 3596.547009] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[ 3596.547099] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[ 3596.547245] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006f
>[ 3596.747133] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped
>[ 3596.997110] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped
>[ 3597.247135] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped
>[ 3597.497244] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped
>[ 3597.747105] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped
>[ 3600.860184] [drm:edp_panel_vdd_off_sync [i915]] Turning eDP port A VDD off
>[ 3600.860330] [drm:edp_panel_vdd_off_sync [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x00000067
>[ 3600.860388] [drm:intel_power_well_disable [i915]] disabling DC off
>[ 3600.860444] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[ 3600.860498] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[ 3602.002112] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 3602.002193] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 3602.002317] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[ 3602.002383] [drm:intel_power_well_enable [i915]] enabling DC off
>[ 3602.002446] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[ 3602.002507] [drm:intel_power_well_enable [i915]] enabling power well 2
>[ 3602.263261] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 3602.263347] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 3607.772203] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [CRTC:37:pipe A] flip_done timed out
>[ 3607.830976] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 3607.831057] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 3608.091907] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 3608.091983] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 3613.666488] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 3613.666569] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 3613.927529] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 3613.927610] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 3618.012201] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [PLANE:28:plane 1A] flip_done timed out
>[ 3619.495483] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 3619.495555] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 3619.757924] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 3619.758005] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 3625.333862] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 3625.333943] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 3625.594257] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 3625.594338] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 3628.252087] [drm:drm_atomic_helper_wait_for_flip_done [drm_kms_helper]] *ERROR* [CRTC:37:pipe A] flip_done timed out
>[ 3628.252368] [IGT] kms_frontbuffer_tracking: exiting, ret=0
>[ 3628.252438] Setting dangerous option enable_psr - tainting kernel
>[ 3628.252453] Setting dangerous option enable_fbc - tainting kernel
>[ 3628.252699] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 00 00 04 00 0f 00 04
>[ 3628.254252] [drm:intel_power_well_disable [i915]] disabling power well 2
>[ 3628.254308] [drm:intel_power_well_disable [i915]] disabling DC off
>[ 3628.254360] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[ 3628.254409] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[ 3628.254486] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[ 3628.254534] [drm:intel_power_well_enable [i915]] enabling DC off
>[ 3628.254582] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[ 3628.254633] [drm:intel_power_well_enable [i915]] enabling power well 2
>[ 3628.255118] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 00 00 04 00 0f 00 04
>[ 3628.256559] [drm:intel_power_well_disable [i915]] disabling power well 2
>[ 3628.256611] [drm:intel_power_well_disable [i915]] disabling DC off
>[ 3628.256660] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[ 3628.256706] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[ 3628.299988] [drm:intel_atomic_check [i915]] [CONNECTOR:57:DP-1] checking for sink bpp constrains
>[ 3628.300005] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 3628.300022] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 148500KHz
>[ 3628.300039] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 3628.300053] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 648000
>[ 3628.300070] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 3628.300085] [drm:intel_dump_pipe_config [i915]] [CRTC:47:pipe B][modeset]
>[ 3628.300100] [drm:intel_dump_pipe_config [i915]] output_types: DP (0x80)
>[ 3628.300114] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 3628.300128] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5767168, gmch_n: 8388608, link_m: 240298, link_n: 262144, tu: 64
>[ 3628.300142] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[ 3628.300155] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 3628.300164] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[ 3628.300178] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 3628.300184] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[ 3628.300199] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[ 3628.300212] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1080, pixel rate 148500
>[ 3628.300225] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[ 3628.300239] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 3628.300251] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 3628.300265] [drm:intel_dump_pipe_config [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[ 3628.300277] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 3628.300290] [drm:intel_dump_pipe_config [i915]] [PLANE:38:plane 1B] disabled, scaler_id = -1
>[ 3628.300303] [drm:intel_dump_pipe_config [i915]] [PLANE:41:plane 2B] disabled, scaler_id = -1
>[ 3628.300316] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor B] disabled, scaler_id = -1
>[ 3628.300332] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 3628.300346] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[ 3628.300364] [drm:intel_find_shared_dpll [i915]] [CRTC:47:pipe B] allocated DPLL 1
>[ 3628.300379] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[ 3631.169908] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 3631.169979] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 3631.170075] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[ 3631.170133] [drm:intel_power_well_enable [i915]] enabling DC off
>[ 3631.170189] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[ 3631.170241] [drm:intel_power_well_enable [i915]] enabling power well 2
>[ 3631.431538] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 3631.431610] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 3637.001179] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 3637.001260] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 3637.262119] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 3637.262200] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 3638.492198] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [CRTC:37:pipe A] flip_done timed out
>[ 3642.832222] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 3642.832303] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 3643.092220] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 3643.092301] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 3648.659559] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 3648.659640] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 3648.732061] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [CONNECTOR:49:eDP-1] flip_done timed out
>[ 3648.920084] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 3648.920165] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 3654.500050] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 3654.500133] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 3654.759434] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 3654.759515] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 3658.972188] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [PLANE:28:plane 1A] flip_done timed out
>[ 3658.972281] [drm:intel_disable_sagv [i915]] Disabling the SAGV
>[ 3658.972375] [drm:intel_atomic_commit_tail [i915]] [ENCODER:48:DDI A]
>[ 3658.972448] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI B]
>[ 3658.972518] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[ 3658.972584] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[ 3658.972647] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DDI C]
>[ 3658.972708] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST A]
>[ 3658.972768] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST B]
>[ 3658.972828] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI D]
>[ 3658.972887] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[ 3658.972946] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[ 3658.973012] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[ 3658.973081] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[ 3658.973144] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[ 3658.973207] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[ 3658.973283] [drm:intel_fbc_enable [i915]] reserved 16588800 bytes of contiguous stolen space for FBC, threshold: 1
>[ 3658.973351] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 3658.979329] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 2, on? 0) for crtc 47
>[ 3658.979407] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[ 3658.979568] [drm:intel_power_well_enable [i915]] enabling DDI B IO power well
>[ 3658.980188] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 3658.981444] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 3658.982702] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 3658.983954] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 3658.985215] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 3658.986095] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[ 3658.987096] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 3658.987164] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 3658.987227] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 3658.987289] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 3659.005964] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 3659.005978] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[ 3659.023714] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 3659.024051] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:57:DP-1] Link Training Passed at Link Rate = 162000, Lane count = 4
>[ 3659.024437] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 3659.024488] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS
>[ 3660.347454] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 3660.347535] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 3660.610604] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 3660.610686] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 3669.212206] [drm:drm_atomic_helper_wait_for_flip_done [drm_kms_helper]] *ERROR* [CRTC:37:pipe A] flip_done timed out
>[ 3669.212338] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:57:DP-1]
>[ 3669.212423] [drm:intel_atomic_commit_tail [i915]] [CRTC:47:pipe B]
>[ 3669.212520] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[ 3669.213122] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 00 00 04 00 0f 00 04
>[ 3669.214566] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[ 3669.215047] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 00 00 04 00 0f 00 04
>[ 3669.269248] [IGT] kms_frontbuffer_tracking: executing
>[ 3669.320414] [drm:drm_mode_addfb2 [drm]] [FB:89]
>[ 3669.320506] [drm:drm_mode_addfb2 [drm]] [FB:91]
>[ 3669.320599] [drm:drm_mode_addfb2 [drm]] [FB:92]
>[ 3669.322517] [drm:drm_mode_addfb2 [drm]] [FB:93]
>[ 3669.338176] [drm:drm_mode_addfb2 [drm]] [FB:94]
>[ 3669.341909] [drm:drm_mode_addfb2 [drm]] [FB:96]
>[ 3669.341988] [drm:drm_mode_addfb2 [drm]] [FB:98]
>[ 3669.342081] [drm:drm_mode_addfb2 [drm]] [FB:102]
>[ 3669.342479] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[ 3669.342508] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[ 3679.452195] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [CRTC:37:pipe A] flip_done timed out
>[ 3689.692185] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [CONNECTOR:49:eDP-1] flip_done timed out
>[ 3699.932175] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [PLANE:28:plane 1A] flip_done timed out
>[ 3710.171926] [drm:drm_atomic_helper_wait_for_flip_done [drm_kms_helper]] *ERROR* [CRTC:37:pipe A] flip_done timed out
>[ 3710.172113] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[ 3710.172269] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006f
>[ 3710.361834] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped
>[ 3710.362077] [IGT] kms_frontbuffer_tracking: starting subtest psr-1p-offscren-pri-shrfb-draw-mmap-gtt
>[ 3710.362155] Setting dangerous option enable_fbc - tainting kernel
>[ 3710.362176] Setting dangerous option enable_psr - tainting kernel
>[ 3713.500170] [drm:edp_panel_vdd_off_sync [i915]] Turning eDP port A VDD off
>[ 3713.500316] [drm:edp_panel_vdd_off_sync [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x00000067
>[ 3720.411925] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [CRTC:37:pipe A] flip_done timed out
>[ 3730.652194] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [PLANE:28:plane 1A] flip_done timed out
>[ 3740.892088] [drm:drm_atomic_helper_wait_for_flip_done [drm_kms_helper]] *ERROR* [CRTC:37:pipe A] flip_done timed out
>[ 3740.896480] [drm:drm_mode_addfb2 [drm]] [FB:72]
>[ 3740.896580] [drm:drm_mode_addfb2 [drm]] [FB:89]
>[ 3740.896686] [drm:drm_mode_addfb2 [drm]] [FB:91]
>[ 3740.897812] [drm:drm_mode_addfb2 [drm]] [FB:92]
>[ 3740.901572] [drm:drm_mode_addfb2 [drm]] [FB:93]
>[ 3740.902416] [drm:drm_mode_addfb2 [drm]] [FB:94]
>[ 3740.902436] [drm:drm_mode_addfb2 [drm]] [FB:96]
>[ 3740.902456] [drm:drm_mode_addfb2 [drm]] [FB:98]
>[ 3740.902571] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[ 3740.902604] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 3740.902619] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[ 3751.132167] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [CRTC:37:pipe A] flip_done timed out
>[ 3761.372042] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [CONNECTOR:49:eDP-1] flip_done timed out
>[ 3771.612129] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [PLANE:28:plane 1A] flip_done timed out
>[ 3771.612256] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[ 3771.612412] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006f
>[ 3771.612689] [drm:intel_edp_backlight_off [i915]] 
>[ 3771.820249] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0
>[ 3771.820388] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 3771.829053] [drm:intel_edp_panel_off.part.31 [i915]] Turn eDP port A panel power off
>[ 3771.829166] [drm:intel_edp_panel_off.part.31 [i915]] Wait for panel power off time
>[ 3771.829298] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000003 control 00000060
>[ 3771.879370] [drm:wait_panel_status [i915]] Wait complete
>[ 3771.879434] [drm:intel_power_well_disable [i915]] disabling DDI A/E IO power well
>[ 3771.879515] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 3771.879594] [drm:intel_disable_shared_dpll [i915]] disable DPLL 0 (active 1, on? 1) for crtc 37
>[ 3771.879665] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 0
>[ 3771.879757] [drm:intel_atomic_commit_tail [i915]] [ENCODER:48:DDI A]
>[ 3771.879827] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI B]
>[ 3771.879929] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[ 3771.880000] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[ 3771.880073] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DDI C]
>[ 3771.880140] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST A]
>[ 3771.880206] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST B]
>[ 3771.880275] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI D]
>[ 3771.880337] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[ 3771.880401] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[ 3771.880468] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:49:eDP-1]
>[ 3771.880537] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[ 3771.880601] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[ 3771.880666] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[ 3771.880727] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[ 3771.888997] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010
>[ 3771.889078] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[ 3771.889153] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0
>[ 3771.889272] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[ 3771.891748] [drm:intel_atomic_commit_tail [i915]] [CRTC:37:pipe A]
>[ 3771.891819] [drm:intel_enable_sagv [i915]] Enabling the SAGV
>[ 3771.891952] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[ 3771.892059] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 3771.892135] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[ 3771.892240] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 3771.909003] [drm:intel_power_well_disable [i915]] disabling DDI B IO power well
>[ 3771.909085] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 2, on? 1) for crtc 47
>[ 3771.909159] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[ 3771.909248] [drm:intel_atomic_commit_tail [i915]] [ENCODER:48:DDI A]
>[ 3771.909314] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI B]
>[ 3771.909377] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[ 3771.909438] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[ 3771.909497] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DDI C]
>[ 3771.909555] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST A]
>[ 3771.909613] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST B]
>[ 3771.909670] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI D]
>[ 3771.909725] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[ 3771.909780] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[ 3771.909842] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:57:DP-1]
>[ 3771.909905] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[ 3771.909967] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[ 3771.910027] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[ 3771.910086] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[ 3771.910144] [drm:intel_power_well_disable [i915]] disabling power well 2
>[ 3771.910216] [drm:intel_atomic_commit_tail [i915]] [CRTC:47:pipe B]
>[ 3771.910270] [drm:intel_power_well_disable [i915]] disabling DC off
>[ 3771.910321] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[ 3771.910370] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[ 3771.910808] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 3771.913547] [drm:drm_mode_addfb2 [drm]] [FB:73]
>[ 3771.915215] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[ 3771.915221] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[ 3771.915242] [drm:intel_atomic_check [i915]] [CONNECTOR:49:eDP-1] checking for sink bpp constrains
>[ 3771.915254] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 3771.915261] [drm:drm_mode_debug_printmodeline [drm]] Modeline 52:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[ 3771.915274] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 138780KHz
>[ 3771.915290] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24
>[ 3771.915301] [drm:intel_dp_compute_config [i915]] DP link bw required 416340 available 540000
>[ 3771.915313] [drm:intel_dp_compute_config [i915]] PSR disable by flag
>[ 3771.915325] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 3771.915338] [drm:intel_dump_pipe_config [i915]] [CRTC:37:pipe A][modeset]
>[ 3771.915350] [drm:intel_dump_pipe_config [i915]] output_types: EDP (0x100)
>[ 3771.915361] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0
>[ 3771.915372] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 6467616, gmch_n: 8388608, link_m: 269484, link_n: 524288, tu: 64
>[ 3771.915383] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[ 3771.915394] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 3771.915399] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[ 3771.915410] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 3771.915415] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[ 3771.915426] [drm:intel_dump_pipe_config [i915]] crtc timings: 138780 1920 1966 1996 2080 1080 1082 1086 1112, type: 0x48 flags: 0xa
>[ 3771.915437] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 138780
>[ 3771.915448] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[ 3771.915458] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 3771.915469] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 3771.915479] [drm:intel_dump_pipe_config [i915]] dpll_hw_state: ctrl1: 0x3, cfgcr1: 0x0, cfgcr2: 0x0
>[ 3771.915489] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 3771.915499] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 1A] disabled, scaler_id = -1
>[ 3771.915509] [drm:intel_dump_pipe_config [i915]] [PLANE:31:plane 2A] disabled, scaler_id = -1
>[ 3771.915520] [drm:intel_dump_pipe_config [i915]] [PLANE:34:cursor A] disabled, scaler_id = -1
>[ 3771.915532] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 3771.915543] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[ 3771.915557] [drm:intel_find_shared_dpll [i915]] [CRTC:37:pipe A] allocated DPLL 0
>[ 3771.915569] [drm:intel_reference_shared_dpll [i915]] using DPLL 0 for pipe A
>[ 3771.916161] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 3771.916170] [drm:intel_power_well_enable [i915]] enabling DC off
>[ 3771.916427] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[ 3771.916443] [drm:intel_atomic_commit_tail [i915]] [ENCODER:48:DDI A]
>[ 3771.916455] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI B]
>[ 3771.916466] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[ 3771.916477] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[ 3771.916488] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DDI C]
>[ 3771.916499] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST A]
>[ 3771.916509] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST B]
>[ 3771.916520] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI D]
>[ 3771.916530] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[ 3771.916541] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[ 3771.916552] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[ 3771.916563] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[ 3771.916575] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[ 3771.916586] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[ 3771.916599] [drm:intel_enable_shared_dpll [i915]] enable DPLL 0 (active 1, on? 0) for crtc 37
>[ 3771.916610] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 0
>[ 3771.916629] [drm:edp_panel_on [i915]] Turn eDP port A panel power on
>[ 3771.916653] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle
>[ 3772.508326] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 00000000 control 00000060
>[ 3772.508434] [drm:wait_panel_status [i915]] Wait complete
>[ 3772.508573] [drm:edp_panel_on [i915]] Wait for panel power on
>[ 3772.508703] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 00000063
>[ 3772.542376] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010
>[ 3772.542457] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[ 3772.542531] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1
>[ 3772.542675] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[ 3772.711415] [drm:wait_panel_status [i915]] Wait complete
>[ 3772.711480] [drm:intel_power_well_enable [i915]] enabling DDI A/E IO power well
>[ 3772.711584] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[ 3772.711733] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b
>[ 3772.712981] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 3772.713054] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 3772.713119] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 3772.713182] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 3772.713898] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 3772.713957] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 3772.714968] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 3772.715028] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:49:eDP-1] Link Training Passed at Link Rate = 270000, Lane count = 2
>[ 3772.715680] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 3772.715761] [drm:intel_edp_backlight_on [i915]] 
>[ 3772.715823] [drm:intel_panel_enable_backlight [i915]] pipe A
>[ 3772.715945] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 120000
>[ 3772.716114] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS
>[ 3775.964282] [drm:edp_panel_vdd_off_sync [i915]] Turning eDP port A VDD off
>[ 3775.964430] [drm:edp_panel_vdd_off_sync [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x00000067
>[ 3782.876096] [drm:drm_atomic_helper_wait_for_flip_done [drm_kms_helper]] *ERROR* [CRTC:37:pipe A] flip_done timed out
>[ 3782.876216] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:49:eDP-1]
>[ 3782.876299] [drm:intel_atomic_commit_tail [i915]] [CRTC:37:pipe A]
>[ 3782.876395] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[ 3782.876459] [drm:intel_power_well_disable [i915]] disabling DC off
>[ 3782.876515] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[ 3782.876568] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[ 3782.916024] [drm:intel_power_well_enable [i915]] enabling DC off
>[ 3782.916084] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[ 3782.916182] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[ 3782.916334] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006f
>[ 3783.115993] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped
>[ 3783.116077] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[ 3783.116172] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 3783.116233] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[ 3786.204168] [drm:edp_panel_vdd_off_sync [i915]] Turning eDP port A VDD off
>[ 3786.204313] [drm:edp_panel_vdd_off_sync [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x00000067
>[ 3786.204370] [drm:intel_power_well_disable [i915]] disabling DC off
>[ 3786.204426] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[ 3786.204479] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[ 3792.636453] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 3792.636534] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 3792.636659] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[ 3792.636725] [drm:intel_power_well_enable [i915]] enabling DC off
>[ 3792.636788] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[ 3792.636847] [drm:intel_power_well_enable [i915]] enabling power well 2
>[ 3792.919336] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 3792.919418] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 3793.372192] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [CRTC:37:pipe A] flip_done timed out
>[ 3797.680173] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 3797.680255] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 3797.949532] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 3797.949614] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 3803.523023] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 3803.523105] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 3803.612094] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [CONNECTOR:49:eDP-1] flip_done timed out
>[ 3803.792006] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 3803.792087] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 3809.365513] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 3809.365595] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 3809.634707] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 3809.634788] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 3813.852077] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [PLANE:28:plane 1A] flip_done timed out
>[ 3813.852182] [drm:intel_edp_backlight_off [i915]] 
>[ 3814.060156] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0
>[ 3814.060291] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 3814.066034] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[ 3814.066191] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b
>[ 3814.066463] [drm:intel_edp_panel_off.part.31 [i915]] Turn eDP port A panel power off
>[ 3814.066565] [drm:intel_edp_panel_off.part.31 [i915]] Wait for panel power off time
>[ 3814.066689] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000003 control 00000060
>[ 3814.116882] [drm:wait_panel_status [i915]] Wait complete
>[ 3814.116938] [drm:intel_power_well_disable [i915]] disabling DDI A/E IO power well
>[ 3814.117014] [drm:intel_disable_shared_dpll [i915]] disable DPLL 0 (active 1, on? 1) for crtc 37
>[ 3814.117081] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 0
>[ 3814.117166] [drm:intel_atomic_commit_tail [i915]] [ENCODER:48:DDI A]
>[ 3814.117229] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI B]
>[ 3814.117288] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[ 3814.117346] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[ 3814.117402] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DDI C]
>[ 3814.117457] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST A]
>[ 3814.117511] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST B]
>[ 3814.117565] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI D]
>[ 3814.117619] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[ 3814.117672] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[ 3814.117731] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:49:eDP-1]
>[ 3814.117790] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[ 3814.117848] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[ 3814.117903] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[ 3814.117957] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[ 3814.118026] [drm:intel_atomic_commit_tail [i915]] [CRTC:37:pipe A]
>[ 3814.118137] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[ 3814.118535] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 00 00 04 00 0f 00 04
>[ 3814.126531] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010
>[ 3814.126612] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[ 3814.126687] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0
>[ 3814.146873] [drm:intel_power_well_disable [i915]] disabling power well 2
>[ 3814.146927] [drm:intel_power_well_disable [i915]] disabling DC off
>[ 3814.146974] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[ 3814.147018] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[ 3814.147454] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 3814.147520] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[ 3814.147581] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[ 3814.147626] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 3814.147668] [drm:intel_power_well_enable [i915]] enabling DC off
>[ 3814.147982] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[ 3814.148037] [drm:intel_power_well_enable [i915]] enabling power well 2
>[ 3814.148522] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 00 00 04 00 0f 00 04
>[ 3814.149905] [drm:intel_power_well_disable [i915]] disabling power well 2
>[ 3814.149952] [drm:intel_power_well_disable [i915]] disabling DC off
>[ 3814.149997] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[ 3814.150039] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[ 3814.150474] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 3814.151602] [drm:drm_mode_addfb2 [drm]] [FB:73]
>[ 3814.153007] [drm:drm_mode_addfb2 [drm]] [FB:102]
>[ 3814.153834] [drm:drm_mode_addfb2 [drm]] [FB:103]
>[ 3814.154664] [drm:drm_mode_addfb2 [drm]] [FB:104]
>[ 3814.224745] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[ 3814.224752] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[ 3814.224778] [drm:intel_atomic_check [i915]] [CONNECTOR:49:eDP-1] checking for sink bpp constrains
>[ 3814.224791] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 3814.224798] [drm:drm_mode_debug_printmodeline [drm]] Modeline 52:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[ 3814.224812] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 138780KHz
>[ 3814.224828] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24
>[ 3814.224840] [drm:intel_dp_compute_config [i915]] DP link bw required 416340 available 540000
>[ 3814.224851] [drm:intel_dp_compute_config [i915]] PSR disable by flag
>[ 3814.224864] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 3814.224876] [drm:intel_dump_pipe_config [i915]] [CRTC:37:pipe A][modeset]
>[ 3814.224889] [drm:intel_dump_pipe_config [i915]] output_types: EDP (0x100)
>[ 3814.224900] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0
>[ 3814.224912] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 6467616, gmch_n: 8388608, link_m: 269484, link_n: 524288, tu: 64
>[ 3814.224923] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[ 3814.224933] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 3814.224939] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[ 3814.224949] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 3814.224955] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[ 3814.224966] [drm:intel_dump_pipe_config [i915]] crtc timings: 138780 1920 1966 1996 2080 1080 1082 1086 1112, type: 0x48 flags: 0xa
>[ 3814.224977] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 138780
>[ 3814.224987] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[ 3814.224998] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 3814.225008] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 3814.225019] [drm:intel_dump_pipe_config [i915]] dpll_hw_state: ctrl1: 0x3, cfgcr1: 0x0, cfgcr2: 0x0
>[ 3814.225029] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 3814.225039] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 1A] disabled, scaler_id = -1
>[ 3814.225049] [drm:intel_dump_pipe_config [i915]] [PLANE:31:plane 2A] disabled, scaler_id = -1
>[ 3814.225060] [drm:intel_dump_pipe_config [i915]] [PLANE:34:cursor A] disabled, scaler_id = -1
>[ 3814.225073] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 3814.225084] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[ 3814.225099] [drm:intel_find_shared_dpll [i915]] [CRTC:37:pipe A] allocated DPLL 0
>[ 3814.225110] [drm:intel_reference_shared_dpll [i915]] using DPLL 0 for pipe A
>[ 3814.226071] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 3814.226080] [drm:intel_power_well_enable [i915]] enabling DC off
>[ 3814.226374] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[ 3814.226392] [drm:intel_atomic_commit_tail [i915]] [ENCODER:48:DDI A]
>[ 3814.226405] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI B]
>[ 3814.226418] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[ 3814.226430] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[ 3814.226443] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DDI C]
>[ 3814.226455] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST A]
>[ 3814.226466] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST B]
>[ 3814.226477] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI D]
>[ 3814.226489] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[ 3814.226501] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[ 3814.226513] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[ 3814.226526] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[ 3814.226554] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[ 3814.226566] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[ 3814.226579] [drm:intel_enable_shared_dpll [i915]] enable DPLL 0 (active 1, on? 0) for crtc 37
>[ 3814.226590] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 0
>[ 3814.226609] [drm:edp_panel_on [i915]] Turn eDP port A panel power on
>[ 3814.226633] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle
>[ 3814.748045] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 00000000 control 00000060
>[ 3814.748130] [drm:wait_panel_status [i915]] Wait complete
>[ 3814.748260] [drm:edp_panel_on [i915]] Wait for panel power on
>[ 3814.748385] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 00000063
>[ 3814.780146] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010
>[ 3814.780208] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[ 3814.780266] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1
>[ 3814.780346] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[ 3814.949789] [drm:wait_panel_status [i915]] Wait complete
>[ 3814.949848] [drm:intel_power_well_enable [i915]] enabling DDI A/E IO power well
>[ 3814.949943] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[ 3814.950085] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b
>[ 3814.951303] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 3814.951369] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 3814.951426] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 3814.951483] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 3814.952214] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 3814.952270] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 3814.953273] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 3814.953329] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:49:eDP-1] Link Training Passed at Link Rate = 270000, Lane count = 2
>[ 3814.953964] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 3814.954030] [drm:intel_edp_backlight_on [i915]] 
>[ 3814.954087] [drm:intel_panel_enable_backlight [i915]] pipe A
>[ 3814.954170] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 120000
>[ 3814.960030] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS
>[ 3815.179548] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 3815.179631] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 3815.179754] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[ 3815.179818] [drm:intel_power_well_enable [i915]] enabling power well 2
>[ 3815.443123] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 3815.443204] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 3818.204295] [drm:edp_panel_vdd_off_sync [i915]] Turning eDP port A VDD off
>[ 3818.204442] [drm:edp_panel_vdd_off_sync [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x00000067
>[ 3821.018720] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 3821.018801] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 3821.280138] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 3821.280219] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 3825.116094] [drm:drm_atomic_helper_wait_for_flip_done [drm_kms_helper]] *ERROR* [CRTC:37:pipe A] flip_done timed out
>[ 3825.116218] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:49:eDP-1]
>[ 3825.116300] [drm:intel_atomic_commit_tail [i915]] [CRTC:37:pipe A]
>[ 3825.116396] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[ 3825.116981] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 00 00 04 00 0f 00 04
>[ 3825.118385] [drm:intel_power_well_disable [i915]] disabling power well 2
>[ 3825.118441] [drm:intel_power_well_disable [i915]] disabling DC off
>[ 3825.118492] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[ 3825.118540] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[ 3825.118613] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[ 3825.118661] [drm:intel_power_well_enable [i915]] enabling DC off
>[ 3825.118723] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[ 3825.118769] [drm:intel_power_well_enable [i915]] enabling power well 2
>[ 3825.119241] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 00 00 04 00 0f 00 04
>[ 3825.120535] [drm:intel_power_well_disable [i915]] disabling power well 2
>[ 3825.120560] [drm:intel_power_well_disable [i915]] disabling DC off
>[ 3825.120570] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[ 3825.120579] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[ 3825.153940] [drm:intel_power_well_enable [i915]] enabling DC off
>[ 3825.153970] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[ 3825.154005] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[ 3825.154102] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006f
>[ 3825.354267] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped
>[ 3825.354310] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[ 3825.354339] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[ 3826.855686] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 3826.855768] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 3826.855889] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[ 3826.855974] [drm:intel_power_well_enable [i915]] enabling power well 2
>[ 3827.116519] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 3827.116601] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 3828.444272] [drm:edp_panel_vdd_off_sync [i915]] Turning eDP port A VDD off
>[ 3828.444416] [drm:edp_panel_vdd_off_sync [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x00000067
>[ 3832.686699] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 3832.686780] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 3832.948543] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 3832.948624] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 3835.356056] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [CRTC:37:pipe A] flip_done timed out
>[ 3838.517403] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 3838.517484] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 3838.779479] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 3838.779561] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 3844.350443] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 3844.350524] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 3844.611446] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 3844.611528] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 3845.596191] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [CONNECTOR:49:eDP-1] flip_done timed out
>[ 3850.181993] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 3850.182074] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 3850.443779] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 3850.443860] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 3855.836076] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [PLANE:28:plane 1A] flip_done timed out
>[ 3856.017950] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 3856.018032] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 3856.279363] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 3856.279444] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 3861.853223] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 3861.853304] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 3862.114496] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 3862.114576] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 3866.076089] [drm:drm_atomic_helper_wait_for_flip_done [drm_kms_helper]] *ERROR* [CRTC:37:pipe A] flip_done timed out
>[ 3866.076687] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 00 00 04 00 0f 00 04
>[ 3866.078088] [drm:intel_power_well_disable [i915]] disabling power well 2
>[ 3866.078146] [drm:intel_power_well_disable [i915]] disabling DC off
>[ 3866.078209] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[ 3866.078252] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[ 3866.078320] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[ 3866.078363] [drm:intel_power_well_enable [i915]] enabling DC off
>[ 3866.078405] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[ 3866.078451] [drm:intel_power_well_enable [i915]] enabling power well 2
>[ 3866.078930] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 00 00 04 00 0f 00 04
>[ 3866.080341] [drm:intel_power_well_disable [i915]] disabling power well 2
>[ 3866.080394] [drm:intel_power_well_disable [i915]] disabling DC off
>[ 3866.080443] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[ 3866.080492] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[ 3866.120155] [drm:intel_power_well_enable [i915]] enabling DC off
>[ 3866.120215] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[ 3866.120313] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[ 3866.120465] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006f
>[ 3866.320223] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped
>[ 3866.320267] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[ 3866.320299] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[ 3867.685439] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 3867.685520] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 3867.685641] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[ 3867.685707] [drm:intel_power_well_enable [i915]] enabling power well 2
>[ 3867.948908] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 3867.948990] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 3869.404023] [drm:edp_panel_vdd_off_sync [i915]] Turning eDP port A VDD off
>[ 3869.404169] [drm:edp_panel_vdd_off_sync [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x00000067
>[ 3873.518458] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 3873.518539] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 3873.779083] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 3873.779164] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 3876.572050] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [CRTC:37:pipe A] flip_done timed out
>[ 3879.347506] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 3879.347588] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 3879.608177] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 3879.608257] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 3885.178464] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 3885.178545] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 3885.439202] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 3885.439283] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 3886.812090] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [CONNECTOR:49:eDP-1] flip_done timed out
>[ 3891.009829] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 3891.009911] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 3891.272812] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 3891.272893] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 3896.844183] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 3896.844263] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 3897.052193] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [PLANE:28:plane 1A] flip_done timed out
>[ 3897.103757] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 3897.103837] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 3902.679131] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 3902.679212] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 3902.939601] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 3902.939684] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 3907.292185] [drm:drm_atomic_helper_wait_for_flip_done [drm_kms_helper]] *ERROR* [CRTC:37:pipe A] flip_done timed out
>[ 3907.292795] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 00 00 04 00 0f 00 04
>[ 3907.294204] [drm:intel_power_well_disable [i915]] disabling power well 2
>[ 3907.294262] [drm:intel_power_well_disable [i915]] disabling DC off
>[ 3907.294312] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[ 3907.294361] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[ 3907.294437] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[ 3907.294485] [drm:intel_power_well_enable [i915]] enabling DC off
>[ 3907.294533] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[ 3907.294584] [drm:intel_power_well_enable [i915]] enabling power well 2
>[ 3907.295068] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 00 00 04 00 0f 00 04
>[ 3907.296495] [drm:intel_power_well_disable [i915]] disabling power well 2
>[ 3907.296547] [drm:intel_power_well_disable [i915]] disabling DC off
>[ 3907.296596] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[ 3907.296643] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[ 3907.335905] [drm:intel_power_well_enable [i915]] enabling DC off
>[ 3907.335958] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[ 3907.336045] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[ 3907.336189] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006f
>[ 3907.536172] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped
>[ 3907.536220] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[ 3907.536252] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[ 3908.512653] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 3908.512735] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 3908.512855] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[ 3908.512921] [drm:intel_power_well_enable [i915]] enabling power well 2
>[ 3908.772011] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 3908.772093] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 3910.620019] [drm:edp_panel_vdd_off_sync [i915]] Turning eDP port A VDD off
>[ 3910.620163] [drm:edp_panel_vdd_off_sync [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x00000067
>[ 3914.341342] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 3914.341423] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 3914.601342] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 3914.601423] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 3917.788048] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [CRTC:37:pipe A] flip_done timed out
>[ 3920.177581] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 3920.177662] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 3920.438431] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 3920.438513] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 3926.004948] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 3926.005029] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 3926.268261] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 3926.268342] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 3928.028187] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [CONNECTOR:49:eDP-1] flip_done timed out
>[ 3931.837398] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 3931.837480] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 3932.100036] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 3932.100117] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 3937.677985] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 3937.678067] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 3937.939039] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 3937.939120] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 3938.268194] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [PLANE:28:plane 1A] flip_done timed out
>[ 3943.512727] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 3943.512807] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 3943.773698] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 3943.773779] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 3948.508184] [drm:drm_atomic_helper_wait_for_flip_done [drm_kms_helper]] *ERROR* [CRTC:37:pipe A] flip_done timed out
>[ 3948.508787] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 00 00 04 00 0f 00 04
>[ 3948.510191] [drm:intel_power_well_disable [i915]] disabling power well 2
>[ 3948.510248] [drm:intel_power_well_disable [i915]] disabling DC off
>[ 3948.510318] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[ 3948.510361] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[ 3948.510429] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[ 3948.510472] [drm:intel_power_well_enable [i915]] enabling DC off
>[ 3948.510515] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[ 3948.510561] [drm:intel_power_well_enable [i915]] enabling power well 2
>[ 3948.511034] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 00 00 04 00 0f 00 04
>[ 3948.512411] [drm:intel_power_well_disable [i915]] disabling power well 2
>[ 3948.512450] [drm:intel_power_well_disable [i915]] disabling DC off
>[ 3948.512459] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[ 3948.512468] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[ 3948.551962] [drm:intel_power_well_enable [i915]] enabling DC off
>[ 3948.551994] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[ 3948.552032] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[ 3948.552131] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006f
>[ 3948.752108] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped
>[ 3948.752226] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[ 3948.752315] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 3948.752375] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[ 3949.350070] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 3949.350151] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 3949.350276] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[ 3949.350342] [drm:intel_power_well_enable [i915]] enabling power well 2
>[ 3949.610223] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 3949.610305] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 3951.836017] [drm:edp_panel_vdd_off_sync [i915]] Turning eDP port A VDD off
>[ 3951.836161] [drm:edp_panel_vdd_off_sync [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x00000067
>[ 3955.185142] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 3955.185223] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 3955.443687] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 3955.443768] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 3959.004050] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [CRTC:37:pipe A] flip_done timed out
>[ 3961.007061] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 3961.007142] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 3961.268544] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 3961.268626] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 3966.834314] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 3966.834394] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 3967.097512] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 3967.097594] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 3969.244185] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [CONNECTOR:49:eDP-1] flip_done timed out
>[ 3972.673883] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 3972.673964] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 3972.932497] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 3972.932579] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 3978.509503] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 3978.509584] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 3978.768715] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 3978.768797] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 3979.484191] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [PLANE:28:plane 1A] flip_done timed out
>[ 3979.484297] [drm:intel_edp_backlight_off [i915]] 
>[ 3979.692244] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0
>[ 3979.692382] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 3979.703374] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[ 3979.703535] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b
>[ 3979.703808] [drm:intel_edp_panel_off.part.31 [i915]] Turn eDP port A panel power off
>[ 3979.703948] [drm:intel_edp_panel_off.part.31 [i915]] Wait for panel power off time
>[ 3979.704080] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000002 control 00000060
>[ 3979.754105] [drm:wait_panel_status [i915]] Wait complete
>[ 3979.754168] [drm:intel_power_well_disable [i915]] disabling DDI A/E IO power well
>[ 3979.754253] [drm:intel_disable_shared_dpll [i915]] disable DPLL 0 (active 1, on? 1) for crtc 37
>[ 3979.754327] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 0
>[ 3979.754418] [drm:intel_atomic_commit_tail [i915]] [ENCODER:48:DDI A]
>[ 3979.754489] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI B]
>[ 3979.754554] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[ 3979.754617] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[ 3979.754679] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DDI C]
>[ 3979.754739] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST A]
>[ 3979.754807] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST B]
>[ 3979.754873] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI D]
>[ 3979.754937] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[ 3979.755013] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[ 3979.755075] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:49:eDP-1]
>[ 3979.755138] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[ 3979.755198] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[ 3979.755256] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[ 3979.755313] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[ 3979.755386] [drm:intel_atomic_commit_tail [i915]] [CRTC:37:pipe A]
>[ 3979.755503] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[ 3979.755988] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 00 00 04 00 0f 00 04
>[ 3979.757426] [drm:intel_power_well_disable [i915]] disabling power well 2
>[ 3979.757479] [drm:intel_power_well_disable [i915]] disabling DC off
>[ 3979.757525] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[ 3979.757569] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[ 3979.757572] Setting dangerous option enable_psr - tainting kernel
>[ 3979.758496] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 3979.758578] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[ 3979.758607] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[ 3979.758651] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 3979.758694] [drm:intel_power_well_enable [i915]] enabling DC off
>[ 3979.758715] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[ 3979.758807] [drm:intel_atomic_check [i915]] [CONNECTOR:49:eDP-1] checking for sink bpp constrains
>[ 3979.758870] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 3979.758900] [drm:drm_mode_debug_printmodeline [drm]] Modeline 52:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[ 3979.758964] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 138780KHz
>[ 3979.759006] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[ 3979.759065] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24
>[ 3979.759123] [drm:intel_dp_compute_config [i915]] DP link bw required 416340 available 540000
>[ 3979.759184] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 3979.759485] [drm:intel_dump_pipe_config [i915]] [CRTC:37:pipe A][modeset]
>[ 3979.759494] [drm:intel_power_well_enable [i915]] enabling power well 2
>[ 3979.759506] [drm:intel_dump_pipe_config [i915]] output_types: EDP (0x100)
>[ 3979.759517] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0
>[ 3979.759529] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 6467616, gmch_n: 8388608, link_m: 269484, link_n: 524288, tu: 64
>[ 3979.759540] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[ 3979.759551] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 3979.759556] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[ 3979.759567] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 3979.759572] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[ 3979.759584] [drm:intel_dump_pipe_config [i915]] crtc timings: 138780 1920 1966 1996 2080 1080 1082 1086 1112, type: 0x48 flags: 0xa
>[ 3979.759594] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 138780
>[ 3979.759605] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[ 3979.759615] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 3979.759625] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 3979.759636] [drm:intel_dump_pipe_config [i915]] dpll_hw_state: ctrl1: 0x3, cfgcr1: 0x0, cfgcr2: 0x0
>[ 3979.759646] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 3979.759656] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 1A] disabled, scaler_id = -1
>[ 3979.759666] [drm:intel_dump_pipe_config [i915]] [PLANE:31:plane 2A] disabled, scaler_id = -1
>[ 3979.759676] [drm:intel_dump_pipe_config [i915]] [PLANE:34:cursor A] disabled, scaler_id = -1
>[ 3979.759689] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 3979.759700] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[ 3979.759715] [drm:intel_find_shared_dpll [i915]] [CRTC:37:pipe A] allocated DPLL 0
>[ 3979.759727] [drm:intel_reference_shared_dpll [i915]] using DPLL 0 for pipe A
>[ 3979.761610] [drm:intel_atomic_commit_tail [i915]] [ENCODER:48:DDI A]
>[ 3979.761625] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI B]
>[ 3979.761638] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[ 3979.761651] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[ 3979.761662] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DDI C]
>[ 3979.761674] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST A]
>[ 3979.761686] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST B]
>[ 3979.761697] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI D]
>[ 3979.761708] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[ 3979.761719] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[ 3979.761732] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[ 3979.761745] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[ 3979.761757] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[ 3979.761769] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[ 3979.761783] [drm:intel_enable_shared_dpll [i915]] enable DPLL 0 (active 1, on? 0) for crtc 37
>[ 3979.761795] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 0
>[ 3979.761814] [drm:edp_panel_on [i915]] Turn eDP port A panel power on
>[ 3979.761839] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle
>[ 3979.763526] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010
>[ 3979.763541] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[ 3979.763555] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0
>[ 3980.380218] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 00000000 control 00000060
>[ 3980.380310] [drm:wait_panel_status [i915]] Wait complete
>[ 3980.380448] [drm:edp_panel_on [i915]] Wait for panel power on
>[ 3980.380582] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 00000063
>[ 3980.414307] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010
>[ 3980.414380] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[ 3980.414470] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1
>[ 3980.580718] [drm:wait_panel_status [i915]] Wait complete
>[ 3980.580784] [drm:intel_power_well_enable [i915]] enabling DDI A/E IO power well
>[ 3980.580887] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[ 3980.581040] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b
>[ 3980.582239] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 3980.582302] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 3980.582362] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 3980.582421] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 3980.583132] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 3980.583190] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 3980.584164] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 3980.584177] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:49:eDP-1] Link Training Passed at Link Rate = 270000, Lane count = 2
>[ 3980.584581] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 3980.584603] [drm:intel_edp_backlight_on [i915]] 
>[ 3980.584615] [drm:intel_panel_enable_backlight [i915]] pipe A
>[ 3980.584654] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 120000
>[ 3980.592182] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS
>[ 3983.836026] [drm:edp_panel_vdd_off_sync [i915]] Turning eDP port A VDD off
>[ 3983.836164] [drm:edp_panel_vdd_off_sync [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x00000067
>[ 3984.332109] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 3984.332190] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 3984.593180] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 3984.593261] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 3990.163335] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 3990.163416] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 3990.424636] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 3990.424717] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 3990.748085] [drm:drm_atomic_helper_wait_for_flip_done [drm_kms_helper]] *ERROR* [CRTC:37:pipe A] flip_done timed out
>[ 3990.748210] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:49:eDP-1]
>[ 3990.748294] [drm:intel_atomic_commit_tail [i915]] [CRTC:37:pipe A]
>[ 3990.748389] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[ 3990.748972] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 00 00 04 00 0f 00 04
>[ 3990.750376] [drm:intel_power_well_disable [i915]] disabling power well 2
>[ 3990.750433] [drm:intel_power_well_disable [i915]] disabling DC off
>[ 3990.750483] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[ 3990.750531] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[ 3990.750604] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[ 3990.750667] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[ 3990.750717] [drm:intel_power_well_enable [i915]] enabling DC off
>[ 3990.750764] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[ 3990.750816] [drm:intel_power_well_enable [i915]] enabling power well 2
>[ 3990.751295] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 00 00 04 00 0f 00 04
>[ 3990.752699] [drm:intel_power_well_disable [i915]] disabling power well 2
>[ 3990.752751] [drm:intel_power_well_disable [i915]] disabling DC off
>[ 3990.752800] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[ 3990.752847] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[ 3990.784605] [drm:intel_power_well_enable [i915]] enabling DC off
>[ 3990.784657] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[ 3990.784744] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[ 3990.784887] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006f
>[ 3990.984871] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped
>[ 3991.234882] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped
>[ 3994.331983] [drm:edp_panel_vdd_off_sync [i915]] Turning eDP port A VDD off
>[ 3994.332121] [drm:edp_panel_vdd_off_sync [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x00000067
>[ 3994.332172] [drm:intel_power_well_disable [i915]] disabling DC off
>[ 3994.332223] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[ 3994.332270] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[ 3995.989941] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 3995.990022] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 3995.990140] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[ 3995.990204] [drm:intel_power_well_enable [i915]] enabling DC off
>[ 3995.990269] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[ 3995.990327] [drm:intel_power_well_enable [i915]] enabling power well 2
>[ 3995.990828] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 00 00 04 00 0f 00 04
>[ 3995.991182] [drm:intel_power_well_disable [i915]] disabling power well 2
>[ 3995.991236] [drm:intel_power_well_disable [i915]] disabling DC off
>[ 3995.991285] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[ 3995.991331] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[ 3995.991410] [drm:i915_hotplug_work_func [i915]] running encoder hotplug functions
>[ 3995.991479] [drm:i915_hotplug_work_func [i915]] Connector DP-1 (pin 5) received hotplug event.
>[ 3995.991546] [drm:intel_dp_detect [i915]] [CONNECTOR:57:DP-1]
>[ 3995.991594] [drm:intel_power_well_enable [i915]] enabling DC off
>[ 3995.991642] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[ 3995.991693] [drm:intel_power_well_enable [i915]] enabling power well 2
>[ 3995.992149] [drm:lspcon_wake_native_aux_ch [i915]] Native AUX CH up, DPCD version: 1.2
>[ 3995.992227] [drm:lspcon_resume [i915]] LSPCON recovering in PCON mode after 0 ms
>[ 3995.992668] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 3995.993924] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 3995.995177] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 3995.996444] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 3995.997697] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 3995.998579] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[ 3995.999055] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 00 00 04 00 0f 00 04
>[ 3995.999402] [drm:intel_power_well_disable [i915]] disabling power well 2
>[ 3995.999452] [drm:intel_power_well_disable [i915]] disabling DC off
>[ 3995.999497] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[ 3995.999540] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[ 3995.999607] [drm:i915_hotplug_work_func [i915]] [CONNECTOR:57:DP-1] status updated from connected to disconnected
>[ 3996.249177] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 3996.249258] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 3996.249380] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[ 3996.249448] [drm:intel_power_well_enable [i915]] enabling DC off
>[ 3996.249512] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[ 3996.249570] [drm:intel_power_well_enable [i915]] enabling power well 2
>[ 3996.250070] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 00 00 04 00 0f 00 04
>[ 3996.250839] [drm:intel_power_well_disable [i915]] disabling power well 2
>[ 3996.250894] [drm:intel_power_well_disable [i915]] disabling DC off
>[ 3996.250944] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[ 3996.250992] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[ 3996.251092] [drm:i915_hotplug_work_func [i915]] running encoder hotplug functions
>[ 3996.251162] [drm:i915_hotplug_work_func [i915]] Connector DP-1 (pin 5) received hotplug event.
>[ 3996.251241] [drm:intel_dp_detect [i915]] [CONNECTOR:57:DP-1]
>[ 3996.251286] [drm:intel_power_well_enable [i915]] enabling DC off
>[ 3996.251329] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[ 3996.251375] [drm:intel_power_well_enable [i915]] enabling power well 2
>[ 3996.251753] [drm:lspcon_wake_native_aux_ch [i915]] Native AUX CH up, DPCD version: 1.2
>[ 3996.251821] [drm:lspcon_resume [i915]] LSPCON recovering in PCON mode after 0 ms
>[ 3996.252285] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 3996.253539] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 3996.254791] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 3996.256037] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 3996.257288] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 3996.258155] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[ 3996.258629] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 00 00 04 00 0f 00 04
>[ 3996.259402] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>[ 3996.259460] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000
>[ 3996.259514] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000
>[ 3996.259941] [drm:drm_dp_read_desc [drm_kms_helper]] DP branch: OUI 00-60-ad dev-ID MC2800 HW-rev 2.2 SW-rev 1.70 quirks 0x0000
>[ 3996.260295] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[ 3996.261064] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 3996.262284] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 3996.263540] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 3996.264761] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 3996.266009] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 3996.267245] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 3996.268474] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 3996.269727] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 3996.270970] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 3996.272351] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 3996.273727] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 3996.275101] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 3996.276480] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 3996.277855] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 3996.279232] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 3996.280640] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 3996.282008] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 3996.283245] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 3996.284539] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 3996.285815] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 3996.287056] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 3996.288432] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 3996.289812] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 3996.291193] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 3996.292588] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 3996.293964] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 3996.295338] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 3996.296628] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 3996.297997] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 3996.299145] [drm:intel_power_well_disable [i915]] disabling power well 2
>[ 3996.299197] [drm:intel_power_well_disable [i915]] disabling DC off
>[ 3996.299244] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[ 3996.299288] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[ 3996.299366] [drm:i915_hotplug_work_func [i915]] [CONNECTOR:57:DP-1] status updated from disconnected to connected
>[ 3996.299430] [drm:intel_power_well_enable [i915]] enabling DC off
>[ 3996.299482] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[ 3996.299571] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[ 3996.299717] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006f
>[ 3996.484772] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped
>[ 3999.707989] [drm:edp_panel_vdd_off_sync [i915]] Turning eDP port A VDD off
>[ 3999.708133] [drm:edp_panel_vdd_off_sync [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x00000067
>[ 3999.708190] [drm:intel_power_well_disable [i915]] disabling DC off
>[ 3999.708247] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[ 3999.708299] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[ 4001.534556] [drm:intel_power_well_enable [i915]] enabling DC off
>[ 4001.534615] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[ 4001.534712] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[ 4001.534866] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006f
>[ 4001.734701] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped
>[ 4001.817614] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 4001.817696] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 4001.817826] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[ 4001.817891] [drm:intel_power_well_enable [i915]] enabling power well 2
>[ 4001.818404] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 00 00 04 00 0f 00 04
>[ 4001.818759] [drm:intel_power_well_disable [i915]] disabling power well 2
>[ 4001.818843] [drm:i915_hotplug_work_func [i915]] running encoder hotplug functions
>[ 4001.818912] [drm:i915_hotplug_work_func [i915]] Connector DP-1 (pin 5) received hotplug event.
>[ 4001.818977] [drm:intel_dp_detect [i915]] [CONNECTOR:57:DP-1]
>[ 4001.819028] [drm:intel_power_well_enable [i915]] enabling power well 2
>[ 4001.819413] [drm:lspcon_wake_native_aux_ch [i915]] Native AUX CH up, DPCD version: 1.2
>[ 4001.819488] [drm:lspcon_resume [i915]] LSPCON recovering in PCON mode after 0 ms
>[ 4001.819958] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4001.821211] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4001.822463] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4001.823705] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4001.824962] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4001.825821] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[ 4001.826296] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 00 00 04 00 0f 00 04
>[ 4001.826644] [drm:intel_power_well_disable [i915]] disabling power well 2
>[ 4001.826714] [drm:i915_hotplug_work_func [i915]] [CONNECTOR:57:DP-1] status updated from connected to disconnected
>[ 4002.077664] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 4002.077745] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 4002.077864] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[ 4002.077931] [drm:intel_power_well_enable [i915]] enabling power well 2
>[ 4002.078442] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 00 00 04 00 0f 00 04
>[ 4002.079213] [drm:intel_power_well_disable [i915]] disabling power well 2
>[ 4002.079295] [drm:i915_hotplug_work_func [i915]] running encoder hotplug functions
>[ 4002.079365] [drm:i915_hotplug_work_func [i915]] Connector DP-1 (pin 5) received hotplug event.
>[ 4002.079432] [drm:intel_dp_detect [i915]] [CONNECTOR:57:DP-1]
>[ 4002.079483] [drm:intel_power_well_enable [i915]] enabling power well 2
>[ 4002.079908] [drm:lspcon_wake_native_aux_ch [i915]] Native AUX CH up, DPCD version: 1.2
>[ 4002.079983] [drm:lspcon_resume [i915]] LSPCON recovering in PCON mode after 0 ms
>[ 4002.080423] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4002.081672] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4002.082925] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4002.084189] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4002.085462] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4002.086328] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[ 4002.086804] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 00 00 04 00 0f 00 04
>[ 4002.087580] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>[ 4002.087640] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000
>[ 4002.087696] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000
>[ 4002.088167] [drm:drm_dp_read_desc [drm_kms_helper]] DP branch: OUI 00-60-ad dev-ID MC2800 HW-rev 2.2 SW-rev 1.70 quirks 0x0000
>[ 4002.088521] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[ 4002.089292] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4002.090510] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4002.091729] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4002.092974] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4002.094232] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4002.095468] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4002.096664] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4002.097914] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4002.099158] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4002.100555] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4002.101948] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4002.103325] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4002.104651] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4002.106028] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4002.107405] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4002.108735] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4002.110102] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4002.111342] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4002.112530] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4002.113790] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4002.115025] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4002.116402] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4002.117799] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4002.119198] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4002.120594] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4002.121977] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4002.123351] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4002.124652] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4002.126018] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4002.127154] [drm:intel_power_well_disable [i915]] disabling power well 2
>[ 4002.127229] [drm:i915_hotplug_work_func [i915]] [CONNECTOR:57:DP-1] status updated from disconnected to connected
>[ 4004.828008] [drm:edp_panel_vdd_off_sync [i915]] Turning eDP port A VDD off
>[ 4004.828152] [drm:edp_panel_vdd_off_sync [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x00000067
>[ 4004.828210] [drm:intel_power_well_disable [i915]] disabling DC off
>[ 4004.828268] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[ 4004.828320] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[ 4006.784521] [drm:intel_power_well_enable [i915]] enabling DC off
>[ 4006.784581] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[ 4006.784679] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[ 4006.784834] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006f
>[ 4006.984589] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped
>[ 4007.648172] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 4007.648240] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 4007.648316] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[ 4007.648363] [drm:intel_power_well_enable [i915]] enabling power well 2
>[ 4007.648850] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 00 00 04 00 0f 00 04
>[ 4007.649195] [drm:intel_power_well_disable [i915]] disabling power well 2
>[ 4007.649268] [drm:i915_hotplug_work_func [i915]] running encoder hotplug functions
>[ 4007.649330] [drm:i915_hotplug_work_func [i915]] Connector DP-1 (pin 5) received hotplug event.
>[ 4007.649389] [drm:intel_dp_detect [i915]] [CONNECTOR:57:DP-1]
>[ 4007.649434] [drm:intel_power_well_enable [i915]] enabling power well 2
>[ 4007.649807] [drm:lspcon_wake_native_aux_ch [i915]] Native AUX CH up, DPCD version: 1.2
>[ 4007.649875] [drm:lspcon_resume [i915]] LSPCON recovering in PCON mode after 0 ms
>[ 4007.650312] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4007.651531] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4007.652741] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4007.653976] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4007.655225] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4007.656110] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[ 4007.656584] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 00 00 04 00 0f 00 04
>[ 4007.656929] [drm:intel_power_well_disable [i915]] disabling power well 2
>[ 4007.657000] [drm:i915_hotplug_work_func [i915]] [CONNECTOR:57:DP-1] status updated from connected to disconnected
>[ 4007.908894] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 4007.908966] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 4007.909064] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[ 4007.909123] [drm:intel_power_well_enable [i915]] enabling power well 2
>[ 4007.909616] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 00 00 04 00 0f 00 04
>[ 4007.910374] [drm:intel_power_well_disable [i915]] disabling power well 2
>[ 4007.910447] [drm:i915_hotplug_work_func [i915]] running encoder hotplug functions
>[ 4007.910508] [drm:i915_hotplug_work_func [i915]] Connector DP-1 (pin 5) received hotplug event.
>[ 4007.910567] [drm:intel_dp_detect [i915]] [CONNECTOR:57:DP-1]
>[ 4007.910612] [drm:intel_power_well_enable [i915]] enabling power well 2
>[ 4007.910987] [drm:lspcon_wake_native_aux_ch [i915]] Native AUX CH up, DPCD version: 1.2
>[ 4007.911056] [drm:lspcon_resume [i915]] LSPCON recovering in PCON mode after 0 ms
>[ 4007.911492] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4007.912688] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4007.913938] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4007.915189] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4007.916457] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4007.917344] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[ 4007.917820] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 00 00 04 00 0f 00 04
>[ 4007.918595] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>[ 4007.918652] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000
>[ 4007.918706] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000
>[ 4007.919105] [drm:drm_dp_read_desc [drm_kms_helper]] DP branch: OUI 00-60-ad dev-ID MC2800 HW-rev 2.2 SW-rev 1.70 quirks 0x0000
>[ 4007.919455] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[ 4007.920230] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4007.921447] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4007.922669] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4007.923919] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4007.925164] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4007.926399] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4007.927650] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4007.928908] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4007.930152] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4007.931527] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4007.932883] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4007.934249] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4007.935623] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4007.937006] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4007.938382] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4007.939761] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4007.941133] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4007.942374] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4007.943628] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4007.944857] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4007.946101] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4007.947477] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4007.948798] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4007.950143] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4007.951552] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4007.952908] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4007.954285] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4007.955660] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4007.957031] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4007.958176] [drm:intel_power_well_disable [i915]] disabling power well 2
>[ 4007.958252] [drm:i915_hotplug_work_func [i915]] [CONNECTOR:57:DP-1] status updated from disconnected to connected
>[ 4010.203987] [drm:edp_panel_vdd_off_sync [i915]] Turning eDP port A VDD off
>[ 4010.204134] [drm:edp_panel_vdd_off_sync [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x00000067
>[ 4010.204190] [drm:intel_power_well_disable [i915]] disabling DC off
>[ 4010.204247] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[ 4010.204300] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[ 4013.479353] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 4013.479434] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 4013.479558] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[ 4013.479625] [drm:intel_power_well_enable [i915]] enabling DC off
>[ 4013.479690] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[ 4013.479750] [drm:intel_power_well_enable [i915]] enabling power well 2
>[ 4013.739557] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 4013.739639] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 4019.316044] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 4019.316126] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 4019.576090] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 4019.576171] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 4022.236138] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [CRTC:37:pipe A] flip_done timed out
>[ 4025.148566] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 4025.148646] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 4025.409938] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 4025.410019] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 4030.984168] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 4030.984250] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 4031.244110] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 4031.244191] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 4032.476177] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [PLANE:28:plane 1A] flip_done timed out
>[ 4036.812806] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 4036.812886] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 4037.072680] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 4037.072759] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 4042.636418] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 4042.636500] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 4042.716039] [drm:drm_atomic_helper_wait_for_flip_done [drm_kms_helper]] *ERROR* [CRTC:37:pipe A] flip_done timed out
>[ 4042.716317] [IGT] kms_frontbuffer_tracking: exiting, ret=0
>[ 4042.716387] Setting dangerous option enable_psr - tainting kernel
>[ 4042.716402] Setting dangerous option enable_fbc - tainting kernel
>[ 4042.716637] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 00 00 04 00 0f 00 04
>[ 4042.717149] [drm:intel_power_well_disable [i915]] disabling power well 2
>[ 4042.717222] [drm:intel_power_well_disable [i915]] disabling DC off
>[ 4042.717298] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[ 4042.717347] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[ 4042.717528] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[ 4042.717587] [drm:intel_power_well_enable [i915]] enabling DC off
>[ 4042.717634] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[ 4042.717684] [drm:intel_power_well_enable [i915]] enabling power well 2
>[ 4042.717825] [drm:i915_hotplug_work_func [i915]] running encoder hotplug functions
>[ 4042.717919] [drm:i915_hotplug_work_func [i915]] Connector DP-1 (pin 5) received hotplug event.
>[ 4042.718189] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 00 00 04 00 0f 00 04
>[ 4042.718541] [drm:intel_power_well_disable [i915]] disabling power well 2
>[ 4042.718593] [drm:intel_power_well_disable [i915]] disabling DC off
>[ 4042.718642] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[ 4042.718688] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[ 4042.718760] [drm:intel_dp_detect [i915]] [CONNECTOR:57:DP-1]
>[ 4042.718807] [drm:intel_power_well_enable [i915]] enabling DC off
>[ 4042.718854] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[ 4042.718905] [drm:intel_power_well_enable [i915]] enabling power well 2
>[ 4042.719290] [drm:lspcon_wake_native_aux_ch [i915]] Native AUX CH up, DPCD version: 1.2
>[ 4042.719366] [drm:lspcon_resume [i915]] LSPCON recovering in PCON mode after 0 ms
>[ 4042.719807] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4042.721065] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4042.722333] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4042.723592] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4042.724834] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4042.725725] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[ 4042.726212] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 00 00 04 00 0f 00 04
>[ 4042.726567] [drm:intel_power_well_disable [i915]] disabling power well 2
>[ 4042.726624] [drm:intel_power_well_disable [i915]] disabling DC off
>[ 4042.726675] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[ 4042.726723] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[ 4042.726798] [drm:i915_hotplug_work_func [i915]] [CONNECTOR:57:DP-1] status updated from connected to disconnected
>[ 4042.726856] [drm:drm_fb_helper_hotplug_event.part.30 [drm_kms_helper]] 
>[ 4042.726872] [drm:drm_setup_crtcs [drm_kms_helper]] 
>[ 4042.726892] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:49:eDP-1]
>[ 4042.726985] [drm:intel_dp_detect [i915]] [CONNECTOR:49:eDP-1]
>[ 4042.727064] [drm:intel_power_well_enable [i915]] enabling DC off
>[ 4042.727143] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[ 4042.727247] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>[ 4042.727338] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[ 4042.727430] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[ 4042.727534] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[ 4042.727702] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006f
>[ 4042.728207] [drm:drm_dp_read_desc [drm_kms_helper]] DP sink: OUI 00-1c-f8 dev-ID  HW-rev 0.1 SW-rev 1.22 quirks 0x0000
>[ 4042.728936] [drm:drm_add_edid_modes [drm]] ELD: no CEA Extension found
>[ 4042.728986] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:49:eDP-1] probed modes :
>[ 4042.729016] [drm:drm_mode_debug_printmodeline [drm]] Modeline 50:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[ 4042.729028] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:57:DP-1]
>[ 4042.729096] [drm:intel_dp_detect [i915]] [CONNECTOR:57:DP-1]
>[ 4042.729147] [drm:intel_power_well_enable [i915]] enabling power well 2
>[ 4042.729534] [drm:lspcon_wake_native_aux_ch [i915]] Native AUX CH up, DPCD version: 1.2
>[ 4042.729609] [drm:lspcon_resume [i915]] LSPCON recovering in PCON mode after 0 ms
>[ 4042.730049] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4042.731292] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4042.732591] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4042.733852] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4042.735085] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4042.735974] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[ 4042.736449] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 00 00 04 00 0f 00 04
>[ 4042.736793] [drm:intel_power_well_disable [i915]] disabling power well 2
>[ 4042.736812] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:57:DP-1] disconnected
>[ 4042.736831] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:61:DP-2]
>[ 4042.736893] [drm:intel_dp_detect [i915]] [CONNECTOR:61:DP-2]
>[ 4042.736938] [drm:intel_power_well_enable [i915]] enabling power well 2
>[ 4042.737016] [drm:intel_power_well_disable [i915]] disabling power well 2
>[ 4042.737032] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:61:DP-2] disconnected
>[ 4042.737042] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:64:HDMI-A-1]
>[ 4042.737102] [drm:intel_hdmi_detect [i915]] [CONNECTOR:64:HDMI-A-1]
>[ 4042.737466] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[ 4042.737520] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[ 4042.737878] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[ 4042.737905] [drm:drm_do_probe_ddc_edid [drm]] drm: skipping non-existent adapter i915 gmbus dpc
>[ 4042.738264] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[ 4042.738316] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[ 4042.738673] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[ 4042.738688] [drm:drm_dp_dual_mode_detect [drm_kms_helper]] DP dual mode HDMI ID:  (err -6)
>[ 4042.738699] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:64:HDMI-A-1] disconnected
>[ 4042.738710] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:67:DP-3]
>[ 4042.738764] [drm:intel_dp_detect [i915]] [CONNECTOR:67:DP-3]
>[ 4042.738809] [drm:intel_power_well_enable [i915]] enabling power well 2
>[ 4042.738882] [drm:intel_power_well_disable [i915]] disabling power well 2
>[ 4042.738897] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:67:DP-3] disconnected
>[ 4042.738907] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:70:HDMI-A-2]
>[ 4042.738960] [drm:intel_hdmi_detect [i915]] [CONNECTOR:70:HDMI-A-2]
>[ 4042.749946] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0050 w(1)
>[ 4042.750015] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK on first message, retry
>[ 4042.759807] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0050 w(1)
>[ 4042.759851] [drm:drm_do_probe_ddc_edid [drm]] drm: skipping non-existent adapter i915 gmbus dpd
>[ 4042.769290] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0040 w(1)
>[ 4042.769305] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK on first message, retry
>[ 4042.779185] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0040 w(1)
>[ 4042.779193] [drm:drm_dp_dual_mode_detect [drm_kms_helper]] DP dual mode HDMI ID:  (err -6)
>[ 4042.779198] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:70:HDMI-A-2] disconnected
>[ 4042.779202] [drm:drm_setup_crtcs [drm_kms_helper]] connector 49 enabled? yes
>[ 4042.779205] [drm:drm_setup_crtcs [drm_kms_helper]] connector 57 enabled? no
>[ 4042.779208] [drm:drm_setup_crtcs [drm_kms_helper]] connector 61 enabled? no
>[ 4042.779210] [drm:drm_setup_crtcs [drm_kms_helper]] connector 64 enabled? no
>[ 4042.779213] [drm:drm_setup_crtcs [drm_kms_helper]] connector 67 enabled? no
>[ 4042.779215] [drm:drm_setup_crtcs [drm_kms_helper]] connector 70 enabled? no
>[ 4042.779235] [drm:intel_fb_initial_config [i915]] Not using firmware configuration
>[ 4042.779239] [drm:drm_setup_crtcs [drm_kms_helper]] looking for cmdline mode on connector 49
>[ 4042.779242] [drm:drm_setup_crtcs [drm_kms_helper]] looking for preferred mode on connector 49 0
>[ 4042.779244] [drm:drm_setup_crtcs [drm_kms_helper]] found mode 1920x1080
>[ 4042.779247] [drm:drm_setup_crtcs [drm_kms_helper]] picking CRTCs for 1920x1080 config
>[ 4042.779252] [drm:drm_setup_crtcs [drm_kms_helper]] desired mode 1920x1080 set on crtc 37 (0,0)
>[ 4042.894746] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 4042.894828] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 4042.894951] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[ 4042.895017] [drm:intel_power_well_enable [i915]] enabling power well 2
>[ 4045.788149] [drm:edp_panel_vdd_off_sync [i915]] Turning eDP port A VDD off
>[ 4045.788294] [drm:edp_panel_vdd_off_sync [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x00000067
>[ 4048.459220] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 4048.459302] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 4048.719653] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 4048.719734] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 4052.956160] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [CRTC:37:pipe A] flip_done timed out
>[ 4054.281549] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 4054.281630] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 4054.542262] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 4054.542342] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 4060.112604] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 4060.112686] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 4060.373256] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 4060.373337] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 4063.196072] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [CONNECTOR:49:eDP-1] flip_done timed out
>[ 4065.946738] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 4065.946820] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 4066.208229] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 4066.208310] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 4071.783412] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 4071.783494] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 4072.044799] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 4072.044880] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 4073.436040] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [PLANE:28:plane 1A] flip_done timed out
>[ 4073.436152] [drm:intel_fbc_enable [i915]] reserved 16588800 bytes of contiguous stolen space for FBC, threshold: 1
>[ 4073.436227] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 4077.613830] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 4077.613911] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 4077.877164] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 4077.877246] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 4083.445354] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 4083.445434] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 4083.676173] [drm:drm_atomic_helper_wait_for_flip_done [drm_kms_helper]] *ERROR* [CRTC:37:pipe A] flip_done timed out
>[ 4083.676246] [drm:drm_fb_helper_hotplug_event.part.30 [drm_kms_helper]] 
>[ 4083.676258] [drm:drm_setup_crtcs [drm_kms_helper]] 
>[ 4083.676274] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:49:eDP-1]
>[ 4083.676788] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 00 00 04 00 0f 00 04
>[ 4083.677145] [drm:intel_power_well_disable [i915]] disabling power well 2
>[ 4083.677200] [drm:intel_power_well_disable [i915]] disabling DC off
>[ 4083.677250] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[ 4083.677299] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[ 4083.677374] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[ 4083.677422] [drm:intel_power_well_enable [i915]] enabling DC off
>[ 4083.677469] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[ 4083.677519] [drm:intel_power_well_enable [i915]] enabling power well 2
>[ 4083.678005] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 00 00 04 00 0f 00 04
>[ 4083.678356] [drm:intel_power_well_disable [i915]] disabling power well 2
>[ 4083.678407] [drm:intel_power_well_disable [i915]] disabling DC off
>[ 4083.678455] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[ 4083.678502] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[ 4083.678575] [drm:intel_dp_detect [i915]] [CONNECTOR:49:eDP-1]
>[ 4083.678623] [drm:intel_power_well_enable [i915]] enabling DC off
>[ 4083.678669] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[ 4083.678741] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>[ 4083.678803] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[ 4083.678863] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[ 4083.678936] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[ 4083.679075] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006f
>[ 4083.679508] [drm:drm_dp_read_desc [drm_kms_helper]] DP sink: OUI 00-1c-f8 dev-ID  HW-rev 0.1 SW-rev 1.22 quirks 0x0000
>[ 4083.680317] [drm:drm_add_edid_modes [drm]] ELD: no CEA Extension found
>[ 4083.680368] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:49:eDP-1] probed modes :
>[ 4083.680398] [drm:drm_mode_debug_printmodeline [drm]] Modeline 50:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[ 4083.680412] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:57:DP-1]
>[ 4083.680477] [drm:intel_dp_detect [i915]] [CONNECTOR:57:DP-1]
>[ 4083.680529] [drm:intel_power_well_enable [i915]] enabling power well 2
>[ 4083.680855] [drm:lspcon_wake_native_aux_ch [i915]] Native AUX CH up, DPCD version: 1.2
>[ 4083.680893] [drm:lspcon_resume [i915]] LSPCON recovering in PCON mode after 0 ms
>[ 4083.681306] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4083.682579] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4083.683880] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4083.685149] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4083.686412] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4083.687262] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[ 4083.687658] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 00 00 04 00 0f 00 04
>[ 4083.687942] [drm:intel_power_well_disable [i915]] disabling power well 2
>[ 4083.687947] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:57:DP-1] disconnected
>[ 4083.687950] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:61:DP-2]
>[ 4083.687964] [drm:intel_dp_detect [i915]] [CONNECTOR:61:DP-2]
>[ 4083.687974] [drm:intel_power_well_enable [i915]] enabling power well 2
>[ 4083.688002] [drm:intel_power_well_disable [i915]] disabling power well 2
>[ 4083.688010] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:61:DP-2] disconnected
>[ 4083.688012] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:64:HDMI-A-1]
>[ 4083.688026] [drm:intel_hdmi_detect [i915]] [CONNECTOR:64:HDMI-A-1]
>[ 4083.688340] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[ 4083.688352] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[ 4083.688664] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[ 4083.688670] [drm:drm_do_probe_ddc_edid [drm]] drm: skipping non-existent adapter i915 gmbus dpc
>[ 4083.688980] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[ 4083.688991] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[ 4083.689301] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[ 4083.689304] [drm:drm_dp_dual_mode_detect [drm_kms_helper]] DP dual mode HDMI ID:  (err -6)
>[ 4083.689307] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:64:HDMI-A-1] disconnected
>[ 4083.689309] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:67:DP-3]
>[ 4083.689322] [drm:intel_dp_detect [i915]] [CONNECTOR:67:DP-3]
>[ 4083.689332] [drm:intel_power_well_enable [i915]] enabling power well 2
>[ 4083.689359] [drm:intel_power_well_disable [i915]] disabling power well 2
>[ 4083.689366] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:67:DP-3] disconnected
>[ 4083.689368] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:70:HDMI-A-2]
>[ 4083.689380] [drm:intel_hdmi_detect [i915]] [CONNECTOR:70:HDMI-A-2]
>[ 4083.700048] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0050 w(1)
>[ 4083.700067] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK on first message, retry
>[ 4083.708646] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 4083.708669] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 4083.708698] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[ 4083.708715] [drm:intel_power_well_enable [i915]] enabling power well 2
>[ 4083.709940] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0050 w(1)
>[ 4083.709951] [drm:drm_do_probe_ddc_edid [drm]] drm: skipping non-existent adapter i915 gmbus dpd
>[ 4083.719801] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0040 w(1)
>[ 4083.719885] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK on first message, retry
>[ 4083.730851] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0040 w(1)
>[ 4083.730869] [drm:drm_dp_dual_mode_detect [drm_kms_helper]] DP dual mode HDMI ID:  (err -6)
>[ 4083.730883] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:70:HDMI-A-2] disconnected
>[ 4083.730902] [drm:drm_setup_crtcs [drm_kms_helper]] connector 49 enabled? yes
>[ 4083.730912] [drm:drm_setup_crtcs [drm_kms_helper]] connector 57 enabled? no
>[ 4083.730921] [drm:drm_setup_crtcs [drm_kms_helper]] connector 61 enabled? no
>[ 4083.730930] [drm:drm_setup_crtcs [drm_kms_helper]] connector 64 enabled? no
>[ 4083.730939] [drm:drm_setup_crtcs [drm_kms_helper]] connector 67 enabled? no
>[ 4083.730951] [drm:drm_setup_crtcs [drm_kms_helper]] connector 70 enabled? no
>[ 4083.731423] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 00 00 04 00 0f 00 04
>[ 4083.732208] [drm:intel_power_well_disable [i915]] disabling power well 2
>[ 4083.732283] [drm:intel_fb_initial_config [i915]] Not using firmware configuration
>[ 4083.732297] [drm:drm_setup_crtcs [drm_kms_helper]] looking for cmdline mode on connector 49
>[ 4083.732309] [drm:drm_setup_crtcs [drm_kms_helper]] looking for preferred mode on connector 49 0
>[ 4083.732319] [drm:drm_setup_crtcs [drm_kms_helper]] found mode 1920x1080
>[ 4083.732328] [drm:drm_setup_crtcs [drm_kms_helper]] picking CRTCs for 1920x1080 config
>[ 4083.732343] [drm:drm_setup_crtcs [drm_kms_helper]] desired mode 1920x1080 set on crtc 37 (0,0)
>[ 4086.748261] [drm:edp_panel_vdd_off_sync [i915]] Turning eDP port A VDD off
>[ 4086.748406] [drm:edp_panel_vdd_off_sync [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x00000067
>[ 4086.748464] [drm:intel_power_well_disable [i915]] disabling DC off
>[ 4086.748521] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[ 4086.748574] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[ 4089.273952] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 4089.274034] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 4089.274158] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[ 4089.274223] [drm:intel_power_well_enable [i915]] enabling DC off
>[ 4089.274290] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[ 4089.274349] [drm:intel_power_well_enable [i915]] enabling power well 2
>[ 4089.534943] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 4089.535025] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 4093.916078] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [CRTC:37:pipe A] flip_done timed out
>[ 4095.107405] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 4095.107486] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 4095.368808] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 4095.368890] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 4100.944138] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 4100.944220] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 4101.205816] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 4101.205897] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 4104.156069] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [CONNECTOR:49:eDP-1] flip_done timed out
>[ 4106.774917] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 4106.774999] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 4107.034841] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 4107.034921] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 4112.609102] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 4112.609183] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 4112.869096] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 4112.869177] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 4114.396177] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [PLANE:28:plane 1A] flip_done timed out
>[ 4118.438877] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 4118.438959] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 4118.700111] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 4118.700193] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 4124.277224] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 4124.277304] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 4124.536951] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 4124.537033] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 4124.636165] [drm:drm_atomic_helper_wait_for_flip_done [drm_kms_helper]] *ERROR* [CRTC:37:pipe A] flip_done timed out
>[ 4124.636777] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 00 00 04 00 0f 00 04
>[ 4124.638233] [drm:intel_power_well_disable [i915]] disabling power well 2
>[ 4124.638318] [drm:intel_power_well_disable [i915]] disabling DC off
>[ 4124.638397] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[ 4124.638474] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[ 4124.638576] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[ 4124.638652] [drm:intel_power_well_enable [i915]] enabling DC off
>[ 4124.638728] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[ 4124.638806] [drm:intel_power_well_enable [i915]] enabling power well 2
>[ 4124.639334] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 00 00 04 00 0f 00 04
>[ 4124.640793] [drm:intel_power_well_disable [i915]] disabling power well 2
>[ 4124.640875] [drm:intel_power_well_disable [i915]] disabling DC off
>[ 4124.640954] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[ 4124.641031] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[ 4124.693848] [IGT] kms_frontbuffer_tracking: executing
>[ 4130.112652] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 4130.112733] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 4130.112856] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[ 4130.112921] [drm:intel_power_well_enable [i915]] enabling DC off
>[ 4130.112987] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[ 4130.113045] [drm:intel_power_well_enable [i915]] enabling power well 2
>[ 4130.373869] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 4130.373951] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 4134.876081] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [CRTC:37:pipe A] flip_done timed out
>[ 4135.944630] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 4135.944712] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 4136.205038] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 4136.205119] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 4141.776758] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 4141.776839] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 4142.035256] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 4142.035337] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 4145.115919] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [CONNECTOR:49:eDP-1] flip_done timed out
>[ 4147.599865] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 4147.599946] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 4147.861995] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 4147.862077] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 4153.430220] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 4153.430301] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 4153.690211] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 4153.690292] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 4155.356173] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [PLANE:28:plane 1A] flip_done timed out
>[ 4159.256629] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 4159.256711] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 4159.519004] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 4159.519084] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 4165.094012] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 4165.094092] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 4165.356595] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 4165.356675] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 4165.596074] [drm:drm_atomic_helper_wait_for_flip_done [drm_kms_helper]] *ERROR* [CRTC:37:pipe A] flip_done timed out
>[ 4165.596222] [drm:i915_hotplug_work_func [i915]] running encoder hotplug functions
>[ 4165.596310] [drm:i915_hotplug_work_func [i915]] Connector DP-1 (pin 5) received hotplug event.
>[ 4165.596706] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 00 00 04 00 0f 00 04
>[ 4165.598122] [drm:intel_power_well_disable [i915]] disabling power well 2
>[ 4165.598178] [drm:intel_power_well_disable [i915]] disabling DC off
>[ 4165.598229] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[ 4165.598278] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[ 4165.598350] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[ 4165.598398] [drm:intel_power_well_enable [i915]] enabling DC off
>[ 4165.598446] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[ 4165.598497] [drm:intel_power_well_enable [i915]] enabling power well 2
>[ 4165.598982] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 00 00 04 00 0f 00 04
>[ 4165.600404] [drm:intel_power_well_disable [i915]] disabling power well 2
>[ 4165.600458] [drm:intel_power_well_disable [i915]] disabling DC off
>[ 4165.600507] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[ 4165.600556] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[ 4165.600631] [drm:intel_dp_detect [i915]] [CONNECTOR:57:DP-1]
>[ 4165.600679] [drm:intel_power_well_enable [i915]] enabling DC off
>[ 4165.600728] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[ 4165.600780] [drm:intel_power_well_enable [i915]] enabling power well 2
>[ 4165.601168] [drm:lspcon_wake_native_aux_ch [i915]] Native AUX CH up, DPCD version: 1.2
>[ 4165.601243] [drm:lspcon_resume [i915]] LSPCON recovering in PCON mode after 0 ms
>[ 4165.601662] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4165.602942] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4165.604236] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4165.605507] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4165.606758] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4165.607596] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[ 4165.607996] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 00 00 04 00 0f 00 04
>[ 4165.608672] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>[ 4165.608686] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000
>[ 4165.608700] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000
>[ 4165.609062] [drm:drm_dp_read_desc [drm_kms_helper]] DP branch: OUI 00-60-ad dev-ID MC2800 HW-rev 2.2 SW-rev 1.70 quirks 0x0000
>[ 4165.609347] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[ 4165.610072] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4165.611306] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4165.612446] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4165.613680] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4165.614949] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4165.616199] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4165.617439] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4165.618673] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4165.619903] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4165.621262] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4165.622624] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4165.623985] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4165.625355] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4165.626715] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4165.628074] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4165.629432] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4165.630780] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4165.632022] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4165.633257] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4165.634491] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4165.635721] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4165.637080] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4165.638440] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4165.639801] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4165.641166] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4165.642523] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4165.643881] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4165.645245] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4165.646596] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4165.647689] [drm:intel_power_well_disable [i915]] disabling power well 2
>[ 4165.647705] [drm:intel_power_well_disable [i915]] disabling DC off
>[ 4165.647719] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[ 4165.647732] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[ 4165.647752] [drm:i915_hotplug_work_func [i915]] [CONNECTOR:57:DP-1] status updated from disconnected to connected
>[ 4165.649201] [drm:drm_mode_addfb2 [drm]] [FB:72]
>[ 4165.649229] [drm:drm_mode_addfb2 [drm]] [FB:74]
>[ 4165.649260] [drm:drm_mode_addfb2 [drm]] [FB:75]
>[ 4165.649837] [drm:drm_mode_addfb2 [drm]] [FB:76]
>[ 4165.653339] [drm:drm_mode_addfb2 [drm]] [FB:77]
>[ 4165.653545] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[ 4165.653554] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[ 4170.927376] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 4170.927459] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 4170.927585] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[ 4170.927661] [drm:intel_power_well_enable [i915]] enabling DC off
>[ 4170.927745] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[ 4170.927801] [drm:intel_power_well_enable [i915]] enabling power well 2
>[ 4171.187824] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 4171.187905] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 4175.836171] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [CRTC:37:pipe A] flip_done timed out
>[ 4176.759777] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 4176.759859] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 4177.019290] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 4177.019372] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 4182.593080] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 4182.593161] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 4182.854749] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 4182.854829] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 4186.076173] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [CONNECTOR:49:eDP-1] flip_done timed out
>[ 4188.429520] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 4188.429601] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 4188.689669] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 4188.689751] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 4194.260595] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 4194.260678] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 4194.522592] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 4194.522673] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 4196.316030] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [PLANE:28:plane 1A] flip_done timed out
>[ 4200.091268] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 4200.091349] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 4200.352250] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 4200.352332] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 4205.929085] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 4205.929167] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 4206.189057] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 4206.189138] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 4206.556180] [drm:drm_atomic_helper_wait_for_flip_done [drm_kms_helper]] *ERROR* [CRTC:37:pipe A] flip_done timed out
>[ 4206.556372] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[ 4206.556528] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006f
>[ 4206.747810] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped
>[ 4206.748126] [IGT] kms_frontbuffer_tracking: starting subtest psr-1p-offscren-pri-shrfb-draw-mmap-wc
>[ 4206.748215] Setting dangerous option enable_fbc - tainting kernel
>[ 4206.748241] Setting dangerous option enable_psr - tainting kernel
>[ 4206.748382] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 00 00 04 00 0f 00 04
>[ 4206.749773] [drm:intel_power_well_disable [i915]] disabling power well 2
>[ 4206.749844] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[ 4206.749890] [drm:intel_power_well_enable [i915]] enabling power well 2
>[ 4206.750366] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 00 00 04 00 0f 00 04
>[ 4206.751750] [drm:intel_power_well_disable [i915]] disabling power well 2
>[ 4209.884125] [drm:edp_panel_vdd_off_sync [i915]] Turning eDP port A VDD off
>[ 4209.884270] [drm:edp_panel_vdd_off_sync [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x00000067
>[ 4209.884326] [drm:intel_power_well_disable [i915]] disabling DC off
>[ 4209.884383] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[ 4209.884436] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[ 4211.763100] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 4211.763181] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 4211.763305] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[ 4211.763370] [drm:intel_power_well_enable [i915]] enabling DC off
>[ 4211.763436] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[ 4211.763495] [drm:intel_power_well_enable [i915]] enabling power well 2
>[ 4212.026090] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 4212.026172] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 4216.796059] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [CRTC:37:pipe A] flip_done timed out
>[ 4217.604457] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 4217.604539] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 4217.865362] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 4217.865444] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 4223.442531] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 4223.442612] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 4223.702395] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 4223.702477] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 4227.036065] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [PLANE:28:plane 1A] flip_done timed out
>[ 4229.273023] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 4229.273104] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 4229.533299] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 4229.533380] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 4235.108648] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 4235.108730] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 4235.368301] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 4235.368382] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 4237.276051] [drm:drm_atomic_helper_wait_for_flip_done [drm_kms_helper]] *ERROR* [CRTC:37:pipe A] flip_done timed out
>[ 4237.276657] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 00 00 04 00 0f 00 04
>[ 4237.278075] [drm:intel_power_well_disable [i915]] disabling power well 2
>[ 4237.278133] [drm:intel_power_well_disable [i915]] disabling DC off
>[ 4237.278184] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[ 4237.278233] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[ 4237.278309] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[ 4237.278356] [drm:intel_power_well_enable [i915]] enabling DC off
>[ 4237.278403] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[ 4237.278455] [drm:intel_power_well_enable [i915]] enabling power well 2
>[ 4237.278950] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 00 00 04 00 0f 00 04
>[ 4237.280397] [drm:intel_power_well_disable [i915]] disabling power well 2
>[ 4237.280443] [drm:intel_power_well_disable [i915]] disabling DC off
>[ 4237.280632] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[ 4237.280679] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[ 4237.280786] [drm:drm_mode_addfb2 [drm]] [FB:71]
>[ 4237.280889] [drm:drm_mode_addfb2 [drm]] [FB:72]
>[ 4237.280995] [drm:drm_mode_addfb2 [drm]] [FB:74]
>[ 4237.281885] [drm:drm_mode_addfb2 [drm]] [FB:75]
>[ 4237.284597] [drm:drm_mode_addfb2 [drm]] [FB:76]
>[ 4237.284710] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[ 4237.284740] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 4237.284753] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[ 4240.940716] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 4240.940797] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 4240.940919] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[ 4240.940985] [drm:intel_power_well_enable [i915]] enabling DC off
>[ 4240.941050] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[ 4240.941108] [drm:intel_power_well_enable [i915]] enabling power well 2
>[ 4241.201009] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 4241.201091] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 4246.771745] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 4246.771826] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 4247.031546] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 4247.031628] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 4247.516167] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [CRTC:37:pipe A] flip_done timed out
>[ 4252.607984] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 4252.608065] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 4252.867980] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 4252.868060] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 4257.756161] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [CONNECTOR:49:eDP-1] flip_done timed out
>[ 4258.442176] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 4258.442258] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 4258.702205] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 4258.702286] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 4264.276337] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 4264.276418] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 4264.536872] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 4264.536953] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 4267.996160] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [PLANE:28:plane 1A] flip_done timed out
>[ 4267.996282] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[ 4267.996439] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006f
>[ 4267.996711] [drm:intel_edp_backlight_off [i915]] 
>[ 4268.204227] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0
>[ 4268.204368] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 4268.215850] [drm:intel_edp_panel_off.part.31 [i915]] Turn eDP port A panel power off
>[ 4268.215980] [drm:intel_edp_panel_off.part.31 [i915]] Wait for panel power off time
>[ 4268.216111] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000003 control 00000060
>[ 4268.268892] [drm:wait_panel_status [i915]] Wait complete
>[ 4268.268956] [drm:intel_power_well_disable [i915]] disabling DDI A/E IO power well
>[ 4268.269038] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 4268.269117] [drm:intel_disable_shared_dpll [i915]] disable DPLL 0 (active 1, on? 1) for crtc 37
>[ 4268.269189] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 0
>[ 4268.269279] [drm:intel_atomic_commit_tail [i915]] [ENCODER:48:DDI A]
>[ 4268.269350] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI B]
>[ 4268.269417] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[ 4268.269483] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[ 4268.269547] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DDI C]
>[ 4268.269610] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST A]
>[ 4268.269672] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST B]
>[ 4268.269733] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI D]
>[ 4268.269793] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[ 4268.269852] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[ 4268.269918] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:49:eDP-1]
>[ 4268.269986] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[ 4268.270051] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[ 4268.270114] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[ 4268.270176] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[ 4268.270253] [drm:intel_atomic_commit_tail [i915]] [CRTC:37:pipe A]
>[ 4268.270361] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[ 4268.270832] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 00 00 04 00 0f 00 04
>[ 4268.272134] [drm:intel_power_well_disable [i915]] disabling power well 2
>[ 4268.272147] [drm:intel_power_well_disable [i915]] disabling DC off
>[ 4268.272171] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[ 4268.272180] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[ 4268.272190] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 4268.272203] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[ 4268.272212] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 4268.272221] [drm:intel_power_well_enable [i915]] enabling DC off
>[ 4268.272579] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[ 4268.272590] [drm:intel_power_well_enable [i915]] enabling power well 2
>[ 4268.272990] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 00 00 04 00 0f 00 04
>[ 4268.273315] [drm:drm_mode_addfb2 [drm]] [FB:77]
>[ 4268.274394] [drm:intel_power_well_disable [i915]] disabling power well 2
>[ 4268.274406] [drm:intel_power_well_disable [i915]] disabling DC off
>[ 4268.274417] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[ 4268.274427] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[ 4268.274439] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 4268.275453] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[ 4268.275460] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[ 4268.275484] [drm:intel_atomic_check [i915]] [CONNECTOR:49:eDP-1] checking for sink bpp constrains
>[ 4268.275500] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 4268.275507] [drm:drm_mode_debug_printmodeline [drm]] Modeline 52:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[ 4268.275523] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 138780KHz
>[ 4268.275542] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24
>[ 4268.275556] [drm:intel_dp_compute_config [i915]] DP link bw required 416340 available 540000
>[ 4268.275569] [drm:intel_dp_compute_config [i915]] PSR disable by flag
>[ 4268.275584] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 4268.275599] [drm:intel_dump_pipe_config [i915]] [CRTC:37:pipe A][modeset]
>[ 4268.275612] [drm:intel_dump_pipe_config [i915]] output_types: EDP (0x100)
>[ 4268.275625] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0
>[ 4268.275639] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 6467616, gmch_n: 8388608, link_m: 269484, link_n: 524288, tu: 64
>[ 4268.275652] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[ 4268.275664] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 4268.275671] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[ 4268.275683] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 4268.275690] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[ 4268.275703] [drm:intel_dump_pipe_config [i915]] crtc timings: 138780 1920 1966 1996 2080 1080 1082 1086 1112, type: 0x48 flags: 0xa
>[ 4268.275716] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 138780
>[ 4268.275728] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[ 4268.275740] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 4268.275752] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 4268.275765] [drm:intel_dump_pipe_config [i915]] dpll_hw_state: ctrl1: 0x3, cfgcr1: 0x0, cfgcr2: 0x0
>[ 4268.275776] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 4268.275789] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 1A] disabled, scaler_id = -1
>[ 4268.275801] [drm:intel_dump_pipe_config [i915]] [PLANE:31:plane 2A] disabled, scaler_id = -1
>[ 4268.275826] [drm:intel_dump_pipe_config [i915]] [PLANE:34:cursor A] disabled, scaler_id = -1
>[ 4268.275847] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 4268.275863] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[ 4268.275885] [drm:intel_find_shared_dpll [i915]] [CRTC:37:pipe A] allocated DPLL 0
>[ 4268.275901] [drm:intel_reference_shared_dpll [i915]] using DPLL 0 for pipe A
>[ 4268.275913] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010
>[ 4268.275928] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[ 4268.275943] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0
>[ 4268.276000] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[ 4268.276611] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 4268.276622] [drm:intel_power_well_enable [i915]] enabling DC off
>[ 4268.276880] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[ 4268.276900] [drm:intel_atomic_commit_tail [i915]] [ENCODER:48:DDI A]
>[ 4268.276915] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI B]
>[ 4268.276929] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[ 4268.276942] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[ 4268.276955] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DDI C]
>[ 4268.276968] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST A]
>[ 4268.276980] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST B]
>[ 4268.276993] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI D]
>[ 4268.277005] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[ 4268.277017] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[ 4268.277030] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[ 4268.277044] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[ 4268.277057] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[ 4268.277070] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[ 4268.277085] [drm:intel_enable_shared_dpll [i915]] enable DPLL 0 (active 1, on? 0) for crtc 37
>[ 4268.277099] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 0
>[ 4268.277119] [drm:edp_panel_on [i915]] Turn eDP port A panel power on
>[ 4268.277145] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle
>[ 4268.892060] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 00000000 control 00000060
>[ 4268.892156] [drm:wait_panel_status [i915]] Wait complete
>[ 4268.892287] [drm:edp_panel_on [i915]] Wait for panel power on
>[ 4268.892410] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 00000063
>[ 4268.924601] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010
>[ 4268.924658] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[ 4268.924714] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1
>[ 4268.924793] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[ 4269.094593] [drm:wait_panel_status [i915]] Wait complete
>[ 4269.094651] [drm:intel_power_well_enable [i915]] enabling DDI A/E IO power well
>[ 4269.094744] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[ 4269.094888] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b
>[ 4269.096097] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 4269.096163] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 4269.096221] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 4269.096278] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 4269.096983] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 4269.097036] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 4269.098036] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 4269.098092] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:49:eDP-1] Link Training Passed at Link Rate = 270000, Lane count = 2
>[ 4269.098726] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 4269.098792] [drm:intel_edp_backlight_on [i915]] 
>[ 4269.098847] [drm:intel_panel_enable_backlight [i915]] pipe A
>[ 4269.098930] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 120000
>[ 4269.103939] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS
>[ 4270.110925] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 4270.111006] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 4270.111130] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[ 4270.111196] [drm:intel_power_well_enable [i915]] enabling power well 2
>[ 4270.373818] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 4270.373900] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 4272.348140] [drm:edp_panel_vdd_off_sync [i915]] Turning eDP port A VDD off
>[ 4272.348286] [drm:edp_panel_vdd_off_sync [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x00000067
>[ 4275.944067] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 4275.944148] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 4276.203929] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 4276.204010] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 4279.260071] [drm:drm_atomic_helper_wait_for_flip_done [drm_kms_helper]] *ERROR* [CRTC:37:pipe A] flip_done timed out
>[ 4279.260193] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:49:eDP-1]
>[ 4279.260276] [drm:intel_atomic_commit_tail [i915]] [CRTC:37:pipe A]
>[ 4279.260372] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[ 4279.260957] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 00 00 04 00 0f 00 04
>[ 4279.262362] [drm:intel_power_well_disable [i915]] disabling power well 2
>[ 4279.262419] [drm:intel_power_well_disable [i915]] disabling DC off
>[ 4279.262470] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[ 4279.262519] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[ 4279.262591] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[ 4279.262640] [drm:intel_power_well_enable [i915]] enabling DC off
>[ 4279.262704] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[ 4279.262750] [drm:intel_power_well_enable [i915]] enabling power well 2
>[ 4279.263226] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 00 00 04 00 0f 00 04
>[ 4279.264517] [drm:intel_power_well_disable [i915]] disabling power well 2
>[ 4279.264542] [drm:intel_power_well_disable [i915]] disabling DC off
>[ 4279.264551] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[ 4279.264560] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[ 4279.298738] [drm:intel_power_well_enable [i915]] enabling DC off
>[ 4279.298752] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[ 4279.298786] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[ 4279.298884] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006f
>[ 4279.499022] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped
>[ 4279.499106] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[ 4279.499200] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 4279.499263] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[ 4281.781613] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 4281.781694] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 4281.781818] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[ 4281.781885] [drm:intel_power_well_enable [i915]] enabling power well 2
>[ 4282.041820] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 4282.041901] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 4282.588148] [drm:edp_panel_vdd_off_sync [i915]] Turning eDP port A VDD off
>[ 4282.588295] [drm:edp_panel_vdd_off_sync [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x00000067
>[ 4287.613349] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 4287.613430] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 4287.873181] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 4287.873263] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 4289.500018] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [CRTC:37:pipe A] flip_done timed out
>[ 4293.441036] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 4293.441117] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 4293.700846] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 4293.700928] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 4299.273531] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 4299.273610] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 4299.534240] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 4299.534322] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 4299.740169] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [CONNECTOR:49:eDP-1] flip_done timed out
>[ 4305.106420] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 4305.106501] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 4305.366671] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 4305.366753] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 4309.980148] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [PLANE:28:plane 1A] flip_done timed out
>[ 4309.980251] [drm:intel_edp_backlight_off [i915]] 
>[ 4310.188226] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0
>[ 4310.188361] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 4310.199542] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[ 4310.199701] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b
>[ 4310.200006] [drm:intel_edp_panel_off.part.31 [i915]] Turn eDP port A panel power off
>[ 4310.200120] [drm:intel_edp_panel_off.part.31 [i915]] Wait for panel power off time
>[ 4310.200254] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000003 control 00000060
>[ 4310.250399] [drm:wait_panel_status [i915]] Wait complete
>[ 4310.250461] [drm:intel_power_well_disable [i915]] disabling DDI A/E IO power well
>[ 4310.250563] [drm:intel_disable_shared_dpll [i915]] disable DPLL 0 (active 1, on? 1) for crtc 37
>[ 4310.250630] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 0
>[ 4310.250712] [drm:intel_atomic_commit_tail [i915]] [ENCODER:48:DDI A]
>[ 4310.250775] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI B]
>[ 4310.250835] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[ 4310.250891] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[ 4310.250947] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DDI C]
>[ 4310.251003] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST A]
>[ 4310.251057] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST B]
>[ 4310.251111] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI D]
>[ 4310.251164] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[ 4310.251217] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[ 4310.251276] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:49:eDP-1]
>[ 4310.251335] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[ 4310.251393] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[ 4310.251449] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[ 4310.251504] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[ 4310.251572] [drm:intel_atomic_commit_tail [i915]] [CRTC:37:pipe A]
>[ 4310.251665] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[ 4310.252146] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 00 00 04 00 0f 00 04
>[ 4310.253539] [drm:intel_power_well_disable [i915]] disabling power well 2
>[ 4310.253591] [drm:intel_power_well_disable [i915]] disabling DC off
>[ 4310.253637] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[ 4310.253681] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[ 4310.254115] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 4310.254179] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[ 4310.254222] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 4310.254264] [drm:intel_power_well_enable [i915]] enabling DC off
>[ 4310.254605] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[ 4310.254651] [drm:intel_power_well_enable [i915]] enabling power well 2
>[ 4310.255134] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 00 00 04 00 0f 00 04
>[ 4310.256382] [drm:drm_mode_addfb2 [drm]] [FB:77]
>[ 4310.256526] [drm:intel_power_well_disable [i915]] disabling power well 2
>[ 4310.256556] [drm:intel_power_well_disable [i915]] disabling DC off
>[ 4310.256566] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[ 4310.256577] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[ 4310.256588] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 4310.257237] [drm:drm_mode_addfb2 [drm]] [FB:78]
>[ 4310.258054] [drm:drm_mode_addfb2 [drm]] [FB:79]
>[ 4310.259175] [drm:drm_mode_addfb2 [drm]] [FB:80]
>[ 4310.260004] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010
>[ 4310.260018] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[ 4310.260031] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0
>[ 4310.260410] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[ 4310.329839] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[ 4310.329846] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[ 4310.329868] [drm:intel_atomic_check [i915]] [CONNECTOR:49:eDP-1] checking for sink bpp constrains
>[ 4310.329882] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 4310.329888] [drm:drm_mode_debug_printmodeline [drm]] Modeline 52:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[ 4310.329902] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 138780KHz
>[ 4310.329918] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24
>[ 4310.329930] [drm:intel_dp_compute_config [i915]] DP link bw required 416340 available 540000
>[ 4310.329942] [drm:intel_dp_compute_config [i915]] PSR disable by flag
>[ 4310.329954] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 4310.329967] [drm:intel_dump_pipe_config [i915]] [CRTC:37:pipe A][modeset]
>[ 4310.329979] [drm:intel_dump_pipe_config [i915]] output_types: EDP (0x100)
>[ 4310.329990] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0
>[ 4310.330002] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 6467616, gmch_n: 8388608, link_m: 269484, link_n: 524288, tu: 64
>[ 4310.330013] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[ 4310.330024] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 4310.330029] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[ 4310.330040] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 4310.330045] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[ 4310.330057] [drm:intel_dump_pipe_config [i915]] crtc timings: 138780 1920 1966 1996 2080 1080 1082 1086 1112, type: 0x48 flags: 0xa
>[ 4310.330067] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 138780
>[ 4310.330078] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[ 4310.330088] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 4310.330099] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 4310.330109] [drm:intel_dump_pipe_config [i915]] dpll_hw_state: ctrl1: 0x3, cfgcr1: 0x0, cfgcr2: 0x0
>[ 4310.330119] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 4310.330130] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 1A] disabled, scaler_id = -1
>[ 4310.330140] [drm:intel_dump_pipe_config [i915]] [PLANE:31:plane 2A] disabled, scaler_id = -1
>[ 4310.330150] [drm:intel_dump_pipe_config [i915]] [PLANE:34:cursor A] disabled, scaler_id = -1
>[ 4310.330163] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 4310.330174] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[ 4310.330189] [drm:intel_find_shared_dpll [i915]] [CRTC:37:pipe A] allocated DPLL 0
>[ 4310.330200] [drm:intel_reference_shared_dpll [i915]] using DPLL 0 for pipe A
>[ 4310.331181] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 4310.331190] [drm:intel_power_well_enable [i915]] enabling DC off
>[ 4310.331464] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[ 4310.331482] [drm:intel_atomic_commit_tail [i915]] [ENCODER:48:DDI A]
>[ 4310.331495] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI B]
>[ 4310.331508] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[ 4310.331521] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[ 4310.331533] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DDI C]
>[ 4310.331563] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST A]
>[ 4310.331576] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST B]
>[ 4310.331587] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI D]
>[ 4310.331599] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[ 4310.331610] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[ 4310.331640] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[ 4310.331669] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[ 4310.331680] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[ 4310.331691] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[ 4310.331705] [drm:intel_enable_shared_dpll [i915]] enable DPLL 0 (active 1, on? 0) for crtc 37
>[ 4310.331716] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 0
>[ 4310.331735] [drm:edp_panel_on [i915]] Turn eDP port A panel power on
>[ 4310.331759] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle
>[ 4310.876172] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 00000000 control 00000060
>[ 4310.876256] [drm:wait_panel_status [i915]] Wait complete
>[ 4310.876386] [drm:edp_panel_on [i915]] Wait for panel power on
>[ 4310.876511] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 00000063
>[ 4310.910006] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010
>[ 4310.910079] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[ 4310.910145] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1
>[ 4310.910249] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[ 4310.946120] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 4310.946192] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 4310.946298] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[ 4310.946358] [drm:intel_power_well_enable [i915]] enabling power well 2
>[ 4311.076653] [drm:wait_panel_status [i915]] Wait complete
>[ 4311.076719] [drm:intel_power_well_enable [i915]] enabling DDI A/E IO power well
>[ 4311.076822] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[ 4311.076985] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b
>[ 4311.078219] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 4311.078294] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 4311.078359] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 4311.078424] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 4311.079154] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 4311.079207] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 4311.080258] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 4311.080321] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:49:eDP-1] Link Training Passed at Link Rate = 270000, Lane count = 2
>[ 4311.080959] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 4311.081049] [drm:intel_edp_backlight_on [i915]] 
>[ 4311.081105] [drm:intel_panel_enable_backlight [i915]] pipe A
>[ 4311.081187] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 120000
>[ 4311.087941] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS
>[ 4311.204172] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 4311.204245] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 4314.331993] [drm:edp_panel_vdd_off_sync [i915]] Turning eDP port A VDD off
>[ 4314.332141] [drm:edp_panel_vdd_off_sync [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x00000067
>[ 4316.774663] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 4316.774743] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 4317.035185] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 4317.035266] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 4321.244068] [drm:drm_atomic_helper_wait_for_flip_done [drm_kms_helper]] *ERROR* [CRTC:37:pipe A] flip_done timed out
>[ 4321.244190] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:49:eDP-1]
>[ 4321.244272] [drm:intel_atomic_commit_tail [i915]] [CRTC:37:pipe A]
>[ 4321.244369] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[ 4321.244955] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 00 00 04 00 0f 00 04
>[ 4321.246358] [drm:intel_power_well_disable [i915]] disabling power well 2
>[ 4321.246408] [drm:intel_power_well_disable [i915]] disabling DC off
>[ 4321.246454] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[ 4321.246497] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[ 4321.246562] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[ 4321.246605] [drm:intel_power_well_enable [i915]] enabling DC off
>[ 4321.246647] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[ 4321.246694] [drm:intel_power_well_enable [i915]] enabling power well 2
>[ 4321.247165] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 00 00 04 00 0f 00 04
>[ 4321.248586] [drm:intel_power_well_disable [i915]] disabling power well 2
>[ 4321.248638] [drm:intel_power_well_disable [i915]] disabling DC off
>[ 4321.248687] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[ 4321.248733] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[ 4321.281198] [drm:intel_power_well_enable [i915]] enabling DC off
>[ 4321.281258] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[ 4321.281355] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[ 4321.281507] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006f
>[ 4321.481261] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped
>[ 4321.481304] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[ 4321.481335] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[ 4322.604751] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 4322.604833] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 4322.604953] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[ 4322.605019] [drm:intel_power_well_enable [i915]] enabling power well 2
>[ 4322.863927] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 4322.864008] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 4324.572248] [drm:edp_panel_vdd_off_sync [i915]] Turning eDP port A VDD off
>[ 4324.572392] [drm:edp_panel_vdd_off_sync [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x00000067
>[ 4328.427967] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 4328.428049] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 4328.688637] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 4328.688718] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 4331.484041] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [CRTC:37:pipe A] flip_done timed out
>[ 4334.250506] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 4334.250588] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 4334.511458] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 4334.511540] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 4340.079996] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 4340.080077] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 4340.338083] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 4340.338164] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 4341.724070] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [CONNECTOR:49:eDP-1] flip_done timed out
>[ 4345.911088] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 4345.911170] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 4346.173120] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 4346.173201] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 4351.743245] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 4351.743326] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 4351.963924] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [PLANE:28:plane 1A] flip_done timed out
>[ 4352.002902] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 4352.002983] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 4357.573686] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 4357.573767] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 4357.834874] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 4357.834955] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 4362.204165] [drm:drm_atomic_helper_wait_for_flip_done [drm_kms_helper]] *ERROR* [CRTC:37:pipe A] flip_done timed out
>[ 4362.204763] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 00 00 04 00 0f 00 04
>[ 4362.206164] [drm:intel_power_well_disable [i915]] disabling power well 2
>[ 4362.206220] [drm:intel_power_well_disable [i915]] disabling DC off
>[ 4362.206286] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[ 4362.206329] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[ 4362.206398] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[ 4362.206441] [drm:intel_power_well_enable [i915]] enabling DC off
>[ 4362.206483] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[ 4362.206530] [drm:intel_power_well_enable [i915]] enabling power well 2
>[ 4362.207002] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 00 00 04 00 0f 00 04
>[ 4362.208414] [drm:intel_power_well_disable [i915]] disabling power well 2
>[ 4362.208466] [drm:intel_power_well_disable [i915]] disabling DC off
>[ 4362.208515] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[ 4362.208561] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[ 4362.247170] [drm:intel_power_well_enable [i915]] enabling DC off
>[ 4362.247229] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[ 4362.247329] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[ 4362.247484] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006f
>[ 4362.447226] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped
>[ 4362.447276] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[ 4362.447307] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[ 4363.394827] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 4363.394908] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 4363.395030] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[ 4363.395097] [drm:intel_power_well_enable [i915]] enabling power well 2
>[ 4363.654521] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 4363.654603] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 4365.532100] [drm:edp_panel_vdd_off_sync [i915]] Turning eDP port A VDD off
>[ 4365.532245] [drm:edp_panel_vdd_off_sync [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x00000067
>[ 4369.225079] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 4369.225159] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 4369.485361] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 4369.485441] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 4372.700136] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [CRTC:37:pipe A] flip_done timed out
>[ 4375.059361] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 4375.059442] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 4375.316856] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 4375.316937] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 4380.881957] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 4380.882039] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 4381.141328] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 4381.141409] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 4382.940051] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [CONNECTOR:49:eDP-1] flip_done timed out
>[ 4386.703965] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 4386.704045] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 4386.964976] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 4386.965057] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 4392.541758] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 4392.541839] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 4392.801461] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 4392.801542] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 4393.179954] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [PLANE:28:plane 1A] flip_done timed out
>[ 4398.379926] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 4398.380008] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 4398.640028] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 4398.640109] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 4403.420168] [drm:drm_atomic_helper_wait_for_flip_done [drm_kms_helper]] *ERROR* [CRTC:37:pipe A] flip_done timed out
>[ 4403.420769] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 00 00 04 00 0f 00 04
>[ 4403.422174] [drm:intel_power_well_disable [i915]] disabling power well 2
>[ 4403.422232] [drm:intel_power_well_disable [i915]] disabling DC off
>[ 4403.422299] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[ 4403.422342] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[ 4403.422410] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[ 4403.422452] [drm:intel_power_well_enable [i915]] enabling DC off
>[ 4403.422494] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[ 4403.422541] [drm:intel_power_well_enable [i915]] enabling power well 2
>[ 4403.423013] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 00 00 04 00 0f 00 04
>[ 4403.424446] [drm:intel_power_well_disable [i915]] disabling power well 2
>[ 4403.424499] [drm:intel_power_well_disable [i915]] disabling DC off
>[ 4403.424547] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[ 4403.424594] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[ 4403.463062] [drm:intel_power_well_enable [i915]] enabling DC off
>[ 4403.463121] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[ 4403.463218] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[ 4403.463369] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006f
>[ 4403.663188] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped
>[ 4403.663238] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[ 4403.663268] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[ 4404.205284] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 4404.205365] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 4404.205487] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[ 4404.205551] [drm:intel_power_well_enable [i915]] enabling power well 2
>[ 4404.466536] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 4404.466618] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 4406.748102] [drm:edp_panel_vdd_off_sync [i915]] Turning eDP port A VDD off
>[ 4406.748248] [drm:edp_panel_vdd_off_sync [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x00000067
>[ 4410.037230] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 4410.037312] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 4410.300133] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 4410.300214] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 4413.916138] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [CRTC:37:pipe A] flip_done timed out
>[ 4415.869549] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 4415.869630] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 4416.129356] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 4416.129438] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 4421.692014] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 4421.692094] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 4421.952102] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 4421.952183] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 4424.156165] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [CONNECTOR:49:eDP-1] flip_done timed out
>[ 4427.518657] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 4427.518739] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 4427.779065] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 4427.779146] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 4433.345877] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 4433.345958] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 4433.608212] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 4433.608293] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 4434.395914] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [PLANE:28:plane 1A] flip_done timed out
>[ 4439.178024] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 4439.178105] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 4439.441085] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 4439.441166] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 4444.636170] [drm:drm_atomic_helper_wait_for_flip_done [drm_kms_helper]] *ERROR* [CRTC:37:pipe A] flip_done timed out
>[ 4444.636768] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 00 00 04 00 0f 00 04
>[ 4444.638178] [drm:intel_power_well_disable [i915]] disabling power well 2
>[ 4444.638235] [drm:intel_power_well_disable [i915]] disabling DC off
>[ 4444.638287] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[ 4444.638336] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[ 4444.638411] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[ 4444.638459] [drm:intel_power_well_enable [i915]] enabling DC off
>[ 4444.638506] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[ 4444.638557] [drm:intel_power_well_enable [i915]] enabling power well 2
>[ 4444.639046] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 00 00 04 00 0f 00 04
>[ 4444.640470] [drm:intel_power_well_disable [i915]] disabling power well 2
>[ 4444.640521] [drm:intel_power_well_disable [i915]] disabling DC off
>[ 4444.640571] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[ 4444.640618] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[ 4444.678867] [drm:intel_power_well_enable [i915]] enabling DC off
>[ 4444.678926] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[ 4444.679022] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[ 4444.679174] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006f
>[ 4444.879144] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped
>[ 4444.879250] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[ 4444.879342] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 4444.879404] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[ 4445.016113] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 4445.016195] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 4445.016316] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[ 4445.016383] [drm:intel_power_well_enable [i915]] enabling power well 2
>[ 4445.279601] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 4445.279682] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 4447.964106] [drm:edp_panel_vdd_off_sync [i915]] Turning eDP port A VDD off
>[ 4447.964251] [drm:edp_panel_vdd_off_sync [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x00000067
>[ 4450.848507] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 4450.848588] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 4451.111455] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 4451.111536] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 4455.132034] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [CRTC:37:pipe A] flip_done timed out
>[ 4456.679421] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 4456.679502] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 4456.940293] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 4456.940374] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 4462.508418] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 4462.508500] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 4462.768528] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 4462.768610] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 4465.372160] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [CONNECTOR:49:eDP-1] flip_done timed out
>[ 4468.333838] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 4468.333919] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 4468.594648] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 4468.594729] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 4474.167059] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 4474.167140] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 4474.426282] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 4474.426362] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 4475.611869] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [PLANE:28:plane 1A] flip_done timed out
>[ 4475.611975] [drm:intel_edp_backlight_off [i915]] 
>[ 4475.820226] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0
>[ 4475.820366] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 4475.828892] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[ 4475.829048] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b
>[ 4475.829320] [drm:intel_edp_panel_off.part.31 [i915]] Turn eDP port A panel power off
>[ 4475.829422] [drm:intel_edp_panel_off.part.31 [i915]] Wait for panel power off time
>[ 4475.829547] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000003 control 00000060
>[ 4475.881943] [drm:wait_panel_status [i915]] Wait complete
>[ 4475.882006] [drm:intel_power_well_disable [i915]] disabling DDI A/E IO power well
>[ 4475.882093] [drm:intel_disable_shared_dpll [i915]] disable DPLL 0 (active 1, on? 1) for crtc 37
>[ 4475.882168] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 0
>[ 4475.882260] [drm:intel_atomic_commit_tail [i915]] [ENCODER:48:DDI A]
>[ 4475.882332] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI B]
>[ 4475.882399] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[ 4475.882465] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[ 4475.882528] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DDI C]
>[ 4475.882589] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST A]
>[ 4475.882650] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST B]
>[ 4475.882711] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI D]
>[ 4475.882770] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[ 4475.882828] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[ 4475.882894] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:49:eDP-1]
>[ 4475.882961] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[ 4475.883026] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[ 4475.883090] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[ 4475.883151] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[ 4475.883228] [drm:intel_atomic_commit_tail [i915]] [CRTC:37:pipe A]
>[ 4475.883352] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[ 4475.883823] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 00 00 04 00 0f 00 04
>[ 4475.885244] [drm:intel_power_well_disable [i915]] disabling power well 2
>[ 4475.885297] [drm:intel_power_well_disable [i915]] disabling DC off
>[ 4475.885343] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[ 4475.885387] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[ 4475.885389] Setting dangerous option enable_psr - tainting kernel
>[ 4475.886316] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 4475.886397] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[ 4475.886440] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 4475.886466] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[ 4475.886507] [drm:intel_power_well_enable [i915]] enabling DC off
>[ 4475.886528] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[ 4475.886612] [drm:intel_atomic_check [i915]] [CONNECTOR:49:eDP-1] checking for sink bpp constrains
>[ 4475.886671] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 4475.886700] [drm:drm_mode_debug_printmodeline [drm]] Modeline 52:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[ 4475.886764] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 138780KHz
>[ 4475.886818] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[ 4475.886876] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24
>[ 4475.886931] [drm:intel_dp_compute_config [i915]] DP link bw required 416340 available 540000
>[ 4475.886992] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 4475.887051] [drm:intel_dump_pipe_config [i915]] [CRTC:37:pipe A][modeset]
>[ 4475.887296] [drm:intel_dump_pipe_config [i915]] output_types: EDP (0x100)
>[ 4475.887305] [drm:intel_power_well_enable [i915]] enabling power well 2
>[ 4475.887317] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0
>[ 4475.887328] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 6467616, gmch_n: 8388608, link_m: 269484, link_n: 524288, tu: 64
>[ 4475.887339] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[ 4475.887350] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 4475.887355] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[ 4475.887366] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 4475.887371] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[ 4475.887382] [drm:intel_dump_pipe_config [i915]] crtc timings: 138780 1920 1966 1996 2080 1080 1082 1086 1112, type: 0x48 flags: 0xa
>[ 4475.887393] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 138780
>[ 4475.887404] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[ 4475.887414] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 4475.887424] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 4475.887435] [drm:intel_dump_pipe_config [i915]] dpll_hw_state: ctrl1: 0x3, cfgcr1: 0x0, cfgcr2: 0x0
>[ 4475.887444] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 4475.887455] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 1A] disabled, scaler_id = -1
>[ 4475.887465] [drm:intel_dump_pipe_config [i915]] [PLANE:31:plane 2A] disabled, scaler_id = -1
>[ 4475.887475] [drm:intel_dump_pipe_config [i915]] [PLANE:34:cursor A] disabled, scaler_id = -1
>[ 4475.887487] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 4475.887499] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[ 4475.887513] [drm:intel_find_shared_dpll [i915]] [CRTC:37:pipe A] allocated DPLL 0
>[ 4475.887525] [drm:intel_reference_shared_dpll [i915]] using DPLL 0 for pipe A
>[ 4475.888972] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010
>[ 4475.889003] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[ 4475.889016] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0
>[ 4475.889117] [drm:intel_atomic_commit_tail [i915]] [ENCODER:48:DDI A]
>[ 4475.889132] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI B]
>[ 4475.889146] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[ 4475.889159] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[ 4475.889171] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DDI C]
>[ 4475.889183] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST A]
>[ 4475.889194] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST B]
>[ 4475.889206] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI D]
>[ 4475.889217] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[ 4475.889228] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[ 4475.889240] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[ 4475.889254] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[ 4475.889266] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[ 4475.889278] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[ 4475.889292] [drm:intel_enable_shared_dpll [i915]] enable DPLL 0 (active 1, on? 0) for crtc 37
>[ 4475.889305] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 0
>[ 4475.889324] [drm:edp_panel_on [i915]] Turn eDP port A panel power on
>[ 4475.889351] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle
>[ 4476.507981] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 00000000 control 00000060
>[ 4476.508048] [drm:wait_panel_status [i915]] Wait complete
>[ 4476.508156] [drm:edp_panel_on [i915]] Wait for panel power on
>[ 4476.508272] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 00000063
>[ 4476.540036] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010
>[ 4476.540107] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[ 4476.540174] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1
>[ 4476.708793] [drm:wait_panel_status [i915]] Wait complete
>[ 4476.708842] [drm:intel_power_well_enable [i915]] enabling DDI A/E IO power well
>[ 4476.708920] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[ 4476.709050] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b
>[ 4476.710254] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 4476.710318] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 4476.710375] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 4476.710431] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 4476.711134] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 4476.711188] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 4476.712214] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 4476.712271] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:49:eDP-1] Link Training Passed at Link Rate = 270000, Lane count = 2
>[ 4476.712909] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 4476.713002] [drm:intel_edp_backlight_on [i915]] 
>[ 4476.713060] [drm:intel_panel_enable_backlight [i915]] pipe A
>[ 4476.713144] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 120000
>[ 4476.720163] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS
>[ 4479.963996] [drm:edp_panel_vdd_off_sync [i915]] Turning eDP port A VDD off
>[ 4479.964142] [drm:edp_panel_vdd_off_sync [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x00000067
>[ 4479.995411] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 4479.995493] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 4480.256226] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 4480.256307] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 4485.834137] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 4485.834218] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 4486.094892] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 4486.094973] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 4486.876063] [drm:drm_atomic_helper_wait_for_flip_done [drm_kms_helper]] *ERROR* [CRTC:37:pipe A] flip_done timed out
>[ 4486.876186] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:49:eDP-1]
>[ 4486.876269] [drm:intel_atomic_commit_tail [i915]] [CRTC:37:pipe A]
>[ 4486.876367] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[ 4486.876954] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 00 00 04 00 0f 00 04
>[ 4486.878356] [drm:intel_power_well_disable [i915]] disabling power well 2
>[ 4486.878412] [drm:intel_power_well_disable [i915]] disabling DC off
>[ 4486.878462] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[ 4486.878511] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[ 4486.878584] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[ 4486.878647] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[ 4486.878696] [drm:intel_power_well_enable [i915]] enabling DC off
>[ 4486.878743] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[ 4486.878795] [drm:intel_power_well_enable [i915]] enabling power well 2
>[ 4486.879272] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 00 00 04 00 0f 00 04
>[ 4486.880679] [drm:intel_power_well_disable [i915]] disabling power well 2
>[ 4486.880732] [drm:intel_power_well_disable [i915]] disabling DC off
>[ 4486.880781] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[ 4486.880828] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[ 4486.913124] [drm:intel_power_well_enable [i915]] enabling DC off
>[ 4486.913177] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[ 4486.913265] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[ 4486.913410] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006f
>[ 4487.113216] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped
>[ 4487.363228] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped
>[ 4487.613214] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped
>[ 4487.863231] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped
>[ 4488.113327] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped
>[ 4491.228149] [drm:edp_panel_vdd_off_sync [i915]] Turning eDP port A VDD off
>[ 4491.228294] [drm:edp_panel_vdd_off_sync [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x00000067
>[ 4491.228352] [drm:intel_power_well_disable [i915]] disabling DC off
>[ 4491.228409] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[ 4491.228461] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[ 4491.666191] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 4491.666273] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 4491.666397] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[ 4491.666463] [drm:intel_power_well_enable [i915]] enabling DC off
>[ 4491.666527] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[ 4491.666585] [drm:intel_power_well_enable [i915]] enabling power well 2
>[ 4491.924573] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 4491.924654] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 4497.496365] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 4497.496446] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 4497.756420] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 4497.756501] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 4498.140059] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [CRTC:37:pipe A] flip_done timed out
>[ 4503.321082] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 4503.321162] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 4503.580372] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 4503.580454] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 4508.379907] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [PLANE:28:plane 1A] flip_done timed out
>[ 4509.156544] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 4509.156625] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 4509.417059] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 4509.417140] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 4514.994734] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 4514.994815] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 4515.255190] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 4515.255272] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 4518.620156] [drm:drm_atomic_helper_wait_for_flip_done [drm_kms_helper]] *ERROR* [CRTC:37:pipe A] flip_done timed out
>[ 4518.620429] [IGT] kms_frontbuffer_tracking: exiting, ret=0
>[ 4518.620499] Setting dangerous option enable_psr - tainting kernel
>[ 4518.620515] Setting dangerous option enable_fbc - tainting kernel
>[ 4518.620766] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 00 00 04 00 0f 00 04
>[ 4518.622353] [drm:intel_power_well_disable [i915]] disabling power well 2
>[ 4518.622410] [drm:intel_power_well_disable [i915]] disabling DC off
>[ 4518.622461] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[ 4518.622510] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[ 4518.622586] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[ 4518.622635] [drm:intel_power_well_enable [i915]] enabling DC off
>[ 4518.622682] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[ 4518.622733] [drm:intel_power_well_enable [i915]] enabling power well 2
>[ 4518.623219] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 00 00 04 00 0f 00 04
>[ 4518.624615] [drm:intel_power_well_disable [i915]] disabling power well 2
>[ 4518.624668] [drm:intel_power_well_disable [i915]] disabling DC off
>[ 4518.624716] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[ 4518.624763] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[ 4520.826117] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 4520.826198] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 4520.826323] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[ 4520.826389] [drm:intel_power_well_enable [i915]] enabling DC off
>[ 4520.826455] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[ 4520.826514] [drm:intel_power_well_enable [i915]] enabling power well 2
>[ 4521.085994] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 4521.086077] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 4526.646210] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 4526.646292] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 4526.908543] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 4526.908624] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 4528.860145] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [CRTC:37:pipe A] flip_done timed out
>[ 4532.478140] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 4532.478221] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 4532.737950] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 4532.738031] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 4538.309503] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 4538.309584] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 4538.567267] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 4538.567348] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 4539.100033] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [CONNECTOR:49:eDP-1] flip_done timed out
>[ 4544.133160] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 4544.133240] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 4544.392924] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 4544.393005] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 4549.340051] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [PLANE:28:plane 1A] flip_done timed out
>[ 4549.340162] [drm:intel_fbc_enable [i915]] reserved 16588800 bytes of contiguous stolen space for FBC, threshold: 1
>[ 4549.340236] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 4549.953787] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 4549.953868] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 4550.215052] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 4550.215134] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 4555.784032] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 4555.784113] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 4556.043722] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 4556.043803] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 4559.580099] [drm:drm_atomic_helper_wait_for_flip_done [drm_kms_helper]] *ERROR* [CRTC:37:pipe A] flip_done timed out
>[ 4559.580164] [drm:drm_fb_helper_hotplug_event.part.30 [drm_kms_helper]] 
>[ 4559.580176] [drm:drm_setup_crtcs [drm_kms_helper]] 
>[ 4559.580192] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:49:eDP-1]
>[ 4559.580280] [drm:intel_dp_detect [i915]] [CONNECTOR:49:eDP-1]
>[ 4559.580360] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>[ 4559.580429] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[ 4559.580495] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[ 4559.580575] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[ 4559.580718] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006f
>[ 4559.581199] [drm:drm_dp_read_desc [drm_kms_helper]] DP sink: OUI 00-1c-f8 dev-ID  HW-rev 0.1 SW-rev 1.22 quirks 0x0000
>[ 4559.581935] [drm:drm_add_edid_modes [drm]] ELD: no CEA Extension found
>[ 4559.581991] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:49:eDP-1] probed modes :
>[ 4559.582020] [drm:drm_mode_debug_printmodeline [drm]] Modeline 50:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[ 4559.582035] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:57:DP-1]
>[ 4559.582514] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 00 00 04 00 0f 00 04
>[ 4559.583952] [drm:intel_power_well_disable [i915]] disabling power well 2
>[ 4559.584032] [drm:intel_dp_detect [i915]] [CONNECTOR:57:DP-1]
>[ 4559.584098] [drm:intel_power_well_enable [i915]] enabling power well 2
>[ 4559.584171] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[ 4559.584608] [drm:lspcon_wake_native_aux_ch [i915]] Native AUX CH up, DPCD version: 1.2
>[ 4559.584695] [drm:lspcon_resume [i915]] LSPCON recovering in PCON mode after 0 ms
>[ 4559.585140] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4559.586401] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4559.587658] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4559.588910] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4559.590168] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4559.591036] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[ 4559.591514] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 00 00 04 00 0f 00 04
>[ 4559.592322] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>[ 4559.592381] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000
>[ 4559.592435] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000
>[ 4559.592838] [drm:drm_dp_read_desc [drm_kms_helper]] DP branch: OUI 00-60-ad dev-ID MC2800 HW-rev 2.2 SW-rev 1.70 quirks 0x0000
>[ 4559.593192] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[ 4559.593966] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4559.595243] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4559.596503] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4559.597752] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4559.599007] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4559.600274] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4559.601528] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4559.602783] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4559.604042] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4559.605421] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4559.606802] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4559.608186] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4559.609568] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4559.610950] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4559.612325] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4559.613704] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4559.615079] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4559.616330] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4559.617586] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4559.618841] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4559.620097] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4559.621476] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4559.622858] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4559.624261] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4559.625640] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4559.627022] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4559.628429] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4559.629834] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4559.631208] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4559.632391] [drm:drm_add_edid_modes [drm]] ELD monitor HP E232
>[ 4559.632417] [drm:drm_add_edid_modes [drm]] HDMI: latency present 0 0, video latency 0 0, audio latency 0 0
>[ 4559.632437] [drm:drm_add_edid_modes [drm]] ELD size 28, SAD count 0
>[ 4559.632457] [drm:drm_add_edid_modes [drm]] HDMI: DVI dual 0, max TMDS clock 170000 kHz
>[ 4559.632733] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:57:DP-1] probed modes :
>[ 4559.632758] [drm:drm_mode_debug_printmodeline [drm]] Modeline 74:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[ 4559.632785] [drm:drm_mode_debug_printmodeline [drm]] Modeline 97:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[ 4559.632811] [drm:drm_mode_debug_printmodeline [drm]] Modeline 76:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[ 4559.632837] [drm:drm_mode_debug_printmodeline [drm]] Modeline 81:"1680x1050" 60 119000 1680 1728 1760 1840 1050 1053 1059 1080 0x40 0x9
>[ 4559.632862] [drm:drm_mode_debug_printmodeline [drm]] Modeline 80:"1600x900" 60 108000 1600 1624 1704 1800 900 901 904 1000 0x40 0x5
>[ 4559.632887] [drm:drm_mode_debug_printmodeline [drm]] Modeline 84:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[ 4559.632909] [drm:drm_mode_debug_printmodeline [drm]] Modeline 82:"1440x900" 60 88750 1440 1488 1520 1600 900 903 909 926 0x40 0x9
>[ 4559.632941] [drm:drm_mode_debug_printmodeline [drm]] Modeline 83:"1280x800" 60 71000 1280 1328 1360 1440 800 803 809 823 0x40 0x9
>[ 4559.632963] [drm:drm_mode_debug_printmodeline [drm]] Modeline 77:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[ 4559.632985] [drm:drm_mode_debug_printmodeline [drm]] Modeline 99:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[ 4559.633007] [drm:drm_mode_debug_printmodeline [drm]] Modeline 78:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[ 4559.633030] [drm:drm_mode_debug_printmodeline [drm]] Modeline 87:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[ 4559.633052] [drm:drm_mode_debug_printmodeline [drm]] Modeline 85:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[ 4559.633074] [drm:drm_mode_debug_printmodeline [drm]] Modeline 95:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[ 4559.633096] [drm:drm_mode_debug_printmodeline [drm]] Modeline 100:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[ 4559.633118] [drm:drm_mode_debug_printmodeline [drm]] Modeline 79:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[ 4559.633143] [drm:drm_mode_debug_printmodeline [drm]] Modeline 101:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[ 4559.633168] [drm:drm_mode_debug_printmodeline [drm]] Modeline 86:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[ 4559.633190] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:61:DP-2]
>[ 4559.633265] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 00 00 04 00 0f 00 04
>[ 4559.634670] [drm:intel_power_well_disable [i915]] disabling power well 2
>[ 4559.634736] [drm:intel_dp_detect [i915]] [CONNECTOR:61:DP-2]
>[ 4559.634790] [drm:intel_power_well_enable [i915]] enabling power well 2
>[ 4559.634855] [drm:intel_power_well_disable [i915]] disabling power well 2
>[ 4559.634873] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:61:DP-2] disconnected
>[ 4559.634885] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:64:HDMI-A-1]
>[ 4559.634946] [drm:intel_hdmi_detect [i915]] [CONNECTOR:64:HDMI-A-1]
>[ 4559.635325] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[ 4559.635380] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[ 4559.635743] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[ 4559.635772] [drm:drm_do_probe_ddc_edid [drm]] drm: skipping non-existent adapter i915 gmbus dpc
>[ 4559.636073] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[ 4559.636125] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[ 4559.636490] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[ 4559.636505] [drm:drm_dp_dual_mode_detect [drm_kms_helper]] DP dual mode HDMI ID:  (err -6)
>[ 4559.636519] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:64:HDMI-A-1] disconnected
>[ 4559.636530] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:67:DP-3]
>[ 4559.636585] [drm:intel_dp_detect [i915]] [CONNECTOR:67:DP-3]
>[ 4559.636633] [drm:intel_power_well_enable [i915]] enabling power well 2
>[ 4559.636695] [drm:intel_power_well_disable [i915]] disabling power well 2
>[ 4559.636711] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:67:DP-3] disconnected
>[ 4559.636723] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:70:HDMI-A-2]
>[ 4559.636776] [drm:intel_hdmi_detect [i915]] [CONNECTOR:70:HDMI-A-2]
>[ 4559.647660] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0050 w(1)
>[ 4559.647729] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK on first message, retry
>[ 4559.658729] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0050 w(1)
>[ 4559.658761] [drm:drm_do_probe_ddc_edid [drm]] drm: skipping non-existent adapter i915 gmbus dpd
>[ 4559.669742] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0040 w(1)
>[ 4559.669811] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK on first message, retry
>[ 4559.680803] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0040 w(1)
>[ 4559.680821] [drm:drm_dp_dual_mode_detect [drm_kms_helper]] DP dual mode HDMI ID:  (err -6)
>[ 4559.680835] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:70:HDMI-A-2] disconnected
>[ 4559.680848] [drm:drm_setup_crtcs [drm_kms_helper]] connector 49 enabled? yes
>[ 4559.680858] [drm:drm_setup_crtcs [drm_kms_helper]] connector 57 enabled? yes
>[ 4559.680867] [drm:drm_setup_crtcs [drm_kms_helper]] connector 61 enabled? no
>[ 4559.680877] [drm:drm_setup_crtcs [drm_kms_helper]] connector 64 enabled? no
>[ 4559.680886] [drm:drm_setup_crtcs [drm_kms_helper]] connector 67 enabled? no
>[ 4559.680895] [drm:drm_setup_crtcs [drm_kms_helper]] connector 70 enabled? no
>[ 4559.680967] [drm:intel_fb_initial_config [i915]] Not using firmware configuration
>[ 4559.680980] [drm:drm_setup_crtcs [drm_kms_helper]] looking for cmdline mode on connector 49
>[ 4559.680990] [drm:drm_setup_crtcs [drm_kms_helper]] looking for preferred mode on connector 49 0
>[ 4559.680999] [drm:drm_setup_crtcs [drm_kms_helper]] found mode 1920x1080
>[ 4559.681008] [drm:drm_setup_crtcs [drm_kms_helper]] looking for cmdline mode on connector 57
>[ 4559.681018] [drm:drm_setup_crtcs [drm_kms_helper]] looking for preferred mode on connector 57 0
>[ 4559.681027] [drm:drm_setup_crtcs [drm_kms_helper]] found mode 1920x1080
>[ 4559.681037] [drm:drm_setup_crtcs [drm_kms_helper]] picking CRTCs for 1920x1080 config
>[ 4559.681053] [drm:drm_setup_crtcs [drm_kms_helper]] desired mode 1920x1080 set on crtc 37 (0,0)
>[ 4559.681065] [drm:drm_setup_crtcs [drm_kms_helper]] desired mode 1920x1080 set on crtc 47 (0,0)
>[ 4559.681168] [drm:intel_atomic_check [i915]] [CONNECTOR:57:DP-1] checking for sink bpp constrains
>[ 4559.681233] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 4559.681300] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 148500KHz
>[ 4559.681365] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 4559.681423] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 648000
>[ 4559.681486] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 4559.681550] [drm:intel_dump_pipe_config [i915]] [CRTC:47:pipe B][modeset]
>[ 4559.681609] [drm:intel_dump_pipe_config [i915]] output_types: DP (0x80)
>[ 4559.681666] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 4559.681723] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5767168, gmch_n: 8388608, link_m: 240298, link_n: 262144, tu: 64
>[ 4559.681778] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[ 4559.681832] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 4559.681861] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[ 4559.681916] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 4559.681944] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[ 4559.682001] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[ 4559.682056] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1080, pixel rate 148500
>[ 4559.682108] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[ 4559.682160] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 4559.682212] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 4559.682264] [drm:intel_dump_pipe_config [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[ 4559.682314] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 4559.682366] [drm:intel_dump_pipe_config [i915]] [PLANE:38:plane 1B] disabled, scaler_id = -1
>[ 4559.682417] [drm:intel_dump_pipe_config [i915]] [PLANE:41:plane 2B] disabled, scaler_id = -1
>[ 4559.682468] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor B] disabled, scaler_id = -1
>[ 4559.682531] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 4559.682588] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[ 4559.682660] [drm:intel_find_shared_dpll [i915]] [CRTC:47:pipe B] allocated DPLL 1
>[ 4559.682719] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[ 4561.614621] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 4561.614703] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 4561.614828] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[ 4561.614893] [drm:intel_power_well_enable [i915]] enabling power well 2
>[ 4561.874151] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 4561.874232] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 4562.652129] [drm:edp_panel_vdd_off_sync [i915]] Turning eDP port A VDD off
>[ 4562.652273] [drm:edp_panel_vdd_off_sync [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x00000067
>[ 4567.441065] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 4567.441146] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 4567.700620] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 4567.700701] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 4569.820150] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [CRTC:37:pipe A] flip_done timed out
>[ 4573.269130] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 4573.269212] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 4573.529595] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 4573.529676] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 4579.104650] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 4579.104731] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 4579.364874] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 4579.364956] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 4580.060160] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [CONNECTOR:49:eDP-1] flip_done timed out
>[ 4584.942577] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 4584.942658] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 4585.204265] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 4585.204346] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 4590.300050] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [PLANE:28:plane 1A] flip_done timed out
>[ 4590.300144] [drm:intel_disable_sagv [i915]] Disabling the SAGV
>[ 4590.300231] [drm:intel_atomic_commit_tail [i915]] [ENCODER:48:DDI A]
>[ 4590.300307] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI B]
>[ 4590.300377] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[ 4590.300444] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[ 4590.300509] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DDI C]
>[ 4590.300572] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST A]
>[ 4590.300634] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST B]
>[ 4590.300695] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI D]
>[ 4590.300755] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[ 4590.300815] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[ 4590.300882] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[ 4590.300950] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[ 4590.301015] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[ 4590.301077] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[ 4590.311413] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 2, on? 0) for crtc 47
>[ 4590.311491] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[ 4590.311652] [drm:intel_power_well_enable [i915]] enabling DDI B IO power well
>[ 4590.312289] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4590.313546] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4590.314803] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4590.316057] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4590.317314] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4590.318194] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[ 4590.319192] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 4590.319259] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 4590.319322] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 4590.319386] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 4590.338095] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 4590.338122] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[ 4590.355954] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 4590.356291] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:57:DP-1] Link Training Passed at Link Rate = 162000, Lane count = 4
>[ 4590.356675] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 4590.356728] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS
>[ 4590.777925] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 4590.778007] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 4591.041163] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 4591.041244] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 4600.540055] [drm:drm_atomic_helper_wait_for_flip_done [drm_kms_helper]] *ERROR* [CRTC:37:pipe A] flip_done timed out
>[ 4600.540193] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:57:DP-1]
>[ 4600.540278] [drm:intel_atomic_commit_tail [i915]] [CRTC:47:pipe B]
>[ 4600.540377] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[ 4600.540978] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 00 00 04 00 0f 00 04
>[ 4600.542467] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[ 4600.542988] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 00 00 04 00 0f 00 04
>[ 4600.599068] [IGT] kms_frontbuffer_tracking: executing
>[ 4600.661863] [drm:drm_mode_addfb2 [drm]] [FB:71]
>[ 4600.661903] [drm:drm_mode_addfb2 [drm]] [FB:91]
>[ 4600.661940] [drm:drm_mode_addfb2 [drm]] [FB:92]
>[ 4600.662638] [drm:drm_mode_addfb2 [drm]] [FB:93]
>[ 4600.669127] [drm:drm_mode_addfb2 [drm]] [FB:94]
>[ 4600.670801] [drm:drm_mode_addfb2 [drm]] [FB:96]
>[ 4600.670905] [drm:drm_mode_addfb2 [drm]] [FB:98]
>[ 4600.670952] [drm:drm_mode_addfb2 [drm]] [FB:102]
>[ 4600.671199] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[ 4600.671213] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[ 4610.780114] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [CRTC:37:pipe A] flip_done timed out
>[ 4621.020161] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [CONNECTOR:49:eDP-1] flip_done timed out
>[ 4631.260033] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [PLANE:28:plane 1A] flip_done timed out
>[ 4641.500149] [drm:drm_atomic_helper_wait_for_flip_done [drm_kms_helper]] *ERROR* [CRTC:37:pipe A] flip_done timed out
>[ 4641.500336] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[ 4641.500494] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006f
>[ 4641.693882] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped
>[ 4641.694130] [IGT] kms_frontbuffer_tracking: starting subtest psr-1p-offscren-pri-shrfb-draw-pwrite
>[ 4641.694207] Setting dangerous option enable_fbc - tainting kernel
>[ 4641.694229] Setting dangerous option enable_psr - tainting kernel
>[ 4644.827963] [drm:edp_panel_vdd_off_sync [i915]] Turning eDP port A VDD off
>[ 4644.828109] [drm:edp_panel_vdd_off_sync [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x00000067
>[ 4651.740031] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [CRTC:37:pipe A] flip_done timed out
>[ 4661.980029] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [PLANE:28:plane 1A] flip_done timed out
>[ 4672.220136] [drm:drm_atomic_helper_wait_for_flip_done [drm_kms_helper]] *ERROR* [CRTC:37:pipe A] flip_done timed out
>[ 4672.224510] [drm:drm_mode_addfb2 [drm]] [FB:71]
>[ 4672.224612] [drm:drm_mode_addfb2 [drm]] [FB:89]
>[ 4672.224717] [drm:drm_mode_addfb2 [drm]] [FB:91]
>[ 4672.225872] [drm:drm_mode_addfb2 [drm]] [FB:92]
>[ 4672.229643] [drm:drm_mode_addfb2 [drm]] [FB:93]
>[ 4672.230479] [drm:drm_mode_addfb2 [drm]] [FB:94]
>[ 4672.230500] [drm:drm_mode_addfb2 [drm]] [FB:96]
>[ 4672.230520] [drm:drm_mode_addfb2 [drm]] [FB:98]
>[ 4672.230635] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[ 4672.230669] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 4672.230684] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[ 4682.459955] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [CRTC:37:pipe A] flip_done timed out
>[ 4692.700142] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [CONNECTOR:49:eDP-1] flip_done timed out
>[ 4702.940139] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [PLANE:28:plane 1A] flip_done timed out
>[ 4702.940263] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[ 4702.940423] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006f
>[ 4702.940697] [drm:intel_edp_backlight_off [i915]] 
>[ 4703.148115] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0
>[ 4703.148254] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 4703.159421] [drm:intel_edp_panel_off.part.31 [i915]] Turn eDP port A panel power off
>[ 4703.159536] [drm:intel_edp_panel_off.part.31 [i915]] Wait for panel power off time
>[ 4703.159670] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000003 control 00000060
>[ 4703.209885] [drm:wait_panel_status [i915]] Wait complete
>[ 4703.209948] [drm:intel_power_well_disable [i915]] disabling DDI A/E IO power well
>[ 4703.210030] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 4703.210110] [drm:intel_disable_shared_dpll [i915]] disable DPLL 0 (active 1, on? 1) for crtc 37
>[ 4703.210182] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 0
>[ 4703.210275] [drm:intel_atomic_commit_tail [i915]] [ENCODER:48:DDI A]
>[ 4703.210346] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI B]
>[ 4703.210412] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[ 4703.210476] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[ 4703.210537] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DDI C]
>[ 4703.210598] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST A]
>[ 4703.210659] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST B]
>[ 4703.210720] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI D]
>[ 4703.210779] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[ 4703.210838] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[ 4703.210905] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:49:eDP-1]
>[ 4703.210971] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[ 4703.211036] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[ 4703.211100] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[ 4703.211162] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[ 4703.219478] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010
>[ 4703.219560] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[ 4703.219636] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0
>[ 4703.219753] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[ 4703.223790] [drm:intel_atomic_commit_tail [i915]] [CRTC:37:pipe A]
>[ 4703.223864] [drm:intel_enable_sagv [i915]] Enabling the SAGV
>[ 4703.223952] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[ 4703.224038] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 4703.224099] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[ 4703.224190] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 4703.241125] [drm:intel_power_well_disable [i915]] disabling DDI B IO power well
>[ 4703.241209] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 2, on? 1) for crtc 47
>[ 4703.241282] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[ 4703.241372] [drm:intel_atomic_commit_tail [i915]] [ENCODER:48:DDI A]
>[ 4703.241437] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI B]
>[ 4703.241501] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[ 4703.241561] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[ 4703.241619] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DDI C]
>[ 4703.241677] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST A]
>[ 4703.241734] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST B]
>[ 4703.241790] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI D]
>[ 4703.241845] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[ 4703.241900] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[ 4703.241963] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:57:DP-1]
>[ 4703.242025] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[ 4703.242086] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[ 4703.242145] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[ 4703.242204] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[ 4703.242262] [drm:intel_power_well_disable [i915]] disabling power well 2
>[ 4703.242333] [drm:intel_atomic_commit_tail [i915]] [CRTC:47:pipe B]
>[ 4703.242388] [drm:intel_power_well_disable [i915]] disabling DC off
>[ 4703.242438] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[ 4703.242487] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[ 4703.242925] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 4703.246993] [drm:drm_mode_addfb2 [drm]] [FB:90]
>[ 4703.248935] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[ 4703.248942] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[ 4703.248963] [drm:intel_atomic_check [i915]] [CONNECTOR:49:eDP-1] checking for sink bpp constrains
>[ 4703.248975] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 4703.248982] [drm:drm_mode_debug_printmodeline [drm]] Modeline 52:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[ 4703.248995] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 138780KHz
>[ 4703.249011] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24
>[ 4703.249022] [drm:intel_dp_compute_config [i915]] DP link bw required 416340 available 540000
>[ 4703.249034] [drm:intel_dp_compute_config [i915]] PSR disable by flag
>[ 4703.249047] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 4703.249059] [drm:intel_dump_pipe_config [i915]] [CRTC:37:pipe A][modeset]
>[ 4703.249071] [drm:intel_dump_pipe_config [i915]] output_types: EDP (0x100)
>[ 4703.249083] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0
>[ 4703.249094] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 6467616, gmch_n: 8388608, link_m: 269484, link_n: 524288, tu: 64
>[ 4703.249105] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[ 4703.249116] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 4703.249121] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[ 4703.249132] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 4703.249137] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[ 4703.249148] [drm:intel_dump_pipe_config [i915]] crtc timings: 138780 1920 1966 1996 2080 1080 1082 1086 1112, type: 0x48 flags: 0xa
>[ 4703.249159] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 138780
>[ 4703.249170] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[ 4703.249180] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 4703.249190] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 4703.249201] [drm:intel_dump_pipe_config [i915]] dpll_hw_state: ctrl1: 0x3, cfgcr1: 0x0, cfgcr2: 0x0
>[ 4703.249210] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 4703.249221] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 1A] disabled, scaler_id = -1
>[ 4703.249231] [drm:intel_dump_pipe_config [i915]] [PLANE:31:plane 2A] disabled, scaler_id = -1
>[ 4703.249241] [drm:intel_dump_pipe_config [i915]] [PLANE:34:cursor A] disabled, scaler_id = -1
>[ 4703.249254] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 4703.249265] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[ 4703.249279] [drm:intel_find_shared_dpll [i915]] [CRTC:37:pipe A] allocated DPLL 0
>[ 4703.249291] [drm:intel_reference_shared_dpll [i915]] using DPLL 0 for pipe A
>[ 4703.249813] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 4703.249823] [drm:intel_power_well_enable [i915]] enabling DC off
>[ 4703.250096] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[ 4703.250114] [drm:intel_atomic_commit_tail [i915]] [ENCODER:48:DDI A]
>[ 4703.250127] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI B]
>[ 4703.250140] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[ 4703.250152] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[ 4703.250165] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DDI C]
>[ 4703.250195] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST A]
>[ 4703.250206] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST B]
>[ 4703.250218] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI D]
>[ 4703.250230] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[ 4703.250242] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[ 4703.250254] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[ 4703.250267] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[ 4703.250296] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[ 4703.250324] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[ 4703.250338] [drm:intel_enable_shared_dpll [i915]] enable DPLL 0 (active 1, on? 0) for crtc 37
>[ 4703.250349] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 0
>[ 4703.250368] [drm:edp_panel_on [i915]] Turn eDP port A panel power on
>[ 4703.250392] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle
>[ 4703.836353] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 00000000 control 00000060
>[ 4703.836459] [drm:wait_panel_status [i915]] Wait complete
>[ 4703.836598] [drm:edp_panel_on [i915]] Wait for panel power on
>[ 4703.836732] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 00000063
>[ 4703.870130] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010
>[ 4703.870212] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[ 4703.870286] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1
>[ 4703.870429] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[ 4704.037019] [drm:wait_panel_status [i915]] Wait complete
>[ 4704.037085] [drm:intel_power_well_enable [i915]] enabling DDI A/E IO power well
>[ 4704.037187] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[ 4704.037339] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b
>[ 4704.038534] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 4704.038597] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 4704.038656] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 4704.038716] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 4704.039426] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 4704.039484] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 4704.040447] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 4704.040473] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:49:eDP-1] Link Training Passed at Link Rate = 270000, Lane count = 2
>[ 4704.040864] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 4704.040886] [drm:intel_edp_backlight_on [i915]] 
>[ 4704.040897] [drm:intel_panel_enable_backlight [i915]] pipe A
>[ 4704.040936] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 120000
>[ 4704.047930] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS
>[ 4707.291987] [drm:edp_panel_vdd_off_sync [i915]] Turning eDP port A VDD off
>[ 4707.292133] [drm:edp_panel_vdd_off_sync [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x00000067
>[ 4714.204147] [drm:drm_atomic_helper_wait_for_flip_done [drm_kms_helper]] *ERROR* [CRTC:37:pipe A] flip_done timed out
>[ 4714.204266] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:49:eDP-1]
>[ 4714.204350] [drm:intel_atomic_commit_tail [i915]] [CRTC:37:pipe A]
>[ 4714.204445] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[ 4714.204509] [drm:intel_power_well_disable [i915]] disabling DC off
>[ 4714.204565] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[ 4714.204617] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[ 4714.241193] [drm:intel_power_well_enable [i915]] enabling DC off
>[ 4714.241252] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[ 4714.241351] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[ 4714.241503] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006f
>[ 4714.441152] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped
>[ 4714.441227] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[ 4714.441316] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 4714.441376] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[ 4717.532226] [drm:edp_panel_vdd_off_sync [i915]] Turning eDP port A VDD off
>[ 4717.532373] [drm:edp_panel_vdd_off_sync [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x00000067
>[ 4717.532430] [drm:intel_power_well_disable [i915]] disabling DC off
>[ 4717.532487] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[ 4717.532540] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[ 4723.977813] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 4723.977893] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 4723.978017] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[ 4723.978083] [drm:intel_power_well_enable [i915]] enabling DC off
>[ 4723.978149] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[ 4723.978207] [drm:intel_power_well_enable [i915]] enabling power well 2
>[ 4724.247230] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 4724.247311] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 4724.444023] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [CRTC:37:pipe A] flip_done timed out
>[ 4729.022198] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 4729.022279] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 4729.291356] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 4729.291438] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 4734.684144] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [CONNECTOR:49:eDP-1] flip_done timed out
>[ 4734.878886] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 4734.878967] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 4735.148037] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 4735.148117] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 4740.721640] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 4740.721721] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 4740.990636] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 4740.990717] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 4744.923896] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [PLANE:28:plane 1A] flip_done timed out
>[ 4744.924002] [drm:intel_edp_backlight_off [i915]] 
>[ 4745.132206] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0
>[ 4745.132341] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 4745.140572] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[ 4745.140729] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b
>[ 4745.141005] [drm:intel_edp_panel_off.part.31 [i915]] Turn eDP port A panel power off
>[ 4745.141108] [drm:intel_edp_panel_off.part.31 [i915]] Wait for panel power off time
>[ 4745.141236] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000003 control 00000060
>[ 4745.194050] [drm:wait_panel_status [i915]] Wait complete
>[ 4745.194114] [drm:intel_power_well_disable [i915]] disabling DDI A/E IO power well
>[ 4745.194200] [drm:intel_disable_shared_dpll [i915]] disable DPLL 0 (active 1, on? 1) for crtc 37
>[ 4745.194275] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 0
>[ 4745.194368] [drm:intel_atomic_commit_tail [i915]] [ENCODER:48:DDI A]
>[ 4745.194437] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI B]
>[ 4745.194503] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[ 4745.194567] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[ 4745.194629] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DDI C]
>[ 4745.194690] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST A]
>[ 4745.194750] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST B]
>[ 4745.194810] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI D]
>[ 4745.194869] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[ 4745.194928] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[ 4745.194994] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:49:eDP-1]
>[ 4745.195060] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[ 4745.195123] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[ 4745.195185] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[ 4745.195246] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[ 4745.195323] [drm:intel_atomic_commit_tail [i915]] [CRTC:37:pipe A]
>[ 4745.195445] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[ 4745.195920] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 00 00 04 00 0f 00 04
>[ 4745.200726] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010
>[ 4745.200807] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[ 4745.200883] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0
>[ 4745.224229] [drm:intel_power_well_disable [i915]] disabling power well 2
>[ 4745.224282] [drm:intel_power_well_disable [i915]] disabling DC off
>[ 4745.224330] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[ 4745.224375] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[ 4745.224808] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 4745.224874] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[ 4745.224936] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[ 4745.224980] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 4745.225021] [drm:intel_power_well_enable [i915]] enabling DC off
>[ 4745.225311] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[ 4745.225357] [drm:intel_power_well_enable [i915]] enabling power well 2
>[ 4745.225835] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 00 00 04 00 0f 00 04
>[ 4745.227214] [drm:intel_power_well_disable [i915]] disabling power well 2
>[ 4745.227261] [drm:intel_power_well_disable [i915]] disabling DC off
>[ 4745.227305] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[ 4745.227347] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[ 4745.227784] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 4745.228975] [drm:drm_mode_addfb2 [drm]] [FB:90]
>[ 4745.232952] [drm:drm_mode_addfb2 [drm]] [FB:102]
>[ 4745.236931] [drm:drm_mode_addfb2 [drm]] [FB:103]
>[ 4745.240918] [drm:drm_mode_addfb2 [drm]] [FB:104]
>[ 4745.333134] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[ 4745.333142] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[ 4745.333168] [drm:intel_atomic_check [i915]] [CONNECTOR:49:eDP-1] checking for sink bpp constrains
>[ 4745.333181] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 4745.333188] [drm:drm_mode_debug_printmodeline [drm]] Modeline 52:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[ 4745.333202] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 138780KHz
>[ 4745.333218] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24
>[ 4745.333229] [drm:intel_dp_compute_config [i915]] DP link bw required 416340 available 540000
>[ 4745.333241] [drm:intel_dp_compute_config [i915]] PSR disable by flag
>[ 4745.333254] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 4745.333266] [drm:intel_dump_pipe_config [i915]] [CRTC:37:pipe A][modeset]
>[ 4745.333278] [drm:intel_dump_pipe_config [i915]] output_types: EDP (0x100)
>[ 4745.333290] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0
>[ 4745.333301] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 6467616, gmch_n: 8388608, link_m: 269484, link_n: 524288, tu: 64
>[ 4745.333312] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[ 4745.333323] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 4745.333329] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[ 4745.333340] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 4745.333345] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[ 4745.333356] [drm:intel_dump_pipe_config [i915]] crtc timings: 138780 1920 1966 1996 2080 1080 1082 1086 1112, type: 0x48 flags: 0xa
>[ 4745.333367] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 138780
>[ 4745.333377] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[ 4745.333388] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 4745.333398] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 4745.333408] [drm:intel_dump_pipe_config [i915]] dpll_hw_state: ctrl1: 0x3, cfgcr1: 0x0, cfgcr2: 0x0
>[ 4745.333419] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 4745.333429] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 1A] disabled, scaler_id = -1
>[ 4745.333439] [drm:intel_dump_pipe_config [i915]] [PLANE:31:plane 2A] disabled, scaler_id = -1
>[ 4745.333449] [drm:intel_dump_pipe_config [i915]] [PLANE:34:cursor A] disabled, scaler_id = -1
>[ 4745.333462] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 4745.333473] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[ 4745.333488] [drm:intel_find_shared_dpll [i915]] [CRTC:37:pipe A] allocated DPLL 0
>[ 4745.333500] [drm:intel_reference_shared_dpll [i915]] using DPLL 0 for pipe A
>[ 4745.334458] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 4745.334467] [drm:intel_power_well_enable [i915]] enabling DC off
>[ 4745.334760] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[ 4745.334796] [drm:intel_atomic_commit_tail [i915]] [ENCODER:48:DDI A]
>[ 4745.334809] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI B]
>[ 4745.334822] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[ 4745.334850] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[ 4745.334862] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DDI C]
>[ 4745.334873] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST A]
>[ 4745.334900] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST B]
>[ 4745.334911] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI D]
>[ 4745.334922] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[ 4745.334932] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[ 4745.334944] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[ 4745.334957] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[ 4745.334968] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[ 4745.334979] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[ 4745.334993] [drm:intel_enable_shared_dpll [i915]] enable DPLL 0 (active 1, on? 0) for crtc 37
>[ 4745.335005] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 0
>[ 4745.335024] [drm:edp_panel_on [i915]] Turn eDP port A panel power on
>[ 4745.335047] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle
>[ 4745.820071] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 00000000 control 00000060
>[ 4745.820170] [drm:wait_panel_status [i915]] Wait complete
>[ 4745.820300] [drm:edp_panel_on [i915]] Wait for panel power on
>[ 4745.820424] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 00000063
>[ 4745.852547] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010
>[ 4745.852609] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[ 4745.852669] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1
>[ 4745.852748] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[ 4746.023133] [drm:wait_panel_status [i915]] Wait complete
>[ 4746.023199] [drm:intel_power_well_enable [i915]] enabling DDI A/E IO power well
>[ 4746.023303] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[ 4746.023452] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b
>[ 4746.024699] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 4746.024764] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 4746.024823] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 4746.024881] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 4746.025586] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 4746.025639] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 4746.026639] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 4746.026694] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:49:eDP-1] Link Training Passed at Link Rate = 270000, Lane count = 2
>[ 4746.027329] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 4746.027394] [drm:intel_edp_backlight_on [i915]] 
>[ 4746.027450] [drm:intel_panel_enable_backlight [i915]] pipe A
>[ 4746.027533] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 120000
>[ 4746.031919] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS
>[ 4746.544071] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 4746.544151] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 4746.544286] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[ 4746.544351] [drm:intel_power_well_enable [i915]] enabling power well 2
>[ 4746.804325] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 4746.804406] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 4749.276239] [drm:edp_panel_vdd_off_sync [i915]] Turning eDP port A VDD off
>[ 4749.276387] [drm:edp_panel_vdd_off_sync [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x00000067
>[ 4752.380080] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 4752.380162] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 4752.640502] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 4752.640583] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 4756.188042] [drm:drm_atomic_helper_wait_for_flip_done [drm_kms_helper]] *ERROR* [CRTC:37:pipe A] flip_done timed out
>[ 4756.188163] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:49:eDP-1]
>[ 4756.188247] [drm:intel_atomic_commit_tail [i915]] [CRTC:37:pipe A]
>[ 4756.188344] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[ 4756.188933] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 00 00 04 00 0f 00 04
>[ 4756.190331] [drm:intel_power_well_disable [i915]] disabling power well 2
>[ 4756.190381] [drm:intel_power_well_disable [i915]] disabling DC off
>[ 4756.190427] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[ 4756.190469] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[ 4756.190534] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[ 4756.190577] [drm:intel_power_well_enable [i915]] enabling DC off
>[ 4756.190619] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[ 4756.190665] [drm:intel_power_well_enable [i915]] enabling power well 2
>[ 4756.191138] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 00 00 04 00 0f 00 04
>[ 4756.192557] [drm:intel_power_well_disable [i915]] disabling power well 2
>[ 4756.192610] [drm:intel_power_well_disable [i915]] disabling DC off
>[ 4756.192658] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[ 4756.192704] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[ 4756.227312] [drm:intel_power_well_enable [i915]] enabling DC off
>[ 4756.227364] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[ 4756.227454] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[ 4756.227600] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006f
>[ 4756.427626] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped
>[ 4756.427675] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[ 4756.427706] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[ 4758.211694] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 4758.211775] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 4758.211895] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[ 4758.211961] [drm:intel_power_well_enable [i915]] enabling power well 2
>[ 4758.472765] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 4758.472847] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 4759.516128] [drm:edp_panel_vdd_off_sync [i915]] Turning eDP port A VDD off
>[ 4759.516272] [drm:edp_panel_vdd_off_sync [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x00000067
>[ 4764.041021] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 4764.041103] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 4764.302086] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 4764.302167] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 4766.684052] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [CRTC:37:pipe A] flip_done timed out
>[ 4769.877370] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 4769.877451] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 4770.135966] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 4770.136046] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 4775.698596] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 4775.698677] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 4775.958788] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 4775.958869] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 4776.924105] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [CONNECTOR:49:eDP-1] flip_done timed out
>[ 4781.530204] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 4781.530285] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 4781.791802] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 4781.791884] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 4787.163999] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [PLANE:28:plane 1A] flip_done timed out
>[ 4787.365380] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 4787.365462] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 4787.626348] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 4787.626429] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 4793.197709] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 4793.197790] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 4793.459391] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 4793.459472] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 4797.404044] [drm:drm_atomic_helper_wait_for_flip_done [drm_kms_helper]] *ERROR* [CRTC:37:pipe A] flip_done timed out
>[ 4797.404646] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 00 00 04 00 0f 00 04
>[ 4797.406047] [drm:intel_power_well_disable [i915]] disabling power well 2
>[ 4797.406103] [drm:intel_power_well_disable [i915]] disabling DC off
>[ 4797.406153] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[ 4797.406202] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[ 4797.406277] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[ 4797.406326] [drm:intel_power_well_enable [i915]] enabling DC off
>[ 4797.406373] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[ 4797.406424] [drm:intel_power_well_enable [i915]] enabling power well 2
>[ 4797.406908] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 00 00 04 00 0f 00 04
>[ 4797.408337] [drm:intel_power_well_disable [i915]] disabling power well 2
>[ 4797.408390] [drm:intel_power_well_disable [i915]] disabling DC off
>[ 4797.408439] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[ 4797.408488] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[ 4797.443491] [drm:intel_power_well_enable [i915]] enabling DC off
>[ 4797.443551] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[ 4797.443650] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[ 4797.443805] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006f
>[ 4797.643557] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped
>[ 4797.643601] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[ 4797.643632] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[ 4799.033336] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 4799.033418] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 4799.033540] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[ 4799.033604] [drm:intel_power_well_enable [i915]] enabling power well 2
>[ 4799.294184] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 4799.294265] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 4800.732079] [drm:edp_panel_vdd_off_sync [i915]] Turning eDP port A VDD off
>[ 4800.732224] [drm:edp_panel_vdd_off_sync [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x00000067
>[ 4804.861745] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 4804.861827] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 4805.123157] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 4805.123239] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 4807.900134] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [CRTC:37:pipe A] flip_done timed out
>[ 4810.698855] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 4810.698935] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 4810.958758] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 4810.958839] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 4816.536427] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 4816.536508] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 4816.796865] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 4816.796947] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 4818.140147] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [CONNECTOR:49:eDP-1] flip_done timed out
>[ 4822.370466] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 4822.370547] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 4822.633629] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 4822.633711] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 4828.208483] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 4828.208565] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 4828.380030] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [PLANE:28:plane 1A] flip_done timed out
>[ 4828.469289] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 4828.469370] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 4834.043857] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 4834.043938] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 4834.303069] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 4834.303151] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 4838.620042] [drm:drm_atomic_helper_wait_for_flip_done [drm_kms_helper]] *ERROR* [CRTC:37:pipe A] flip_done timed out
>[ 4838.620645] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 00 00 04 00 0f 00 04
>[ 4838.622050] [drm:intel_power_well_disable [i915]] disabling power well 2
>[ 4838.622107] [drm:intel_power_well_disable [i915]] disabling DC off
>[ 4838.622157] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[ 4838.622206] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[ 4838.622281] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[ 4838.622329] [drm:intel_power_well_enable [i915]] enabling DC off
>[ 4838.622376] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[ 4838.622427] [drm:intel_power_well_enable [i915]] enabling power well 2
>[ 4838.622910] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 00 00 04 00 0f 00 04
>[ 4838.624326] [drm:intel_power_well_disable [i915]] disabling power well 2
>[ 4838.624379] [drm:intel_power_well_disable [i915]] disabling DC off
>[ 4838.624428] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[ 4838.624477] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[ 4838.659449] [drm:intel_power_well_enable [i915]] enabling DC off
>[ 4838.659508] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[ 4838.659605] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[ 4838.659757] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006f
>[ 4838.859530] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped
>[ 4838.859579] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[ 4838.859610] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[ 4839.866845] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 4839.866926] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 4839.867046] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[ 4839.867110] [drm:intel_power_well_enable [i915]] enabling power well 2
>[ 4840.128780] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 4840.128861] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 4841.948113] [drm:edp_panel_vdd_off_sync [i915]] Turning eDP port A VDD off
>[ 4841.948257] [drm:edp_panel_vdd_off_sync [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x00000067
>[ 4845.705294] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 4845.705376] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 4845.963472] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 4845.963553] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 4849.116133] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [CRTC:37:pipe A] flip_done timed out
>[ 4851.531098] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 4851.531180] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 4851.792167] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 4851.792249] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 4857.363797] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 4857.363879] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 4857.625012] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 4857.625093] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 4859.356044] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [CONNECTOR:49:eDP-1] flip_done timed out
>[ 4863.195450] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 4863.195531] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 4863.456781] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 4863.456862] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 4869.019178] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 4869.019260] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 4869.278153] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 4869.278234] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 4869.596024] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [PLANE:28:plane 1A] flip_done timed out
>[ 4874.847569] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 4874.847651] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 4875.107846] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 4875.107927] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 4879.836029] [drm:drm_atomic_helper_wait_for_flip_done [drm_kms_helper]] *ERROR* [CRTC:37:pipe A] flip_done timed out
>[ 4879.836629] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 00 00 04 00 0f 00 04
>[ 4879.838039] [drm:intel_power_well_disable [i915]] disabling power well 2
>[ 4879.838096] [drm:intel_power_well_disable [i915]] disabling DC off
>[ 4879.838146] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[ 4879.838203] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[ 4879.838218] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[ 4879.838227] [drm:intel_power_well_enable [i915]] enabling DC off
>[ 4879.838236] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[ 4879.838247] [drm:intel_power_well_enable [i915]] enabling power well 2
>[ 4879.838644] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 00 00 04 00 0f 00 04
>[ 4879.839897] [drm:intel_power_well_disable [i915]] disabling power well 2
>[ 4879.839935] [drm:intel_power_well_disable [i915]] disabling DC off
>[ 4879.839945] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[ 4879.839954] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[ 4879.875191] [drm:intel_power_well_enable [i915]] enabling DC off
>[ 4879.875205] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[ 4879.875238] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[ 4879.875334] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006f
>[ 4880.075490] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped
>[ 4880.075623] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[ 4880.075717] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 4880.075779] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[ 4880.680290] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 4880.680371] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 4880.680495] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[ 4880.680561] [drm:intel_power_well_enable [i915]] enabling power well 2
>[ 4880.939171] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 4880.939252] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 4883.164117] [drm:edp_panel_vdd_off_sync [i915]] Turning eDP port A VDD off
>[ 4883.164264] [drm:edp_panel_vdd_off_sync [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x00000067
>[ 4886.509582] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 4886.509664] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 4886.771585] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 4886.771667] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 4890.332037] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [CRTC:37:pipe A] flip_done timed out
>[ 4892.341549] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 4892.341630] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 4892.603431] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 4892.603512] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 4898.175149] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 4898.175230] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 4898.436473] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 4898.436555] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 4900.572039] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [CONNECTOR:49:eDP-1] flip_done timed out
>[ 4904.009685] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 4904.009765] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 4904.273248] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 4904.273329] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 4909.843941] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 4909.844023] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 4910.105336] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 4910.105417] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 4910.812029] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [PLANE:28:plane 1A] flip_done timed out
>[ 4910.812135] [drm:intel_edp_backlight_off [i915]] 
>[ 4911.020110] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0
>[ 4911.020251] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 4911.025721] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[ 4911.025878] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b
>[ 4911.026150] [drm:intel_edp_panel_off.part.31 [i915]] Turn eDP port A panel power off
>[ 4911.026253] [drm:intel_edp_panel_off.part.31 [i915]] Wait for panel power off time
>[ 4911.026378] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000003 control 00000060
>[ 4911.079176] [drm:wait_panel_status [i915]] Wait complete
>[ 4911.079239] [drm:intel_power_well_disable [i915]] disabling DDI A/E IO power well
>[ 4911.079326] [drm:intel_disable_shared_dpll [i915]] disable DPLL 0 (active 1, on? 1) for crtc 37
>[ 4911.079400] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 0
>[ 4911.079492] [drm:intel_atomic_commit_tail [i915]] [ENCODER:48:DDI A]
>[ 4911.079563] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI B]
>[ 4911.079629] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[ 4911.079694] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[ 4911.079757] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DDI C]
>[ 4911.079820] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST A]
>[ 4911.079918] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST B]
>[ 4911.079985] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI D]
>[ 4911.080056] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[ 4911.080119] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[ 4911.080192] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:49:eDP-1]
>[ 4911.080266] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[ 4911.080337] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[ 4911.080405] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[ 4911.080468] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[ 4911.080547] [drm:intel_atomic_commit_tail [i915]] [CRTC:37:pipe A]
>[ 4911.080665] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[ 4911.081123] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 00 00 04 00 0f 00 04
>[ 4911.082528] [drm:intel_power_well_disable [i915]] disabling power well 2
>[ 4911.082580] [drm:intel_power_well_disable [i915]] disabling DC off
>[ 4911.082625] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[ 4911.082670] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[ 4911.082672] Setting dangerous option enable_psr - tainting kernel
>[ 4911.083601] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 4911.083681] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[ 4911.083724] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 4911.083751] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[ 4911.083793] [drm:intel_power_well_enable [i915]] enabling DC off
>[ 4911.083815] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[ 4911.083936] [drm:intel_atomic_check [i915]] [CONNECTOR:49:eDP-1] checking for sink bpp constrains
>[ 4911.084010] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 4911.084047] [drm:drm_mode_debug_printmodeline [drm]] Modeline 52:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[ 4911.084118] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 138780KHz
>[ 4911.084162] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[ 4911.084210] [drm:intel_power_well_enable [i915]] enabling power well 2
>[ 4911.084286] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24
>[ 4911.084299] [drm:intel_dp_compute_config [i915]] DP link bw required 416340 available 540000
>[ 4911.084333] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 4911.084347] [drm:intel_dump_pipe_config [i915]] [CRTC:37:pipe A][modeset]
>[ 4911.084360] [drm:intel_dump_pipe_config [i915]] output_types: EDP (0x100)
>[ 4911.084375] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0
>[ 4911.084388] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 6467616, gmch_n: 8388608, link_m: 269484, link_n: 524288, tu: 64
>[ 4911.084400] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[ 4911.084428] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 4911.084452] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[ 4911.084463] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 4911.084469] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[ 4911.084481] [drm:intel_dump_pipe_config [i915]] crtc timings: 138780 1920 1966 1996 2080 1080 1082 1086 1112, type: 0x48 flags: 0xa
>[ 4911.084492] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 138780
>[ 4911.084503] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[ 4911.084514] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 4911.084525] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 4911.084535] [drm:intel_dump_pipe_config [i915]] dpll_hw_state: ctrl1: 0x3, cfgcr1: 0x0, cfgcr2: 0x0
>[ 4911.084546] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 4911.084557] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 1A] disabled, scaler_id = -1
>[ 4911.084568] [drm:intel_dump_pipe_config [i915]] [PLANE:31:plane 2A] disabled, scaler_id = -1
>[ 4911.084578] [drm:intel_dump_pipe_config [i915]] [PLANE:34:cursor A] disabled, scaler_id = -1
>[ 4911.084591] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 4911.084603] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[ 4911.084618] [drm:intel_find_shared_dpll [i915]] [CRTC:37:pipe A] allocated DPLL 0
>[ 4911.084631] [drm:intel_reference_shared_dpll [i915]] using DPLL 0 for pipe A
>[ 4911.085836] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010
>[ 4911.085849] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[ 4911.085861] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0
>[ 4911.086671] [drm:intel_atomic_commit_tail [i915]] [ENCODER:48:DDI A]
>[ 4911.086684] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI B]
>[ 4911.086696] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[ 4911.086710] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[ 4911.086723] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DDI C]
>[ 4911.086736] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST A]
>[ 4911.086749] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST B]
>[ 4911.086762] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI D]
>[ 4911.086774] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[ 4911.086786] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[ 4911.086800] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[ 4911.086814] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[ 4911.086828] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[ 4911.086842] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[ 4911.086857] [drm:intel_enable_shared_dpll [i915]] enable DPLL 0 (active 1, on? 0) for crtc 37
>[ 4911.086869] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 0
>[ 4911.086890] [drm:edp_panel_on [i915]] Turn eDP port A panel power on
>[ 4911.086917] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle
>[ 4911.708223] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 00000000 control 00000060
>[ 4911.708321] [drm:wait_panel_status [i915]] Wait complete
>[ 4911.708452] [drm:edp_panel_on [i915]] Wait for panel power on
>[ 4911.708576] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 00000063
>[ 4911.742272] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010
>[ 4911.742345] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[ 4911.742411] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1
>[ 4911.909278] [drm:wait_panel_status [i915]] Wait complete
>[ 4911.909344] [drm:intel_power_well_enable [i915]] enabling DDI A/E IO power well
>[ 4911.909447] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[ 4911.909599] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b
>[ 4911.910795] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 4911.910858] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 4911.910918] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 4911.910978] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 4911.911690] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 4911.911748] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 4911.912732] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 4911.912758] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:49:eDP-1] Link Training Passed at Link Rate = 270000, Lane count = 2
>[ 4911.913149] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 4911.913170] [drm:intel_edp_backlight_on [i915]] 
>[ 4911.913182] [drm:intel_panel_enable_backlight [i915]] pipe A
>[ 4911.913221] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 120000
>[ 4911.924076] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS
>[ 4915.163973] [drm:edp_panel_vdd_off_sync [i915]] Turning eDP port A VDD off
>[ 4915.164120] [drm:edp_panel_vdd_off_sync [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x00000067
>[ 4915.680127] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 4915.680208] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 4915.941422] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 4915.941503] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 4921.502089] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 4921.502171] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 4921.762558] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 4921.762639] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 4922.076038] [drm:drm_atomic_helper_wait_for_flip_done [drm_kms_helper]] *ERROR* [CRTC:37:pipe A] flip_done timed out
>[ 4922.076162] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:49:eDP-1]
>[ 4922.076245] [drm:intel_atomic_commit_tail [i915]] [CRTC:37:pipe A]
>[ 4922.076343] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[ 4922.076927] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 00 00 04 00 0f 00 04
>[ 4922.078324] [drm:intel_power_well_disable [i915]] disabling power well 2
>[ 4922.078375] [drm:intel_power_well_disable [i915]] disabling DC off
>[ 4922.078421] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[ 4922.078464] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[ 4922.078530] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[ 4922.078587] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[ 4922.078630] [drm:intel_power_well_enable [i915]] enabling DC off
>[ 4922.078673] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[ 4922.078719] [drm:intel_power_well_enable [i915]] enabling power well 2
>[ 4922.079188] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 00 00 04 00 0f 00 04
>[ 4922.080593] [drm:intel_power_well_disable [i915]] disabling power well 2
>[ 4922.080640] [drm:intel_power_well_disable [i915]] disabling DC off
>[ 4922.080684] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[ 4922.080726] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[ 4922.113136] [drm:intel_power_well_enable [i915]] enabling DC off
>[ 4922.113188] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[ 4922.113275] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[ 4922.113421] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006f
>[ 4922.313450] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped
>[ 4922.613454] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped
>[ 4922.963431] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped
>[ 4923.296766] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped
>[ 4923.646751] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped
>[ 4926.684110] [drm:edp_panel_vdd_off_sync [i915]] Turning eDP port A VDD off
>[ 4926.684256] [drm:edp_panel_vdd_off_sync [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x00000067
>[ 4926.684314] [drm:intel_power_well_disable [i915]] disabling DC off
>[ 4926.684370] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[ 4926.684424] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[ 4927.331736] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 4927.331817] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 4927.331943] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[ 4927.332009] [drm:intel_power_well_enable [i915]] enabling DC off
>[ 4927.332074] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[ 4927.332133] [drm:intel_power_well_enable [i915]] enabling power well 2
>[ 4927.591743] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 4927.591826] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 4933.163904] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 4933.163985] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 4933.424620] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 4933.424701] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 4933.852118] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [CRTC:37:pipe A] flip_done timed out
>[ 4939.003140] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 4939.003221] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 4939.263848] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 4939.263929] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 4944.092039] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [PLANE:28:plane 1A] flip_done timed out
>[ 4944.832079] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 4944.832151] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 4945.094415] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 4945.094496] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 4950.662354] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 4950.662436] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 4950.923207] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 4950.923288] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 4954.331993] [drm:drm_atomic_helper_wait_for_flip_done [drm_kms_helper]] *ERROR* [CRTC:37:pipe A] flip_done timed out
>[ 4954.332272] [IGT] kms_frontbuffer_tracking: exiting, ret=0
>[ 4954.332342] Setting dangerous option enable_psr - tainting kernel
>[ 4954.332357] Setting dangerous option enable_fbc - tainting kernel
>[ 4954.332606] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 00 00 04 00 0f 00 04
>[ 4954.334161] [drm:intel_power_well_disable [i915]] disabling power well 2
>[ 4954.334219] [drm:intel_power_well_disable [i915]] disabling DC off
>[ 4954.334270] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[ 4954.334320] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[ 4954.334395] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[ 4954.334443] [drm:intel_power_well_enable [i915]] enabling DC off
>[ 4954.334491] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[ 4954.334543] [drm:intel_power_well_enable [i915]] enabling power well 2
>[ 4954.335027] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 00 00 04 00 0f 00 04
>[ 4954.336432] [drm:intel_power_well_disable [i915]] disabling power well 2
>[ 4954.336485] [drm:intel_power_well_disable [i915]] disabling DC off
>[ 4954.336534] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[ 4954.336582] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[ 4954.379919] [drm:intel_atomic_check [i915]] [CONNECTOR:57:DP-1] checking for sink bpp constrains
>[ 4954.379935] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 4954.379951] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 148500KHz
>[ 4954.379966] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 4954.379980] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 648000
>[ 4954.379995] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 4954.380010] [drm:intel_dump_pipe_config [i915]] [CRTC:47:pipe B][modeset]
>[ 4954.380024] [drm:intel_dump_pipe_config [i915]] output_types: DP (0x80)
>[ 4954.380037] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 4954.380051] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5767168, gmch_n: 8388608, link_m: 240298, link_n: 262144, tu: 64
>[ 4954.380064] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[ 4954.380076] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 4954.380084] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[ 4954.380097] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 4954.380103] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[ 4954.380116] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[ 4954.380129] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1080, pixel rate 148500
>[ 4954.380141] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[ 4954.380153] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 4954.380165] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 4954.380178] [drm:intel_dump_pipe_config [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[ 4954.380189] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 4954.380201] [drm:intel_dump_pipe_config [i915]] [PLANE:38:plane 1B] disabled, scaler_id = -1
>[ 4954.380213] [drm:intel_dump_pipe_config [i915]] [PLANE:41:plane 2B] disabled, scaler_id = -1
>[ 4954.380225] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor B] disabled, scaler_id = -1
>[ 4954.380240] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 4954.380253] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[ 4954.380270] [drm:intel_find_shared_dpll [i915]] [CRTC:47:pipe B] allocated DPLL 1
>[ 4954.380284] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[ 4956.486976] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 4956.487058] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 4956.487181] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[ 4956.487246] [drm:intel_power_well_enable [i915]] enabling DC off
>[ 4956.487311] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[ 4956.487373] [drm:intel_power_well_enable [i915]] enabling power well 2
>[ 4956.748634] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 4956.748717] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 4962.320925] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 4962.321006] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 4962.582710] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 4962.582791] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 4964.572125] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [CRTC:37:pipe A] flip_done timed out
>[ 4968.157813] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 4968.157894] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 4968.417890] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 4968.417971] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 4973.995859] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 4973.995941] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 4974.255386] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 4974.255468] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 4974.812127] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [CONNECTOR:49:eDP-1] flip_done timed out
>[ 4979.830969] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 4979.831050] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 4980.093252] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 4980.093334] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 4985.052123] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [PLANE:28:plane 1A] flip_done timed out
>[ 4985.052215] [drm:intel_disable_sagv [i915]] Disabling the SAGV
>[ 4985.052302] [drm:intel_atomic_commit_tail [i915]] [ENCODER:48:DDI A]
>[ 4985.052376] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI B]
>[ 4985.052445] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[ 4985.052510] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[ 4985.052571] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DDI C]
>[ 4985.052632] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST A]
>[ 4985.052692] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST B]
>[ 4985.052750] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI D]
>[ 4985.052810] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[ 4985.052869] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[ 4985.052936] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[ 4985.053005] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[ 4985.053069] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[ 4985.053131] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[ 4985.053207] [drm:intel_fbc_enable [i915]] reserved 16588800 bytes of contiguous stolen space for FBC, threshold: 1
>[ 4985.053273] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 4985.062336] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 2, on? 0) for crtc 47
>[ 4985.062415] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[ 4985.062531] [drm:intel_power_well_enable [i915]] enabling DDI B IO power well
>[ 4985.063147] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4985.064434] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4985.065694] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4985.066948] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4985.068233] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 4985.069115] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[ 4985.070114] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 4985.070182] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 4985.070244] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 4985.070306] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 4985.088994] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 4985.089009] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[ 4985.106835] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 4985.107172] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:57:DP-1] Link Training Passed at Link Rate = 162000, Lane count = 4
>[ 4985.107542] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 4985.107558] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS
>[ 4985.666987] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 4985.667068] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 4985.930239] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 4985.930321] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 4995.292015] [drm:drm_atomic_helper_wait_for_flip_done [drm_kms_helper]] *ERROR* [CRTC:37:pipe A] flip_done timed out
>[ 4995.292148] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:57:DP-1]
>[ 4995.292231] [drm:intel_atomic_commit_tail [i915]] [CRTC:47:pipe B]
>[ 4995.292330] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[ 4995.292931] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 00 00 04 00 0f 00 04
>[ 4995.294417] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[ 4995.294936] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 00 00 04 00 0f 00 04
>[ 4995.350737] [IGT] kms_frontbuffer_tracking: executing
>[ 4995.435274] [drm:drm_mode_addfb2 [drm]] [FB:90]
>[ 4995.435342] [drm:drm_mode_addfb2 [drm]] [FB:91]
>[ 4995.435410] [drm:drm_mode_addfb2 [drm]] [FB:92]
>[ 4995.436807] [drm:drm_mode_addfb2 [drm]] [FB:93]
>[ 4995.452116] [drm:drm_mode_addfb2 [drm]] [FB:94]
>[ 4995.455867] [drm:drm_mode_addfb2 [drm]] [FB:96]
>[ 4995.455954] [drm:drm_mode_addfb2 [drm]] [FB:98]
>[ 4995.456050] [drm:drm_mode_addfb2 [drm]] [FB:102]
>[ 4995.456454] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[ 4995.456481] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[ 5005.532118] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [CRTC:37:pipe A] flip_done timed out
>[ 5015.772133] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [CONNECTOR:49:eDP-1] flip_done timed out
>[ 5026.012045] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [PLANE:28:plane 1A] flip_done timed out
>[ 5036.252134] [drm:drm_atomic_helper_wait_for_flip_done [drm_kms_helper]] *ERROR* [CRTC:37:pipe A] flip_done timed out
>[ 5036.252322] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[ 5036.252478] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006f
>[ 5036.444803] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped
>[ 5036.445050] [IGT] kms_frontbuffer_tracking: starting subtest psr-1p-offscren-pri-shrfb-draw-render
>[ 5036.445128] Setting dangerous option enable_fbc - tainting kernel
>[ 5036.445149] Setting dangerous option enable_psr - tainting kernel
>[ 5039.580075] [drm:edp_panel_vdd_off_sync [i915]] Turning eDP port A VDD off
>[ 5039.580221] [drm:edp_panel_vdd_off_sync [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x00000067
>[ 5046.492037] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [CRTC:37:pipe A] flip_done timed out
>[ 5056.732014] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [PLANE:28:plane 1A] flip_done timed out
>[ 5066.972026] [drm:drm_atomic_helper_wait_for_flip_done [drm_kms_helper]] *ERROR* [CRTC:37:pipe A] flip_done timed out
>[ 5066.976410] [drm:drm_mode_addfb2 [drm]] [FB:71]
>[ 5066.976510] [drm:drm_mode_addfb2 [drm]] [FB:90]
>[ 5066.976616] [drm:drm_mode_addfb2 [drm]] [FB:91]
>[ 5066.977738] [drm:drm_mode_addfb2 [drm]] [FB:92]
>[ 5066.981496] [drm:drm_mode_addfb2 [drm]] [FB:93]
>[ 5066.982337] [drm:drm_mode_addfb2 [drm]] [FB:94]
>[ 5066.982356] [drm:drm_mode_addfb2 [drm]] [FB:96]
>[ 5066.982376] [drm:drm_mode_addfb2 [drm]] [FB:98]
>[ 5066.982489] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[ 5066.982523] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 5066.982538] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[ 5077.212064] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [CRTC:37:pipe A] flip_done timed out
>[ 5087.452121] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [CONNECTOR:49:eDP-1] flip_done timed out
>[ 5097.692118] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [PLANE:28:plane 1A] flip_done timed out
>[ 5097.692246] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[ 5097.692400] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006f
>[ 5097.692682] [drm:intel_edp_backlight_off [i915]] 
>[ 5097.900094] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0
>[ 5097.900233] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 5097.911417] [drm:intel_edp_panel_off.part.31 [i915]] Turn eDP port A panel power off
>[ 5097.911529] [drm:intel_edp_panel_off.part.31 [i915]] Wait for panel power off time
>[ 5097.911661] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000003 control 00000060
>[ 5097.964389] [drm:wait_panel_status [i915]] Wait complete
>[ 5097.964452] [drm:intel_power_well_disable [i915]] disabling DDI A/E IO power well
>[ 5097.964534] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 5097.964614] [drm:intel_disable_shared_dpll [i915]] disable DPLL 0 (active 1, on? 1) for crtc 37
>[ 5097.964686] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 0
>[ 5097.964780] [drm:intel_atomic_commit_tail [i915]] [ENCODER:48:DDI A]
>[ 5097.964852] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI B]
>[ 5097.964919] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[ 5097.964984] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[ 5097.965047] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DDI C]
>[ 5097.965109] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST A]
>[ 5097.965170] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST B]
>[ 5097.965230] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI D]
>[ 5097.965290] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[ 5097.965350] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[ 5097.965415] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:49:eDP-1]
>[ 5097.965481] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[ 5097.965545] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[ 5097.965608] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[ 5097.965669] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[ 5097.971364] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010
>[ 5097.971446] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[ 5097.971520] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0
>[ 5097.971637] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[ 5097.974832] [drm:intel_atomic_commit_tail [i915]] [CRTC:37:pipe A]
>[ 5097.974902] [drm:intel_enable_sagv [i915]] Enabling the SAGV
>[ 5097.975000] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[ 5097.975101] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 5097.975172] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[ 5097.975275] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 5097.992110] [drm:intel_power_well_disable [i915]] disabling DDI B IO power well
>[ 5097.992194] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 2, on? 1) for crtc 47
>[ 5097.992267] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[ 5097.992357] [drm:intel_atomic_commit_tail [i915]] [ENCODER:48:DDI A]
>[ 5097.992424] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI B]
>[ 5097.992488] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[ 5097.992549] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[ 5097.992608] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DDI C]
>[ 5097.992666] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST A]
>[ 5097.992722] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST B]
>[ 5097.992777] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI D]
>[ 5097.992832] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[ 5097.992888] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[ 5097.992949] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:57:DP-1]
>[ 5097.993010] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[ 5097.993071] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[ 5097.993129] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[ 5097.993188] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[ 5097.993246] [drm:intel_power_well_disable [i915]] disabling power well 2
>[ 5097.993319] [drm:intel_atomic_commit_tail [i915]] [CRTC:47:pipe B]
>[ 5097.993373] [drm:intel_power_well_disable [i915]] disabling DC off
>[ 5097.993425] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[ 5097.993474] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[ 5097.993913] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 5097.996389] [drm:drm_mode_addfb2 [drm]] [FB:89]
>[ 5097.998127] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[ 5097.998134] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[ 5097.998155] [drm:intel_atomic_check [i915]] [CONNECTOR:49:eDP-1] checking for sink bpp constrains
>[ 5097.998167] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 5097.998173] [drm:drm_mode_debug_printmodeline [drm]] Modeline 52:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[ 5097.998187] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 138780KHz
>[ 5097.998203] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24
>[ 5097.998215] [drm:intel_dp_compute_config [i915]] DP link bw required 416340 available 540000
>[ 5097.998227] [drm:intel_dp_compute_config [i915]] PSR disable by flag
>[ 5097.998239] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 5097.998252] [drm:intel_dump_pipe_config [i915]] [CRTC:37:pipe A][modeset]
>[ 5097.998263] [drm:intel_dump_pipe_config [i915]] output_types: EDP (0x100)
>[ 5097.998275] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0
>[ 5097.998286] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 6467616, gmch_n: 8388608, link_m: 269484, link_n: 524288, tu: 64
>[ 5097.998297] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[ 5097.998308] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 5097.998313] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[ 5097.998324] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 5097.998329] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[ 5097.998341] [drm:intel_dump_pipe_config [i915]] crtc timings: 138780 1920 1966 1996 2080 1080 1082 1086 1112, type: 0x48 flags: 0xa
>[ 5097.998352] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 138780
>[ 5097.998362] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[ 5097.998373] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 5097.998383] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 5097.998394] [drm:intel_dump_pipe_config [i915]] dpll_hw_state: ctrl1: 0x3, cfgcr1: 0x0, cfgcr2: 0x0
>[ 5097.998404] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 5097.998414] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 1A] disabled, scaler_id = -1
>[ 5097.998425] [drm:intel_dump_pipe_config [i915]] [PLANE:31:plane 2A] disabled, scaler_id = -1
>[ 5097.998435] [drm:intel_dump_pipe_config [i915]] [PLANE:34:cursor A] disabled, scaler_id = -1
>[ 5097.998448] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 5097.998459] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[ 5097.998473] [drm:intel_find_shared_dpll [i915]] [CRTC:37:pipe A] allocated DPLL 0
>[ 5097.998484] [drm:intel_reference_shared_dpll [i915]] using DPLL 0 for pipe A
>[ 5097.998997] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 5097.999007] [drm:intel_power_well_enable [i915]] enabling DC off
>[ 5097.999281] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[ 5097.999298] [drm:intel_atomic_commit_tail [i915]] [ENCODER:48:DDI A]
>[ 5097.999311] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI B]
>[ 5097.999324] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[ 5097.999337] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[ 5097.999350] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DDI C]
>[ 5097.999379] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST A]
>[ 5097.999391] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST B]
>[ 5097.999402] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI D]
>[ 5097.999415] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[ 5097.999426] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[ 5097.999439] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[ 5097.999486] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[ 5097.999497] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[ 5097.999509] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[ 5097.999522] [drm:intel_enable_shared_dpll [i915]] enable DPLL 0 (active 1, on? 0) for crtc 37
>[ 5097.999534] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 0
>[ 5097.999553] [drm:edp_panel_on [i915]] Turn eDP port A panel power on
>[ 5097.999577] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle
>[ 5098.588290] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 00000000 control 00000060
>[ 5098.588398] [drm:wait_panel_status [i915]] Wait complete
>[ 5098.588535] [drm:edp_panel_on [i915]] Wait for panel power on
>[ 5098.588663] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 00000063
>[ 5098.622157] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010
>[ 5098.622237] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[ 5098.622312] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1
>[ 5098.622456] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[ 5098.791402] [drm:wait_panel_status [i915]] Wait complete
>[ 5098.791467] [drm:intel_power_well_enable [i915]] enabling DDI A/E IO power well
>[ 5098.791569] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[ 5098.791719] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b
>[ 5098.792963] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 5098.793026] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 5098.793085] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 5098.793144] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 5098.793854] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 5098.793910] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 5098.793965] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 5098.794666] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 5098.794723] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 5098.795728] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 5098.795788] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:49:eDP-1] Link Training Passed at Link Rate = 270000, Lane count = 2
>[ 5098.796461] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 5098.796548] [drm:intel_edp_backlight_on [i915]] 
>[ 5098.796560] [drm:intel_panel_enable_backlight [i915]] pipe A
>[ 5098.796598] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 120000
>[ 5098.796711] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS
>[ 5102.044100] [drm:edp_panel_vdd_off_sync [i915]] Turning eDP port A VDD off
>[ 5102.044245] [drm:edp_panel_vdd_off_sync [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x00000067
>[ 5108.956135] [drm:drm_atomic_helper_wait_for_flip_done [drm_kms_helper]] *ERROR* [CRTC:37:pipe A] flip_done timed out
>[ 5108.956253] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:49:eDP-1]
>[ 5108.956338] [drm:intel_atomic_commit_tail [i915]] [CRTC:37:pipe A]
>[ 5108.956434] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[ 5108.956498] [drm:intel_power_well_disable [i915]] disabling DC off
>[ 5108.956554] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[ 5108.956608] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[ 5108.996616] [drm:intel_power_well_enable [i915]] enabling DC off
>[ 5108.996676] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[ 5108.996774] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[ 5108.996925] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006f
>[ 5109.196769] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped
>[ 5109.196853] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[ 5109.196947] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 5109.197009] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[ 5112.284096] [drm:edp_panel_vdd_off_sync [i915]] Turning eDP port A VDD off
>[ 5112.284240] [drm:edp_panel_vdd_off_sync [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x00000067
>[ 5112.284298] [drm:intel_power_well_disable [i915]] disabling DC off
>[ 5112.284355] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[ 5112.284408] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[ 5118.731644] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 5118.731726] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 5118.731851] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[ 5118.731916] [drm:intel_power_well_enable [i915]] enabling DC off
>[ 5118.731987] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[ 5118.732067] [drm:intel_power_well_enable [i915]] enabling power well 2
>[ 5119.000765] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 5119.000847] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 5119.452123] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [CRTC:37:pipe A] flip_done timed out
>[ 5123.761821] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 5123.761902] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 5124.031135] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 5124.031216] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 5129.604705] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 5129.604786] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 5129.692017] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [CONNECTOR:49:eDP-1] flip_done timed out
>[ 5129.873892] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 5129.873973] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 5135.433487] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 5135.433567] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 5135.716265] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 5135.716346] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 5139.931994] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [PLANE:28:plane 1A] flip_done timed out
>[ 5139.932100] [drm:intel_edp_backlight_off [i915]] 
>[ 5140.140073] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0
>[ 5140.140208] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 5140.145922] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[ 5140.146079] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b
>[ 5140.146350] [drm:intel_edp_panel_off.part.31 [i915]] Turn eDP port A panel power off
>[ 5140.146452] [drm:intel_edp_panel_off.part.31 [i915]] Wait for panel power off time
>[ 5140.146578] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000003 control 00000060
>[ 5140.196735] [drm:wait_panel_status [i915]] Wait complete
>[ 5140.196791] [drm:intel_power_well_disable [i915]] disabling DDI A/E IO power well
>[ 5140.196867] [drm:intel_disable_shared_dpll [i915]] disable DPLL 0 (active 1, on? 1) for crtc 37
>[ 5140.196936] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 0
>[ 5140.197021] [drm:intel_atomic_commit_tail [i915]] [ENCODER:48:DDI A]
>[ 5140.197085] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI B]
>[ 5140.197144] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[ 5140.197202] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[ 5140.197259] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DDI C]
>[ 5140.197314] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST A]
>[ 5140.197368] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST B]
>[ 5140.197422] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI D]
>[ 5140.197475] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[ 5140.197528] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[ 5140.197588] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:49:eDP-1]
>[ 5140.197648] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[ 5140.197707] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[ 5140.197765] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[ 5140.197821] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[ 5140.197890] [drm:intel_atomic_commit_tail [i915]] [CRTC:37:pipe A]
>[ 5140.198001] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[ 5140.198403] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 00 00 04 00 0f 00 04
>[ 5140.199796] [drm:intel_power_well_disable [i915]] disabling power well 2
>[ 5140.199867] [drm:intel_power_well_disable [i915]] disabling DC off
>[ 5140.199922] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[ 5140.199969] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[ 5140.200436] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 5140.200524] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[ 5140.200587] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 5140.200630] [drm:intel_power_well_enable [i915]] enabling DC off
>[ 5140.200920] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[ 5140.200968] [drm:intel_power_well_enable [i915]] enabling power well 2
>[ 5140.203925] [drm:drm_mode_addfb2 [drm]] [FB:89]
>[ 5140.206080] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010
>[ 5140.206152] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[ 5140.206219] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0
>[ 5140.206893] [drm:drm_mode_addfb2 [drm]] [FB:102]
>[ 5140.207875] [drm:drm_mode_addfb2 [drm]] [FB:103]
>[ 5140.208796] [drm:drm_mode_addfb2 [drm]] [FB:104]
>[ 5140.226920] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 00 00 04 00 0f 00 04
>[ 5140.228176] [drm:intel_power_well_disable [i915]] disabling power well 2
>[ 5140.228188] [drm:intel_power_well_disable [i915]] disabling DC off
>[ 5140.228213] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[ 5140.228222] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[ 5140.228232] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 5140.228246] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[ 5140.282593] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[ 5140.282600] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[ 5140.282623] [drm:intel_atomic_check [i915]] [CONNECTOR:49:eDP-1] checking for sink bpp constrains
>[ 5140.282636] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 5140.282643] [drm:drm_mode_debug_printmodeline [drm]] Modeline 52:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[ 5140.282657] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 138780KHz
>[ 5140.282672] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24
>[ 5140.282684] [drm:intel_dp_compute_config [i915]] DP link bw required 416340 available 540000
>[ 5140.282696] [drm:intel_dp_compute_config [i915]] PSR disable by flag
>[ 5140.282708] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 5140.282721] [drm:intel_dump_pipe_config [i915]] [CRTC:37:pipe A][modeset]
>[ 5140.282733] [drm:intel_dump_pipe_config [i915]] output_types: EDP (0x100)
>[ 5140.282744] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0
>[ 5140.282756] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 6467616, gmch_n: 8388608, link_m: 269484, link_n: 524288, tu: 64
>[ 5140.282767] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[ 5140.282777] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 5140.282783] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[ 5140.282794] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 5140.282799] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[ 5140.282811] [drm:intel_dump_pipe_config [i915]] crtc timings: 138780 1920 1966 1996 2080 1080 1082 1086 1112, type: 0x48 flags: 0xa
>[ 5140.282822] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 138780
>[ 5140.282832] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[ 5140.282843] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 5140.282853] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 5140.282863] [drm:intel_dump_pipe_config [i915]] dpll_hw_state: ctrl1: 0x3, cfgcr1: 0x0, cfgcr2: 0x0
>[ 5140.282874] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 5140.282884] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 1A] disabled, scaler_id = -1
>[ 5140.282895] [drm:intel_dump_pipe_config [i915]] [PLANE:31:plane 2A] disabled, scaler_id = -1
>[ 5140.282905] [drm:intel_dump_pipe_config [i915]] [PLANE:34:cursor A] disabled, scaler_id = -1
>[ 5140.282918] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 5140.282929] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[ 5140.282944] [drm:intel_find_shared_dpll [i915]] [CRTC:37:pipe A] allocated DPLL 0
>[ 5140.282956] [drm:intel_reference_shared_dpll [i915]] using DPLL 0 for pipe A
>[ 5140.283978] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 5140.283987] [drm:intel_power_well_enable [i915]] enabling DC off
>[ 5140.284244] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[ 5140.284260] [drm:intel_atomic_commit_tail [i915]] [ENCODER:48:DDI A]
>[ 5140.284272] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI B]
>[ 5140.284284] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[ 5140.284295] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[ 5140.284305] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DDI C]
>[ 5140.284316] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST A]
>[ 5140.284326] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST B]
>[ 5140.284337] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI D]
>[ 5140.284347] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[ 5140.284358] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[ 5140.284369] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[ 5140.284381] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[ 5140.284392] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[ 5140.284403] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[ 5140.284416] [drm:intel_enable_shared_dpll [i915]] enable DPLL 0 (active 1, on? 0) for crtc 37
>[ 5140.284428] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 0
>[ 5140.284447] [drm:edp_panel_on [i915]] Turn eDP port A panel power on
>[ 5140.284472] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle
>[ 5140.828225] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 00000000 control 00000060
>[ 5140.828333] [drm:wait_panel_status [i915]] Wait complete
>[ 5140.828464] [drm:edp_panel_on [i915]] Wait for panel power on
>[ 5140.828589] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 00000063
>[ 5140.862027] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010
>[ 5140.862107] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[ 5140.862182] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1
>[ 5140.862309] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[ 5141.031150] [drm:wait_panel_status [i915]] Wait complete
>[ 5141.031216] [drm:intel_power_well_enable [i915]] enabling DDI A/E IO power well
>[ 5141.031321] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[ 5141.031473] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b
>[ 5141.032709] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 5141.032782] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 5141.032848] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 5141.032913] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 5141.033613] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 5141.033667] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 5141.034665] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 5141.034720] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:49:eDP-1] Link Training Passed at Link Rate = 270000, Lane count = 2
>[ 5141.035355] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 5141.035423] [drm:intel_edp_backlight_on [i915]] 
>[ 5141.035480] [drm:intel_panel_enable_backlight [i915]] pipe A
>[ 5141.035563] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 120000
>[ 5141.039928] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS
>[ 5141.261880] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 5141.261961] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 5141.262085] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[ 5141.262151] [drm:intel_power_well_enable [i915]] enabling power well 2
>[ 5141.523989] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 5141.524070] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 5144.284212] [drm:edp_panel_vdd_off_sync [i915]] Turning eDP port A VDD off
>[ 5144.284357] [drm:edp_panel_vdd_off_sync [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x00000067
>[ 5147.098568] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 5147.098649] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 5147.361006] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 5147.361087] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 5151.196023] [drm:drm_atomic_helper_wait_for_flip_done [drm_kms_helper]] *ERROR* [CRTC:37:pipe A] flip_done timed out
>[ 5151.196147] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:49:eDP-1]
>[ 5151.196230] [drm:intel_atomic_commit_tail [i915]] [CRTC:37:pipe A]
>[ 5151.196327] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[ 5151.196914] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 00 00 04 00 0f 00 04
>[ 5151.198315] [drm:intel_power_well_disable [i915]] disabling power well 2
>[ 5151.198371] [drm:intel_power_well_disable [i915]] disabling DC off
>[ 5151.198421] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[ 5151.198469] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[ 5151.198543] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[ 5151.198591] [drm:intel_power_well_enable [i915]] enabling DC off
>[ 5151.198638] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[ 5151.198690] [drm:intel_power_well_enable [i915]] enabling power well 2
>[ 5151.199177] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 00 00 04 00 0f 00 04
>[ 5151.200630] [drm:intel_power_well_disable [i915]] disabling power well 2
>[ 5151.200682] [drm:intel_power_well_disable [i915]] disabling DC off
>[ 5151.200731] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[ 5151.200779] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[ 5151.235382] [drm:intel_power_well_enable [i915]] enabling DC off
>[ 5151.235435] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[ 5151.235523] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[ 5151.235670] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006f
>[ 5151.435652] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped
>[ 5151.435702] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[ 5151.435733] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[ 5152.937232] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 5152.937314] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 5152.937435] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[ 5152.937500] [drm:intel_power_well_enable [i915]] enabling power well 2
>[ 5153.196161] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 5153.196242] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 5154.524065] [drm:edp_panel_vdd_off_sync [i915]] Turning eDP port A VDD off
>[ 5154.524210] [drm:edp_panel_vdd_off_sync [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x00000067
>[ 5158.771747] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 5158.771827] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 5159.032404] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 5159.032486] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 5161.692124] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [CRTC:37:pipe A] flip_done timed out
>[ 5164.608940] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 5164.609021] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 5164.868743] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 5164.868825] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 5170.432067] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 5170.432149] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 5170.693401] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 5170.693483] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 5171.932129] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [CONNECTOR:49:eDP-1] flip_done timed out
>[ 5176.261784] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 5176.261865] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 5176.521384] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 5176.521464] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 5182.089528] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 5182.089610] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 5182.172019] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [PLANE:28:plane 1A] flip_done timed out
>[ 5182.349943] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 5182.350024] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 5187.917190] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 5187.917273] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 5188.176145] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 5188.176225] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 5192.411845] [drm:drm_atomic_helper_wait_for_flip_done [drm_kms_helper]] *ERROR* [CRTC:37:pipe A] flip_done timed out
>[ 5192.412447] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 00 00 04 00 0f 00 04
>[ 5192.413850] [drm:intel_power_well_disable [i915]] disabling power well 2
>[ 5192.413908] [drm:intel_power_well_disable [i915]] disabling DC off
>[ 5192.413976] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[ 5192.414019] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[ 5192.414086] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[ 5192.414129] [drm:intel_power_well_enable [i915]] enabling DC off
>[ 5192.414171] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[ 5192.414218] [drm:intel_power_well_enable [i915]] enabling power well 2
>[ 5192.414691] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 00 00 04 00 0f 00 04
>[ 5192.416062] [drm:intel_power_well_disable [i915]] disabling power well 2
>[ 5192.416074] [drm:intel_power_well_disable [i915]] disabling DC off
>[ 5192.416098] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[ 5192.416107] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[ 5192.451288] [drm:intel_power_well_enable [i915]] enabling DC off
>[ 5192.451302] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[ 5192.451335] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[ 5192.451431] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006f
>[ 5192.651611] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped
>[ 5192.651661] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[ 5192.651691] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[ 5193.749039] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 5193.749111] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 5193.749212] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[ 5193.749272] [drm:intel_power_well_enable [i915]] enabling power well 2
>[ 5194.009238] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 5194.009319] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 5195.740106] [drm:edp_panel_vdd_off_sync [i915]] Turning eDP port A VDD off
>[ 5195.740252] [drm:edp_panel_vdd_off_sync [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x00000067
>[ 5199.568135] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 5199.568217] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 5199.829296] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 5199.829377] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 5202.908123] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [CRTC:37:pipe A] flip_done timed out
>[ 5205.397073] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 5205.397155] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 5205.657744] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 5205.657826] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 5211.230531] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 5211.230613] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 5211.490968] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 5211.491048] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 5213.148022] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [CONNECTOR:49:eDP-1] flip_done timed out
>[ 5217.061873] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 5217.061954] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 5217.323390] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 5217.323471] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 5222.894884] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 5222.894965] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 5223.154840] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 5223.154921] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 5223.388012] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [PLANE:28:plane 1A] flip_done timed out
>[ 5228.731531] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 5228.731613] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 5228.990574] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 5228.990655] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 5233.628024] [drm:drm_atomic_helper_wait_for_flip_done [drm_kms_helper]] *ERROR* [CRTC:37:pipe A] flip_done timed out
>[ 5233.628626] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 00 00 04 00 0f 00 04
>[ 5233.630033] [drm:intel_power_well_disable [i915]] disabling power well 2
>[ 5233.630090] [drm:intel_power_well_disable [i915]] disabling DC off
>[ 5233.630140] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[ 5233.630189] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[ 5233.630263] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[ 5233.630311] [drm:intel_power_well_enable [i915]] enabling DC off
>[ 5233.630358] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[ 5233.630410] [drm:intel_power_well_enable [i915]] enabling power well 2
>[ 5233.630896] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 00 00 04 00 0f 00 04
>[ 5233.632330] [drm:intel_power_well_disable [i915]] disabling power well 2
>[ 5233.632378] [drm:intel_power_well_disable [i915]] disabling DC off
>[ 5233.632423] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[ 5233.632464] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[ 5233.667278] [drm:intel_power_well_enable [i915]] enabling DC off
>[ 5233.667331] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[ 5233.667418] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[ 5233.667563] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006f
>[ 5233.867544] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped
>[ 5233.867586] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[ 5233.867614] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[ 5234.563047] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 5234.563128] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 5234.563248] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[ 5234.563314] [drm:intel_power_well_enable [i915]] enabling power well 2
>[ 5234.824318] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 5234.824400] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 5236.956089] [drm:edp_panel_vdd_off_sync [i915]] Turning eDP port A VDD off
>[ 5236.956232] [drm:edp_panel_vdd_off_sync [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x00000067
>[ 5240.391604] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 5240.391685] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 5240.652241] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 5240.652322] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 5244.124127] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [CRTC:37:pipe A] flip_done timed out
>[ 5246.226945] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 5246.227025] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 5246.486428] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 5246.486508] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 5252.062952] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 5252.063033] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 5252.322414] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 5252.322496] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 5254.364023] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [CONNECTOR:49:eDP-1] flip_done timed out
>[ 5257.900552] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 5257.900634] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 5258.159903] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 5258.159985] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 5263.723411] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 5263.723431] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 5263.981589] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 5263.981669] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 5264.604067] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [PLANE:28:plane 1A] flip_done timed out
>[ 5269.544405] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 5269.544487] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 5269.803301] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 5269.803384] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 5274.844030] [drm:drm_atomic_helper_wait_for_flip_done [drm_kms_helper]] *ERROR* [CRTC:37:pipe A] flip_done timed out
>[ 5274.844623] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 00 00 04 00 0f 00 04
>[ 5274.846030] [drm:intel_power_well_disable [i915]] disabling power well 2
>[ 5274.846105] [drm:intel_power_well_disable [i915]] disabling DC off
>[ 5274.846151] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[ 5274.846195] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[ 5274.846263] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[ 5274.846306] [drm:intel_power_well_enable [i915]] enabling DC off
>[ 5274.846349] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[ 5274.846395] [drm:intel_power_well_enable [i915]] enabling power well 2
>[ 5274.846868] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 00 00 04 00 0f 00 04
>[ 5274.848278] [drm:intel_power_well_disable [i915]] disabling power well 2
>[ 5274.848332] [drm:intel_power_well_disable [i915]] disabling DC off
>[ 5274.848382] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[ 5274.848431] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[ 5274.883230] [drm:intel_power_well_enable [i915]] enabling DC off
>[ 5274.883282] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[ 5274.883370] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[ 5274.883514] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006f
>[ 5275.083734] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped
>[ 5275.083903] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[ 5275.084001] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 5275.084064] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[ 5275.374207] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 5275.374287] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 5275.374412] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[ 5275.374479] [drm:intel_power_well_enable [i915]] enabling power well 2
>[ 5275.637374] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 5275.637455] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 5278.171913] [drm:edp_panel_vdd_off_sync [i915]] Turning eDP port A VDD off
>[ 5278.172050] [drm:edp_panel_vdd_off_sync [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x00000067
>[ 5281.207334] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 5281.207415] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 5281.465569] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 5281.465650] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 5285.340020] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [CRTC:37:pipe A] flip_done timed out
>[ 5287.031202] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 5287.031283] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 5287.290356] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 5287.290438] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 5292.849854] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 5292.849937] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 5293.111300] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 5293.111381] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 5295.580105] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [CONNECTOR:49:eDP-1] flip_done timed out
>[ 5298.679726] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 5298.679807] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 5298.939681] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 5298.939763] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 5304.512375] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 5304.512457] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 5304.773373] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 5304.773455] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 5305.820006] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [PLANE:28:plane 1A] flip_done timed out
>[ 5305.820113] [drm:intel_edp_backlight_off [i915]] 
>[ 5306.028044] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0
>[ 5306.028182] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 5306.033928] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[ 5306.034086] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b
>[ 5306.034359] [drm:intel_edp_panel_off.part.31 [i915]] Turn eDP port A panel power off
>[ 5306.034460] [drm:intel_edp_panel_off.part.31 [i915]] Wait for panel power off time
>[ 5306.034587] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000002 control 00000060
>[ 5306.084756] [drm:wait_panel_status [i915]] Wait complete
>[ 5306.084811] [drm:intel_power_well_disable [i915]] disabling DDI A/E IO power well
>[ 5306.084888] [drm:intel_disable_shared_dpll [i915]] disable DPLL 0 (active 1, on? 1) for crtc 37
>[ 5306.084953] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 0
>[ 5306.085036] [drm:intel_atomic_commit_tail [i915]] [ENCODER:48:DDI A]
>[ 5306.085098] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI B]
>[ 5306.085157] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[ 5306.085215] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[ 5306.085270] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DDI C]
>[ 5306.085325] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST A]
>[ 5306.085379] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST B]
>[ 5306.085433] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI D]
>[ 5306.085486] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[ 5306.085539] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[ 5306.085598] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:49:eDP-1]
>[ 5306.085657] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[ 5306.085716] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[ 5306.085773] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[ 5306.085828] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[ 5306.085896] [drm:intel_atomic_commit_tail [i915]] [CRTC:37:pipe A]
>[ 5306.086007] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[ 5306.086406] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 00 00 04 00 0f 00 04
>[ 5306.087822] [drm:intel_power_well_disable [i915]] disabling power well 2
>[ 5306.087884] [drm:intel_power_well_disable [i915]] disabling DC off
>[ 5306.087937] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[ 5306.087941] Setting dangerous option enable_psr - tainting kernel
>[ 5306.087990] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[ 5306.088922] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 5306.088997] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[ 5306.089040] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 5306.089067] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[ 5306.089109] [drm:intel_power_well_enable [i915]] enabling DC off
>[ 5306.089131] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[ 5306.089225] [drm:intel_atomic_check [i915]] [CONNECTOR:49:eDP-1] checking for sink bpp constrains
>[ 5306.089289] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 5306.089320] [drm:drm_mode_debug_printmodeline [drm]] Modeline 52:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[ 5306.089385] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 138780KHz
>[ 5306.089426] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[ 5306.089473] [drm:intel_power_well_enable [i915]] enabling power well 2
>[ 5306.089534] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24
>[ 5306.089592] [drm:intel_dp_compute_config [i915]] DP link bw required 416340 available 540000
>[ 5306.089653] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 5306.089742] [drm:intel_dump_pipe_config [i915]] [CRTC:37:pipe A][modeset]
>[ 5306.089798] [drm:intel_dump_pipe_config [i915]] output_types: EDP (0x100)
>[ 5306.089853] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0
>[ 5306.089907] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 6467616, gmch_n: 8388608, link_m: 269484, link_n: 524288, tu: 64
>[ 5306.089959] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[ 5306.090009] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 5306.090035] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[ 5306.090087] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 5306.090113] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[ 5306.090167] [drm:intel_dump_pipe_config [i915]] crtc timings: 138780 1920 1966 1996 2080 1080 1082 1086 1112, type: 0x48 flags: 0xa
>[ 5306.090220] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 138780
>[ 5306.090271] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[ 5306.090321] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 5306.090371] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 5306.090421] [drm:intel_dump_pipe_config [i915]] dpll_hw_state: ctrl1: 0x3, cfgcr1: 0x0, cfgcr2: 0x0
>[ 5306.090475] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 5306.090525] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 1A] disabled, scaler_id = -1
>[ 5306.090573] [drm:intel_dump_pipe_config [i915]] [PLANE:31:plane 2A] disabled, scaler_id = -1
>[ 5306.090621] [drm:intel_dump_pipe_config [i915]] [PLANE:34:cursor A] disabled, scaler_id = -1
>[ 5306.090680] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 5306.090735] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[ 5306.090801] [drm:intel_find_shared_dpll [i915]] [CRTC:37:pipe A] allocated DPLL 0
>[ 5306.090857] [drm:intel_reference_shared_dpll [i915]] using DPLL 0 for pipe A
>[ 5306.092124] [drm:intel_atomic_commit_tail [i915]] [ENCODER:48:DDI A]
>[ 5306.092139] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI B]
>[ 5306.092152] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[ 5306.092165] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[ 5306.092177] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DDI C]
>[ 5306.092189] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST A]
>[ 5306.092201] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST B]
>[ 5306.092212] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI D]
>[ 5306.092224] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[ 5306.092235] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[ 5306.092247] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[ 5306.092260] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[ 5306.092273] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[ 5306.092285] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[ 5306.092299] [drm:intel_enable_shared_dpll [i915]] enable DPLL 0 (active 1, on? 0) for crtc 37
>[ 5306.092311] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 0
>[ 5306.092331] [drm:edp_panel_on [i915]] Turn eDP port A panel power on
>[ 5306.092356] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle
>[ 5306.095999] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010
>[ 5306.096021] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[ 5306.096038] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0
>[ 5306.716153] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 00000000 control 00000060
>[ 5306.716243] [drm:wait_panel_status [i915]] Wait complete
>[ 5306.716368] [drm:edp_panel_on [i915]] Wait for panel power on
>[ 5306.716500] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 00000063
>[ 5306.750173] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010
>[ 5306.750255] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[ 5306.750329] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1
>[ 5306.916693] [drm:wait_panel_status [i915]] Wait complete
>[ 5306.916757] [drm:intel_power_well_enable [i915]] enabling DDI A/E IO power well
>[ 5306.916860] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[ 5306.917011] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b
>[ 5306.918248] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 5306.918321] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 5306.918385] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 5306.918447] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 5306.919160] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 5306.919220] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 5306.920241] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 5306.920306] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:49:eDP-1] Link Training Passed at Link Rate = 270000, Lane count = 2
>[ 5306.920962] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 5306.921037] [drm:intel_edp_backlight_on [i915]] 
>[ 5306.921101] [drm:intel_panel_enable_backlight [i915]] pipe A
>[ 5306.921190] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 120000
>[ 5306.928073] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS
>[ 5310.171949] [drm:edp_panel_vdd_off_sync [i915]] Turning eDP port A VDD off
>[ 5310.172093] [drm:edp_panel_vdd_off_sync [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x00000067
>[ 5310.336856] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 5310.336938] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 5310.596484] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 5310.596565] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 5316.168211] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 5316.168292] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 5316.427741] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 5316.427824] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 5317.084003] [drm:drm_atomic_helper_wait_for_flip_done [drm_kms_helper]] *ERROR* [CRTC:37:pipe A] flip_done timed out
>[ 5317.084128] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:49:eDP-1]
>[ 5317.084211] [drm:intel_atomic_commit_tail [i915]] [CRTC:37:pipe A]
>[ 5317.084307] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[ 5317.084894] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 00 00 04 00 0f 00 04
>[ 5317.086299] [drm:intel_power_well_disable [i915]] disabling power well 2
>[ 5317.086355] [drm:intel_power_well_disable [i915]] disabling DC off
>[ 5317.086407] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[ 5317.086456] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[ 5317.086528] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[ 5317.086592] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[ 5317.086641] [drm:intel_power_well_enable [i915]] enabling DC off
>[ 5317.086688] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[ 5317.086739] [drm:intel_power_well_enable [i915]] enabling power well 2
>[ 5317.087220] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 00 00 04 00 0f 00 04
>[ 5317.088636] [drm:intel_power_well_disable [i915]] disabling power well 2
>[ 5317.088689] [drm:intel_power_well_disable [i915]] disabling DC off
>[ 5317.088738] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[ 5317.088785] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[ 5317.120993] [drm:intel_power_well_enable [i915]] enabling DC off
>[ 5317.121045] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[ 5317.121133] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[ 5317.121279] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006f
>[ 5317.321277] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped
>[ 5317.571265] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped
>[ 5319.121232] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped
>[ 5321.137862] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped
>[ 5321.995195] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 5321.995266] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 5321.995353] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[ 5321.995404] [drm:intel_power_well_enable [i915]] enabling power well 2
>[ 5321.995920] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 00 00 04 00 0f 00 04
>[ 5321.996281] [drm:intel_power_well_disable [i915]] disabling power well 2
>[ 5321.996356] [drm:i915_hotplug_work_func [i915]] running encoder hotplug functions
>[ 5321.996420] [drm:i915_hotplug_work_func [i915]] Connector DP-1 (pin 5) received hotplug event.
>[ 5321.996482] [drm:intel_dp_detect [i915]] [CONNECTOR:57:DP-1]
>[ 5321.996527] [drm:intel_power_well_enable [i915]] enabling power well 2
>[ 5321.996911] [drm:lspcon_wake_native_aux_ch [i915]] Native AUX CH up, DPCD version: 1.2
>[ 5321.996981] [drm:lspcon_resume [i915]] LSPCON recovering in PCON mode after 0 ms
>[ 5321.997419] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5321.998663] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5321.999919] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5322.001163] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5322.002413] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5322.003283] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[ 5322.003760] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 00 00 04 00 0f 00 04
>[ 5322.004137] [drm:intel_power_well_disable [i915]] disabling power well 2
>[ 5322.004209] [drm:i915_hotplug_work_func [i915]] [CONNECTOR:57:DP-1] status updated from connected to disconnected
>[ 5322.252956] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 5322.253037] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 5322.253161] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[ 5322.253227] [drm:intel_power_well_enable [i915]] enabling power well 2
>[ 5322.253750] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 00 00 04 00 0f 00 04
>[ 5322.254530] [drm:intel_power_well_disable [i915]] disabling power well 2
>[ 5322.254614] [drm:i915_hotplug_work_func [i915]] running encoder hotplug functions
>[ 5322.254683] [drm:i915_hotplug_work_func [i915]] Connector DP-1 (pin 5) received hotplug event.
>[ 5322.254749] [drm:intel_dp_detect [i915]] [CONNECTOR:57:DP-1]
>[ 5322.254800] [drm:intel_power_well_enable [i915]] enabling power well 2
>[ 5322.255183] [drm:lspcon_wake_native_aux_ch [i915]] Native AUX CH up, DPCD version: 1.2
>[ 5322.255258] [drm:lspcon_resume [i915]] LSPCON recovering in PCON mode after 0 ms
>[ 5322.255700] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5322.256931] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5322.258185] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5322.259430] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5322.260634] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5322.261511] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[ 5322.261997] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 00 00 04 00 0f 00 04
>[ 5322.262778] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>[ 5322.262836] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000
>[ 5322.262890] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000
>[ 5322.263292] [drm:drm_dp_read_desc [drm_kms_helper]] DP branch: OUI 00-60-ad dev-ID MC2800 HW-rev 2.2 SW-rev 1.70 quirks 0x0000
>[ 5322.263652] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[ 5322.264486] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5322.265736] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5322.266990] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5322.268286] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5322.269537] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5322.270793] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5322.272073] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5322.273299] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5322.274541] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5322.275926] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5322.277276] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5322.278650] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5322.280031] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5322.281410] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5322.282787] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5322.284167] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5322.285536] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5322.286776] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5322.288048] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5322.289275] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5322.290517] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5322.291888] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5322.293266] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5322.294640] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5322.296023] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5322.297390] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5322.298766] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5322.300152] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5322.301519] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5322.302664] [drm:intel_power_well_disable [i915]] disabling power well 2
>[ 5322.302740] [drm:i915_hotplug_work_func [i915]] [CONNECTOR:57:DP-1] status updated from disconnected to connected
>[ 5323.121157] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped
>[ 5326.300126] [drm:edp_panel_vdd_off_sync [i915]] Turning eDP port A VDD off
>[ 5326.300291] [drm:edp_panel_vdd_off_sync [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x00000067
>[ 5326.300345] [drm:intel_power_well_disable [i915]] disabling DC off
>[ 5326.300398] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[ 5326.300448] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[ 5327.819777] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 5327.819858] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 5327.819983] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[ 5327.820049] [drm:intel_power_well_enable [i915]] enabling DC off
>[ 5327.820120] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[ 5327.820200] [drm:intel_power_well_enable [i915]] enabling power well 2
>[ 5328.080601] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 5328.080682] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 5333.653309] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 5333.653390] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 5333.913184] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 5333.913265] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 5335.004123] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [CRTC:37:pipe A] flip_done timed out
>[ 5339.474522] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 5339.474604] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 5339.734512] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 5339.734594] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 5345.244111] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [PLANE:28:plane 1A] flip_done timed out
>[ 5345.301938] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 5345.302020] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 5345.562499] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 5345.562581] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 5351.136427] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 5351.136508] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 5351.394675] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 5351.394756] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 5355.484120] [drm:drm_atomic_helper_wait_for_flip_done [drm_kms_helper]] *ERROR* [CRTC:37:pipe A] flip_done timed out
>[ 5355.484396] [IGT] kms_frontbuffer_tracking: exiting, ret=0
>[ 5355.484466] Setting dangerous option enable_psr - tainting kernel
>[ 5355.484481] Setting dangerous option enable_fbc - tainting kernel
>[ 5355.484729] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 00 00 04 00 0f 00 04
>[ 5355.486311] [drm:intel_power_well_disable [i915]] disabling power well 2
>[ 5355.486368] [drm:intel_power_well_disable [i915]] disabling DC off
>[ 5355.486419] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[ 5355.486467] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[ 5355.486543] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[ 5355.486591] [drm:intel_power_well_enable [i915]] enabling DC off
>[ 5355.486638] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[ 5355.486690] [drm:intel_power_well_enable [i915]] enabling power well 2
>[ 5355.487177] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 00 00 04 00 0f 00 04
>[ 5355.488589] [drm:intel_power_well_disable [i915]] disabling power well 2
>[ 5355.488641] [drm:intel_power_well_disable [i915]] disabling DC off
>[ 5355.488690] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[ 5355.488737] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[ 5355.532053] [drm:intel_atomic_check [i915]] [CONNECTOR:57:DP-1] checking for sink bpp constrains
>[ 5355.532070] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 5355.532087] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 148500KHz
>[ 5355.532105] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 5355.532119] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 648000
>[ 5355.532136] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 5355.532151] [drm:intel_dump_pipe_config [i915]] [CRTC:47:pipe B][modeset]
>[ 5355.532166] [drm:intel_dump_pipe_config [i915]] output_types: DP (0x80)
>[ 5355.532180] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 5355.532195] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5767168, gmch_n: 8388608, link_m: 240298, link_n: 262144, tu: 64
>[ 5355.532208] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[ 5355.532221] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 5355.532230] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[ 5355.532244] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 5355.532250] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[ 5355.532265] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[ 5355.532278] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1080, pixel rate 148500
>[ 5355.532291] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[ 5355.532304] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 5355.532317] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 5355.532330] [drm:intel_dump_pipe_config [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[ 5355.532342] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 5355.532355] [drm:intel_dump_pipe_config [i915]] [PLANE:38:plane 1B] disabled, scaler_id = -1
>[ 5355.532368] [drm:intel_dump_pipe_config [i915]] [PLANE:41:plane 2B] disabled, scaler_id = -1
>[ 5355.532380] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor B] disabled, scaler_id = -1
>[ 5355.532396] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 5355.532410] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[ 5355.532429] [drm:intel_find_shared_dpll [i915]] [CRTC:47:pipe B] allocated DPLL 1
>[ 5355.532444] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[ 5356.959413] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 5356.959494] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 5356.959618] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[ 5356.959683] [drm:intel_power_well_enable [i915]] enabling DC off
>[ 5356.959754] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[ 5356.959856] [drm:intel_power_well_enable [i915]] enabling power well 2
>[ 5357.220274] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 5357.220356] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 5362.788755] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 5362.788836] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 5363.050858] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 5363.050939] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 5365.724119] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [CRTC:37:pipe A] flip_done timed out
>[ 5368.626171] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 5368.626253] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 5368.886286] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 5368.886367] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 5374.458004] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 5374.458085] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 5374.719415] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 5374.719495] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 5375.963958] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [CONNECTOR:49:eDP-1] flip_done timed out
>[ 5380.294390] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 5380.294471] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 5380.556151] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 5380.556232] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 5386.124409] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 5386.124490] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 5386.204022] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [PLANE:28:plane 1A] flip_done timed out
>[ 5386.204114] [drm:intel_disable_sagv [i915]] Disabling the SAGV
>[ 5386.204200] [drm:intel_atomic_commit_tail [i915]] [ENCODER:48:DDI A]
>[ 5386.204273] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI B]
>[ 5386.204341] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[ 5386.204407] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[ 5386.204470] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DDI C]
>[ 5386.204533] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST A]
>[ 5386.204594] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST B]
>[ 5386.204654] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI D]
>[ 5386.204714] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[ 5386.204773] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[ 5386.204839] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[ 5386.204908] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[ 5386.204973] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[ 5386.205035] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[ 5386.205111] [drm:intel_fbc_enable [i915]] reserved 16588800 bytes of contiguous stolen space for FBC, threshold: 1
>[ 5386.205179] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 5386.220049] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 2, on? 0) for crtc 47
>[ 5386.220125] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[ 5386.220288] [drm:intel_power_well_enable [i915]] enabling DDI B IO power well
>[ 5386.220902] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5386.222159] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5386.223417] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5386.224630] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5386.225888] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5386.226768] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[ 5386.227754] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 5386.227844] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 5386.227910] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 5386.227985] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 5386.247798] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 5386.247812] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[ 5386.265550] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 5386.265873] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:57:DP-1] Link Training Passed at Link Rate = 162000, Lane count = 4
>[ 5386.266257] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 5386.266324] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS
>[ 5386.388199] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 5386.388234] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 5396.444118] [drm:drm_atomic_helper_wait_for_flip_done [drm_kms_helper]] *ERROR* [CRTC:37:pipe A] flip_done timed out
>[ 5396.444252] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:57:DP-1]
>[ 5396.444337] [drm:intel_atomic_commit_tail [i915]] [CRTC:47:pipe B]
>[ 5396.444435] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[ 5396.444487] [drm:drm_fb_helper_hotplug_event.part.30 [drm_kms_helper]] 
>[ 5396.444499] [drm:drm_setup_crtcs [drm_kms_helper]] 
>[ 5396.444514] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:49:eDP-1]
>[ 5396.444590] [drm:intel_dp_detect [i915]] [CONNECTOR:49:eDP-1]
>[ 5396.444667] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>[ 5396.444735] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[ 5396.444800] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[ 5396.444879] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[ 5396.445020] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006f
>[ 5396.445467] [drm:drm_dp_read_desc [drm_kms_helper]] DP sink: OUI 00-1c-f8 dev-ID  HW-rev 0.1 SW-rev 1.22 quirks 0x0000
>[ 5396.446204] [drm:drm_add_edid_modes [drm]] ELD: no CEA Extension found
>[ 5396.446257] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:49:eDP-1] probed modes :
>[ 5396.446287] [drm:drm_mode_debug_printmodeline [drm]] Modeline 50:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[ 5396.446300] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:57:DP-1]
>[ 5396.446773] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 00 00 04 00 0f 00 04
>[ 5396.448223] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[ 5396.448307] [drm:intel_dp_detect [i915]] [CONNECTOR:57:DP-1]
>[ 5396.448699] [drm:lspcon_wake_native_aux_ch [i915]] Native AUX CH up, DPCD version: 1.2
>[ 5396.448776] [drm:lspcon_resume [i915]] LSPCON recovering in PCON mode after 0 ms
>[ 5396.449217] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5396.450498] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5396.451783] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5396.453060] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5396.454342] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5396.455119] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[ 5396.455517] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 00 00 04 00 0f 00 04
>[ 5396.456199] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>[ 5396.456214] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000
>[ 5396.456227] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000
>[ 5396.456591] [drm:drm_dp_read_desc [drm_kms_helper]] DP branch: OUI 00-60-ad dev-ID MC2800 HW-rev 2.2 SW-rev 1.70 quirks 0x0000
>[ 5396.456877] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[ 5396.457603] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5396.458855] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5396.460098] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5396.461332] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5396.462574] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5396.463802] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5396.465039] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5396.466279] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5396.467507] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5396.468863] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5396.470181] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5396.471539] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5396.472900] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5396.474259] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5396.475620] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5396.476983] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5396.478338] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5396.479558] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5396.480800] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5396.482036] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5396.483263] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5396.484556] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5396.485915] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5396.487274] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5396.488545] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5396.489915] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5396.491274] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5396.492552] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5396.493907] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5396.495001] [drm:drm_add_edid_modes [drm]] ELD monitor HP E232
>[ 5396.495008] [drm:drm_add_edid_modes [drm]] HDMI: latency present 0 0, video latency 0 0, audio latency 0 0
>[ 5396.495014] [drm:drm_add_edid_modes [drm]] ELD size 28, SAD count 0
>[ 5396.495020] [drm:drm_add_edid_modes [drm]] HDMI: DVI dual 0, max TMDS clock 170000 kHz
>[ 5396.495103] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:57:DP-1] probed modes :
>[ 5396.495110] [drm:drm_mode_debug_printmodeline [drm]] Modeline 74:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[ 5396.495117] [drm:drm_mode_debug_printmodeline [drm]] Modeline 97:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[ 5396.495122] [drm:drm_mode_debug_printmodeline [drm]] Modeline 76:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[ 5396.495128] [drm:drm_mode_debug_printmodeline [drm]] Modeline 81:"1680x1050" 60 119000 1680 1728 1760 1840 1050 1053 1059 1080 0x40 0x9
>[ 5396.495134] [drm:drm_mode_debug_printmodeline [drm]] Modeline 80:"1600x900" 60 108000 1600 1624 1704 1800 900 901 904 1000 0x40 0x5
>[ 5396.495141] [drm:drm_mode_debug_printmodeline [drm]] Modeline 84:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[ 5396.495147] [drm:drm_mode_debug_printmodeline [drm]] Modeline 82:"1440x900" 60 88750 1440 1488 1520 1600 900 903 909 926 0x40 0x9
>[ 5396.495154] [drm:drm_mode_debug_printmodeline [drm]] Modeline 83:"1280x800" 60 71000 1280 1328 1360 1440 800 803 809 823 0x40 0x9
>[ 5396.495160] [drm:drm_mode_debug_printmodeline [drm]] Modeline 77:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[ 5396.495167] [drm:drm_mode_debug_printmodeline [drm]] Modeline 99:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[ 5396.495173] [drm:drm_mode_debug_printmodeline [drm]] Modeline 78:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[ 5396.495180] [drm:drm_mode_debug_printmodeline [drm]] Modeline 87:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[ 5396.495186] [drm:drm_mode_debug_printmodeline [drm]] Modeline 85:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[ 5396.495192] [drm:drm_mode_debug_printmodeline [drm]] Modeline 95:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[ 5396.495199] [drm:drm_mode_debug_printmodeline [drm]] Modeline 100:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[ 5396.495206] [drm:drm_mode_debug_printmodeline [drm]] Modeline 79:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[ 5396.495213] [drm:drm_mode_debug_printmodeline [drm]] Modeline 101:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[ 5396.495221] [drm:drm_mode_debug_printmodeline [drm]] Modeline 86:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[ 5396.495225] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:61:DP-2]
>[ 5396.495535] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 00 00 04 00 0f 00 04
>[ 5396.496817] [drm:intel_dp_detect [i915]] [CONNECTOR:61:DP-2]
>[ 5396.496834] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:61:DP-2] disconnected
>[ 5396.496838] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:64:HDMI-A-1]
>[ 5396.496856] [drm:intel_hdmi_detect [i915]] [CONNECTOR:64:HDMI-A-1]
>[ 5396.497180] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[ 5396.497197] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[ 5396.497515] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[ 5396.497523] [drm:drm_do_probe_ddc_edid [drm]] drm: skipping non-existent adapter i915 gmbus dpc
>[ 5396.497840] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[ 5396.497855] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[ 5396.498171] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[ 5396.498175] [drm:drm_dp_dual_mode_detect [drm_kms_helper]] DP dual mode HDMI ID:  (err -6)
>[ 5396.498178] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:64:HDMI-A-1] disconnected
>[ 5396.498182] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:67:DP-3]
>[ 5396.498198] [drm:intel_dp_detect [i915]] [CONNECTOR:67:DP-3]
>[ 5396.498213] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:67:DP-3] disconnected
>[ 5396.498216] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:70:HDMI-A-2]
>[ 5396.498232] [drm:intel_hdmi_detect [i915]] [CONNECTOR:70:HDMI-A-2]
>[ 5396.509102] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0050 w(1)
>[ 5396.509121] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK on first message, retry
>[ 5396.519924] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0050 w(1)
>[ 5396.519935] [drm:drm_do_probe_ddc_edid [drm]] drm: skipping non-existent adapter i915 gmbus dpd
>[ 5396.529724] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0040 w(1)
>[ 5396.529757] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK on first message, retry
>[ 5396.539543] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0040 w(1)
>[ 5396.539557] [drm:drm_dp_dual_mode_detect [drm_kms_helper]] DP dual mode HDMI ID:  (err -6)
>[ 5396.539567] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:70:HDMI-A-2] disconnected
>[ 5396.539576] [drm:drm_setup_crtcs [drm_kms_helper]] connector 49 enabled? yes
>[ 5396.539583] [drm:drm_setup_crtcs [drm_kms_helper]] connector 57 enabled? yes
>[ 5396.539590] [drm:drm_setup_crtcs [drm_kms_helper]] connector 61 enabled? no
>[ 5396.539596] [drm:drm_setup_crtcs [drm_kms_helper]] connector 64 enabled? no
>[ 5396.539602] [drm:drm_setup_crtcs [drm_kms_helper]] connector 67 enabled? no
>[ 5396.539609] [drm:drm_setup_crtcs [drm_kms_helper]] connector 70 enabled? no
>[ 5396.539659] [drm:intel_fb_initial_config [i915]] Not using firmware configuration
>[ 5396.539668] [drm:drm_setup_crtcs [drm_kms_helper]] looking for cmdline mode on connector 49
>[ 5396.539675] [drm:drm_setup_crtcs [drm_kms_helper]] looking for preferred mode on connector 49 0
>[ 5396.539682] [drm:drm_setup_crtcs [drm_kms_helper]] found mode 1920x1080
>[ 5396.539688] [drm:drm_setup_crtcs [drm_kms_helper]] looking for cmdline mode on connector 57
>[ 5396.539694] [drm:drm_setup_crtcs [drm_kms_helper]] looking for preferred mode on connector 57 0
>[ 5396.539701] [drm:drm_setup_crtcs [drm_kms_helper]] found mode 1920x1080
>[ 5396.539708] [drm:drm_setup_crtcs [drm_kms_helper]] picking CRTCs for 1920x1080 config
>[ 5396.539720] [drm:drm_setup_crtcs [drm_kms_helper]] desired mode 1920x1080 set on crtc 37 (0,0)
>[ 5396.539727] [drm:drm_setup_crtcs [drm_kms_helper]] desired mode 1920x1080 set on crtc 47 (0,0)
>[ 5399.516098] [drm:edp_panel_vdd_off_sync [i915]] Turning eDP port A VDD off
>[ 5399.516242] [drm:edp_panel_vdd_off_sync [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x00000067
>[ 5406.684097] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [CRTC:37:pipe A] flip_done timed out
>[ 5416.924004] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [CONNECTOR:49:eDP-1] flip_done timed out
>[ 5427.163999] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [PLANE:28:plane 1A] flip_done timed out
>[ 5437.403969] [drm:drm_atomic_helper_wait_for_flip_done [drm_kms_helper]] *ERROR* [CRTC:37:pipe A] flip_done timed out
>[ 5437.465994] [IGT] kms_frontbuffer_tracking: executing
>[ 5437.522003] [drm:drm_mode_addfb2 [drm]] [FB:71]
>[ 5437.522055] [drm:drm_mode_addfb2 [drm]] [FB:89]
>[ 5437.522105] [drm:drm_mode_addfb2 [drm]] [FB:92]
>[ 5437.523035] [drm:drm_mode_addfb2 [drm]] [FB:93]
>[ 5437.531949] [drm:drm_mode_addfb2 [drm]] [FB:94]
>[ 5437.534196] [drm:drm_mode_addfb2 [drm]] [FB:96]
>[ 5437.534244] [drm:drm_mode_addfb2 [drm]] [FB:98]
>[ 5437.534300] [drm:drm_mode_addfb2 [drm]] [FB:102]
>[ 5437.534579] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[ 5437.534595] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[ 5447.643960] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [CRTC:37:pipe A] flip_done timed out
>[ 5457.884113] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [CONNECTOR:49:eDP-1] flip_done timed out
>[ 5468.124107] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [PLANE:28:plane 1A] flip_done timed out
>[ 5478.364066] [drm:drm_atomic_helper_wait_for_flip_done [drm_kms_helper]] *ERROR* [CRTC:37:pipe A] flip_done timed out
>[ 5478.364257] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[ 5478.364411] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006f
>[ 5478.551788] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped
>[ 5478.552012] [IGT] kms_frontbuffer_tracking: starting subtest psr-1p-primscrn-cur-indfb-draw-blt
>[ 5478.552087] Setting dangerous option enable_fbc - tainting kernel
>[ 5478.552110] Setting dangerous option enable_psr - tainting kernel
>[ 5481.692189] [drm:edp_panel_vdd_off_sync [i915]] Turning eDP port A VDD off
>[ 5481.692333] [drm:edp_panel_vdd_off_sync [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x00000067
>[ 5488.603978] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [CRTC:37:pipe A] flip_done timed out
>[ 5498.844110] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [PLANE:28:plane 1A] flip_done timed out
>[ 5509.084001] [drm:drm_atomic_helper_wait_for_flip_done [drm_kms_helper]] *ERROR* [CRTC:37:pipe A] flip_done timed out
>[ 5509.088388] [drm:drm_mode_addfb2 [drm]] [FB:71]
>[ 5509.088490] [drm:drm_mode_addfb2 [drm]] [FB:75]
>[ 5509.088597] [drm:drm_mode_addfb2 [drm]] [FB:89]
>[ 5509.089585] [drm:drm_mode_addfb2 [drm]] [FB:92]
>[ 5509.093343] [drm:drm_mode_addfb2 [drm]] [FB:93]
>[ 5509.094180] [drm:drm_mode_addfb2 [drm]] [FB:94]
>[ 5509.094199] [drm:drm_mode_addfb2 [drm]] [FB:96]
>[ 5509.094219] [drm:drm_mode_addfb2 [drm]] [FB:98]
>[ 5509.094226] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[ 5509.094261] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 5509.094275] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[ 5519.324101] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [CRTC:37:pipe A] flip_done timed out
>[ 5529.564105] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [CONNECTOR:49:eDP-1] flip_done timed out
>[ 5539.804078] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [PLANE:28:plane 1A] flip_done timed out
>[ 5539.804204] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[ 5539.804358] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006f
>[ 5539.804629] [drm:intel_edp_backlight_off [i915]] 
>[ 5540.012075] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0
>[ 5540.012215] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 5540.018116] [drm:intel_edp_panel_off.part.31 [i915]] Turn eDP port A panel power off
>[ 5540.018229] [drm:intel_edp_panel_off.part.31 [i915]] Wait for panel power off time
>[ 5540.018361] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000002 control 00000060
>[ 5540.068372] [drm:wait_panel_status [i915]] Wait complete
>[ 5540.068436] [drm:intel_power_well_disable [i915]] disabling DDI A/E IO power well
>[ 5540.068519] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 5540.068599] [drm:intel_disable_shared_dpll [i915]] disable DPLL 0 (active 1, on? 1) for crtc 37
>[ 5540.068670] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 0
>[ 5540.068763] [drm:intel_atomic_commit_tail [i915]] [ENCODER:48:DDI A]
>[ 5540.068832] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI B]
>[ 5540.068898] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[ 5540.068963] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[ 5540.069026] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DDI C]
>[ 5540.069087] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST A]
>[ 5540.069147] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST B]
>[ 5540.069207] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI D]
>[ 5540.069267] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[ 5540.069325] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[ 5540.069391] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:49:eDP-1]
>[ 5540.069458] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[ 5540.069523] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[ 5540.069587] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[ 5540.069648] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[ 5540.077999] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010
>[ 5540.078081] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[ 5540.078154] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0
>[ 5540.078272] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[ 5540.083719] [drm:intel_atomic_commit_tail [i915]] [CRTC:37:pipe A]
>[ 5540.083830] [drm:intel_enable_sagv [i915]] Enabling the SAGV
>[ 5540.083934] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[ 5540.084037] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 5540.084111] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[ 5540.084214] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 5540.101092] [drm:intel_power_well_disable [i915]] disabling DDI B IO power well
>[ 5540.101176] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 2, on? 1) for crtc 47
>[ 5540.101249] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[ 5540.101340] [drm:intel_atomic_commit_tail [i915]] [ENCODER:48:DDI A]
>[ 5540.101404] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI B]
>[ 5540.101469] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[ 5540.101529] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[ 5540.101586] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DDI C]
>[ 5540.101644] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST A]
>[ 5540.101700] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST B]
>[ 5540.101755] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI D]
>[ 5540.101810] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[ 5540.101865] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[ 5540.101927] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:57:DP-1]
>[ 5540.101989] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[ 5540.102050] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[ 5540.102108] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[ 5540.102166] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[ 5540.102225] [drm:intel_power_well_disable [i915]] disabling power well 2
>[ 5540.102296] [drm:intel_atomic_commit_tail [i915]] [CRTC:47:pipe B]
>[ 5540.102351] [drm:intel_power_well_disable [i915]] disabling DC off
>[ 5540.102402] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[ 5540.102451] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[ 5540.102890] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 5540.106997] [drm:drm_mode_addfb2 [drm]] [FB:91]
>[ 5540.109048] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[ 5540.109055] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[ 5540.109078] [drm:intel_atomic_check [i915]] [CONNECTOR:49:eDP-1] checking for sink bpp constrains
>[ 5540.109093] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 5540.109100] [drm:drm_mode_debug_printmodeline [drm]] Modeline 52:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[ 5540.109115] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 138780KHz
>[ 5540.109133] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24
>[ 5540.109146] [drm:intel_dp_compute_config [i915]] DP link bw required 416340 available 540000
>[ 5540.109159] [drm:intel_dp_compute_config [i915]] PSR disable by flag
>[ 5540.109173] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 5540.109187] [drm:intel_dump_pipe_config [i915]] [CRTC:37:pipe A][modeset]
>[ 5540.109200] [drm:intel_dump_pipe_config [i915]] output_types: EDP (0x100)
>[ 5540.109213] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0
>[ 5540.109226] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 6467616, gmch_n: 8388608, link_m: 269484, link_n: 524288, tu: 64
>[ 5540.109239] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[ 5540.109250] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 5540.109257] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[ 5540.109269] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 5540.109275] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[ 5540.109288] [drm:intel_dump_pipe_config [i915]] crtc timings: 138780 1920 1966 1996 2080 1080 1082 1086 1112, type: 0x48 flags: 0xa
>[ 5540.109300] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 138780
>[ 5540.109312] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[ 5540.109324] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 5540.109336] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 5540.109348] [drm:intel_dump_pipe_config [i915]] dpll_hw_state: ctrl1: 0x3, cfgcr1: 0x0, cfgcr2: 0x0
>[ 5540.109359] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 5540.109371] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 1A] disabled, scaler_id = -1
>[ 5540.109382] [drm:intel_dump_pipe_config [i915]] [PLANE:31:plane 2A] disabled, scaler_id = -1
>[ 5540.109394] [drm:intel_dump_pipe_config [i915]] [PLANE:34:cursor A] disabled, scaler_id = -1
>[ 5540.109408] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 5540.109421] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[ 5540.109437] [drm:intel_find_shared_dpll [i915]] [CRTC:37:pipe A] allocated DPLL 0
>[ 5540.109450] [drm:intel_reference_shared_dpll [i915]] using DPLL 0 for pipe A
>[ 5540.110005] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 5540.110015] [drm:intel_power_well_enable [i915]] enabling DC off
>[ 5540.110273] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[ 5540.110291] [drm:intel_atomic_commit_tail [i915]] [ENCODER:48:DDI A]
>[ 5540.110304] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI B]
>[ 5540.110317] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[ 5540.110330] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[ 5540.110342] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DDI C]
>[ 5540.110354] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST A]
>[ 5540.110366] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST B]
>[ 5540.110378] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI D]
>[ 5540.110390] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[ 5540.110402] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[ 5540.110415] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[ 5540.110428] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[ 5540.110441] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[ 5540.110454] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[ 5540.110468] [drm:intel_enable_shared_dpll [i915]] enable DPLL 0 (active 1, on? 0) for crtc 37
>[ 5540.110482] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 0
>[ 5540.110502] [drm:edp_panel_on [i915]] Turn eDP port A panel power on
>[ 5540.110527] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle
>[ 5540.700315] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 00000000 control 00000060
>[ 5540.700422] [drm:wait_panel_status [i915]] Wait complete
>[ 5540.700560] [drm:edp_panel_on [i915]] Wait for panel power on
>[ 5540.700691] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 00000063
>[ 5540.734121] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010
>[ 5540.734202] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[ 5540.734277] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1
>[ 5540.734420] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[ 5540.903218] [drm:wait_panel_status [i915]] Wait complete
>[ 5540.903284] [drm:intel_power_well_enable [i915]] enabling DDI A/E IO power well
>[ 5540.903387] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[ 5540.903536] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b
>[ 5540.904739] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 5540.904803] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 5540.904863] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 5540.904922] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 5540.905635] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 5540.905693] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 5540.906656] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 5540.906682] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:49:eDP-1] Link Training Passed at Link Rate = 270000, Lane count = 2
>[ 5540.907060] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 5540.907095] [drm:intel_edp_backlight_on [i915]] 
>[ 5540.907107] [drm:intel_panel_enable_backlight [i915]] pipe A
>[ 5540.907146] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 120000
>[ 5540.911895] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS
>[ 5544.156090] [drm:edp_panel_vdd_off_sync [i915]] Turning eDP port A VDD off
>[ 5544.156236] [drm:edp_panel_vdd_off_sync [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x00000067
>[ 5551.068011] [drm:drm_atomic_helper_wait_for_flip_done [drm_kms_helper]] *ERROR* [CRTC:37:pipe A] flip_done timed out
>[ 5551.068131] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:49:eDP-1]
>[ 5551.068215] [drm:intel_atomic_commit_tail [i915]] [CRTC:37:pipe A]
>[ 5551.068312] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[ 5551.068376] [drm:intel_power_well_disable [i915]] disabling DC off
>[ 5551.068432] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[ 5551.068486] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[ 5551.107398] [drm:intel_power_well_enable [i915]] enabling DC off
>[ 5551.107457] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[ 5551.107554] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[ 5551.107707] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006f
>[ 5551.307369] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped
>[ 5551.307443] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[ 5551.307535] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 5551.307599] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[ 5554.396082] [drm:edp_panel_vdd_off_sync [i915]] Turning eDP port A VDD off
>[ 5554.396227] [drm:edp_panel_vdd_off_sync [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x00000067
>[ 5554.396285] [drm:intel_power_well_disable [i915]] disabling DC off
>[ 5554.396342] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[ 5554.396395] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[ 5560.830151] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 5560.830224] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 5560.830328] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[ 5560.830387] [drm:intel_power_well_enable [i915]] enabling DC off
>[ 5560.830444] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[ 5560.830496] [drm:intel_power_well_enable [i915]] enabling power well 2
>[ 5561.113441] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 5561.113521] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 5561.307874] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [CRTC:37:pipe A] flip_done timed out
>[ 5565.874226] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 5565.874307] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 5566.143664] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 5566.143745] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 5571.548113] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [CONNECTOR:49:eDP-1] flip_done timed out
>[ 5571.717210] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 5571.717290] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 5571.986532] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 5571.986613] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 5577.560040] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 5577.560120] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 5577.829192] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 5577.829273] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 5581.788025] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [PLANE:28:plane 1A] flip_done timed out
>[ 5581.788132] [drm:intel_edp_backlight_off [i915]] 
>[ 5581.996068] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0
>[ 5581.996202] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 5582.007195] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[ 5582.007352] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b
>[ 5582.007625] [drm:intel_edp_panel_off.part.31 [i915]] Turn eDP port A panel power off
>[ 5582.007727] [drm:intel_edp_panel_off.part.31 [i915]] Wait for panel power off time
>[ 5582.007889] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000003 control 00000060
>[ 5582.060721] [drm:wait_panel_status [i915]] Wait complete
>[ 5582.060784] [drm:intel_power_well_disable [i915]] disabling DDI A/E IO power well
>[ 5582.060870] [drm:intel_disable_shared_dpll [i915]] disable DPLL 0 (active 1, on? 1) for crtc 37
>[ 5582.060944] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 0
>[ 5582.061035] [drm:intel_atomic_commit_tail [i915]] [ENCODER:48:DDI A]
>[ 5582.061106] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI B]
>[ 5582.061171] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[ 5582.061234] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[ 5582.061296] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DDI C]
>[ 5582.061357] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST A]
>[ 5582.061417] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST B]
>[ 5582.061477] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI D]
>[ 5582.061537] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[ 5582.061596] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[ 5582.061661] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:49:eDP-1]
>[ 5582.061727] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[ 5582.061792] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[ 5582.061854] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[ 5582.061916] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[ 5582.061991] [drm:intel_atomic_commit_tail [i915]] [CRTC:37:pipe A]
>[ 5582.062112] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[ 5582.062571] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 00 00 04 00 0f 00 04
>[ 5582.067388] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010
>[ 5582.067468] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[ 5582.067542] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0
>[ 5582.090898] [drm:intel_power_well_disable [i915]] disabling power well 2
>[ 5582.090951] [drm:intel_power_well_disable [i915]] disabling DC off
>[ 5582.090997] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[ 5582.091042] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[ 5582.091475] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 5582.091541] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[ 5582.091601] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[ 5582.091644] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 5582.091685] [drm:intel_power_well_enable [i915]] enabling DC off
>[ 5582.092002] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[ 5582.092057] [drm:intel_power_well_enable [i915]] enabling power well 2
>[ 5582.092544] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 00 00 04 00 0f 00 04
>[ 5582.093926] [drm:intel_power_well_disable [i915]] disabling power well 2
>[ 5582.093975] [drm:intel_power_well_disable [i915]] disabling DC off
>[ 5582.094018] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[ 5582.094061] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[ 5582.094497] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 5582.095662] [drm:drm_mode_addfb2 [drm]] [FB:91]
>[ 5582.096688] [drm:drm_mode_addfb2 [drm]] [FB:102]
>[ 5582.097826] [drm:drm_mode_addfb2 [drm]] [FB:103]
>[ 5582.098658] [drm:drm_mode_addfb2 [drm]] [FB:104]
>[ 5582.113079] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[ 5582.113086] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[ 5582.113113] [drm:intel_atomic_check [i915]] [CONNECTOR:49:eDP-1] checking for sink bpp constrains
>[ 5582.113126] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 5582.113133] [drm:drm_mode_debug_printmodeline [drm]] Modeline 52:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[ 5582.113147] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 138780KHz
>[ 5582.113163] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24
>[ 5582.113174] [drm:intel_dp_compute_config [i915]] DP link bw required 416340 available 540000
>[ 5582.113186] [drm:intel_dp_compute_config [i915]] PSR disable by flag
>[ 5582.113198] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 5582.113211] [drm:intel_dump_pipe_config [i915]] [CRTC:37:pipe A][modeset]
>[ 5582.113223] [drm:intel_dump_pipe_config [i915]] output_types: EDP (0x100)
>[ 5582.113234] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0
>[ 5582.113246] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 6467616, gmch_n: 8388608, link_m: 269484, link_n: 524288, tu: 64
>[ 5582.113257] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[ 5582.113267] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 5582.113273] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[ 5582.113283] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 5582.113289] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[ 5582.113300] [drm:intel_dump_pipe_config [i915]] crtc timings: 138780 1920 1966 1996 2080 1080 1082 1086 1112, type: 0x48 flags: 0xa
>[ 5582.113311] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 138780
>[ 5582.113321] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[ 5582.113332] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 5582.113342] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 5582.113352] [drm:intel_dump_pipe_config [i915]] dpll_hw_state: ctrl1: 0x3, cfgcr1: 0x0, cfgcr2: 0x0
>[ 5582.113362] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 5582.113372] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 1A] disabled, scaler_id = -1
>[ 5582.113382] [drm:intel_dump_pipe_config [i915]] [PLANE:31:plane 2A] disabled, scaler_id = -1
>[ 5582.113392] [drm:intel_dump_pipe_config [i915]] [PLANE:34:cursor A] disabled, scaler_id = -1
>[ 5582.113405] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 5582.113417] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[ 5582.113431] [drm:intel_find_shared_dpll [i915]] [CRTC:37:pipe A] allocated DPLL 0
>[ 5582.113443] [drm:intel_reference_shared_dpll [i915]] using DPLL 0 for pipe A
>[ 5582.114398] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 5582.114407] [drm:intel_power_well_enable [i915]] enabling DC off
>[ 5582.114705] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[ 5582.114723] [drm:intel_atomic_commit_tail [i915]] [ENCODER:48:DDI A]
>[ 5582.114736] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI B]
>[ 5582.114749] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[ 5582.114762] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[ 5582.114791] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DDI C]
>[ 5582.114802] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST A]
>[ 5582.114813] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST B]
>[ 5582.114825] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI D]
>[ 5582.114837] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[ 5582.114866] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[ 5582.114894] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[ 5582.114906] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[ 5582.114918] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[ 5582.114929] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[ 5582.114942] [drm:intel_enable_shared_dpll [i915]] enable DPLL 0 (active 1, on? 0) for crtc 37
>[ 5582.114954] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 0
>[ 5582.114973] [drm:edp_panel_on [i915]] Turn eDP port A panel power on
>[ 5582.114998] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle
>[ 5582.683954] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 00000000 control 00000060
>[ 5582.684036] [drm:wait_panel_status [i915]] Wait complete
>[ 5582.684153] [drm:edp_panel_on [i915]] Wait for panel power on
>[ 5582.684280] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 00000063
>[ 5582.716466] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010
>[ 5582.716528] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[ 5582.716587] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1
>[ 5582.716666] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[ 5582.885555] [drm:wait_panel_status [i915]] Wait complete
>[ 5582.885612] [drm:intel_power_well_enable [i915]] enabling DDI A/E IO power well
>[ 5582.885703] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[ 5582.885845] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b
>[ 5582.887050] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 5582.887114] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 5582.887170] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 5582.887228] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 5582.887937] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 5582.887992] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 5582.888991] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 5582.889046] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:49:eDP-1] Link Training Passed at Link Rate = 270000, Lane count = 2
>[ 5582.889683] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 5582.889748] [drm:intel_edp_backlight_on [i915]] 
>[ 5582.889805] [drm:intel_panel_enable_backlight [i915]] pipe A
>[ 5582.889887] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 120000
>[ 5582.895943] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS
>[ 5583.379269] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 5583.379350] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 5583.379475] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[ 5583.379543] [drm:intel_power_well_enable [i915]] enabling power well 2
>[ 5583.640145] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 5583.640227] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 5586.140112] [drm:edp_panel_vdd_off_sync [i915]] Turning eDP port A VDD off
>[ 5586.140259] [drm:edp_panel_vdd_off_sync [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x00000067
>[ 5589.217444] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 5589.217525] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 5589.477668] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 5589.477749] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 5593.052015] [drm:drm_atomic_helper_wait_for_flip_done [drm_kms_helper]] *ERROR* [CRTC:37:pipe A] flip_done timed out
>[ 5593.052160] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:49:eDP-1]
>[ 5593.052257] [drm:intel_atomic_commit_tail [i915]] [CRTC:37:pipe A]
>[ 5593.052351] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[ 5593.052925] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 00 00 04 00 0f 00 04
>[ 5593.054321] [drm:intel_power_well_disable [i915]] disabling power well 2
>[ 5593.054372] [drm:intel_power_well_disable [i915]] disabling DC off
>[ 5593.054417] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[ 5593.054460] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[ 5593.054525] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[ 5593.054568] [drm:intel_power_well_enable [i915]] enabling DC off
>[ 5593.054610] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[ 5593.054656] [drm:intel_power_well_enable [i915]] enabling power well 2
>[ 5593.055128] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 00 00 04 00 0f 00 04
>[ 5593.056544] [drm:intel_power_well_disable [i915]] disabling power well 2
>[ 5593.056596] [drm:intel_power_well_disable [i915]] disabling DC off
>[ 5593.056646] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[ 5593.056693] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[ 5593.089653] [drm:intel_power_well_enable [i915]] enabling DC off
>[ 5593.089695] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[ 5593.089773] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[ 5593.089910] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006f
>[ 5593.289984] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped
>[ 5593.290028] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[ 5593.290057] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[ 5595.046053] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 5595.046135] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 5595.046256] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[ 5595.046323] [drm:intel_power_well_enable [i915]] enabling power well 2
>[ 5595.306324] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 5595.306405] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 5596.380184] [drm:edp_panel_vdd_off_sync [i915]] Turning eDP port A VDD off
>[ 5596.380328] [drm:edp_panel_vdd_off_sync [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x00000067
>[ 5600.880052] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 5600.880133] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 5601.140420] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 5601.140502] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 5603.291968] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [CRTC:37:pipe A] flip_done timed out
>[ 5606.708086] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 5606.708159] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 5606.970017] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 5606.970089] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 5612.542285] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 5612.542366] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 5612.804595] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 5612.804676] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 5613.532011] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [CONNECTOR:49:eDP-1] flip_done timed out
>[ 5618.373880] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 5618.373961] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 5618.635121] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 5618.635202] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 5623.772102] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [PLANE:28:plane 1A] flip_done timed out
>[ 5624.210125] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 5624.210205] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 5624.470646] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 5624.470728] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 5630.046278] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 5630.046351] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 5630.307350] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 5630.307431] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 5634.012099] [drm:drm_atomic_helper_wait_for_flip_done [drm_kms_helper]] *ERROR* [CRTC:37:pipe A] flip_done timed out
>[ 5634.012701] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 00 00 04 00 0f 00 04
>[ 5634.014107] [drm:intel_power_well_disable [i915]] disabling power well 2
>[ 5634.014164] [drm:intel_power_well_disable [i915]] disabling DC off
>[ 5634.014215] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[ 5634.014263] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[ 5634.014338] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[ 5634.014386] [drm:intel_power_well_enable [i915]] enabling DC off
>[ 5634.014434] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[ 5634.014486] [drm:intel_power_well_enable [i915]] enabling power well 2
>[ 5634.014970] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 00 00 04 00 0f 00 04
>[ 5634.016385] [drm:intel_power_well_disable [i915]] disabling power well 2
>[ 5634.016437] [drm:intel_power_well_disable [i915]] disabling DC off
>[ 5634.016486] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[ 5634.016533] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[ 5634.055865] [drm:intel_power_well_enable [i915]] enabling DC off
>[ 5634.055918] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[ 5634.056007] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[ 5634.056151] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006f
>[ 5634.255965] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped
>[ 5634.256015] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[ 5634.256046] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[ 5635.878037] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 5635.878119] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 5635.878239] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[ 5635.878305] [drm:intel_power_well_enable [i915]] enabling power well 2
>[ 5636.138449] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 5636.138530] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 5637.339932] [drm:edp_panel_vdd_off_sync [i915]] Turning eDP port A VDD off
>[ 5637.340077] [drm:edp_panel_vdd_off_sync [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x00000067
>[ 5641.709843] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 5641.709925] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 5641.970875] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 5641.970956] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 5644.507829] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [CRTC:37:pipe A] flip_done timed out
>[ 5647.539409] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 5647.539482] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 5647.800202] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 5647.800273] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 5653.370684] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 5653.370765] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 5653.631746] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 5653.631828] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 5654.748104] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [CONNECTOR:49:eDP-1] flip_done timed out
>[ 5659.200522] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 5659.200603] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 5659.460591] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 5659.460672] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 5664.988025] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [PLANE:28:plane 1A] flip_done timed out
>[ 5665.028167] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 5665.028248] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 5665.289855] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 5665.289936] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 5670.861281] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 5670.861354] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 5671.121811] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 5671.121892] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 5675.227812] [drm:drm_atomic_helper_wait_for_flip_done [drm_kms_helper]] *ERROR* [CRTC:37:pipe A] flip_done timed out
>[ 5675.228383] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 00 00 04 00 0f 00 04
>[ 5675.229772] [drm:intel_power_well_disable [i915]] disabling power well 2
>[ 5675.229824] [drm:intel_power_well_disable [i915]] disabling DC off
>[ 5675.229870] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[ 5675.229914] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[ 5675.229981] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[ 5675.230023] [drm:intel_power_well_enable [i915]] enabling DC off
>[ 5675.230066] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[ 5675.230112] [drm:intel_power_well_enable [i915]] enabling power well 2
>[ 5675.230590] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 00 00 04 00 0f 00 04
>[ 5675.232027] [drm:intel_power_well_disable [i915]] disabling power well 2
>[ 5675.232082] [drm:intel_power_well_disable [i915]] disabling DC off
>[ 5675.232131] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[ 5675.232179] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[ 5675.271823] [drm:intel_power_well_enable [i915]] enabling DC off
>[ 5675.271876] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[ 5675.271965] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[ 5675.272111] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006f
>[ 5675.471888] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped
>[ 5675.471935] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[ 5675.471967] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[ 5676.689460] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 5676.689533] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 5676.689649] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[ 5676.689713] [drm:intel_power_well_enable [i915]] enabling power well 2
>[ 5676.950446] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 5676.950527] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 5678.555933] [drm:edp_panel_vdd_off_sync [i915]] Turning eDP port A VDD off
>[ 5678.556082] [drm:edp_panel_vdd_off_sync [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x00000067
>[ 5682.521402] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 5682.521474] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 5682.781119] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 5682.781200] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 5685.724064] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [CRTC:37:pipe A] flip_done timed out
>[ 5688.351450] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 5688.351531] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 5688.610944] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 5688.611025] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 5694.186038] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 5694.186119] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 5694.446250] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 5694.446332] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 5695.963992] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [CONNECTOR:49:eDP-1] flip_done timed out
>[ 5697.876529] [IGT] kms_flip: executing
>[ 5697.916637] [IGT] kms_flip: exiting, ret=77
>[ 5697.952489] [IGT] kms_flip: executing
>[ 5698.025281] [IGT] kms_flip: exiting, ret=77
>[ 5698.064322] [IGT] kms_flip: executing
>[ 5698.116528] [IGT] kms_flip: exiting, ret=77
>[ 5698.171159] [IGT] kms_flip: executing
>[ 5698.225138] [IGT] kms_flip: exiting, ret=77
>[ 5698.296012] [IGT] kms_flip: executing
>[ 5698.345120] [IGT] kms_flip: exiting, ret=77
>[ 5700.009491] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 5700.009573] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 5700.271461] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 5700.271543] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 5705.847508] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 5705.847590] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 5706.106088] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 5706.106170] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 5706.204112] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [PLANE:28:plane 1A] flip_done timed out
>[ 5711.666523] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 5711.666605] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 5711.927869] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 5711.927951] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 5716.444000] [drm:drm_atomic_helper_wait_for_flip_done [drm_kms_helper]] *ERROR* [CRTC:37:pipe A] flip_done timed out
>[ 5716.444599] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 00 00 04 00 0f 00 04
>[ 5716.446007] [drm:intel_power_well_disable [i915]] disabling power well 2
>[ 5716.446064] [drm:intel_power_well_disable [i915]] disabling DC off
>[ 5716.446115] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[ 5716.446163] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[ 5716.446238] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[ 5716.446286] [drm:intel_power_well_enable [i915]] enabling DC off
>[ 5716.446334] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[ 5716.446385] [drm:intel_power_well_enable [i915]] enabling power well 2
>[ 5716.446870] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 00 00 04 00 0f 00 04
>[ 5716.448306] [drm:intel_power_well_disable [i915]] disabling power well 2
>[ 5716.448360] [drm:intel_power_well_disable [i915]] disabling DC off
>[ 5716.448410] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[ 5716.448458] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[ 5716.487727] [drm:intel_power_well_enable [i915]] enabling DC off
>[ 5716.487809] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[ 5716.487908] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[ 5716.488060] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006f
>[ 5716.687828] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped
>[ 5716.687948] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[ 5716.688038] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 5716.688096] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[ 5717.501354] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 5717.501435] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 5717.501563] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[ 5717.501634] [drm:intel_power_well_enable [i915]] enabling power well 2
>[ 5717.761662] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 5717.761744] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 5719.771932] [drm:edp_panel_vdd_off_sync [i915]] Turning eDP port A VDD off
>[ 5719.772076] [drm:edp_panel_vdd_off_sync [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x00000067
>[ 5723.325923] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 5723.326004] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 5723.585941] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 5723.586022] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 5726.939970] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [CRTC:37:pipe A] flip_done timed out
>[ 5729.158954] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 5729.159035] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 5729.419981] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 5729.420062] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 5734.990154] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 5734.990235] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 5735.250485] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 5735.250566] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 5737.180122] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [CONNECTOR:49:eDP-1] flip_done timed out
>[ 5740.820339] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 5740.820420] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 5741.081628] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 5741.081710] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 5746.654617] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 5746.654698] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 5746.915752] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 5746.915833] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 5747.420005] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [PLANE:28:plane 1A] flip_done timed out
>[ 5747.420111] [drm:intel_edp_backlight_off [i915]] 
>[ 5747.628065] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0
>[ 5747.628203] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 5747.639191] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[ 5747.639353] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b
>[ 5747.639627] [drm:intel_edp_panel_off.part.31 [i915]] Turn eDP port A panel power off
>[ 5747.639729] [drm:intel_edp_panel_off.part.31 [i915]] Wait for panel power off time
>[ 5747.639910] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000003 control 00000060
>[ 5747.690228] [drm:wait_panel_status [i915]] Wait complete
>[ 5747.690291] [drm:intel_power_well_disable [i915]] disabling DDI A/E IO power well
>[ 5747.690376] [drm:intel_disable_shared_dpll [i915]] disable DPLL 0 (active 1, on? 1) for crtc 37
>[ 5747.690451] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 0
>[ 5747.690542] [drm:intel_atomic_commit_tail [i915]] [ENCODER:48:DDI A]
>[ 5747.690613] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI B]
>[ 5747.690679] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[ 5747.690743] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[ 5747.690806] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DDI C]
>[ 5747.690867] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST A]
>[ 5747.690928] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST B]
>[ 5747.690989] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI D]
>[ 5747.691049] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[ 5747.691108] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[ 5747.691173] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:49:eDP-1]
>[ 5747.691240] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[ 5747.691304] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[ 5747.691368] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[ 5747.691428] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[ 5747.691504] [drm:intel_atomic_commit_tail [i915]] [CRTC:37:pipe A]
>[ 5747.691622] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[ 5747.692134] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 00 00 04 00 0f 00 04
>[ 5747.693550] [drm:intel_power_well_disable [i915]] disabling power well 2
>[ 5747.693601] [drm:intel_power_well_disable [i915]] disabling DC off
>[ 5747.693626] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[ 5747.693635] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[ 5747.693637] Setting dangerous option enable_psr - tainting kernel
>[ 5747.693645] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 5747.693658] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[ 5747.693667] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 5747.693676] [drm:intel_power_well_enable [i915]] enabling DC off
>[ 5747.694035] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[ 5747.694591] [drm:intel_power_well_enable [i915]] enabling power well 2
>[ 5747.694602] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[ 5747.695006] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 00 00 04 00 0f 00 04
>[ 5747.696265] [drm:intel_power_well_disable [i915]] disabling power well 2
>[ 5747.696271] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[ 5747.696284] [drm:intel_power_well_disable [i915]] disabling DC off
>[ 5747.696302] [drm:intel_atomic_check [i915]] [CONNECTOR:49:eDP-1] checking for sink bpp constrains
>[ 5747.696318] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 5747.696325] [drm:drm_mode_debug_printmodeline [drm]] Modeline 52:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[ 5747.696336] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[ 5747.696346] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[ 5747.696362] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 138780KHz
>[ 5747.696374] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 5747.696389] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24
>[ 5747.696403] [drm:intel_dp_compute_config [i915]] DP link bw required 416340 available 540000
>[ 5747.696418] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 5747.696433] [drm:intel_dump_pipe_config [i915]] [CRTC:37:pipe A][modeset]
>[ 5747.696447] [drm:intel_dump_pipe_config [i915]] output_types: EDP (0x100)
>[ 5747.696460] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0
>[ 5747.696473] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 6467616, gmch_n: 8388608, link_m: 269484, link_n: 524288, tu: 64
>[ 5747.696486] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[ 5747.696498] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 5747.696504] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[ 5747.696517] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 5747.696523] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[ 5747.696536] [drm:intel_dump_pipe_config [i915]] crtc timings: 138780 1920 1966 1996 2080 1080 1082 1086 1112, type: 0x48 flags: 0xa
>[ 5747.696549] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 138780
>[ 5747.696561] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[ 5747.696573] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 5747.696585] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 5747.696597] [drm:intel_dump_pipe_config [i915]] dpll_hw_state: ctrl1: 0x3, cfgcr1: 0x0, cfgcr2: 0x0
>[ 5747.696609] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 5747.696621] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 1A] disabled, scaler_id = -1
>[ 5747.696633] [drm:intel_dump_pipe_config [i915]] [PLANE:31:plane 2A] disabled, scaler_id = -1
>[ 5747.696645] [drm:intel_dump_pipe_config [i915]] [PLANE:34:cursor A] disabled, scaler_id = -1
>[ 5747.696660] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 5747.696673] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[ 5747.696690] [drm:intel_find_shared_dpll [i915]] [CRTC:37:pipe A] allocated DPLL 0
>[ 5747.696703] [drm:intel_reference_shared_dpll [i915]] using DPLL 0 for pipe A
>[ 5747.697098] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 5747.697110] [drm:intel_power_well_enable [i915]] enabling DC off
>[ 5747.697371] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[ 5747.697392] [drm:intel_atomic_commit_tail [i915]] [ENCODER:48:DDI A]
>[ 5747.697408] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI B]
>[ 5747.697424] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[ 5747.697438] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[ 5747.697452] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DDI C]
>[ 5747.697466] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST A]
>[ 5747.697479] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST B]
>[ 5747.697492] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI D]
>[ 5747.697506] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[ 5747.697519] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[ 5747.697534] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[ 5747.697549] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[ 5747.697563] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[ 5747.697578] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[ 5747.697594] [drm:intel_enable_shared_dpll [i915]] enable DPLL 0 (active 1, on? 0) for crtc 37
>[ 5747.697608] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 0
>[ 5747.697631] [drm:edp_panel_on [i915]] Turn eDP port A panel power on
>[ 5747.697658] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle
>[ 5747.699354] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010
>[ 5747.699372] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[ 5747.699388] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0
>[ 5747.699407] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[ 5748.315999] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 00000000 control 00000060
>[ 5748.316093] [drm:wait_panel_status [i915]] Wait complete
>[ 5748.316223] [drm:edp_panel_on [i915]] Wait for panel power on
>[ 5748.316345] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 00000063
>[ 5748.348322] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010
>[ 5748.348395] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[ 5748.348461] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1
>[ 5748.348558] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[ 5748.516979] [drm:wait_panel_status [i915]] Wait complete
>[ 5748.517029] [drm:intel_power_well_enable [i915]] enabling DDI A/E IO power well
>[ 5748.517109] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[ 5748.517245] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b
>[ 5748.518448] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 5748.518511] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 5748.518568] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 5748.518625] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 5748.519329] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 5748.519382] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 5748.520385] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 5748.520441] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:49:eDP-1] Link Training Passed at Link Rate = 270000, Lane count = 2
>[ 5748.521078] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 5748.521142] [drm:intel_edp_backlight_on [i915]] 
>[ 5748.521198] [drm:intel_panel_enable_backlight [i915]] pipe A
>[ 5748.521281] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 120000
>[ 5748.532054] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS
>[ 5751.771934] [drm:edp_panel_vdd_off_sync [i915]] Turning eDP port A VDD off
>[ 5751.772081] [drm:edp_panel_vdd_off_sync [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x00000067
>[ 5752.486849] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 5752.486923] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 5752.487035] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[ 5752.487095] [drm:intel_power_well_enable [i915]] enabling power well 2
>[ 5752.748664] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 5752.748746] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 5758.315169] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 5758.315240] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 5758.575927] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 5758.575999] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 5758.683834] [drm:drm_atomic_helper_wait_for_flip_done [drm_kms_helper]] *ERROR* [CRTC:37:pipe A] flip_done timed out
>[ 5758.683939] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:49:eDP-1]
>[ 5758.684014] [drm:intel_atomic_commit_tail [i915]] [CRTC:37:pipe A]
>[ 5758.684102] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[ 5758.684668] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 00 00 04 00 0f 00 04
>[ 5758.686053] [drm:intel_power_well_disable [i915]] disabling power well 2
>[ 5758.686103] [drm:intel_power_well_disable [i915]] disabling DC off
>[ 5758.686149] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[ 5758.686191] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[ 5758.686257] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[ 5758.686299] [drm:intel_power_well_enable [i915]] enabling DC off
>[ 5758.686340] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[ 5758.686387] [drm:intel_power_well_enable [i915]] enabling power well 2
>[ 5758.686861] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 00 00 04 00 0f 00 04
>[ 5758.688282] [drm:intel_power_well_disable [i915]] disabling power well 2
>[ 5758.688331] [drm:intel_power_well_disable [i915]] disabling DC off
>[ 5758.688376] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[ 5758.688420] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[ 5758.721062] [drm:intel_power_well_enable [i915]] enabling DC off
>[ 5758.721114] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[ 5758.721201] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[ 5758.721346] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006f
>[ 5758.921379] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped
>[ 5759.171372] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped
>[ 5762.268085] [drm:edp_panel_vdd_off_sync [i915]] Turning eDP port A VDD off
>[ 5762.268229] [drm:edp_panel_vdd_off_sync [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x00000067
>[ 5762.268286] [drm:intel_power_well_disable [i915]] disabling DC off
>[ 5762.268342] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[ 5762.268395] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[ 5764.143284] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 5764.143356] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 5764.143465] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[ 5764.143529] [drm:intel_power_well_enable [i915]] enabling DC off
>[ 5764.143594] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[ 5764.143668] [drm:intel_power_well_enable [i915]] enabling power well 2
>[ 5764.144172] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 00 00 04 00 0f 00 04
>[ 5764.144517] [drm:intel_power_well_disable [i915]] disabling power well 2
>[ 5764.144565] [drm:intel_power_well_disable [i915]] disabling DC off
>[ 5764.144609] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[ 5764.144651] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[ 5764.144722] [drm:i915_hotplug_work_func [i915]] running encoder hotplug functions
>[ 5764.144784] [drm:i915_hotplug_work_func [i915]] Connector DP-1 (pin 5) received hotplug event.
>[ 5764.144843] [drm:intel_dp_detect [i915]] [CONNECTOR:57:DP-1]
>[ 5764.144887] [drm:intel_power_well_enable [i915]] enabling DC off
>[ 5764.144930] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[ 5764.144977] [drm:intel_power_well_enable [i915]] enabling power well 2
>[ 5764.145359] [drm:lspcon_wake_native_aux_ch [i915]] Native AUX CH up, DPCD version: 1.2
>[ 5764.145428] [drm:lspcon_resume [i915]] LSPCON recovering in PCON mode after 0 ms
>[ 5764.145866] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5764.147121] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5764.148486] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5764.149728] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5764.150980] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5764.151960] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[ 5764.152438] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 00 00 04 00 0f 00 04
>[ 5764.152784] [drm:intel_power_well_disable [i915]] disabling power well 2
>[ 5764.152835] [drm:intel_power_well_disable [i915]] disabling DC off
>[ 5764.152882] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[ 5764.152925] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[ 5764.152992] [drm:i915_hotplug_work_func [i915]] [CONNECTOR:57:DP-1] status updated from connected to disconnected
>[ 5764.403273] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 5764.403354] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 5764.403480] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[ 5764.403551] [drm:intel_power_well_enable [i915]] enabling DC off
>[ 5764.403626] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[ 5764.403711] [drm:intel_power_well_enable [i915]] enabling power well 2
>[ 5764.404267] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 00 00 04 00 0f 00 04
>[ 5764.405033] [drm:intel_power_well_disable [i915]] disabling power well 2
>[ 5764.405087] [drm:intel_power_well_disable [i915]] disabling DC off
>[ 5764.405137] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[ 5764.405185] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[ 5764.405265] [drm:i915_hotplug_work_func [i915]] running encoder hotplug functions
>[ 5764.405349] [drm:i915_hotplug_work_func [i915]] Connector DP-1 (pin 5) received hotplug event.
>[ 5764.405409] [drm:intel_dp_detect [i915]] [CONNECTOR:57:DP-1]
>[ 5764.405453] [drm:intel_power_well_enable [i915]] enabling DC off
>[ 5764.405496] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[ 5764.405542] [drm:intel_power_well_enable [i915]] enabling power well 2
>[ 5764.405920] [drm:lspcon_wake_native_aux_ch [i915]] Native AUX CH up, DPCD version: 1.2
>[ 5764.405990] [drm:lspcon_resume [i915]] LSPCON recovering in PCON mode after 0 ms
>[ 5764.406429] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5764.407679] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5764.408934] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5764.410176] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5764.411427] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5764.412244] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[ 5764.412717] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 00 00 04 00 0f 00 04
>[ 5764.413491] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>[ 5764.413548] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000
>[ 5764.413602] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000
>[ 5764.414002] [drm:drm_dp_read_desc [drm_kms_helper]] DP branch: OUI 00-60-ad dev-ID MC2800 HW-rev 2.2 SW-rev 1.70 quirks 0x0000
>[ 5764.414354] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[ 5764.415125] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5764.416550] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5764.417774] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5764.419015] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5764.420312] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5764.421504] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5764.422753] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5764.424015] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5764.425257] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5764.426632] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5764.428023] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5764.429398] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5764.430773] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5764.432158] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5764.433535] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5764.434913] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5764.436319] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5764.437574] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5764.438851] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5764.440107] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5764.441349] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5764.442724] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5764.444108] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5764.445482] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5764.446856] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5764.448324] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5764.449700] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5764.451080] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5764.452478] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5764.453622] [drm:intel_power_well_disable [i915]] disabling power well 2
>[ 5764.453675] [drm:intel_power_well_disable [i915]] disabling DC off
>[ 5764.453721] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[ 5764.453764] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[ 5764.453833] [drm:i915_hotplug_work_func [i915]] [CONNECTOR:57:DP-1] status updated from disconnected to connected
>[ 5765.458413] [IGT] kms_frontbuffer_tracking: executing
>[ 5765.516457] [IGT] kms_frontbuffer_tracking: exiting, ret=77
>[ 5765.557139] [IGT] kms_frontbuffer_tracking: executing
>[ 5765.624561] [IGT] kms_frontbuffer_tracking: exiting, ret=77
>[ 5769.179977] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [CRTC:37:pipe A] flip_done timed out
>[ 5769.221198] [drm:intel_power_well_enable [i915]] enabling DC off
>[ 5769.221258] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[ 5769.221354] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[ 5769.221506] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006f
>[ 5769.421385] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped
>[ 5769.671194] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped
>[ 5769.921387] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped
>[ 5769.972505] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 5769.972585] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 5769.972685] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[ 5769.972743] [drm:intel_power_well_enable [i915]] enabling power well 2
>[ 5769.973260] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 00 00 04 00 0f 00 04
>[ 5769.973617] [drm:intel_power_well_disable [i915]] disabling power well 2
>[ 5769.973699] [drm:i915_hotplug_work_func [i915]] running encoder hotplug functions
>[ 5769.973768] [drm:i915_hotplug_work_func [i915]] Connector DP-1 (pin 5) received hotplug event.
>[ 5769.973833] [drm:intel_dp_detect [i915]] [CONNECTOR:57:DP-1]
>[ 5769.973884] [drm:intel_power_well_enable [i915]] enabling power well 2
>[ 5769.974272] [drm:lspcon_wake_native_aux_ch [i915]] Native AUX CH up, DPCD version: 1.2
>[ 5769.974347] [drm:lspcon_resume [i915]] LSPCON recovering in PCON mode after 0 ms
>[ 5769.974789] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5769.976194] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5769.977420] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5769.978633] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5769.979870] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5769.980748] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[ 5769.981224] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 00 00 04 00 0f 00 04
>[ 5769.981570] [drm:intel_power_well_disable [i915]] disabling power well 2
>[ 5769.981641] [drm:i915_hotplug_work_func [i915]] [CONNECTOR:57:DP-1] status updated from connected to disconnected
>[ 5770.234670] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 5770.234742] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 5770.234844] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[ 5770.234906] [drm:intel_power_well_enable [i915]] enabling power well 2
>[ 5770.235402] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 00 00 04 00 0f 00 04
>[ 5770.236169] [drm:intel_power_well_disable [i915]] disabling power well 2
>[ 5770.236244] [drm:i915_hotplug_work_func [i915]] running encoder hotplug functions
>[ 5770.236306] [drm:i915_hotplug_work_func [i915]] Connector DP-1 (pin 5) received hotplug event.
>[ 5770.236364] [drm:intel_dp_detect [i915]] [CONNECTOR:57:DP-1]
>[ 5770.236409] [drm:intel_power_well_enable [i915]] enabling power well 2
>[ 5770.236784] [drm:lspcon_wake_native_aux_ch [i915]] Native AUX CH up, DPCD version: 1.2
>[ 5770.236853] [drm:lspcon_resume [i915]] LSPCON recovering in PCON mode after 0 ms
>[ 5770.237289] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5770.238560] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5770.240027] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5770.241273] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5770.242512] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5770.243352] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[ 5770.243966] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 00 00 04 00 0f 00 04
>[ 5770.244746] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>[ 5770.244806] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000
>[ 5770.244862] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000
>[ 5770.245261] [drm:drm_dp_read_desc [drm_kms_helper]] DP branch: OUI 00-60-ad dev-ID MC2800 HW-rev 2.2 SW-rev 1.70 quirks 0x0000
>[ 5770.245615] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[ 5770.246386] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5770.247608] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5770.248835] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5770.250046] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5770.251257] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5770.252440] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5770.253692] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5770.254953] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5770.256267] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5770.257645] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5770.259021] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5770.260400] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5770.261746] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5770.263089] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5770.264459] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5770.265826] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5770.267165] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5770.268486] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5770.269738] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5770.271009] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5770.272323] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5770.273690] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5770.275066] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5770.276471] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5770.277819] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5770.279158] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5770.280617] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5770.281994] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5770.283363] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5770.284468] [drm:intel_power_well_disable [i915]] disabling power well 2
>[ 5770.284544] [drm:i915_hotplug_work_func [i915]] [CONNECTOR:57:DP-1] status updated from disconnected to connected
>[ 5771.121156] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped
>[ 5771.371172] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped
>[ 5773.137838] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped
>[ 5773.387809] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped
>[ 5775.121076] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped
>[ 5775.371073] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped
>[ 5775.806520] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 5775.806592] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 5775.806676] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[ 5775.806727] [drm:intel_power_well_enable [i915]] enabling power well 2
>[ 5775.807215] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 00 00 04 00 0f 00 04
>[ 5775.807563] [drm:intel_power_well_disable [i915]] disabling power well 2
>[ 5775.807638] [drm:i915_hotplug_work_func [i915]] running encoder hotplug functions
>[ 5775.807701] [drm:i915_hotplug_work_func [i915]] Connector DP-1 (pin 5) received hotplug event.
>[ 5775.807760] [drm:intel_dp_detect [i915]] [CONNECTOR:57:DP-1]
>[ 5775.807841] [drm:intel_power_well_enable [i915]] enabling power well 2
>[ 5775.808234] [drm:lspcon_wake_native_aux_ch [i915]] Native AUX CH up, DPCD version: 1.2
>[ 5775.808303] [drm:lspcon_resume [i915]] LSPCON recovering in PCON mode after 0 ms
>[ 5775.808743] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5775.810003] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5775.811228] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5775.812544] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5775.813795] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5775.814671] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[ 5775.815147] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 00 00 04 00 0f 00 04
>[ 5775.815494] [drm:intel_power_well_disable [i915]] disabling power well 2
>[ 5775.815566] [drm:i915_hotplug_work_func [i915]] [CONNECTOR:57:DP-1] status updated from connected to disconnected
>[ 5776.066612] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 5776.066685] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 5776.066790] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[ 5776.066854] [drm:intel_power_well_enable [i915]] enabling power well 2
>[ 5776.067352] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 00 00 04 00 0f 00 04
>[ 5776.068130] [drm:intel_power_well_disable [i915]] disabling power well 2
>[ 5776.068206] [drm:i915_hotplug_work_func [i915]] running encoder hotplug functions
>[ 5776.068267] [drm:i915_hotplug_work_func [i915]] Connector DP-1 (pin 5) received hotplug event.
>[ 5776.068326] [drm:intel_dp_detect [i915]] [CONNECTOR:57:DP-1]
>[ 5776.068371] [drm:intel_power_well_enable [i915]] enabling power well 2
>[ 5776.068748] [drm:lspcon_wake_native_aux_ch [i915]] Native AUX CH up, DPCD version: 1.2
>[ 5776.068818] [drm:lspcon_resume [i915]] LSPCON recovering in PCON mode after 0 ms
>[ 5776.069255] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5776.070528] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5776.072037] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5776.073281] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5776.074535] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5776.075407] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[ 5776.075967] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 00 00 04 00 0f 00 04
>[ 5776.076745] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>[ 5776.076802] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000
>[ 5776.076857] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000
>[ 5776.077258] [drm:drm_dp_read_desc [drm_kms_helper]] DP branch: OUI 00-60-ad dev-ID MC2800 HW-rev 2.2 SW-rev 1.70 quirks 0x0000
>[ 5776.077609] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[ 5776.078381] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5776.079602] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5776.080832] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5776.082045] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5776.083295] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5776.084504] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5776.085755] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5776.087005] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5776.088239] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5776.089612] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5776.090991] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5776.092372] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5776.093749] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5776.095124] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5776.096644] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5776.098020] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5776.099389] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5776.100575] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5776.101827] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5776.103078] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5776.104373] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5776.105750] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5776.107126] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5776.108599] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5776.109969] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5776.111348] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5776.112681] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5776.114056] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5776.115425] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5776.116525] [drm:intel_power_well_disable [i915]] disabling power well 2
>[ 5776.116599] [drm:i915_hotplug_work_func [i915]] [CONNECTOR:57:DP-1] status updated from disconnected to connected
>[ 5777.104391] [drm:intel_dp_sink_crc_stop [i915]] TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped
>[ 5777.104527] Setting dangerous option enable_psr - tainting kernel
>[ 5777.104541] Setting dangerous option enable_fbc - tainting kernel
>[ 5780.187922] [drm:edp_panel_vdd_off_sync [i915]] Turning eDP port A VDD off
>[ 5780.188067] [drm:edp_panel_vdd_off_sync [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x00000067
>[ 5780.188124] [drm:intel_power_well_disable [i915]] disabling DC off
>[ 5780.188181] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[ 5780.188233] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[ 5781.639716] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 5781.639789] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 5781.639899] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[ 5781.639971] [drm:intel_power_well_enable [i915]] enabling DC off
>[ 5781.640043] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[ 5781.640107] [drm:intel_power_well_enable [i915]] enabling power well 2
>[ 5781.901311] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 5781.901382] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 5787.355950] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [PLANE:28:plane 1A] flip_done timed out
>[ 5787.478957] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 5787.479039] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 5787.737518] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 5787.737599] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 5793.302863] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 5793.302944] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 5793.563552] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 5793.563635] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 5797.595976] [drm:drm_atomic_helper_wait_for_flip_done [drm_kms_helper]] *ERROR* [CRTC:37:pipe A] flip_done timed out
>[ 5797.596580] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 00 00 04 00 0f 00 04
>[ 5797.597990] [drm:intel_power_well_disable [i915]] disabling power well 2
>[ 5797.598075] [drm:intel_atomic_check [i915]] [CONNECTOR:57:DP-1] checking for sink bpp constrains
>[ 5797.598149] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 5797.598198] [drm:intel_power_well_disable [i915]] disabling DC off
>[ 5797.598250] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[ 5797.598321] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 148500KHz
>[ 5797.598370] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[ 5797.598438] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 5797.598502] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 648000
>[ 5797.598573] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 5797.598643] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[ 5797.598692] [drm:intel_power_well_enable [i915]] enabling DC off
>[ 5797.598758] [drm:intel_dump_pipe_config [i915]] [CRTC:47:pipe B][modeset]
>[ 5797.598822] [drm:intel_dump_pipe_config [i915]] output_types: DP (0x80)
>[ 5797.598868] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[ 5797.598928] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 5797.598974] [drm:intel_power_well_enable [i915]] enabling power well 2
>[ 5797.599035] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5767168, gmch_n: 8388608, link_m: 240298, link_n: 262144, tu: 64
>[ 5797.599092] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[ 5797.599160] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 5797.599190] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[ 5797.599240] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 5797.599266] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[ 5797.599319] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[ 5797.599370] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1080, pixel rate 148500
>[ 5797.599420] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[ 5797.599470] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 5797.599518] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 5797.599566] [drm:intel_dump_pipe_config [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[ 5797.599614] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 5797.599664] [drm:intel_dump_pipe_config [i915]] [PLANE:38:plane 1B] disabled, scaler_id = -1
>[ 5797.599711] [drm:intel_dump_pipe_config [i915]] [PLANE:41:plane 2B] disabled, scaler_id = -1
>[ 5797.599759] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor B] disabled, scaler_id = -1
>[ 5797.599847] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 5797.599910] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[ 5797.599987] [drm:intel_find_shared_dpll [i915]] [CRTC:47:pipe B] allocated DPLL 1
>[ 5797.600048] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[ 5799.134658] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 5799.134730] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 5799.397010] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 5799.397082] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 5804.974270] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 5804.974351] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 5805.233411] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 5805.233492] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 5807.836015] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [CRTC:37:pipe A] flip_done timed out
>[ 5810.805169] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 5810.805251] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 5811.064946] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 5811.065027] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 5816.640264] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 5816.640346] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 5816.900834] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 5816.900915] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 5818.076104] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [CONNECTOR:49:eDP-1] flip_done timed out
>[ 5822.473399] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 5822.473480] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 5822.733845] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 5822.733927] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 5828.301291] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 5828.301373] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 5828.316106] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [PLANE:28:plane 1A] flip_done timed out
>[ 5828.316199] [drm:intel_disable_sagv [i915]] Disabling the SAGV
>[ 5828.316288] [drm:intel_atomic_commit_tail [i915]] [ENCODER:48:DDI A]
>[ 5828.316362] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI B]
>[ 5828.316431] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[ 5828.316496] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[ 5828.316559] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DDI C]
>[ 5828.316620] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST A]
>[ 5828.316680] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST B]
>[ 5828.316739] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI D]
>[ 5828.316798] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[ 5828.316856] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[ 5828.316920] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[ 5828.316988] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[ 5828.317051] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[ 5828.317113] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[ 5828.317189] [drm:intel_fbc_enable [i915]] reserved 16588800 bytes of contiguous stolen space for FBC, threshold: 1
>[ 5828.317255] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 5828.320019] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 2, on? 0) for crtc 47
>[ 5828.320101] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[ 5828.320271] [drm:intel_power_well_enable [i915]] enabling DDI B IO power well
>[ 5828.320884] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5828.322142] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5828.323400] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5828.324609] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5828.325864] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5828.326747] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[ 5828.327744] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 5828.327843] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 5828.327917] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 5828.327989] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 5828.346663] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 5828.346691] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[ 5828.364435] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 5828.364758] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:57:DP-1] Link Training Passed at Link Rate = 162000, Lane count = 4
>[ 5828.365142] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 5828.365209] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS
>[ 5828.566283] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 5828.566364] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 5838.555960] [drm:drm_atomic_helper_wait_for_flip_done [drm_kms_helper]] *ERROR* [CRTC:37:pipe A] flip_done timed out
>[ 5838.556094] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:57:DP-1]
>[ 5838.556180] [drm:intel_atomic_commit_tail [i915]] [CRTC:47:pipe B]
>[ 5838.556278] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[ 5838.556335] [drm:drm_fb_helper_hotplug_event.part.30 [drm_kms_helper]] 
>[ 5838.556347] [drm:drm_setup_crtcs [drm_kms_helper]] 
>[ 5838.556363] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:49:eDP-1]
>[ 5838.556439] [drm:intel_dp_detect [i915]] [CONNECTOR:49:eDP-1]
>[ 5838.556515] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>[ 5838.556582] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[ 5838.556646] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[ 5838.556724] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[ 5838.556865] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006f
>[ 5838.557313] [drm:drm_dp_read_desc [drm_kms_helper]] DP sink: OUI 00-1c-f8 dev-ID  HW-rev 0.1 SW-rev 1.22 quirks 0x0000
>[ 5838.558051] [drm:drm_add_edid_modes [drm]] ELD: no CEA Extension found
>[ 5838.558104] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:49:eDP-1] probed modes :
>[ 5838.558132] [drm:drm_mode_debug_printmodeline [drm]] Modeline 50:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[ 5838.558146] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:57:DP-1]
>[ 5838.558618] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 00 00 04 00 0f 00 04
>[ 5838.559953] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[ 5838.559983] [drm:intel_dp_detect [i915]] [CONNECTOR:57:DP-1]
>[ 5838.560296] [drm:lspcon_wake_native_aux_ch [i915]] Native AUX CH up, DPCD version: 1.2
>[ 5838.560335] [drm:lspcon_resume [i915]] LSPCON recovering in PCON mode after 0 ms
>[ 5838.560748] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5838.562028] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5838.563325] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5838.564472] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5838.565725] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5838.566565] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[ 5838.566963] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 00 00 04 00 0f 00 04
>[ 5838.567641] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>[ 5838.567655] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000
>[ 5838.567668] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000
>[ 5838.568032] [drm:drm_dp_read_desc [drm_kms_helper]] DP branch: OUI 00-60-ad dev-ID MC2800 HW-rev 2.2 SW-rev 1.70 quirks 0x0000
>[ 5838.568335] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[ 5838.569061] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5838.570219] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5838.571462] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5838.572689] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5838.573925] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5838.575144] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5838.576405] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5838.577640] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5838.578885] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5838.580236] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5838.581588] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5838.582939] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5838.584292] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5838.585642] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5838.586945] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5838.588301] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5838.589644] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5838.590858] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5838.592085] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5838.593313] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5838.594534] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5838.595887] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5838.597239] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5838.598590] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5838.599944] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5838.601297] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5838.602650] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5838.603999] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5838.605344] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5838.606426] [drm:drm_add_edid_modes [drm]] ELD monitor HP E232
>[ 5838.606434] [drm:drm_add_edid_modes [drm]] HDMI: latency present 0 0, video latency 0 0, audio latency 0 0
>[ 5838.606441] [drm:drm_add_edid_modes [drm]] ELD size 28, SAD count 0
>[ 5838.606447] [drm:drm_add_edid_modes [drm]] HDMI: DVI dual 0, max TMDS clock 170000 kHz
>[ 5838.606538] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:57:DP-1] probed modes :
>[ 5838.606546] [drm:drm_mode_debug_printmodeline [drm]] Modeline 74:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[ 5838.606553] [drm:drm_mode_debug_printmodeline [drm]] Modeline 97:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[ 5838.606559] [drm:drm_mode_debug_printmodeline [drm]] Modeline 76:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[ 5838.606565] [drm:drm_mode_debug_printmodeline [drm]] Modeline 81:"1680x1050" 60 119000 1680 1728 1760 1840 1050 1053 1059 1080 0x40 0x9
>[ 5838.606572] [drm:drm_mode_debug_printmodeline [drm]] Modeline 80:"1600x900" 60 108000 1600 1624 1704 1800 900 901 904 1000 0x40 0x5
>[ 5838.606580] [drm:drm_mode_debug_printmodeline [drm]] Modeline 84:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[ 5838.606588] [drm:drm_mode_debug_printmodeline [drm]] Modeline 82:"1440x900" 60 88750 1440 1488 1520 1600 900 903 909 926 0x40 0x9
>[ 5838.606595] [drm:drm_mode_debug_printmodeline [drm]] Modeline 83:"1280x800" 60 71000 1280 1328 1360 1440 800 803 809 823 0x40 0x9
>[ 5838.606602] [drm:drm_mode_debug_printmodeline [drm]] Modeline 77:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[ 5838.606609] [drm:drm_mode_debug_printmodeline [drm]] Modeline 99:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[ 5838.606617] [drm:drm_mode_debug_printmodeline [drm]] Modeline 78:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[ 5838.606624] [drm:drm_mode_debug_printmodeline [drm]] Modeline 87:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[ 5838.606631] [drm:drm_mode_debug_printmodeline [drm]] Modeline 85:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[ 5838.606638] [drm:drm_mode_debug_printmodeline [drm]] Modeline 95:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[ 5838.606646] [drm:drm_mode_debug_printmodeline [drm]] Modeline 100:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[ 5838.606653] [drm:drm_mode_debug_printmodeline [drm]] Modeline 79:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[ 5838.606660] [drm:drm_mode_debug_printmodeline [drm]] Modeline 101:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[ 5838.606667] [drm:drm_mode_debug_printmodeline [drm]] Modeline 86:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[ 5838.606672] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:61:DP-2]
>[ 5838.606975] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 00 00 04 00 0f 00 04
>[ 5838.608259] [drm:intel_dp_detect [i915]] [CONNECTOR:61:DP-2]
>[ 5838.608276] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:61:DP-2] disconnected
>[ 5838.608281] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:64:HDMI-A-1]
>[ 5838.608302] [drm:intel_hdmi_detect [i915]] [CONNECTOR:64:HDMI-A-1]
>[ 5838.608626] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[ 5838.608644] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[ 5838.608960] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[ 5838.608968] [drm:drm_do_probe_ddc_edid [drm]] drm: skipping non-existent adapter i915 gmbus dpc
>[ 5838.609287] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[ 5838.609304] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[ 5838.609624] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[ 5838.609629] [drm:drm_dp_dual_mode_detect [drm_kms_helper]] DP dual mode HDMI ID:  (err -6)
>[ 5838.609633] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:64:HDMI-A-1] disconnected
>[ 5838.609637] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:67:DP-3]
>[ 5838.609654] [drm:intel_dp_detect [i915]] [CONNECTOR:67:DP-3]
>[ 5838.609670] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:67:DP-3] disconnected
>[ 5838.609673] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:70:HDMI-A-2]
>[ 5838.609690] [drm:intel_hdmi_detect [i915]] [CONNECTOR:70:HDMI-A-2]
>[ 5838.619813] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0050 w(1)
>[ 5838.619835] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK on first message, retry
>[ 5838.629662] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0050 w(1)
>[ 5838.629675] [drm:drm_do_probe_ddc_edid [drm]] drm: skipping non-existent adapter i915 gmbus dpd
>[ 5838.640611] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0040 w(1)
>[ 5838.640650] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK on first message, retry
>[ 5838.651607] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0040 w(1)
>[ 5838.651624] [drm:drm_dp_dual_mode_detect [drm_kms_helper]] DP dual mode HDMI ID:  (err -6)
>[ 5838.651636] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:70:HDMI-A-2] disconnected
>[ 5838.651648] [drm:drm_setup_crtcs [drm_kms_helper]] connector 49 enabled? yes
>[ 5838.651657] [drm:drm_setup_crtcs [drm_kms_helper]] connector 57 enabled? yes
>[ 5838.651666] [drm:drm_setup_crtcs [drm_kms_helper]] connector 61 enabled? no
>[ 5838.651674] [drm:drm_setup_crtcs [drm_kms_helper]] connector 64 enabled? no
>[ 5838.651682] [drm:drm_setup_crtcs [drm_kms_helper]] connector 67 enabled? no
>[ 5838.651690] [drm:drm_setup_crtcs [drm_kms_helper]] connector 70 enabled? no
>[ 5838.651755] [drm:intel_fb_initial_config [i915]] Not using firmware configuration
>[ 5838.651793] [drm:drm_setup_crtcs [drm_kms_helper]] looking for cmdline mode on connector 49
>[ 5838.651802] [drm:drm_setup_crtcs [drm_kms_helper]] looking for preferred mode on connector 49 0
>[ 5838.651816] [drm:drm_setup_crtcs [drm_kms_helper]] found mode 1920x1080
>[ 5838.651832] [drm:drm_setup_crtcs [drm_kms_helper]] looking for cmdline mode on connector 57
>[ 5838.651842] [drm:drm_setup_crtcs [drm_kms_helper]] looking for preferred mode on connector 57 0
>[ 5838.651854] [drm:drm_setup_crtcs [drm_kms_helper]] found mode 1920x1080
>[ 5838.651868] [drm:drm_setup_crtcs [drm_kms_helper]] picking CRTCs for 1920x1080 config
>[ 5838.651889] [drm:drm_setup_crtcs [drm_kms_helper]] desired mode 1920x1080 set on crtc 37 (0,0)
>[ 5838.651900] [drm:drm_setup_crtcs [drm_kms_helper]] desired mode 1920x1080 set on crtc 47 (0,0)
>[ 5841.628056] [drm:edp_panel_vdd_off_sync [i915]] Turning eDP port A VDD off
>[ 5841.628201] [drm:edp_panel_vdd_off_sync [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x00000067
>[ 5848.795813] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [CRTC:37:pipe A] flip_done timed out
>[ 5855.637818] [IGT] kms_fbcon_fbt: executing
>[ 5859.036119] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [CONNECTOR:49:eDP-1] flip_done timed out
>[ 5869.276090] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [PLANE:28:plane 1A] flip_done timed out
>[ 5879.516106] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [PLANE:34:cursor A] flip_done timed out
>[ 5889.755974] [drm:drm_atomic_helper_wait_for_flip_done [drm_kms_helper]] *ERROR* [CRTC:37:pipe A] flip_done timed out
>[ 5889.808138] [IGT] kms_fbcon_fbt: starting subtest psr-suspend
>[ 5889.808430] Setting dangerous option enable_fbc - tainting kernel
>[ 5889.808454] Setting dangerous option enable_psr - tainting kernel
>[ 5889.808463] Setting dangerous option enable_psr - tainting kernel
>[ 5889.808502] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[ 5889.808616] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 5889.808692] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[ 5899.996008] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [CRTC:37:pipe A] flip_done timed out
>[ 5910.235839] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [CONNECTOR:49:eDP-1] flip_done timed out
>[ 5920.476091] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [PLANE:28:plane 1A] flip_done timed out
>[ 5920.476217] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[ 5920.476374] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006f
>[ 5920.476631] [drm:intel_edp_backlight_off [i915]] 
>[ 5920.684148] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0
>[ 5920.684290] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 5920.685272] [drm:intel_edp_panel_off.part.31 [i915]] Turn eDP port A panel power off
>[ 5920.685378] [drm:intel_edp_panel_off.part.31 [i915]] Wait for panel power off time
>[ 5920.685505] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000003 control 00000060
>[ 5920.737562] [drm:wait_panel_status [i915]] Wait complete
>[ 5920.737626] [drm:intel_power_well_disable [i915]] disabling DDI A/E IO power well
>[ 5920.737710] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 5920.737789] [drm:intel_disable_shared_dpll [i915]] disable DPLL 0 (active 1, on? 1) for crtc 37
>[ 5920.737860] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 0
>[ 5920.737950] [drm:intel_atomic_commit_tail [i915]] [ENCODER:48:DDI A]
>[ 5920.738020] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI B]
>[ 5920.738086] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[ 5920.738150] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[ 5920.738212] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DDI C]
>[ 5920.738274] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST A]
>[ 5920.738335] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST B]
>[ 5920.738396] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI D]
>[ 5920.738455] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[ 5920.738514] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[ 5920.738580] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:49:eDP-1]
>[ 5920.738647] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[ 5920.738711] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[ 5920.738775] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[ 5920.738837] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[ 5920.745178] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010
>[ 5920.745259] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[ 5920.745333] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0
>[ 5920.745454] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[ 5920.749148] [drm:intel_atomic_commit_tail [i915]] [CRTC:37:pipe A]
>[ 5920.749219] [drm:intel_enable_sagv [i915]] Enabling the SAGV
>[ 5920.749284] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[ 5920.749385] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 5920.749457] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[ 5920.749582] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 5920.765743] [drm:intel_power_well_disable [i915]] disabling DDI B IO power well
>[ 5920.765827] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 2, on? 1) for crtc 47
>[ 5920.765900] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[ 5920.765988] [drm:intel_atomic_commit_tail [i915]] [ENCODER:48:DDI A]
>[ 5920.766053] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI B]
>[ 5920.766118] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[ 5920.766178] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[ 5920.766236] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DDI C]
>[ 5920.766293] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST A]
>[ 5920.766350] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST B]
>[ 5920.766405] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI D]
>[ 5920.766460] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[ 5920.766515] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[ 5920.766577] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:57:DP-1]
>[ 5920.766641] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[ 5920.766702] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[ 5920.766761] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[ 5920.766819] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[ 5920.766878] [drm:intel_power_well_disable [i915]] disabling power well 2
>[ 5920.766949] [drm:intel_atomic_commit_tail [i915]] [CRTC:47:pipe B]
>[ 5920.767004] [drm:intel_power_well_disable [i915]] disabling DC off
>[ 5920.767056] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[ 5920.767105] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[ 5920.767544] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 5925.772689] [drm:drm_mode_addfb2 [drm]] [FB:71]
>[ 5925.780635] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[ 5925.780665] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:49:eDP-1]
>[ 5925.780770] [drm:intel_atomic_check [i915]] [CONNECTOR:49:eDP-1] checking for sink bpp constrains
>[ 5925.780839] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 5925.780870] [drm:drm_mode_debug_printmodeline [drm]] Modeline 52:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[ 5925.780941] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 138780KHz
>[ 5925.781020] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24
>[ 5925.781079] [drm:intel_dp_compute_config [i915]] DP link bw required 416340 available 540000
>[ 5925.781144] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 5925.781207] [drm:intel_dump_pipe_config [i915]] [CRTC:37:pipe A][modeset]
>[ 5925.781267] [drm:intel_dump_pipe_config [i915]] output_types: EDP (0x100)
>[ 5925.781326] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0
>[ 5925.781383] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 6467616, gmch_n: 8388608, link_m: 269484, link_n: 524288, tu: 64
>[ 5925.781438] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[ 5925.781492] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 5925.781520] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[ 5925.781575] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 5925.781602] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[ 5925.781658] [drm:intel_dump_pipe_config [i915]] crtc timings: 138780 1920 1966 1996 2080 1080 1082 1086 1112, type: 0x48 flags: 0xa
>[ 5925.781712] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 138780
>[ 5925.781766] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[ 5925.781818] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 5925.781870] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 5925.781922] [drm:intel_dump_pipe_config [i915]] dpll_hw_state: ctrl1: 0x3, cfgcr1: 0x0, cfgcr2: 0x0
>[ 5925.781973] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 5925.782025] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 1A] disabled, scaler_id = -1
>[ 5925.782076] [drm:intel_dump_pipe_config [i915]] [PLANE:31:plane 2A] disabled, scaler_id = -1
>[ 5925.782128] [drm:intel_dump_pipe_config [i915]] [PLANE:34:cursor A] disabled, scaler_id = -1
>[ 5925.782192] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 5925.782250] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[ 5925.782318] [drm:intel_find_shared_dpll [i915]] [CRTC:37:pipe A] allocated DPLL 0
>[ 5925.782378] [drm:intel_reference_shared_dpll [i915]] using DPLL 0 for pipe A
>[ 5925.784233] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 5925.784285] [drm:intel_power_well_enable [i915]] enabling DC off
>[ 5925.784586] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[ 5925.784669] [drm:intel_atomic_commit_tail [i915]] [ENCODER:48:DDI A]
>[ 5925.784734] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI B]
>[ 5925.784798] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[ 5925.784857] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[ 5925.784915] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DDI C]
>[ 5925.784970] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST A]
>[ 5925.785027] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST B]
>[ 5925.785082] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI D]
>[ 5925.785136] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[ 5925.785188] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[ 5925.785249] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[ 5925.785312] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[ 5925.785371] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[ 5925.785429] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[ 5925.785496] [drm:intel_enable_shared_dpll [i915]] enable DPLL 0 (active 1, on? 0) for crtc 37
>[ 5925.785556] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 0
>[ 5925.785635] [drm:edp_panel_on [i915]] Turn eDP port A panel power on
>[ 5925.785709] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle
>[ 5925.785910] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 00000000 control 00000060
>[ 5925.785997] [drm:wait_panel_status [i915]] Wait complete
>[ 5925.786122] [drm:edp_panel_on [i915]] Wait for panel power on
>[ 5925.786243] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 00000063
>[ 5925.821968] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010
>[ 5925.822042] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[ 5925.822108] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0
>[ 5925.822216] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[ 5925.988157] [drm:wait_panel_status [i915]] Wait complete
>[ 5925.988223] [drm:intel_power_well_enable [i915]] enabling DDI A/E IO power well
>[ 5925.988324] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[ 5925.988476] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b
>[ 5925.989708] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 5925.989781] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 5925.989846] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 5925.989910] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 5925.990626] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 5925.990685] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 5925.991693] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 5925.991755] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:49:eDP-1] Link Training Passed at Link Rate = 270000, Lane count = 2
>[ 5925.992443] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 5925.992516] [drm:intel_edp_backlight_on [i915]] 
>[ 5925.992579] [drm:intel_panel_enable_backlight [i915]] pipe A
>[ 5925.992670] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 120000
>[ 5926.000043] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS
>[ 5929.180063] [drm:edp_panel_vdd_off_sync [i915]] Turning eDP port A VDD off
>[ 5929.180208] [drm:edp_panel_vdd_off_sync [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x00000067
>[ 5936.092014] [drm:drm_atomic_helper_wait_for_flip_done [drm_kms_helper]] *ERROR* [CRTC:37:pipe A] flip_done timed out
>[ 5936.092129] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:49:eDP-1]
>[ 5936.092209] [drm:intel_atomic_commit_tail [i915]] [CRTC:37:pipe A]
>[ 5936.092301] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[ 5936.092381] [drm:intel_power_well_disable [i915]] disabling DC off
>[ 5936.092433] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[ 5936.092482] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[ 5936.231469] PM: suspend entry (deep)
>[ 5936.231472] PM: Syncing filesystems ... done.
>[ 5936.234823] Freezing user space processes ... (elapsed 0.001 seconds) done.
>[ 5936.236434] OOM killer disabled.
>[ 5936.236435] Freezing remaining freezable tasks ... (elapsed 0.001 seconds) done.
>[ 5936.237771] Suspending console(s) (use no_console_suspend to debug)
>[ 5936.572559] e1000e: EEE TX LPI TIMER: 00000011
>[ 5936.573012] [drm:intel_power_well_enable [i915]] enabling DC off
>[ 5936.573074] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[ 5936.573154] [drm:intel_power_well_enable [i915]] enabling power well 2
>[ 5936.573251] [drm:intel_power_well_enable [i915]] enabling DDI B IO power well
>[ 5936.573297] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well
>[ 5936.573342] [drm:intel_power_well_enable [i915]] enabling DDI D IO power well
>[ 5936.574112] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 5936.574180] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[ 5941.490192] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 5941.490263] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 5941.490360] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[ 5941.773073] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 5941.773144] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 5946.534022] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 5946.534093] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 5946.587982] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [CRTC:37:pipe A] flip_done timed out
>[ 5946.803375] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 5946.803446] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 5952.376764] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 5952.376835] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 5952.646029] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 5952.646100] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 5956.827954] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [CONNECTOR:49:eDP-1] flip_done timed out
>[ 5958.205465] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 5958.205536] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 5958.488248] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 5958.488319] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 5964.047965] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 5964.048036] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 5964.330770] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 5964.330840] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 5967.068078] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [PLANE:28:plane 1A] flip_done timed out
>[ 5967.068192] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[ 5967.068340] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006f
>[ 5967.068578] [drm:intel_edp_backlight_off [i915]] 
>[ 5967.275876] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0
>[ 5967.275998] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 5967.292978] [drm:intel_edp_panel_off.part.31 [i915]] Turn eDP port A panel power off
>[ 5967.293080] [drm:intel_edp_panel_off.part.31 [i915]] Wait for panel power off time
>[ 5967.293202] [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000003 control 00000060
>[ 5967.345967] [drm:wait_panel_status [i915]] Wait complete
>[ 5967.346049] [drm:intel_disable_shared_dpll [i915]] disable DPLL 0 (active 1, on? 1) for crtc 37
>[ 5967.346117] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 0
>[ 5967.346199] [drm:intel_atomic_commit_tail [i915]] [ENCODER:48:DDI A]
>[ 5967.346262] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI B]
>[ 5967.346321] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[ 5967.346378] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[ 5967.346433] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DDI C]
>[ 5967.346487] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST A]
>[ 5967.346541] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST B]
>[ 5967.346594] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI D]
>[ 5967.346647] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[ 5967.346700] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[ 5967.346758] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:49:eDP-1]
>[ 5967.346817] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[ 5967.346874] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[ 5967.346929] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[ 5967.346982] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[ 5967.347047] [drm:intel_atomic_commit_tail [i915]] [CRTC:37:pipe A]
>[ 5967.403747] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 00 00 04 00 0f 00 04
>[ 5967.564357] PM: Some devices failed to suspend, or early wake event detected
>[ 5967.565015] [drm:intel_opregion_setup [i915]] graphic opregion physical addr: 0x8cb19018
>[ 5967.565224] [drm:intel_opregion_setup [i915]] Public ACPI methods supported
>[ 5967.565289] [drm:intel_opregion_setup [i915]] SWSCI supported
>[ 5967.566045] serial 00:06: activated
>[ 5967.567185] [drm:intel_opregion_setup [i915]] SWSCI GBDA callbacks 00000cb3, SBCB callbacks 00300483
>[ 5967.567234] [drm:intel_opregion_setup [i915]] ASLE supported
>[ 5967.567265] [drm:intel_opregion_setup [i915]] ASLE extension supported
>[ 5967.567296] [drm:intel_opregion_setup [i915]] Found valid VBT in ACPI OpRegion (Mailbox #4)
>[ 5967.567945] [drm:intel_dp_init_panel_power_sequencer_registers [i915]] panel power sequencer register settings: PP_ON 0x7d00001, PP_OFF 0x1f40001, PP_DIV 0x60
>[ 5967.568263] [drm:lspcon_wake_native_aux_ch [i915]] Native AUX CH up, DPCD version: 1.2
>[ 5967.568305] [drm:lspcon_resume [i915]] LSPCON recovering in PCON mode after 0 ms
>[ 5967.568724] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5967.569908] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5967.571184] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5967.572452] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5967.573729] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5967.574613] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[ 5967.574688] [drm:intel_uc_fw_upload [i915]] HuC fw load i915/kbl_huc_ver02_00_1810.bin
>[ 5967.574700] [drm:intel_uc_fw_upload [i915]] HuC fw load PENDING
>[ 5967.791773] atkbd serio0: Failed to deactivate keyboard on isa0060/serio0
>[ 5967.801642] [drm:huc_ucode_xfer [i915]] HuC DMA transfer wait over with ret 0
>[ 5967.801695] [drm:intel_uc_fw_upload [i915]] HuC fw load SUCCESS
>[ 5967.801697] [drm] HuC: Loaded firmware i915/kbl_huc_ver02_00_1810.bin (version 2.0)
>[ 5967.801756] [drm:intel_uc_fw_upload [i915]] GuC fw load i915/kbl_guc_ver9_39.bin
>[ 5967.801799] [drm:intel_uc_fw_upload [i915]] GuC fw load PENDING
>[ 5967.803507] [drm:guc_fw_xfer [i915]] GuC DMA status 0x10
>[ 5967.806254] [drm:guc_fw_xfer [i915]] GuC status 0x8002f0ec
>[ 5967.806309] [drm:intel_uc_fw_upload [i915]] GuC fw load SUCCESS
>[ 5967.806312] [drm] GuC: Loaded firmware i915/kbl_guc_ver9_39.bin (version 9.39)
>[ 5967.806760] i915 0000:00:02.0: GuC submission enabled (firmware i915/kbl_guc_ver9_39.bin [version 9.39])
>[ 5967.806890] [drm:gen8_init_common_ring [i915]] Execlists enabled for rcs0
>[ 5967.806958] [drm:init_workarounds_ring [i915]] rcs0: Number of context specific w/a: 14
>[ 5967.807055] [drm:gen8_init_common_ring [i915]] Execlists enabled for bcs0
>[ 5967.807150] [drm:gen8_init_common_ring [i915]] Execlists enabled for vcs0
>[ 5967.807243] [drm:gen8_init_common_ring [i915]] Execlists enabled for vecs0
>[ 5967.807342] [drm] RC6 on
>[ 5967.807599] [drm:intel_dump_cdclk_state [i915]] Current CDCLK 337500 kHz, VCO 8100000 kHz, ref 24000 kHz, voltage level 0
>[ 5967.807828] [drm:intel_modeset_setup_hw_state [i915]] pipe A active planes 0x0
>[ 5967.807878] [drm:intel_modeset_setup_hw_state [i915]] pipe A active planes 0x0
>[ 5967.807926] [drm:intel_modeset_setup_hw_state [i915]] pipe A active planes 0x0
>[ 5967.807972] [drm:intel_modeset_setup_hw_state [i915]] [CRTC:37:pipe A] hw state readout: disabled
>[ 5967.808021] [drm:intel_modeset_setup_hw_state [i915]] pipe B active planes 0x0
>[ 5967.808065] [drm:intel_modeset_setup_hw_state [i915]] pipe B active planes 0x0
>[ 5967.808108] [drm:intel_modeset_setup_hw_state [i915]] pipe B active planes 0x0
>[ 5967.808151] [drm:intel_modeset_setup_hw_state [i915]] [CRTC:47:pipe B] hw state readout: disabled
>[ 5967.808196] [drm:intel_modeset_setup_hw_state [i915]] DPLL 0 hw state readout: crtc_mask 0x00000000, on 1
>[ 5967.808239] [drm:intel_modeset_setup_hw_state [i915]] DPLL 1 hw state readout: crtc_mask 0x00000000, on 0
>[ 5967.808280] [drm:intel_modeset_setup_hw_state [i915]] DPLL 2 hw state readout: crtc_mask 0x00000000, on 0
>[ 5967.808322] [drm:intel_modeset_setup_hw_state [i915]] DPLL 3 hw state readout: crtc_mask 0x00000000, on 0
>[ 5967.808365] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:48:DDI A] hw state readout: disabled, pipe A
>[ 5967.808407] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:56:DDI B] hw state readout: disabled, pipe A
>[ 5967.808448] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:58:DP-MST A] hw state readout: disabled, pipe A
>[ 5967.808489] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:59:DP-MST B] hw state readout: disabled, pipe B
>[ 5967.808529] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:60:DDI C] hw state readout: disabled, pipe A
>[ 5967.808569] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:62:DP-MST A] hw state readout: disabled, pipe A
>[ 5967.808608] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:63:DP-MST B] hw state readout: disabled, pipe B
>[ 5967.808649] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:66:DDI D] hw state readout: disabled, pipe A
>[ 5967.808689] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:68:DP-MST A] hw state readout: disabled, pipe A
>[ 5967.808728] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:69:DP-MST B] hw state readout: disabled, pipe B
>[ 5967.808769] [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:49:eDP-1] hw state readout: disabled
>[ 5967.808810] [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:57:DP-1] hw state readout: disabled
>[ 5967.808852] [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:61:DP-2] hw state readout: disabled
>[ 5967.808893] [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:64:HDMI-A-1] hw state readout: disabled
>[ 5967.808934] [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:67:DP-3] hw state readout: disabled
>[ 5967.808975] [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:70:HDMI-A-2] hw state readout: disabled
>[ 5967.809026] [drm:intel_dump_pipe_config [i915]] [CRTC:37:pipe A][setup_hw_state]
>[ 5967.809071] [drm:intel_dump_pipe_config [i915]] output_types:  (0x0)
>[ 5967.809115] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 0, dithering: 0
>[ 5967.809158] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[ 5967.809200] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 5967.809224] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[ 5967.809267] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 5967.809287] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[ 5967.809332] [drm:intel_dump_pipe_config [i915]] crtc timings: 0 0 0 0 0 0 0 0 0, type: 0x0 flags: 0x0
>[ 5967.809375] [drm:intel_dump_pipe_config [i915]] port clock: 0, pipe src size: 0x0, pixel rate 0
>[ 5967.809417] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[ 5967.809459] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 5967.809500] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 5967.809542] [drm:intel_dump_pipe_config [i915]] dpll_hw_state: ctrl1: 0x0, cfgcr1: 0x0, cfgcr2: 0x0
>[ 5967.809588] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 5967.809630] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 1A] disabled, scaler_id = -1
>[ 5967.809670] [drm:intel_dump_pipe_config [i915]] [PLANE:31:plane 2A] disabled, scaler_id = -1
>[ 5967.809711] [drm:intel_dump_pipe_config [i915]] [PLANE:34:cursor A] disabled, scaler_id = -1
>[ 5967.809752] [drm:intel_dump_pipe_config [i915]] [CRTC:47:pipe B][setup_hw_state]
>[ 5967.809792] [drm:intel_dump_pipe_config [i915]] output_types:  (0x0)
>[ 5967.809832] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 0, dithering: 0
>[ 5967.809871] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[ 5967.809910] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 5967.809931] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[ 5967.809973] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 5967.809993] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[ 5967.810036] [drm:intel_dump_pipe_config [i915]] crtc timings: 0 0 0 0 0 0 0 0 0, type: 0x0 flags: 0x0
>[ 5967.810077] [drm:intel_dump_pipe_config [i915]] port clock: 0, pipe src size: 0x0, pixel rate 0
>[ 5967.810118] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[ 5967.810158] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 5967.810198] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 5967.810237] [drm:intel_dump_pipe_config [i915]] dpll_hw_state: ctrl1: 0x0, cfgcr1: 0x0, cfgcr2: 0x0
>[ 5967.810275] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 5967.810315] [drm:intel_dump_pipe_config [i915]] [PLANE:38:plane 1B] disabled, scaler_id = -1
>[ 5967.810354] [drm:intel_dump_pipe_config [i915]] [PLANE:41:plane 2B] disabled, scaler_id = -1
>[ 5967.810393] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor B] disabled, scaler_id = -1
>[ 5967.810442] [drm:intel_modeset_setup_hw_state [i915]] DPLL 0 enabled but not in use, disabling
>[ 5967.810506] [drm:intel_power_well_disable [i915]] disabling DDI D IO power well
>[ 5967.810543] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well
>[ 5967.810578] [drm:intel_power_well_disable [i915]] disabling DDI B IO power well
>[ 5967.810612] [drm:intel_power_well_disable [i915]] disabling DDI A/E IO power well
>[ 5967.810647] [drm:intel_power_well_disable [i915]] disabling power well 2
>[ 5967.810685] [drm:intel_power_well_disable [i915]] disabling DC off
>[ 5967.810721] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[ 5967.810755] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[ 5967.811181] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 5967.811249] [drm:intel_atomic_check [i915]] [CONNECTOR:49:eDP-1] checking for sink bpp constrains
>[ 5967.811295] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 5967.811320] [drm:drm_mode_debug_printmodeline [drm]] Modeline 52:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[ 5967.811371] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 2 max bw 270000 pixel clock 138780KHz
>[ 5967.811431] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 2 clock 270000 bpp 24
>[ 5967.811477] [drm:intel_dp_compute_config [i915]] DP link bw required 416340 available 540000
>[ 5967.811526] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 5967.811574] [drm:intel_dump_pipe_config [i915]] [CRTC:37:pipe A][modeset]
>[ 5967.811619] [drm:intel_dump_pipe_config [i915]] output_types: EDP (0x100)
>[ 5967.811663] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0
>[ 5967.811708] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 2; gmch_m: 6467616, gmch_n: 8388608, link_m: 269484, link_n: 524288, tu: 64
>[ 5967.811762] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[ 5967.811811] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 5967.811832] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[ 5967.811875] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 5967.811896] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 138780 1920 1966 1996 2080 1080 1082 1086 1112 0x48 0xa
>[ 5967.811941] [drm:intel_dump_pipe_config [i915]] crtc timings: 138780 1920 1966 1996 2080 1080 1082 1086 1112, type: 0x48 flags: 0xa
>[ 5967.811982] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 138780
>[ 5967.812024] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[ 5967.812065] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 5967.812105] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 5967.812144] [drm:intel_dump_pipe_config [i915]] dpll_hw_state: ctrl1: 0x3, cfgcr1: 0x0, cfgcr2: 0x0
>[ 5967.812183] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 5967.812223] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 1A] disabled, scaler_id = -1
>[ 5967.812263] [drm:intel_dump_pipe_config [i915]] [PLANE:31:plane 2A] disabled, scaler_id = -1
>[ 5967.812302] [drm:intel_dump_pipe_config [i915]] [PLANE:34:cursor A] disabled, scaler_id = -1
>[ 5967.812350] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 5967.812394] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[ 5967.812448] [drm:intel_find_shared_dpll [i915]] [CRTC:37:pipe A] allocated DPLL 0
>[ 5967.812494] [drm:intel_reference_shared_dpll [i915]] using DPLL 0 for pipe A
>[ 5967.812903] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 5967.812939] [drm:intel_power_well_enable [i915]] enabling DC off
>[ 5967.813296] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[ 5967.813352] [drm:intel_atomic_commit_tail [i915]] [ENCODER:48:DDI A]
>[ 5967.813397] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI B]
>[ 5967.813441] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[ 5967.813483] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[ 5967.813525] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DDI C]
>[ 5967.813566] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST A]
>[ 5967.813607] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST B]
>[ 5967.813647] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI D]
>[ 5967.813688] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[ 5967.813728] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[ 5967.813772] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:57:DP-1]
>[ 5967.813817] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:61:DP-2]
>[ 5967.813860] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:64:HDMI-A-1]
>[ 5967.813902] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:67:DP-3]
>[ 5967.813944] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:70:HDMI-A-2]
>[ 5967.813985] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[ 5967.814030] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[ 5967.814071] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[ 5967.814111] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[ 5967.814161] [drm:intel_enable_shared_dpll [i915]] enable DPLL 0 (active 1, on? 0) for crtc 37
>[ 5967.814207] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 0
>[ 5967.814269] [drm:edp_panel_on [i915]] Turn eDP port A panel power on
>[ 5967.814327] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle
>[ 5967.952168] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 00000000 control 00000060
>[ 5967.952259] [drm:wait_panel_status [i915]] Wait complete
>[ 5967.952383] [drm:edp_panel_on [i915]] Wait for panel power on
>[ 5967.952501] [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 00000063
>[ 5967.985840] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010
>[ 5967.985904] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[ 5967.985964] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0
>[ 5967.986043] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[ 5968.060826] ata2: SATA link down (SStatus 4 SControl 300)
>[ 5968.060902] ata4: SATA link down (SStatus 4 SControl 300)
>[ 5968.060971] ata3: SATA link down (SStatus 4 SControl 300)
>[ 5968.153699] [drm:wait_panel_status [i915]] Wait complete
>[ 5968.153756] [drm:intel_power_well_enable [i915]] enabling DDI A/E IO power well
>[ 5968.153852] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[ 5968.153995] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006b
>[ 5968.155207] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 5968.155271] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 5968.155328] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 5968.155385] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 5968.156106] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 5968.156154] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 5968.157141] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 5968.157190] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:49:eDP-1] Link Training Passed at Link Rate = 270000, Lane count = 2
>[ 5968.157809] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 5968.157894] [drm:intel_edp_backlight_on [i915]] 
>[ 5968.157945] [drm:intel_panel_enable_backlight [i915]] pipe A
>[ 5968.158022] [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 120000
>[ 5968.164033] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS
>[ 5968.167783] atkbd serio0: Failed to enable keyboard on isa0060/serio0
>[ 5969.696176] asix 1-2:1.0 enx00106031c2aa: link up, 100Mbps, full-duplex, lpa 0xC5E1
>[ 5969.880653] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 5969.880694] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 5969.880751] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[ 5969.880781] [drm:intel_power_well_enable [i915]] enabling power well 2
>[ 5970.140875] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 5970.140939] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 5971.420058] [drm:edp_panel_vdd_off_sync [i915]] Turning eDP port A VDD off
>[ 5971.420194] [drm:edp_panel_vdd_off_sync [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x00000067
>[ 5975.708763] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 5975.708827] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 5975.970496] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 5975.970560] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 5978.332088] [drm:drm_atomic_helper_wait_for_flip_done [drm_kms_helper]] *ERROR* [CRTC:37:pipe A] flip_done timed out
>[ 5978.332364] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:49:eDP-1]
>[ 5978.332438] [drm:intel_atomic_commit_tail [i915]] [CRTC:37:pipe A]
>[ 5978.332526] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[ 5978.332592] [drm:intel_atomic_commit_tail [i915]] [CRTC:47:pipe B]
>[ 5978.332836] [drm:intel_opregion_register [i915]] 6 outputs detected
>[ 5978.333202] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 00 00 04 00 0f 00 04
>[ 5978.334649] [drm:intel_dp_detect [i915]] [CONNECTOR:49:eDP-1]
>[ 5978.334712] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>[ 5978.334767] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[ 5978.334820] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[ 5978.334888] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[ 5978.335019] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000006f
>[ 5978.335115] [drm:intel_power_well_disable [i915]] disabling power well 2
>[ 5978.335185] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[ 5978.335292] [drm:intel_power_well_enable [i915]] enabling power well 2
>[ 5978.335471] [drm:drm_dp_read_desc [drm_kms_helper]] DP sink: OUI 00-1c-f8 dev-ID  HW-rev 0.1 SW-rev 1.22 quirks 0x0000
>[ 5978.336179] [drm:drm_helper_hpd_irq_event [drm_kms_helper]] [CONNECTOR:49:eDP-1] status updated from connected to connected
>[ 5978.336386] OOM killer enabled.
>[ 5978.336388] Restarting tasks ... 
>[ 5978.336674] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 00 00 04 00 0f 00 04
>[ 5978.337131] done.
>[ 5978.338308] [drm:intel_dp_detect [i915]] [CONNECTOR:57:DP-1]
>[ 5978.338666] [drm:lspcon_wake_native_aux_ch [i915]] Native AUX CH up, DPCD version: 1.2
>[ 5978.338710] [drm:lspcon_resume [i915]] LSPCON recovering in PCON mode after 0 ms
>[ 5978.339129] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5978.340289] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5978.341444] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5978.342588] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5978.343792] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5978.344559] PM: suspend exit
>[ 5978.344682] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[ 5978.345082] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 00 00 04 00 0f 00 04
>[ 5978.345600] [IGT] kms_fbcon_fbt: exiting, ret=99
>[ 5978.345615] Setting dangerous option enable_psr - tainting kernel
>[ 5978.345618] Setting dangerous option enable_fbc - tainting kernel
>[ 5978.345906] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>[ 5978.345920] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000
>[ 5978.345934] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000
>[ 5978.346339] [drm:drm_dp_read_desc [drm_kms_helper]] DP branch: OUI 00-60-ad dev-ID MC2800 HW-rev 2.2 SW-rev 1.70 quirks 0x0000
>[ 5978.346626] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[ 5978.347410] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5978.348563] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5978.349817] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5978.351054] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5978.352315] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5978.353550] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5978.354805] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5978.356116] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5978.357354] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5978.358745] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5978.360122] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5978.361499] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5978.362979] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5978.364360] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5978.365737] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5978.367113] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5978.368516] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5978.369759] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5978.371010] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5978.372270] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5978.373514] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5978.374911] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5978.376287] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5978.377666] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5978.379087] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5978.380469] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5978.381846] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5978.383222] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5978.384517] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5978.385625] [drm:intel_power_well_disable [i915]] disabling power well 2
>[ 5978.385631] [drm:drm_helper_hpd_irq_event [drm_kms_helper]] [CONNECTOR:57:DP-1] status updated from connected to connected
>[ 5978.385647] [drm:intel_dp_detect [i915]] [CONNECTOR:61:DP-2]
>[ 5978.385658] [drm:intel_power_well_enable [i915]] enabling power well 2
>[ 5978.385687] [drm:intel_power_well_disable [i915]] disabling power well 2
>[ 5978.385697] [drm:drm_helper_hpd_irq_event [drm_kms_helper]] [CONNECTOR:61:DP-2] status updated from disconnected to disconnected
>[ 5978.385713] [drm:intel_hdmi_detect [i915]] [CONNECTOR:64:HDMI-A-1]
>[ 5978.386029] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[ 5978.386043] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[ 5978.386356] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[ 5978.386364] [drm:drm_do_probe_ddc_edid [drm]] drm: skipping non-existent adapter i915 gmbus dpc
>[ 5978.386677] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[ 5978.386690] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[ 5978.387003] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[ 5978.387006] [drm:drm_dp_dual_mode_detect [drm_kms_helper]] DP dual mode HDMI ID:  (err -6)
>[ 5978.387009] [drm:drm_helper_hpd_irq_event [drm_kms_helper]] [CONNECTOR:64:HDMI-A-1] status updated from disconnected to disconnected
>[ 5978.387023] [drm:intel_dp_detect [i915]] [CONNECTOR:67:DP-3]
>[ 5978.387034] [drm:intel_power_well_enable [i915]] enabling power well 2
>[ 5978.387064] [drm:intel_power_well_disable [i915]] disabling power well 2
>[ 5978.387069] [drm:drm_helper_hpd_irq_event [drm_kms_helper]] [CONNECTOR:67:DP-3] status updated from disconnected to disconnected
>[ 5978.387082] [drm:intel_hdmi_detect [i915]] [CONNECTOR:70:HDMI-A-2]
>[ 5978.396347] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0050 w(1)
>[ 5978.396363] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK on first message, retry
>[ 5978.407280] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0050 w(1)
>[ 5978.407312] [drm:drm_do_probe_ddc_edid [drm]] drm: skipping non-existent adapter i915 gmbus dpd
>[ 5978.417186] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0040 w(1)
>[ 5978.417250] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK on first message, retry
>[ 5978.427990] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0040 w(1)
>[ 5978.428008] [drm:drm_dp_dual_mode_detect [drm_kms_helper]] DP dual mode HDMI ID:  (err -6)
>[ 5978.428026] [drm:drm_helper_hpd_irq_event [drm_kms_helper]] [CONNECTOR:70:HDMI-A-2] status updated from disconnected to disconnected
>[ 5981.404063] [drm:edp_panel_vdd_off_sync [i915]] Turning eDP port A VDD off
>[ 5981.404201] [drm:edp_panel_vdd_off_sync [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x00000067
>[ 5981.404251] [drm:intel_power_well_disable [i915]] disabling DC off
>[ 5981.404302] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[ 5981.404350] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[ 5981.546518] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 5981.546590] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 5981.546712] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[ 5981.546787] [drm:intel_power_well_enable [i915]] enabling DC off
>[ 5981.546864] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[ 5981.546931] [drm:intel_power_well_enable [i915]] enabling power well 2
>[ 5981.806287] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 5981.806303] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 5987.369776] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 5987.369848] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 5987.629791] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 5987.629864] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 5988.571989] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [CRTC:37:pipe A] flip_done timed out
>[ 5993.195578] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 5993.195650] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 5993.457259] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 5993.457332] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 5998.811984] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [PLANE:28:plane 1A] flip_done timed out
>[ 5999.032587] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 5999.032669] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 5999.293232] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 5999.293312] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 6004.868020] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 6004.868101] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 6005.128207] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 6005.128279] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 6009.051827] [drm:drm_atomic_helper_wait_for_flip_done [drm_kms_helper]] *ERROR* [CRTC:37:pipe A] flip_done timed out
>[ 6009.052432] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 00 00 04 00 0f 00 04
>[ 6009.053843] [drm:intel_power_well_disable [i915]] disabling power well 2
>[ 6009.053928] [drm:intel_atomic_check [i915]] [CONNECTOR:57:DP-1] checking for sink bpp constrains
>[ 6009.054001] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 6009.054051] [drm:intel_power_well_disable [i915]] disabling DC off
>[ 6009.054103] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[ 6009.054173] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 148500KHz
>[ 6009.054223] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[ 6009.054290] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 6009.054352] [drm:intel_dp_compute_config [i915]] DP link bw required 445500 available 648000
>[ 6009.054435] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 6009.054497] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[ 6009.054541] [drm:intel_power_well_enable [i915]] enabling DC off
>[ 6009.054600] [drm:intel_dump_pipe_config [i915]] [CRTC:47:pipe B][modeset]
>[ 6009.054657] [drm:intel_dump_pipe_config [i915]] output_types: DP (0x80)
>[ 6009.054699] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[ 6009.054754] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 6009.054795] [drm:intel_power_well_enable [i915]] enabling power well 2
>[ 6009.054851] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5767168, gmch_n: 8388608, link_m: 240298, link_n: 262144, tu: 64
>[ 6009.054903] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[ 6009.054955] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 6009.054984] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[ 6009.055036] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 6009.055063] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x5
>[ 6009.055117] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x5
>[ 6009.055169] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1080, pixel rate 148500
>[ 6009.055220] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[ 6009.055271] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 6009.055321] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 6009.055372] [drm:intel_dump_pipe_config [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[ 6009.055421] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 6009.055472] [drm:intel_dump_pipe_config [i915]] [PLANE:38:plane 1B] disabled, scaler_id = -1
>[ 6009.055520] [drm:intel_dump_pipe_config [i915]] [PLANE:41:plane 2B] disabled, scaler_id = -1
>[ 6009.055569] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor B] disabled, scaler_id = -1
>[ 6009.055630] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 6009.055685] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[ 6009.055753] [drm:intel_find_shared_dpll [i915]] [CRTC:47:pipe B] allocated DPLL 1
>[ 6009.055837] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[ 6010.693488] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 6010.693561] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 6010.955632] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 6010.955705] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 6016.525886] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 6016.525968] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 6016.788353] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 6016.788435] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 6019.291932] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [CRTC:37:pipe A] flip_done timed out
>[ 6022.360015] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 6022.360095] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 6022.621434] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 6022.621506] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 6028.189454] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 6028.189527] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 6028.450227] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 6028.450308] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 6029.531983] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [CONNECTOR:49:eDP-1] flip_done timed out
>[ 6034.020517] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 6034.020598] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 6034.281640] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 6034.281722] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 6039.771987] [drm:drm_atomic_helper_wait_for_dependencies [drm_kms_helper]] *ERROR* [PLANE:28:plane 1A] flip_done timed out
>[ 6039.772074] [drm:intel_disable_sagv [i915]] Disabling the SAGV
>[ 6039.772154] [drm:intel_atomic_commit_tail [i915]] [ENCODER:48:DDI A]
>[ 6039.772224] [drm:intel_atomic_commit_tail [i915]] [ENCODER:56:DDI B]
>[ 6039.772286] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST A]
>[ 6039.772346] [drm:intel_atomic_commit_tail [i915]] [ENCODER:59:DP-MST B]
>[ 6039.772403] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DDI C]
>[ 6039.772458] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST A]
>[ 6039.772513] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST B]
>[ 6039.772567] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI D]
>[ 6039.772620] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[ 6039.772673] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[ 6039.772732] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[ 6039.772793] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[ 6039.772850] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[ 6039.772908] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[ 6039.772976] [drm:intel_fbc_enable [i915]] reserved 16588800 bytes of contiguous stolen space for FBC, threshold: 1
>[ 6039.773036] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 6039.773405] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 2, on? 0) for crtc 47
>[ 6039.773473] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[ 6039.773625] [drm:intel_power_well_enable [i915]] enabling DDI B IO power well
>[ 6039.774230] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 6039.775486] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 6039.776749] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 6039.777996] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 6039.779250] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 6039.780095] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[ 6039.781083] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 6039.781144] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 6039.781200] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 6039.781254] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 6039.799965] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 6039.799979] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[ 6039.817804] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 6039.818140] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:57:DP-1] Link Training Passed at Link Rate = 162000, Lane count = 4
>[ 6039.818523] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 6039.818578] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS
>[ 6039.862407] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 6039.862443] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 6040.125738] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 6040.125811] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 6050.011985] [drm:drm_atomic_helper_wait_for_flip_done [drm_kms_helper]] *ERROR* [CRTC:37:pipe A] flip_done timed out
>[ 6050.012109] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:57:DP-1]
>[ 6050.012187] [drm:intel_atomic_commit_tail [i915]] [CRTC:47:pipe B]
>[ 6050.012276] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[ 6050.012883] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 00 00 04 00 0f 00 04
>[ 6050.014369] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[ 6050.014873] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 00 00 04 00 0f 00 04

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Attachments on bug 104021: 135860 | 135861 | 136791 | 136792 | 137724 | 137726

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