Attachment 135982 Details for Bug 104119 – Output from RADV_DEBUG=shaders

Output from RADV_DEBUG=shaders

RADV_DEBUG=shaders output (text/plain), 3.93 KB, created by James Legg on 2017-12-05 15:54:43 UTC

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Creator: James Legg

Created: 2017-12-05 15:54:43 UTC

Size: 3.93 KB

patch

obsolete

>shader: MESA_SHADER_COMPUTE
>local-size: 1, 1, 1
>shared-size: 1
>inputs: 0
>outputs: 0
>uniforms: 0
>shared: 0
>decl_function main returning void
>
>impl main {
>	block block_0:
>	/* preds: */
>	vec1 32 ssa_0 = load_const (0x00000000 /* 0.000000 */)
>	vec1 32 ssa_1 = intrinsic vulkan_resource_index (ssa_0) () (0, 0) /* desc-set=0 */ /* binding=0 */
>	intrinsic store_ssbo (ssa_0, ssa_1, ssa_0) () (1) /* wrmask=x */
>	vec1 32 ssa_2 = load_const (0x00000004 /* 0.000000 */)
>	intrinsic store_ssbo (ssa_0, ssa_1, ssa_2) () (1) /* wrmask=x */
>	vec1 32 ssa_3 = load_const (0x00000008 /* 0.000000 */)
>	intrinsic store_ssbo (ssa_0, ssa_1, ssa_3) () (1) /* wrmask=x */
>	vec1 32 ssa_4 = load_const (0x0000000c /* 0.000000 */)
>	intrinsic store_ssbo (ssa_0, ssa_1, ssa_4) () (1) /* wrmask=x */
>	vec1 32 ssa_5 = load_const (0x00000010 /* 0.000000 */)
>	intrinsic store_ssbo (ssa_0, ssa_1, ssa_5) () (1) /* wrmask=x */
>	vec1 32 ssa_6 = load_const (0x00000014 /* 0.000000 */)
>	intrinsic store_ssbo (ssa_0, ssa_1, ssa_6) () (1) /* wrmask=x */
>	vec1 32 ssa_7 = load_const (0x00000018 /* 0.000000 */)
>	intrinsic store_ssbo (ssa_0, ssa_1, ssa_7) () (1) /* wrmask=x */
>	vec1 32 ssa_8 = load_const (0x0000001c /* 0.000000 */)
>	intrinsic store_ssbo (ssa_0, ssa_1, ssa_8) () (1) /* wrmask=x */
>	/* succs: block_0 */
>	block block_0:
>}
>
>; ModuleID = 'shader'
>source_filename = "shader"
>target datalayout = "e-p:32:32-p1:64:64-p2:64:64-p3:32:32-p4:64:64-p5:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"
>target triple = "amdgcn-mesa-mesa3d"
>
>define amdgpu_cs void @main([1048576 x i8] addrspace(2)* byval dereferenceable(18446744073709551615), <3 x i32> inreg, i32 inreg, <3 x i32>) #0 {
>main_body:
>  %4 = bitcast [1048576 x i8] addrspace(2)* %0 to <4 x i32> addrspace(2)*, !amdgpu.uniform !0
>  %5 = load <4 x i32>, <4 x i32> addrspace(2)* %4, align 16
>  call void @llvm.amdgcn.buffer.store.f32(float 0.000000e+00, <4 x i32> %5, i32 0, i32 0, i1 false, i1 false) #3
>  call void @llvm.amdgcn.buffer.store.f32(float 0.000000e+00, <4 x i32> %5, i32 0, i32 4, i1 false, i1 false) #3
>  call void @llvm.amdgcn.buffer.store.f32(float 0.000000e+00, <4 x i32> %5, i32 0, i32 8, i1 false, i1 false) #3
>  call void @llvm.amdgcn.buffer.store.f32(float 0.000000e+00, <4 x i32> %5, i32 0, i32 12, i1 false, i1 false) #3
>  call void @llvm.amdgcn.buffer.store.f32(float 0.000000e+00, <4 x i32> %5, i32 0, i32 16, i1 false, i1 false) #3
>  call void @llvm.amdgcn.buffer.store.f32(float 0.000000e+00, <4 x i32> %5, i32 0, i32 20, i1 false, i1 false) #3
>  call void @llvm.amdgcn.buffer.store.f32(float 0.000000e+00, <4 x i32> %5, i32 0, i32 24, i1 false, i1 false) #3
>  call void @llvm.amdgcn.buffer.store.f32(float 0.000000e+00, <4 x i32> %5, i32 0, i32 28, i1 false, i1 false) #3
>  ret void
>}
>
>; Function Attrs: nounwind readnone speculatable
>declare i8 addrspace(2)* @llvm.amdgcn.implicit.buffer.ptr() #1
>
>; Function Attrs: nounwind writeonly
>declare void @llvm.amdgcn.buffer.store.f32(float, <4 x i32>, i32, i32, i1, i1) #2
>
>attributes #0 = { "amdgpu-max-work-group-size"="1" }
>attributes #1 = { nounwind readnone speculatable }
>attributes #2 = { nounwind writeonly }
>attributes #3 = { nounwind }
>
>!0 = !{}
>disasm:
>	s_load_dwordx4 s[0:3], s[2:3], 0x0              ; C00A0001 00000000
>	v_mov_b32_e32 v0, 0                             ; 7E000280
>	s_waitcnt lgkmcnt(0)                            ; BF8C007F
>	buffer_store_dword v0, off, s[0:3], 0           ; E0700000 80000000
>	buffer_store_dword v0, off, s[0:3], 0 offset:4  ; E0700004 80000000
>	buffer_store_dword v0, off, s[0:3], 0 offset:8  ; E0700008 80000000
>	buffer_store_dword v0, off, s[0:3], 0 offset:12 ; E070000C 80000000
>	buffer_store_dword v0, off, s[0:3], 0 offset:16 ; E0700010 80000000
>	buffer_store_dword v0, off, s[0:3], 0 offset:20 ; E0700014 80000000
>	buffer_store_dword v0, off, s[0:3], 0 offset:24 ; E0700018 80000000
>	buffer_store_dword v0, off, s[0:3], 0 offset:28 ; E070001C 80000000
>	s_endpgm                                        ; BF810000
>

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