Attachment 136433 Details for Bug 104407 – dmesg -w

dmesg -w

Fails-dmesg-w (text/plain), 1.44 MB, created by Hector Velazquez on 2017-12-28 21:48:20 UTC

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Creator: Hector Velazquez

Created: 2017-12-28 21:48:20 UTC

Size: 1.44 MB

patch

obsolete

>[ 5163.793465] [drm:skl_compute_wm [i915]] [PLANE:38:plane 1B] ddb (0 - 860) -> (0 - 0)
>[ 5163.793518] [drm:skl_compute_wm [i915]] [PLANE:44:cursor B] ddb (860 - 892) -> (0 - 0)
>[ 5163.793550] [drm:drm_atomic_commit [drm]] committing 00000000c9227e70
>[ 5163.793652] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 5163.810555] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well
>[ 5163.810626] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 2, on? 1) for crtc 47
>[ 5163.810687] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[ 5163.810760] [drm:intel_atomic_commit_tail [i915]] [ENCODER:48:DDI A]
>[ 5163.810816] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI B]
>[ 5163.810867] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[ 5163.810916] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[ 5163.810965] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DDI C]
>[ 5163.811014] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST A]
>[ 5163.811061] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST B]
>[ 5163.811107] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI D]
>[ 5163.811153] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[ 5163.811198] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[ 5163.811251] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:61:DP-2]
>[ 5163.811304] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[ 5163.811356] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[ 5163.811406] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[ 5163.811455] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[ 5163.811504] [drm:intel_power_well_disable [i915]] disabling power well 2
>[ 5163.811560] [drm:intel_atomic_commit_tail [i915]] [CRTC:47:pipe B]
>[ 5163.811595] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000c9227e70
>[ 5163.811621] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000c9227e70
>[ 5163.811828] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[ 5163.811854] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:61:DP-2]
>[ 5163.811878] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000c9227e70
>[ 5163.811903] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:47:pipe B] 00000000c85dec7a state to 00000000c9227e70
>[ 5163.811924] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:38:plane 1B] 00000000261eaafb state to 00000000c9227e70
>[ 5163.811945] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [MODE:1920x1200] for CRTC state 00000000c85dec7a
>[ 5163.811964] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 00000000261eaafb to [CRTC:47:pipe B]
>[ 5163.811982] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:71] for plane state 00000000261eaafb
>[ 5163.812000] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:47:pipe B] to 00000000c9227e70
>[ 5163.812020] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:61:DP-2] 00000000faa5f290 state to 00000000c9227e70
>[ 5163.812037] [drm:drm_atomic_set_crtc_for_connector [drm]] Link connector state 00000000faa5f290 to [CRTC:47:pipe B]
>[ 5163.812056] [drm:drm_atomic_check_only [drm]] checking 00000000c9227e70
>[ 5163.812071] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:47:pipe B] mode changed
>[ 5163.812081] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:47:pipe B] enable changed
>[ 5163.812090] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:47:pipe B] active changed
>[ 5163.812100] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:61:DP-2]
>[ 5163.812110] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:61:DP-2] using [ENCODER:60:DDI C] on [CRTC:47:pipe B]
>[ 5163.812120] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:47:pipe B] needs all connectors, enable: y, active: y
>[ 5163.812138] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:47:pipe B] to 00000000c9227e70
>[ 5163.812158] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:47:pipe B] to 00000000c9227e70
>[ 5163.812224] [drm:intel_atomic_check [i915]] [CONNECTOR:61:DP-2] checking for sink bpp constrains
>[ 5163.812284] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 5163.812347] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 5163.812419] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 5163.812472] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 5163.812530] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 5163.812586] [drm:intel_dump_pipe_config [i915]] [CRTC:47:pipe B][modeset]
>[ 5163.812639] [drm:intel_dump_pipe_config [i915]] output_types: DP (0x80)
>[ 5163.812690] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 5163.812742] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 5163.812790] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[ 5163.812836] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 5163.812862] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[ 5163.812910] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 5163.812934] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[ 5163.812986] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[ 5163.813033] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 5163.813080] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[ 5163.813166] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 5163.813227] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 5163.813284] [drm:intel_dump_pipe_config [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[ 5163.813337] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 5163.813391] [drm:intel_dump_pipe_config [i915]] [PLANE:38:plane 1B] disabled, scaler_id = -1
>[ 5163.813443] [drm:intel_dump_pipe_config [i915]] [PLANE:41:plane 2B] disabled, scaler_id = -1
>[ 5163.813497] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor B] disabled, scaler_id = -1
>[ 5163.813559] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 5163.813618] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[ 5163.813683] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:47:pipe B] has [PLANE:38:plane 1B] with fb 71
>[ 5163.813742] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:38:plane 1B] visible 0 -> 1, off 0, on 1, ms 1
>[ 5163.813806] [drm:intel_find_shared_dpll [i915]] [CRTC:47:pipe B] allocated DPLL 1
>[ 5163.813866] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[ 5163.813905] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:37:pipe A] 00000000ba1798da state to 00000000c9227e70
>[ 5163.813959] [drm:skl_compute_wm [i915]] [PLANE:38:plane 1B] ddb (0 - 0) -> (0 - 860)
>[ 5163.814008] [drm:skl_compute_wm [i915]] [PLANE:44:cursor B] ddb (0 - 0) -> (860 - 892)
>[ 5163.814040] [drm:drm_atomic_commit [drm]] committing 00000000c9227e70
>[ 5164.812068] [drm:intel_power_well_enable [i915]] enabling power well 2
>[ 5164.812143] [drm:intel_atomic_commit_tail [i915]] [ENCODER:48:DDI A]
>[ 5164.812200] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI B]
>[ 5164.812252] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[ 5164.812321] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[ 5164.812374] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DDI C]
>[ 5164.812426] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST A]
>[ 5164.812477] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST B]
>[ 5164.812528] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI D]
>[ 5164.812578] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[ 5164.812628] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[ 5164.812685] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[ 5164.812742] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[ 5164.812796] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[ 5164.812850] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[ 5164.812913] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 2, on? 0) for crtc 47
>[ 5164.812970] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[ 5164.813112] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well
>[ 5164.814248] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 5164.814301] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 5164.814351] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 5164.814400] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 5164.815043] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 04000000
>[ 5164.815090] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[ 5164.815136] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 5164.815769] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 5164.815817] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 5164.816753] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 5164.817213] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:61:DP-2] Link Training Passed at Link Rate = 162000, Lane count = 4
>[ 5164.817756] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 5164.817830] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS
>[ 5164.834592] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:61:DP-2]
>[ 5164.834664] [drm:intel_atomic_commit_tail [i915]] [CRTC:47:pipe B]
>[ 5164.834743] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[ 5164.834781] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000c9227e70
>[ 5164.834807] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000c9227e70
>[ 5164.834865] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[ 5164.834889] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000c9227e70
>[ 5164.834913] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:47:pipe B] 00000000ef7e8929 state to 00000000c9227e70
>[ 5164.834934] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:38:plane 1B] 00000000d91f5621 state to 00000000c9227e70
>[ 5164.834954] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for CRTC state 00000000ef7e8929
>[ 5164.834972] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 00000000d91f5621 to [NOCRTC]
>[ 5164.834991] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for plane state 00000000d91f5621
>[ 5164.835010] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:47:pipe B] to 00000000c9227e70
>[ 5164.835030] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:61:DP-2] 000000007f13d173 state to 00000000c9227e70
>[ 5164.835048] [drm:drm_atomic_set_crtc_for_connector [drm]] Link connector state 000000007f13d173 to [NOCRTC]
>[ 5164.835065] [drm:drm_atomic_check_only [drm]] checking 00000000c9227e70
>[ 5164.835081] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:47:pipe B] mode changed
>[ 5164.835092] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:47:pipe B] enable changed
>[ 5164.835102] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:47:pipe B] active changed
>[ 5164.835111] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:61:DP-2]
>[ 5164.835120] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Disabling [CONNECTOR:61:DP-2]
>[ 5164.835130] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:47:pipe B] needs all connectors, enable: n, active: n
>[ 5164.835150] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:47:pipe B] to 00000000c9227e70
>[ 5164.835224] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 5164.835289] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[ 5164.835353] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:47:pipe B] has [PLANE:38:plane 1B] with fb -1
>[ 5164.835412] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:38:plane 1B] visible 1 -> 0, off 1, on 0, ms 1
>[ 5164.835441] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:37:pipe A] 000000002b48c403 state to 00000000c9227e70
>[ 5164.835492] [drm:skl_compute_wm [i915]] [PLANE:38:plane 1B] ddb (0 - 860) -> (0 - 0)
>[ 5164.835538] [drm:skl_compute_wm [i915]] [PLANE:44:cursor B] ddb (860 - 892) -> (0 - 0)
>[ 5164.835561] [drm:drm_atomic_commit [drm]] committing 00000000c9227e70
>[ 5164.835655] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 5164.851935] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well
>[ 5164.852006] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 2, on? 1) for crtc 47
>[ 5164.852068] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[ 5164.852139] [drm:intel_atomic_commit_tail [i915]] [ENCODER:48:DDI A]
>[ 5164.852194] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI B]
>[ 5164.852245] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[ 5164.852293] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[ 5164.852340] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DDI C]
>[ 5164.852389] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST A]
>[ 5164.852434] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST B]
>[ 5164.852480] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI D]
>[ 5164.852525] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[ 5164.852570] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[ 5164.852622] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:61:DP-2]
>[ 5164.852674] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[ 5164.852726] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[ 5164.852775] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[ 5164.852823] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[ 5164.852873] [drm:intel_power_well_disable [i915]] disabling power well 2
>[ 5164.852929] [drm:intel_atomic_commit_tail [i915]] [CRTC:47:pipe B]
>[ 5164.852963] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000c9227e70
>[ 5164.852988] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000c9227e70
>[ 5164.854354] [IGT] kms_flip: exiting, ret=0
>[ 5164.854707] [drm:intel_power_well_disable [i915]] disabling DC off
>[ 5164.854761] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[ 5164.854808] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[ 5164.855243] [drm:intel_power_well_disable [i915]] disabling always-on
>[ 5164.898743] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000162c6079
>[ 5164.898776] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 0000000057f8b943 state to 00000000162c6079
>[ 5164.898799] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 2A] 00000000e01f1330 state to 00000000162c6079
>[ 5164.898818] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 00000000e01f1330 to [NOCRTC]
>[ 5164.898838] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for plane state 00000000e01f1330
>[ 5164.898856] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:34:cursor A] 00000000d54c0854 state to 00000000162c6079
>[ 5164.898873] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 00000000d54c0854 to [NOCRTC]
>[ 5164.898890] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for plane state 00000000d54c0854
>[ 5164.898907] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:38:plane 1B] 00000000da896c60 state to 00000000162c6079
>[ 5164.898925] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:41:plane 2B] 00000000d98108c3 state to 00000000162c6079
>[ 5164.898941] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 00000000d98108c3 to [NOCRTC]
>[ 5164.898957] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for plane state 00000000d98108c3
>[ 5164.898974] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:44:cursor B] 0000000005f2a656 state to 00000000162c6079
>[ 5164.898991] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 0000000005f2a656 to [NOCRTC]
>[ 5164.899007] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for plane state 0000000005f2a656
>[ 5164.899027] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:37:pipe A] 00000000e1fcf8a7 state to 00000000162c6079
>[ 5164.899051] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [MODE:1920x1080] for CRTC state 00000000e1fcf8a7
>[ 5164.899067] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 0000000057f8b943 to [CRTC:37:pipe A]
>[ 5164.899085] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:115] for plane state 0000000057f8b943
>[ 5164.899103] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:37:pipe A] to 00000000162c6079
>[ 5164.899124] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:56:DP-1] 000000008e78eea9 state to 00000000162c6079
>[ 5164.899141] [drm:drm_atomic_set_crtc_for_connector [drm]] Link connector state 000000008e78eea9 to [CRTC:37:pipe A]
>[ 5164.899160] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:47:pipe B] 0000000024d204e2 state to 00000000162c6079
>[ 5164.899178] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [MODE:1920x1200] for CRTC state 0000000024d204e2
>[ 5164.899195] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 00000000da896c60 to [CRTC:47:pipe B]
>[ 5164.899211] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:115] for plane state 00000000da896c60
>[ 5164.899228] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:47:pipe B] to 00000000162c6079
>[ 5164.899246] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:61:DP-2] 0000000058e88fb4 state to 00000000162c6079
>[ 5164.899263] [drm:drm_atomic_set_crtc_for_connector [drm]] Link connector state 0000000058e88fb4 to [CRTC:47:pipe B]
>[ 5164.899279] [drm:drm_atomic_check_only [drm]] checking 00000000162c6079
>[ 5164.899299] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:37:pipe A] mode changed
>[ 5164.899309] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:37:pipe A] enable changed
>[ 5164.899318] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:37:pipe A] active changed
>[ 5164.899327] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:47:pipe B] mode changed
>[ 5164.899336] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:47:pipe B] enable changed
>[ 5164.899345] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:47:pipe B] active changed
>[ 5164.899359] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:56:DP-1]
>[ 5164.899371] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:56:DP-1] using [ENCODER:55:DDI B] on [CRTC:37:pipe A]
>[ 5164.899380] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:61:DP-2]
>[ 5164.899390] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:61:DP-2] using [ENCODER:60:DDI C] on [CRTC:47:pipe B]
>[ 5164.899400] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:37:pipe A] needs all connectors, enable: y, active: y
>[ 5164.899419] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:37:pipe A] to 00000000162c6079
>[ 5164.899431] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:47:pipe B] needs all connectors, enable: y, active: y
>[ 5164.899449] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:47:pipe B] to 00000000162c6079
>[ 5164.899469] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:37:pipe A] to 00000000162c6079
>[ 5164.899553] [drm:intel_atomic_check [i915]] [CONNECTOR:56:DP-1] checking for sink bpp constrains
>[ 5164.899624] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 148500KHz
>[ 5164.899705] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 4 clock 270000 bpp 36
>[ 5164.899764] [drm:intel_dp_compute_config [i915]] DP link bw required 668250 available 1080000
>[ 5164.899829] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 36, dithering: 0
>[ 5164.899891] [drm:intel_dump_pipe_config [i915]] [CRTC:37:pipe A][modeset]
>[ 5164.899948] [drm:intel_dump_pipe_config [i915]] output_types: DP (0x80)
>[ 5164.900004] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 36, dithering: 0
>[ 5164.900058] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5190451, gmch_n: 8388608, link_m: 288358, link_n: 524288, tu: 64
>[ 5164.900108] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 5164.900158] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 5164.900187] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x9
>[ 5164.900240] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 5164.900266] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x9
>[ 5164.900322] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x9
>[ 5164.900374] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500
>[ 5164.900424] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[ 5164.900473] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 5164.900521] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 5164.900570] [drm:intel_dump_pipe_config [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[ 5164.900617] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 5164.900665] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 1A] disabled, scaler_id = -1
>[ 5164.900713] [drm:intel_dump_pipe_config [i915]] [PLANE:31:plane 2A] disabled, scaler_id = -1
>[ 5164.900760] [drm:intel_dump_pipe_config [i915]] [PLANE:34:cursor A] disabled, scaler_id = -1
>[ 5164.900790] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:47:pipe B] to 00000000162c6079
>[ 5164.900851] [drm:intel_atomic_check [i915]] [CONNECTOR:61:DP-2] checking for sink bpp constrains
>[ 5164.900907] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 5164.900968] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 5164.901039] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 5164.901107] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 5164.901216] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 5164.901285] [drm:intel_dump_pipe_config [i915]] [CRTC:47:pipe B][modeset]
>[ 5164.901348] [drm:intel_dump_pipe_config [i915]] output_types: DP (0x80)
>[ 5164.901408] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 5164.901467] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 5164.901525] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[ 5164.901580] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 5164.901619] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[ 5164.901675] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 5164.901708] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[ 5164.901769] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[ 5164.901826] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 5164.901883] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[ 5164.901938] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 5164.901995] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 5164.902049] [drm:intel_dump_pipe_config [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[ 5164.902104] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 5164.902157] [drm:intel_dump_pipe_config [i915]] [PLANE:38:plane 1B] disabled, scaler_id = -1
>[ 5164.902212] [drm:intel_dump_pipe_config [i915]] [PLANE:41:plane 2B] disabled, scaler_id = -1
>[ 5164.902264] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor B] disabled, scaler_id = -1
>[ 5164.902331] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 5164.902391] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[ 5164.902459] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:37:pipe A] has [PLANE:28:plane 1A] with fb 115
>[ 5164.902519] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 0 -> 1, off 0, on 1, ms 1
>[ 5164.902578] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:47:pipe B] has [PLANE:38:plane 1B] with fb 115
>[ 5164.902629] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:38:plane 1B] visible 0 -> 1, off 0, on 1, ms 1
>[ 5164.902691] [drm:intel_find_shared_dpll [i915]] [CRTC:37:pipe A] allocated DPLL 1
>[ 5164.902747] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[ 5164.902805] [drm:intel_find_shared_dpll [i915]] [CRTC:47:pipe B] allocated DPLL 2
>[ 5164.902868] [drm:intel_reference_shared_dpll [i915]] using DPLL 2 for pipe B
>[ 5164.902934] [drm:skl_compute_wm [i915]] [PLANE:28:plane 1A] ddb (0 - 0) -> (0 - 438)
>[ 5164.902987] [drm:skl_compute_wm [i915]] [PLANE:34:cursor A] ddb (0 - 0) -> (438 - 446)
>[ 5164.903043] [drm:skl_compute_wm [i915]] [PLANE:38:plane 1B] ddb (0 - 0) -> (446 - 884)
>[ 5164.903092] [drm:skl_compute_wm [i915]] [PLANE:44:cursor B] ddb (0 - 0) -> (884 - 892)
>[ 5164.903130] [drm:drm_atomic_commit [drm]] committing 00000000162c6079
>[ 5164.903216] [drm:intel_power_well_enable [i915]] enabling always-on
>[ 5164.903263] [drm:intel_power_well_enable [i915]] enabling DC off
>[ 5164.903539] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[ 5164.903552] [drm:intel_power_well_enable [i915]] enabling power well 2
>[ 5164.903580] [drm:intel_disable_sagv [i915]] Disabling the SAGV
>[ 5164.903598] [drm:intel_atomic_commit_tail [i915]] [ENCODER:48:DDI A]
>[ 5164.903626] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI B]
>[ 5164.903639] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[ 5164.903650] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[ 5164.903661] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DDI C]
>[ 5164.903672] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST A]
>[ 5164.903698] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST B]
>[ 5164.903708] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI D]
>[ 5164.903719] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[ 5164.903730] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[ 5164.903742] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[ 5164.903754] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[ 5164.903766] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[ 5164.903778] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[ 5164.903792] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 37
>[ 5164.903804] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[ 5164.903889] [drm:intel_power_well_enable [i915]] enabling DDI B IO power well
>[ 5164.904452] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5164.905642] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5164.906770] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5164.907897] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5164.909024] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5164.910152] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5164.911272] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5164.911976] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] too many retries, giving up
>[ 5164.912393] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5164.913519] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5164.914638] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5164.915770] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5164.916879] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5164.917990] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5164.919101] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5164.919805] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] too many retries, giving up
>[ 5164.921312] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5164.922416] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5164.923518] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5164.924621] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5164.925627] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5164.926729] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5164.927838] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5164.928523] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] too many retries, giving up
>[ 5164.928943] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5164.930043] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5164.930870] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5164.931968] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5164.933070] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5164.934183] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5164.935302] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5164.935981] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] too many retries, giving up
>[ 5164.937624] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5164.938865] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5164.940094] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5164.941337] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5164.942180] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[ 5164.943117] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 5164.943149] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 5164.943178] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 5164.943206] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 5164.961870] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 5164.961900] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[ 5164.980561] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 5164.980893] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:56:DP-1] Link Training Passed at Link Rate = 270000, Lane count = 4
>[ 5164.981284] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 5164.981311] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS
>[ 5164.981330] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:56:DP-1], [ENCODER:55:DDI B]
>[ 5164.981347] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 5164.981367] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 5164.981396] [drm:intel_fbc_enable [i915]] reserved 8294400 bytes of contiguous stolen space for FBC, threshold: 1
>[ 5164.981414] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 5164.981446] [drm:intel_enable_shared_dpll [i915]] enable DPLL 2 (active 2, on? 0) for crtc 47
>[ 5164.981462] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 2
>[ 5164.981553] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well
>[ 5164.982582] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 5164.982599] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 5164.982615] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 5164.982631] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 5164.983213] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 5164.983229] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 5164.984109] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 5164.984436] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:61:DP-2] Link Training Passed at Link Rate = 162000, Lane count = 4
>[ 5164.984827] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 5164.984887] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS
>[ 5165.001675] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:56:DP-1]
>[ 5165.001694] [drm:intel_atomic_commit_tail [i915]] [CRTC:37:pipe A]
>[ 5165.001718] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[ 5165.001741] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:61:DP-2]
>[ 5165.001757] [drm:intel_atomic_commit_tail [i915]] [CRTC:47:pipe B]
>[ 5165.001778] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[ 5165.001790] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000162c6079
>[ 5165.001797] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000162c6079
>[ 5165.001801] [drm:drm_fb_helper_hotplug_event.part.33 [drm_kms_helper]] 
>[ 5165.001804] [drm:drm_setup_crtcs [drm_kms_helper]] 
>[ 5165.001807] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:49:eDP-1]
>[ 5165.001824] [drm:intel_dp_detect [i915]] [CONNECTOR:49:eDP-1]
>[ 5165.001840] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>[ 5165.001854] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[ 5165.001868] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[ 5165.001937] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[ 5165.002004] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle
>[ 5165.002247] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 00000000 control 00000060
>[ 5165.002314] [drm:wait_panel_status [i915]] Wait complete
>[ 5165.002555] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x00000000 PP_CONTROL: 0x00000068
>[ 5165.002622] [drm:edp_panel_vdd_on [i915]] eDP port A panel power wasn't enabled
>[ 5165.104483] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010
>[ 5165.104519] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[ 5165.104550] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0
>[ 5165.104602] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[ 5165.209783] [drm:drm_dp_read_desc [drm_kms_helper]] DP sink: OUI 00-1c-f8 dev-ID q\006UA\022\001 HW-rev 10.0 SW-rev 1.41 quirks 0x0000
>[ 5165.210960] [drm:drm_add_display_info [drm]] non_desktop set to 0
>[ 5165.210989] [drm:drm_add_edid_modes [drm]] ELD: no CEA Extension found
>[ 5165.211008] [drm:drm_add_display_info [drm]] non_desktop set to 0
>[ 5165.211048] [drm:drm_mode_debug_printmodeline [drm]] Modeline 100:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa
>[ 5165.211066] [drm:drm_mode_prune_invalid [drm]] Not using 1920x1080 mode: CLOCK_HIGH
>[ 5165.211080] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:56:DP-1]
>[ 5165.211151] [drm:intel_dp_detect [i915]] [CONNECTOR:56:DP-1]
>[ 5165.211567] [drm:lspcon_wake_native_aux_ch [i915]] Native AUX CH up, DPCD version: 1.2
>[ 5165.211679] [drm:lspcon_resume [i915]] LSPCON recovering in PCON mode after 0 ms
>[ 5165.212117] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5165.213358] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5165.214629] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5165.215888] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5165.217171] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5165.218080] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[ 5165.218558] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 00 00 04 00 0f 00 04
>[ 5165.219326] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>[ 5165.219380] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000
>[ 5165.219431] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000
>[ 5165.219833] [drm:drm_dp_read_desc [drm_kms_helper]] DP branch: OUI 00-60-ad dev-ID MC2800 HW-rev 2.2 SW-rev 1.72 quirks 0x0000
>[ 5165.220182] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[ 5165.220952] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5165.222197] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5165.223468] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5165.224734] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5165.225945] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5165.227197] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5165.228466] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5165.229811] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5165.231073] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5165.232464] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5165.233944] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5165.235339] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5165.236730] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5165.238064] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5165.239459] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5165.240849] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5165.242208] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5165.243460] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5165.244727] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5165.245931] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5165.247188] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5165.248578] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5165.249928] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5165.251318] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5165.252706] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5165.254036] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5165.255428] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5165.256816] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5165.258179] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5165.259022] [drm:drm_detect_monitor_audio [drm]] Monitor has basic audio support
>[ 5165.259346] [drm:drm_add_display_info [drm]] non_desktop set to 0
>[ 5165.259365] [drm:drm_add_display_info [drm]] HDMI: DVI dual 0, max TMDS clock 225000 kHz
>[ 5165.259389] [drm:drm_add_edid_modes [drm]] ELD monitor BOBCAT2800
>[ 5165.259405] [drm:drm_add_edid_modes [drm]] HDMI: latency present 0 0, video latency 0 0, audio latency 0 0
>[ 5165.259419] [drm:drm_add_edid_modes [drm]] ELD size 36, SAD count 1
>[ 5165.259433] [drm:drm_add_display_info [drm]] non_desktop set to 0
>[ 5165.259447] [drm:drm_add_display_info [drm]] HDMI: DVI dual 0, max TMDS clock 225000 kHz
>[ 5165.259864] [drm:drm_mode_debug_printmodeline [drm]] Modeline 139:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[ 5165.259881] [drm:drm_mode_prune_invalid [drm]] Not using 720x480i mode: H_ILLEGAL
>[ 5165.259898] [drm:drm_mode_debug_printmodeline [drm]] Modeline 140:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[ 5165.259911] [drm:drm_mode_prune_invalid [drm]] Not using 720x576i mode: H_ILLEGAL
>[ 5165.259927] [drm:drm_mode_debug_printmodeline [drm]] Modeline 160:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[ 5165.259940] [drm:drm_mode_prune_invalid [drm]] Not using 720x480i mode: H_ILLEGAL
>[ 5165.259957] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:56:DP-1] probed modes :
>[ 5165.259974] [drm:drm_mode_debug_printmodeline [drm]] Modeline 74:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x9
>[ 5165.259989] [drm:drm_mode_debug_printmodeline [drm]] Modeline 81:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x40 0x9
>[ 5165.260004] [drm:drm_mode_debug_printmodeline [drm]] Modeline 75:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[ 5165.260018] [drm:drm_mode_debug_printmodeline [drm]] Modeline 120:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[ 5165.260033] [drm:drm_mode_debug_printmodeline [drm]] Modeline 76:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[ 5165.260047] [drm:drm_mode_debug_printmodeline [drm]] Modeline 121:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[ 5165.260062] [drm:drm_mode_debug_printmodeline [drm]] Modeline 109:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[ 5165.260077] [drm:drm_mode_debug_printmodeline [drm]] Modeline 114:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[ 5165.260091] [drm:drm_mode_debug_printmodeline [drm]] Modeline 116:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[ 5165.260105] [drm:drm_mode_debug_printmodeline [drm]] Modeline 132:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[ 5165.260120] [drm:drm_mode_debug_printmodeline [drm]] Modeline 80:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[ 5165.260134] [drm:drm_mode_debug_printmodeline [drm]] Modeline 87:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[ 5165.260148] [drm:drm_mode_debug_printmodeline [drm]] Modeline 79:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[ 5165.260163] [drm:drm_mode_debug_printmodeline [drm]] Modeline 82:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[ 5165.260177] [drm:drm_mode_debug_printmodeline [drm]] Modeline 77:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[ 5165.260192] [drm:drm_mode_debug_printmodeline [drm]] Modeline 122:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[ 5165.260206] [drm:drm_mode_debug_printmodeline [drm]] Modeline 113:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[ 5165.260220] [drm:drm_mode_debug_printmodeline [drm]] Modeline 88:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[ 5165.260234] [drm:drm_mode_debug_printmodeline [drm]] Modeline 89:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[ 5165.260249] [drm:drm_mode_debug_printmodeline [drm]] Modeline 90:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[ 5165.260263] [drm:drm_mode_debug_printmodeline [drm]] Modeline 83:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[ 5165.260278] [drm:drm_mode_debug_printmodeline [drm]] Modeline 110:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[ 5165.260292] [drm:drm_mode_debug_printmodeline [drm]] Modeline 123:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[ 5165.260306] [drm:drm_mode_debug_printmodeline [drm]] Modeline 78:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[ 5165.260320] [drm:drm_mode_debug_printmodeline [drm]] Modeline 84:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[ 5165.260334] [drm:drm_mode_debug_printmodeline [drm]] Modeline 124:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[ 5165.260349] [drm:drm_mode_debug_printmodeline [drm]] Modeline 85:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[ 5165.260363] [drm:drm_mode_debug_printmodeline [drm]] Modeline 86:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[ 5165.260373] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:61:DP-2]
>[ 5165.260435] [drm:intel_dp_detect [i915]] [CONNECTOR:61:DP-2]
>[ 5165.260945] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 00 02 02 06 05 00 00 00
>[ 5165.261333] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>[ 5165.261393] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[ 5165.261451] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[ 5165.261850] [drm:drm_dp_read_desc [drm_kms_helper]] DP sink: OUI 00-00-00 dev-ID  HW-rev 0.0 SW-rev 0.0 quirks 0x0000
>[ 5165.261905] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[ 5165.265858] [drm:drm_add_display_info [drm]] non_desktop set to 0
>[ 5165.265881] [drm:drm_add_edid_modes [drm]] ELD: no CEA Extension found
>[ 5165.265898] [drm:drm_add_display_info [drm]] non_desktop set to 0
>[ 5165.266043] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:61:DP-2] probed modes :
>[ 5165.266063] [drm:drm_mode_debug_printmodeline [drm]] Modeline 91:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[ 5165.266080] [drm:drm_mode_debug_printmodeline [drm]] Modeline 95:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0xa
>[ 5165.266095] [drm:drm_mode_debug_printmodeline [drm]] Modeline 103:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[ 5165.266109] [drm:drm_mode_debug_printmodeline [drm]] Modeline 92:"1680x1050" 60 146250 1680 1784 1960 2240 1050 1053 1059 1089 0x40 0x6
>[ 5165.266124] [drm:drm_mode_debug_printmodeline [drm]] Modeline 96:"1600x900" 60 108000 1600 1624 1704 1800 900 901 904 1000 0x40 0x5
>[ 5165.266138] [drm:drm_mode_debug_printmodeline [drm]] Modeline 104:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[ 5165.266152] [drm:drm_mode_debug_printmodeline [drm]] Modeline 93:"1440x900" 60 106500 1440 1520 1672 1904 900 903 909 934 0x40 0x6
>[ 5165.266167] [drm:drm_mode_debug_printmodeline [drm]] Modeline 94:"1280x800" 60 83500 1280 1352 1480 1680 800 803 809 831 0x40 0x6
>[ 5165.266181] [drm:drm_mode_debug_printmodeline [drm]] Modeline 97:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[ 5165.266195] [drm:drm_mode_debug_printmodeline [drm]] Modeline 112:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[ 5165.266210] [drm:drm_mode_debug_printmodeline [drm]] Modeline 105:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[ 5165.266224] [drm:drm_mode_debug_printmodeline [drm]] Modeline 111:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[ 5165.266234] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:64:HDMI-A-1]
>[ 5165.266294] [drm:intel_hdmi_detect [i915]] [CONNECTOR:64:HDMI-A-1]
>[ 5165.266822] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[ 5165.266872] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[ 5165.267299] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[ 5165.267394] [drm:drm_do_probe_ddc_edid [drm]] drm: skipping non-existent adapter i915 gmbus dpc
>[ 5165.267818] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[ 5165.267862] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[ 5165.268248] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[ 5165.268312] [drm:drm_dp_dual_mode_detect [drm_kms_helper]] DP dual mode HDMI ID:  (err -6)
>[ 5165.268323] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:64:HDMI-A-1] disconnected
>[ 5165.268333] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:67:DP-3]
>[ 5165.268381] [drm:intel_dp_detect [i915]] [CONNECTOR:67:DP-3]
>[ 5165.268427] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:67:DP-3] disconnected
>[ 5165.268436] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:70:HDMI-A-2]
>[ 5165.268481] [drm:intel_hdmi_detect [i915]] [CONNECTOR:70:HDMI-A-2]
>[ 5165.288689] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0050 w(1)
>[ 5165.288736] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK on first message, retry
>[ 5165.308972] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0050 w(1)
>[ 5165.309054] [drm:drm_do_probe_ddc_edid [drm]] drm: skipping non-existent adapter i915 gmbus dpd
>[ 5165.329324] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0040 w(1)
>[ 5165.329386] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK on first message, retry
>[ 5165.349488] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0040 w(1)
>[ 5165.349575] [drm:drm_dp_dual_mode_detect [drm_kms_helper]] DP dual mode HDMI ID:  (err -6)
>[ 5165.349585] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:70:HDMI-A-2] disconnected
>[ 5165.349598] [drm:drm_setup_crtcs [drm_kms_helper]] connector 49 enabled? yes
>[ 5165.349607] [drm:drm_setup_crtcs [drm_kms_helper]] connector 56 enabled? yes
>[ 5165.349616] [drm:drm_setup_crtcs [drm_kms_helper]] connector 61 enabled? yes
>[ 5165.349626] [drm:drm_setup_crtcs [drm_kms_helper]] connector 64 enabled? no
>[ 5165.349635] [drm:drm_setup_crtcs [drm_kms_helper]] connector 67 enabled? no
>[ 5165.349644] [drm:drm_setup_crtcs [drm_kms_helper]] connector 70 enabled? no
>[ 5165.349702] [drm:intel_fb_initial_config [i915]] Not using firmware configuration
>[ 5165.349715] [drm:drm_setup_crtcs [drm_kms_helper]] looking for cmdline mode on connector 49
>[ 5165.349725] [drm:drm_setup_crtcs [drm_kms_helper]] looking for preferred mode on connector 49 0
>[ 5165.349734] [drm:drm_setup_crtcs [drm_kms_helper]] found mode none
>[ 5165.349743] [drm:drm_setup_crtcs [drm_kms_helper]] looking for cmdline mode on connector 56
>[ 5165.349752] [drm:drm_setup_crtcs [drm_kms_helper]] looking for preferred mode on connector 56 0
>[ 5165.349761] [drm:drm_setup_crtcs [drm_kms_helper]] found mode 1920x1080
>[ 5165.349770] [drm:drm_setup_crtcs [drm_kms_helper]] looking for cmdline mode on connector 61
>[ 5165.349779] [drm:drm_setup_crtcs [drm_kms_helper]] looking for preferred mode on connector 61 0
>[ 5165.349788] [drm:drm_setup_crtcs [drm_kms_helper]] found mode 1920x1200
>[ 5165.349797] [drm:drm_setup_crtcs [drm_kms_helper]] picking CRTCs for 1920x1200 config
>[ 5165.349813] [drm:drm_setup_crtcs [drm_kms_helper]] desired mode 1920x1080 set on crtc 37 (0,0)
>[ 5165.349824] [drm:drm_setup_crtcs [drm_kms_helper]] desired mode 1920x1200 set on crtc 47 (0,0)
>[ 5165.349856] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000000fefa0bc
>[ 5165.349881] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 0000000055fe572b state to 000000000fefa0bc
>[ 5165.349904] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:37:pipe A] 00000000ef7e8929 state to 000000000fefa0bc
>[ 5165.349923] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 2A] 0000000032a3a1e1 state to 000000000fefa0bc
>[ 5165.349940] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 0000000032a3a1e1 to [NOCRTC]
>[ 5165.349959] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for plane state 0000000032a3a1e1
>[ 5165.349976] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:34:cursor A] 00000000bb3ca1c0 state to 000000000fefa0bc
>[ 5165.349992] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 00000000bb3ca1c0 to [NOCRTC]
>[ 5165.350008] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for plane state 00000000bb3ca1c0
>[ 5165.350024] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:38:plane 1B] 00000000d603436b state to 000000000fefa0bc
>[ 5165.350041] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:47:pipe B] 000000002b48c403 state to 000000000fefa0bc
>[ 5165.350056] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:41:plane 2B] 000000005aff8048 state to 000000000fefa0bc
>[ 5165.350072] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 000000005aff8048 to [NOCRTC]
>[ 5165.350087] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for plane state 000000005aff8048
>[ 5165.350103] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:44:cursor B] 000000007867cbaf state to 000000000fefa0bc
>[ 5165.350118] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 000000007867cbaf to [NOCRTC]
>[ 5165.350133] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for plane state 000000007867cbaf
>[ 5165.350152] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [MODE:1920x1080] for CRTC state 00000000ef7e8929
>[ 5165.350168] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 0000000055fe572b to [CRTC:37:pipe A]
>[ 5165.350183] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:115] for plane state 0000000055fe572b
>[ 5165.350200] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:37:pipe A] to 000000000fefa0bc
>[ 5165.350217] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:56:DP-1] 00000000e58e1614 state to 000000000fefa0bc
>[ 5165.350233] [drm:drm_atomic_set_crtc_for_connector [drm]] Link connector state 00000000e58e1614 to [NOCRTC]
>[ 5165.350249] [drm:drm_atomic_set_crtc_for_connector [drm]] Link connector state 00000000e58e1614 to [CRTC:37:pipe A]
>[ 5165.350267] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [MODE:1920x1200] for CRTC state 000000002b48c403
>[ 5165.350283] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 00000000d603436b to [CRTC:47:pipe B]
>[ 5165.350298] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:115] for plane state 00000000d603436b
>[ 5165.350314] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:47:pipe B] to 000000000fefa0bc
>[ 5165.350330] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:61:DP-2] 00000000faa5f290 state to 000000000fefa0bc
>[ 5165.350346] [drm:drm_atomic_set_crtc_for_connector [drm]] Link connector state 00000000faa5f290 to [NOCRTC]
>[ 5165.350361] [drm:drm_atomic_set_crtc_for_connector [drm]] Link connector state 00000000faa5f290 to [CRTC:47:pipe B]
>[ 5165.350376] [drm:drm_atomic_check_only [drm]] checking 000000000fefa0bc
>[ 5165.350394] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:56:DP-1]
>[ 5165.350406] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:56:DP-1] keeps [ENCODER:55:DDI B], now on [CRTC:37:pipe A]
>[ 5165.350415] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:61:DP-2]
>[ 5165.350424] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:61:DP-2] keeps [ENCODER:60:DDI C], now on [CRTC:47:pipe B]
>[ 5165.350494] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:37:pipe A] has [PLANE:28:plane 1A] with fb 115
>[ 5165.350554] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>[ 5165.350611] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:47:pipe B] has [PLANE:38:plane 1B] with fb 115
>[ 5165.350664] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:38:plane 1B] visible 1 -> 1, off 0, on 0, ms 0
>[ 5165.350699] [drm:drm_atomic_commit [drm]] committing 000000000fefa0bc
>[ 5165.364722] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000000fefa0bc
>[ 5165.364749] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000000fefa0bc
>[ 5165.427474] [IGT] kms_render: executing
>[ 5165.465607] [IGT] kms_render: starting subtest direct-render
>[ 5165.465858] [drm:drm_mode_addfb2 [drm]] [FB:71]
>[ 5165.465900] [drm:drm_mode_addfb2 [drm]] [FB:98]
>[ 5165.465928] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[ 5165.465954] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:56:DP-1]
>[ 5165.465982] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000e57367c2
>[ 5165.466009] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:37:pipe A] 0000000034b58950 state to 00000000e57367c2
>[ 5165.466031] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000d9719b68 state to 00000000e57367c2
>[ 5165.466053] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [MODE:1920x1080] for CRTC state 0000000034b58950
>[ 5165.466072] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 00000000d9719b68 to [CRTC:37:pipe A]
>[ 5165.466135] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:71] for plane state 00000000d9719b68
>[ 5165.466154] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:37:pipe A] to 00000000e57367c2
>[ 5165.466174] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:56:DP-1] 0000000029fd320b state to 00000000e57367c2
>[ 5165.466192] [drm:drm_atomic_set_crtc_for_connector [drm]] Link connector state 0000000029fd320b to [NOCRTC]
>[ 5165.466209] [drm:drm_atomic_set_crtc_for_connector [drm]] Link connector state 0000000029fd320b to [CRTC:37:pipe A]
>[ 5165.466229] [drm:drm_atomic_check_only [drm]] checking 00000000e57367c2
>[ 5165.466250] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:56:DP-1]
>[ 5165.466262] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:56:DP-1] keeps [ENCODER:55:DDI B], now on [CRTC:37:pipe A]
>[ 5165.466353] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:37:pipe A] has [PLANE:28:plane 1A] with fb 71
>[ 5165.466420] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>[ 5165.466454] [drm:drm_atomic_commit [drm]] committing 00000000e57367c2
>[ 5165.481415] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000e57367c2
>[ 5165.481449] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000e57367c2
>[ 5165.481497] [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000047bcff61
>[ 5165.481524] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:37:pipe A] 00000000ef7e8929 state to 0000000047bcff61
>[ 5165.481546] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000499e6cef state to 0000000047bcff61
>[ 5165.481565] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 00000000499e6cef to [CRTC:37:pipe A]
>[ 5165.481584] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:71] for plane state 00000000499e6cef
>[ 5165.481602] [drm:drm_atomic_check_only [drm]] checking 0000000047bcff61
>[ 5165.481691] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:37:pipe A] has [PLANE:28:plane 1A] with fb 71
>[ 5165.481758] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>[ 5165.481792] [drm:drm_atomic_nonblocking_commit [drm]] committing 0000000047bcff61 nonblocking
>[ 5165.498199] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000047bcff61
>[ 5165.498230] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000047bcff61
>[ 5166.361919] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 5166.361992] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 5166.362116] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[ 5166.362609] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 00 00 04 00 0f 00 04
>[ 5166.362970] [drm:i915_hotplug_work_func [i915]] running encoder hotplug functions
>[ 5166.363028] [drm:i915_hotplug_work_func [i915]] Connector DP-1 (pin 5) received hotplug event.
>[ 5166.363083] [drm:intel_dp_detect [i915]] [CONNECTOR:56:DP-1]
>[ 5166.363493] [drm:lspcon_wake_native_aux_ch [i915]] Native AUX CH up, DPCD version: 1.2
>[ 5166.363599] [drm:lspcon_resume [i915]] LSPCON recovering in PCON mode after 0 ms
>[ 5166.364035] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5166.365307] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5166.366569] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5166.367823] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5166.369124] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5166.370009] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[ 5166.370479] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 00 00 04 00 0f 00 04
>[ 5166.370840] [drm:i915_hotplug_work_func [i915]] [CONNECTOR:56:DP-1] status updated from connected to disconnected
>[ 5168.377293] [drm:edp_panel_vdd_off_sync [i915]] Turning eDP port A VDD off
>[ 5168.377591] [drm:edp_panel_vdd_off_sync [i915]] PP_STATUS: 0x00000000 PP_CONTROL: 0x00000060
>[ 5168.385106] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010
>[ 5168.385178] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[ 5168.385242] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0
>[ 5168.385349] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[ 5168.436823] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 5168.436895] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 5168.437001] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[ 5168.437496] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 00 00 04 00 0f 00 04
>[ 5168.438264] [drm:i915_hotplug_work_func [i915]] running encoder hotplug functions
>[ 5168.438323] [drm:i915_hotplug_work_func [i915]] Connector DP-1 (pin 5) received hotplug event.
>[ 5168.438378] [drm:intel_dp_detect [i915]] [CONNECTOR:56:DP-1]
>[ 5168.438786] [drm:lspcon_wake_native_aux_ch [i915]] Native AUX CH up, DPCD version: 1.2
>[ 5168.438893] [drm:lspcon_resume [i915]] LSPCON recovering in PCON mode after 0 ms
>[ 5168.439329] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5168.440562] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5168.441770] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5168.443003] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5168.444263] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5168.445186] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[ 5168.445672] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 00 00 04 00 0f 00 04
>[ 5168.446439] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>[ 5168.446492] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000
>[ 5168.446541] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000
>[ 5168.446939] [drm:drm_dp_read_desc [drm_kms_helper]] DP branch: OUI 00-60-ad dev-ID MC2800 HW-rev 2.2 SW-rev 1.72 quirks 0x0000
>[ 5168.447285] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[ 5168.448052] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5168.449321] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5168.450585] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5168.451839] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5168.453130] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5168.454389] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5168.455653] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5168.456914] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5168.458177] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5168.459567] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5168.460955] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5168.462346] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5168.463737] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5168.465131] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5168.466529] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5168.467915] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5168.469297] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5168.470545] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5168.471808] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5168.473069] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5168.474385] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5168.475775] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5168.477174] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5168.478561] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5168.479951] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5168.481347] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5168.482735] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5168.484121] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5168.485537] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5168.486381] [drm:drm_detect_monitor_audio [drm]] Monitor has basic audio support
>[ 5168.486749] [drm:i915_hotplug_work_func [i915]] [CONNECTOR:56:DP-1] status updated from disconnected to connected
>[ 5172.666319] [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000043e34f58
>[ 5172.666358] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000e3ceaa91 state to 0000000043e34f58
>[ 5172.666386] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:37:pipe A] 00000000604357f6 state to 0000000043e34f58
>[ 5172.666410] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for plane state 00000000e3ceaa91
>[ 5172.666431] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 00000000e3ceaa91 to [NOCRTC]
>[ 5172.666453] [drm:drm_atomic_check_only [drm]] checking 0000000043e34f58
>[ 5172.666550] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:37:pipe A] has [PLANE:28:plane 1A] with fb -1
>[ 5172.666625] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 0, off 1, on 0, ms 0
>[ 5172.666688] [drm:skl_compute_wm [i915]] [PLANE:28:plane 1A] ddb (0 - 438) -> (0 - 0)
>[ 5172.666716] [drm:drm_atomic_commit [drm]] committing 0000000043e34f58
>[ 5172.681390] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000043e34f58
>[ 5172.681423] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000043e34f58
>[ 5172.681606] [drm:drm_mode_addfb2 [drm]] [FB:71]
>[ 5172.681653] [drm:drm_mode_addfb2 [drm]] [FB:73]
>[ 5172.681684] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[ 5172.681714] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:56:DP-1]
>[ 5172.681744] [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000099c77857
>[ 5172.681774] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:37:pipe A] 000000007b1f6733 state to 0000000099c77857
>[ 5172.681798] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 0000000046f05351 state to 0000000099c77857
>[ 5172.681823] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [MODE:1920x1080] for CRTC state 000000007b1f6733
>[ 5172.681844] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 0000000046f05351 to [CRTC:37:pipe A]
>[ 5172.681865] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:71] for plane state 0000000046f05351
>[ 5172.681886] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:37:pipe A] to 0000000099c77857
>[ 5172.681909] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:56:DP-1] 0000000017a83230 state to 0000000099c77857
>[ 5172.681930] [drm:drm_atomic_set_crtc_for_connector [drm]] Link connector state 0000000017a83230 to [NOCRTC]
>[ 5172.681949] [drm:drm_atomic_set_crtc_for_connector [drm]] Link connector state 0000000017a83230 to [CRTC:37:pipe A]
>[ 5172.681973] [drm:drm_atomic_check_only [drm]] checking 0000000099c77857
>[ 5172.681995] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:56:DP-1]
>[ 5172.682009] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:56:DP-1] keeps [ENCODER:55:DDI B], now on [CRTC:37:pipe A]
>[ 5172.682106] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:37:pipe A] has [PLANE:28:plane 1A] with fb 71
>[ 5172.682181] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 0 -> 1, off 0, on 1, ms 0
>[ 5172.682245] [drm:skl_compute_wm [i915]] [PLANE:28:plane 1A] ddb (0 - 0) -> (0 - 438)
>[ 5172.682271] [drm:drm_atomic_commit [drm]] committing 0000000099c77857
>[ 5172.698215] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000099c77857
>[ 5172.698225] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000099c77857
>[ 5172.698238] [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000043e34f58
>[ 5172.698246] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:37:pipe A] 00000000604357f6 state to 0000000043e34f58
>[ 5172.698251] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000e3ceaa91 state to 0000000043e34f58
>[ 5172.698255] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 00000000e3ceaa91 to [CRTC:37:pipe A]
>[ 5172.698260] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:71] for plane state 00000000e3ceaa91
>[ 5172.698265] [drm:drm_atomic_check_only [drm]] checking 0000000043e34f58
>[ 5172.698291] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:37:pipe A] has [PLANE:28:plane 1A] with fb 71
>[ 5172.698307] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>[ 5172.698316] [drm:drm_atomic_nonblocking_commit [drm]] committing 0000000043e34f58 nonblocking
>[ 5172.714860] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000043e34f58
>[ 5172.714871] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000043e34f58
>[ 5179.730981] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000e0d3124a
>[ 5179.731019] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000366b2994 state to 00000000e0d3124a
>[ 5179.731046] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:37:pipe A] 00000000ef7e8929 state to 00000000e0d3124a
>[ 5179.731069] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for plane state 00000000366b2994
>[ 5179.731089] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 00000000366b2994 to [NOCRTC]
>[ 5179.731112] [drm:drm_atomic_check_only [drm]] checking 00000000e0d3124a
>[ 5179.731209] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:37:pipe A] has [PLANE:28:plane 1A] with fb -1
>[ 5179.731284] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 0, off 1, on 0, ms 0
>[ 5179.731346] [drm:skl_compute_wm [i915]] [PLANE:28:plane 1A] ddb (0 - 438) -> (0 - 0)
>[ 5179.731374] [drm:drm_atomic_commit [drm]] committing 00000000e0d3124a
>[ 5179.748352] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000e0d3124a
>[ 5179.748385] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000e0d3124a
>[ 5179.748573] [drm:drm_mode_addfb2 [drm]] [FB:71]
>[ 5179.748620] [drm:drm_mode_addfb2 [drm]] [FB:73]
>[ 5179.748650] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[ 5179.748680] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:56:DP-1]
>[ 5179.748711] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000ae4a27ef
>[ 5179.748742] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:37:pipe A] 00000000fd63c90d state to 00000000ae4a27ef
>[ 5179.748766] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000420f0690 state to 00000000ae4a27ef
>[ 5179.748792] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [MODE:1920x1080] for CRTC state 00000000fd63c90d
>[ 5179.748814] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 00000000420f0690 to [CRTC:37:pipe A]
>[ 5179.748835] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:71] for plane state 00000000420f0690
>[ 5179.748856] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:37:pipe A] to 00000000ae4a27ef
>[ 5179.748878] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:56:DP-1] 00000000cb20bf08 state to 00000000ae4a27ef
>[ 5179.748899] [drm:drm_atomic_set_crtc_for_connector [drm]] Link connector state 00000000cb20bf08 to [NOCRTC]
>[ 5179.748918] [drm:drm_atomic_set_crtc_for_connector [drm]] Link connector state 00000000cb20bf08 to [CRTC:37:pipe A]
>[ 5179.748942] [drm:drm_atomic_check_only [drm]] checking 00000000ae4a27ef
>[ 5179.748964] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:56:DP-1]
>[ 5179.748979] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:56:DP-1] keeps [ENCODER:55:DDI B], now on [CRTC:37:pipe A]
>[ 5179.749075] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:37:pipe A] has [PLANE:28:plane 1A] with fb 71
>[ 5179.749211] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 0 -> 1, off 0, on 1, ms 0
>[ 5179.749293] [drm:skl_compute_wm [i915]] [PLANE:28:plane 1A] ddb (0 - 0) -> (0 - 438)
>[ 5179.749331] [drm:drm_atomic_commit [drm]] committing 00000000ae4a27ef
>[ 5179.764943] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000ae4a27ef
>[ 5179.764953] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000ae4a27ef
>[ 5179.764967] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000e0d3124a
>[ 5179.764974] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:37:pipe A] 00000000ef7e8929 state to 00000000e0d3124a
>[ 5179.764980] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000366b2994 state to 00000000e0d3124a
>[ 5179.764984] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 00000000366b2994 to [CRTC:37:pipe A]
>[ 5179.764989] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:71] for plane state 00000000366b2994
>[ 5179.764993] [drm:drm_atomic_check_only [drm]] checking 00000000e0d3124a
>[ 5179.765019] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:37:pipe A] has [PLANE:28:plane 1A] with fb 71
>[ 5179.765036] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>[ 5179.765045] [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000e0d3124a nonblocking
>[ 5179.781351] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000e0d3124a
>[ 5179.781363] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000e0d3124a
>[ 5187.174116] [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000005397892
>[ 5187.174151] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000c4e4455d state to 0000000005397892
>[ 5187.174177] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:37:pipe A] 00000000604357f6 state to 0000000005397892
>[ 5187.174198] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for plane state 00000000c4e4455d
>[ 5187.174217] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 00000000c4e4455d to [NOCRTC]
>[ 5187.174237] [drm:drm_atomic_check_only [drm]] checking 0000000005397892
>[ 5187.174324] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:37:pipe A] has [PLANE:28:plane 1A] with fb -1
>[ 5187.174390] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 0, off 1, on 0, ms 0
>[ 5187.174444] [drm:skl_compute_wm [i915]] [PLANE:28:plane 1A] ddb (0 - 438) -> (0 - 0)
>[ 5187.174468] [drm:drm_atomic_commit [drm]] committing 0000000005397892
>[ 5187.181445] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000005397892
>[ 5187.181475] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000005397892
>[ 5187.181648] [drm:drm_mode_addfb2 [drm]] [FB:71]
>[ 5187.181690] [drm:drm_mode_addfb2 [drm]] [FB:73]
>[ 5187.181717] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[ 5187.181744] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:56:DP-1]
>[ 5187.181770] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000005828b813
>[ 5187.181797] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:37:pipe A] 0000000018046d93 state to 000000005828b813
>[ 5187.181819] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 0000000063e42a62 state to 000000005828b813
>[ 5187.181842] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [MODE:1920x1080] for CRTC state 0000000018046d93
>[ 5187.181861] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 0000000063e42a62 to [CRTC:37:pipe A]
>[ 5187.181880] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:71] for plane state 0000000063e42a62
>[ 5187.181899] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:37:pipe A] to 000000005828b813
>[ 5187.181920] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:56:DP-1] 00000000db02382d state to 000000005828b813
>[ 5187.181939] [drm:drm_atomic_set_crtc_for_connector [drm]] Link connector state 00000000db02382d to [NOCRTC]
>[ 5187.181956] [drm:drm_atomic_set_crtc_for_connector [drm]] Link connector state 00000000db02382d to [CRTC:37:pipe A]
>[ 5187.181977] [drm:drm_atomic_check_only [drm]] checking 000000005828b813
>[ 5187.181998] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:56:DP-1]
>[ 5187.182011] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:56:DP-1] keeps [ENCODER:55:DDI B], now on [CRTC:37:pipe A]
>[ 5187.182099] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:37:pipe A] has [PLANE:28:plane 1A] with fb 71
>[ 5187.182167] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 0 -> 1, off 0, on 1, ms 0
>[ 5187.182224] [drm:skl_compute_wm [i915]] [PLANE:28:plane 1A] ddb (0 - 0) -> (0 - 438)
>[ 5187.182248] [drm:drm_atomic_commit [drm]] committing 000000005828b813
>[ 5187.198233] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000005828b813
>[ 5187.198244] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000005828b813
>[ 5187.198258] [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000005397892
>[ 5187.198265] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:37:pipe A] 00000000604357f6 state to 0000000005397892
>[ 5187.198270] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000c4e4455d state to 0000000005397892
>[ 5187.198275] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 00000000c4e4455d to [CRTC:37:pipe A]
>[ 5187.198280] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:71] for plane state 00000000c4e4455d
>[ 5187.198284] [drm:drm_atomic_check_only [drm]] checking 0000000005397892
>[ 5187.198310] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:37:pipe A] has [PLANE:28:plane 1A] with fb 71
>[ 5187.198326] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>[ 5187.198335] [drm:drm_atomic_nonblocking_commit [drm]] committing 0000000005397892 nonblocking
>[ 5187.214889] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000005397892
>[ 5187.214900] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000005397892
>[ 5194.230890] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000009cf785c6
>[ 5194.230930] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000436a997d state to 000000009cf785c6
>[ 5194.230958] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:37:pipe A] 00000000ef7e8929 state to 000000009cf785c6
>[ 5194.230981] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for plane state 00000000436a997d
>[ 5194.231003] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 00000000436a997d to [NOCRTC]
>[ 5194.231025] [drm:drm_atomic_check_only [drm]] checking 000000009cf785c6
>[ 5194.231120] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:37:pipe A] has [PLANE:28:plane 1A] with fb -1
>[ 5194.231195] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 0, off 1, on 0, ms 0
>[ 5194.231258] [drm:skl_compute_wm [i915]] [PLANE:28:plane 1A] ddb (0 - 438) -> (0 - 0)
>[ 5194.231285] [drm:drm_atomic_commit [drm]] committing 000000009cf785c6
>[ 5194.248378] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000009cf785c6
>[ 5194.248412] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000009cf785c6
>[ 5194.248659] [drm:drm_mode_addfb2 [drm]] [FB:71]
>[ 5194.248706] [drm:drm_mode_addfb2 [drm]] [FB:73]
>[ 5194.248735] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[ 5194.248765] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:56:DP-1]
>[ 5194.248795] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000003bd6433a
>[ 5194.248826] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:47:pipe B] 0000000052fcd53d state to 000000003bd6433a
>[ 5194.248850] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:38:plane 1B] 000000003b0972d9 state to 000000003bd6433a
>[ 5194.248876] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [MODE:1920x1080] for CRTC state 0000000052fcd53d
>[ 5194.248898] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 000000003b0972d9 to [CRTC:47:pipe B]
>[ 5194.248920] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:71] for plane state 000000003b0972d9
>[ 5194.248941] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:47:pipe B] to 000000003bd6433a
>[ 5194.248964] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:61:DP-2] 00000000a92bebac state to 000000003bd6433a
>[ 5194.248984] [drm:drm_atomic_set_crtc_for_connector [drm]] Link connector state 00000000a92bebac to [NOCRTC]
>[ 5194.249004] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:56:DP-1] 00000000f11217d0 state to 000000003bd6433a
>[ 5194.249024] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:37:pipe A] 0000000043cb4c64 state to 000000003bd6433a
>[ 5194.249043] [drm:drm_atomic_set_crtc_for_connector [drm]] Link connector state 00000000f11217d0 to [CRTC:47:pipe B]
>[ 5194.249064] [drm:drm_atomic_set_mode_prop_for_crtc [drm]] Set [NOMODE] for CRTC state 0000000043cb4c64
>[ 5194.249148] [drm:drm_atomic_check_only [drm]] checking 000000003bd6433a
>[ 5194.249186] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:37:pipe A] mode changed
>[ 5194.249203] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:37:pipe A] enable changed
>[ 5194.249226] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:37:pipe A] active changed
>[ 5194.249248] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:47:pipe B] mode changed
>[ 5194.249268] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:56:DP-1]
>[ 5194.249290] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:56:DP-1] keeps [ENCODER:55:DDI B], now on [CRTC:47:pipe B]
>[ 5194.249310] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:61:DP-2]
>[ 5194.249331] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Disabling [CONNECTOR:61:DP-2]
>[ 5194.249354] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:37:pipe A] needs all connectors, enable: n, active: n
>[ 5194.249385] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:37:pipe A] to 000000003bd6433a
>[ 5194.249407] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:47:pipe B] needs all connectors, enable: y, active: y
>[ 5194.249430] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:47:pipe B] to 000000003bd6433a
>[ 5194.249459] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:47:pipe B] to 000000003bd6433a
>[ 5194.249552] [drm:intel_atomic_check [i915]] [CONNECTOR:56:DP-1] checking for sink bpp constrains
>[ 5194.249649] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 148500KHz
>[ 5194.249751] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 4 clock 270000 bpp 36
>[ 5194.249821] [drm:intel_dp_compute_config [i915]] DP link bw required 668250 available 1080000
>[ 5194.249900] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 36, dithering: 0
>[ 5194.249976] [drm:intel_dump_pipe_config [i915]] [CRTC:47:pipe B][modeset]
>[ 5194.250047] [drm:intel_dump_pipe_config [i915]] output_types: DP (0x80)
>[ 5194.250113] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 36, dithering: 0
>[ 5194.250182] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5190451, gmch_n: 8388608, link_m: 288358, link_n: 524288, tu: 64
>[ 5194.250244] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 5194.250306] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 5194.250342] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x9
>[ 5194.250407] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 5194.250441] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x9
>[ 5194.250509] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x9
>[ 5194.250571] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500
>[ 5194.250633] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[ 5194.250692] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 5194.250752] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 5194.250811] [drm:intel_dump_pipe_config [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[ 5194.250870] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 5194.250931] [drm:intel_dump_pipe_config [i915]] [PLANE:38:plane 1B] FB:115, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[ 5194.250992] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1200 dst 0x0+1920+1200
>[ 5194.251050] [drm:intel_dump_pipe_config [i915]] [PLANE:41:plane 2B] disabled, scaler_id = -1
>[ 5194.251111] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor B] disabled, scaler_id = -1
>[ 5194.251183] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 5194.251250] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[ 5194.251327] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:47:pipe B] has [PLANE:38:plane 1B] with fb 71
>[ 5194.251393] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:38:plane 1B] visible 1 -> 1, off 1, on 1, ms 1
>[ 5194.251469] [drm:intel_find_shared_dpll [i915]] [CRTC:47:pipe B] allocated DPLL 1
>[ 5194.251535] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[ 5194.251603] [drm:skl_compute_wm [i915]] [PLANE:34:cursor A] ddb (438 - 446) -> (0 - 0)
>[ 5194.251659] [drm:skl_compute_wm [i915]] [PLANE:38:plane 1B] ddb (446 - 884) -> (0 - 860)
>[ 5194.251714] [drm:skl_compute_wm [i915]] [PLANE:44:cursor B] ddb (884 - 892) -> (860 - 892)
>[ 5194.251750] [drm:drm_atomic_commit [drm]] committing 000000003bd6433a
>[ 5194.254543] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 5194.254557] [drm:i915_audio_component_get_eld [i915]] Not valid for port B
>[ 5194.254578] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 5194.265582] [drm:intel_power_well_disable [i915]] disabling DDI B IO power well
>[ 5194.265602] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 5194.265620] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 37
>[ 5194.265635] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[ 5194.265664] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 5194.276262] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well
>[ 5194.276288] [drm:intel_disable_shared_dpll [i915]] disable DPLL 2 (active 2, on? 1) for crtc 47
>[ 5194.276309] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 2
>[ 5194.276332] [drm:intel_atomic_commit_tail [i915]] [ENCODER:48:DDI A]
>[ 5194.276350] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI B]
>[ 5194.276367] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[ 5194.276382] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[ 5194.276397] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DDI C]
>[ 5194.276413] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST A]
>[ 5194.276428] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST B]
>[ 5194.276443] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI D]
>[ 5194.276457] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[ 5194.276472] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[ 5194.276489] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:61:DP-2]
>[ 5194.276506] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[ 5194.276523] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[ 5194.276539] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[ 5194.276555] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[ 5194.276576] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 2, on? 0) for crtc 47
>[ 5194.276593] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[ 5194.276685] [drm:intel_power_well_enable [i915]] enabling DDI B IO power well
>[ 5194.277249] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5194.278491] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5194.279739] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5194.280970] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5194.282216] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5194.283048] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[ 5194.283965] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 5194.283984] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 5194.284002] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 5194.284021] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 5194.302750] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 5194.302763] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[ 5194.320495] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 5194.320817] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:56:DP-1] Link Training Passed at Link Rate = 270000, Lane count = 4
>[ 5194.321281] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 5194.321297] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS
>[ 5194.321310] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:56:DP-1], [ENCODER:55:DDI B]
>[ 5194.321322] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[ 5194.321335] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 5194.338233] [drm:intel_atomic_commit_tail [i915]] [CRTC:37:pipe A]
>[ 5194.338259] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:56:DP-1]
>[ 5194.338275] [drm:intel_atomic_commit_tail [i915]] [CRTC:47:pipe B]
>[ 5194.338297] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[ 5194.338309] [drm:intel_enable_sagv [i915]] Enabling the SAGV
>[ 5194.338321] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000003bd6433a
>[ 5194.338328] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000003bd6433a
>[ 5194.338340] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000009cf785c6
>[ 5194.338346] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:47:pipe B] 000000002b48c403 state to 000000009cf785c6
>[ 5194.338351] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:38:plane 1B] 00000000c4e4455d state to 000000009cf785c6
>[ 5194.338355] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 00000000c4e4455d to [CRTC:47:pipe B]
>[ 5194.338359] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:71] for plane state 00000000c4e4455d
>[ 5194.338363] [drm:drm_atomic_check_only [drm]] checking 000000009cf785c6
>[ 5194.338380] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:47:pipe B] has [PLANE:38:plane 1B] with fb 71
>[ 5194.338394] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:38:plane 1B] visible 1 -> 1, off 0, on 0, ms 0
>[ 5194.338401] [drm:drm_atomic_nonblocking_commit [drm]] committing 000000009cf785c6 nonblocking
>[ 5194.354944] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000009cf785c6
>[ 5194.354952] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000009cf785c6
>[ 5195.793145] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040
>[ 5195.793227] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short
>[ 5195.793368] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short
>[ 5195.793870] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 00 02 02 06 03 00 00 00
>[ 5201.504952] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000f16dcf01
>[ 5201.504991] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:38:plane 1B] 00000000f7df0cd9 state to 00000000f16dcf01
>[ 5201.505020] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:47:pipe B] 00000000ef7e8929 state to 00000000f16dcf01
>[ 5201.505043] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for plane state 00000000f7df0cd9
>[ 5201.505064] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 00000000f7df0cd9 to [NOCRTC]
>[ 5201.505150] [drm:drm_atomic_check_only [drm]] checking 00000000f16dcf01
>[ 5201.505263] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:47:pipe B] has [PLANE:38:plane 1B] with fb -1
>[ 5201.505349] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:38:plane 1B] visible 1 -> 0, off 1, on 0, ms 0
>[ 5201.505417] [drm:skl_compute_wm [i915]] [PLANE:38:plane 1B] ddb (0 - 860) -> (0 - 0)
>[ 5201.505449] [drm:drm_atomic_commit [drm]] committing 00000000f16dcf01
>[ 5201.521420] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000f16dcf01
>[ 5201.521454] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000f16dcf01
>[ 5201.521642] [drm:drm_mode_addfb2 [drm]] [FB:71]
>[ 5201.521689] [drm:drm_mode_addfb2 [drm]] [FB:73]
>[ 5201.521719] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[ 5201.521748] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:56:DP-1]
>[ 5201.521778] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000005281b9e0
>[ 5201.521808] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:47:pipe B] 0000000008dd7b22 state to 000000005281b9e0
>[ 5201.521832] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:38:plane 1B] 00000000689b5fd3 state to 000000005281b9e0
>[ 5201.521857] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [MODE:1920x1080] for CRTC state 0000000008dd7b22
>[ 5201.521879] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 00000000689b5fd3 to [CRTC:47:pipe B]
>[ 5201.521900] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:71] for plane state 00000000689b5fd3
>[ 5201.521921] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:47:pipe B] to 000000005281b9e0
>[ 5201.521944] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:56:DP-1] 0000000017a83230 state to 000000005281b9e0
>[ 5201.521965] [drm:drm_atomic_set_crtc_for_connector [drm]] Link connector state 0000000017a83230 to [NOCRTC]
>[ 5201.521984] [drm:drm_atomic_set_crtc_for_connector [drm]] Link connector state 0000000017a83230 to [CRTC:47:pipe B]
>[ 5201.522007] [drm:drm_atomic_check_only [drm]] checking 000000005281b9e0
>[ 5201.522030] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:56:DP-1]
>[ 5201.522045] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:56:DP-1] keeps [ENCODER:55:DDI B], now on [CRTC:47:pipe B]
>[ 5201.522141] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:47:pipe B] has [PLANE:38:plane 1B] with fb 71
>[ 5201.522217] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:38:plane 1B] visible 0 -> 1, off 0, on 1, ms 0
>[ 5201.522280] [drm:skl_compute_wm [i915]] [PLANE:38:plane 1B] ddb (0 - 0) -> (0 - 860)
>[ 5201.522306] [drm:drm_atomic_commit [drm]] committing 000000005281b9e0
>[ 5201.538209] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000005281b9e0
>[ 5201.538219] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000005281b9e0
>[ 5201.538233] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000f16dcf01
>[ 5201.538240] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:47:pipe B] 00000000ef7e8929 state to 00000000f16dcf01
>[ 5201.538245] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:38:plane 1B] 00000000f7df0cd9 state to 00000000f16dcf01
>[ 5201.538249] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 00000000f7df0cd9 to [CRTC:47:pipe B]
>[ 5201.538254] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:71] for plane state 00000000f7df0cd9
>[ 5201.538258] [drm:drm_atomic_check_only [drm]] checking 00000000f16dcf01
>[ 5201.538284] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:47:pipe B] has [PLANE:38:plane 1B] with fb 71
>[ 5201.538300] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:38:plane 1B] visible 1 -> 1, off 0, on 0, ms 0
>[ 5201.538309] [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000f16dcf01 nonblocking
>[ 5201.554855] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000f16dcf01
>[ 5201.554866] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000f16dcf01
>[ 5208.569860] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000f16dcf01
>[ 5208.569901] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:38:plane 1B] 00000000c4e4455d state to 00000000f16dcf01
>[ 5208.569928] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:47:pipe B] 000000002b48c403 state to 00000000f16dcf01
>[ 5208.569951] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for plane state 00000000c4e4455d
>[ 5208.569972] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 00000000c4e4455d to [NOCRTC]
>[ 5208.569993] [drm:drm_atomic_check_only [drm]] checking 00000000f16dcf01
>[ 5208.570090] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:47:pipe B] has [PLANE:38:plane 1B] with fb -1
>[ 5208.570166] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:38:plane 1B] visible 1 -> 0, off 1, on 0, ms 0
>[ 5208.570227] [drm:skl_compute_wm [i915]] [PLANE:38:plane 1B] ddb (0 - 860) -> (0 - 0)
>[ 5208.570255] [drm:drm_atomic_commit [drm]] committing 00000000f16dcf01
>[ 5208.571542] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000f16dcf01
>[ 5208.571576] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000f16dcf01
>[ 5208.571766] [drm:drm_mode_addfb2 [drm]] [FB:71]
>[ 5208.571813] [drm:drm_mode_addfb2 [drm]] [FB:73]
>[ 5208.571844] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[ 5208.571873] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:56:DP-1]
>[ 5208.571904] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000fac241da
>[ 5208.571935] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:47:pipe B] 00000000612a648b state to 00000000fac241da
>[ 5208.571959] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:38:plane 1B] 0000000032e4809f state to 00000000fac241da
>[ 5208.571985] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [MODE:1920x1080] for CRTC state 00000000612a648b
>[ 5208.572007] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 0000000032e4809f to [CRTC:47:pipe B]
>[ 5208.572028] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:71] for plane state 0000000032e4809f
>[ 5208.572049] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:47:pipe B] to 00000000fac241da
>[ 5208.572072] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:56:DP-1] 0000000058e88fb4 state to 00000000fac241da
>[ 5208.572093] [drm:drm_atomic_set_crtc_for_connector [drm]] Link connector state 0000000058e88fb4 to [NOCRTC]
>[ 5208.572112] [drm:drm_atomic_set_crtc_for_connector [drm]] Link connector state 0000000058e88fb4 to [CRTC:47:pipe B]
>[ 5208.572135] [drm:drm_atomic_check_only [drm]] checking 00000000fac241da
>[ 5208.572157] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:56:DP-1]
>[ 5208.572171] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:56:DP-1] keeps [ENCODER:55:DDI B], now on [CRTC:47:pipe B]
>[ 5208.572267] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:47:pipe B] has [PLANE:38:plane 1B] with fb 71
>[ 5208.572344] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:38:plane 1B] visible 0 -> 1, off 0, on 1, ms 0
>[ 5208.572408] [drm:skl_compute_wm [i915]] [PLANE:38:plane 1B] ddb (0 - 0) -> (0 - 860)
>[ 5208.572434] [drm:drm_atomic_commit [drm]] committing 00000000fac241da
>[ 5208.588254] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000fac241da
>[ 5208.588264] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000fac241da
>[ 5208.588278] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000f16dcf01
>[ 5208.588285] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:47:pipe B] 000000002b48c403 state to 00000000f16dcf01
>[ 5208.588290] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:38:plane 1B] 00000000c4e4455d state to 00000000f16dcf01
>[ 5208.588295] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 00000000c4e4455d to [CRTC:47:pipe B]
>[ 5208.588300] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:71] for plane state 00000000c4e4455d
>[ 5208.588304] [drm:drm_atomic_check_only [drm]] checking 00000000f16dcf01
>[ 5208.588330] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:47:pipe B] has [PLANE:38:plane 1B] with fb 71
>[ 5208.588347] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:38:plane 1B] visible 1 -> 1, off 0, on 0, ms 0
>[ 5208.588355] [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000f16dcf01 nonblocking
>[ 5208.604908] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000f16dcf01
>[ 5208.604919] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000f16dcf01
>[ 5215.996781] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000f1dca00e
>[ 5215.996819] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:38:plane 1B] 000000003075b3b2 state to 00000000f1dca00e
>[ 5215.996848] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:47:pipe B] 00000000ef7e8929 state to 00000000f1dca00e
>[ 5215.996872] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for plane state 000000003075b3b2
>[ 5215.996892] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 000000003075b3b2 to [NOCRTC]
>[ 5215.996913] [drm:drm_atomic_check_only [drm]] checking 00000000f1dca00e
>[ 5215.997010] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:47:pipe B] has [PLANE:38:plane 1B] with fb -1
>[ 5215.997085] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:38:plane 1B] visible 1 -> 0, off 1, on 0, ms 0
>[ 5215.997217] [drm:skl_compute_wm [i915]] [PLANE:38:plane 1B] ddb (0 - 860) -> (0 - 0)
>[ 5215.997257] [drm:drm_atomic_commit [drm]] committing 00000000f1dca00e
>[ 5216.004943] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000f1dca00e
>[ 5216.004977] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000f1dca00e
>[ 5216.005197] [drm:drm_mode_addfb2 [drm]] [FB:71]
>[ 5216.005251] [drm:drm_mode_addfb2 [drm]] [FB:73]
>[ 5216.005287] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[ 5216.005321] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:56:DP-1]
>[ 5216.005357] [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000020b6dfe7
>[ 5216.005390] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:47:pipe B] 0000000052fcd53d state to 0000000020b6dfe7
>[ 5216.005419] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:38:plane 1B] 00000000478fa000 state to 0000000020b6dfe7
>[ 5216.005451] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [MODE:1920x1080] for CRTC state 0000000052fcd53d
>[ 5216.005473] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 00000000478fa000 to [CRTC:47:pipe B]
>[ 5216.005499] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:71] for plane state 00000000478fa000
>[ 5216.005527] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:47:pipe B] to 0000000020b6dfe7
>[ 5216.005552] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:56:DP-1] 000000008e78eea9 state to 0000000020b6dfe7
>[ 5216.005578] [drm:drm_atomic_set_crtc_for_connector [drm]] Link connector state 000000008e78eea9 to [NOCRTC]
>[ 5216.005600] [drm:drm_atomic_set_crtc_for_connector [drm]] Link connector state 000000008e78eea9 to [CRTC:47:pipe B]
>[ 5216.005629] [drm:drm_atomic_check_only [drm]] checking 0000000020b6dfe7
>[ 5216.005654] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:56:DP-1]
>[ 5216.005672] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:56:DP-1] keeps [ENCODER:55:DDI B], now on [CRTC:47:pipe B]
>[ 5216.005774] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:47:pipe B] has [PLANE:38:plane 1B] with fb 71
>[ 5216.005854] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:38:plane 1B] visible 0 -> 1, off 0, on 1, ms 0
>[ 5216.005926] [drm:skl_compute_wm [i915]] [PLANE:38:plane 1B] ddb (0 - 0) -> (0 - 860)
>[ 5216.005955] [drm:drm_atomic_commit [drm]] committing 0000000020b6dfe7
>[ 5216.021380] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000020b6dfe7
>[ 5216.021389] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000020b6dfe7
>[ 5216.021402] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000f1dca00e
>[ 5216.021409] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:47:pipe B] 00000000ef7e8929 state to 00000000f1dca00e
>[ 5216.021415] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:38:plane 1B] 000000003075b3b2 state to 00000000f1dca00e
>[ 5216.021419] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 000000003075b3b2 to [CRTC:47:pipe B]
>[ 5216.021424] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:71] for plane state 000000003075b3b2
>[ 5216.021429] [drm:drm_atomic_check_only [drm]] checking 00000000f1dca00e
>[ 5216.021455] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:47:pipe B] has [PLANE:38:plane 1B] with fb 71
>[ 5216.021471] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:38:plane 1B] visible 1 -> 1, off 0, on 0, ms 0
>[ 5216.021480] [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000f1dca00e nonblocking
>[ 5216.038156] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000f1dca00e
>[ 5216.038167] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000f1dca00e
>[ 5223.053890] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000f1dca00e
>[ 5223.053930] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:38:plane 1B] 00000000c4e4455d state to 00000000f1dca00e
>[ 5223.053958] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:47:pipe B] 000000002b48c403 state to 00000000f1dca00e
>[ 5223.053980] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for plane state 00000000c4e4455d
>[ 5223.054001] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 00000000c4e4455d to [NOCRTC]
>[ 5223.054023] [drm:drm_atomic_check_only [drm]] checking 00000000f1dca00e
>[ 5223.054118] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:47:pipe B] has [PLANE:38:plane 1B] with fb -1
>[ 5223.054193] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:38:plane 1B] visible 1 -> 0, off 1, on 0, ms 0
>[ 5223.054254] [drm:skl_compute_wm [i915]] [PLANE:38:plane 1B] ddb (0 - 860) -> (0 - 0)
>[ 5223.054283] [drm:drm_atomic_commit [drm]] committing 00000000f1dca00e
>[ 5223.054870] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000f1dca00e
>[ 5223.054903] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000f1dca00e
>[ 5223.055138] [drm:drm_mode_addfb2 [drm]] [FB:71]
>[ 5223.055183] [drm:drm_mode_addfb2 [drm]] [FB:73]
>[ 5223.055213] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[ 5223.055242] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:61:DP-2]
>[ 5223.055272] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000797fb672
>[ 5223.055302] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:37:pipe A] 0000000008dd7b22 state to 00000000797fb672
>[ 5223.055326] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 0000000019ad87fe state to 00000000797fb672
>[ 5223.055352] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [MODE:1920x1200] for CRTC state 0000000008dd7b22
>[ 5223.055373] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 0000000019ad87fe to [CRTC:37:pipe A]
>[ 5223.055394] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:71] for plane state 0000000019ad87fe
>[ 5223.055415] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:37:pipe A] to 00000000797fb672
>[ 5223.055438] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:61:DP-2] 0000000025c1c53f state to 00000000797fb672
>[ 5223.055457] [drm:drm_atomic_set_crtc_for_connector [drm]] Link connector state 0000000025c1c53f to [CRTC:37:pipe A]
>[ 5223.055479] [drm:drm_atomic_check_only [drm]] checking 00000000797fb672
>[ 5223.055499] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:37:pipe A] mode changed
>[ 5223.055511] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:37:pipe A] enable changed
>[ 5223.055522] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:37:pipe A] active changed
>[ 5223.055534] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:61:DP-2]
>[ 5223.055546] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:61:DP-2] using [ENCODER:60:DDI C] on [CRTC:37:pipe A]
>[ 5223.055558] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:37:pipe A] needs all connectors, enable: y, active: y
>[ 5223.055579] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:37:pipe A] to 00000000797fb672
>[ 5223.055602] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:37:pipe A] to 00000000797fb672
>[ 5223.055693] [drm:intel_atomic_check [i915]] [CONNECTOR:61:DP-2] checking for sink bpp constrains
>[ 5223.055768] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 5223.055844] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 5223.055932] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 5223.055996] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 5223.056066] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 5223.056135] [drm:intel_dump_pipe_config [i915]] [CRTC:37:pipe A][modeset]
>[ 5223.056200] [drm:intel_dump_pipe_config [i915]] output_types: DP (0x80)
>[ 5223.056262] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 5223.056323] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 5223.056380] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[ 5223.056435] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 5223.056468] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[ 5223.056527] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 5223.056556] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[ 5223.056618] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[ 5223.056676] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 5223.056731] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[ 5223.056786] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 5223.056840] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 5223.056895] [drm:intel_dump_pipe_config [i915]] dpll_hw_state: ctrl1: 0x3, cfgcr1: 0x0, cfgcr2: 0x0
>[ 5223.056948] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 5223.057002] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 1A] disabled, scaler_id = -1
>[ 5223.057056] [drm:intel_dump_pipe_config [i915]] [PLANE:31:plane 2A] disabled, scaler_id = -1
>[ 5223.057111] [drm:intel_dump_pipe_config [i915]] [PLANE:34:cursor A] disabled, scaler_id = -1
>[ 5223.057222] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 5223.057299] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[ 5223.057382] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:37:pipe A] has [PLANE:28:plane 1A] with fb 71
>[ 5223.057455] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 0 -> 1, off 0, on 1, ms 1
>[ 5223.057534] [drm:intel_find_shared_dpll [i915]] [CRTC:37:pipe A] allocated DPLL 2
>[ 5223.057606] [drm:intel_reference_shared_dpll [i915]] using DPLL 2 for pipe A
>[ 5223.057657] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:47:pipe B] 0000000018046d93 state to 00000000797fb672
>[ 5223.057727] [drm:skl_compute_wm [i915]] [PLANE:28:plane 1A] ddb (0 - 0) -> (0 - 438)
>[ 5223.057789] [drm:skl_compute_wm [i915]] [PLANE:34:cursor A] ddb (0 - 0) -> (438 - 446)
>[ 5223.057849] [drm:skl_compute_wm [i915]] [PLANE:44:cursor B] ddb (860 - 892) -> (884 - 892)
>[ 5223.057889] [drm:drm_atomic_commit [drm]] committing 00000000797fb672
>[ 5223.060660] [drm:intel_disable_sagv [i915]] Disabling the SAGV
>[ 5223.060676] [drm:intel_atomic_commit_tail [i915]] [ENCODER:48:DDI A]
>[ 5223.060688] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI B]
>[ 5223.060700] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[ 5223.060711] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[ 5223.060721] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DDI C]
>[ 5223.060732] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST A]
>[ 5223.060743] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST B]
>[ 5223.060753] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI D]
>[ 5223.060764] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[ 5223.060774] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[ 5223.060785] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[ 5223.060798] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[ 5223.060809] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[ 5223.060820] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[ 5223.071611] [drm:intel_enable_shared_dpll [i915]] enable DPLL 2 (active 1, on? 0) for crtc 37
>[ 5223.071628] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 2
>[ 5223.071717] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well
>[ 5223.072745] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 5223.072758] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 5223.072771] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 5223.072784] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 5223.073361] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 04000000
>[ 5223.073373] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[ 5223.073385] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 5223.073951] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 5223.073963] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 5223.074836] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 5223.075158] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:61:DP-2] Link Training Passed at Link Rate = 162000, Lane count = 4
>[ 5223.075530] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 5223.075548] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS
>[ 5223.075565] [drm:intel_fbc_enable [i915]] reserved 4608000 bytes of contiguous stolen space for FBC, threshold: 1
>[ 5223.075579] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 5223.092488] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:61:DP-2]
>[ 5223.092516] [drm:intel_atomic_commit_tail [i915]] [CRTC:37:pipe A]
>[ 5223.092551] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[ 5223.092569] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000797fb672
>[ 5223.092580] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000797fb672
>[ 5223.092599] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000f1dca00e
>[ 5223.092608] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:37:pipe A] 000000002b48c403 state to 00000000f1dca00e
>[ 5223.092616] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000436a997d state to 00000000f1dca00e
>[ 5223.092623] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 00000000436a997d to [CRTC:37:pipe A]
>[ 5223.092630] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:71] for plane state 00000000436a997d
>[ 5223.092637] [drm:drm_atomic_check_only [drm]] checking 00000000f1dca00e
>[ 5223.092665] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:37:pipe A] has [PLANE:28:plane 1A] with fb 71
>[ 5223.092688] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>[ 5223.092701] [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000f1dca00e nonblocking
>[ 5223.109188] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000f1dca00e
>[ 5223.109206] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000f1dca00e
>[ 5230.275928] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000005c12011a
>[ 5230.275968] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 000000000c3ecdec state to 000000005c12011a
>[ 5230.275996] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:37:pipe A] 00000000ef7e8929 state to 000000005c12011a
>[ 5230.276020] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for plane state 000000000c3ecdec
>[ 5230.276041] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 000000000c3ecdec to [NOCRTC]
>[ 5230.276063] [drm:drm_atomic_check_only [drm]] checking 000000005c12011a
>[ 5230.276160] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:37:pipe A] has [PLANE:28:plane 1A] with fb -1
>[ 5230.276234] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 0, off 1, on 0, ms 0
>[ 5230.276297] [drm:skl_compute_wm [i915]] [PLANE:28:plane 1A] ddb (0 - 438) -> (0 - 0)
>[ 5230.276324] [drm:drm_atomic_commit [drm]] committing 000000005c12011a
>[ 5230.281756] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000005c12011a
>[ 5230.281790] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000005c12011a
>[ 5230.281979] [drm:drm_mode_addfb2 [drm]] [FB:71]
>[ 5230.282025] [drm:drm_mode_addfb2 [drm]] [FB:73]
>[ 5230.282055] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[ 5230.282084] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:61:DP-2]
>[ 5230.282115] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000008fe4fc91
>[ 5230.282147] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:37:pipe A] 00000000fd63c90d state to 000000008fe4fc91
>[ 5230.282172] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000d98108c3 state to 000000008fe4fc91
>[ 5230.282198] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [MODE:1920x1200] for CRTC state 00000000fd63c90d
>[ 5230.282220] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 00000000d98108c3 to [CRTC:37:pipe A]
>[ 5230.282241] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:71] for plane state 00000000d98108c3
>[ 5230.282262] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:37:pipe A] to 000000008fe4fc91
>[ 5230.282285] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:61:DP-2] 000000000c9ce06d state to 000000008fe4fc91
>[ 5230.282306] [drm:drm_atomic_set_crtc_for_connector [drm]] Link connector state 000000000c9ce06d to [NOCRTC]
>[ 5230.282325] [drm:drm_atomic_set_crtc_for_connector [drm]] Link connector state 000000000c9ce06d to [CRTC:37:pipe A]
>[ 5230.282348] [drm:drm_atomic_check_only [drm]] checking 000000008fe4fc91
>[ 5230.282370] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:61:DP-2]
>[ 5230.282384] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:61:DP-2] keeps [ENCODER:60:DDI C], now on [CRTC:37:pipe A]
>[ 5230.282481] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:37:pipe A] has [PLANE:28:plane 1A] with fb 71
>[ 5230.282557] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 0 -> 1, off 0, on 1, ms 0
>[ 5230.282623] [drm:skl_compute_wm [i915]] [PLANE:28:plane 1A] ddb (0 - 0) -> (0 - 438)
>[ 5230.282650] [drm:drm_atomic_commit [drm]] committing 000000008fe4fc91
>[ 5230.298483] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000008fe4fc91
>[ 5230.298493] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000008fe4fc91
>[ 5230.298506] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000005c12011a
>[ 5230.298513] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:37:pipe A] 00000000ef7e8929 state to 000000005c12011a
>[ 5230.298519] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 000000000c3ecdec state to 000000005c12011a
>[ 5230.298523] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 000000000c3ecdec to [CRTC:37:pipe A]
>[ 5230.298528] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:71] for plane state 000000000c3ecdec
>[ 5230.298532] [drm:drm_atomic_check_only [drm]] checking 000000005c12011a
>[ 5230.298558] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:37:pipe A] has [PLANE:28:plane 1A] with fb 71
>[ 5230.298575] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>[ 5230.298583] [drm:drm_atomic_nonblocking_commit [drm]] committing 000000005c12011a nonblocking
>[ 5230.315147] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000005c12011a
>[ 5230.315158] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000005c12011a
>[ 5237.332858] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000005c12011a
>[ 5237.332897] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000436a997d state to 000000005c12011a
>[ 5237.332925] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:37:pipe A] 000000002b48c403 state to 000000005c12011a
>[ 5237.332948] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for plane state 00000000436a997d
>[ 5237.332969] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 00000000436a997d to [NOCRTC]
>[ 5237.332991] [drm:drm_atomic_check_only [drm]] checking 000000005c12011a
>[ 5237.333087] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:37:pipe A] has [PLANE:28:plane 1A] with fb -1
>[ 5237.333228] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 0, off 1, on 0, ms 0
>[ 5237.333312] [drm:skl_compute_wm [i915]] [PLANE:28:plane 1A] ddb (0 - 438) -> (0 - 0)
>[ 5237.333353] [drm:drm_atomic_commit [drm]] committing 000000005c12011a
>[ 5237.337543] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000005c12011a
>[ 5237.337575] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000005c12011a
>[ 5237.337759] [drm:drm_mode_addfb2 [drm]] [FB:71]
>[ 5237.337805] [drm:drm_mode_addfb2 [drm]] [FB:73]
>[ 5237.337835] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[ 5237.337864] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:61:DP-2]
>[ 5237.337895] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000009d28d480
>[ 5237.337925] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:37:pipe A] 000000007b1f6733 state to 000000009d28d480
>[ 5237.337949] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000d54c0854 state to 000000009d28d480
>[ 5237.337973] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [MODE:1920x1200] for CRTC state 000000007b1f6733
>[ 5237.337994] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 00000000d54c0854 to [CRTC:37:pipe A]
>[ 5237.338015] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:71] for plane state 00000000d54c0854
>[ 5237.338036] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:37:pipe A] to 000000009d28d480
>[ 5237.338060] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:61:DP-2] 00000000d388f03f state to 000000009d28d480
>[ 5237.338080] [drm:drm_atomic_set_crtc_for_connector [drm]] Link connector state 00000000d388f03f to [NOCRTC]
>[ 5237.338099] [drm:drm_atomic_set_crtc_for_connector [drm]] Link connector state 00000000d388f03f to [CRTC:37:pipe A]
>[ 5237.338122] [drm:drm_atomic_check_only [drm]] checking 000000009d28d480
>[ 5237.338145] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:61:DP-2]
>[ 5237.338158] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:61:DP-2] keeps [ENCODER:60:DDI C], now on [CRTC:37:pipe A]
>[ 5237.338253] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:37:pipe A] has [PLANE:28:plane 1A] with fb 71
>[ 5237.338329] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 0 -> 1, off 0, on 1, ms 0
>[ 5237.338394] [drm:skl_compute_wm [i915]] [PLANE:28:plane 1A] ddb (0 - 0) -> (0 - 438)
>[ 5237.338419] [drm:drm_atomic_commit [drm]] committing 000000009d28d480
>[ 5237.354352] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000009d28d480
>[ 5237.354362] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000009d28d480
>[ 5237.354376] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000005c12011a
>[ 5237.354383] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:37:pipe A] 000000002b48c403 state to 000000005c12011a
>[ 5237.354388] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000436a997d state to 000000005c12011a
>[ 5237.354393] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 00000000436a997d to [CRTC:37:pipe A]
>[ 5237.354398] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:71] for plane state 00000000436a997d
>[ 5237.354402] [drm:drm_atomic_check_only [drm]] checking 000000005c12011a
>[ 5237.354428] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:37:pipe A] has [PLANE:28:plane 1A] with fb 71
>[ 5237.354445] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>[ 5237.354454] [drm:drm_atomic_nonblocking_commit [drm]] committing 000000005c12011a nonblocking
>[ 5237.371026] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000005c12011a
>[ 5237.371038] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000005c12011a
>[ 5244.806188] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000005c12011a
>[ 5244.806227] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 000000000c3ecdec state to 000000005c12011a
>[ 5244.806255] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:37:pipe A] 00000000ef7e8929 state to 000000005c12011a
>[ 5244.806278] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for plane state 000000000c3ecdec
>[ 5244.806298] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 000000000c3ecdec to [NOCRTC]
>[ 5244.806320] [drm:drm_atomic_check_only [drm]] checking 000000005c12011a
>[ 5244.806416] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:37:pipe A] has [PLANE:28:plane 1A] with fb -1
>[ 5244.806492] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 0, off 1, on 0, ms 0
>[ 5244.806552] [drm:skl_compute_wm [i915]] [PLANE:28:plane 1A] ddb (0 - 438) -> (0 - 0)
>[ 5244.806580] [drm:drm_atomic_commit [drm]] committing 000000005c12011a
>[ 5244.810543] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000005c12011a
>[ 5244.810578] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000005c12011a
>[ 5244.810767] [drm:drm_mode_addfb2 [drm]] [FB:71]
>[ 5244.810814] [drm:drm_mode_addfb2 [drm]] [FB:73]
>[ 5244.810844] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[ 5244.810874] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:61:DP-2]
>[ 5244.810905] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000cad0d81d
>[ 5244.810935] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:37:pipe A] 0000000024d204e2 state to 00000000cad0d81d
>[ 5244.810959] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 0000000057f8b943 state to 00000000cad0d81d
>[ 5244.810984] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [MODE:1920x1200] for CRTC state 0000000024d204e2
>[ 5244.811005] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 0000000057f8b943 to [CRTC:37:pipe A]
>[ 5244.811026] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:71] for plane state 0000000057f8b943
>[ 5244.811048] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:37:pipe A] to 00000000cad0d81d
>[ 5244.811072] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:61:DP-2] 000000008369248d state to 00000000cad0d81d
>[ 5244.811093] [drm:drm_atomic_set_crtc_for_connector [drm]] Link connector state 000000008369248d to [NOCRTC]
>[ 5244.811112] [drm:drm_atomic_set_crtc_for_connector [drm]] Link connector state 000000008369248d to [CRTC:37:pipe A]
>[ 5244.811136] [drm:drm_atomic_check_only [drm]] checking 00000000cad0d81d
>[ 5244.811158] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:61:DP-2]
>[ 5244.811172] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:61:DP-2] keeps [ENCODER:60:DDI C], now on [CRTC:37:pipe A]
>[ 5244.811269] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:37:pipe A] has [PLANE:28:plane 1A] with fb 71
>[ 5244.811345] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 0 -> 1, off 0, on 1, ms 0
>[ 5244.811411] [drm:skl_compute_wm [i915]] [PLANE:28:plane 1A] ddb (0 - 0) -> (0 - 438)
>[ 5244.811437] [drm:drm_atomic_commit [drm]] committing 00000000cad0d81d
>[ 5244.827267] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000cad0d81d
>[ 5244.827276] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000cad0d81d
>[ 5244.827290] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000005c12011a
>[ 5244.827297] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:37:pipe A] 00000000ef7e8929 state to 000000005c12011a
>[ 5244.827303] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 000000000c3ecdec state to 000000005c12011a
>[ 5244.827307] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 000000000c3ecdec to [CRTC:37:pipe A]
>[ 5244.827312] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:71] for plane state 000000000c3ecdec
>[ 5244.827316] [drm:drm_atomic_check_only [drm]] checking 000000005c12011a
>[ 5244.827342] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:37:pipe A] has [PLANE:28:plane 1A] with fb 71
>[ 5244.827358] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>[ 5244.827367] [drm:drm_atomic_nonblocking_commit [drm]] committing 000000005c12011a nonblocking
>[ 5244.843932] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000005c12011a
>[ 5244.843942] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000005c12011a
>[ 5251.861703] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000005c12011a
>[ 5251.861742] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000436a997d state to 000000005c12011a
>[ 5251.861771] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:37:pipe A] 000000002b48c403 state to 000000005c12011a
>[ 5251.861794] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for plane state 00000000436a997d
>[ 5251.861815] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 00000000436a997d to [NOCRTC]
>[ 5251.861838] [drm:drm_atomic_check_only [drm]] checking 000000005c12011a
>[ 5251.861934] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:37:pipe A] has [PLANE:28:plane 1A] with fb -1
>[ 5251.862009] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 0, off 1, on 0, ms 0
>[ 5251.862070] [drm:skl_compute_wm [i915]] [PLANE:28:plane 1A] ddb (0 - 438) -> (0 - 0)
>[ 5251.862098] [drm:drm_atomic_commit [drm]] committing 000000005c12011a
>[ 5251.866405] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000005c12011a
>[ 5251.866438] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000005c12011a
>[ 5251.866670] [drm:drm_mode_addfb2 [drm]] [FB:71]
>[ 5251.866716] [drm:drm_mode_addfb2 [drm]] [FB:73]
>[ 5251.866745] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[ 5251.866775] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:61:DP-2]
>[ 5251.866806] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000008fe4fc91
>[ 5251.866835] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:47:pipe B] 00000000e1fcf8a7 state to 000000008fe4fc91
>[ 5251.866860] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:38:plane 1B] 0000000086f11a73 state to 000000008fe4fc91
>[ 5251.866885] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [MODE:1920x1200] for CRTC state 00000000e1fcf8a7
>[ 5251.866906] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 0000000086f11a73 to [CRTC:47:pipe B]
>[ 5251.866927] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:71] for plane state 0000000086f11a73
>[ 5251.866948] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:47:pipe B] to 000000008fe4fc91
>[ 5251.866971] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:56:DP-1] 00000000b02a1863 state to 000000008fe4fc91
>[ 5251.866991] [drm:drm_atomic_set_crtc_for_connector [drm]] Link connector state 00000000b02a1863 to [NOCRTC]
>[ 5251.867010] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:61:DP-2] 00000000bcdfc2e8 state to 000000008fe4fc91
>[ 5251.867031] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:37:pipe A] 000000006794fe06 state to 000000008fe4fc91
>[ 5251.867050] [drm:drm_atomic_set_crtc_for_connector [drm]] Link connector state 00000000bcdfc2e8 to [CRTC:47:pipe B]
>[ 5251.867070] [drm:drm_atomic_set_mode_prop_for_crtc [drm]] Set [NOMODE] for CRTC state 000000006794fe06
>[ 5251.867092] [drm:drm_atomic_check_only [drm]] checking 000000008fe4fc91
>[ 5251.867113] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:37:pipe A] mode changed
>[ 5251.867125] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:37:pipe A] enable changed
>[ 5251.867136] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:37:pipe A] active changed
>[ 5251.867147] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:47:pipe B] mode changed
>[ 5251.867160] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:56:DP-1]
>[ 5251.867170] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Disabling [CONNECTOR:56:DP-1]
>[ 5251.867181] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:61:DP-2]
>[ 5251.867193] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:61:DP-2] keeps [ENCODER:60:DDI C], now on [CRTC:47:pipe B]
>[ 5251.867204] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:37:pipe A] needs all connectors, enable: n, active: n
>[ 5251.867226] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:37:pipe A] to 000000008fe4fc91
>[ 5251.867240] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:47:pipe B] needs all connectors, enable: y, active: y
>[ 5251.867260] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:47:pipe B] to 000000008fe4fc91
>[ 5251.867283] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:47:pipe B] to 000000008fe4fc91
>[ 5251.867375] [drm:intel_atomic_check [i915]] [CONNECTOR:61:DP-2] checking for sink bpp constrains
>[ 5251.867450] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 5251.867527] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 5251.867615] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 5251.867681] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 5251.867753] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 5251.867822] [drm:intel_dump_pipe_config [i915]] [CRTC:47:pipe B][modeset]
>[ 5251.867887] [drm:intel_dump_pipe_config [i915]] output_types: DP (0x80)
>[ 5251.867948] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 5251.868009] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 5251.868067] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[ 5251.868123] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 5251.868155] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[ 5251.868214] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 5251.868244] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[ 5251.868306] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[ 5251.868364] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 5251.868419] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[ 5251.868474] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 5251.868529] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 5251.868584] [drm:intel_dump_pipe_config [i915]] dpll_hw_state: ctrl1: 0x3, cfgcr1: 0x0, cfgcr2: 0x0
>[ 5251.868637] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 5251.868691] [drm:intel_dump_pipe_config [i915]] [PLANE:38:plane 1B] disabled, scaler_id = -1
>[ 5251.868745] [drm:intel_dump_pipe_config [i915]] [PLANE:41:plane 2B] disabled, scaler_id = -1
>[ 5251.868798] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor B] disabled, scaler_id = -1
>[ 5251.868867] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 5251.868929] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[ 5251.868998] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:47:pipe B] has [PLANE:38:plane 1B] with fb 71
>[ 5251.869059] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:38:plane 1B] visible 0 -> 1, off 0, on 1, ms 1
>[ 5251.869189] [drm:intel_find_shared_dpll [i915]] [CRTC:47:pipe B] allocated DPLL 1
>[ 5251.869267] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[ 5251.869346] [drm:skl_compute_wm [i915]] [PLANE:34:cursor A] ddb (438 - 446) -> (0 - 0)
>[ 5251.869408] [drm:skl_compute_wm [i915]] [PLANE:38:plane 1B] ddb (0 - 0) -> (0 - 860)
>[ 5251.869471] [drm:skl_compute_wm [i915]] [PLANE:44:cursor B] ddb (884 - 892) -> (860 - 892)
>[ 5251.869511] [drm:drm_atomic_commit [drm]] committing 000000008fe4fc91
>[ 5251.872579] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 5251.883925] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well
>[ 5251.883943] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 5251.883959] [drm:intel_disable_shared_dpll [i915]] disable DPLL 2 (active 1, on? 1) for crtc 37
>[ 5251.883973] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 2
>[ 5251.883997] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[ 5251.884012] [drm:i915_audio_component_get_eld [i915]] Not valid for port B
>[ 5251.884035] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 5251.889241] [drm:intel_power_well_disable [i915]] disabling DDI B IO power well
>[ 5251.889258] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 2, on? 1) for crtc 47
>[ 5251.889273] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[ 5251.889290] [drm:intel_atomic_commit_tail [i915]] [ENCODER:48:DDI A]
>[ 5251.889304] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI B]
>[ 5251.889319] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[ 5251.889332] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[ 5251.889344] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DDI C]
>[ 5251.889357] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST A]
>[ 5251.889369] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST B]
>[ 5251.889381] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI D]
>[ 5251.889393] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[ 5251.889405] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[ 5251.889419] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:56:DP-1]
>[ 5251.889433] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[ 5251.889446] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[ 5251.889460] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[ 5251.889473] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[ 5251.889489] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 2, on? 0) for crtc 47
>[ 5251.889503] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[ 5251.889592] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well
>[ 5251.890627] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 5251.890643] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 5251.890657] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 5251.890672] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 5251.891251] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 5251.891265] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 5251.892141] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 5251.892467] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:61:DP-2] Link Training Passed at Link Rate = 162000, Lane count = 4
>[ 5251.892839] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 5251.892858] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS
>[ 5251.909742] [drm:intel_atomic_commit_tail [i915]] [CRTC:37:pipe A]
>[ 5251.909786] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:61:DP-2]
>[ 5251.909815] [drm:intel_atomic_commit_tail [i915]] [CRTC:47:pipe B]
>[ 5251.909852] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[ 5251.909875] [drm:intel_enable_sagv [i915]] Enabling the SAGV
>[ 5251.909893] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000008fe4fc91
>[ 5251.909906] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000008fe4fc91
>[ 5251.909926] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000005c12011a
>[ 5251.909937] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:47:pipe B] 000000002b48c403 state to 000000005c12011a
>[ 5251.909946] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:38:plane 1B] 00000000c4e4455d state to 000000005c12011a
>[ 5251.909954] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 00000000c4e4455d to [CRTC:47:pipe B]
>[ 5251.909962] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:71] for plane state 00000000c4e4455d
>[ 5251.909970] [drm:drm_atomic_check_only [drm]] checking 000000005c12011a
>[ 5251.910001] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:47:pipe B] has [PLANE:38:plane 1B] with fb 71
>[ 5251.910027] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:38:plane 1B] visible 1 -> 1, off 0, on 0, ms 0
>[ 5251.910041] [drm:drm_atomic_nonblocking_commit [drm]] committing 000000005c12011a nonblocking
>[ 5251.926456] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000005c12011a
>[ 5251.926485] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000005c12011a
>[ 5259.093305] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000005c12011a
>[ 5259.093345] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:38:plane 1B] 000000000c3ecdec state to 000000005c12011a
>[ 5259.093372] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:47:pipe B] 00000000ef7e8929 state to 000000005c12011a
>[ 5259.093395] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for plane state 000000000c3ecdec
>[ 5259.093417] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 000000000c3ecdec to [NOCRTC]
>[ 5259.093438] [drm:drm_atomic_check_only [drm]] checking 000000005c12011a
>[ 5259.093535] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:47:pipe B] has [PLANE:38:plane 1B] with fb -1
>[ 5259.093610] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:38:plane 1B] visible 1 -> 0, off 1, on 0, ms 0
>[ 5259.093671] [drm:skl_compute_wm [i915]] [PLANE:38:plane 1B] ddb (0 - 860) -> (0 - 0)
>[ 5259.093698] [drm:drm_atomic_commit [drm]] committing 000000005c12011a
>[ 5259.099096] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000005c12011a
>[ 5259.099130] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000005c12011a
>[ 5259.099317] [drm:drm_mode_addfb2 [drm]] [FB:71]
>[ 5259.099364] [drm:drm_mode_addfb2 [drm]] [FB:73]
>[ 5259.099395] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[ 5259.099424] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:61:DP-2]
>[ 5259.099455] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000009d28d480
>[ 5259.099485] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:47:pipe B] 00000000fae58dee state to 000000009d28d480
>[ 5259.099510] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:38:plane 1B] 000000009f45c02e state to 000000009d28d480
>[ 5259.099536] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [MODE:1920x1200] for CRTC state 00000000fae58dee
>[ 5259.099559] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 000000009f45c02e to [CRTC:47:pipe B]
>[ 5259.099581] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:71] for plane state 000000009f45c02e
>[ 5259.099602] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:47:pipe B] to 000000009d28d480
>[ 5259.099626] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:61:DP-2] 000000004f9e92d7 state to 000000009d28d480
>[ 5259.099647] [drm:drm_atomic_set_crtc_for_connector [drm]] Link connector state 000000004f9e92d7 to [NOCRTC]
>[ 5259.099666] [drm:drm_atomic_set_crtc_for_connector [drm]] Link connector state 000000004f9e92d7 to [CRTC:47:pipe B]
>[ 5259.099689] [drm:drm_atomic_check_only [drm]] checking 000000009d28d480
>[ 5259.099711] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:61:DP-2]
>[ 5259.099725] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:61:DP-2] keeps [ENCODER:60:DDI C], now on [CRTC:47:pipe B]
>[ 5259.099822] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:47:pipe B] has [PLANE:38:plane 1B] with fb 71
>[ 5259.099898] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:38:plane 1B] visible 0 -> 1, off 0, on 1, ms 0
>[ 5259.099962] [drm:skl_compute_wm [i915]] [PLANE:38:plane 1B] ddb (0 - 0) -> (0 - 860)
>[ 5259.099989] [drm:drm_atomic_commit [drm]] committing 000000009d28d480
>[ 5259.115804] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000009d28d480
>[ 5259.115815] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000009d28d480
>[ 5259.115830] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000005c12011a
>[ 5259.115837] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:47:pipe B] 00000000ef7e8929 state to 000000005c12011a
>[ 5259.115843] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:38:plane 1B] 000000000c3ecdec state to 000000005c12011a
>[ 5259.115848] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 000000000c3ecdec to [CRTC:47:pipe B]
>[ 5259.115853] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:71] for plane state 000000000c3ecdec
>[ 5259.115858] [drm:drm_atomic_check_only [drm]] checking 000000005c12011a
>[ 5259.115885] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:47:pipe B] has [PLANE:38:plane 1B] with fb 71
>[ 5259.115903] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:38:plane 1B] visible 1 -> 1, off 0, on 0, ms 0
>[ 5259.115913] [drm:drm_atomic_nonblocking_commit [drm]] committing 000000005c12011a nonblocking
>[ 5259.132478] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000005c12011a
>[ 5259.132489] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000005c12011a
>[ 5266.150058] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000005c12011a
>[ 5266.150098] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:38:plane 1B] 00000000c4e4455d state to 000000005c12011a
>[ 5266.150125] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:47:pipe B] 000000002b48c403 state to 000000005c12011a
>[ 5266.150148] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for plane state 00000000c4e4455d
>[ 5266.150168] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 00000000c4e4455d to [NOCRTC]
>[ 5266.150190] [drm:drm_atomic_check_only [drm]] checking 000000005c12011a
>[ 5266.150287] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:47:pipe B] has [PLANE:38:plane 1B] with fb -1
>[ 5266.150362] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:38:plane 1B] visible 1 -> 0, off 1, on 0, ms 0
>[ 5266.150423] [drm:skl_compute_wm [i915]] [PLANE:38:plane 1B] ddb (0 - 860) -> (0 - 0)
>[ 5266.150450] [drm:drm_atomic_commit [drm]] committing 000000005c12011a
>[ 5266.154846] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000005c12011a
>[ 5266.154878] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000005c12011a
>[ 5266.155057] [drm:drm_mode_addfb2 [drm]] [FB:71]
>[ 5266.155104] [drm:drm_mode_addfb2 [drm]] [FB:73]
>[ 5266.155134] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[ 5266.155163] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:61:DP-2]
>[ 5266.155193] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000001c79d1f4
>[ 5266.155223] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:47:pipe B] 00000000d9d9b155 state to 000000001c79d1f4
>[ 5266.155247] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:38:plane 1B] 0000000086f11a73 state to 000000001c79d1f4
>[ 5266.155273] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [MODE:1920x1200] for CRTC state 00000000d9d9b155
>[ 5266.155294] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 0000000086f11a73 to [CRTC:47:pipe B]
>[ 5266.155315] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:71] for plane state 0000000086f11a73
>[ 5266.155336] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:47:pipe B] to 000000001c79d1f4
>[ 5266.155360] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:61:DP-2] 00000000ae6ecbe2 state to 000000001c79d1f4
>[ 5266.155381] [drm:drm_atomic_set_crtc_for_connector [drm]] Link connector state 00000000ae6ecbe2 to [NOCRTC]
>[ 5266.155400] [drm:drm_atomic_set_crtc_for_connector [drm]] Link connector state 00000000ae6ecbe2 to [CRTC:47:pipe B]
>[ 5266.155423] [drm:drm_atomic_check_only [drm]] checking 000000001c79d1f4
>[ 5266.155446] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:61:DP-2]
>[ 5266.155460] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:61:DP-2] keeps [ENCODER:60:DDI C], now on [CRTC:47:pipe B]
>[ 5266.155556] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:47:pipe B] has [PLANE:38:plane 1B] with fb 71
>[ 5266.155634] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:38:plane 1B] visible 0 -> 1, off 0, on 1, ms 0
>[ 5266.155702] [drm:skl_compute_wm [i915]] [PLANE:38:plane 1B] ddb (0 - 0) -> (0 - 860)
>[ 5266.155728] [drm:drm_atomic_commit [drm]] committing 000000001c79d1f4
>[ 5266.171689] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000001c79d1f4
>[ 5266.171699] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000001c79d1f4
>[ 5266.171712] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000005c12011a
>[ 5266.171719] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:47:pipe B] 000000002b48c403 state to 000000005c12011a
>[ 5266.171725] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:38:plane 1B] 00000000c4e4455d state to 000000005c12011a
>[ 5266.171729] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 00000000c4e4455d to [CRTC:47:pipe B]
>[ 5266.171734] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:71] for plane state 00000000c4e4455d
>[ 5266.171738] [drm:drm_atomic_check_only [drm]] checking 000000005c12011a
>[ 5266.171764] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:47:pipe B] has [PLANE:38:plane 1B] with fb 71
>[ 5266.171781] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:38:plane 1B] visible 1 -> 1, off 0, on 0, ms 0
>[ 5266.171790] [drm:drm_atomic_nonblocking_commit [drm]] committing 000000005c12011a nonblocking
>[ 5266.188353] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000005c12011a
>[ 5266.188364] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000005c12011a
>[ 5273.623946] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000005c12011a
>[ 5273.623986] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:38:plane 1B] 000000000c3ecdec state to 000000005c12011a
>[ 5273.624014] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:47:pipe B] 00000000ef7e8929 state to 000000005c12011a
>[ 5273.624037] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for plane state 000000000c3ecdec
>[ 5273.624058] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 000000000c3ecdec to [NOCRTC]
>[ 5273.624079] [drm:drm_atomic_check_only [drm]] checking 000000005c12011a
>[ 5273.624175] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:47:pipe B] has [PLANE:38:plane 1B] with fb -1
>[ 5273.624250] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:38:plane 1B] visible 1 -> 0, off 1, on 0, ms 0
>[ 5273.624311] [drm:skl_compute_wm [i915]] [PLANE:38:plane 1B] ddb (0 - 860) -> (0 - 0)
>[ 5273.624339] [drm:drm_atomic_commit [drm]] committing 000000005c12011a
>[ 5273.627894] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000005c12011a
>[ 5273.627928] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000005c12011a
>[ 5273.628117] [drm:drm_mode_addfb2 [drm]] [FB:71]
>[ 5273.628165] [drm:drm_mode_addfb2 [drm]] [FB:73]
>[ 5273.628196] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[ 5273.628225] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:61:DP-2]
>[ 5273.628256] [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000020b6dfe7
>[ 5273.628286] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:47:pipe B] 0000000081e9cf65 state to 0000000020b6dfe7
>[ 5273.628311] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:38:plane 1B] 0000000057f8b943 state to 0000000020b6dfe7
>[ 5273.628337] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [MODE:1920x1200] for CRTC state 0000000081e9cf65
>[ 5273.628358] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 0000000057f8b943 to [CRTC:47:pipe B]
>[ 5273.628379] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:71] for plane state 0000000057f8b943
>[ 5273.628400] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:47:pipe B] to 0000000020b6dfe7
>[ 5273.628423] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:61:DP-2] 00000000d388f03f state to 0000000020b6dfe7
>[ 5273.628444] [drm:drm_atomic_set_crtc_for_connector [drm]] Link connector state 00000000d388f03f to [NOCRTC]
>[ 5273.628463] [drm:drm_atomic_set_crtc_for_connector [drm]] Link connector state 00000000d388f03f to [CRTC:47:pipe B]
>[ 5273.628486] [drm:drm_atomic_check_only [drm]] checking 0000000020b6dfe7
>[ 5273.628507] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:61:DP-2]
>[ 5273.628522] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:61:DP-2] keeps [ENCODER:60:DDI C], now on [CRTC:47:pipe B]
>[ 5273.628618] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:47:pipe B] has [PLANE:38:plane 1B] with fb 71
>[ 5273.628693] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:38:plane 1B] visible 0 -> 1, off 0, on 1, ms 0
>[ 5273.628757] [drm:skl_compute_wm [i915]] [PLANE:38:plane 1B] ddb (0 - 0) -> (0 - 860)
>[ 5273.628782] [drm:drm_atomic_commit [drm]] committing 0000000020b6dfe7
>[ 5273.644588] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000020b6dfe7
>[ 5273.644598] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000020b6dfe7
>[ 5273.644611] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000005c12011a
>[ 5273.644619] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:47:pipe B] 00000000ef7e8929 state to 000000005c12011a
>[ 5273.644624] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:38:plane 1B] 000000000c3ecdec state to 000000005c12011a
>[ 5273.644629] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 000000000c3ecdec to [CRTC:47:pipe B]
>[ 5273.644634] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:71] for plane state 000000000c3ecdec
>[ 5273.644638] [drm:drm_atomic_check_only [drm]] checking 000000005c12011a
>[ 5273.644664] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:47:pipe B] has [PLANE:38:plane 1B] with fb 71
>[ 5273.644681] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:38:plane 1B] visible 1 -> 1, off 0, on 0, ms 0
>[ 5273.644689] [drm:drm_atomic_nonblocking_commit [drm]] committing 000000005c12011a nonblocking
>[ 5273.661260] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000005c12011a
>[ 5273.661271] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000005c12011a
>[ 5280.678988] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000005c12011a
>[ 5280.679028] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:38:plane 1B] 00000000c4e4455d state to 000000005c12011a
>[ 5280.679057] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:47:pipe B] 000000002b48c403 state to 000000005c12011a
>[ 5280.679081] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for plane state 00000000c4e4455d
>[ 5280.679102] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 00000000c4e4455d to [NOCRTC]
>[ 5280.679124] [drm:drm_atomic_check_only [drm]] checking 000000005c12011a
>[ 5280.679220] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:47:pipe B] has [PLANE:38:plane 1B] with fb -1
>[ 5280.679296] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:38:plane 1B] visible 1 -> 0, off 1, on 0, ms 0
>[ 5280.679359] [drm:skl_compute_wm [i915]] [PLANE:38:plane 1B] ddb (0 - 860) -> (0 - 0)
>[ 5280.679387] [drm:drm_atomic_commit [drm]] committing 000000005c12011a
>[ 5280.683766] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000005c12011a
>[ 5280.683800] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000005c12011a
>[ 5280.684156] [IGT] kms_render: exiting, ret=0
>[ 5280.717405] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000005c12011a
>[ 5280.717439] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 000000000c3ecdec state to 000000005c12011a
>[ 5280.717462] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 2A] 00000000c7235117 state to 000000005c12011a
>[ 5280.717482] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 00000000c7235117 to [NOCRTC]
>[ 5280.717501] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for plane state 00000000c7235117
>[ 5280.717520] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:34:cursor A] 00000000ac301d3a state to 000000005c12011a
>[ 5280.717537] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 00000000ac301d3a to [NOCRTC]
>[ 5280.717554] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for plane state 00000000ac301d3a
>[ 5280.717571] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:38:plane 1B] 00000000ea2bc5b3 state to 000000005c12011a
>[ 5280.717589] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:41:plane 2B] 00000000dda4a458 state to 000000005c12011a
>[ 5280.717605] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 00000000dda4a458 to [NOCRTC]
>[ 5280.717622] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for plane state 00000000dda4a458
>[ 5280.717639] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:44:cursor B] 00000000499e6cef state to 000000005c12011a
>[ 5280.717655] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 00000000499e6cef to [NOCRTC]
>[ 5280.717671] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for plane state 00000000499e6cef
>[ 5280.717691] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:37:pipe A] 00000000ef7e8929 state to 000000005c12011a
>[ 5280.717714] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [MODE:1920x1080] for CRTC state 00000000ef7e8929
>[ 5280.717731] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 000000000c3ecdec to [CRTC:37:pipe A]
>[ 5280.717748] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:115] for plane state 000000000c3ecdec
>[ 5280.717766] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:37:pipe A] to 000000005c12011a
>[ 5280.717787] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:56:DP-1] 000000008b5a8568 state to 000000005c12011a
>[ 5280.717804] [drm:drm_atomic_set_crtc_for_connector [drm]] Link connector state 000000008b5a8568 to [CRTC:37:pipe A]
>[ 5280.717823] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:47:pipe B] 00000000604357f6 state to 000000005c12011a
>[ 5280.717841] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [MODE:1920x1200] for CRTC state 00000000604357f6
>[ 5280.717858] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 00000000ea2bc5b3 to [CRTC:47:pipe B]
>[ 5280.717874] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:115] for plane state 00000000ea2bc5b3
>[ 5280.717891] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:47:pipe B] to 000000005c12011a
>[ 5280.717909] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:61:DP-2] 000000000e2efd0f state to 000000005c12011a
>[ 5280.717926] [drm:drm_atomic_set_crtc_for_connector [drm]] Link connector state 000000000e2efd0f to [NOCRTC]
>[ 5280.717943] [drm:drm_atomic_set_crtc_for_connector [drm]] Link connector state 000000000e2efd0f to [CRTC:47:pipe B]
>[ 5280.717960] [drm:drm_atomic_check_only [drm]] checking 000000005c12011a
>[ 5280.717979] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:37:pipe A] mode changed
>[ 5280.717990] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:37:pipe A] enable changed
>[ 5280.718000] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:37:pipe A] active changed
>[ 5280.718014] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:56:DP-1]
>[ 5280.718026] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:56:DP-1] using [ENCODER:55:DDI B] on [CRTC:37:pipe A]
>[ 5280.718035] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:61:DP-2]
>[ 5280.718046] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:61:DP-2] keeps [ENCODER:60:DDI C], now on [CRTC:47:pipe B]
>[ 5280.718056] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:37:pipe A] needs all connectors, enable: y, active: y
>[ 5280.718075] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:37:pipe A] to 000000005c12011a
>[ 5280.718096] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:37:pipe A] to 000000005c12011a
>[ 5280.718180] [drm:intel_atomic_check [i915]] [CONNECTOR:56:DP-1] checking for sink bpp constrains
>[ 5280.718252] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 148500KHz
>[ 5280.718333] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 4 clock 270000 bpp 36
>[ 5280.718392] [drm:intel_dp_compute_config [i915]] DP link bw required 668250 available 1080000
>[ 5280.718457] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 36, dithering: 0
>[ 5280.718520] [drm:intel_dump_pipe_config [i915]] [CRTC:37:pipe A][modeset]
>[ 5280.718578] [drm:intel_dump_pipe_config [i915]] output_types: DP (0x80)
>[ 5280.718634] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 36, dithering: 0
>[ 5280.718688] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5190451, gmch_n: 8388608, link_m: 288358, link_n: 524288, tu: 64
>[ 5280.718739] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 5280.718790] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 5280.718819] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x9
>[ 5280.718872] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 5280.718899] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x9
>[ 5280.718954] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x9
>[ 5280.719007] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500
>[ 5280.719057] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[ 5280.719106] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 5280.719155] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 5280.719205] [drm:intel_dump_pipe_config [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[ 5280.719252] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 5280.719300] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 1A] disabled, scaler_id = -1
>[ 5280.719348] [drm:intel_dump_pipe_config [i915]] [PLANE:31:plane 2A] disabled, scaler_id = -1
>[ 5280.719395] [drm:intel_dump_pipe_config [i915]] [PLANE:34:cursor A] disabled, scaler_id = -1
>[ 5280.719457] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 5280.719513] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[ 5280.719576] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:37:pipe A] has [PLANE:28:plane 1A] with fb 115
>[ 5280.719633] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 0 -> 1, off 0, on 1, ms 1
>[ 5280.719688] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:47:pipe B] has [PLANE:38:plane 1B] with fb 115
>[ 5280.719741] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:38:plane 1B] visible 0 -> 1, off 0, on 1, ms 0
>[ 5280.719801] [drm:intel_find_shared_dpll [i915]] [CRTC:37:pipe A] allocated DPLL 2
>[ 5280.719856] [drm:intel_reference_shared_dpll [i915]] using DPLL 2 for pipe A
>[ 5280.719913] [drm:skl_compute_wm [i915]] [PLANE:28:plane 1A] ddb (0 - 0) -> (0 - 438)
>[ 5280.719959] [drm:skl_compute_wm [i915]] [PLANE:34:cursor A] ddb (0 - 0) -> (438 - 446)
>[ 5280.720003] [drm:skl_compute_wm [i915]] [PLANE:38:plane 1B] ddb (0 - 0) -> (446 - 884)
>[ 5280.720047] [drm:skl_compute_wm [i915]] [PLANE:44:cursor B] ddb (860 - 892) -> (884 - 892)
>[ 5280.720075] [drm:drm_atomic_commit [drm]] committing 000000005c12011a
>[ 5280.720166] [drm:intel_disable_sagv [i915]] Disabling the SAGV
>[ 5280.720233] [drm:intel_atomic_commit_tail [i915]] [ENCODER:48:DDI A]
>[ 5280.720289] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI B]
>[ 5280.720341] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[ 5280.720392] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[ 5280.720442] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DDI C]
>[ 5280.720492] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST A]
>[ 5280.720542] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST B]
>[ 5280.720591] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI D]
>[ 5280.720640] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[ 5280.720689] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[ 5280.720744] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[ 5280.720801] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[ 5280.720855] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[ 5280.720908] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[ 5280.733764] [drm:intel_enable_shared_dpll [i915]] enable DPLL 2 (active 1, on? 0) for crtc 37
>[ 5280.733780] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 2
>[ 5280.733870] [drm:intel_power_well_enable [i915]] enabling DDI B IO power well
>[ 5280.734429] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5280.735560] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5280.736684] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5280.737704] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5280.738822] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5280.739941] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5280.741055] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5280.741760] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] too many retries, giving up
>[ 5280.742178] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5280.743290] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5280.744400] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5280.745529] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5280.746637] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5280.747742] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5280.748846] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5280.749539] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] too many retries, giving up
>[ 5280.750978] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5280.752081] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5280.753184] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5280.754288] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5280.755391] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5280.756490] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5280.757631] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5280.758317] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] too many retries, giving up
>[ 5280.758740] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5280.759839] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5280.760845] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5280.761946] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5280.763048] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5280.764146] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5280.765246] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5280.765924] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] too many retries, giving up
>[ 5280.767570] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5280.768812] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5280.770035] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5280.771284] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5280.772143] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[ 5280.773094] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 5280.773162] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 5280.773207] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 5280.773251] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 5280.791978] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 5280.792023] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[ 5280.809874] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 5280.810055] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:56:DP-1] Link Training Passed at Link Rate = 270000, Lane count = 4
>[ 5280.810479] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 5280.810506] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS
>[ 5280.810528] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:56:DP-1], [ENCODER:55:DDI B]
>[ 5280.810548] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 5280.810569] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 5280.810604] [drm:intel_fbc_enable [i915]] reserved 8294400 bytes of contiguous stolen space for FBC, threshold: 1
>[ 5280.810624] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 5280.827275] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:56:DP-1]
>[ 5280.827299] [drm:intel_atomic_commit_tail [i915]] [CRTC:37:pipe A]
>[ 5280.827329] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[ 5280.827347] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000005c12011a
>[ 5280.827358] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000005c12011a
>[ 5280.827363] [drm:drm_fb_helper_hotplug_event.part.33 [drm_kms_helper]] 
>[ 5280.827366] [drm:drm_setup_crtcs [drm_kms_helper]] 
>[ 5280.827371] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:49:eDP-1]
>[ 5280.827392] [drm:intel_dp_detect [i915]] [CONNECTOR:49:eDP-1]
>[ 5280.827413] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>[ 5280.827431] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[ 5280.827447] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[ 5280.827519] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[ 5280.827590] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle
>[ 5280.827836] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 00000000 control 00000060
>[ 5280.827906] [drm:wait_panel_status [i915]] Wait complete
>[ 5280.828151] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x00000000 PP_CONTROL: 0x00000068
>[ 5280.828220] [drm:edp_panel_vdd_on [i915]] eDP port A panel power wasn't enabled
>[ 5280.930216] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010
>[ 5280.930297] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[ 5280.930367] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0
>[ 5280.930499] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[ 5281.033939] [drm:drm_dp_read_desc [drm_kms_helper]] DP sink: OUI 00-1c-f8 dev-ID q\006UA\022\001 HW-rev 10.0 SW-rev 1.41 quirks 0x0000
>[ 5281.035130] [drm:drm_add_display_info [drm]] non_desktop set to 0
>[ 5281.035163] [drm:drm_add_edid_modes [drm]] ELD: no CEA Extension found
>[ 5281.035185] [drm:drm_add_display_info [drm]] non_desktop set to 0
>[ 5281.035231] [drm:drm_mode_debug_printmodeline [drm]] Modeline 99:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa
>[ 5281.035251] [drm:drm_mode_prune_invalid [drm]] Not using 1920x1080 mode: CLOCK_HIGH
>[ 5281.035267] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:56:DP-1]
>[ 5281.035351] [drm:intel_dp_detect [i915]] [CONNECTOR:56:DP-1]
>[ 5281.035787] [drm:lspcon_wake_native_aux_ch [i915]] Native AUX CH up, DPCD version: 1.2
>[ 5281.035905] [drm:lspcon_resume [i915]] LSPCON recovering in PCON mode after 0 ms
>[ 5281.036345] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5281.037614] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5281.038882] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5281.040142] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5281.041422] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5281.042315] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[ 5281.042790] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 00 00 04 00 0f 00 04
>[ 5281.043562] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>[ 5281.043615] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000
>[ 5281.043665] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000
>[ 5281.044066] [drm:drm_dp_read_desc [drm_kms_helper]] DP branch: OUI 00-60-ad dev-ID MC2800 HW-rev 2.2 SW-rev 1.72 quirks 0x0000
>[ 5281.044415] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[ 5281.045209] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5281.046495] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5281.047769] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5281.049041] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5281.050320] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5281.051579] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5281.052849] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5281.054098] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5281.055360] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5281.056755] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5281.058080] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5281.059477] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5281.060879] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5281.062253] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5281.063652] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5281.065048] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5281.066443] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5281.067701] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5281.068978] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5281.070256] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5281.071516] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5281.072910] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5281.074313] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5281.075717] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5281.077125] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5281.078532] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5281.079925] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5281.081324] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5281.082715] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5281.083560] [drm:drm_detect_monitor_audio [drm]] Monitor has basic audio support
>[ 5281.083887] [drm:drm_add_display_info [drm]] non_desktop set to 0
>[ 5281.083908] [drm:drm_add_display_info [drm]] HDMI: DVI dual 0, max TMDS clock 225000 kHz
>[ 5281.083934] [drm:drm_add_edid_modes [drm]] ELD monitor BOBCAT2800
>[ 5281.083953] [drm:drm_add_edid_modes [drm]] HDMI: latency present 0 0, video latency 0 0, audio latency 0 0
>[ 5281.083968] [drm:drm_add_edid_modes [drm]] ELD size 36, SAD count 1
>[ 5281.083985] [drm:drm_add_display_info [drm]] non_desktop set to 0
>[ 5281.084000] [drm:drm_add_display_info [drm]] HDMI: DVI dual 0, max TMDS clock 225000 kHz
>[ 5281.084463] [drm:drm_mode_debug_printmodeline [drm]] Modeline 139:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[ 5281.084482] [drm:drm_mode_prune_invalid [drm]] Not using 720x480i mode: H_ILLEGAL
>[ 5281.084502] [drm:drm_mode_debug_printmodeline [drm]] Modeline 140:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[ 5281.084518] [drm:drm_mode_prune_invalid [drm]] Not using 720x576i mode: H_ILLEGAL
>[ 5281.084536] [drm:drm_mode_debug_printmodeline [drm]] Modeline 160:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[ 5281.084550] [drm:drm_mode_prune_invalid [drm]] Not using 720x480i mode: H_ILLEGAL
>[ 5281.084569] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:56:DP-1] probed modes :
>[ 5281.084587] [drm:drm_mode_debug_printmodeline [drm]] Modeline 74:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x9
>[ 5281.084604] [drm:drm_mode_debug_printmodeline [drm]] Modeline 81:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x40 0x9
>[ 5281.084620] [drm:drm_mode_debug_printmodeline [drm]] Modeline 75:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[ 5281.084637] [drm:drm_mode_debug_printmodeline [drm]] Modeline 120:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[ 5281.084653] [drm:drm_mode_debug_printmodeline [drm]] Modeline 76:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[ 5281.084669] [drm:drm_mode_debug_printmodeline [drm]] Modeline 121:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[ 5281.084686] [drm:drm_mode_debug_printmodeline [drm]] Modeline 109:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[ 5281.084704] [drm:drm_mode_debug_printmodeline [drm]] Modeline 114:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[ 5281.084720] [drm:drm_mode_debug_printmodeline [drm]] Modeline 116:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[ 5281.084736] [drm:drm_mode_debug_printmodeline [drm]] Modeline 132:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[ 5281.084752] [drm:drm_mode_debug_printmodeline [drm]] Modeline 80:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[ 5281.084768] [drm:drm_mode_debug_printmodeline [drm]] Modeline 87:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[ 5281.084784] [drm:drm_mode_debug_printmodeline [drm]] Modeline 79:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[ 5281.084800] [drm:drm_mode_debug_printmodeline [drm]] Modeline 82:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[ 5281.084817] [drm:drm_mode_debug_printmodeline [drm]] Modeline 77:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[ 5281.084833] [drm:drm_mode_debug_printmodeline [drm]] Modeline 122:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[ 5281.084848] [drm:drm_mode_debug_printmodeline [drm]] Modeline 113:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[ 5281.084864] [drm:drm_mode_debug_printmodeline [drm]] Modeline 88:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[ 5281.084881] [drm:drm_mode_debug_printmodeline [drm]] Modeline 89:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[ 5281.084897] [drm:drm_mode_debug_printmodeline [drm]] Modeline 90:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[ 5281.084913] [drm:drm_mode_debug_printmodeline [drm]] Modeline 83:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[ 5281.084929] [drm:drm_mode_debug_printmodeline [drm]] Modeline 110:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[ 5281.084945] [drm:drm_mode_debug_printmodeline [drm]] Modeline 123:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[ 5281.084960] [drm:drm_mode_debug_printmodeline [drm]] Modeline 78:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[ 5281.084976] [drm:drm_mode_debug_printmodeline [drm]] Modeline 84:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[ 5281.084992] [drm:drm_mode_debug_printmodeline [drm]] Modeline 124:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[ 5281.085008] [drm:drm_mode_debug_printmodeline [drm]] Modeline 85:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[ 5281.085024] [drm:drm_mode_debug_printmodeline [drm]] Modeline 86:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[ 5281.085035] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:61:DP-2]
>[ 5281.085105] [drm:intel_dp_detect [i915]] [CONNECTOR:61:DP-2]
>[ 5281.085664] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 00 02 02 06 05 00 00 00
>[ 5281.086014] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>[ 5281.086075] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[ 5281.086130] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[ 5281.086524] [drm:drm_dp_read_desc [drm_kms_helper]] DP sink: OUI 00-00-00 dev-ID  HW-rev 0.0 SW-rev 0.0 quirks 0x0000
>[ 5281.086585] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[ 5281.090531] [drm:drm_add_display_info [drm]] non_desktop set to 0
>[ 5281.090555] [drm:drm_add_edid_modes [drm]] ELD: no CEA Extension found
>[ 5281.090573] [drm:drm_add_display_info [drm]] non_desktop set to 0
>[ 5281.090713] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:61:DP-2] probed modes :
>[ 5281.090733] [drm:drm_mode_debug_printmodeline [drm]] Modeline 91:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[ 5281.090751] [drm:drm_mode_debug_printmodeline [drm]] Modeline 95:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0xa
>[ 5281.090767] [drm:drm_mode_debug_printmodeline [drm]] Modeline 103:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[ 5281.090783] [drm:drm_mode_debug_printmodeline [drm]] Modeline 92:"1680x1050" 60 146250 1680 1784 1960 2240 1050 1053 1059 1089 0x40 0x6
>[ 5281.090798] [drm:drm_mode_debug_printmodeline [drm]] Modeline 96:"1600x900" 60 108000 1600 1624 1704 1800 900 901 904 1000 0x40 0x5
>[ 5281.090812] [drm:drm_mode_debug_printmodeline [drm]] Modeline 104:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[ 5281.090827] [drm:drm_mode_debug_printmodeline [drm]] Modeline 93:"1440x900" 60 106500 1440 1520 1672 1904 900 903 909 934 0x40 0x6
>[ 5281.090842] [drm:drm_mode_debug_printmodeline [drm]] Modeline 94:"1280x800" 60 83500 1280 1352 1480 1680 800 803 809 831 0x40 0x6
>[ 5281.090857] [drm:drm_mode_debug_printmodeline [drm]] Modeline 97:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[ 5281.090871] [drm:drm_mode_debug_printmodeline [drm]] Modeline 112:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[ 5281.090886] [drm:drm_mode_debug_printmodeline [drm]] Modeline 105:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[ 5281.090900] [drm:drm_mode_debug_printmodeline [drm]] Modeline 111:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[ 5281.090910] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:64:HDMI-A-1]
>[ 5281.090967] [drm:intel_hdmi_detect [i915]] [CONNECTOR:64:HDMI-A-1]
>[ 5281.091472] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[ 5281.091519] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[ 5281.091916] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[ 5281.091992] [drm:drm_do_probe_ddc_edid [drm]] drm: skipping non-existent adapter i915 gmbus dpc
>[ 5281.092429] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[ 5281.092474] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[ 5281.092864] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[ 5281.092950] [drm:drm_dp_dual_mode_detect [drm_kms_helper]] DP dual mode HDMI ID:  (err -6)
>[ 5281.092960] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:64:HDMI-A-1] disconnected
>[ 5281.092970] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:67:DP-3]
>[ 5281.093018] [drm:intel_dp_detect [i915]] [CONNECTOR:67:DP-3]
>[ 5281.093111] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:67:DP-3] disconnected
>[ 5281.093122] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:70:HDMI-A-2]
>[ 5281.093169] [drm:intel_hdmi_detect [i915]] [CONNECTOR:70:HDMI-A-2]
>[ 5281.113598] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0050 w(1)
>[ 5281.113664] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK on first message, retry
>[ 5281.133927] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0050 w(1)
>[ 5281.134029] [drm:drm_do_probe_ddc_edid [drm]] drm: skipping non-existent adapter i915 gmbus dpd
>[ 5281.154371] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0040 w(1)
>[ 5281.154434] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK on first message, retry
>[ 5281.175119] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0040 w(1)
>[ 5281.175192] [drm:drm_dp_dual_mode_detect [drm_kms_helper]] DP dual mode HDMI ID:  (err -6)
>[ 5281.175205] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:70:HDMI-A-2] disconnected
>[ 5281.175218] [drm:drm_setup_crtcs [drm_kms_helper]] connector 49 enabled? yes
>[ 5281.175229] [drm:drm_setup_crtcs [drm_kms_helper]] connector 56 enabled? yes
>[ 5281.175238] [drm:drm_setup_crtcs [drm_kms_helper]] connector 61 enabled? yes
>[ 5281.175248] [drm:drm_setup_crtcs [drm_kms_helper]] connector 64 enabled? no
>[ 5281.175257] [drm:drm_setup_crtcs [drm_kms_helper]] connector 67 enabled? no
>[ 5281.175267] [drm:drm_setup_crtcs [drm_kms_helper]] connector 70 enabled? no
>[ 5281.175338] [drm:intel_fb_initial_config [i915]] Not using firmware configuration
>[ 5281.175351] [drm:drm_setup_crtcs [drm_kms_helper]] looking for cmdline mode on connector 49
>[ 5281.175361] [drm:drm_setup_crtcs [drm_kms_helper]] looking for preferred mode on connector 49 0
>[ 5281.175371] [drm:drm_setup_crtcs [drm_kms_helper]] found mode none
>[ 5281.175380] [drm:drm_setup_crtcs [drm_kms_helper]] looking for cmdline mode on connector 56
>[ 5281.175390] [drm:drm_setup_crtcs [drm_kms_helper]] looking for preferred mode on connector 56 0
>[ 5281.175399] [drm:drm_setup_crtcs [drm_kms_helper]] found mode 1920x1080
>[ 5281.175409] [drm:drm_setup_crtcs [drm_kms_helper]] looking for cmdline mode on connector 61
>[ 5281.175418] [drm:drm_setup_crtcs [drm_kms_helper]] looking for preferred mode on connector 61 0
>[ 5281.175427] [drm:drm_setup_crtcs [drm_kms_helper]] found mode 1920x1200
>[ 5281.175437] [drm:drm_setup_crtcs [drm_kms_helper]] picking CRTCs for 1920x1200 config
>[ 5281.175454] [drm:drm_setup_crtcs [drm_kms_helper]] desired mode 1920x1080 set on crtc 37 (0,0)
>[ 5281.175466] [drm:drm_setup_crtcs [drm_kms_helper]] desired mode 1920x1200 set on crtc 47 (0,0)
>[ 5281.175500] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000005c12011a
>[ 5281.175527] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 000000009ab65c06 state to 000000005c12011a
>[ 5281.175549] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:37:pipe A] 000000002b48c403 state to 000000005c12011a
>[ 5281.175568] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 2A] 00000000b2cd0f1b state to 000000005c12011a
>[ 5281.175586] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 00000000b2cd0f1b to [NOCRTC]
>[ 5281.175605] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for plane state 00000000b2cd0f1b
>[ 5281.175623] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:34:cursor A] 000000004dbc9d33 state to 000000005c12011a
>[ 5281.175641] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 000000004dbc9d33 to [NOCRTC]
>[ 5281.175658] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for plane state 000000004dbc9d33
>[ 5281.175675] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:38:plane 1B] 00000000c88ee4f4 state to 000000005c12011a
>[ 5281.175693] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:47:pipe B] 00000000c85dec7a state to 000000005c12011a
>[ 5281.175710] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:41:plane 2B] 00000000517535b1 state to 000000005c12011a
>[ 5281.175726] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 00000000517535b1 to [NOCRTC]
>[ 5281.175742] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for plane state 00000000517535b1
>[ 5281.175759] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:44:cursor B] 000000002b2bc549 state to 000000005c12011a
>[ 5281.175774] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 000000002b2bc549 to [NOCRTC]
>[ 5281.175790] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for plane state 000000002b2bc549
>[ 5281.175811] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [MODE:1920x1080] for CRTC state 000000002b48c403
>[ 5281.175828] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 000000009ab65c06 to [CRTC:37:pipe A]
>[ 5281.175845] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:115] for plane state 000000009ab65c06
>[ 5281.175863] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:37:pipe A] to 000000005c12011a
>[ 5281.175881] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:56:DP-1] 00000000b07225ab state to 000000005c12011a
>[ 5281.175899] [drm:drm_atomic_set_crtc_for_connector [drm]] Link connector state 00000000b07225ab to [NOCRTC]
>[ 5281.175916] [drm:drm_atomic_set_crtc_for_connector [drm]] Link connector state 00000000b07225ab to [CRTC:37:pipe A]
>[ 5281.175935] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [MODE:1920x1200] for CRTC state 00000000c85dec7a
>[ 5281.175951] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 00000000c88ee4f4 to [CRTC:47:pipe B]
>[ 5281.175967] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:115] for plane state 00000000c88ee4f4
>[ 5281.175984] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:47:pipe B] to 000000005c12011a
>[ 5281.176002] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:61:DP-2] 000000009f87d14d state to 000000005c12011a
>[ 5281.176019] [drm:drm_atomic_set_crtc_for_connector [drm]] Link connector state 000000009f87d14d to [NOCRTC]
>[ 5281.176035] [drm:drm_atomic_set_crtc_for_connector [drm]] Link connector state 000000009f87d14d to [CRTC:47:pipe B]
>[ 5281.176052] [drm:drm_atomic_check_only [drm]] checking 000000005c12011a
>[ 5281.176071] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:56:DP-1]
>[ 5281.176083] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:56:DP-1] keeps [ENCODER:55:DDI B], now on [CRTC:37:pipe A]
>[ 5281.176093] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:61:DP-2]
>[ 5281.176102] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:61:DP-2] keeps [ENCODER:60:DDI C], now on [CRTC:47:pipe B]
>[ 5281.176182] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:37:pipe A] has [PLANE:28:plane 1A] with fb 115
>[ 5281.176249] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>[ 5281.176312] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:47:pipe B] has [PLANE:38:plane 1B] with fb 115
>[ 5281.176370] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:38:plane 1B] visible 1 -> 1, off 0, on 0, ms 0
>[ 5281.176406] [drm:drm_atomic_commit [drm]] committing 000000005c12011a
>[ 5281.184036] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000005c12011a
>[ 5281.184070] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000005c12011a
>[ 5282.152935] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 5282.153008] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 5282.153158] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[ 5282.153652] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 00 00 04 00 0f 00 04
>[ 5282.154013] [drm:i915_hotplug_work_func [i915]] running encoder hotplug functions
>[ 5282.154073] [drm:i915_hotplug_work_func [i915]] Connector DP-1 (pin 5) received hotplug event.
>[ 5282.154128] [drm:intel_dp_detect [i915]] [CONNECTOR:56:DP-1]
>[ 5282.154539] [drm:lspcon_wake_native_aux_ch [i915]] Native AUX CH up, DPCD version: 1.2
>[ 5282.154648] [drm:lspcon_resume [i915]] LSPCON recovering in PCON mode after 0 ms
>[ 5282.155085] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5282.156351] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5282.157633] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5282.158889] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5282.160153] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5282.161042] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[ 5282.161529] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 00 00 04 00 0f 00 04
>[ 5282.161891] [drm:i915_hotplug_work_func [i915]] [CONNECTOR:56:DP-1] status updated from connected to disconnected
>[ 5282.161945] [drm:drm_fb_helper_hotplug_event.part.33 [drm_kms_helper]] 
>[ 5282.161955] [drm:drm_setup_crtcs [drm_kms_helper]] 
>[ 5282.161968] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:49:eDP-1]
>[ 5282.162027] [drm:intel_dp_detect [i915]] [CONNECTOR:49:eDP-1]
>[ 5282.162087] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>[ 5282.162140] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[ 5282.162189] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[ 5282.162848] [drm:drm_dp_read_desc [drm_kms_helper]] DP sink: OUI 00-1c-f8 dev-ID q\006UA\022\001 HW-rev 10.0 SW-rev 1.41 quirks 0x0000
>[ 5282.164020] [drm:drm_add_display_info [drm]] non_desktop set to 0
>[ 5282.164049] [drm:drm_add_edid_modes [drm]] ELD: no CEA Extension found
>[ 5282.164069] [drm:drm_add_display_info [drm]] non_desktop set to 0
>[ 5282.164109] [drm:drm_mode_debug_printmodeline [drm]] Modeline 73:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa
>[ 5282.164129] [drm:drm_mode_prune_invalid [drm]] Not using 1920x1080 mode: CLOCK_HIGH
>[ 5282.164141] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:56:DP-1]
>[ 5282.164203] [drm:intel_dp_detect [i915]] [CONNECTOR:56:DP-1]
>[ 5282.164639] [drm:lspcon_wake_native_aux_ch [i915]] Native AUX CH up, DPCD version: 1.2
>[ 5282.164773] [drm:lspcon_resume [i915]] LSPCON recovering in PCON mode after 0 ms
>[ 5282.165219] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5282.166436] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5282.167694] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5282.168945] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5282.170210] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5282.171096] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[ 5282.171566] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 00 00 04 00 0f 00 04
>[ 5282.171874] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:56:DP-1] disconnected
>[ 5282.171896] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:61:DP-2]
>[ 5282.171954] [drm:intel_dp_detect [i915]] [CONNECTOR:61:DP-2]
>[ 5282.172459] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 00 02 02 06 05 00 00 00
>[ 5282.172794] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>[ 5282.172844] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[ 5282.172892] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[ 5282.173291] [drm:drm_dp_read_desc [drm_kms_helper]] DP sink: OUI 00-00-00 dev-ID  HW-rev 0.0 SW-rev 0.0 quirks 0x0000
>[ 5282.173345] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[ 5282.177177] [drm:drm_add_display_info [drm]] non_desktop set to 0
>[ 5282.177184] [drm:drm_add_edid_modes [drm]] ELD: no CEA Extension found
>[ 5282.177202] [drm:drm_add_display_info [drm]] non_desktop set to 0
>[ 5282.177238] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:61:DP-2] probed modes :
>[ 5282.177243] [drm:drm_mode_debug_printmodeline [drm]] Modeline 91:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[ 5282.177247] [drm:drm_mode_debug_printmodeline [drm]] Modeline 95:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0xa
>[ 5282.177251] [drm:drm_mode_debug_printmodeline [drm]] Modeline 103:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[ 5282.177255] [drm:drm_mode_debug_printmodeline [drm]] Modeline 92:"1680x1050" 60 146250 1680 1784 1960 2240 1050 1053 1059 1089 0x40 0x6
>[ 5282.177258] [drm:drm_mode_debug_printmodeline [drm]] Modeline 96:"1600x900" 60 108000 1600 1624 1704 1800 900 901 904 1000 0x40 0x5
>[ 5282.177262] [drm:drm_mode_debug_printmodeline [drm]] Modeline 104:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[ 5282.177265] [drm:drm_mode_debug_printmodeline [drm]] Modeline 93:"1440x900" 60 106500 1440 1520 1672 1904 900 903 909 934 0x40 0x6
>[ 5282.177269] [drm:drm_mode_debug_printmodeline [drm]] Modeline 94:"1280x800" 60 83500 1280 1352 1480 1680 800 803 809 831 0x40 0x6
>[ 5282.177272] [drm:drm_mode_debug_printmodeline [drm]] Modeline 97:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[ 5282.177276] [drm:drm_mode_debug_printmodeline [drm]] Modeline 112:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[ 5282.177279] [drm:drm_mode_debug_printmodeline [drm]] Modeline 105:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[ 5282.177283] [drm:drm_mode_debug_printmodeline [drm]] Modeline 111:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[ 5282.177285] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:64:HDMI-A-1]
>[ 5282.177299] [drm:intel_hdmi_detect [i915]] [CONNECTOR:64:HDMI-A-1]
>[ 5282.177718] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[ 5282.177729] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[ 5282.178102] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[ 5282.178173] [drm:drm_do_probe_ddc_edid [drm]] drm: skipping non-existent adapter i915 gmbus dpc
>[ 5282.178603] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[ 5282.178614] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[ 5282.178958] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[ 5282.179005] [drm:drm_dp_dual_mode_detect [drm_kms_helper]] DP dual mode HDMI ID:  (err -6)
>[ 5282.179007] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:64:HDMI-A-1] disconnected
>[ 5282.179009] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:67:DP-3]
>[ 5282.179021] [drm:intel_dp_detect [i915]] [CONNECTOR:67:DP-3]
>[ 5282.179049] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:67:DP-3] disconnected
>[ 5282.179051] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:70:HDMI-A-2]
>[ 5282.179062] [drm:intel_hdmi_detect [i915]] [CONNECTOR:70:HDMI-A-2]
>[ 5282.199201] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0050 w(1)
>[ 5282.199215] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK on first message, retry
>[ 5282.219285] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0050 w(1)
>[ 5282.219352] [drm:drm_do_probe_ddc_edid [drm]] drm: skipping non-existent adapter i915 gmbus dpd
>[ 5282.239317] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0040 w(1)
>[ 5282.239357] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK on first message, retry
>[ 5282.259558] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0040 w(1)
>[ 5282.259677] [drm:drm_dp_dual_mode_detect [drm_kms_helper]] DP dual mode HDMI ID:  (err -6)
>[ 5282.259691] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:70:HDMI-A-2] disconnected
>[ 5282.259706] [drm:drm_setup_crtcs [drm_kms_helper]] connector 49 enabled? yes
>[ 5282.259716] [drm:drm_setup_crtcs [drm_kms_helper]] connector 56 enabled? no
>[ 5282.259725] [drm:drm_setup_crtcs [drm_kms_helper]] connector 61 enabled? yes
>[ 5282.259735] [drm:drm_setup_crtcs [drm_kms_helper]] connector 64 enabled? no
>[ 5282.259744] [drm:drm_setup_crtcs [drm_kms_helper]] connector 67 enabled? no
>[ 5282.259752] [drm:drm_setup_crtcs [drm_kms_helper]] connector 70 enabled? no
>[ 5282.259820] [drm:intel_fb_initial_config [i915]] Not using firmware configuration
>[ 5282.259833] [drm:drm_setup_crtcs [drm_kms_helper]] looking for cmdline mode on connector 49
>[ 5282.259843] [drm:drm_setup_crtcs [drm_kms_helper]] looking for preferred mode on connector 49 0
>[ 5282.259852] [drm:drm_setup_crtcs [drm_kms_helper]] found mode none
>[ 5282.259860] [drm:drm_setup_crtcs [drm_kms_helper]] looking for cmdline mode on connector 61
>[ 5282.259869] [drm:drm_setup_crtcs [drm_kms_helper]] looking for preferred mode on connector 61 0
>[ 5282.259879] [drm:drm_setup_crtcs [drm_kms_helper]] found mode 1920x1200
>[ 5282.259888] [drm:drm_setup_crtcs [drm_kms_helper]] picking CRTCs for 1920x1200 config
>[ 5282.259904] [drm:drm_setup_crtcs [drm_kms_helper]] desired mode 1920x1200 set on crtc 37 (0,0)
>[ 5282.259938] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000fc827636
>[ 5282.259965] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000256624cf state to 00000000fc827636
>[ 5282.259988] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:37:pipe A] 00000000604357f6 state to 00000000fc827636
>[ 5282.260007] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 2A] 00000000e3bc9df0 state to 00000000fc827636
>[ 5282.260024] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 00000000e3bc9df0 to [NOCRTC]
>[ 5282.260041] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for plane state 00000000e3bc9df0
>[ 5282.260059] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:34:cursor A] 0000000046187cf3 state to 00000000fc827636
>[ 5282.260074] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 0000000046187cf3 to [NOCRTC]
>[ 5282.260090] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for plane state 0000000046187cf3
>[ 5282.260106] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:38:plane 1B] 0000000025337555 state to 00000000fc827636
>[ 5282.260123] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:47:pipe B] 00000000ef7e8929 state to 00000000fc827636
>[ 5282.260140] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:41:plane 2B] 00000000861bd9b9 state to 00000000fc827636
>[ 5282.260155] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 00000000861bd9b9 to [NOCRTC]
>[ 5282.260170] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for plane state 00000000861bd9b9
>[ 5282.260187] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:44:cursor B] 000000008da9ecee state to 00000000fc827636
>[ 5282.260201] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 000000008da9ecee to [NOCRTC]
>[ 5282.260216] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for plane state 000000008da9ecee
>[ 5282.260236] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [MODE:1920x1200] for CRTC state 00000000604357f6
>[ 5282.260251] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 00000000256624cf to [CRTC:37:pipe A]
>[ 5282.260267] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:115] for plane state 00000000256624cf
>[ 5282.260284] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:37:pipe A] to 00000000fc827636
>[ 5282.260303] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:56:DP-1] 000000000e2efd0f state to 00000000fc827636
>[ 5282.260319] [drm:drm_atomic_set_crtc_for_connector [drm]] Link connector state 000000000e2efd0f to [NOCRTC]
>[ 5282.260336] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:61:DP-2] 000000008b5a8568 state to 00000000fc827636
>[ 5282.260351] [drm:drm_atomic_set_crtc_for_connector [drm]] Link connector state 000000008b5a8568 to [CRTC:37:pipe A]
>[ 5282.260368] [drm:drm_atomic_set_mode_prop_for_crtc [drm]] Set [NOMODE] for CRTC state 00000000ef7e8929
>[ 5282.260384] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for CRTC state 00000000ef7e8929
>[ 5282.260400] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 0000000025337555 to [NOCRTC]
>[ 5282.260414] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for plane state 0000000025337555
>[ 5282.260430] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:47:pipe B] to 00000000fc827636
>[ 5282.260447] [drm:drm_atomic_check_only [drm]] checking 00000000fc827636
>[ 5282.260462] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:37:pipe A] mode changed
>[ 5282.260473] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:47:pipe B] mode changed
>[ 5282.260482] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:47:pipe B] enable changed
>[ 5282.260491] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:47:pipe B] active changed
>[ 5282.260504] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:56:DP-1]
>[ 5282.260512] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Disabling [CONNECTOR:56:DP-1]
>[ 5282.260521] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:61:DP-2]
>[ 5282.260532] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:61:DP-2] keeps [ENCODER:60:DDI C], now on [CRTC:37:pipe A]
>[ 5282.260541] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:37:pipe A] needs all connectors, enable: y, active: y
>[ 5282.260559] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:37:pipe A] to 00000000fc827636
>[ 5282.260570] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:47:pipe B] needs all connectors, enable: n, active: n
>[ 5282.260587] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:47:pipe B] to 00000000fc827636
>[ 5282.260606] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:37:pipe A] to 00000000fc827636
>[ 5282.260675] [drm:intel_atomic_check [i915]] [CONNECTOR:61:DP-2] checking for sink bpp constrains
>[ 5282.260739] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 5282.260804] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 5282.260878] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 5282.260931] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 5282.260991] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 5282.261050] [drm:intel_dump_pipe_config [i915]] [CRTC:37:pipe A][modeset]
>[ 5282.261103] [drm:intel_dump_pipe_config [i915]] output_types: DP (0x80)
>[ 5282.261189] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[ 5282.261255] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 5282.261318] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[ 5282.261376] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 5282.261412] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[ 5282.261471] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 5282.261508] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[ 5282.261569] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[ 5282.261627] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 5282.261685] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[ 5282.261742] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 5282.261800] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 5282.261856] [drm:intel_dump_pipe_config [i915]] dpll_hw_state: ctrl1: 0x3, cfgcr1: 0x0, cfgcr2: 0x0
>[ 5282.261910] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 5282.261967] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 1A] FB:115, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[ 5282.262022] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1080 dst 0x0+1920+1080
>[ 5282.262078] [drm:intel_dump_pipe_config [i915]] [PLANE:31:plane 2A] disabled, scaler_id = -1
>[ 5282.262134] [drm:intel_dump_pipe_config [i915]] [PLANE:34:cursor A] disabled, scaler_id = -1
>[ 5282.262202] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 5282.262265] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[ 5282.262334] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:37:pipe A] has [PLANE:28:plane 1A] with fb 115
>[ 5282.262398] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 1, on 1, ms 1
>[ 5282.262461] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:47:pipe B] has [PLANE:38:plane 1B] with fb -1
>[ 5282.262520] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:38:plane 1B] visible 1 -> 0, off 1, on 0, ms 1
>[ 5282.262587] [drm:intel_find_shared_dpll [i915]] [CRTC:37:pipe A] allocated DPLL 1
>[ 5282.262649] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[ 5282.262710] [drm:skl_compute_wm [i915]] [PLANE:28:plane 1A] ddb (0 - 438) -> (0 - 860)
>[ 5282.262756] [drm:skl_compute_wm [i915]] [PLANE:34:cursor A] ddb (438 - 446) -> (860 - 892)
>[ 5282.262803] [drm:skl_compute_wm [i915]] [PLANE:38:plane 1B] ddb (446 - 884) -> (0 - 0)
>[ 5282.262847] [drm:skl_compute_wm [i915]] [PLANE:44:cursor B] ddb (884 - 892) -> (0 - 0)
>[ 5282.262879] [drm:drm_atomic_commit [drm]] committing 00000000fc827636
>[ 5282.262968] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[ 5282.263035] [drm:i915_audio_component_get_eld [i915]] Not valid for port B
>[ 5282.263121] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 5282.279920] [drm:intel_power_well_disable [i915]] disabling DDI B IO power well
>[ 5282.279994] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 5282.280058] [drm:intel_disable_shared_dpll [i915]] disable DPLL 2 (active 1, on? 1) for crtc 37
>[ 5282.280115] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 2
>[ 5282.280189] [drm:intel_disable_pipe [i915]] disabling pipe B
>[ 5282.285984] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well
>[ 5282.286058] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 2, on? 1) for crtc 47
>[ 5282.286121] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[ 5282.286204] [drm:intel_atomic_commit_tail [i915]] [ENCODER:48:DDI A]
>[ 5282.286261] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI B]
>[ 5282.286315] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[ 5282.286364] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[ 5282.286411] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DDI C]
>[ 5282.286458] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST A]
>[ 5282.286504] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST B]
>[ 5282.286550] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI D]
>[ 5282.286596] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[ 5282.286642] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[ 5282.286695] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:56:DP-1]
>[ 5282.286748] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[ 5282.286800] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[ 5282.286849] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[ 5282.286898] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[ 5282.286961] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 37
>[ 5282.287014] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[ 5282.287152] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well
>[ 5282.288259] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 5282.288313] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 5282.288364] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 5282.288416] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 5282.289065] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 5282.289158] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 5282.290121] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 5282.290499] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:61:DP-2] Link Training Passed at Link Rate = 162000, Lane count = 4
>[ 5282.291079] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 5282.291143] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS
>[ 5282.291149] [drm] Reducing the compressed framebuffer size. This may lead to less power savings than a non-reduced-size. Try to increase stolen memory size if available in BIOS.
>[ 5282.291206] [drm:intel_fbc_enable [i915]] reserved 4608000 bytes of contiguous stolen space for FBC, threshold: 2
>[ 5282.291258] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 5282.307994] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:61:DP-2]
>[ 5282.308072] [drm:intel_atomic_commit_tail [i915]] [CRTC:37:pipe A]
>[ 5282.308157] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[ 5282.308223] [drm:intel_atomic_commit_tail [i915]] [CRTC:47:pipe B]
>[ 5282.308282] [drm:intel_enable_sagv [i915]] Enabling the SAGV
>[ 5282.308325] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000fc827636
>[ 5282.308355] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000fc827636
>[ 5284.224302] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[ 5284.224369] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[ 5284.224475] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[ 5284.224959] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 00 00 04 00 0f 00 04
>[ 5284.225783] [drm:i915_hotplug_work_func [i915]] running encoder hotplug functions
>[ 5284.225840] [drm:i915_hotplug_work_func [i915]] Connector DP-1 (pin 5) received hotplug event.
>[ 5284.225897] [drm:intel_dp_detect [i915]] [CONNECTOR:56:DP-1]
>[ 5284.226306] [drm:lspcon_wake_native_aux_ch [i915]] Native AUX CH up, DPCD version: 1.2
>[ 5284.226414] [drm:lspcon_resume [i915]] LSPCON recovering in PCON mode after 0 ms
>[ 5284.226851] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5284.227963] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5284.229121] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5284.230256] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5284.231374] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5284.232492] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5284.233679] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5284.234364] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] too many retries, giving up
>[ 5284.234808] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5284.235920] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5284.237035] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5284.238157] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5284.239270] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5284.240383] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5284.241536] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5284.242225] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] too many retries, giving up
>[ 5284.243743] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5284.244857] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5284.245956] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5284.247076] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5284.248194] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5284.249318] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5284.250434] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5284.251123] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] too many retries, giving up
>[ 5284.251370] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5284.252484] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5284.253719] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5284.254836] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5284.255950] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5284.257065] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5284.258214] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5284.258898] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] too many retries, giving up
>[ 5284.260566] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5284.261849] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5284.263103] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5284.264365] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5284.265275] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[ 5284.265748] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 00 00 04 00 0f 00 04
>[ 5284.266515] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>[ 5284.266569] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000
>[ 5284.266620] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000
>[ 5284.267018] [drm:drm_dp_read_desc [drm_kms_helper]] DP branch: OUI 00-60-ad dev-ID MC2800 HW-rev 2.2 SW-rev 1.72 quirks 0x0000
>[ 5284.267364] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[ 5284.268133] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5284.269399] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5284.270660] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5284.271917] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5284.273214] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5284.274463] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5284.275724] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5284.276995] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5284.278256] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5284.279644] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5284.281034] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5284.282423] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5284.283808] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5284.285201] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5284.286591] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5284.287977] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5284.289362] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5284.290611] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5284.291878] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5284.293216] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5284.294472] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5284.295863] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5284.297256] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5284.298642] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5284.300031] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5284.301429] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5284.302821] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5284.304216] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5284.305646] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5284.306490] [drm:drm_detect_monitor_audio [drm]] Monitor has basic audio support
>[ 5284.306856] [drm:i915_hotplug_work_func [i915]] [CONNECTOR:56:DP-1] status updated from disconnected to connected
>[ 5284.306911] [drm:drm_fb_helper_hotplug_event.part.33 [drm_kms_helper]] 
>[ 5284.306921] [drm:drm_setup_crtcs [drm_kms_helper]] 
>[ 5284.306934] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:49:eDP-1]
>[ 5284.306998] [drm:intel_dp_detect [i915]] [CONNECTOR:49:eDP-1]
>[ 5284.307061] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>[ 5284.307115] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[ 5284.307165] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[ 5284.307827] [drm:drm_dp_read_desc [drm_kms_helper]] DP sink: OUI 00-1c-f8 dev-ID q\006UA\022\001 HW-rev 10.0 SW-rev 1.41 quirks 0x0000
>[ 5284.308996] [drm:drm_add_display_info [drm]] non_desktop set to 0
>[ 5284.309024] [drm:drm_add_edid_modes [drm]] ELD: no CEA Extension found
>[ 5284.309044] [drm:drm_add_display_info [drm]] non_desktop set to 0
>[ 5284.309124] [drm:drm_mode_debug_printmodeline [drm]] Modeline 71:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa
>[ 5284.309156] [drm:drm_mode_prune_invalid [drm]] Not using 1920x1080 mode: CLOCK_HIGH
>[ 5284.309178] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:56:DP-1]
>[ 5284.309246] [drm:intel_dp_detect [i915]] [CONNECTOR:56:DP-1]
>[ 5284.309673] [drm:lspcon_wake_native_aux_ch [i915]] Native AUX CH up, DPCD version: 1.2
>[ 5284.309787] [drm:lspcon_resume [i915]] LSPCON recovering in PCON mode after 0 ms
>[ 5284.310225] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5284.311467] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5284.312728] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5284.313915] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5284.315180] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5284.316066] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[ 5284.316538] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 00 00 04 00 0f 00 04
>[ 5284.317311] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>[ 5284.317367] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000
>[ 5284.317420] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000
>[ 5284.317820] [drm:drm_dp_read_desc [drm_kms_helper]] DP branch: OUI 00-60-ad dev-ID MC2800 HW-rev 2.2 SW-rev 1.72 quirks 0x0000
>[ 5284.318167] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[ 5284.318934] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5284.320195] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5284.321469] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5284.322730] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5284.323990] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5284.325246] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5284.326514] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5284.327781] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5284.329033] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5284.330430] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5284.331825] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5284.333217] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5284.334603] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5284.335989] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5284.337388] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5284.338778] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5284.340161] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5284.341417] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5284.342680] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5284.343944] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5284.345215] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5284.346601] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5284.347992] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5284.349386] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5284.350777] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5284.352175] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5284.353657] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5284.355046] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5284.356423] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5284.357295] [drm:drm_detect_monitor_audio [drm]] Monitor has basic audio support
>[ 5284.357622] [drm:drm_add_display_info [drm]] non_desktop set to 0
>[ 5284.357642] [drm:drm_add_display_info [drm]] HDMI: DVI dual 0, max TMDS clock 225000 kHz
>[ 5284.357667] [drm:drm_add_edid_modes [drm]] ELD monitor BOBCAT2800
>[ 5284.357684] [drm:drm_add_edid_modes [drm]] HDMI: latency present 0 0, video latency 0 0, audio latency 0 0
>[ 5284.357700] [drm:drm_add_edid_modes [drm]] ELD size 36, SAD count 1
>[ 5284.357716] [drm:drm_add_display_info [drm]] non_desktop set to 0
>[ 5284.357731] [drm:drm_add_display_info [drm]] HDMI: DVI dual 0, max TMDS clock 225000 kHz
>[ 5284.358180] [drm:drm_mode_debug_printmodeline [drm]] Modeline 106:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[ 5284.358198] [drm:drm_mode_prune_invalid [drm]] Not using 720x480i mode: H_ILLEGAL
>[ 5284.358217] [drm:drm_mode_debug_printmodeline [drm]] Modeline 107:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[ 5284.358232] [drm:drm_mode_prune_invalid [drm]] Not using 720x576i mode: H_ILLEGAL
>[ 5284.358250] [drm:drm_mode_debug_printmodeline [drm]] Modeline 130:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[ 5284.358265] [drm:drm_mode_prune_invalid [drm]] Not using 720x480i mode: H_ILLEGAL
>[ 5284.358286] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:56:DP-1] probed modes :
>[ 5284.358304] [drm:drm_mode_debug_printmodeline [drm]] Modeline 74:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x9
>[ 5284.358321] [drm:drm_mode_debug_printmodeline [drm]] Modeline 81:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x40 0x9
>[ 5284.358339] [drm:drm_mode_debug_printmodeline [drm]] Modeline 75:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[ 5284.358355] [drm:drm_mode_debug_printmodeline [drm]] Modeline 120:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[ 5284.358372] [drm:drm_mode_debug_printmodeline [drm]] Modeline 76:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[ 5284.358388] [drm:drm_mode_debug_printmodeline [drm]] Modeline 121:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[ 5284.358405] [drm:drm_mode_debug_printmodeline [drm]] Modeline 109:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[ 5284.358421] [drm:drm_mode_debug_printmodeline [drm]] Modeline 114:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[ 5284.358437] [drm:drm_mode_debug_printmodeline [drm]] Modeline 116:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[ 5284.358453] [drm:drm_mode_debug_printmodeline [drm]] Modeline 132:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[ 5284.358471] [drm:drm_mode_debug_printmodeline [drm]] Modeline 80:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[ 5284.358487] [drm:drm_mode_debug_printmodeline [drm]] Modeline 87:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[ 5284.358503] [drm:drm_mode_debug_printmodeline [drm]] Modeline 79:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[ 5284.358518] [drm:drm_mode_debug_printmodeline [drm]] Modeline 82:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[ 5284.358535] [drm:drm_mode_debug_printmodeline [drm]] Modeline 77:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[ 5284.358551] [drm:drm_mode_debug_printmodeline [drm]] Modeline 122:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[ 5284.358567] [drm:drm_mode_debug_printmodeline [drm]] Modeline 113:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[ 5284.358582] [drm:drm_mode_debug_printmodeline [drm]] Modeline 88:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[ 5284.358599] [drm:drm_mode_debug_printmodeline [drm]] Modeline 89:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[ 5284.358615] [drm:drm_mode_debug_printmodeline [drm]] Modeline 90:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[ 5284.358631] [drm:drm_mode_debug_printmodeline [drm]] Modeline 83:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[ 5284.358647] [drm:drm_mode_debug_printmodeline [drm]] Modeline 110:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[ 5284.358663] [drm:drm_mode_debug_printmodeline [drm]] Modeline 123:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[ 5284.358678] [drm:drm_mode_debug_printmodeline [drm]] Modeline 78:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[ 5284.358694] [drm:drm_mode_debug_printmodeline [drm]] Modeline 84:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[ 5284.358710] [drm:drm_mode_debug_printmodeline [drm]] Modeline 124:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[ 5284.358726] [drm:drm_mode_debug_printmodeline [drm]] Modeline 85:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[ 5284.358742] [drm:drm_mode_debug_printmodeline [drm]] Modeline 86:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[ 5284.358753] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:61:DP-2]
>[ 5284.358823] [drm:intel_dp_detect [i915]] [CONNECTOR:61:DP-2]
>[ 5284.359340] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 00 02 02 06 05 00 00 00
>[ 5284.359683] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>[ 5284.359738] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[ 5284.359790] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[ 5284.360188] [drm:drm_dp_read_desc [drm_kms_helper]] DP sink: OUI 00-00-00 dev-ID  HW-rev 0.0 SW-rev 0.0 quirks 0x0000
>[ 5284.360240] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[ 5284.365405] [drm:drm_add_display_info [drm]] non_desktop set to 0
>[ 5284.365421] [drm:drm_add_edid_modes [drm]] ELD: no CEA Extension found
>[ 5284.365434] [drm:drm_add_display_info [drm]] non_desktop set to 0
>[ 5284.365535] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:61:DP-2] probed modes :
>[ 5284.365550] [drm:drm_mode_debug_printmodeline [drm]] Modeline 91:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[ 5284.365563] [drm:drm_mode_debug_printmodeline [drm]] Modeline 95:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0xa
>[ 5284.365574] [drm:drm_mode_debug_printmodeline [drm]] Modeline 103:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[ 5284.365585] [drm:drm_mode_debug_printmodeline [drm]] Modeline 92:"1680x1050" 60 146250 1680 1784 1960 2240 1050 1053 1059 1089 0x40 0x6
>[ 5284.365596] [drm:drm_mode_debug_printmodeline [drm]] Modeline 96:"1600x900" 60 108000 1600 1624 1704 1800 900 901 904 1000 0x40 0x5
>[ 5284.365606] [drm:drm_mode_debug_printmodeline [drm]] Modeline 104:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[ 5284.365617] [drm:drm_mode_debug_printmodeline [drm]] Modeline 93:"1440x900" 60 106500 1440 1520 1672 1904 900 903 909 934 0x40 0x6
>[ 5284.365627] [drm:drm_mode_debug_printmodeline [drm]] Modeline 94:"1280x800" 60 83500 1280 1352 1480 1680 800 803 809 831 0x40 0x6
>[ 5284.365638] [drm:drm_mode_debug_printmodeline [drm]] Modeline 97:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[ 5284.365648] [drm:drm_mode_debug_printmodeline [drm]] Modeline 112:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[ 5284.365659] [drm:drm_mode_debug_printmodeline [drm]] Modeline 105:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[ 5284.365669] [drm:drm_mode_debug_printmodeline [drm]] Modeline 111:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[ 5284.365676] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:64:HDMI-A-1]
>[ 5284.365717] [drm:intel_hdmi_detect [i915]] [CONNECTOR:64:HDMI-A-1]
>[ 5284.366181] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[ 5284.366217] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[ 5284.366631] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[ 5284.366718] [drm:drm_do_probe_ddc_edid [drm]] drm: skipping non-existent adapter i915 gmbus dpc
>[ 5284.367238] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[ 5284.367270] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[ 5284.367630] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[ 5284.367691] [drm:drm_dp_dual_mode_detect [drm_kms_helper]] DP dual mode HDMI ID:  (err -6)
>[ 5284.367698] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:64:HDMI-A-1] disconnected
>[ 5284.367706] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:67:DP-3]
>[ 5284.367739] [drm:intel_dp_detect [i915]] [CONNECTOR:67:DP-3]
>[ 5284.367780] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:67:DP-3] disconnected
>[ 5284.367786] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:70:HDMI-A-2]
>[ 5284.367818] [drm:intel_hdmi_detect [i915]] [CONNECTOR:70:HDMI-A-2]
>[ 5284.388005] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0050 w(1)
>[ 5284.388038] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK on first message, retry
>[ 5284.408213] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0050 w(1)
>[ 5284.408285] [drm:drm_do_probe_ddc_edid [drm]] drm: skipping non-existent adapter i915 gmbus dpd
>[ 5284.429037] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0040 w(1)
>[ 5284.429098] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK on first message, retry
>[ 5284.449267] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0040 w(1)
>[ 5284.449356] [drm:drm_dp_dual_mode_detect [drm_kms_helper]] DP dual mode HDMI ID:  (err -6)
>[ 5284.449369] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:70:HDMI-A-2] disconnected
>[ 5284.449382] [drm:drm_setup_crtcs [drm_kms_helper]] connector 49 enabled? yes
>[ 5284.449392] [drm:drm_setup_crtcs [drm_kms_helper]] connector 56 enabled? yes
>[ 5284.449401] [drm:drm_setup_crtcs [drm_kms_helper]] connector 61 enabled? yes
>[ 5284.449410] [drm:drm_setup_crtcs [drm_kms_helper]] connector 64 enabled? no
>[ 5284.449419] [drm:drm_setup_crtcs [drm_kms_helper]] connector 67 enabled? no
>[ 5284.449428] [drm:drm_setup_crtcs [drm_kms_helper]] connector 70 enabled? no
>[ 5284.449496] [drm:intel_fb_initial_config [i915]] Not using firmware configuration
>[ 5284.449508] [drm:drm_setup_crtcs [drm_kms_helper]] looking for cmdline mode on connector 49
>[ 5284.449518] [drm:drm_setup_crtcs [drm_kms_helper]] looking for preferred mode on connector 49 0
>[ 5284.449527] [drm:drm_setup_crtcs [drm_kms_helper]] found mode none
>[ 5284.449536] [drm:drm_setup_crtcs [drm_kms_helper]] looking for cmdline mode on connector 56
>[ 5284.449545] [drm:drm_setup_crtcs [drm_kms_helper]] looking for preferred mode on connector 56 0
>[ 5284.449554] [drm:drm_setup_crtcs [drm_kms_helper]] found mode 1920x1080
>[ 5284.449563] [drm:drm_setup_crtcs [drm_kms_helper]] looking for cmdline mode on connector 61
>[ 5284.449572] [drm:drm_setup_crtcs [drm_kms_helper]] looking for preferred mode on connector 61 0
>[ 5284.449581] [drm:drm_setup_crtcs [drm_kms_helper]] found mode 1920x1200
>[ 5284.449591] [drm:drm_setup_crtcs [drm_kms_helper]] picking CRTCs for 1920x1200 config
>[ 5284.449607] [drm:drm_setup_crtcs [drm_kms_helper]] desired mode 1920x1080 set on crtc 37 (0,0)
>[ 5284.449618] [drm:drm_setup_crtcs [drm_kms_helper]] desired mode 1920x1200 set on crtc 47 (0,0)
>[ 5284.449650] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000ae57c542
>[ 5284.449675] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000b7de9afe state to 00000000ae57c542
>[ 5284.449697] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:37:pipe A] 00000000c85dec7a state to 00000000ae57c542
>[ 5284.449717] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 2A] 00000000261eaafb state to 00000000ae57c542
>[ 5284.449733] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 00000000261eaafb to [NOCRTC]
>[ 5284.449752] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for plane state 00000000261eaafb
>[ 5284.449768] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:34:cursor A] 00000000dbc91590 state to 00000000ae57c542
>[ 5284.449784] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 00000000dbc91590 to [NOCRTC]
>[ 5284.449800] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for plane state 00000000dbc91590
>[ 5284.449816] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:38:plane 1B] 000000005eb15537 state to 00000000ae57c542
>[ 5284.449832] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:41:plane 2B] 00000000b6fe34e8 state to 00000000ae57c542
>[ 5284.449847] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 00000000b6fe34e8 to [NOCRTC]
>[ 5284.449862] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for plane state 00000000b6fe34e8
>[ 5284.449878] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:44:cursor B] 00000000e3ceaa91 state to 00000000ae57c542
>[ 5284.449894] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 00000000e3ceaa91 to [NOCRTC]
>[ 5284.449909] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for plane state 00000000e3ceaa91
>[ 5284.449929] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [MODE:1920x1080] for CRTC state 00000000c85dec7a
>[ 5284.449944] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 00000000b7de9afe to [CRTC:37:pipe A]
>[ 5284.449960] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:115] for plane state 00000000b7de9afe
>[ 5284.449977] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:37:pipe A] to 00000000ae57c542
>[ 5284.449995] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:61:DP-2] 000000009f87d14d state to 00000000ae57c542
>[ 5284.450011] [drm:drm_atomic_set_crtc_for_connector [drm]] Link connector state 000000009f87d14d to [NOCRTC]
>[ 5284.450027] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:56:DP-1] 00000000b07225ab state to 00000000ae57c542
>[ 5284.450043] [drm:drm_atomic_set_crtc_for_connector [drm]] Link connector state 00000000b07225ab to [CRTC:37:pipe A]
>[ 5284.450060] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:47:pipe B] 000000002b48c403 state to 00000000ae57c542
>[ 5284.450077] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [MODE:1920x1200] for CRTC state 000000002b48c403
>[ 5284.450093] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 000000005eb15537 to [CRTC:47:pipe B]
>[ 5284.450108] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:115] for plane state 000000005eb15537
>[ 5284.450125] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:47:pipe B] to 00000000ae57c542
>[ 5284.450142] [drm:drm_atomic_set_crtc_for_connector [drm]] Link connector state 000000009f87d14d to [CRTC:47:pipe B]
>[ 5284.450157] [drm:drm_atomic_check_only [drm]] checking 00000000ae57c542
>[ 5284.450172] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:37:pipe A] mode changed
>[ 5284.450183] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:47:pipe B] mode changed
>[ 5284.450192] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:47:pipe B] enable changed
>[ 5284.450201] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:47:pipe B] active changed
>[ 5284.450213] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:56:DP-1]
>[ 5284.450223] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:56:DP-1] using [ENCODER:55:DDI B] on [CRTC:37:pipe A]
>[ 5284.450232] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:61:DP-2]
>[ 5284.450242] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:61:DP-2] keeps [ENCODER:60:DDI C], now on [CRTC:47:pipe B]
>[ 5284.450251] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:37:pipe A] needs all connectors, enable: y, active: y
>[ 5284.450269] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:37:pipe A] to 00000000ae57c542
>[ 5284.450280] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:47:pipe B] needs all connectors, enable: y, active: y
>[ 5284.450297] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:47:pipe B] to 00000000ae57c542
>[ 5284.450316] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:37:pipe A] to 00000000ae57c542
>[ 5284.450385] [drm:intel_atomic_check [i915]] [CONNECTOR:56:DP-1] checking for sink bpp constrains
>[ 5284.450451] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 148500KHz
>[ 5284.450527] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 4 clock 270000 bpp 36
>[ 5284.450582] [drm:intel_dp_compute_config [i915]] DP link bw required 668250 available 1080000
>[ 5284.450643] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 36, dithering: 0
>[ 5284.450702] [drm:intel_dump_pipe_config [i915]] [CRTC:37:pipe A][modeset]
>[ 5284.450757] [drm:intel_dump_pipe_config [i915]] output_types: DP (0x80)
>[ 5284.450809] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 36, dithering: 0
>[ 5284.450861] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5190451, gmch_n: 8388608, link_m: 288358, link_n: 524288, tu: 64
>[ 5284.450911] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[ 5284.450958] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 5284.450985] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x9
>[ 5284.451034] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 5284.451060] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x9
>[ 5284.451111] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x9
>[ 5284.451160] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500
>[ 5284.451207] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[ 5284.451253] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 5284.451298] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 5284.451345] [drm:intel_dump_pipe_config [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[ 5284.451389] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 5284.451437] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 1A] FB:115, fb = 1920x1200 format = XR24 little-endian (0x34325258)
>[ 5284.451483] [drm:intel_dump_pipe_config [i915]] 	scaler:-1 src 0x0+1920+1200 dst 0x0+1920+1200
>[ 5284.451528] [drm:intel_dump_pipe_config [i915]] [PLANE:31:plane 2A] disabled, scaler_id = -1
>[ 5284.451573] [drm:intel_dump_pipe_config [i915]] [PLANE:34:cursor A] disabled, scaler_id = -1
>[ 5284.451600] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:47:pipe B] to 00000000ae57c542
>[ 5284.451656] [drm:intel_atomic_check [i915]] [CONNECTOR:61:DP-2] checking for sink bpp constrains
>[ 5284.451709] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[ 5284.451766] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[ 5284.451834] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[ 5284.451884] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[ 5284.451938] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[ 5284.451992] [drm:intel_dump_pipe_config [i915]] [CRTC:47:pipe B][modeset]
>[ 5284.452042] [drm:intel_dump_pipe_config [i915]] output_types: DP (0x80)
>[ 5284.452090] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[ 5284.452137] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[ 5284.452183] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[ 5284.452229] [drm:intel_dump_pipe_config [i915]] requested mode:
>[ 5284.452254] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[ 5284.452301] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[ 5284.452326] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[ 5284.452375] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[ 5284.452420] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[ 5284.452465] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[ 5284.452510] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[ 5284.452554] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[ 5284.452597] [drm:intel_dump_pipe_config [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[ 5284.452640] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[ 5284.452684] [drm:intel_dump_pipe_config [i915]] [PLANE:38:plane 1B] disabled, scaler_id = -1
>[ 5284.452728] [drm:intel_dump_pipe_config [i915]] [PLANE:41:plane 2B] disabled, scaler_id = -1
>[ 5284.452772] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor B] disabled, scaler_id = -1
>[ 5284.452829] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[ 5284.452881] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[ 5284.452940] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:37:pipe A] has [PLANE:28:plane 1A] with fb 115
>[ 5284.452992] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 1, on 1, ms 1
>[ 5284.453044] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:47:pipe B] has [PLANE:38:plane 1B] with fb 115
>[ 5284.453093] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:38:plane 1B] visible 0 -> 1, off 0, on 1, ms 1
>[ 5284.453187] [drm:intel_find_shared_dpll [i915]] [CRTC:37:pipe A] allocated DPLL 1
>[ 5284.453257] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[ 5284.453323] [drm:intel_find_shared_dpll [i915]] [CRTC:47:pipe B] allocated DPLL 2
>[ 5284.453382] [drm:intel_reference_shared_dpll [i915]] using DPLL 2 for pipe B
>[ 5284.453443] [drm:skl_compute_wm [i915]] [PLANE:28:plane 1A] ddb (0 - 860) -> (0 - 438)
>[ 5284.453493] [drm:skl_compute_wm [i915]] [PLANE:34:cursor A] ddb (860 - 892) -> (438 - 446)
>[ 5284.453544] [drm:skl_compute_wm [i915]] [PLANE:38:plane 1B] ddb (0 - 0) -> (446 - 884)
>[ 5284.453593] [drm:skl_compute_wm [i915]] [PLANE:44:cursor B] ddb (0 - 0) -> (884 - 892)
>[ 5284.453630] [drm:drm_atomic_commit [drm]] committing 00000000ae57c542
>[ 5284.453728] [drm:intel_disable_pipe [i915]] disabling pipe A
>[ 5284.461879] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well
>[ 5284.461952] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[ 5284.462016] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 37
>[ 5284.462073] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[ 5284.462125] [drm:intel_disable_sagv [i915]] Disabling the SAGV
>[ 5284.462193] [drm:intel_atomic_commit_tail [i915]] [ENCODER:48:DDI A]
>[ 5284.462249] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI B]
>[ 5284.462301] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[ 5284.462352] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[ 5284.462401] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DDI C]
>[ 5284.462450] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST A]
>[ 5284.462497] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST B]
>[ 5284.462544] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI D]
>[ 5284.462590] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[ 5284.462636] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[ 5284.462688] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[ 5284.462740] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[ 5284.462790] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[ 5284.462840] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[ 5284.462899] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 37
>[ 5284.462952] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[ 5284.463090] [drm:intel_power_well_enable [i915]] enabling DDI B IO power well
>[ 5284.463683] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5284.464938] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5284.466132] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5284.467388] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5284.468650] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[ 5284.469475] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[ 5284.470457] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 5284.470515] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 5284.470567] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 5284.470617] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 5284.489530] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 5284.489594] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[ 5284.508274] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 5284.508616] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:56:DP-1] Link Training Passed at Link Rate = 270000, Lane count = 4
>[ 5284.509029] [drm:intel_enable_pipe [i915]] enabling pipe A
>[ 5284.509059] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS
>[ 5284.509095] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:56:DP-1], [ENCODER:55:DDI B]
>[ 5284.509119] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[ 5284.509152] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[ 5284.509194] [drm:intel_fbc_enable [i915]] reserved 8294400 bytes of contiguous stolen space for FBC, threshold: 1
>[ 5284.509219] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[ 5284.525931] [drm:intel_enable_shared_dpll [i915]] enable DPLL 2 (active 2, on? 0) for crtc 47
>[ 5284.525955] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 2
>[ 5284.526053] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well
>[ 5284.527092] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[ 5284.527112] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[ 5284.527130] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[ 5284.527149] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[ 5284.527733] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[ 5284.527751] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[ 5284.528634] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[ 5284.528963] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:61:DP-2] Link Training Passed at Link Rate = 162000, Lane count = 4
>[ 5284.529392] [drm:intel_enable_pipe [i915]] enabling pipe B
>[ 5284.529417] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS
>[ 5284.546304] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:56:DP-1]
>[ 5284.546382] [drm:intel_atomic_commit_tail [i915]] [CRTC:37:pipe A]
>[ 5284.546466] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[ 5284.546543] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:61:DP-2]
>[ 5284.546605] [drm:intel_atomic_commit_tail [i915]] [CRTC:47:pipe B]
>[ 5284.546678] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[ 5284.546726] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000ae57c542
>[ 5284.546756] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000ae57c542
>[ 5287.417472] [drm:edp_panel_vdd_off_sync [i915]] Turning eDP port A VDD off
>[ 5287.417777] [drm:edp_panel_vdd_off_sync [i915]] PP_STATUS: 0x00000000 PP_CONTROL: 0x00000060
>[ 5287.425534] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010
>[ 5287.425616] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[ 5287.425687] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0
>[ 5287.425823] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[13242.608779] [IGT] kms_flip: executing
>[13242.653039] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:49:eDP-1]
>[13242.653087] [drm:intel_dp_detect [i915]] [CONNECTOR:49:eDP-1]
>[13242.653129] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>[13242.653161] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[13242.653193] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[13242.653281] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[13242.653364] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle
>[13242.653624] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 00000000 control 00000060
>[13242.653709] [drm:wait_panel_status [i915]] Wait complete
>[13242.653966] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x00000000 PP_CONTROL: 0x00000068
>[13242.654049] [drm:edp_panel_vdd_on [i915]] eDP port A panel power wasn't enabled
>[13242.756084] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010
>[13242.756157] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[13242.756221] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0
>[13242.756338] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[13242.861679] [drm:drm_dp_read_desc [drm_kms_helper]] DP sink: OUI 00-1c-f8 dev-ID q\006UA\022\001 HW-rev 10.0 SW-rev 1.41 quirks 0x0000
>[13242.862868] [drm:drm_add_display_info [drm]] non_desktop set to 0
>[13242.862902] [drm:drm_add_edid_modes [drm]] ELD: no CEA Extension found
>[13242.862926] [drm:drm_add_display_info [drm]] non_desktop set to 0
>[13242.862972] [drm:drm_mode_debug_printmodeline [drm]] Modeline 72:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa
>[13242.862992] [drm:drm_mode_prune_invalid [drm]] Not using 1920x1080 mode: CLOCK_HIGH
>[13242.863033] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:56:DP-1]
>[13242.863115] [drm:intel_dp_detect [i915]] [CONNECTOR:56:DP-1]
>[13242.863543] [drm:lspcon_wake_native_aux_ch [i915]] Native AUX CH up, DPCD version: 1.2
>[13242.863661] [drm:lspcon_resume [i915]] LSPCON recovering in PCON mode after 0 ms
>[13242.864102] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13242.865399] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13242.866667] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13242.867932] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13242.869225] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13242.870119] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[13242.870594] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 00 00 04 00 0f 00 04
>[13242.871368] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>[13242.871421] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000
>[13242.871471] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000
>[13242.871872] [drm:drm_dp_read_desc [drm_kms_helper]] DP branch: OUI 00-60-ad dev-ID MC2800 HW-rev 2.2 SW-rev 1.72 quirks 0x0000
>[13242.872222] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[13242.873001] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13242.874241] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13242.875508] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13242.876785] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13242.878074] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13242.879328] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13242.880600] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13242.881875] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13242.883137] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13242.884537] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13242.885935] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13242.887329] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13242.888740] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13242.890148] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13242.891541] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13242.892942] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13242.894328] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13242.895585] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13242.896867] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13242.898137] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13242.899398] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13242.900805] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13242.902218] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13242.903612] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13242.905012] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13242.906408] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13242.907808] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13242.909225] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13242.910609] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13242.911455] [drm:drm_detect_monitor_audio [drm]] Monitor has basic audio support
>[13242.911781] [drm:drm_add_display_info [drm]] non_desktop set to 0
>[13242.911802] [drm:drm_add_display_info [drm]] HDMI: DVI dual 0, max TMDS clock 225000 kHz
>[13242.911828] [drm:drm_add_edid_modes [drm]] ELD monitor BOBCAT2800
>[13242.911847] [drm:drm_add_edid_modes [drm]] HDMI: latency present 0 0, video latency 0 0, audio latency 0 0
>[13242.911862] [drm:drm_add_edid_modes [drm]] ELD size 36, SAD count 1
>[13242.911878] [drm:drm_add_display_info [drm]] non_desktop set to 0
>[13242.911893] [drm:drm_add_display_info [drm]] HDMI: DVI dual 0, max TMDS clock 225000 kHz
>[13242.912358] [drm:drm_mode_debug_printmodeline [drm]] Modeline 139:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[13242.912377] [drm:drm_mode_prune_invalid [drm]] Not using 720x480i mode: H_ILLEGAL
>[13242.912395] [drm:drm_mode_debug_printmodeline [drm]] Modeline 140:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[13242.912411] [drm:drm_mode_prune_invalid [drm]] Not using 720x576i mode: H_ILLEGAL
>[13242.912428] [drm:drm_mode_debug_printmodeline [drm]] Modeline 160:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[13242.912443] [drm:drm_mode_prune_invalid [drm]] Not using 720x480i mode: H_ILLEGAL
>[13242.912461] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:56:DP-1] probed modes :
>[13242.912480] [drm:drm_mode_debug_printmodeline [drm]] Modeline 74:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x9
>[13242.912497] [drm:drm_mode_debug_printmodeline [drm]] Modeline 81:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x40 0x9
>[13242.912513] [drm:drm_mode_debug_printmodeline [drm]] Modeline 75:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[13242.912529] [drm:drm_mode_debug_printmodeline [drm]] Modeline 120:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[13242.912546] [drm:drm_mode_debug_printmodeline [drm]] Modeline 76:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[13242.912562] [drm:drm_mode_debug_printmodeline [drm]] Modeline 121:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[13242.912578] [drm:drm_mode_debug_printmodeline [drm]] Modeline 109:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[13242.912594] [drm:drm_mode_debug_printmodeline [drm]] Modeline 114:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[13242.912610] [drm:drm_mode_debug_printmodeline [drm]] Modeline 116:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[13242.912626] [drm:drm_mode_debug_printmodeline [drm]] Modeline 132:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[13242.912642] [drm:drm_mode_debug_printmodeline [drm]] Modeline 80:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[13242.912659] [drm:drm_mode_debug_printmodeline [drm]] Modeline 87:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[13242.912675] [drm:drm_mode_debug_printmodeline [drm]] Modeline 79:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[13242.912726] [drm:drm_mode_debug_printmodeline [drm]] Modeline 82:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[13242.912742] [drm:drm_mode_debug_printmodeline [drm]] Modeline 77:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[13242.912768] [drm:drm_mode_debug_printmodeline [drm]] Modeline 122:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[13242.912794] [drm:drm_mode_debug_printmodeline [drm]] Modeline 113:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[13242.912817] [drm:drm_mode_debug_printmodeline [drm]] Modeline 88:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[13242.912841] [drm:drm_mode_debug_printmodeline [drm]] Modeline 89:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[13242.912866] [drm:drm_mode_debug_printmodeline [drm]] Modeline 90:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[13242.912889] [drm:drm_mode_debug_printmodeline [drm]] Modeline 83:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[13242.912913] [drm:drm_mode_debug_printmodeline [drm]] Modeline 110:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[13242.912937] [drm:drm_mode_debug_printmodeline [drm]] Modeline 123:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[13242.912961] [drm:drm_mode_debug_printmodeline [drm]] Modeline 78:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[13242.912985] [drm:drm_mode_debug_printmodeline [drm]] Modeline 84:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[13242.913008] [drm:drm_mode_debug_printmodeline [drm]] Modeline 124:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[13242.913032] [drm:drm_mode_debug_printmodeline [drm]] Modeline 85:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[13242.913056] [drm:drm_mode_debug_printmodeline [drm]] Modeline 86:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[13242.913106] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:61:DP-2]
>[13242.913176] [drm:intel_dp_detect [i915]] [CONNECTOR:61:DP-2]
>[13242.913702] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 00 02 02 06 05 00 00 00
>[13242.914047] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>[13242.914104] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[13242.914159] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[13242.914551] [drm:drm_dp_read_desc [drm_kms_helper]] DP sink: OUI 00-00-00 dev-ID  HW-rev 0.0 SW-rev 0.0 quirks 0x0000
>[13242.914606] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[13242.918576] [drm:drm_add_display_info [drm]] non_desktop set to 0
>[13242.918601] [drm:drm_add_edid_modes [drm]] ELD: no CEA Extension found
>[13242.918618] [drm:drm_add_display_info [drm]] non_desktop set to 0
>[13242.918762] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:61:DP-2] probed modes :
>[13242.918782] [drm:drm_mode_debug_printmodeline [drm]] Modeline 91:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[13242.918800] [drm:drm_mode_debug_printmodeline [drm]] Modeline 95:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0xa
>[13242.918816] [drm:drm_mode_debug_printmodeline [drm]] Modeline 103:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[13242.918831] [drm:drm_mode_debug_printmodeline [drm]] Modeline 92:"1680x1050" 60 146250 1680 1784 1960 2240 1050 1053 1059 1089 0x40 0x6
>[13242.918846] [drm:drm_mode_debug_printmodeline [drm]] Modeline 96:"1600x900" 60 108000 1600 1624 1704 1800 900 901 904 1000 0x40 0x5
>[13242.918860] [drm:drm_mode_debug_printmodeline [drm]] Modeline 104:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[13242.918875] [drm:drm_mode_debug_printmodeline [drm]] Modeline 93:"1440x900" 60 106500 1440 1520 1672 1904 900 903 909 934 0x40 0x6
>[13242.918890] [drm:drm_mode_debug_printmodeline [drm]] Modeline 94:"1280x800" 60 83500 1280 1352 1480 1680 800 803 809 831 0x40 0x6
>[13242.918904] [drm:drm_mode_debug_printmodeline [drm]] Modeline 97:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[13242.918919] [drm:drm_mode_debug_printmodeline [drm]] Modeline 112:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[13242.918933] [drm:drm_mode_debug_printmodeline [drm]] Modeline 105:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[13242.918948] [drm:drm_mode_debug_printmodeline [drm]] Modeline 111:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[13242.918974] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:64:HDMI-A-1]
>[13242.919032] [drm:intel_hdmi_detect [i915]] [CONNECTOR:64:HDMI-A-1]
>[13242.919590] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[13242.919639] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[13242.920060] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[13242.920155] [drm:drm_do_probe_ddc_edid [drm]] drm: skipping non-existent adapter i915 gmbus dpc
>[13242.920631] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[13242.920675] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[13242.921090] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[13242.921176] [drm:drm_dp_dual_mode_detect [drm_kms_helper]] DP dual mode HDMI ID:  (err -6)
>[13242.921189] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:64:HDMI-A-1] disconnected
>[13242.921216] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:67:DP-3]
>[13242.921264] [drm:intel_dp_detect [i915]] [CONNECTOR:67:DP-3]
>[13242.921334] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:67:DP-3] disconnected
>[13242.921350] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:70:HDMI-A-2]
>[13242.921397] [drm:intel_hdmi_detect [i915]] [CONNECTOR:70:HDMI-A-2]
>[13242.941876] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0050 w(1)
>[13242.941935] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK on first message, retry
>[13242.962686] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0050 w(1)
>[13242.962790] [drm:drm_do_probe_ddc_edid [drm]] drm: skipping non-existent adapter i915 gmbus dpd
>[13242.983120] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0040 w(1)
>[13242.983181] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK on first message, retry
>[13243.004068] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0040 w(1)
>[13243.004160] [drm:drm_dp_dual_mode_detect [drm_kms_helper]] DP dual mode HDMI ID:  (err -6)
>[13243.004173] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:70:HDMI-A-2] disconnected
>[13243.004413] [IGT] kms_flip: starting subtest blt-wf_vblank-vs-modeset
>[13243.004940] [drm:drm_mode_addfb2 [drm]] [FB:98]
>[13243.004979] [drm:drm_mode_addfb2 [drm]] [FB:101]
>[13243.061488] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[13243.061498] [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000002434bbd
>[13243.061507] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:37:pipe A] 00000000b8d65185 state to 0000000002434bbd
>[13243.061514] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000a8722221 state to 0000000002434bbd
>[13243.061520] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for CRTC state 00000000b8d65185
>[13243.061525] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 00000000a8722221 to [NOCRTC]
>[13243.061530] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for plane state 00000000a8722221
>[13243.061535] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:37:pipe A] to 0000000002434bbd
>[13243.061542] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:56:DP-1] 000000009bdbb67b state to 0000000002434bbd
>[13243.061547] [drm:drm_atomic_set_crtc_for_connector [drm]] Link connector state 000000009bdbb67b to [NOCRTC]
>[13243.061552] [drm:drm_atomic_check_only [drm]] checking 0000000002434bbd
>[13243.061557] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:37:pipe A] mode changed
>[13243.061560] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:37:pipe A] enable changed
>[13243.061563] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:37:pipe A] active changed
>[13243.061566] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:56:DP-1]
>[13243.061568] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Disabling [CONNECTOR:56:DP-1]
>[13243.061571] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:37:pipe A] needs all connectors, enable: n, active: n
>[13243.061577] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:37:pipe A] to 0000000002434bbd
>[13243.061602] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[13243.061621] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[13243.061640] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:37:pipe A] has [PLANE:28:plane 1A] with fb -1
>[13243.061657] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 0, off 1, on 0, ms 1
>[13243.061666] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:47:pipe B] 00000000bd3c0152 state to 0000000002434bbd
>[13243.061673] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:38:plane 1B] 00000000feda2dba state to 0000000002434bbd
>[13243.061688] [drm:skl_compute_wm [i915]] [PLANE:28:plane 1A] ddb (0 - 438) -> (0 - 0)
>[13243.061701] [drm:skl_compute_wm [i915]] [PLANE:34:cursor A] ddb (438 - 446) -> (0 - 0)
>[13243.061713] [drm:skl_compute_wm [i915]] [PLANE:38:plane 1B] ddb (446 - 884) -> (0 - 860)
>[13243.061725] [drm:skl_compute_wm [i915]] [PLANE:44:cursor B] ddb (884 - 892) -> (860 - 892)
>[13243.061731] [drm:drm_atomic_commit [drm]] committing 0000000002434bbd
>[13243.061762] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[13243.061780] [drm:i915_audio_component_get_eld [i915]] Not valid for port B
>[13243.061807] [drm:intel_disable_pipe [i915]] disabling pipe A
>[13243.070563] [drm:intel_power_well_disable [i915]] disabling DDI B IO power well
>[13243.070580] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[13243.070594] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 37
>[13243.070607] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[13243.070630] [drm:intel_atomic_commit_tail [i915]] [ENCODER:48:DDI A]
>[13243.070642] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI B]
>[13243.070654] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[13243.070666] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[13243.070676] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DDI C]
>[13243.070687] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST A]
>[13243.070697] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST B]
>[13243.070708] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI D]
>[13243.070718] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[13243.070728] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[13243.070739] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:56:DP-1]
>[13243.070751] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[13243.070762] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[13243.070773] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[13243.070784] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[13243.074021] [drm:intel_atomic_commit_tail [i915]] [CRTC:37:pipe A]
>[13243.074038] [drm:intel_enable_sagv [i915]] Enabling the SAGV
>[13243.074051] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000002434bbd
>[13243.074058] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000002434bbd
>[13243.074069] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[13243.074074] [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000002434bbd
>[13243.074080] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:47:pipe B] 000000002b48c403 state to 0000000002434bbd
>[13243.074085] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:38:plane 1B] 00000000e4c2821e state to 0000000002434bbd
>[13243.074090] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for CRTC state 000000002b48c403
>[13243.074094] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 00000000e4c2821e to [NOCRTC]
>[13243.074098] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for plane state 00000000e4c2821e
>[13243.074101] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:47:pipe B] to 0000000002434bbd
>[13243.074107] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:61:DP-2] 000000006f8e13bc state to 0000000002434bbd
>[13243.074111] [drm:drm_atomic_set_crtc_for_connector [drm]] Link connector state 000000006f8e13bc to [NOCRTC]
>[13243.074115] [drm:drm_atomic_check_only [drm]] checking 0000000002434bbd
>[13243.074120] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:47:pipe B] mode changed
>[13243.074122] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:47:pipe B] enable changed
>[13243.074124] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:47:pipe B] active changed
>[13243.074127] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:61:DP-2]
>[13243.074129] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Disabling [CONNECTOR:61:DP-2]
>[13243.074131] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:47:pipe B] needs all connectors, enable: n, active: n
>[13243.074135] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:47:pipe B] to 0000000002434bbd
>[13243.074154] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[13243.074168] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[13243.074183] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:47:pipe B] has [PLANE:38:plane 1B] with fb -1
>[13243.074197] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:38:plane 1B] visible 1 -> 0, off 1, on 0, ms 1
>[13243.074203] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:37:pipe A] 00000000c85dec7a state to 0000000002434bbd
>[13243.074215] [drm:skl_compute_wm [i915]] [PLANE:38:plane 1B] ddb (0 - 860) -> (0 - 0)
>[13243.074225] [drm:skl_compute_wm [i915]] [PLANE:44:cursor B] ddb (860 - 892) -> (0 - 0)
>[13243.074230] [drm:drm_atomic_commit [drm]] committing 0000000002434bbd
>[13243.074257] [drm:intel_disable_pipe [i915]] disabling pipe B
>[13243.091071] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well
>[13243.091088] [drm:intel_disable_shared_dpll [i915]] disable DPLL 2 (active 2, on? 1) for crtc 47
>[13243.091103] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 2
>[13243.091125] [drm:intel_atomic_commit_tail [i915]] [ENCODER:48:DDI A]
>[13243.091137] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI B]
>[13243.091149] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[13243.091159] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[13243.091170] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DDI C]
>[13243.091181] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST A]
>[13243.091191] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST B]
>[13243.091201] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI D]
>[13243.091211] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[13243.091221] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[13243.091233] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:61:DP-2]
>[13243.091245] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[13243.091256] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[13243.091268] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[13243.091278] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[13243.091291] [drm:intel_power_well_disable [i915]] disabling power well 2
>[13243.091306] [drm:intel_atomic_commit_tail [i915]] [CRTC:47:pipe B]
>[13243.091317] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000002434bbd
>[13243.091323] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000002434bbd
>[13243.091335] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[13243.091342] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:56:DP-1]
>[13243.091347] [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000002434bbd
>[13243.091353] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:37:pipe A] 00000000bd3c0152 state to 0000000002434bbd
>[13243.091358] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000dbafe848 state to 0000000002434bbd
>[13243.091363] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [MODE:1920x1080] for CRTC state 00000000bd3c0152
>[13243.091368] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 00000000dbafe848 to [CRTC:37:pipe A]
>[13243.091372] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:98] for plane state 00000000dbafe848
>[13243.091376] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:37:pipe A] to 0000000002434bbd
>[13243.091381] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:56:DP-1] 00000000f8eadac6 state to 0000000002434bbd
>[13243.091385] [drm:drm_atomic_set_crtc_for_connector [drm]] Link connector state 00000000f8eadac6 to [CRTC:37:pipe A]
>[13243.091390] [drm:drm_atomic_check_only [drm]] checking 0000000002434bbd
>[13243.091394] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:37:pipe A] mode changed
>[13243.091396] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:37:pipe A] enable changed
>[13243.091398] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:37:pipe A] active changed
>[13243.091401] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:56:DP-1]
>[13243.091403] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:56:DP-1] using [ENCODER:55:DDI B] on [CRTC:37:pipe A]
>[13243.091405] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:37:pipe A] needs all connectors, enable: y, active: y
>[13243.091410] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:37:pipe A] to 0000000002434bbd
>[13243.091415] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:37:pipe A] to 0000000002434bbd
>[13243.091430] [drm:intel_atomic_check [i915]] [CONNECTOR:56:DP-1] checking for sink bpp constrains
>[13243.091444] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 148500KHz
>[13243.091461] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 4 clock 270000 bpp 36
>[13243.091473] [drm:intel_dp_compute_config [i915]] DP link bw required 668250 available 1080000
>[13243.091486] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 36, dithering: 0
>[13243.091499] [drm:intel_dump_pipe_config [i915]] [CRTC:37:pipe A][modeset]
>[13243.091511] [drm:intel_dump_pipe_config [i915]] output_types: DP (0x80)
>[13243.091523] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 36, dithering: 0
>[13243.091534] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5190451, gmch_n: 8388608, link_m: 288358, link_n: 524288, tu: 64
>[13243.091545] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[13243.091555] [drm:intel_dump_pipe_config [i915]] requested mode:
>[13243.091562] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x9
>[13243.091572] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[13243.091578] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x9
>[13243.091589] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x9
>[13243.091600] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500
>[13243.091610] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[13243.091620] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[13243.091631] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[13243.091641] [drm:intel_dump_pipe_config [i915]] dpll_hw_state: ctrl1: 0x3, cfgcr1: 0x0, cfgcr2: 0x0
>[13243.091651] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[13243.091661] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 1A] disabled, scaler_id = -1
>[13243.091671] [drm:intel_dump_pipe_config [i915]] [PLANE:31:plane 2A] disabled, scaler_id = -1
>[13243.091681] [drm:intel_dump_pipe_config [i915]] [PLANE:34:cursor A] disabled, scaler_id = -1
>[13243.091694] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[13243.091705] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[13243.091719] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:37:pipe A] has [PLANE:28:plane 1A] with fb 98
>[13243.091731] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 0 -> 1, off 0, on 1, ms 1
>[13243.091744] [drm:intel_find_shared_dpll [i915]] [CRTC:37:pipe A] allocated DPLL 1
>[13243.091755] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[13243.091763] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:47:pipe B] 00000000b8d65185 state to 0000000002434bbd
>[13243.091774] [drm:skl_compute_wm [i915]] [PLANE:28:plane 1A] ddb (0 - 0) -> (0 - 860)
>[13243.091783] [drm:skl_compute_wm [i915]] [PLANE:34:cursor A] ddb (0 - 0) -> (860 - 892)
>[13243.091788] [drm:drm_atomic_commit [drm]] committing 0000000002434bbd
>[13243.092180] [drm:intel_power_well_enable [i915]] enabling power well 2
>[13243.092198] [drm:intel_atomic_commit_tail [i915]] [ENCODER:48:DDI A]
>[13243.092209] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI B]
>[13243.092220] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[13243.092231] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[13243.092241] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DDI C]
>[13243.092251] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST A]
>[13243.092261] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST B]
>[13243.092271] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI D]
>[13243.092281] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[13243.092291] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[13243.092302] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[13243.092314] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[13243.092325] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[13243.092336] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[13243.092349] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 37
>[13243.092361] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[13243.092446] [drm:intel_power_well_enable [i915]] enabling DDI B IO power well
>[13243.093006] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13243.094282] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13243.095449] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13243.096722] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13243.098002] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13243.098865] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[13243.099768] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[13243.099781] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[13243.099792] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[13243.099805] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[13243.118410] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[13243.118424] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[13243.136244] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[13243.136566] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:56:DP-1] Link Training Passed at Link Rate = 270000, Lane count = 4
>[13243.136925] [drm:intel_enable_pipe [i915]] enabling pipe A
>[13243.136956] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS
>[13243.136969] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:56:DP-1], [ENCODER:55:DDI B]
>[13243.136980] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[13243.136993] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[13243.137014] [drm:intel_fbc_enable [i915]] reserved 8294400 bytes of contiguous stolen space for FBC, threshold: 1
>[13243.137026] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[13243.153904] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:56:DP-1]
>[13243.153921] [drm:intel_atomic_commit_tail [i915]] [CRTC:37:pipe A]
>[13243.153944] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[13243.153956] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000002434bbd
>[13243.153963] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000002434bbd
>[13243.153978] [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000002434bbd
>[13243.153983] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:37:pipe A] 000000002b48c403 state to 0000000002434bbd
>[13243.153988] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000feda2dba state to 0000000002434bbd
>[13243.153992] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 00000000feda2dba to [CRTC:37:pipe A]
>[13243.153996] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:101] for plane state 00000000feda2dba
>[13243.154000] [drm:drm_atomic_check_only [drm]] checking 0000000002434bbd
>[13243.154018] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:37:pipe A] has [PLANE:28:plane 1A] with fb 101
>[13243.154031] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>[13243.154039] [drm:drm_atomic_nonblocking_commit [drm]] committing 0000000002434bbd nonblocking
>[13243.170546] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000002434bbd
>[13243.170554] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000002434bbd
>[13243.171017] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[13243.171025] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:56:DP-1]
>[13243.171032] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000004cdc04ee
>[13243.171039] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:37:pipe A] 00000000195b8dec state to 000000004cdc04ee
>[13243.171045] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000f9695a62 state to 000000004cdc04ee
>[13243.171050] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [MODE:1920x1080] for CRTC state 00000000195b8dec
>[13243.171054] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 00000000f9695a62 to [CRTC:37:pipe A]
>[13243.171059] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:98] for plane state 00000000f9695a62
>[13243.171063] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:37:pipe A] to 000000004cdc04ee
>[13243.171068] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:56:DP-1] 00000000cbb38251 state to 000000004cdc04ee
>[13243.171072] [drm:drm_atomic_set_crtc_for_connector [drm]] Link connector state 00000000cbb38251 to [NOCRTC]
>[13243.171076] [drm:drm_atomic_set_crtc_for_connector [drm]] Link connector state 00000000cbb38251 to [CRTC:37:pipe A]
>[13243.171081] [drm:drm_atomic_check_only [drm]] checking 000000004cdc04ee
>[13243.171087] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:56:DP-1]
>[13243.171090] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:56:DP-1] keeps [ENCODER:55:DDI B], now on [CRTC:37:pipe A]
>[13243.171114] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:37:pipe A] has [PLANE:28:plane 1A] with fb 98
>[13243.171129] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>[13243.171137] [drm:drm_atomic_commit [drm]] committing 000000004cdc04ee
>[13244.187033] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000004cdc04ee
>[13244.187063] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000004cdc04ee
>[13244.187133] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[13244.187158] [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000002434bbd
>[13244.187183] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:37:pipe A] 000000002b48c403 state to 0000000002434bbd
>[13244.187204] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000feda2dba state to 0000000002434bbd
>[13244.187225] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for CRTC state 000000002b48c403
>[13244.187244] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 00000000feda2dba to [NOCRTC]
>[13244.187262] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for plane state 00000000feda2dba
>[13244.187280] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:37:pipe A] to 0000000002434bbd
>[13244.187299] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:56:DP-1] 00000000d1e5643f state to 0000000002434bbd
>[13244.187317] [drm:drm_atomic_set_crtc_for_connector [drm]] Link connector state 00000000d1e5643f to [NOCRTC]
>[13244.187334] [drm:drm_atomic_check_only [drm]] checking 0000000002434bbd
>[13244.187350] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:37:pipe A] mode changed
>[13244.187361] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:37:pipe A] enable changed
>[13244.187370] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:37:pipe A] active changed
>[13244.187380] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:56:DP-1]
>[13244.187389] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Disabling [CONNECTOR:56:DP-1]
>[13244.187399] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:37:pipe A] needs all connectors, enable: n, active: n
>[13244.187418] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:37:pipe A] to 0000000002434bbd
>[13244.187498] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[13244.187565] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[13244.187631] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:37:pipe A] has [PLANE:28:plane 1A] with fb -1
>[13244.187692] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 0, off 1, on 0, ms 1
>[13244.187722] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:47:pipe B] 00000000bd3c0152 state to 0000000002434bbd
>[13244.187771] [drm:skl_compute_wm [i915]] [PLANE:28:plane 1A] ddb (0 - 860) -> (0 - 0)
>[13244.187817] [drm:skl_compute_wm [i915]] [PLANE:34:cursor A] ddb (860 - 892) -> (0 - 0)
>[13244.187841] [drm:drm_atomic_commit [drm]] committing 0000000002434bbd
>[13244.187932] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[13244.187994] [drm:i915_audio_component_get_eld [i915]] Not valid for port B
>[13244.188073] [drm:intel_disable_pipe [i915]] disabling pipe A
>[13244.204058] [drm:intel_power_well_disable [i915]] disabling DDI B IO power well
>[13244.204129] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[13244.204194] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 37
>[13244.204249] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[13244.204320] [drm:intel_atomic_commit_tail [i915]] [ENCODER:48:DDI A]
>[13244.204375] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI B]
>[13244.204427] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[13244.204477] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[13244.204524] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DDI C]
>[13244.204571] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST A]
>[13244.204616] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST B]
>[13244.204661] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI D]
>[13244.204706] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[13244.204780] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[13244.204843] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:56:DP-1]
>[13244.204905] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[13244.204963] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[13244.205019] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[13244.205074] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[13244.205128] [drm:intel_power_well_disable [i915]] disabling power well 2
>[13244.205189] [drm:intel_atomic_commit_tail [i915]] [CRTC:37:pipe A]
>[13244.205228] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000002434bbd
>[13244.205256] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000002434bbd
>[13244.205492] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[13244.205518] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:56:DP-1]
>[13244.205542] [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000002434bbd
>[13244.205568] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:37:pipe A] 00000000b8d65185 state to 0000000002434bbd
>[13244.205592] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000a8722221 state to 0000000002434bbd
>[13244.205614] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [MODE:1920x1080] for CRTC state 00000000b8d65185
>[13244.205633] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 00000000a8722221 to [CRTC:37:pipe A]
>[13244.205653] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:101] for plane state 00000000a8722221
>[13244.205671] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:37:pipe A] to 0000000002434bbd
>[13244.205690] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:56:DP-1] 00000000f8eadac6 state to 0000000002434bbd
>[13244.205708] [drm:drm_atomic_set_crtc_for_connector [drm]] Link connector state 00000000f8eadac6 to [CRTC:37:pipe A]
>[13244.205726] [drm:drm_atomic_check_only [drm]] checking 0000000002434bbd
>[13244.205741] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:37:pipe A] mode changed
>[13244.205753] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:37:pipe A] enable changed
>[13244.205762] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:37:pipe A] active changed
>[13244.205773] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:56:DP-1]
>[13244.205783] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:56:DP-1] using [ENCODER:55:DDI B] on [CRTC:37:pipe A]
>[13244.205794] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:37:pipe A] needs all connectors, enable: y, active: y
>[13244.205812] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:37:pipe A] to 0000000002434bbd
>[13244.205833] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:37:pipe A] to 0000000002434bbd
>[13244.205898] [drm:intel_atomic_check [i915]] [CONNECTOR:56:DP-1] checking for sink bpp constrains
>[13244.205963] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 148500KHz
>[13244.206038] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 4 clock 270000 bpp 36
>[13244.206092] [drm:intel_dp_compute_config [i915]] DP link bw required 668250 available 1080000
>[13244.206151] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 36, dithering: 0
>[13244.206209] [drm:intel_dump_pipe_config [i915]] [CRTC:37:pipe A][modeset]
>[13244.206264] [drm:intel_dump_pipe_config [i915]] output_types: DP (0x80)
>[13244.206315] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 36, dithering: 0
>[13244.206367] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5190451, gmch_n: 8388608, link_m: 288358, link_n: 524288, tu: 64
>[13244.206416] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[13244.206464] [drm:intel_dump_pipe_config [i915]] requested mode:
>[13244.206492] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x9
>[13244.206542] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[13244.206567] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x9
>[13244.206618] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x9
>[13244.206667] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500
>[13244.206715] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[13244.206762] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[13244.206809] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[13244.206855] [drm:intel_dump_pipe_config [i915]] dpll_hw_state: ctrl1: 0x3, cfgcr1: 0x0, cfgcr2: 0x0
>[13244.206900] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[13244.206945] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 1A] disabled, scaler_id = -1
>[13244.206991] [drm:intel_dump_pipe_config [i915]] [PLANE:31:plane 2A] disabled, scaler_id = -1
>[13244.207035] [drm:intel_dump_pipe_config [i915]] [PLANE:34:cursor A] disabled, scaler_id = -1
>[13244.207092] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[13244.207144] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[13244.207201] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:37:pipe A] has [PLANE:28:plane 1A] with fb 101
>[13244.207254] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 0 -> 1, off 0, on 1, ms 1
>[13244.207312] [drm:intel_find_shared_dpll [i915]] [CRTC:37:pipe A] allocated DPLL 1
>[13244.207364] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[13244.207398] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:47:pipe B] 00000000c85dec7a state to 0000000002434bbd
>[13244.207445] [drm:skl_compute_wm [i915]] [PLANE:28:plane 1A] ddb (0 - 0) -> (0 - 860)
>[13244.207487] [drm:skl_compute_wm [i915]] [PLANE:34:cursor A] ddb (0 - 0) -> (860 - 892)
>[13244.207514] [drm:drm_atomic_commit [drm]] committing 0000000002434bbd
>[13244.606922] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040
>[13244.606994] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short
>[13244.607091] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short
>[13244.607150] [drm:intel_power_well_enable [i915]] enabling power well 2
>[13245.205752] [drm:intel_atomic_commit_tail [i915]] [ENCODER:48:DDI A]
>[13245.205819] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI B]
>[13245.205877] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[13245.205931] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[13245.205984] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DDI C]
>[13245.206034] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST A]
>[13245.206084] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST B]
>[13245.206132] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI D]
>[13245.206180] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[13245.206229] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[13245.206285] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[13245.206342] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[13245.206396] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[13245.206449] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[13245.206511] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 37
>[13245.206568] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[13245.206711] [drm:intel_power_well_enable [i915]] enabling DDI B IO power well
>[13245.207306] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13245.208543] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13245.209787] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13245.211015] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13245.212250] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13245.213070] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[13245.214044] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[13245.214100] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[13245.214150] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[13245.214198] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[13245.232844] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[13245.232873] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[13245.251565] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[13245.251740] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:56:DP-1] Link Training Passed at Link Rate = 270000, Lane count = 4
>[13245.252100] [drm:intel_enable_pipe [i915]] enabling pipe A
>[13245.252126] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS
>[13245.252138] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:56:DP-1], [ENCODER:55:DDI B]
>[13245.252150] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[13245.252163] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[13245.252181] [drm:intel_fbc_enable [i915]] reserved 8294400 bytes of contiguous stolen space for FBC, threshold: 1
>[13245.252192] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[13245.268836] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:56:DP-1]
>[13245.268852] [drm:intel_atomic_commit_tail [i915]] [CRTC:37:pipe A]
>[13245.268873] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[13245.268882] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000002434bbd
>[13245.268887] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000002434bbd
>[13245.268902] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[13245.268907] [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000002434bbd
>[13245.268912] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:37:pipe A] 00000000bd3c0152 state to 0000000002434bbd
>[13245.268917] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000dbafe848 state to 0000000002434bbd
>[13245.268921] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for CRTC state 00000000bd3c0152
>[13245.268925] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 00000000dbafe848 to [NOCRTC]
>[13245.268929] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for plane state 00000000dbafe848
>[13245.268933] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:37:pipe A] to 0000000002434bbd
>[13245.268937] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:56:DP-1] 00000000fcc1d3f4 state to 0000000002434bbd
>[13245.268941] [drm:drm_atomic_set_crtc_for_connector [drm]] Link connector state 00000000fcc1d3f4 to [NOCRTC]
>[13245.268945] [drm:drm_atomic_check_only [drm]] checking 0000000002434bbd
>[13245.268948] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:37:pipe A] mode changed
>[13245.268951] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:37:pipe A] enable changed
>[13245.268953] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:37:pipe A] active changed
>[13245.268955] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:56:DP-1]
>[13245.268957] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Disabling [CONNECTOR:56:DP-1]
>[13245.268959] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:37:pipe A] needs all connectors, enable: n, active: n
>[13245.268963] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:37:pipe A] to 0000000002434bbd
>[13245.268979] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[13245.268992] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[13245.269006] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:37:pipe A] has [PLANE:28:plane 1A] with fb -1
>[13245.269018] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 0, off 1, on 0, ms 1
>[13245.269025] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:47:pipe B] 000000002b48c403 state to 0000000002434bbd
>[13245.269035] [drm:skl_compute_wm [i915]] [PLANE:28:plane 1A] ddb (0 - 860) -> (0 - 0)
>[13245.269045] [drm:skl_compute_wm [i915]] [PLANE:34:cursor A] ddb (860 - 892) -> (0 - 0)
>[13245.269050] [drm:drm_atomic_commit [drm]] committing 0000000002434bbd
>[13245.269070] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[13245.269084] [drm:i915_audio_component_get_eld [i915]] Not valid for port B
>[13245.269100] [drm:intel_disable_pipe [i915]] disabling pipe A
>[13245.287570] [drm:intel_power_well_disable [i915]] disabling DDI B IO power well
>[13245.287588] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[13245.287604] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 37
>[13245.287618] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[13245.287639] [drm:intel_atomic_commit_tail [i915]] [ENCODER:48:DDI A]
>[13245.287653] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI B]
>[13245.287666] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[13245.287679] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[13245.287691] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DDI C]
>[13245.287702] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST A]
>[13245.287713] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST B]
>[13245.287725] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI D]
>[13245.287736] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[13245.287747] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[13245.287760] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:56:DP-1]
>[13245.287773] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[13245.287785] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[13245.287798] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[13245.287809] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[13245.287824] [drm:intel_atomic_commit_tail [i915]] [CRTC:37:pipe A]
>[13245.287834] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000002434bbd
>[13245.287840] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000002434bbd
>[13245.287901] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[13245.288263] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 00 02 02 06 03 00 00 00
>[13245.289094] [drm:intel_power_well_disable [i915]] disabling power well 2
>[13245.289101] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:56:DP-1]
>[13245.289108] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000b714ca26
>[13245.289115] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:37:pipe A] 00000000831a44cb state to 00000000b714ca26
>[13245.289120] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000acbdfc95 state to 00000000b714ca26
>[13245.289126] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [MODE:1920x1080] for CRTC state 00000000831a44cb
>[13245.289130] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 00000000acbdfc95 to [CRTC:37:pipe A]
>[13245.289134] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:98] for plane state 00000000acbdfc95
>[13245.289138] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:37:pipe A] to 00000000b714ca26
>[13245.289143] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:56:DP-1] 0000000008d3c0bd state to 00000000b714ca26
>[13245.289147] [drm:drm_atomic_set_crtc_for_connector [drm]] Link connector state 0000000008d3c0bd to [CRTC:37:pipe A]
>[13245.289151] [drm:drm_atomic_check_only [drm]] checking 00000000b714ca26
>[13245.289155] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:37:pipe A] mode changed
>[13245.289157] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:37:pipe A] enable changed
>[13245.289160] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:37:pipe A] active changed
>[13245.289163] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:56:DP-1]
>[13245.289165] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:56:DP-1] using [ENCODER:55:DDI B] on [CRTC:37:pipe A]
>[13245.289167] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:37:pipe A] needs all connectors, enable: y, active: y
>[13245.289172] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:37:pipe A] to 00000000b714ca26
>[13245.289176] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:37:pipe A] to 00000000b714ca26
>[13245.289194] [drm:intel_atomic_check [i915]] [CONNECTOR:56:DP-1] checking for sink bpp constrains
>[13245.289210] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 148500KHz
>[13245.289228] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 4 clock 270000 bpp 36
>[13245.289241] [drm:intel_dp_compute_config [i915]] DP link bw required 668250 available 1080000
>[13245.289256] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 36, dithering: 0
>[13245.289270] [drm:intel_dump_pipe_config [i915]] [CRTC:37:pipe A][modeset]
>[13245.289283] [drm:intel_dump_pipe_config [i915]] output_types: DP (0x80)
>[13245.289296] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 36, dithering: 0
>[13245.289308] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5190451, gmch_n: 8388608, link_m: 288358, link_n: 524288, tu: 64
>[13245.289320] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[13245.289332] [drm:intel_dump_pipe_config [i915]] requested mode:
>[13245.289338] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x9
>[13245.289350] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[13245.289356] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x9
>[13245.289369] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x9
>[13245.289381] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500
>[13245.289392] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[13245.289404] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[13245.289415] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[13245.289426] [drm:intel_dump_pipe_config [i915]] dpll_hw_state: ctrl1: 0x3, cfgcr1: 0x0, cfgcr2: 0x0
>[13245.289437] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[13245.289447] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 1A] disabled, scaler_id = -1
>[13245.289458] [drm:intel_dump_pipe_config [i915]] [PLANE:31:plane 2A] disabled, scaler_id = -1
>[13245.289469] [drm:intel_dump_pipe_config [i915]] [PLANE:34:cursor A] disabled, scaler_id = -1
>[13245.289483] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[13245.289495] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[13245.289509] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:37:pipe A] has [PLANE:28:plane 1A] with fb 98
>[13245.289522] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 0 -> 1, off 0, on 1, ms 1
>[13245.289535] [drm:intel_find_shared_dpll [i915]] [CRTC:37:pipe A] allocated DPLL 1
>[13245.289548] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[13245.289556] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:47:pipe B] 00000000195b8dec state to 00000000b714ca26
>[13245.289568] [drm:skl_compute_wm [i915]] [PLANE:28:plane 1A] ddb (0 - 0) -> (0 - 860)
>[13245.289578] [drm:skl_compute_wm [i915]] [PLANE:34:cursor A] ddb (0 - 0) -> (860 - 892)
>[13245.289584] [drm:drm_atomic_commit [drm]] committing 00000000b714ca26
>[13245.944860] [drm:edp_panel_vdd_off_sync [i915]] Turning eDP port A VDD off
>[13245.945157] [drm:edp_panel_vdd_off_sync [i915]] PP_STATUS: 0x00000000 PP_CONTROL: 0x00000060
>[13245.952413] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010
>[13245.952484] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[13245.952547] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0
>[13245.952637] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[13246.288159] [drm:intel_power_well_enable [i915]] enabling power well 2
>[13246.288243] [drm:intel_atomic_commit_tail [i915]] [ENCODER:48:DDI A]
>[13246.288306] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI B]
>[13246.288363] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[13246.288417] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[13246.288468] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DDI C]
>[13246.288518] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST A]
>[13246.288568] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST B]
>[13246.288617] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI D]
>[13246.288666] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[13246.288715] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[13246.288804] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[13246.288871] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[13246.288934] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[13246.288993] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[13246.289062] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 37
>[13246.289122] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[13246.289266] [drm:intel_power_well_enable [i915]] enabling DDI B IO power well
>[13246.289860] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13246.291060] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13246.292299] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13246.293492] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13246.294729] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13246.295586] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[13246.296558] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[13246.296613] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[13246.296663] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[13246.296713] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[13246.315387] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[13246.315417] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[13246.334131] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[13246.334453] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:56:DP-1] Link Training Passed at Link Rate = 270000, Lane count = 4
>[13246.334814] [drm:intel_enable_pipe [i915]] enabling pipe A
>[13246.334843] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS
>[13246.334855] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:56:DP-1], [ENCODER:55:DDI B]
>[13246.334867] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[13246.334880] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[13246.334897] [drm:intel_fbc_enable [i915]] reserved 8294400 bytes of contiguous stolen space for FBC, threshold: 1
>[13246.334908] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[13246.351828] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:56:DP-1]
>[13246.351845] [drm:intel_atomic_commit_tail [i915]] [CRTC:37:pipe A]
>[13246.351868] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[13246.351880] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000b714ca26
>[13246.351886] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000b714ca26
>[13246.351916] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[13246.351922] [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000002434bbd
>[13246.351927] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:37:pipe A] 000000002b48c403 state to 0000000002434bbd
>[13246.351932] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000dbafe848 state to 0000000002434bbd
>[13246.351937] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for CRTC state 000000002b48c403
>[13246.351941] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 00000000dbafe848 to [NOCRTC]
>[13246.351944] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for plane state 00000000dbafe848
>[13246.351948] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:37:pipe A] to 0000000002434bbd
>[13246.351953] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:56:DP-1] 00000000d1e5643f state to 0000000002434bbd
>[13246.351957] [drm:drm_atomic_set_crtc_for_connector [drm]] Link connector state 00000000d1e5643f to [NOCRTC]
>[13246.351961] [drm:drm_atomic_check_only [drm]] checking 0000000002434bbd
>[13246.351966] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:37:pipe A] mode changed
>[13246.351968] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:37:pipe A] enable changed
>[13246.351970] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:37:pipe A] active changed
>[13246.351972] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:56:DP-1]
>[13246.351974] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Disabling [CONNECTOR:56:DP-1]
>[13246.351977] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:37:pipe A] needs all connectors, enable: n, active: n
>[13246.351981] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:37:pipe A] to 0000000002434bbd
>[13246.351998] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[13246.352011] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[13246.352026] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:37:pipe A] has [PLANE:28:plane 1A] with fb -1
>[13246.352039] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 0, off 1, on 0, ms 1
>[13246.352045] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:47:pipe B] 00000000bd3c0152 state to 0000000002434bbd
>[13246.352057] [drm:skl_compute_wm [i915]] [PLANE:28:plane 1A] ddb (0 - 860) -> (0 - 0)
>[13246.352067] [drm:skl_compute_wm [i915]] [PLANE:34:cursor A] ddb (860 - 892) -> (0 - 0)
>[13246.352072] [drm:drm_atomic_commit [drm]] committing 0000000002434bbd
>[13246.352096] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[13246.352110] [drm:i915_audio_component_get_eld [i915]] Not valid for port B
>[13246.352131] [drm:intel_disable_pipe [i915]] disabling pipe A
>[13246.369447] [drm:intel_power_well_disable [i915]] disabling DDI B IO power well
>[13246.369465] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[13246.369480] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 37
>[13246.369493] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[13246.369515] [drm:intel_atomic_commit_tail [i915]] [ENCODER:48:DDI A]
>[13246.369527] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI B]
>[13246.369540] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[13246.369551] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[13246.369563] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DDI C]
>[13246.369573] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST A]
>[13246.369584] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST B]
>[13246.369594] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI D]
>[13246.369605] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[13246.369615] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[13246.369627] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:56:DP-1]
>[13246.369639] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[13246.369651] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[13246.369662] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[13246.369673] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[13246.369685] [drm:intel_power_well_disable [i915]] disabling power well 2
>[13246.369701] [drm:intel_atomic_commit_tail [i915]] [CRTC:37:pipe A]
>[13246.369713] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000002434bbd
>[13246.369720] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000002434bbd
>[13246.369823] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[13246.369830] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:56:DP-1]
>[13246.369835] [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000002434bbd
>[13246.369841] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:37:pipe A] 00000000c85dec7a state to 0000000002434bbd
>[13246.369846] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000feda2dba state to 0000000002434bbd
>[13246.369851] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [MODE:1920x1080] for CRTC state 00000000c85dec7a
>[13246.369856] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 00000000feda2dba to [CRTC:37:pipe A]
>[13246.369860] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:101] for plane state 00000000feda2dba
>[13246.369864] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:37:pipe A] to 0000000002434bbd
>[13246.369869] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:56:DP-1] 00000000fcc1d3f4 state to 0000000002434bbd
>[13246.369872] [drm:drm_atomic_set_crtc_for_connector [drm]] Link connector state 00000000fcc1d3f4 to [CRTC:37:pipe A]
>[13246.369877] [drm:drm_atomic_check_only [drm]] checking 0000000002434bbd
>[13246.369882] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:37:pipe A] mode changed
>[13246.369884] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:37:pipe A] enable changed
>[13246.369886] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:37:pipe A] active changed
>[13246.369889] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:56:DP-1]
>[13246.369891] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:56:DP-1] using [ENCODER:55:DDI B] on [CRTC:37:pipe A]
>[13246.369893] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:37:pipe A] needs all connectors, enable: y, active: y
>[13246.369897] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:37:pipe A] to 0000000002434bbd
>[13246.369902] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:37:pipe A] to 0000000002434bbd
>[13246.369918] [drm:intel_atomic_check [i915]] [CONNECTOR:56:DP-1] checking for sink bpp constrains
>[13246.369932] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 148500KHz
>[13246.369950] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 4 clock 270000 bpp 36
>[13246.369962] [drm:intel_dp_compute_config [i915]] DP link bw required 668250 available 1080000
>[13246.369976] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 36, dithering: 0
>[13246.369989] [drm:intel_dump_pipe_config [i915]] [CRTC:37:pipe A][modeset]
>[13246.370001] [drm:intel_dump_pipe_config [i915]] output_types: DP (0x80)
>[13246.370013] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 36, dithering: 0
>[13246.370024] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5190451, gmch_n: 8388608, link_m: 288358, link_n: 524288, tu: 64
>[13246.370035] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[13246.370046] [drm:intel_dump_pipe_config [i915]] requested mode:
>[13246.370052] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x9
>[13246.370063] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[13246.370069] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x9
>[13246.370080] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x9
>[13246.370091] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500
>[13246.370102] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[13246.370112] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[13246.370123] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[13246.370133] [drm:intel_dump_pipe_config [i915]] dpll_hw_state: ctrl1: 0x3, cfgcr1: 0x0, cfgcr2: 0x0
>[13246.370143] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[13246.370153] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 1A] disabled, scaler_id = -1
>[13246.370164] [drm:intel_dump_pipe_config [i915]] [PLANE:31:plane 2A] disabled, scaler_id = -1
>[13246.370174] [drm:intel_dump_pipe_config [i915]] [PLANE:34:cursor A] disabled, scaler_id = -1
>[13246.370187] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[13246.370198] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[13246.370212] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:37:pipe A] has [PLANE:28:plane 1A] with fb 101
>[13246.370224] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 0 -> 1, off 0, on 1, ms 1
>[13246.370237] [drm:intel_find_shared_dpll [i915]] [CRTC:37:pipe A] allocated DPLL 1
>[13246.370249] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[13246.370257] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:47:pipe B] 00000000b8d65185 state to 0000000002434bbd
>[13246.370268] [drm:skl_compute_wm [i915]] [PLANE:28:plane 1A] ddb (0 - 0) -> (0 - 860)
>[13246.370278] [drm:skl_compute_wm [i915]] [PLANE:34:cursor A] ddb (0 - 0) -> (860 - 892)
>[13246.370283] [drm:drm_atomic_commit [drm]] committing 0000000002434bbd
>[13247.370088] [drm:intel_power_well_enable [i915]] enabling power well 2
>[13247.370172] [drm:intel_atomic_commit_tail [i915]] [ENCODER:48:DDI A]
>[13247.370236] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI B]
>[13247.370292] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[13247.370346] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[13247.370397] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DDI C]
>[13247.370447] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST A]
>[13247.370496] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST B]
>[13247.370545] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI D]
>[13247.370594] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[13247.370642] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[13247.370698] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[13247.370754] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[13247.370809] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[13247.370861] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[13247.370924] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 37
>[13247.370981] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[13247.371122] [drm:intel_power_well_enable [i915]] enabling DDI B IO power well
>[13247.371716] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13247.372961] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13247.374211] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13247.375440] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13247.376677] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13247.377564] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[13247.378539] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[13247.378594] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[13247.378646] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[13247.378696] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[13247.397302] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[13247.397332] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[13247.415155] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[13247.415332] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:56:DP-1] Link Training Passed at Link Rate = 270000, Lane count = 4
>[13247.415693] [drm:intel_enable_pipe [i915]] enabling pipe A
>[13247.415716] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS
>[13247.415728] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:56:DP-1], [ENCODER:55:DDI B]
>[13247.415740] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[13247.415753] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[13247.415773] [drm:intel_fbc_enable [i915]] reserved 8294400 bytes of contiguous stolen space for FBC, threshold: 1
>[13247.415784] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[13247.432491] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:56:DP-1]
>[13247.432507] [drm:intel_atomic_commit_tail [i915]] [CRTC:37:pipe A]
>[13247.432528] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[13247.432537] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000002434bbd
>[13247.432543] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000002434bbd
>[13247.432558] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[13247.432563] [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000002434bbd
>[13247.432568] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:37:pipe A] 00000000bd3c0152 state to 0000000002434bbd
>[13247.432573] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000a8722221 state to 0000000002434bbd
>[13247.432577] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for CRTC state 00000000bd3c0152
>[13247.432581] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 00000000a8722221 to [NOCRTC]
>[13247.432585] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for plane state 00000000a8722221
>[13247.432589] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:37:pipe A] to 0000000002434bbd
>[13247.432593] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:56:DP-1] 00000000de6d4337 state to 0000000002434bbd
>[13247.432597] [drm:drm_atomic_set_crtc_for_connector [drm]] Link connector state 00000000de6d4337 to [NOCRTC]
>[13247.432601] [drm:drm_atomic_check_only [drm]] checking 0000000002434bbd
>[13247.432604] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:37:pipe A] mode changed
>[13247.432606] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:37:pipe A] enable changed
>[13247.432608] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:37:pipe A] active changed
>[13247.432610] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:56:DP-1]
>[13247.432612] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Disabling [CONNECTOR:56:DP-1]
>[13247.432614] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:37:pipe A] needs all connectors, enable: n, active: n
>[13247.432618] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:37:pipe A] to 0000000002434bbd
>[13247.432634] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[13247.432648] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[13247.432662] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:37:pipe A] has [PLANE:28:plane 1A] with fb -1
>[13247.432674] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 0, off 1, on 0, ms 1
>[13247.432688] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:47:pipe B] 000000002b48c403 state to 0000000002434bbd
>[13247.432731] [drm:skl_compute_wm [i915]] [PLANE:28:plane 1A] ddb (0 - 860) -> (0 - 0)
>[13247.432742] [drm:skl_compute_wm [i915]] [PLANE:34:cursor A] ddb (860 - 892) -> (0 - 0)
>[13247.432750] [drm:drm_atomic_commit [drm]] committing 0000000002434bbd
>[13247.432789] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[13247.432804] [drm:i915_audio_component_get_eld [i915]] Not valid for port B
>[13247.432841] [drm:intel_disable_pipe [i915]] disabling pipe A
>[13247.451578] [drm:intel_power_well_disable [i915]] disabling DDI B IO power well
>[13247.451595] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[13247.451611] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 37
>[13247.451624] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[13247.451646] [drm:intel_atomic_commit_tail [i915]] [ENCODER:48:DDI A]
>[13247.451659] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI B]
>[13247.451672] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[13247.451685] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[13247.451697] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DDI C]
>[13247.451708] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST A]
>[13247.451719] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST B]
>[13247.451730] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI D]
>[13247.451741] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[13247.451752] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[13247.451765] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:56:DP-1]
>[13247.451778] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[13247.451791] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[13247.451803] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[13247.451815] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[13247.451827] [drm:intel_power_well_disable [i915]] disabling power well 2
>[13247.451842] [drm:intel_atomic_commit_tail [i915]] [CRTC:37:pipe A]
>[13247.451852] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000002434bbd
>[13247.451858] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000002434bbd
>[13247.451913] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[13247.451920] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:56:DP-1]
>[13247.451926] [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000002434bbd
>[13247.451932] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:37:pipe A] 00000000b8d65185 state to 0000000002434bbd
>[13247.451937] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000dbafe848 state to 0000000002434bbd
>[13247.451943] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [MODE:1920x1080] for CRTC state 00000000b8d65185
>[13247.451947] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 00000000dbafe848 to [CRTC:37:pipe A]
>[13247.451952] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:98] for plane state 00000000dbafe848
>[13247.451956] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:37:pipe A] to 0000000002434bbd
>[13247.451961] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:56:DP-1] 00000000d1e5643f state to 0000000002434bbd
>[13247.451965] [drm:drm_atomic_set_crtc_for_connector [drm]] Link connector state 00000000d1e5643f to [CRTC:37:pipe A]
>[13247.451969] [drm:drm_atomic_check_only [drm]] checking 0000000002434bbd
>[13247.451973] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:37:pipe A] mode changed
>[13247.451975] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:37:pipe A] enable changed
>[13247.451978] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:37:pipe A] active changed
>[13247.451980] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:56:DP-1]
>[13247.451983] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:56:DP-1] using [ENCODER:55:DDI B] on [CRTC:37:pipe A]
>[13247.451985] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:37:pipe A] needs all connectors, enable: y, active: y
>[13247.451989] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:37:pipe A] to 0000000002434bbd
>[13247.451994] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:37:pipe A] to 0000000002434bbd
>[13247.452010] [drm:intel_atomic_check [i915]] [CONNECTOR:56:DP-1] checking for sink bpp constrains
>[13247.452025] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 148500KHz
>[13247.452043] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 4 clock 270000 bpp 36
>[13247.452056] [drm:intel_dp_compute_config [i915]] DP link bw required 668250 available 1080000
>[13247.452070] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 36, dithering: 0
>[13247.452084] [drm:intel_dump_pipe_config [i915]] [CRTC:37:pipe A][modeset]
>[13247.452098] [drm:intel_dump_pipe_config [i915]] output_types: DP (0x80)
>[13247.452111] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 36, dithering: 0
>[13247.452123] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5190451, gmch_n: 8388608, link_m: 288358, link_n: 524288, tu: 64
>[13247.452135] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[13247.452146] [drm:intel_dump_pipe_config [i915]] requested mode:
>[13247.452153] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x9
>[13247.452165] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[13247.452171] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x9
>[13247.452184] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x9
>[13247.452195] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500
>[13247.452207] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[13247.452218] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[13247.452230] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[13247.452241] [drm:intel_dump_pipe_config [i915]] dpll_hw_state: ctrl1: 0x3, cfgcr1: 0x0, cfgcr2: 0x0
>[13247.452251] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[13247.452262] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 1A] disabled, scaler_id = -1
>[13247.452273] [drm:intel_dump_pipe_config [i915]] [PLANE:31:plane 2A] disabled, scaler_id = -1
>[13247.452284] [drm:intel_dump_pipe_config [i915]] [PLANE:34:cursor A] disabled, scaler_id = -1
>[13247.452298] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[13247.452310] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[13247.452325] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:37:pipe A] has [PLANE:28:plane 1A] with fb 98
>[13247.452337] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 0 -> 1, off 0, on 1, ms 1
>[13247.452351] [drm:intel_find_shared_dpll [i915]] [CRTC:37:pipe A] allocated DPLL 1
>[13247.452364] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[13247.452372] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:47:pipe B] 00000000c85dec7a state to 0000000002434bbd
>[13247.452384] [drm:skl_compute_wm [i915]] [PLANE:28:plane 1A] ddb (0 - 0) -> (0 - 860)
>[13247.452394] [drm:skl_compute_wm [i915]] [PLANE:34:cursor A] ddb (0 - 0) -> (860 - 892)
>[13247.452400] [drm:drm_atomic_commit [drm]] committing 0000000002434bbd
>[13248.452164] [drm:intel_power_well_enable [i915]] enabling power well 2
>[13248.452248] [drm:intel_atomic_commit_tail [i915]] [ENCODER:48:DDI A]
>[13248.452313] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI B]
>[13248.452370] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[13248.452423] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[13248.452474] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DDI C]
>[13248.452524] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST A]
>[13248.452573] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST B]
>[13248.452622] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI D]
>[13248.452670] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[13248.452717] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[13248.452814] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[13248.452897] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[13248.452955] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[13248.453010] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[13248.453075] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 37
>[13248.453134] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[13248.453276] [drm:intel_power_well_enable [i915]] enabling DDI B IO power well
>[13248.453873] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13248.455109] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13248.456344] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13248.457536] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13248.458772] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13248.459635] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[13248.460608] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[13248.460663] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[13248.460714] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[13248.460790] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[13248.479444] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[13248.479473] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[13248.497294] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[13248.497616] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:56:DP-1] Link Training Passed at Link Rate = 270000, Lane count = 4
>[13248.497993] [drm:intel_enable_pipe [i915]] enabling pipe A
>[13248.498037] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS
>[13248.498049] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:56:DP-1], [ENCODER:55:DDI B]
>[13248.498061] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[13248.498074] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[13248.498091] [drm:intel_fbc_enable [i915]] reserved 8294400 bytes of contiguous stolen space for FBC, threshold: 1
>[13248.498102] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[13248.514824] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:56:DP-1]
>[13248.514840] [drm:intel_atomic_commit_tail [i915]] [CRTC:37:pipe A]
>[13248.514860] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[13248.514869] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000002434bbd
>[13248.514874] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000002434bbd
>[13248.514887] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[13248.514893] [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000002434bbd
>[13248.514898] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:37:pipe A] 000000002b48c403 state to 0000000002434bbd
>[13248.514902] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000feda2dba state to 0000000002434bbd
>[13248.514906] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for CRTC state 000000002b48c403
>[13248.514910] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 00000000feda2dba to [NOCRTC]
>[13248.514914] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for plane state 00000000feda2dba
>[13248.514918] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:37:pipe A] to 0000000002434bbd
>[13248.514922] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:56:DP-1] 00000000f8eadac6 state to 0000000002434bbd
>[13248.514926] [drm:drm_atomic_set_crtc_for_connector [drm]] Link connector state 00000000f8eadac6 to [NOCRTC]
>[13248.514930] [drm:drm_atomic_check_only [drm]] checking 0000000002434bbd
>[13248.514933] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:37:pipe A] mode changed
>[13248.514935] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:37:pipe A] enable changed
>[13248.514937] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:37:pipe A] active changed
>[13248.514939] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:56:DP-1]
>[13248.514941] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Disabling [CONNECTOR:56:DP-1]
>[13248.514943] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:37:pipe A] needs all connectors, enable: n, active: n
>[13248.514947] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:37:pipe A] to 0000000002434bbd
>[13248.514963] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[13248.514977] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[13248.514991] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:37:pipe A] has [PLANE:28:plane 1A] with fb -1
>[13248.515004] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 0, off 1, on 0, ms 1
>[13248.515010] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:47:pipe B] 00000000bd3c0152 state to 0000000002434bbd
>[13248.515021] [drm:skl_compute_wm [i915]] [PLANE:28:plane 1A] ddb (0 - 860) -> (0 - 0)
>[13248.515030] [drm:skl_compute_wm [i915]] [PLANE:34:cursor A] ddb (860 - 892) -> (0 - 0)
>[13248.515036] [drm:drm_atomic_commit [drm]] committing 0000000002434bbd
>[13248.515055] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[13248.515069] [drm:i915_audio_component_get_eld [i915]] Not valid for port B
>[13248.515086] [drm:intel_disable_pipe [i915]] disabling pipe A
>[13248.531924] [drm:intel_power_well_disable [i915]] disabling DDI B IO power well
>[13248.531943] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[13248.531959] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 37
>[13248.531973] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[13248.531996] [drm:intel_atomic_commit_tail [i915]] [ENCODER:48:DDI A]
>[13248.532010] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI B]
>[13248.532023] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[13248.532035] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[13248.532047] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DDI C]
>[13248.532059] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST A]
>[13248.532070] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST B]
>[13248.532081] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI D]
>[13248.532093] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[13248.532104] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[13248.532117] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:56:DP-1]
>[13248.532130] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[13248.532143] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[13248.532156] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[13248.532168] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[13248.532181] [drm:intel_power_well_disable [i915]] disabling power well 2
>[13248.532198] [drm:intel_atomic_commit_tail [i915]] [CRTC:37:pipe A]
>[13248.532210] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000002434bbd
>[13248.532217] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000002434bbd
>[13248.532324] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[13248.532331] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:56:DP-1]
>[13248.532337] [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000002434bbd
>[13248.532344] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:37:pipe A] 00000000c85dec7a state to 0000000002434bbd
>[13248.532349] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000a8722221 state to 0000000002434bbd
>[13248.532355] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [MODE:1920x1080] for CRTC state 00000000c85dec7a
>[13248.532359] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 00000000a8722221 to [CRTC:37:pipe A]
>[13248.532364] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:101] for plane state 00000000a8722221
>[13248.532368] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:37:pipe A] to 0000000002434bbd
>[13248.532374] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:56:DP-1] 00000000de6d4337 state to 0000000002434bbd
>[13248.532378] [drm:drm_atomic_set_crtc_for_connector [drm]] Link connector state 00000000de6d4337 to [CRTC:37:pipe A]
>[13248.532383] [drm:drm_atomic_check_only [drm]] checking 0000000002434bbd
>[13248.532388] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:37:pipe A] mode changed
>[13248.532391] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:37:pipe A] enable changed
>[13248.532393] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:37:pipe A] active changed
>[13248.532396] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:56:DP-1]
>[13248.532398] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:56:DP-1] using [ENCODER:55:DDI B] on [CRTC:37:pipe A]
>[13248.532401] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:37:pipe A] needs all connectors, enable: y, active: y
>[13248.532405] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:37:pipe A] to 0000000002434bbd
>[13248.532411] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:37:pipe A] to 0000000002434bbd
>[13248.532427] [drm:intel_atomic_check [i915]] [CONNECTOR:56:DP-1] checking for sink bpp constrains
>[13248.532443] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 148500KHz
>[13248.532461] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 4 clock 270000 bpp 36
>[13248.532475] [drm:intel_dp_compute_config [i915]] DP link bw required 668250 available 1080000
>[13248.532494] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 36, dithering: 0
>[13248.532508] [drm:intel_dump_pipe_config [i915]] [CRTC:37:pipe A][modeset]
>[13248.532521] [drm:intel_dump_pipe_config [i915]] output_types: DP (0x80)
>[13248.532534] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 36, dithering: 0
>[13248.532546] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5190451, gmch_n: 8388608, link_m: 288358, link_n: 524288, tu: 64
>[13248.532558] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[13248.532569] [drm:intel_dump_pipe_config [i915]] requested mode:
>[13248.532575] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x9
>[13248.532587] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[13248.532593] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x9
>[13248.532605] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x9
>[13248.532617] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500
>[13248.532628] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[13248.532640] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[13248.532651] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[13248.532662] [drm:intel_dump_pipe_config [i915]] dpll_hw_state: ctrl1: 0x3, cfgcr1: 0x0, cfgcr2: 0x0
>[13248.532672] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[13248.532697] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 1A] disabled, scaler_id = -1
>[13248.532708] [drm:intel_dump_pipe_config [i915]] [PLANE:31:plane 2A] disabled, scaler_id = -1
>[13248.532719] [drm:intel_dump_pipe_config [i915]] [PLANE:34:cursor A] disabled, scaler_id = -1
>[13248.532733] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[13248.532750] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[13248.532766] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:37:pipe A] has [PLANE:28:plane 1A] with fb 101
>[13248.532781] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 0 -> 1, off 0, on 1, ms 1
>[13248.532797] [drm:intel_find_shared_dpll [i915]] [CRTC:37:pipe A] allocated DPLL 1
>[13248.532811] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[13248.532828] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:47:pipe B] 00000000b8d65185 state to 0000000002434bbd
>[13248.532842] [drm:skl_compute_wm [i915]] [PLANE:28:plane 1A] ddb (0 - 0) -> (0 - 860)
>[13248.532853] [drm:skl_compute_wm [i915]] [PLANE:34:cursor A] ddb (0 - 0) -> (860 - 892)
>[13248.532862] [drm:drm_atomic_commit [drm]] committing 0000000002434bbd
>[13249.532585] [drm:intel_power_well_enable [i915]] enabling power well 2
>[13249.532668] [drm:intel_atomic_commit_tail [i915]] [ENCODER:48:DDI A]
>[13249.532741] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI B]
>[13249.532832] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[13249.532896] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[13249.532955] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DDI C]
>[13249.533005] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST A]
>[13249.533056] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST B]
>[13249.533104] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI D]
>[13249.533153] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[13249.533199] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[13249.533254] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[13249.533310] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[13249.533363] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[13249.533414] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[13249.533476] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 37
>[13249.533532] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[13249.533671] [drm:intel_power_well_enable [i915]] enabling DDI B IO power well
>[13249.534265] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13249.535504] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13249.536753] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13249.537999] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13249.539236] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13249.540092] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[13249.541076] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[13249.541133] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[13249.541184] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[13249.541234] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[13249.559873] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[13249.559902] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[13249.577648] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[13249.577970] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:56:DP-1] Link Training Passed at Link Rate = 270000, Lane count = 4
>[13249.578347] [drm:intel_enable_pipe [i915]] enabling pipe A
>[13249.578391] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS
>[13249.578404] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:56:DP-1], [ENCODER:55:DDI B]
>[13249.578415] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[13249.578429] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[13249.578449] [drm:intel_fbc_enable [i915]] reserved 8294400 bytes of contiguous stolen space for FBC, threshold: 1
>[13249.578460] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[13249.595164] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:56:DP-1]
>[13249.595180] [drm:intel_atomic_commit_tail [i915]] [CRTC:37:pipe A]
>[13249.595201] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[13249.595209] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000002434bbd
>[13249.595215] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000002434bbd
>[13249.595230] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[13249.595235] [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000002434bbd
>[13249.595240] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:37:pipe A] 00000000bd3c0152 state to 0000000002434bbd
>[13249.595245] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000dbafe848 state to 0000000002434bbd
>[13249.595249] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for CRTC state 00000000bd3c0152
>[13249.595253] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 00000000dbafe848 to [NOCRTC]
>[13249.595257] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for plane state 00000000dbafe848
>[13249.595261] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:37:pipe A] to 0000000002434bbd
>[13249.595265] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:56:DP-1] 00000000fcc1d3f4 state to 0000000002434bbd
>[13249.595269] [drm:drm_atomic_set_crtc_for_connector [drm]] Link connector state 00000000fcc1d3f4 to [NOCRTC]
>[13249.595273] [drm:drm_atomic_check_only [drm]] checking 0000000002434bbd
>[13249.595276] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:37:pipe A] mode changed
>[13249.595279] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:37:pipe A] enable changed
>[13249.595281] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:37:pipe A] active changed
>[13249.595283] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:56:DP-1]
>[13249.595285] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Disabling [CONNECTOR:56:DP-1]
>[13249.595287] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:37:pipe A] needs all connectors, enable: n, active: n
>[13249.595291] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:37:pipe A] to 0000000002434bbd
>[13249.595307] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[13249.595321] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[13249.595335] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:37:pipe A] has [PLANE:28:plane 1A] with fb -1
>[13249.595347] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 0, off 1, on 0, ms 1
>[13249.595353] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:47:pipe B] 000000002b48c403 state to 0000000002434bbd
>[13249.595364] [drm:skl_compute_wm [i915]] [PLANE:28:plane 1A] ddb (0 - 860) -> (0 - 0)
>[13249.595374] [drm:skl_compute_wm [i915]] [PLANE:34:cursor A] ddb (860 - 892) -> (0 - 0)
>[13249.595379] [drm:drm_atomic_commit [drm]] committing 0000000002434bbd
>[13249.595399] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[13249.595412] [drm:i915_audio_component_get_eld [i915]] Not valid for port B
>[13249.595429] [drm:intel_disable_pipe [i915]] disabling pipe A
>[13249.614229] [drm:intel_power_well_disable [i915]] disabling DDI B IO power well
>[13249.614247] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[13249.614262] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 37
>[13249.614276] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[13249.614298] [drm:intel_atomic_commit_tail [i915]] [ENCODER:48:DDI A]
>[13249.614311] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI B]
>[13249.614324] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[13249.614337] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[13249.614348] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DDI C]
>[13249.614360] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST A]
>[13249.614371] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST B]
>[13249.614382] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI D]
>[13249.614393] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[13249.614404] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[13249.614417] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:56:DP-1]
>[13249.614430] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[13249.614443] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[13249.614455] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[13249.614467] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[13249.614479] [drm:intel_power_well_disable [i915]] disabling power well 2
>[13249.614494] [drm:intel_atomic_commit_tail [i915]] [CRTC:37:pipe A]
>[13249.614504] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000002434bbd
>[13249.614510] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000002434bbd
>[13249.614576] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[13249.614582] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:56:DP-1]
>[13249.614588] [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000002434bbd
>[13249.614594] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:37:pipe A] 00000000b8d65185 state to 0000000002434bbd
>[13249.614599] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000feda2dba state to 0000000002434bbd
>[13249.614605] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [MODE:1920x1080] for CRTC state 00000000b8d65185
>[13249.614609] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 00000000feda2dba to [CRTC:37:pipe A]
>[13249.614613] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:98] for plane state 00000000feda2dba
>[13249.614618] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:37:pipe A] to 0000000002434bbd
>[13249.614623] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:56:DP-1] 00000000f8eadac6 state to 0000000002434bbd
>[13249.614627] [drm:drm_atomic_set_crtc_for_connector [drm]] Link connector state 00000000f8eadac6 to [CRTC:37:pipe A]
>[13249.614631] [drm:drm_atomic_check_only [drm]] checking 0000000002434bbd
>[13249.614635] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:37:pipe A] mode changed
>[13249.614637] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:37:pipe A] enable changed
>[13249.614639] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:37:pipe A] active changed
>[13249.614642] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:56:DP-1]
>[13249.614644] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:56:DP-1] using [ENCODER:55:DDI B] on [CRTC:37:pipe A]
>[13249.614647] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:37:pipe A] needs all connectors, enable: y, active: y
>[13249.614651] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:37:pipe A] to 0000000002434bbd
>[13249.614656] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:37:pipe A] to 0000000002434bbd
>[13249.614672] [drm:intel_atomic_check [i915]] [CONNECTOR:56:DP-1] checking for sink bpp constrains
>[13249.614687] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 148500KHz
>[13249.614705] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 4 clock 270000 bpp 36
>[13249.614719] [drm:intel_dp_compute_config [i915]] DP link bw required 668250 available 1080000
>[13249.614733] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 36, dithering: 0
>[13249.614747] [drm:intel_dump_pipe_config [i915]] [CRTC:37:pipe A][modeset]
>[13249.614760] [drm:intel_dump_pipe_config [i915]] output_types: DP (0x80)
>[13249.614773] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 36, dithering: 0
>[13249.614785] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5190451, gmch_n: 8388608, link_m: 288358, link_n: 524288, tu: 64
>[13249.614797] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[13249.614808] [drm:intel_dump_pipe_config [i915]] requested mode:
>[13249.614814] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x9
>[13249.614826] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[13249.614832] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x9
>[13249.614845] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x9
>[13249.614857] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500
>[13249.614868] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[13249.614879] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[13249.614891] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[13249.614902] [drm:intel_dump_pipe_config [i915]] dpll_hw_state: ctrl1: 0x3, cfgcr1: 0x0, cfgcr2: 0x0
>[13249.614912] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[13249.614923] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 1A] disabled, scaler_id = -1
>[13249.614934] [drm:intel_dump_pipe_config [i915]] [PLANE:31:plane 2A] disabled, scaler_id = -1
>[13249.614945] [drm:intel_dump_pipe_config [i915]] [PLANE:34:cursor A] disabled, scaler_id = -1
>[13249.614959] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[13249.614971] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[13249.614985] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:37:pipe A] has [PLANE:28:plane 1A] with fb 98
>[13249.614998] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 0 -> 1, off 0, on 1, ms 1
>[13249.615012] [drm:intel_find_shared_dpll [i915]] [CRTC:37:pipe A] allocated DPLL 1
>[13249.615025] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[13249.615033] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:47:pipe B] 00000000c85dec7a state to 0000000002434bbd
>[13249.615044] [drm:skl_compute_wm [i915]] [PLANE:28:plane 1A] ddb (0 - 0) -> (0 - 860)
>[13249.615054] [drm:skl_compute_wm [i915]] [PLANE:34:cursor A] ddb (0 - 0) -> (860 - 892)
>[13249.615061] [drm:drm_atomic_commit [drm]] committing 0000000002434bbd
>[13250.614828] [drm:intel_power_well_enable [i915]] enabling power well 2
>[13250.614911] [drm:intel_atomic_commit_tail [i915]] [ENCODER:48:DDI A]
>[13250.614976] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI B]
>[13250.615034] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[13250.615089] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[13250.615141] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DDI C]
>[13250.615192] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST A]
>[13250.615242] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST B]
>[13250.615291] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI D]
>[13250.615339] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[13250.615388] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[13250.615443] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[13250.615499] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[13250.615553] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[13250.615605] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[13250.615668] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 37
>[13250.615725] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[13250.615866] [drm:intel_power_well_enable [i915]] enabling DDI B IO power well
>[13250.616458] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13250.617645] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13250.618847] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13250.620075] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13250.621377] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13250.622233] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[13250.623209] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[13250.623265] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[13250.623317] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[13250.623367] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[13250.642089] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[13250.642119] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[13250.660819] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[13250.661142] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:56:DP-1] Link Training Passed at Link Rate = 270000, Lane count = 4
>[13250.661502] [drm:intel_enable_pipe [i915]] enabling pipe A
>[13250.661531] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS
>[13250.661544] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:56:DP-1], [ENCODER:55:DDI B]
>[13250.661555] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[13250.661568] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[13250.661585] [drm:intel_fbc_enable [i915]] reserved 8294400 bytes of contiguous stolen space for FBC, threshold: 1
>[13250.661596] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[13250.678308] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:56:DP-1]
>[13250.678323] [drm:intel_atomic_commit_tail [i915]] [CRTC:37:pipe A]
>[13250.678343] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[13250.678352] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000002434bbd
>[13250.678358] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000002434bbd
>[13250.678371] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[13250.678376] [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000002434bbd
>[13250.678381] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:37:pipe A] 000000002b48c403 state to 0000000002434bbd
>[13250.678386] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000a8722221 state to 0000000002434bbd
>[13250.678390] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for CRTC state 000000002b48c403
>[13250.678394] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 00000000a8722221 to [NOCRTC]
>[13250.678398] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for plane state 00000000a8722221
>[13250.678402] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:37:pipe A] to 0000000002434bbd
>[13250.678406] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:56:DP-1] 00000000d1e5643f state to 0000000002434bbd
>[13250.678410] [drm:drm_atomic_set_crtc_for_connector [drm]] Link connector state 00000000d1e5643f to [NOCRTC]
>[13250.678413] [drm:drm_atomic_check_only [drm]] checking 0000000002434bbd
>[13250.678416] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:37:pipe A] mode changed
>[13250.678419] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:37:pipe A] enable changed
>[13250.678421] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:37:pipe A] active changed
>[13250.678423] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:56:DP-1]
>[13250.678425] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Disabling [CONNECTOR:56:DP-1]
>[13250.678427] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:37:pipe A] needs all connectors, enable: n, active: n
>[13250.678431] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:37:pipe A] to 0000000002434bbd
>[13250.678447] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[13250.678460] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[13250.678474] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:37:pipe A] has [PLANE:28:plane 1A] with fb -1
>[13250.678486] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 0, off 1, on 0, ms 1
>[13250.678493] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:47:pipe B] 00000000bd3c0152 state to 0000000002434bbd
>[13250.678504] [drm:skl_compute_wm [i915]] [PLANE:28:plane 1A] ddb (0 - 860) -> (0 - 0)
>[13250.678513] [drm:skl_compute_wm [i915]] [PLANE:34:cursor A] ddb (860 - 892) -> (0 - 0)
>[13250.678519] [drm:drm_atomic_commit [drm]] committing 0000000002434bbd
>[13250.678538] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[13250.678552] [drm:i915_audio_component_get_eld [i915]] Not valid for port B
>[13250.678569] [drm:intel_disable_pipe [i915]] disabling pipe A
>[13250.697522] [drm:intel_power_well_disable [i915]] disabling DDI B IO power well
>[13250.697541] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[13250.697557] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 37
>[13250.697572] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[13250.697595] [drm:intel_atomic_commit_tail [i915]] [ENCODER:48:DDI A]
>[13250.697608] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI B]
>[13250.697622] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[13250.697634] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[13250.697646] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DDI C]
>[13250.697658] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST A]
>[13250.697669] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST B]
>[13250.697681] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI D]
>[13250.697692] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[13250.697703] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[13250.697716] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:56:DP-1]
>[13250.697729] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[13250.697745] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[13250.697758] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[13250.697769] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[13250.697783] [drm:intel_power_well_disable [i915]] disabling power well 2
>[13250.697799] [drm:intel_atomic_commit_tail [i915]] [CRTC:37:pipe A]
>[13250.697811] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000002434bbd
>[13250.697819] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000002434bbd
>[13250.697925] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[13250.697932] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:56:DP-1]
>[13250.697938] [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000002434bbd
>[13250.697945] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:37:pipe A] 00000000c85dec7a state to 0000000002434bbd
>[13250.697950] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000dbafe848 state to 0000000002434bbd
>[13250.697956] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [MODE:1920x1080] for CRTC state 00000000c85dec7a
>[13250.697961] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 00000000dbafe848 to [CRTC:37:pipe A]
>[13250.697965] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:101] for plane state 00000000dbafe848
>[13250.697970] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:37:pipe A] to 0000000002434bbd
>[13250.697975] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:56:DP-1] 00000000fcc1d3f4 state to 0000000002434bbd
>[13250.697979] [drm:drm_atomic_set_crtc_for_connector [drm]] Link connector state 00000000fcc1d3f4 to [CRTC:37:pipe A]
>[13250.697984] [drm:drm_atomic_check_only [drm]] checking 0000000002434bbd
>[13250.697989] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:37:pipe A] mode changed
>[13250.697991] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:37:pipe A] enable changed
>[13250.697994] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:37:pipe A] active changed
>[13250.697996] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:56:DP-1]
>[13250.697999] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:56:DP-1] using [ENCODER:55:DDI B] on [CRTC:37:pipe A]
>[13250.698001] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:37:pipe A] needs all connectors, enable: y, active: y
>[13250.698006] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:37:pipe A] to 0000000002434bbd
>[13250.698011] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:37:pipe A] to 0000000002434bbd
>[13250.698027] [drm:intel_atomic_check [i915]] [CONNECTOR:56:DP-1] checking for sink bpp constrains
>[13250.698043] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 148500KHz
>[13250.698062] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 4 clock 270000 bpp 36
>[13250.698079] [drm:intel_dp_compute_config [i915]] DP link bw required 668250 available 1080000
>[13250.698094] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 36, dithering: 0
>[13250.698108] [drm:intel_dump_pipe_config [i915]] [CRTC:37:pipe A][modeset]
>[13250.698121] [drm:intel_dump_pipe_config [i915]] output_types: DP (0x80)
>[13250.698133] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 36, dithering: 0
>[13250.698146] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5190451, gmch_n: 8388608, link_m: 288358, link_n: 524288, tu: 64
>[13250.698157] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[13250.698168] [drm:intel_dump_pipe_config [i915]] requested mode:
>[13250.698175] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x9
>[13250.698187] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[13250.698193] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x9
>[13250.698206] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x9
>[13250.698217] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500
>[13250.698229] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[13250.698240] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[13250.698251] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[13250.698262] [drm:intel_dump_pipe_config [i915]] dpll_hw_state: ctrl1: 0x3, cfgcr1: 0x0, cfgcr2: 0x0
>[13250.698273] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[13250.698284] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 1A] disabled, scaler_id = -1
>[13250.698295] [drm:intel_dump_pipe_config [i915]] [PLANE:31:plane 2A] disabled, scaler_id = -1
>[13250.698306] [drm:intel_dump_pipe_config [i915]] [PLANE:34:cursor A] disabled, scaler_id = -1
>[13250.698320] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[13250.698332] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[13250.698347] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:37:pipe A] has [PLANE:28:plane 1A] with fb 101
>[13250.698360] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 0 -> 1, off 0, on 1, ms 1
>[13250.698374] [drm:intel_find_shared_dpll [i915]] [CRTC:37:pipe A] allocated DPLL 1
>[13250.698387] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[13250.698402] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:47:pipe B] 00000000b8d65185 state to 0000000002434bbd
>[13250.698414] [drm:skl_compute_wm [i915]] [PLANE:28:plane 1A] ddb (0 - 0) -> (0 - 860)
>[13250.698424] [drm:skl_compute_wm [i915]] [PLANE:34:cursor A] ddb (0 - 0) -> (860 - 892)
>[13250.698430] [drm:drm_atomic_commit [drm]] committing 0000000002434bbd
>[13251.698188] [drm:intel_power_well_enable [i915]] enabling power well 2
>[13251.698271] [drm:intel_atomic_commit_tail [i915]] [ENCODER:48:DDI A]
>[13251.698335] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI B]
>[13251.698392] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[13251.698446] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[13251.698497] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DDI C]
>[13251.698547] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST A]
>[13251.698596] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST B]
>[13251.698646] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI D]
>[13251.698694] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[13251.698744] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[13251.698799] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[13251.698855] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[13251.698910] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[13251.698963] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[13251.699025] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 37
>[13251.699081] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[13251.699223] [drm:intel_power_well_enable [i915]] enabling DDI B IO power well
>[13251.699816] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13251.701066] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13251.702320] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13251.703548] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13251.704788] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13251.705644] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[13251.706620] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[13251.706675] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[13251.706727] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[13251.706777] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[13251.725376] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[13251.725405] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[13251.743144] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[13251.743321] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:56:DP-1] Link Training Passed at Link Rate = 270000, Lane count = 4
>[13251.743682] [drm:intel_enable_pipe [i915]] enabling pipe A
>[13251.743705] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS
>[13251.743717] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:56:DP-1], [ENCODER:55:DDI B]
>[13251.743729] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[13251.743742] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[13251.743762] [drm:intel_fbc_enable [i915]] reserved 8294400 bytes of contiguous stolen space for FBC, threshold: 1
>[13251.743774] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[13251.760483] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:56:DP-1]
>[13251.760499] [drm:intel_atomic_commit_tail [i915]] [CRTC:37:pipe A]
>[13251.760520] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[13251.760529] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000002434bbd
>[13251.760534] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000002434bbd
>[13251.760550] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[13251.760555] [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000002434bbd
>[13251.760560] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:37:pipe A] 00000000bd3c0152 state to 0000000002434bbd
>[13251.760565] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000feda2dba state to 0000000002434bbd
>[13251.760569] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for CRTC state 00000000bd3c0152
>[13251.760573] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 00000000feda2dba to [NOCRTC]
>[13251.760577] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for plane state 00000000feda2dba
>[13251.760581] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:37:pipe A] to 0000000002434bbd
>[13251.760585] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:56:DP-1] 00000000de6d4337 state to 0000000002434bbd
>[13251.760589] [drm:drm_atomic_set_crtc_for_connector [drm]] Link connector state 00000000de6d4337 to [NOCRTC]
>[13251.760592] [drm:drm_atomic_check_only [drm]] checking 0000000002434bbd
>[13251.760596] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:37:pipe A] mode changed
>[13251.760598] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:37:pipe A] enable changed
>[13251.760600] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:37:pipe A] active changed
>[13251.760602] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:56:DP-1]
>[13251.760604] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Disabling [CONNECTOR:56:DP-1]
>[13251.760606] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:37:pipe A] needs all connectors, enable: n, active: n
>[13251.760610] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:37:pipe A] to 0000000002434bbd
>[13251.760626] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[13251.760640] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[13251.760654] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:37:pipe A] has [PLANE:28:plane 1A] with fb -1
>[13251.760667] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 0, off 1, on 0, ms 1
>[13251.760673] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:47:pipe B] 000000002b48c403 state to 0000000002434bbd
>[13251.760691] [drm:skl_compute_wm [i915]] [PLANE:28:plane 1A] ddb (0 - 860) -> (0 - 0)
>[13251.760732] [drm:skl_compute_wm [i915]] [PLANE:34:cursor A] ddb (860 - 892) -> (0 - 0)
>[13251.760738] [drm:drm_atomic_commit [drm]] committing 0000000002434bbd
>[13251.760777] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[13251.760793] [drm:i915_audio_component_get_eld [i915]] Not valid for port B
>[13251.760830] [drm:intel_disable_pipe [i915]] disabling pipe A
>[13251.778238] [drm:intel_power_well_disable [i915]] disabling DDI B IO power well
>[13251.778256] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[13251.778271] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 37
>[13251.778285] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[13251.778307] [drm:intel_atomic_commit_tail [i915]] [ENCODER:48:DDI A]
>[13251.778321] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI B]
>[13251.778334] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[13251.778346] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[13251.778358] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DDI C]
>[13251.778369] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST A]
>[13251.778381] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST B]
>[13251.778392] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI D]
>[13251.778403] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[13251.778414] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[13251.778427] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:56:DP-1]
>[13251.778440] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[13251.778453] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[13251.778465] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[13251.778477] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[13251.778490] [drm:intel_power_well_disable [i915]] disabling power well 2
>[13251.778505] [drm:intel_atomic_commit_tail [i915]] [CRTC:37:pipe A]
>[13251.778514] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000002434bbd
>[13251.778521] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000002434bbd
>[13251.778578] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[13251.778584] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:56:DP-1]
>[13251.778590] [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000002434bbd
>[13251.778596] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:37:pipe A] 00000000b8d65185 state to 0000000002434bbd
>[13251.778602] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000a8722221 state to 0000000002434bbd
>[13251.778607] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [MODE:1920x1080] for CRTC state 00000000b8d65185
>[13251.778612] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 00000000a8722221 to [CRTC:37:pipe A]
>[13251.778616] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:98] for plane state 00000000a8722221
>[13251.778620] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:37:pipe A] to 0000000002434bbd
>[13251.778625] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:56:DP-1] 00000000d1e5643f state to 0000000002434bbd
>[13251.778629] [drm:drm_atomic_set_crtc_for_connector [drm]] Link connector state 00000000d1e5643f to [CRTC:37:pipe A]
>[13251.778634] [drm:drm_atomic_check_only [drm]] checking 0000000002434bbd
>[13251.778637] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:37:pipe A] mode changed
>[13251.778640] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:37:pipe A] enable changed
>[13251.778642] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:37:pipe A] active changed
>[13251.778645] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:56:DP-1]
>[13251.778647] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:56:DP-1] using [ENCODER:55:DDI B] on [CRTC:37:pipe A]
>[13251.778650] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:37:pipe A] needs all connectors, enable: y, active: y
>[13251.778654] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:37:pipe A] to 0000000002434bbd
>[13251.778659] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:37:pipe A] to 0000000002434bbd
>[13251.778675] [drm:intel_atomic_check [i915]] [CONNECTOR:56:DP-1] checking for sink bpp constrains
>[13251.778690] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 148500KHz
>[13251.778708] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 4 clock 270000 bpp 36
>[13251.778721] [drm:intel_dp_compute_config [i915]] DP link bw required 668250 available 1080000
>[13251.778736] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 36, dithering: 0
>[13251.778750] [drm:intel_dump_pipe_config [i915]] [CRTC:37:pipe A][modeset]
>[13251.778763] [drm:intel_dump_pipe_config [i915]] output_types: DP (0x80)
>[13251.778775] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 36, dithering: 0
>[13251.778788] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5190451, gmch_n: 8388608, link_m: 288358, link_n: 524288, tu: 64
>[13251.778799] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[13251.778811] [drm:intel_dump_pipe_config [i915]] requested mode:
>[13251.778817] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x9
>[13251.778829] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[13251.778835] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x9
>[13251.778848] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x9
>[13251.778860] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500
>[13251.778871] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[13251.778883] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[13251.778894] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[13251.778905] [drm:intel_dump_pipe_config [i915]] dpll_hw_state: ctrl1: 0x3, cfgcr1: 0x0, cfgcr2: 0x0
>[13251.778916] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[13251.778927] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 1A] disabled, scaler_id = -1
>[13251.778938] [drm:intel_dump_pipe_config [i915]] [PLANE:31:plane 2A] disabled, scaler_id = -1
>[13251.778948] [drm:intel_dump_pipe_config [i915]] [PLANE:34:cursor A] disabled, scaler_id = -1
>[13251.778962] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[13251.778975] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[13251.778989] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:37:pipe A] has [PLANE:28:plane 1A] with fb 98
>[13251.779001] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 0 -> 1, off 0, on 1, ms 1
>[13251.779015] [drm:intel_find_shared_dpll [i915]] [CRTC:37:pipe A] allocated DPLL 1
>[13251.779028] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[13251.779036] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:47:pipe B] 00000000c85dec7a state to 0000000002434bbd
>[13251.779048] [drm:skl_compute_wm [i915]] [PLANE:28:plane 1A] ddb (0 - 0) -> (0 - 860)
>[13251.779058] [drm:skl_compute_wm [i915]] [PLANE:34:cursor A] ddb (0 - 0) -> (860 - 892)
>[13251.779064] [drm:drm_atomic_commit [drm]] committing 0000000002434bbd
>[13252.778834] [drm:intel_power_well_enable [i915]] enabling power well 2
>[13252.778917] [drm:intel_atomic_commit_tail [i915]] [ENCODER:48:DDI A]
>[13252.778981] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI B]
>[13252.779039] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[13252.779094] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[13252.779145] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DDI C]
>[13252.779195] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST A]
>[13252.779245] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST B]
>[13252.779293] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI D]
>[13252.779341] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[13252.779390] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[13252.779445] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[13252.779501] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[13252.779555] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[13252.779606] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[13252.779669] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 37
>[13252.779725] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[13252.779866] [drm:intel_power_well_enable [i915]] enabling DDI B IO power well
>[13252.780458] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13252.781646] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13252.782847] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13252.784083] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13252.785379] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13252.786235] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[13252.787209] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[13252.787264] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[13252.787314] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[13252.787364] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[13252.806009] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[13252.806023] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[13252.824772] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[13252.825095] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:56:DP-1] Link Training Passed at Link Rate = 270000, Lane count = 4
>[13252.825457] [drm:intel_enable_pipe [i915]] enabling pipe A
>[13252.825484] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS
>[13252.825497] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:56:DP-1], [ENCODER:55:DDI B]
>[13252.825508] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[13252.825521] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[13252.825538] [drm:intel_fbc_enable [i915]] reserved 8294400 bytes of contiguous stolen space for FBC, threshold: 1
>[13252.825549] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[13252.842259] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:56:DP-1]
>[13252.842274] [drm:intel_atomic_commit_tail [i915]] [CRTC:37:pipe A]
>[13252.842295] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[13252.842303] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000002434bbd
>[13252.842309] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000002434bbd
>[13252.842322] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[13252.842327] [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000002434bbd
>[13252.842332] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:37:pipe A] 000000002b48c403 state to 0000000002434bbd
>[13252.842337] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000dbafe848 state to 0000000002434bbd
>[13252.842341] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for CRTC state 000000002b48c403
>[13252.842345] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 00000000dbafe848 to [NOCRTC]
>[13252.842349] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for plane state 00000000dbafe848
>[13252.842353] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:37:pipe A] to 0000000002434bbd
>[13252.842357] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:56:DP-1] 00000000f8eadac6 state to 0000000002434bbd
>[13252.842361] [drm:drm_atomic_set_crtc_for_connector [drm]] Link connector state 00000000f8eadac6 to [NOCRTC]
>[13252.842365] [drm:drm_atomic_check_only [drm]] checking 0000000002434bbd
>[13252.842368] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:37:pipe A] mode changed
>[13252.842370] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:37:pipe A] enable changed
>[13252.842372] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:37:pipe A] active changed
>[13252.842374] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:56:DP-1]
>[13252.842376] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Disabling [CONNECTOR:56:DP-1]
>[13252.842378] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:37:pipe A] needs all connectors, enable: n, active: n
>[13252.842382] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:37:pipe A] to 0000000002434bbd
>[13252.842398] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[13252.842412] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[13252.842426] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:37:pipe A] has [PLANE:28:plane 1A] with fb -1
>[13252.842439] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 0, off 1, on 0, ms 1
>[13252.842445] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:47:pipe B] 00000000bd3c0152 state to 0000000002434bbd
>[13252.842456] [drm:skl_compute_wm [i915]] [PLANE:28:plane 1A] ddb (0 - 860) -> (0 - 0)
>[13252.842465] [drm:skl_compute_wm [i915]] [PLANE:34:cursor A] ddb (860 - 892) -> (0 - 0)
>[13252.842470] [drm:drm_atomic_commit [drm]] committing 0000000002434bbd
>[13252.842490] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[13252.842503] [drm:i915_audio_component_get_eld [i915]] Not valid for port B
>[13252.842520] [drm:intel_disable_pipe [i915]] disabling pipe A
>[13252.861215] [drm:intel_power_well_disable [i915]] disabling DDI B IO power well
>[13252.861233] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[13252.861250] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 37
>[13252.861264] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[13252.861287] [drm:intel_atomic_commit_tail [i915]] [ENCODER:48:DDI A]
>[13252.861301] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI B]
>[13252.861314] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[13252.861326] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[13252.861338] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DDI C]
>[13252.861350] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST A]
>[13252.861361] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST B]
>[13252.861372] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI D]
>[13252.861383] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[13252.861395] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[13252.861407] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:56:DP-1]
>[13252.861420] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[13252.861433] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[13252.861446] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[13252.861458] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[13252.861471] [drm:intel_power_well_disable [i915]] disabling power well 2
>[13252.861487] [drm:intel_atomic_commit_tail [i915]] [CRTC:37:pipe A]
>[13252.861500] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000002434bbd
>[13252.861507] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000002434bbd
>[13252.861614] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[13252.861621] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:56:DP-1]
>[13252.861627] [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000002434bbd
>[13252.861633] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:37:pipe A] 00000000c85dec7a state to 0000000002434bbd
>[13252.861639] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000feda2dba state to 0000000002434bbd
>[13252.861645] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [MODE:1920x1080] for CRTC state 00000000c85dec7a
>[13252.861649] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 00000000feda2dba to [CRTC:37:pipe A]
>[13252.861654] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:101] for plane state 00000000feda2dba
>[13252.861658] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:37:pipe A] to 0000000002434bbd
>[13252.861663] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:56:DP-1] 00000000de6d4337 state to 0000000002434bbd
>[13252.861668] [drm:drm_atomic_set_crtc_for_connector [drm]] Link connector state 00000000de6d4337 to [CRTC:37:pipe A]
>[13252.861673] [drm:drm_atomic_check_only [drm]] checking 0000000002434bbd
>[13252.861678] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:37:pipe A] mode changed
>[13252.861680] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:37:pipe A] enable changed
>[13252.861682] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:37:pipe A] active changed
>[13252.861685] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:56:DP-1]
>[13252.861688] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:56:DP-1] using [ENCODER:55:DDI B] on [CRTC:37:pipe A]
>[13252.861690] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:37:pipe A] needs all connectors, enable: y, active: y
>[13252.861695] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:37:pipe A] to 0000000002434bbd
>[13252.861700] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:37:pipe A] to 0000000002434bbd
>[13252.861716] [drm:intel_atomic_check [i915]] [CONNECTOR:56:DP-1] checking for sink bpp constrains
>[13252.861732] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 148500KHz
>[13252.861752] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 4 clock 270000 bpp 36
>[13252.861766] [drm:intel_dp_compute_config [i915]] DP link bw required 668250 available 1080000
>[13252.861781] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 36, dithering: 0
>[13252.861795] [drm:intel_dump_pipe_config [i915]] [CRTC:37:pipe A][modeset]
>[13252.861808] [drm:intel_dump_pipe_config [i915]] output_types: DP (0x80)
>[13252.861821] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 36, dithering: 0
>[13252.861834] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5190451, gmch_n: 8388608, link_m: 288358, link_n: 524288, tu: 64
>[13252.861846] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[13252.861857] [drm:intel_dump_pipe_config [i915]] requested mode:
>[13252.861864] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x9
>[13252.861876] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[13252.861882] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x9
>[13252.861894] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x9
>[13252.861906] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500
>[13252.861917] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[13252.861929] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[13252.861940] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[13252.861951] [drm:intel_dump_pipe_config [i915]] dpll_hw_state: ctrl1: 0x3, cfgcr1: 0x0, cfgcr2: 0x0
>[13252.861962] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[13252.861973] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 1A] disabled, scaler_id = -1
>[13252.861984] [drm:intel_dump_pipe_config [i915]] [PLANE:31:plane 2A] disabled, scaler_id = -1
>[13252.861995] [drm:intel_dump_pipe_config [i915]] [PLANE:34:cursor A] disabled, scaler_id = -1
>[13252.862009] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[13252.862022] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[13252.862036] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:37:pipe A] has [PLANE:28:plane 1A] with fb 101
>[13252.862049] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 0 -> 1, off 0, on 1, ms 1
>[13252.862063] [drm:intel_find_shared_dpll [i915]] [CRTC:37:pipe A] allocated DPLL 1
>[13252.862076] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[13252.862084] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:47:pipe B] 00000000b8d65185 state to 0000000002434bbd
>[13252.862097] [drm:skl_compute_wm [i915]] [PLANE:28:plane 1A] ddb (0 - 0) -> (0 - 860)
>[13252.862107] [drm:skl_compute_wm [i915]] [PLANE:34:cursor A] ddb (0 - 0) -> (860 - 892)
>[13252.862113] [drm:drm_atomic_commit [drm]] committing 0000000002434bbd
>[13253.861886] [drm:intel_power_well_enable [i915]] enabling power well 2
>[13253.861970] [drm:intel_atomic_commit_tail [i915]] [ENCODER:48:DDI A]
>[13253.862034] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI B]
>[13253.862091] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[13253.862145] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[13253.862197] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DDI C]
>[13253.862249] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST A]
>[13253.862300] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST B]
>[13253.862350] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI D]
>[13253.862399] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[13253.862447] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[13253.862503] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[13253.862560] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[13253.862615] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[13253.862667] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[13253.862731] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 37
>[13253.862787] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[13253.862929] [drm:intel_power_well_enable [i915]] enabling DDI B IO power well
>[13253.863523] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13253.864761] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13253.865994] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13253.867237] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13253.868472] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13253.869306] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[13253.870280] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[13253.870337] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[13253.870387] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[13253.870437] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[13253.889113] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[13253.889142] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[13253.906964] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[13253.907287] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:56:DP-1] Link Training Passed at Link Rate = 270000, Lane count = 4
>[13253.907648] [drm:intel_enable_pipe [i915]] enabling pipe A
>[13253.907677] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS
>[13253.907689] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:56:DP-1], [ENCODER:55:DDI B]
>[13253.907701] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[13253.907714] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[13253.907734] [drm:intel_fbc_enable [i915]] reserved 8294400 bytes of contiguous stolen space for FBC, threshold: 1
>[13253.907745] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[13253.924464] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:56:DP-1]
>[13253.924480] [drm:intel_atomic_commit_tail [i915]] [CRTC:37:pipe A]
>[13253.924501] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[13253.924509] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000002434bbd
>[13253.924515] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000002434bbd
>[13253.924530] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[13253.924535] [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000002434bbd
>[13253.924540] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:37:pipe A] 00000000bd3c0152 state to 0000000002434bbd
>[13253.924545] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000a8722221 state to 0000000002434bbd
>[13253.924549] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for CRTC state 00000000bd3c0152
>[13253.924553] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 00000000a8722221 to [NOCRTC]
>[13253.924556] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for plane state 00000000a8722221
>[13253.924560] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:37:pipe A] to 0000000002434bbd
>[13253.924564] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:56:DP-1] 00000000fcc1d3f4 state to 0000000002434bbd
>[13253.924568] [drm:drm_atomic_set_crtc_for_connector [drm]] Link connector state 00000000fcc1d3f4 to [NOCRTC]
>[13253.924572] [drm:drm_atomic_check_only [drm]] checking 0000000002434bbd
>[13253.924575] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:37:pipe A] mode changed
>[13253.924578] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:37:pipe A] enable changed
>[13253.924580] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:37:pipe A] active changed
>[13253.924582] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:56:DP-1]
>[13253.924584] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Disabling [CONNECTOR:56:DP-1]
>[13253.924586] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:37:pipe A] needs all connectors, enable: n, active: n
>[13253.924590] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:37:pipe A] to 0000000002434bbd
>[13253.924606] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[13253.924619] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[13253.924633] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:37:pipe A] has [PLANE:28:plane 1A] with fb -1
>[13253.924646] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 0, off 1, on 0, ms 1
>[13253.924652] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:47:pipe B] 000000002b48c403 state to 0000000002434bbd
>[13253.924663] [drm:skl_compute_wm [i915]] [PLANE:28:plane 1A] ddb (0 - 860) -> (0 - 0)
>[13253.924673] [drm:skl_compute_wm [i915]] [PLANE:34:cursor A] ddb (860 - 892) -> (0 - 0)
>[13253.924685] [drm:drm_atomic_commit [drm]] committing 0000000002434bbd
>[13253.924738] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[13253.924771] [drm:i915_audio_component_get_eld [i915]] Not valid for port B
>[13253.924809] [drm:intel_disable_pipe [i915]] disabling pipe A
>[13253.943555] [drm:intel_power_well_disable [i915]] disabling DDI B IO power well
>[13253.943572] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[13253.943588] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 37
>[13253.943602] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[13253.943623] [drm:intel_atomic_commit_tail [i915]] [ENCODER:48:DDI A]
>[13253.943636] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI B]
>[13253.943650] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[13253.943662] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[13253.943674] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DDI C]
>[13253.943685] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST A]
>[13253.943697] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST B]
>[13253.943708] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI D]
>[13253.943719] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[13253.943730] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[13253.943742] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:56:DP-1]
>[13253.943756] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[13253.943768] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[13253.943781] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[13253.943793] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[13253.943805] [drm:intel_power_well_disable [i915]] disabling power well 2
>[13253.943820] [drm:intel_atomic_commit_tail [i915]] [CRTC:37:pipe A]
>[13253.943830] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000002434bbd
>[13253.943836] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000002434bbd
>[13253.943893] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[13253.943899] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:56:DP-1]
>[13253.943905] [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000002434bbd
>[13253.943911] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:37:pipe A] 00000000b8d65185 state to 0000000002434bbd
>[13253.943916] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000dbafe848 state to 0000000002434bbd
>[13253.943922] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [MODE:1920x1080] for CRTC state 00000000b8d65185
>[13253.943926] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 00000000dbafe848 to [CRTC:37:pipe A]
>[13253.943931] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:98] for plane state 00000000dbafe848
>[13253.943935] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:37:pipe A] to 0000000002434bbd
>[13253.943940] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:56:DP-1] 00000000f8eadac6 state to 0000000002434bbd
>[13253.943944] [drm:drm_atomic_set_crtc_for_connector [drm]] Link connector state 00000000f8eadac6 to [CRTC:37:pipe A]
>[13253.943949] [drm:drm_atomic_check_only [drm]] checking 0000000002434bbd
>[13253.943953] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:37:pipe A] mode changed
>[13253.943955] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:37:pipe A] enable changed
>[13253.943957] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:37:pipe A] active changed
>[13253.943960] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:56:DP-1]
>[13253.943962] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:56:DP-1] using [ENCODER:55:DDI B] on [CRTC:37:pipe A]
>[13253.943965] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:37:pipe A] needs all connectors, enable: y, active: y
>[13253.943969] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:37:pipe A] to 0000000002434bbd
>[13253.943974] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:37:pipe A] to 0000000002434bbd
>[13253.943990] [drm:intel_atomic_check [i915]] [CONNECTOR:56:DP-1] checking for sink bpp constrains
>[13253.944006] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 148500KHz
>[13253.944024] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 4 clock 270000 bpp 36
>[13253.944037] [drm:intel_dp_compute_config [i915]] DP link bw required 668250 available 1080000
>[13253.944051] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 36, dithering: 0
>[13253.944065] [drm:intel_dump_pipe_config [i915]] [CRTC:37:pipe A][modeset]
>[13253.944079] [drm:intel_dump_pipe_config [i915]] output_types: DP (0x80)
>[13253.944091] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 36, dithering: 0
>[13253.944104] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5190451, gmch_n: 8388608, link_m: 288358, link_n: 524288, tu: 64
>[13253.944116] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[13253.944127] [drm:intel_dump_pipe_config [i915]] requested mode:
>[13253.944134] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x9
>[13253.944146] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[13253.944152] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x9
>[13253.944164] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x9
>[13253.944176] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500
>[13253.944188] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[13253.944199] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[13253.944210] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[13253.944222] [drm:intel_dump_pipe_config [i915]] dpll_hw_state: ctrl1: 0x3, cfgcr1: 0x0, cfgcr2: 0x0
>[13253.944233] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[13253.944244] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 1A] disabled, scaler_id = -1
>[13253.944255] [drm:intel_dump_pipe_config [i915]] [PLANE:31:plane 2A] disabled, scaler_id = -1
>[13253.944266] [drm:intel_dump_pipe_config [i915]] [PLANE:34:cursor A] disabled, scaler_id = -1
>[13253.944280] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[13253.944293] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[13253.944307] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:37:pipe A] has [PLANE:28:plane 1A] with fb 98
>[13253.944320] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 0 -> 1, off 0, on 1, ms 1
>[13253.944334] [drm:intel_find_shared_dpll [i915]] [CRTC:37:pipe A] allocated DPLL 1
>[13253.944347] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[13253.944355] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:47:pipe B] 00000000c85dec7a state to 0000000002434bbd
>[13253.944366] [drm:skl_compute_wm [i915]] [PLANE:28:plane 1A] ddb (0 - 0) -> (0 - 860)
>[13253.944376] [drm:skl_compute_wm [i915]] [PLANE:34:cursor A] ddb (0 - 0) -> (860 - 892)
>[13253.944383] [drm:drm_atomic_commit [drm]] committing 0000000002434bbd
>[13254.944149] [drm:intel_power_well_enable [i915]] enabling power well 2
>[13254.944233] [drm:intel_atomic_commit_tail [i915]] [ENCODER:48:DDI A]
>[13254.944297] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI B]
>[13254.944354] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[13254.944407] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[13254.944458] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DDI C]
>[13254.944508] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST A]
>[13254.944557] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST B]
>[13254.944605] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI D]
>[13254.944653] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[13254.944701] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[13254.944796] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[13254.944864] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[13254.944926] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[13254.944986] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[13254.945055] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 37
>[13254.945114] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[13254.945260] [drm:intel_power_well_enable [i915]] enabling DDI B IO power well
>[13254.945856] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13254.947093] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13254.948329] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13254.949521] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13254.950759] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13254.951621] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[13254.952597] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[13254.952652] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[13254.952702] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[13254.952781] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[13254.971422] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[13254.971452] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[13254.990166] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[13254.990488] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:56:DP-1] Link Training Passed at Link Rate = 270000, Lane count = 4
>[13254.990849] [drm:intel_enable_pipe [i915]] enabling pipe A
>[13254.990878] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS
>[13254.990891] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:56:DP-1], [ENCODER:55:DDI B]
>[13254.990902] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[13254.990915] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[13254.990932] [drm:intel_fbc_enable [i915]] reserved 8294400 bytes of contiguous stolen space for FBC, threshold: 1
>[13254.990944] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[13255.007672] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:56:DP-1]
>[13255.007688] [drm:intel_atomic_commit_tail [i915]] [CRTC:37:pipe A]
>[13255.007708] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[13255.007716] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000002434bbd
>[13255.007722] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000002434bbd
>[13255.007735] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[13255.007740] [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000002434bbd
>[13255.007745] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:37:pipe A] 000000002b48c403 state to 0000000002434bbd
>[13255.007750] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000feda2dba state to 0000000002434bbd
>[13255.007754] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for CRTC state 000000002b48c403
>[13255.007758] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 00000000feda2dba to [NOCRTC]
>[13255.007761] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for plane state 00000000feda2dba
>[13255.007765] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:37:pipe A] to 0000000002434bbd
>[13255.007770] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:56:DP-1] 00000000d1e5643f state to 0000000002434bbd
>[13255.007773] [drm:drm_atomic_set_crtc_for_connector [drm]] Link connector state 00000000d1e5643f to [NOCRTC]
>[13255.007777] [drm:drm_atomic_check_only [drm]] checking 0000000002434bbd
>[13255.007780] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:37:pipe A] mode changed
>[13255.007783] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:37:pipe A] enable changed
>[13255.007785] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:37:pipe A] active changed
>[13255.007787] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:56:DP-1]
>[13255.007789] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Disabling [CONNECTOR:56:DP-1]
>[13255.007791] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:37:pipe A] needs all connectors, enable: n, active: n
>[13255.007795] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:37:pipe A] to 0000000002434bbd
>[13255.007811] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[13255.007824] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[13255.007838] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:37:pipe A] has [PLANE:28:plane 1A] with fb -1
>[13255.007851] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 0, off 1, on 0, ms 1
>[13255.007857] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:47:pipe B] 00000000bd3c0152 state to 0000000002434bbd
>[13255.007868] [drm:skl_compute_wm [i915]] [PLANE:28:plane 1A] ddb (0 - 860) -> (0 - 0)
>[13255.007878] [drm:skl_compute_wm [i915]] [PLANE:34:cursor A] ddb (860 - 892) -> (0 - 0)
>[13255.007883] [drm:drm_atomic_commit [drm]] committing 0000000002434bbd
>[13255.007903] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[13255.007916] [drm:i915_audio_component_get_eld [i915]] Not valid for port B
>[13255.007932] [drm:intel_disable_pipe [i915]] disabling pipe A
>[13255.024929] [drm:intel_power_well_disable [i915]] disabling DDI B IO power well
>[13255.024945] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[13255.024959] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 37
>[13255.024972] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[13255.024992] [drm:intel_atomic_commit_tail [i915]] [ENCODER:48:DDI A]
>[13255.025004] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI B]
>[13255.025017] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[13255.025028] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[13255.025039] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DDI C]
>[13255.025049] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST A]
>[13255.025059] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST B]
>[13255.025070] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI D]
>[13255.025080] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[13255.025090] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[13255.025101] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:56:DP-1]
>[13255.025113] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[13255.025125] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[13255.025136] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[13255.025147] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[13255.025159] [drm:intel_power_well_disable [i915]] disabling power well 2
>[13255.025173] [drm:intel_atomic_commit_tail [i915]] [CRTC:37:pipe A]
>[13255.025181] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000002434bbd
>[13255.025187] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000002434bbd
>[13255.025240] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[13255.025246] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:56:DP-1]
>[13255.025252] [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000002434bbd
>[13255.025257] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:37:pipe A] 00000000c85dec7a state to 0000000002434bbd
>[13255.025262] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000a8722221 state to 0000000002434bbd
>[13255.025267] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [MODE:1920x1080] for CRTC state 00000000c85dec7a
>[13255.025272] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 00000000a8722221 to [CRTC:37:pipe A]
>[13255.025276] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:101] for plane state 00000000a8722221
>[13255.025280] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:37:pipe A] to 0000000002434bbd
>[13255.025284] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:56:DP-1] 00000000fcc1d3f4 state to 0000000002434bbd
>[13255.025288] [drm:drm_atomic_set_crtc_for_connector [drm]] Link connector state 00000000fcc1d3f4 to [CRTC:37:pipe A]
>[13255.025292] [drm:drm_atomic_check_only [drm]] checking 0000000002434bbd
>[13255.025295] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:37:pipe A] mode changed
>[13255.025298] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:37:pipe A] enable changed
>[13255.025300] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:37:pipe A] active changed
>[13255.025302] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:56:DP-1]
>[13255.025321] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:56:DP-1] using [ENCODER:55:DDI B] on [CRTC:37:pipe A]
>[13255.025323] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:37:pipe A] needs all connectors, enable: y, active: y
>[13255.025327] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:37:pipe A] to 0000000002434bbd
>[13255.025332] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:37:pipe A] to 0000000002434bbd
>[13255.025348] [drm:intel_atomic_check [i915]] [CONNECTOR:56:DP-1] checking for sink bpp constrains
>[13255.025363] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 148500KHz
>[13255.025381] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 4 clock 270000 bpp 36
>[13255.025394] [drm:intel_dp_compute_config [i915]] DP link bw required 668250 available 1080000
>[13255.025409] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 36, dithering: 0
>[13255.025423] [drm:intel_dump_pipe_config [i915]] [CRTC:37:pipe A][modeset]
>[13255.025436] [drm:intel_dump_pipe_config [i915]] output_types: DP (0x80)
>[13255.025448] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 36, dithering: 0
>[13255.025461] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5190451, gmch_n: 8388608, link_m: 288358, link_n: 524288, tu: 64
>[13255.025473] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[13255.025484] [drm:intel_dump_pipe_config [i915]] requested mode:
>[13255.025491] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x9
>[13255.025502] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[13255.025508] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x9
>[13255.025521] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x9
>[13255.025533] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500
>[13255.025544] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[13255.025556] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[13255.025567] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[13255.025578] [drm:intel_dump_pipe_config [i915]] dpll_hw_state: ctrl1: 0x3, cfgcr1: 0x0, cfgcr2: 0x0
>[13255.025588] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[13255.025599] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 1A] disabled, scaler_id = -1
>[13255.025610] [drm:intel_dump_pipe_config [i915]] [PLANE:31:plane 2A] disabled, scaler_id = -1
>[13255.025621] [drm:intel_dump_pipe_config [i915]] [PLANE:34:cursor A] disabled, scaler_id = -1
>[13255.025635] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[13255.025648] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[13255.025661] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:37:pipe A] has [PLANE:28:plane 1A] with fb 101
>[13255.025674] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 0 -> 1, off 0, on 1, ms 1
>[13255.025688] [drm:intel_find_shared_dpll [i915]] [CRTC:37:pipe A] allocated DPLL 1
>[13255.025701] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[13255.025709] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:47:pipe B] 00000000b8d65185 state to 0000000002434bbd
>[13255.025720] [drm:skl_compute_wm [i915]] [PLANE:28:plane 1A] ddb (0 - 0) -> (0 - 860)
>[13255.025730] [drm:skl_compute_wm [i915]] [PLANE:34:cursor A] ddb (0 - 0) -> (860 - 892)
>[13255.025736] [drm:drm_atomic_commit [drm]] committing 0000000002434bbd
>[13256.025494] [drm:intel_power_well_enable [i915]] enabling power well 2
>[13256.025578] [drm:intel_atomic_commit_tail [i915]] [ENCODER:48:DDI A]
>[13256.025642] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI B]
>[13256.025698] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[13256.025752] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[13256.025804] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DDI C]
>[13256.025854] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST A]
>[13256.025904] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST B]
>[13256.025953] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI D]
>[13256.026002] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[13256.026049] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[13256.026105] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[13256.026162] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[13256.026215] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[13256.026267] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[13256.026330] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 37
>[13256.026386] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[13256.026526] [drm:intel_power_well_enable [i915]] enabling DDI B IO power well
>[13256.027117] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13256.028353] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13256.029601] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13256.030837] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13256.032075] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13256.032993] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[13256.033970] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[13256.034027] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[13256.034078] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[13256.034128] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[13256.052773] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[13256.052787] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[13256.071487] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[13256.071664] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:56:DP-1] Link Training Passed at Link Rate = 270000, Lane count = 4
>[13256.072041] [drm:intel_enable_pipe [i915]] enabling pipe A
>[13256.072078] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS
>[13256.072091] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:56:DP-1], [ENCODER:55:DDI B]
>[13256.072102] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[13256.072115] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[13256.072132] [drm:intel_fbc_enable [i915]] reserved 8294400 bytes of contiguous stolen space for FBC, threshold: 1
>[13256.072144] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[13256.088821] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:56:DP-1]
>[13256.088837] [drm:intel_atomic_commit_tail [i915]] [CRTC:37:pipe A]
>[13256.088858] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[13256.088867] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000002434bbd
>[13256.088872] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000002434bbd
>[13256.088885] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[13256.088890] [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000002434bbd
>[13256.088896] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:37:pipe A] 00000000bd3c0152 state to 0000000002434bbd
>[13256.088900] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000dbafe848 state to 0000000002434bbd
>[13256.088904] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for CRTC state 00000000bd3c0152
>[13256.088908] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 00000000dbafe848 to [NOCRTC]
>[13256.088912] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for plane state 00000000dbafe848
>[13256.088916] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:37:pipe A] to 0000000002434bbd
>[13256.088920] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:56:DP-1] 00000000de6d4337 state to 0000000002434bbd
>[13256.088924] [drm:drm_atomic_set_crtc_for_connector [drm]] Link connector state 00000000de6d4337 to [NOCRTC]
>[13256.088928] [drm:drm_atomic_check_only [drm]] checking 0000000002434bbd
>[13256.088931] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:37:pipe A] mode changed
>[13256.088933] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:37:pipe A] enable changed
>[13256.088935] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:37:pipe A] active changed
>[13256.088937] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:56:DP-1]
>[13256.088939] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Disabling [CONNECTOR:56:DP-1]
>[13256.088941] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:37:pipe A] needs all connectors, enable: n, active: n
>[13256.088945] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:37:pipe A] to 0000000002434bbd
>[13256.088961] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[13256.088975] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[13256.088989] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:37:pipe A] has [PLANE:28:plane 1A] with fb -1
>[13256.089001] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 0, off 1, on 0, ms 1
>[13256.089008] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:47:pipe B] 000000002b48c403 state to 0000000002434bbd
>[13256.089019] [drm:skl_compute_wm [i915]] [PLANE:28:plane 1A] ddb (0 - 860) -> (0 - 0)
>[13256.089028] [drm:skl_compute_wm [i915]] [PLANE:34:cursor A] ddb (860 - 892) -> (0 - 0)
>[13256.089034] [drm:drm_atomic_commit [drm]] committing 0000000002434bbd
>[13256.089053] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[13256.089066] [drm:i915_audio_component_get_eld [i915]] Not valid for port B
>[13256.089083] [drm:intel_disable_pipe [i915]] disabling pipe A
>[13256.107573] [drm:intel_power_well_disable [i915]] disabling DDI B IO power well
>[13256.107591] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[13256.107607] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 37
>[13256.107621] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[13256.107642] [drm:intel_atomic_commit_tail [i915]] [ENCODER:48:DDI A]
>[13256.107657] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI B]
>[13256.107670] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[13256.107683] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[13256.107695] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DDI C]
>[13256.107706] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST A]
>[13256.107718] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST B]
>[13256.107729] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI D]
>[13256.107741] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[13256.107752] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[13256.107764] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:56:DP-1]
>[13256.107777] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[13256.107790] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[13256.107803] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[13256.107815] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[13256.107827] [drm:intel_power_well_disable [i915]] disabling power well 2
>[13256.107843] [drm:intel_atomic_commit_tail [i915]] [CRTC:37:pipe A]
>[13256.107852] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000002434bbd
>[13256.107859] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000002434bbd
>[13256.107914] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[13256.107921] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:56:DP-1]
>[13256.107927] [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000002434bbd
>[13256.107933] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:37:pipe A] 00000000b8d65185 state to 0000000002434bbd
>[13256.107938] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000feda2dba state to 0000000002434bbd
>[13256.107943] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [MODE:1920x1080] for CRTC state 00000000b8d65185
>[13256.107948] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 00000000feda2dba to [CRTC:37:pipe A]
>[13256.107953] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:98] for plane state 00000000feda2dba
>[13256.107957] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:37:pipe A] to 0000000002434bbd
>[13256.107962] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:56:DP-1] 00000000d1e5643f state to 0000000002434bbd
>[13256.107966] [drm:drm_atomic_set_crtc_for_connector [drm]] Link connector state 00000000d1e5643f to [CRTC:37:pipe A]
>[13256.107971] [drm:drm_atomic_check_only [drm]] checking 0000000002434bbd
>[13256.107975] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:37:pipe A] mode changed
>[13256.107977] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:37:pipe A] enable changed
>[13256.107979] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:37:pipe A] active changed
>[13256.107982] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:56:DP-1]
>[13256.107985] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:56:DP-1] using [ENCODER:55:DDI B] on [CRTC:37:pipe A]
>[13256.107987] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:37:pipe A] needs all connectors, enable: y, active: y
>[13256.107992] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:37:pipe A] to 0000000002434bbd
>[13256.107996] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:37:pipe A] to 0000000002434bbd
>[13256.108013] [drm:intel_atomic_check [i915]] [CONNECTOR:56:DP-1] checking for sink bpp constrains
>[13256.108028] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 148500KHz
>[13256.108046] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 4 clock 270000 bpp 36
>[13256.108059] [drm:intel_dp_compute_config [i915]] DP link bw required 668250 available 1080000
>[13256.108073] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 36, dithering: 0
>[13256.108087] [drm:intel_dump_pipe_config [i915]] [CRTC:37:pipe A][modeset]
>[13256.108100] [drm:intel_dump_pipe_config [i915]] output_types: DP (0x80)
>[13256.108113] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 36, dithering: 0
>[13256.108125] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5190451, gmch_n: 8388608, link_m: 288358, link_n: 524288, tu: 64
>[13256.108136] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[13256.108148] [drm:intel_dump_pipe_config [i915]] requested mode:
>[13256.108154] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x9
>[13256.108166] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[13256.108172] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x9
>[13256.108184] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x9
>[13256.108196] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500
>[13256.108207] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[13256.108219] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[13256.108230] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[13256.108241] [drm:intel_dump_pipe_config [i915]] dpll_hw_state: ctrl1: 0x3, cfgcr1: 0x0, cfgcr2: 0x0
>[13256.108252] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[13256.108263] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 1A] disabled, scaler_id = -1
>[13256.108274] [drm:intel_dump_pipe_config [i915]] [PLANE:31:plane 2A] disabled, scaler_id = -1
>[13256.108285] [drm:intel_dump_pipe_config [i915]] [PLANE:34:cursor A] disabled, scaler_id = -1
>[13256.108299] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[13256.108312] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[13256.108325] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:37:pipe A] has [PLANE:28:plane 1A] with fb 98
>[13256.108338] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 0 -> 1, off 0, on 1, ms 1
>[13256.108352] [drm:intel_find_shared_dpll [i915]] [CRTC:37:pipe A] allocated DPLL 1
>[13256.108365] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[13256.108373] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:47:pipe B] 00000000c85dec7a state to 0000000002434bbd
>[13256.108385] [drm:skl_compute_wm [i915]] [PLANE:28:plane 1A] ddb (0 - 0) -> (0 - 860)
>[13256.108395] [drm:skl_compute_wm [i915]] [PLANE:34:cursor A] ddb (0 - 0) -> (860 - 892)
>[13256.108401] [drm:drm_atomic_commit [drm]] committing 0000000002434bbd
>[13257.108175] [drm:intel_power_well_enable [i915]] enabling power well 2
>[13257.108258] [drm:intel_atomic_commit_tail [i915]] [ENCODER:48:DDI A]
>[13257.108322] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI B]
>[13257.108379] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[13257.108434] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[13257.108486] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DDI C]
>[13257.108537] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST A]
>[13257.108588] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST B]
>[13257.108638] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI D]
>[13257.108688] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[13257.108775] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[13257.108841] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[13257.108908] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[13257.108969] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[13257.109030] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[13257.109098] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 37
>[13257.109156] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[13257.109300] [drm:intel_power_well_enable [i915]] enabling DDI B IO power well
>[13257.109895] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13257.111133] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13257.112368] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13257.113558] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13257.114795] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13257.115650] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[13257.116626] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[13257.116682] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[13257.116764] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[13257.116824] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[13257.135459] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[13257.135488] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[13257.153315] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[13257.153638] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:56:DP-1] Link Training Passed at Link Rate = 270000, Lane count = 4
>[13257.153999] [drm:intel_enable_pipe [i915]] enabling pipe A
>[13257.154028] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS
>[13257.154041] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:56:DP-1], [ENCODER:55:DDI B]
>[13257.154052] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[13257.154065] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[13257.154082] [drm:intel_fbc_enable [i915]] reserved 8294400 bytes of contiguous stolen space for FBC, threshold: 1
>[13257.154094] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[13257.170815] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:56:DP-1]
>[13257.170831] [drm:intel_atomic_commit_tail [i915]] [CRTC:37:pipe A]
>[13257.170851] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[13257.170860] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000002434bbd
>[13257.170865] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000002434bbd
>[13257.170879] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[13257.170884] [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000002434bbd
>[13257.170889] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:37:pipe A] 000000002b48c403 state to 0000000002434bbd
>[13257.170893] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000a8722221 state to 0000000002434bbd
>[13257.170898] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for CRTC state 000000002b48c403
>[13257.170901] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 00000000a8722221 to [NOCRTC]
>[13257.170905] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for plane state 00000000a8722221
>[13257.170909] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:37:pipe A] to 0000000002434bbd
>[13257.170913] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:56:DP-1] 00000000f8eadac6 state to 0000000002434bbd
>[13257.170917] [drm:drm_atomic_set_crtc_for_connector [drm]] Link connector state 00000000f8eadac6 to [NOCRTC]
>[13257.170921] [drm:drm_atomic_check_only [drm]] checking 0000000002434bbd
>[13257.170924] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:37:pipe A] mode changed
>[13257.170926] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:37:pipe A] enable changed
>[13257.170928] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:37:pipe A] active changed
>[13257.170930] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:56:DP-1]
>[13257.170932] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Disabling [CONNECTOR:56:DP-1]
>[13257.170934] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:37:pipe A] needs all connectors, enable: n, active: n
>[13257.170938] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:37:pipe A] to 0000000002434bbd
>[13257.170954] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[13257.170968] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[13257.170982] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:37:pipe A] has [PLANE:28:plane 1A] with fb -1
>[13257.170994] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 0, off 1, on 0, ms 1
>[13257.171001] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:47:pipe B] 00000000bd3c0152 state to 0000000002434bbd
>[13257.171012] [drm:skl_compute_wm [i915]] [PLANE:28:plane 1A] ddb (0 - 860) -> (0 - 0)
>[13257.171022] [drm:skl_compute_wm [i915]] [PLANE:34:cursor A] ddb (860 - 892) -> (0 - 0)
>[13257.171027] [drm:drm_atomic_commit [drm]] committing 0000000002434bbd
>[13257.171046] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[13257.171060] [drm:i915_audio_component_get_eld [i915]] Not valid for port B
>[13257.171077] [drm:intel_disable_pipe [i915]] disabling pipe A
>[13257.187568] [drm:intel_power_well_disable [i915]] disabling DDI B IO power well
>[13257.187586] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[13257.187601] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 37
>[13257.187615] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[13257.187637] [drm:intel_atomic_commit_tail [i915]] [ENCODER:48:DDI A]
>[13257.187650] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI B]
>[13257.187663] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[13257.187676] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[13257.187687] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DDI C]
>[13257.187699] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST A]
>[13257.187710] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST B]
>[13257.187721] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI D]
>[13257.187732] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[13257.187743] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[13257.187755] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:56:DP-1]
>[13257.187768] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[13257.187781] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[13257.187793] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[13257.187805] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[13257.187818] [drm:intel_power_well_disable [i915]] disabling power well 2
>[13257.187833] [drm:intel_atomic_commit_tail [i915]] [CRTC:37:pipe A]
>[13257.187842] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000002434bbd
>[13257.187848] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000002434bbd
>[13257.187904] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[13257.187910] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:56:DP-1]
>[13257.187916] [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000002434bbd
>[13257.187922] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:37:pipe A] 00000000c85dec7a state to 0000000002434bbd
>[13257.187927] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000dbafe848 state to 0000000002434bbd
>[13257.187933] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [MODE:1920x1080] for CRTC state 00000000c85dec7a
>[13257.187937] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 00000000dbafe848 to [CRTC:37:pipe A]
>[13257.187942] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:101] for plane state 00000000dbafe848
>[13257.187946] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:37:pipe A] to 0000000002434bbd
>[13257.187951] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:56:DP-1] 00000000de6d4337 state to 0000000002434bbd
>[13257.187955] [drm:drm_atomic_set_crtc_for_connector [drm]] Link connector state 00000000de6d4337 to [CRTC:37:pipe A]
>[13257.187959] [drm:drm_atomic_check_only [drm]] checking 0000000002434bbd
>[13257.187963] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:37:pipe A] mode changed
>[13257.187965] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:37:pipe A] enable changed
>[13257.187967] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:37:pipe A] active changed
>[13257.187970] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:56:DP-1]
>[13257.187972] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:56:DP-1] using [ENCODER:55:DDI B] on [CRTC:37:pipe A]
>[13257.187975] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:37:pipe A] needs all connectors, enable: y, active: y
>[13257.187979] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:37:pipe A] to 0000000002434bbd
>[13257.187984] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:37:pipe A] to 0000000002434bbd
>[13257.188000] [drm:intel_atomic_check [i915]] [CONNECTOR:56:DP-1] checking for sink bpp constrains
>[13257.188015] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 148500KHz
>[13257.188033] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 4 clock 270000 bpp 36
>[13257.188047] [drm:intel_dp_compute_config [i915]] DP link bw required 668250 available 1080000
>[13257.188061] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 36, dithering: 0
>[13257.188075] [drm:intel_dump_pipe_config [i915]] [CRTC:37:pipe A][modeset]
>[13257.188088] [drm:intel_dump_pipe_config [i915]] output_types: DP (0x80)
>[13257.188101] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 36, dithering: 0
>[13257.188113] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5190451, gmch_n: 8388608, link_m: 288358, link_n: 524288, tu: 64
>[13257.188125] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[13257.188136] [drm:intel_dump_pipe_config [i915]] requested mode:
>[13257.188142] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x9
>[13257.188154] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[13257.188160] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x9
>[13257.188173] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x9
>[13257.188185] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500
>[13257.188196] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[13257.188207] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[13257.188218] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[13257.188229] [drm:intel_dump_pipe_config [i915]] dpll_hw_state: ctrl1: 0x3, cfgcr1: 0x0, cfgcr2: 0x0
>[13257.188240] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[13257.188251] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 1A] disabled, scaler_id = -1
>[13257.188262] [drm:intel_dump_pipe_config [i915]] [PLANE:31:plane 2A] disabled, scaler_id = -1
>[13257.188272] [drm:intel_dump_pipe_config [i915]] [PLANE:34:cursor A] disabled, scaler_id = -1
>[13257.188286] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[13257.188299] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[13257.188313] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:37:pipe A] has [PLANE:28:plane 1A] with fb 101
>[13257.188325] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 0 -> 1, off 0, on 1, ms 1
>[13257.188339] [drm:intel_find_shared_dpll [i915]] [CRTC:37:pipe A] allocated DPLL 1
>[13257.188352] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[13257.188360] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:47:pipe B] 00000000b8d65185 state to 0000000002434bbd
>[13257.188371] [drm:skl_compute_wm [i915]] [PLANE:28:plane 1A] ddb (0 - 0) -> (0 - 860)
>[13257.188381] [drm:skl_compute_wm [i915]] [PLANE:34:cursor A] ddb (0 - 0) -> (860 - 892)
>[13257.188387] [drm:drm_atomic_commit [drm]] committing 0000000002434bbd
>[13258.188165] [drm:intel_power_well_enable [i915]] enabling power well 2
>[13258.188248] [drm:intel_atomic_commit_tail [i915]] [ENCODER:48:DDI A]
>[13258.188313] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI B]
>[13258.188370] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[13258.188424] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[13258.188476] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DDI C]
>[13258.188526] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST A]
>[13258.188576] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST B]
>[13258.188625] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI D]
>[13258.188674] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[13258.188763] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[13258.188829] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[13258.188894] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[13258.188952] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[13258.189012] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[13258.189080] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 37
>[13258.189139] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[13258.189283] [drm:intel_power_well_enable [i915]] enabling DDI B IO power well
>[13258.189879] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13258.191115] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13258.192353] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13258.193545] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13258.194783] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13258.195639] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[13258.196613] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[13258.196668] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[13258.196718] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[13258.196798] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[13258.215454] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[13258.215467] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[13258.233287] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[13258.233609] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:56:DP-1] Link Training Passed at Link Rate = 270000, Lane count = 4
>[13258.233971] [drm:intel_enable_pipe [i915]] enabling pipe A
>[13258.234000] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS
>[13258.234012] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:56:DP-1], [ENCODER:55:DDI B]
>[13258.234023] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[13258.234036] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[13258.234054] [drm:intel_fbc_enable [i915]] reserved 8294400 bytes of contiguous stolen space for FBC, threshold: 1
>[13258.234065] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[13258.250787] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:56:DP-1]
>[13258.250803] [drm:intel_atomic_commit_tail [i915]] [CRTC:37:pipe A]
>[13258.250824] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[13258.250832] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000002434bbd
>[13258.250837] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000002434bbd
>[13258.250851] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[13258.250856] [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000002434bbd
>[13258.250861] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:37:pipe A] 00000000bd3c0152 state to 0000000002434bbd
>[13258.250865] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000feda2dba state to 0000000002434bbd
>[13258.250870] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for CRTC state 00000000bd3c0152
>[13258.250873] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 00000000feda2dba to [NOCRTC]
>[13258.250877] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for plane state 00000000feda2dba
>[13258.250881] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:37:pipe A] to 0000000002434bbd
>[13258.250885] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:56:DP-1] 00000000fcc1d3f4 state to 0000000002434bbd
>[13258.250889] [drm:drm_atomic_set_crtc_for_connector [drm]] Link connector state 00000000fcc1d3f4 to [NOCRTC]
>[13258.250893] [drm:drm_atomic_check_only [drm]] checking 0000000002434bbd
>[13258.250896] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:37:pipe A] mode changed
>[13258.250899] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:37:pipe A] enable changed
>[13258.250901] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:37:pipe A] active changed
>[13258.250903] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:56:DP-1]
>[13258.250905] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Disabling [CONNECTOR:56:DP-1]
>[13258.250907] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:37:pipe A] needs all connectors, enable: n, active: n
>[13258.250911] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:37:pipe A] to 0000000002434bbd
>[13258.250927] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[13258.250941] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[13258.250955] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:37:pipe A] has [PLANE:28:plane 1A] with fb -1
>[13258.250968] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 0, off 1, on 0, ms 1
>[13258.250974] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:47:pipe B] 000000002b48c403 state to 0000000002434bbd
>[13258.250985] [drm:skl_compute_wm [i915]] [PLANE:28:plane 1A] ddb (0 - 860) -> (0 - 0)
>[13258.250995] [drm:skl_compute_wm [i915]] [PLANE:34:cursor A] ddb (860 - 892) -> (0 - 0)
>[13258.251000] [drm:drm_atomic_commit [drm]] committing 0000000002434bbd
>[13258.251020] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[13258.251033] [drm:i915_audio_component_get_eld [i915]] Not valid for port B
>[13258.251050] [drm:intel_disable_pipe [i915]] disabling pipe A
>[13258.267579] [drm:intel_power_well_disable [i915]] disabling DDI B IO power well
>[13258.267597] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[13258.267612] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 37
>[13258.267626] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[13258.267648] [drm:intel_atomic_commit_tail [i915]] [ENCODER:48:DDI A]
>[13258.267661] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI B]
>[13258.267674] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[13258.267687] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[13258.267699] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DDI C]
>[13258.267711] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST A]
>[13258.267722] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST B]
>[13258.267733] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI D]
>[13258.267745] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[13258.267756] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[13258.267768] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:56:DP-1]
>[13258.267781] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[13258.267794] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[13258.267807] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[13258.267819] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[13258.267831] [drm:intel_power_well_disable [i915]] disabling power well 2
>[13258.267846] [drm:intel_atomic_commit_tail [i915]] [CRTC:37:pipe A]
>[13258.267856] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000002434bbd
>[13258.267862] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000002434bbd
>[13258.267917] [drm:drm_mode_addfb2 [drm]] [FB:98]
>[13258.267926] [drm:drm_mode_addfb2 [drm]] [FB:99]
>[13258.283410] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[13258.283420] [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000002434bbd
>[13258.283428] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:37:pipe A] 00000000c85dec7a state to 0000000002434bbd
>[13258.283434] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000dbafe848 state to 0000000002434bbd
>[13258.283440] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for CRTC state 00000000c85dec7a
>[13258.283445] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 00000000dbafe848 to [NOCRTC]
>[13258.283450] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for plane state 00000000dbafe848
>[13258.283454] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:37:pipe A] to 0000000002434bbd
>[13258.283460] [drm:drm_atomic_check_only [drm]] checking 0000000002434bbd
>[13258.283467] [drm:drm_atomic_commit [drm]] committing 0000000002434bbd
>[13258.283481] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000002434bbd
>[13258.283486] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000002434bbd
>[13258.283493] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[13258.283498] [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000002434bbd
>[13258.283503] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:47:pipe B] 00000000bd3c0152 state to 0000000002434bbd
>[13258.283508] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:38:plane 1B] 00000000feda2dba state to 0000000002434bbd
>[13258.283512] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for CRTC state 00000000bd3c0152
>[13258.283517] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 00000000feda2dba to [NOCRTC]
>[13258.283521] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for plane state 00000000feda2dba
>[13258.283525] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:47:pipe B] to 0000000002434bbd
>[13258.283530] [drm:drm_atomic_check_only [drm]] checking 0000000002434bbd
>[13258.283535] [drm:drm_atomic_commit [drm]] committing 0000000002434bbd
>[13258.283543] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000002434bbd
>[13258.283547] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000002434bbd
>[13258.283553] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[13258.283560] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:56:DP-1]
>[13258.283565] [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000002434bbd
>[13258.283569] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:47:pipe B] 000000002b48c403 state to 0000000002434bbd
>[13258.283574] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:38:plane 1B] 00000000a8722221 state to 0000000002434bbd
>[13258.283578] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [MODE:1920x1080] for CRTC state 000000002b48c403
>[13258.283583] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 00000000a8722221 to [CRTC:47:pipe B]
>[13258.283587] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:98] for plane state 00000000a8722221
>[13258.283591] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:47:pipe B] to 0000000002434bbd
>[13258.283596] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:56:DP-1] 00000000f8eadac6 state to 0000000002434bbd
>[13258.283600] [drm:drm_atomic_set_crtc_for_connector [drm]] Link connector state 00000000f8eadac6 to [CRTC:47:pipe B]
>[13258.283605] [drm:drm_atomic_check_only [drm]] checking 0000000002434bbd
>[13258.283610] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:47:pipe B] mode changed
>[13258.283613] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:47:pipe B] enable changed
>[13258.283616] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:47:pipe B] active changed
>[13258.283618] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:56:DP-1]
>[13258.283621] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:56:DP-1] using [ENCODER:55:DDI B] on [CRTC:47:pipe B]
>[13258.283624] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:47:pipe B] needs all connectors, enable: y, active: y
>[13258.283629] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:47:pipe B] to 0000000002434bbd
>[13258.283634] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:47:pipe B] to 0000000002434bbd
>[13258.283654] [drm:intel_atomic_check [i915]] [CONNECTOR:56:DP-1] checking for sink bpp constrains
>[13258.283673] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 148500KHz
>[13258.283693] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 4 clock 270000 bpp 36
>[13258.283708] [drm:intel_dp_compute_config [i915]] DP link bw required 668250 available 1080000
>[13258.283725] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 36, dithering: 0
>[13258.283740] [drm:intel_dump_pipe_config [i915]] [CRTC:47:pipe B][modeset]
>[13258.283755] [drm:intel_dump_pipe_config [i915]] output_types: DP (0x80)
>[13258.283769] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 36, dithering: 0
>[13258.283783] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5190451, gmch_n: 8388608, link_m: 288358, link_n: 524288, tu: 64
>[13258.283796] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[13258.283808] [drm:intel_dump_pipe_config [i915]] requested mode:
>[13258.283815] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x9
>[13258.283828] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[13258.283835] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x9
>[13258.283848] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x9
>[13258.283861] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500
>[13258.283874] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[13258.283886] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[13258.283898] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[13258.283911] [drm:intel_dump_pipe_config [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[13258.283923] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[13258.283935] [drm:intel_dump_pipe_config [i915]] [PLANE:38:plane 1B] disabled, scaler_id = -1
>[13258.283947] [drm:intel_dump_pipe_config [i915]] [PLANE:41:plane 2B] disabled, scaler_id = -1
>[13258.283959] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor B] disabled, scaler_id = -1
>[13258.283974] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[13258.283988] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[13258.284004] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:47:pipe B] has [PLANE:38:plane 1B] with fb 98
>[13258.284018] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:38:plane 1B] visible 0 -> 1, off 0, on 1, ms 1
>[13258.284033] [drm:intel_find_shared_dpll [i915]] [CRTC:47:pipe B] allocated DPLL 1
>[13258.284047] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[13258.284055] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:37:pipe A] 00000000604357f6 state to 0000000002434bbd
>[13258.284069] [drm:skl_compute_wm [i915]] [PLANE:38:plane 1B] ddb (0 - 0) -> (0 - 860)
>[13258.284080] [drm:skl_compute_wm [i915]] [PLANE:44:cursor B] ddb (0 - 0) -> (860 - 892)
>[13258.284086] [drm:drm_atomic_commit [drm]] committing 0000000002434bbd
>[13258.284410] [drm:intel_power_well_enable [i915]] enabling power well 2
>[13258.284430] [drm:intel_atomic_commit_tail [i915]] [ENCODER:48:DDI A]
>[13258.284445] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI B]
>[13258.284458] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[13258.284471] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[13258.284484] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DDI C]
>[13258.284496] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST A]
>[13258.284508] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST B]
>[13258.284520] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI D]
>[13258.284532] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[13258.284544] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[13258.284558] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[13258.284572] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[13258.284585] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[13258.284598] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[13258.284614] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 2, on? 0) for crtc 47
>[13258.284628] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[13258.284762] [drm:intel_power_well_enable [i915]] enabling DDI B IO power well
>[13258.285325] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13258.286548] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13258.287771] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13258.288986] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13258.290212] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13258.291026] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[13258.291932] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[13258.291946] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[13258.291959] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[13258.291973] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[13258.310588] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[13258.310602] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[13258.328339] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[13258.328662] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:56:DP-1] Link Training Passed at Link Rate = 270000, Lane count = 4
>[13258.329036] [drm:intel_enable_pipe [i915]] enabling pipe B
>[13258.329083] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS
>[13258.329095] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:56:DP-1], [ENCODER:55:DDI B]
>[13258.329107] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[13258.329120] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[13258.345880] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:56:DP-1]
>[13258.345896] [drm:intel_atomic_commit_tail [i915]] [CRTC:47:pipe B]
>[13258.345917] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[13258.345925] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000002434bbd
>[13258.345931] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000002434bbd
>[13258.345939] [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000002434bbd
>[13258.345944] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:47:pipe B] 00000000bd3c0152 state to 0000000002434bbd
>[13258.345949] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:38:plane 1B] 00000000e4c2821e state to 0000000002434bbd
>[13258.345953] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 00000000e4c2821e to [CRTC:47:pipe B]
>[13258.345957] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:99] for plane state 00000000e4c2821e
>[13258.345960] [drm:drm_atomic_check_only [drm]] checking 0000000002434bbd
>[13258.345976] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:47:pipe B] has [PLANE:38:plane 1B] with fb 99
>[13258.345989] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:38:plane 1B] visible 1 -> 1, off 0, on 0, ms 0
>[13258.345996] [drm:drm_atomic_nonblocking_commit [drm]] committing 0000000002434bbd nonblocking
>[13258.362524] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000002434bbd
>[13258.362531] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000002434bbd
>[13258.362615] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[13258.362621] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:56:DP-1]
>[13258.362628] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000006202e550
>[13258.362635] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:47:pipe B] 000000006794fe06 state to 000000006202e550
>[13258.362639] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:38:plane 1B] 00000000526a3ced state to 000000006202e550
>[13258.362645] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [MODE:1920x1080] for CRTC state 000000006794fe06
>[13258.362649] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 00000000526a3ced to [CRTC:47:pipe B]
>[13258.362653] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:98] for plane state 00000000526a3ced
>[13258.362657] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:47:pipe B] to 000000006202e550
>[13258.362662] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:56:DP-1] 000000000faf882c state to 000000006202e550
>[13258.362666] [drm:drm_atomic_set_crtc_for_connector [drm]] Link connector state 000000000faf882c to [NOCRTC]
>[13258.362670] [drm:drm_atomic_set_crtc_for_connector [drm]] Link connector state 000000000faf882c to [CRTC:47:pipe B]
>[13258.362674] [drm:drm_atomic_check_only [drm]] checking 000000006202e550
>[13258.362678] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:56:DP-1]
>[13258.362681] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:56:DP-1] keeps [ENCODER:55:DDI B], now on [CRTC:47:pipe B]
>[13258.362699] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:47:pipe B] has [PLANE:38:plane 1B] with fb 98
>[13258.362714] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:38:plane 1B] visible 1 -> 1, off 0, on 0, ms 0
>[13258.362721] [drm:drm_atomic_commit [drm]] committing 000000006202e550
>[13259.379164] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000006202e550
>[13259.379194] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000006202e550
>[13259.379255] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[13259.379279] [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000002434bbd
>[13259.379304] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:47:pipe B] 00000000bd3c0152 state to 0000000002434bbd
>[13259.379324] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:38:plane 1B] 00000000e4c2821e state to 0000000002434bbd
>[13259.379344] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for CRTC state 00000000bd3c0152
>[13259.379362] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 00000000e4c2821e to [NOCRTC]
>[13259.379380] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for plane state 00000000e4c2821e
>[13259.379399] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:47:pipe B] to 0000000002434bbd
>[13259.379418] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:56:DP-1] 00000000de6d4337 state to 0000000002434bbd
>[13259.379436] [drm:drm_atomic_set_crtc_for_connector [drm]] Link connector state 00000000de6d4337 to [NOCRTC]
>[13259.379453] [drm:drm_atomic_check_only [drm]] checking 0000000002434bbd
>[13259.379469] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:47:pipe B] mode changed
>[13259.379480] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:47:pipe B] enable changed
>[13259.379489] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:47:pipe B] active changed
>[13259.379499] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:56:DP-1]
>[13259.379508] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Disabling [CONNECTOR:56:DP-1]
>[13259.379518] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:47:pipe B] needs all connectors, enable: n, active: n
>[13259.379537] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:47:pipe B] to 0000000002434bbd
>[13259.379615] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[13259.379684] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[13259.379751] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:47:pipe B] has [PLANE:38:plane 1B] with fb -1
>[13259.379813] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:38:plane 1B] visible 1 -> 0, off 1, on 0, ms 1
>[13259.379841] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:37:pipe A] 000000002b48c403 state to 0000000002434bbd
>[13259.379893] [drm:skl_compute_wm [i915]] [PLANE:38:plane 1B] ddb (0 - 860) -> (0 - 0)
>[13259.379939] [drm:skl_compute_wm [i915]] [PLANE:44:cursor B] ddb (860 - 892) -> (0 - 0)
>[13259.379963] [drm:drm_atomic_commit [drm]] committing 0000000002434bbd
>[13259.380053] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[13259.380114] [drm:i915_audio_component_get_eld [i915]] Not valid for port B
>[13259.380190] [drm:intel_disable_pipe [i915]] disabling pipe B
>[13259.396184] [drm:intel_power_well_disable [i915]] disabling DDI B IO power well
>[13259.396256] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 2, on? 1) for crtc 47
>[13259.396317] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[13259.396389] [drm:intel_atomic_commit_tail [i915]] [ENCODER:48:DDI A]
>[13259.396443] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI B]
>[13259.396496] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[13259.396543] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[13259.396590] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DDI C]
>[13259.396636] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST A]
>[13259.396682] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST B]
>[13259.396761] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI D]
>[13259.396817] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[13259.396872] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[13259.396930] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:56:DP-1]
>[13259.396989] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[13259.397046] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[13259.397098] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[13259.397149] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[13259.397201] [drm:intel_power_well_disable [i915]] disabling power well 2
>[13259.397260] [drm:intel_atomic_commit_tail [i915]] [CRTC:47:pipe B]
>[13259.397296] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000002434bbd
>[13259.397326] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000002434bbd
>[13259.397552] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[13259.397577] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:56:DP-1]
>[13259.397602] [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000002434bbd
>[13259.397628] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:47:pipe B] 00000000604357f6 state to 0000000002434bbd
>[13259.397650] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:38:plane 1B] 00000000feda2dba state to 0000000002434bbd
>[13259.397672] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [MODE:1920x1080] for CRTC state 00000000604357f6
>[13259.397692] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 00000000feda2dba to [CRTC:47:pipe B]
>[13259.397711] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:99] for plane state 00000000feda2dba
>[13259.397729] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:47:pipe B] to 0000000002434bbd
>[13259.397750] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:56:DP-1] 00000000f8eadac6 state to 0000000002434bbd
>[13259.397766] [drm:drm_atomic_set_crtc_for_connector [drm]] Link connector state 00000000f8eadac6 to [CRTC:47:pipe B]
>[13259.397785] [drm:drm_atomic_check_only [drm]] checking 0000000002434bbd
>[13259.397801] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:47:pipe B] mode changed
>[13259.397811] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:47:pipe B] enable changed
>[13259.397820] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:47:pipe B] active changed
>[13259.397832] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:56:DP-1]
>[13259.397842] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:56:DP-1] using [ENCODER:55:DDI B] on [CRTC:47:pipe B]
>[13259.397852] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:47:pipe B] needs all connectors, enable: y, active: y
>[13259.397870] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:47:pipe B] to 0000000002434bbd
>[13259.397890] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:47:pipe B] to 0000000002434bbd
>[13259.397955] [drm:intel_atomic_check [i915]] [CONNECTOR:56:DP-1] checking for sink bpp constrains
>[13259.398019] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 148500KHz
>[13259.398093] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 4 clock 270000 bpp 36
>[13259.398148] [drm:intel_dp_compute_config [i915]] DP link bw required 668250 available 1080000
>[13259.398209] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 36, dithering: 0
>[13259.398268] [drm:intel_dump_pipe_config [i915]] [CRTC:47:pipe B][modeset]
>[13259.398324] [drm:intel_dump_pipe_config [i915]] output_types: DP (0x80)
>[13259.398375] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 36, dithering: 0
>[13259.398427] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5190451, gmch_n: 8388608, link_m: 288358, link_n: 524288, tu: 64
>[13259.398476] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[13259.398525] [drm:intel_dump_pipe_config [i915]] requested mode:
>[13259.398552] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x9
>[13259.398603] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[13259.398627] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x9
>[13259.398680] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x9
>[13259.398728] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500
>[13259.398776] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[13259.398823] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[13259.398869] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[13259.398915] [drm:intel_dump_pipe_config [i915]] dpll_hw_state: ctrl1: 0x3, cfgcr1: 0x0, cfgcr2: 0x0
>[13259.398961] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[13259.399005] [drm:intel_dump_pipe_config [i915]] [PLANE:38:plane 1B] disabled, scaler_id = -1
>[13259.399050] [drm:intel_dump_pipe_config [i915]] [PLANE:41:plane 2B] disabled, scaler_id = -1
>[13259.399094] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor B] disabled, scaler_id = -1
>[13259.399152] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[13259.399203] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[13259.399261] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:47:pipe B] has [PLANE:38:plane 1B] with fb 99
>[13259.399314] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:38:plane 1B] visible 0 -> 1, off 0, on 1, ms 1
>[13259.399372] [drm:intel_find_shared_dpll [i915]] [CRTC:47:pipe B] allocated DPLL 1
>[13259.399424] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[13259.399456] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:37:pipe A] 00000000c85dec7a state to 0000000002434bbd
>[13259.399505] [drm:skl_compute_wm [i915]] [PLANE:38:plane 1B] ddb (0 - 0) -> (0 - 860)
>[13259.399547] [drm:skl_compute_wm [i915]] [PLANE:44:cursor B] ddb (0 - 0) -> (860 - 892)
>[13259.399573] [drm:drm_atomic_commit [drm]] committing 0000000002434bbd
>[13259.816087] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[13259.816158] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[13259.816256] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[13259.816316] [drm:intel_power_well_enable [i915]] enabling power well 2
>[13260.397814] [drm:intel_atomic_commit_tail [i915]] [ENCODER:48:DDI A]
>[13260.397880] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI B]
>[13260.397938] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[13260.397992] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[13260.398043] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DDI C]
>[13260.398094] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST A]
>[13260.398144] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST B]
>[13260.398193] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI D]
>[13260.398243] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[13260.398292] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[13260.398347] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[13260.398403] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[13260.398456] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[13260.398507] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[13260.398570] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 2, on? 0) for crtc 47
>[13260.398627] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[13260.398769] [drm:intel_power_well_enable [i915]] enabling DDI B IO power well
>[13260.399362] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13260.400598] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13260.401841] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13260.403069] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13260.404306] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13260.405124] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[13260.406096] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[13260.406151] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[13260.406203] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[13260.406253] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[13260.424868] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[13260.424882] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[13260.443582] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[13260.443904] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:56:DP-1] Link Training Passed at Link Rate = 270000, Lane count = 4
>[13260.444294] [drm:intel_enable_pipe [i915]] enabling pipe B
>[13260.444324] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS
>[13260.444337] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:56:DP-1], [ENCODER:55:DDI B]
>[13260.444348] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[13260.444361] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[13260.461099] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:56:DP-1]
>[13260.461115] [drm:intel_atomic_commit_tail [i915]] [CRTC:47:pipe B]
>[13260.461135] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[13260.461144] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000002434bbd
>[13260.461149] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000002434bbd
>[13260.461164] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[13260.461169] [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000002434bbd
>[13260.461174] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:47:pipe B] 00000000bd3c0152 state to 0000000002434bbd
>[13260.461179] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:38:plane 1B] 00000000a8722221 state to 0000000002434bbd
>[13260.461183] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for CRTC state 00000000bd3c0152
>[13260.461187] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 00000000a8722221 to [NOCRTC]
>[13260.461191] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for plane state 00000000a8722221
>[13260.461195] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:47:pipe B] to 0000000002434bbd
>[13260.461199] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:56:DP-1] 000000005a636f37 state to 0000000002434bbd
>[13260.461203] [drm:drm_atomic_set_crtc_for_connector [drm]] Link connector state 000000005a636f37 to [NOCRTC]
>[13260.461207] [drm:drm_atomic_check_only [drm]] checking 0000000002434bbd
>[13260.461210] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:47:pipe B] mode changed
>[13260.461212] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:47:pipe B] enable changed
>[13260.461214] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:47:pipe B] active changed
>[13260.461216] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:56:DP-1]
>[13260.461218] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Disabling [CONNECTOR:56:DP-1]
>[13260.461220] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:47:pipe B] needs all connectors, enable: n, active: n
>[13260.461224] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:47:pipe B] to 0000000002434bbd
>[13260.461240] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[13260.461254] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[13260.461268] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:47:pipe B] has [PLANE:38:plane 1B] with fb -1
>[13260.461280] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:38:plane 1B] visible 1 -> 0, off 1, on 0, ms 1
>[13260.461286] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:37:pipe A] 000000002b48c403 state to 0000000002434bbd
>[13260.461297] [drm:skl_compute_wm [i915]] [PLANE:38:plane 1B] ddb (0 - 860) -> (0 - 0)
>[13260.461307] [drm:skl_compute_wm [i915]] [PLANE:44:cursor B] ddb (860 - 892) -> (0 - 0)
>[13260.461312] [drm:drm_atomic_commit [drm]] committing 0000000002434bbd
>[13260.461332] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[13260.461345] [drm:i915_audio_component_get_eld [i915]] Not valid for port B
>[13260.461362] [drm:intel_disable_pipe [i915]] disabling pipe B
>[13260.479555] [drm:intel_power_well_disable [i915]] disabling DDI B IO power well
>[13260.479573] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 2, on? 1) for crtc 47
>[13260.479589] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[13260.479611] [drm:intel_atomic_commit_tail [i915]] [ENCODER:48:DDI A]
>[13260.479625] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI B]
>[13260.479638] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[13260.479650] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[13260.479662] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DDI C]
>[13260.479674] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST A]
>[13260.479685] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST B]
>[13260.479696] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI D]
>[13260.479707] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[13260.479718] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[13260.479731] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:56:DP-1]
>[13260.479743] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[13260.479756] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[13260.479768] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[13260.479780] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[13260.479795] [drm:intel_atomic_commit_tail [i915]] [CRTC:47:pipe B]
>[13260.479805] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000002434bbd
>[13260.479811] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000002434bbd
>[13260.479876] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[13260.480250] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 00 00 04 00 0f 00 04
>[13260.480537] [drm:intel_power_well_disable [i915]] disabling power well 2
>[13260.480545] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:56:DP-1]
>[13260.480553] [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000001fbffed
>[13260.480561] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:47:pipe B] 0000000081e9cf65 state to 0000000001fbffed
>[13260.480566] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:38:plane 1B] 000000002969d135 state to 0000000001fbffed
>[13260.480572] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [MODE:1920x1080] for CRTC state 0000000081e9cf65
>[13260.480577] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 000000002969d135 to [CRTC:47:pipe B]
>[13260.480582] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:98] for plane state 000000002969d135
>[13260.480586] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:47:pipe B] to 0000000001fbffed
>[13260.480591] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:56:DP-1] 00000000e8f304c8 state to 0000000001fbffed
>[13260.480596] [drm:drm_atomic_set_crtc_for_connector [drm]] Link connector state 00000000e8f304c8 to [CRTC:47:pipe B]
>[13260.480601] [drm:drm_atomic_check_only [drm]] checking 0000000001fbffed
>[13260.480606] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:47:pipe B] mode changed
>[13260.480608] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:47:pipe B] enable changed
>[13260.480611] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:47:pipe B] active changed
>[13260.480613] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:56:DP-1]
>[13260.480616] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:56:DP-1] using [ENCODER:55:DDI B] on [CRTC:47:pipe B]
>[13260.480619] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:47:pipe B] needs all connectors, enable: y, active: y
>[13260.480624] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:47:pipe B] to 0000000001fbffed
>[13260.480629] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:47:pipe B] to 0000000001fbffed
>[13260.480648] [drm:intel_atomic_check [i915]] [CONNECTOR:56:DP-1] checking for sink bpp constrains
>[13260.480666] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 148500KHz
>[13260.480697] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 4 clock 270000 bpp 36
>[13260.480712] [drm:intel_dp_compute_config [i915]] DP link bw required 668250 available 1080000
>[13260.480729] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 36, dithering: 0
>[13260.480749] [drm:intel_dump_pipe_config [i915]] [CRTC:47:pipe B][modeset]
>[13260.480766] [drm:intel_dump_pipe_config [i915]] output_types: DP (0x80)
>[13260.480782] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 36, dithering: 0
>[13260.480798] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5190451, gmch_n: 8388608, link_m: 288358, link_n: 524288, tu: 64
>[13260.480813] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[13260.480828] [drm:intel_dump_pipe_config [i915]] requested mode:
>[13260.480838] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x9
>[13260.480854] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[13260.480863] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x9
>[13260.480880] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x9
>[13260.480895] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500
>[13260.480910] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[13260.480924] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[13260.480940] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[13260.480954] [drm:intel_dump_pipe_config [i915]] dpll_hw_state: ctrl1: 0x3, cfgcr1: 0x0, cfgcr2: 0x0
>[13260.480969] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[13260.480983] [drm:intel_dump_pipe_config [i915]] [PLANE:38:plane 1B] disabled, scaler_id = -1
>[13260.480998] [drm:intel_dump_pipe_config [i915]] [PLANE:41:plane 2B] disabled, scaler_id = -1
>[13260.481012] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor B] disabled, scaler_id = -1
>[13260.481029] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[13260.481046] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[13260.481064] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:47:pipe B] has [PLANE:38:plane 1B] with fb 98
>[13260.481079] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:38:plane 1B] visible 0 -> 1, off 0, on 1, ms 1
>[13260.481097] [drm:intel_find_shared_dpll [i915]] [CRTC:47:pipe B] allocated DPLL 1
>[13260.481113] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[13260.481122] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:37:pipe A] 00000000d9d9b155 state to 0000000001fbffed
>[13260.481135] [drm:skl_compute_wm [i915]] [PLANE:38:plane 1B] ddb (0 - 0) -> (0 - 860)
>[13260.481147] [drm:skl_compute_wm [i915]] [PLANE:44:cursor B] ddb (0 - 0) -> (860 - 892)
>[13260.481155] [drm:drm_atomic_commit [drm]] committing 0000000001fbffed
>[13261.480127] [drm:intel_power_well_enable [i915]] enabling power well 2
>[13261.480210] [drm:intel_atomic_commit_tail [i915]] [ENCODER:48:DDI A]
>[13261.480274] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI B]
>[13261.480332] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[13261.480386] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[13261.480438] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DDI C]
>[13261.480489] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST A]
>[13261.480540] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST B]
>[13261.480590] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI D]
>[13261.480639] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[13261.480688] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[13261.480792] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[13261.480858] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[13261.480920] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[13261.480977] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[13261.481045] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 2, on? 0) for crtc 47
>[13261.481105] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[13261.481248] [drm:intel_power_well_enable [i915]] enabling DDI B IO power well
>[13261.481842] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13261.483081] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13261.484323] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13261.485513] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13261.486752] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13261.487614] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[13261.488587] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[13261.488643] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[13261.488708] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[13261.488787] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[13261.507447] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[13261.507476] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[13261.525300] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[13261.525623] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:56:DP-1] Link Training Passed at Link Rate = 270000, Lane count = 4
>[13261.526013] [drm:intel_enable_pipe [i915]] enabling pipe B
>[13261.526043] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS
>[13261.526055] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:56:DP-1], [ENCODER:55:DDI B]
>[13261.526066] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[13261.526079] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[13261.542891] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:56:DP-1]
>[13261.542908] [drm:intel_atomic_commit_tail [i915]] [CRTC:47:pipe B]
>[13261.542931] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[13261.542943] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000001fbffed
>[13261.542950] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000001fbffed
>[13261.542971] [drm:i915_hotplug_work_func [i915]] running encoder hotplug functions
>[13261.542985] [drm:i915_hotplug_work_func [i915]] Connector DP-1 (pin 5) received hotplug event.
>[13261.542999] [drm:intel_dp_detect [i915]] [CONNECTOR:56:DP-1]
>[13261.543118] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[13261.543346] [drm:lspcon_wake_native_aux_ch [i915]] Native AUX CH up, DPCD version: 1.2
>[13261.543425] [drm:lspcon_resume [i915]] LSPCON recovering in PCON mode after 0 ms
>[13261.543839] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13261.545136] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13261.546433] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13261.547715] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13261.549006] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13261.549883] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[13261.550292] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 00 00 04 00 0f 00 04
>[13261.550579] [drm:i915_hotplug_work_func [i915]] [CONNECTOR:56:DP-1] status updated from connected to disconnected
>[13261.550626] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000e880ab74
>[13261.550634] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:47:pipe B] 00000000fae58dee state to 00000000e880ab74
>[13261.550640] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:38:plane 1B] 00000000731b73cd state to 00000000e880ab74
>[13261.550645] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for CRTC state 00000000fae58dee
>[13261.550650] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 00000000731b73cd to [NOCRTC]
>[13261.550654] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for plane state 00000000731b73cd
>[13261.550658] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:47:pipe B] to 00000000e880ab74
>[13261.550664] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:56:DP-1] 00000000eda334e9 state to 00000000e880ab74
>[13261.550668] [drm:drm_atomic_set_crtc_for_connector [drm]] Link connector state 00000000eda334e9 to [NOCRTC]
>[13261.550673] [drm:drm_atomic_check_only [drm]] checking 00000000e880ab74
>[13261.550677] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:47:pipe B] mode changed
>[13261.550680] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:47:pipe B] enable changed
>[13261.550682] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:47:pipe B] active changed
>[13261.550684] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:56:DP-1]
>[13261.550687] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Disabling [CONNECTOR:56:DP-1]
>[13261.550689] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:47:pipe B] needs all connectors, enable: n, active: n
>[13261.550695] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:47:pipe B] to 00000000e880ab74
>[13261.550716] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[13261.550732] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[13261.550750] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:47:pipe B] has [PLANE:38:plane 1B] with fb -1
>[13261.550764] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:38:plane 1B] visible 1 -> 0, off 1, on 0, ms 1
>[13261.550773] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:37:pipe A] 00000000e1fcf8a7 state to 00000000e880ab74
>[13261.550787] [drm:skl_compute_wm [i915]] [PLANE:38:plane 1B] ddb (0 - 860) -> (0 - 0)
>[13261.550799] [drm:skl_compute_wm [i915]] [PLANE:44:cursor B] ddb (860 - 892) -> (0 - 0)
>[13261.550805] [drm:drm_atomic_commit [drm]] committing 00000000e880ab74
>[13261.550832] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[13261.550848] [drm:i915_audio_component_get_eld [i915]] Not valid for port B
>[13261.550871] [drm:intel_disable_pipe [i915]] disabling pipe B
>[13261.561901] [drm:intel_power_well_disable [i915]] disabling DDI B IO power well
>[13261.561919] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 2, on? 1) for crtc 47
>[13261.561934] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[13261.561957] [drm:intel_atomic_commit_tail [i915]] [ENCODER:48:DDI A]
>[13261.561970] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI B]
>[13261.561983] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[13261.561995] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[13261.562007] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DDI C]
>[13261.562019] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST A]
>[13261.562030] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST B]
>[13261.562041] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI D]
>[13261.562052] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[13261.562063] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[13261.562076] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:56:DP-1]
>[13261.562090] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[13261.562102] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[13261.562115] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[13261.562127] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[13261.562140] [drm:intel_power_well_disable [i915]] disabling power well 2
>[13261.562155] [drm:intel_atomic_commit_tail [i915]] [CRTC:47:pipe B]
>[13261.562165] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000e880ab74
>[13261.562171] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000e880ab74
>[13261.562254] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[13261.562261] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:56:DP-1]
>[13261.562267] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000fe24d7eb
>[13261.562273] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:47:pipe B] 00000000bd3c0152 state to 00000000fe24d7eb
>[13261.562278] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:38:plane 1B] 00000000c4c517e9 state to 00000000fe24d7eb
>[13261.562283] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [MODE:1920x1080] for CRTC state 00000000bd3c0152
>[13261.562288] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 00000000c4c517e9 to [CRTC:47:pipe B]
>[13261.562292] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:99] for plane state 00000000c4c517e9
>[13261.562296] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:47:pipe B] to 00000000fe24d7eb
>[13261.562302] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:56:DP-1] 000000005a636f37 state to 00000000fe24d7eb
>[13261.562306] [drm:drm_atomic_set_crtc_for_connector [drm]] Link connector state 000000005a636f37 to [CRTC:47:pipe B]
>[13261.562310] [drm:drm_atomic_check_only [drm]] checking 00000000fe24d7eb
>[13261.562314] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:47:pipe B] mode changed
>[13261.562317] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:47:pipe B] enable changed
>[13261.562319] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:47:pipe B] active changed
>[13261.562322] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:56:DP-1]
>[13261.562324] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:56:DP-1] using [ENCODER:55:DDI B] on [CRTC:47:pipe B]
>[13261.562326] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:47:pipe B] needs all connectors, enable: y, active: y
>[13261.562331] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:47:pipe B] to 00000000fe24d7eb
>[13261.562336] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:47:pipe B] to 00000000fe24d7eb
>[13261.562352] [drm:intel_atomic_check [i915]] [CONNECTOR:56:DP-1] checking for sink bpp constrains
>[13261.562368] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 148500KHz
>[13261.562387] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 4 clock 270000 bpp 36
>[13261.562400] [drm:intel_dp_compute_config [i915]] DP link bw required 668250 available 1080000
>[13261.562415] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 36, dithering: 0
>[13261.562429] [drm:intel_dump_pipe_config [i915]] [CRTC:47:pipe B][modeset]
>[13261.562446] [drm:intel_dump_pipe_config [i915]] output_types: DP (0x80)
>[13261.562459] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 36, dithering: 0
>[13261.562472] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5190451, gmch_n: 8388608, link_m: 288358, link_n: 524288, tu: 64
>[13261.562483] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[13261.562494] [drm:intel_dump_pipe_config [i915]] requested mode:
>[13261.562501] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x9
>[13261.562513] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[13261.562519] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x9
>[13261.562532] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x9
>[13261.562543] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500
>[13261.562555] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[13261.562566] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[13261.562577] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[13261.562588] [drm:intel_dump_pipe_config [i915]] dpll_hw_state: ctrl1: 0x3, cfgcr1: 0x0, cfgcr2: 0x0
>[13261.562599] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[13261.562610] [drm:intel_dump_pipe_config [i915]] [PLANE:38:plane 1B] disabled, scaler_id = -1
>[13261.562621] [drm:intel_dump_pipe_config [i915]] [PLANE:41:plane 2B] disabled, scaler_id = -1
>[13261.562632] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor B] disabled, scaler_id = -1
>[13261.562645] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[13261.562658] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[13261.562672] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:47:pipe B] has [PLANE:38:plane 1B] with fb 99
>[13261.562685] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:38:plane 1B] visible 0 -> 1, off 0, on 1, ms 1
>[13261.562698] [drm:intel_find_shared_dpll [i915]] [CRTC:47:pipe B] allocated DPLL 1
>[13261.562711] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[13261.562724] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:37:pipe A] 000000002b48c403 state to 00000000fe24d7eb
>[13261.562736] [drm:skl_compute_wm [i915]] [PLANE:38:plane 1B] ddb (0 - 0) -> (0 - 860)
>[13261.562746] [drm:skl_compute_wm [i915]] [PLANE:44:cursor B] ddb (0 - 0) -> (860 - 892)
>[13261.562753] [drm:drm_atomic_commit [drm]] committing 00000000fe24d7eb
>[13261.865531] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[13261.865602] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[13261.865700] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[13261.865758] [drm:intel_power_well_enable [i915]] enabling power well 2
>[13262.562541] [drm:intel_atomic_commit_tail [i915]] [ENCODER:48:DDI A]
>[13262.562607] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI B]
>[13262.562665] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[13262.562719] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[13262.562771] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DDI C]
>[13262.562824] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST A]
>[13262.562874] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST B]
>[13262.562924] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI D]
>[13262.562974] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[13262.563023] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[13262.563080] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[13262.563138] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[13262.563193] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[13262.563246] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[13262.563309] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 2, on? 0) for crtc 47
>[13262.563367] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[13262.563510] [drm:intel_power_well_enable [i915]] enabling DDI B IO power well
>[13262.564101] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13262.565376] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13262.566614] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13262.567843] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13262.569085] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13262.569941] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[13262.570916] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[13262.570971] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[13262.571022] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[13262.571072] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[13262.589763] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[13262.589776] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[13262.608442] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[13262.608784] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:56:DP-1] Link Training Passed at Link Rate = 270000, Lane count = 4
>[13262.609175] [drm:intel_enable_pipe [i915]] enabling pipe B
>[13262.609215] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS
>[13262.626010] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:56:DP-1]
>[13262.626026] [drm:intel_atomic_commit_tail [i915]] [CRTC:47:pipe B]
>[13262.626047] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[13262.626055] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000fe24d7eb
>[13262.626061] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000fe24d7eb
>[13262.626076] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[13262.626081] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000fe24d7eb
>[13262.626087] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:47:pipe B] 00000000604357f6 state to 00000000fe24d7eb
>[13262.626091] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:38:plane 1B] 000000007f4576a8 state to 00000000fe24d7eb
>[13262.626095] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for CRTC state 00000000604357f6
>[13262.626099] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 000000007f4576a8 to [NOCRTC]
>[13262.626103] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for plane state 000000007f4576a8
>[13262.626107] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:47:pipe B] to 00000000fe24d7eb
>[13262.626111] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:56:DP-1] 00000000de6d4337 state to 00000000fe24d7eb
>[13262.626115] [drm:drm_atomic_set_crtc_for_connector [drm]] Link connector state 00000000de6d4337 to [NOCRTC]
>[13262.626118] [drm:drm_atomic_check_only [drm]] checking 00000000fe24d7eb
>[13262.626121] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:47:pipe B] mode changed
>[13262.626124] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:47:pipe B] enable changed
>[13262.626125] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:47:pipe B] active changed
>[13262.626127] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:56:DP-1]
>[13262.626129] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Disabling [CONNECTOR:56:DP-1]
>[13262.626132] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:47:pipe B] needs all connectors, enable: n, active: n
>[13262.626136] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:47:pipe B] to 00000000fe24d7eb
>[13262.626151] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[13262.626165] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[13262.626179] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:47:pipe B] has [PLANE:38:plane 1B] with fb -1
>[13262.626191] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:38:plane 1B] visible 1 -> 0, off 1, on 0, ms 1
>[13262.626197] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:37:pipe A] 00000000c85dec7a state to 00000000fe24d7eb
>[13262.626209] [drm:skl_compute_wm [i915]] [PLANE:38:plane 1B] ddb (0 - 860) -> (0 - 0)
>[13262.626218] [drm:skl_compute_wm [i915]] [PLANE:44:cursor B] ddb (860 - 892) -> (0 - 0)
>[13262.626223] [drm:drm_atomic_commit [drm]] committing 00000000fe24d7eb
>[13262.626245] [drm:intel_disable_pipe [i915]] disabling pipe B
>[13262.644895] [drm:intel_power_well_disable [i915]] disabling DDI B IO power well
>[13262.644913] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 2, on? 1) for crtc 47
>[13262.644928] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[13262.644950] [drm:intel_atomic_commit_tail [i915]] [ENCODER:48:DDI A]
>[13262.644964] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI B]
>[13262.644977] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[13262.644989] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[13262.645000] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DDI C]
>[13262.645012] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST A]
>[13262.645023] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST B]
>[13262.645035] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI D]
>[13262.645046] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[13262.645057] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[13262.645070] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:56:DP-1]
>[13262.645082] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[13262.645095] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[13262.645107] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[13262.645119] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[13262.645133] [drm:intel_atomic_commit_tail [i915]] [CRTC:47:pipe B]
>[13262.645143] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000fe24d7eb
>[13262.645149] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000fe24d7eb
>[13262.645214] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[13262.645582] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 00 00 04 00 0f 00 04
>[13262.646257] [drm:intel_power_well_disable [i915]] disabling power well 2
>[13262.646264] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:56:DP-1]
>[13262.646272] [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000099b1e95b
>[13262.646280] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:47:pipe B] 0000000018046d93 state to 0000000099b1e95b
>[13262.646286] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:38:plane 1B] 00000000b4b233b5 state to 0000000099b1e95b
>[13262.646292] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [MODE:1920x1080] for CRTC state 0000000018046d93
>[13262.646297] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 00000000b4b233b5 to [CRTC:47:pipe B]
>[13262.646301] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:98] for plane state 00000000b4b233b5
>[13262.646306] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:47:pipe B] to 0000000099b1e95b
>[13262.646311] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:56:DP-1] 000000006b45dc93 state to 0000000099b1e95b
>[13262.646315] [drm:drm_atomic_set_crtc_for_connector [drm]] Link connector state 000000006b45dc93 to [CRTC:47:pipe B]
>[13262.646320] [drm:drm_atomic_check_only [drm]] checking 0000000099b1e95b
>[13262.646325] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:47:pipe B] mode changed
>[13262.646327] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:47:pipe B] enable changed
>[13262.646330] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:47:pipe B] active changed
>[13262.646332] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:56:DP-1]
>[13262.646335] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:56:DP-1] using [ENCODER:55:DDI B] on [CRTC:47:pipe B]
>[13262.646338] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:47:pipe B] needs all connectors, enable: y, active: y
>[13262.646342] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:47:pipe B] to 0000000099b1e95b
>[13262.646347] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:47:pipe B] to 0000000099b1e95b
>[13262.646367] [drm:intel_atomic_check [i915]] [CONNECTOR:56:DP-1] checking for sink bpp constrains
>[13262.646385] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 148500KHz
>[13262.646405] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 4 clock 270000 bpp 36
>[13262.646419] [drm:intel_dp_compute_config [i915]] DP link bw required 668250 available 1080000
>[13262.646435] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 36, dithering: 0
>[13262.646451] [drm:intel_dump_pipe_config [i915]] [CRTC:47:pipe B][modeset]
>[13262.646466] [drm:intel_dump_pipe_config [i915]] output_types: DP (0x80)
>[13262.646479] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 36, dithering: 0
>[13262.646493] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5190451, gmch_n: 8388608, link_m: 288358, link_n: 524288, tu: 64
>[13262.646506] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[13262.646518] [drm:intel_dump_pipe_config [i915]] requested mode:
>[13262.646526] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x9
>[13262.646539] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[13262.646545] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x9
>[13262.646559] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x9
>[13262.646572] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500
>[13262.646584] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[13262.646597] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[13262.646609] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[13262.646621] [drm:intel_dump_pipe_config [i915]] dpll_hw_state: ctrl1: 0x3, cfgcr1: 0x0, cfgcr2: 0x0
>[13262.646633] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[13262.646645] [drm:intel_dump_pipe_config [i915]] [PLANE:38:plane 1B] disabled, scaler_id = -1
>[13262.646657] [drm:intel_dump_pipe_config [i915]] [PLANE:41:plane 2B] disabled, scaler_id = -1
>[13262.646669] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor B] disabled, scaler_id = -1
>[13262.646685] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[13262.646698] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[13262.646714] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:47:pipe B] has [PLANE:38:plane 1B] with fb 98
>[13262.646727] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:38:plane 1B] visible 0 -> 1, off 0, on 1, ms 1
>[13262.646742] [drm:intel_find_shared_dpll [i915]] [CRTC:47:pipe B] allocated DPLL 1
>[13262.646757] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[13262.646765] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:37:pipe A] 0000000024d204e2 state to 0000000099b1e95b
>[13262.646778] [drm:skl_compute_wm [i915]] [PLANE:38:plane 1B] ddb (0 - 0) -> (0 - 860)
>[13262.646789] [drm:skl_compute_wm [i915]] [PLANE:44:cursor B] ddb (0 - 0) -> (860 - 892)
>[13262.646796] [drm:drm_atomic_commit [drm]] committing 0000000099b1e95b
>[13263.645467] [drm:intel_power_well_enable [i915]] enabling power well 2
>[13263.645551] [drm:intel_atomic_commit_tail [i915]] [ENCODER:48:DDI A]
>[13263.645614] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI B]
>[13263.645671] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[13263.645724] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[13263.645776] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DDI C]
>[13263.645827] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST A]
>[13263.645877] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST B]
>[13263.645926] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI D]
>[13263.645974] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[13263.646023] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[13263.646078] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[13263.646134] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[13263.646188] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[13263.646239] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[13263.646302] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 2, on? 0) for crtc 47
>[13263.646358] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[13263.646499] [drm:intel_power_well_enable [i915]] enabling DDI B IO power well
>[13263.647090] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13263.648327] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13263.649575] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13263.650804] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13263.652038] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13263.652925] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[13263.653903] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[13263.653960] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[13263.654012] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[13263.654062] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[13263.672707] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[13263.672720] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[13263.691427] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[13263.691750] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:56:DP-1] Link Training Passed at Link Rate = 270000, Lane count = 4
>[13263.692140] [drm:intel_enable_pipe [i915]] enabling pipe B
>[13263.692170] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS
>[13263.708905] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:56:DP-1]
>[13263.708922] [drm:intel_atomic_commit_tail [i915]] [CRTC:47:pipe B]
>[13263.708945] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[13263.708957] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000099b1e95b
>[13263.708964] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000099b1e95b
>[13263.708985] [drm:i915_hotplug_work_func [i915]] running encoder hotplug functions
>[13263.708999] [drm:i915_hotplug_work_func [i915]] Connector DP-1 (pin 5) received hotplug event.
>[13263.709012] [drm:intel_dp_detect [i915]] [CONNECTOR:56:DP-1]
>[13263.709134] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[13263.709358] [drm:lspcon_wake_native_aux_ch [i915]] Native AUX CH up, DPCD version: 1.2
>[13263.709438] [drm:lspcon_resume [i915]] LSPCON recovering in PCON mode after 0 ms
>[13263.709852] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13263.711142] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13263.712431] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13263.713575] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13263.714864] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13263.715755] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[13263.716164] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 00 00 04 00 0f 00 04
>[13263.716838] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>[13263.716863] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000
>[13263.716873] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000
>[13263.717235] [drm:drm_dp_read_desc [drm_kms_helper]] DP branch: OUI 00-60-ad dev-ID MC2800 HW-rev 2.2 SW-rev 1.72 quirks 0x0000
>[13263.717532] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[13263.718255] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13263.719539] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13263.720830] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13263.722111] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13263.723401] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13263.724683] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13263.725974] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13263.727264] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13263.728547] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13263.729960] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13263.731373] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13263.732788] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13263.734201] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13263.735615] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13263.737016] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13263.738415] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13263.739805] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13263.741065] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13263.742271] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13263.743548] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13263.744817] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13263.746222] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13263.747620] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13263.749020] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13263.750418] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13263.751818] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13263.753217] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13263.754613] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13263.756005] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13263.756872] [drm:drm_detect_monitor_audio [drm]] Monitor has basic audio support
>[13263.757160] [drm:i915_hotplug_work_func [i915]] [CONNECTOR:56:DP-1] status updated from disconnected to connected
>[13263.757207] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000289ae621
>[13263.757214] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:47:pipe B] 000000007b1f6733 state to 00000000289ae621
>[13263.757220] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:38:plane 1B] 000000002632017f state to 00000000289ae621
>[13263.757225] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for CRTC state 000000007b1f6733
>[13263.757229] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 000000002632017f to [NOCRTC]
>[13263.757233] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for plane state 000000002632017f
>[13263.757237] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:47:pipe B] to 00000000289ae621
>[13263.757242] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:56:DP-1] 000000006152bc9a state to 00000000289ae621
>[13263.757246] [drm:drm_atomic_set_crtc_for_connector [drm]] Link connector state 000000006152bc9a to [NOCRTC]
>[13263.757250] [drm:drm_atomic_check_only [drm]] checking 00000000289ae621
>[13263.757255] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:47:pipe B] mode changed
>[13263.757257] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:47:pipe B] enable changed
>[13263.757259] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:47:pipe B] active changed
>[13263.757261] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:56:DP-1]
>[13263.757264] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Disabling [CONNECTOR:56:DP-1]
>[13263.757266] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:47:pipe B] needs all connectors, enable: n, active: n
>[13263.757270] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:47:pipe B] to 00000000289ae621
>[13263.757291] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[13263.757307] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[13263.757322] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:47:pipe B] has [PLANE:38:plane 1B] with fb -1
>[13263.757336] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:38:plane 1B] visible 1 -> 0, off 1, on 0, ms 1
>[13263.757343] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:37:pipe A] 00000000fd63c90d state to 00000000289ae621
>[13263.757356] [drm:skl_compute_wm [i915]] [PLANE:38:plane 1B] ddb (0 - 860) -> (0 - 0)
>[13263.757366] [drm:skl_compute_wm [i915]] [PLANE:44:cursor B] ddb (860 - 892) -> (0 - 0)
>[13263.757372] [drm:drm_atomic_commit [drm]] committing 00000000289ae621
>[13263.757397] [drm:intel_disable_pipe [i915]] disabling pipe B
>[13263.758990] [drm:intel_power_well_disable [i915]] disabling DDI B IO power well
>[13263.759007] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 2, on? 1) for crtc 47
>[13263.759021] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[13263.759042] [drm:intel_atomic_commit_tail [i915]] [ENCODER:48:DDI A]
>[13263.759055] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI B]
>[13263.759067] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[13263.759078] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[13263.759089] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DDI C]
>[13263.759100] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST A]
>[13263.759111] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST B]
>[13263.759121] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI D]
>[13263.759131] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[13263.759141] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[13263.759153] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:56:DP-1]
>[13263.759165] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[13263.759177] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[13263.759189] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[13263.759200] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[13263.759211] [drm:intel_power_well_disable [i915]] disabling power well 2
>[13263.759226] [drm:intel_atomic_commit_tail [i915]] [CRTC:47:pipe B]
>[13263.759234] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000289ae621
>[13263.759240] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000289ae621
>[13263.759314] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[13263.759320] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:56:DP-1]
>[13263.759325] [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000059ed298d
>[13263.759331] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:47:pipe B] 00000000604357f6 state to 0000000059ed298d
>[13263.759336] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:38:plane 1B] 000000005906dec2 state to 0000000059ed298d
>[13263.759340] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [MODE:1920x1080] for CRTC state 00000000604357f6
>[13263.759345] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 000000005906dec2 to [CRTC:47:pipe B]
>[13263.759349] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:99] for plane state 000000005906dec2
>[13263.759353] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:47:pipe B] to 0000000059ed298d
>[13263.759357] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:56:DP-1] 00000000de6d4337 state to 0000000059ed298d
>[13263.759361] [drm:drm_atomic_set_crtc_for_connector [drm]] Link connector state 00000000de6d4337 to [CRTC:47:pipe B]
>[13263.759365] [drm:drm_atomic_check_only [drm]] checking 0000000059ed298d
>[13263.759369] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:47:pipe B] mode changed
>[13263.759371] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:47:pipe B] enable changed
>[13263.759373] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:47:pipe B] active changed
>[13263.759375] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:56:DP-1]
>[13263.759378] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:56:DP-1] using [ENCODER:55:DDI B] on [CRTC:47:pipe B]
>[13263.759380] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:47:pipe B] needs all connectors, enable: y, active: y
>[13263.759384] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:47:pipe B] to 0000000059ed298d
>[13263.759388] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:47:pipe B] to 0000000059ed298d
>[13263.759403] [drm:intel_atomic_check [i915]] [CONNECTOR:56:DP-1] checking for sink bpp constrains
>[13263.759418] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 148500KHz
>[13263.759435] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 4 clock 270000 bpp 36
>[13263.759447] [drm:intel_dp_compute_config [i915]] DP link bw required 668250 available 1080000
>[13263.759461] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 36, dithering: 0
>[13263.759474] [drm:intel_dump_pipe_config [i915]] [CRTC:47:pipe B][modeset]
>[13263.759486] [drm:intel_dump_pipe_config [i915]] output_types: DP (0x80)
>[13263.759498] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 36, dithering: 0
>[13263.759509] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5190451, gmch_n: 8388608, link_m: 288358, link_n: 524288, tu: 64
>[13263.759525] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[13263.759535] [drm:intel_dump_pipe_config [i915]] requested mode:
>[13263.759541] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x9
>[13263.759552] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[13263.759558] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x9
>[13263.759569] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x9
>[13263.759580] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500
>[13263.759590] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[13263.759600] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[13263.759611] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[13263.759621] [drm:intel_dump_pipe_config [i915]] dpll_hw_state: ctrl1: 0x3, cfgcr1: 0x0, cfgcr2: 0x0
>[13263.759631] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[13263.759641] [drm:intel_dump_pipe_config [i915]] [PLANE:38:plane 1B] disabled, scaler_id = -1
>[13263.759652] [drm:intel_dump_pipe_config [i915]] [PLANE:41:plane 2B] disabled, scaler_id = -1
>[13263.759662] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor B] disabled, scaler_id = -1
>[13263.759675] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[13263.759686] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[13263.759700] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:47:pipe B] has [PLANE:38:plane 1B] with fb 99
>[13263.759712] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:38:plane 1B] visible 0 -> 1, off 0, on 1, ms 1
>[13263.759725] [drm:intel_find_shared_dpll [i915]] [CRTC:47:pipe B] allocated DPLL 1
>[13263.759737] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[13263.759749] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:37:pipe A] 00000000c85dec7a state to 0000000059ed298d
>[13263.759760] [drm:skl_compute_wm [i915]] [PLANE:38:plane 1B] ddb (0 - 0) -> (0 - 860)
>[13263.759770] [drm:skl_compute_wm [i915]] [PLANE:44:cursor B] ddb (0 - 0) -> (860 - 892)
>[13263.759775] [drm:drm_atomic_commit [drm]] committing 0000000059ed298d
>[13264.759533] [drm:intel_power_well_enable [i915]] enabling power well 2
>[13264.759618] [drm:intel_atomic_commit_tail [i915]] [ENCODER:48:DDI A]
>[13264.759682] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI B]
>[13264.759740] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[13264.759795] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[13264.759847] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DDI C]
>[13264.759898] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST A]
>[13264.759948] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST B]
>[13264.759996] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI D]
>[13264.760045] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[13264.760093] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[13264.760148] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[13264.760204] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[13264.760257] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[13264.760309] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[13264.760371] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 2, on? 0) for crtc 47
>[13264.760427] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[13264.760568] [drm:intel_power_well_enable [i915]] enabling DDI B IO power well
>[13264.761222] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13264.762461] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13264.763698] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13264.764930] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13264.766168] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13264.767024] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[13264.767999] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[13264.768054] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[13264.768106] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[13264.768156] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[13264.786796] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[13264.786810] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[13264.804628] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[13264.804850] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:56:DP-1] Link Training Passed at Link Rate = 270000, Lane count = 4
>[13264.805247] [drm:intel_enable_pipe [i915]] enabling pipe B
>[13264.805283] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS
>[13264.805296] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:56:DP-1], [ENCODER:55:DDI B]
>[13264.805307] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[13264.805320] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[13264.822068] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:56:DP-1]
>[13264.822084] [drm:intel_atomic_commit_tail [i915]] [CRTC:47:pipe B]
>[13264.822105] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[13264.822114] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000059ed298d
>[13264.822120] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000059ed298d
>[13264.822135] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[13264.822140] [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000059ed298d
>[13264.822146] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:47:pipe B] 00000000bd3c0152 state to 0000000059ed298d
>[13264.822150] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:38:plane 1B] 00000000c4c517e9 state to 0000000059ed298d
>[13264.822154] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for CRTC state 00000000bd3c0152
>[13264.822158] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 00000000c4c517e9 to [NOCRTC]
>[13264.822162] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for plane state 00000000c4c517e9
>[13264.822166] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:47:pipe B] to 0000000059ed298d
>[13264.822170] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:56:DP-1] 00000000f8eadac6 state to 0000000059ed298d
>[13264.822174] [drm:drm_atomic_set_crtc_for_connector [drm]] Link connector state 00000000f8eadac6 to [NOCRTC]
>[13264.822178] [drm:drm_atomic_check_only [drm]] checking 0000000059ed298d
>[13264.822181] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:47:pipe B] mode changed
>[13264.822183] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:47:pipe B] enable changed
>[13264.822185] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:47:pipe B] active changed
>[13264.822187] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:56:DP-1]
>[13264.822189] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Disabling [CONNECTOR:56:DP-1]
>[13264.822191] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:47:pipe B] needs all connectors, enable: n, active: n
>[13264.822196] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:47:pipe B] to 0000000059ed298d
>[13264.822212] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[13264.822225] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[13264.822239] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:47:pipe B] has [PLANE:38:plane 1B] with fb -1
>[13264.822252] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:38:plane 1B] visible 1 -> 0, off 1, on 0, ms 1
>[13264.822258] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:37:pipe A] 000000002b48c403 state to 0000000059ed298d
>[13264.822269] [drm:skl_compute_wm [i915]] [PLANE:38:plane 1B] ddb (0 - 860) -> (0 - 0)
>[13264.822279] [drm:skl_compute_wm [i915]] [PLANE:44:cursor B] ddb (860 - 892) -> (0 - 0)
>[13264.822284] [drm:drm_atomic_commit [drm]] committing 0000000059ed298d
>[13264.822304] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[13264.822317] [drm:i915_audio_component_get_eld [i915]] Not valid for port B
>[13264.822334] [drm:intel_disable_pipe [i915]] disabling pipe B
>[13264.840929] [drm:intel_power_well_disable [i915]] disabling DDI B IO power well
>[13264.840947] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 2, on? 1) for crtc 47
>[13264.840962] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[13264.840984] [drm:intel_atomic_commit_tail [i915]] [ENCODER:48:DDI A]
>[13264.840997] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI B]
>[13264.841011] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[13264.841023] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[13264.841035] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DDI C]
>[13264.841046] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST A]
>[13264.841057] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST B]
>[13264.841068] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI D]
>[13264.841079] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[13264.841090] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[13264.841103] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:56:DP-1]
>[13264.841116] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[13264.841129] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[13264.841141] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[13264.841152] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[13264.841165] [drm:intel_power_well_disable [i915]] disabling power well 2
>[13264.841180] [drm:intel_atomic_commit_tail [i915]] [CRTC:47:pipe B]
>[13264.841189] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000059ed298d
>[13264.841195] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000059ed298d
>[13264.841261] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[13264.841268] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:56:DP-1]
>[13264.841274] [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000059ed298d
>[13264.841280] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:47:pipe B] 00000000604357f6 state to 0000000059ed298d
>[13264.841285] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:38:plane 1B] 00000000ab8e9814 state to 0000000059ed298d
>[13264.841291] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [MODE:1920x1080] for CRTC state 00000000604357f6
>[13264.841295] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 00000000ab8e9814 to [CRTC:47:pipe B]
>[13264.841300] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:98] for plane state 00000000ab8e9814
>[13264.841304] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:47:pipe B] to 0000000059ed298d
>[13264.841309] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:56:DP-1] 000000005a636f37 state to 0000000059ed298d
>[13264.841313] [drm:drm_atomic_set_crtc_for_connector [drm]] Link connector state 000000005a636f37 to [CRTC:47:pipe B]
>[13264.841317] [drm:drm_atomic_check_only [drm]] checking 0000000059ed298d
>[13264.841321] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:47:pipe B] mode changed
>[13264.841324] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:47:pipe B] enable changed
>[13264.841326] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:47:pipe B] active changed
>[13264.841328] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:56:DP-1]
>[13264.841331] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:56:DP-1] using [ENCODER:55:DDI B] on [CRTC:47:pipe B]
>[13264.841333] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:47:pipe B] needs all connectors, enable: y, active: y
>[13264.841338] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:47:pipe B] to 0000000059ed298d
>[13264.841342] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:47:pipe B] to 0000000059ed298d
>[13264.841358] [drm:intel_atomic_check [i915]] [CONNECTOR:56:DP-1] checking for sink bpp constrains
>[13264.841374] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 148500KHz
>[13264.841392] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 4 clock 270000 bpp 36
>[13264.841405] [drm:intel_dp_compute_config [i915]] DP link bw required 668250 available 1080000
>[13264.841420] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 36, dithering: 0
>[13264.841434] [drm:intel_dump_pipe_config [i915]] [CRTC:47:pipe B][modeset]
>[13264.841447] [drm:intel_dump_pipe_config [i915]] output_types: DP (0x80)
>[13264.841460] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 36, dithering: 0
>[13264.841472] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5190451, gmch_n: 8388608, link_m: 288358, link_n: 524288, tu: 64
>[13264.841484] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[13264.841496] [drm:intel_dump_pipe_config [i915]] requested mode:
>[13264.841502] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x9
>[13264.841514] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[13264.841520] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x9
>[13264.841533] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x9
>[13264.841544] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500
>[13264.841556] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[13264.841567] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[13264.841578] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[13264.841589] [drm:intel_dump_pipe_config [i915]] dpll_hw_state: ctrl1: 0x3, cfgcr1: 0x0, cfgcr2: 0x0
>[13264.841600] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[13264.841611] [drm:intel_dump_pipe_config [i915]] [PLANE:38:plane 1B] disabled, scaler_id = -1
>[13264.841622] [drm:intel_dump_pipe_config [i915]] [PLANE:41:plane 2B] disabled, scaler_id = -1
>[13264.841633] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor B] disabled, scaler_id = -1
>[13264.841647] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[13264.841659] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[13264.841674] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:47:pipe B] has [PLANE:38:plane 1B] with fb 98
>[13264.841687] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:38:plane 1B] visible 0 -> 1, off 0, on 1, ms 1
>[13264.841701] [drm:intel_find_shared_dpll [i915]] [CRTC:47:pipe B] allocated DPLL 1
>[13264.841714] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[13264.841721] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:37:pipe A] 00000000c85dec7a state to 0000000059ed298d
>[13264.841733] [drm:skl_compute_wm [i915]] [PLANE:38:plane 1B] ddb (0 - 0) -> (0 - 860)
>[13264.841744] [drm:skl_compute_wm [i915]] [PLANE:44:cursor B] ddb (0 - 0) -> (860 - 892)
>[13264.841750] [drm:drm_atomic_commit [drm]] committing 0000000059ed298d
>[13265.841515] [drm:intel_power_well_enable [i915]] enabling power well 2
>[13265.841599] [drm:intel_atomic_commit_tail [i915]] [ENCODER:48:DDI A]
>[13265.841664] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI B]
>[13265.841721] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[13265.841775] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[13265.841826] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DDI C]
>[13265.841875] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST A]
>[13265.841925] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST B]
>[13265.841974] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI D]
>[13265.842023] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[13265.842072] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[13265.842127] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[13265.842184] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[13265.842239] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[13265.842291] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[13265.842354] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 2, on? 0) for crtc 47
>[13265.842410] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[13265.842551] [drm:intel_power_well_enable [i915]] enabling DDI B IO power well
>[13265.843143] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13265.844384] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13265.845631] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13265.846861] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13265.848096] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13265.848995] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[13265.849971] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[13265.850026] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[13265.850076] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[13265.850126] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[13265.868771] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[13265.868801] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[13265.886620] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[13265.886797] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:56:DP-1] Link Training Passed at Link Rate = 270000, Lane count = 4
>[13265.887186] [drm:intel_enable_pipe [i915]] enabling pipe B
>[13265.887211] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS
>[13265.887224] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:56:DP-1], [ENCODER:55:DDI B]
>[13265.887235] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[13265.887248] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[13265.903989] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:56:DP-1]
>[13265.904005] [drm:intel_atomic_commit_tail [i915]] [CRTC:47:pipe B]
>[13265.904026] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[13265.904035] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000059ed298d
>[13265.904040] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000059ed298d
>[13265.904053] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[13265.904059] [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000059ed298d
>[13265.904064] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:47:pipe B] 00000000bd3c0152 state to 0000000059ed298d
>[13265.904068] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:38:plane 1B] 000000005906dec2 state to 0000000059ed298d
>[13265.904073] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for CRTC state 00000000bd3c0152
>[13265.904076] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 000000005906dec2 to [NOCRTC]
>[13265.904080] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for plane state 000000005906dec2
>[13265.904084] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:47:pipe B] to 0000000059ed298d
>[13265.904088] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:56:DP-1] 00000000d1e5643f state to 0000000059ed298d
>[13265.904092] [drm:drm_atomic_set_crtc_for_connector [drm]] Link connector state 00000000d1e5643f to [NOCRTC]
>[13265.904096] [drm:drm_atomic_check_only [drm]] checking 0000000059ed298d
>[13265.904099] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:47:pipe B] mode changed
>[13265.904101] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:47:pipe B] enable changed
>[13265.904103] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:47:pipe B] active changed
>[13265.904105] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:56:DP-1]
>[13265.904107] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Disabling [CONNECTOR:56:DP-1]
>[13265.904109] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:47:pipe B] needs all connectors, enable: n, active: n
>[13265.904113] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:47:pipe B] to 0000000059ed298d
>[13265.904129] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[13265.904142] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[13265.904156] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:47:pipe B] has [PLANE:38:plane 1B] with fb -1
>[13265.904168] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:38:plane 1B] visible 1 -> 0, off 1, on 0, ms 1
>[13265.904174] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:37:pipe A] 000000002b48c403 state to 0000000059ed298d
>[13265.904185] [drm:skl_compute_wm [i915]] [PLANE:38:plane 1B] ddb (0 - 860) -> (0 - 0)
>[13265.904195] [drm:skl_compute_wm [i915]] [PLANE:44:cursor B] ddb (860 - 892) -> (0 - 0)
>[13265.904200] [drm:drm_atomic_commit [drm]] committing 0000000059ed298d
>[13265.904220] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[13265.904233] [drm:i915_audio_component_get_eld [i915]] Not valid for port B
>[13265.904250] [drm:intel_disable_pipe [i915]] disabling pipe B
>[13265.923198] [drm:intel_power_well_disable [i915]] disabling DDI B IO power well
>[13265.923216] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 2, on? 1) for crtc 47
>[13265.923231] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[13265.923253] [drm:intel_atomic_commit_tail [i915]] [ENCODER:48:DDI A]
>[13265.923267] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI B]
>[13265.923280] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[13265.923291] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[13265.923303] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DDI C]
>[13265.923314] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST A]
>[13265.923325] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST B]
>[13265.923336] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI D]
>[13265.923347] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[13265.923358] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[13265.923371] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:56:DP-1]
>[13265.923384] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[13265.923397] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[13265.923409] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[13265.923421] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[13265.923434] [drm:intel_power_well_disable [i915]] disabling power well 2
>[13265.923449] [drm:intel_atomic_commit_tail [i915]] [CRTC:47:pipe B]
>[13265.923458] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000059ed298d
>[13265.923464] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000059ed298d
>[13265.923520] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[13265.923526] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:56:DP-1]
>[13265.923532] [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000059ed298d
>[13265.923538] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:47:pipe B] 00000000604357f6 state to 0000000059ed298d
>[13265.923543] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:38:plane 1B] 00000000c4c517e9 state to 0000000059ed298d
>[13265.923549] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [MODE:1920x1080] for CRTC state 00000000604357f6
>[13265.923554] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 00000000c4c517e9 to [CRTC:47:pipe B]
>[13265.923558] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:99] for plane state 00000000c4c517e9
>[13265.923563] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:47:pipe B] to 0000000059ed298d
>[13265.923568] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:56:DP-1] 00000000f8eadac6 state to 0000000059ed298d
>[13265.923572] [drm:drm_atomic_set_crtc_for_connector [drm]] Link connector state 00000000f8eadac6 to [CRTC:47:pipe B]
>[13265.923577] [drm:drm_atomic_check_only [drm]] checking 0000000059ed298d
>[13265.923580] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:47:pipe B] mode changed
>[13265.923583] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:47:pipe B] enable changed
>[13265.923585] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:47:pipe B] active changed
>[13265.923588] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:56:DP-1]
>[13265.923590] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:56:DP-1] using [ENCODER:55:DDI B] on [CRTC:47:pipe B]
>[13265.923592] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:47:pipe B] needs all connectors, enable: y, active: y
>[13265.923597] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:47:pipe B] to 0000000059ed298d
>[13265.923602] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:47:pipe B] to 0000000059ed298d
>[13265.923618] [drm:intel_atomic_check [i915]] [CONNECTOR:56:DP-1] checking for sink bpp constrains
>[13265.923633] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 148500KHz
>[13265.923651] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 4 clock 270000 bpp 36
>[13265.923664] [drm:intel_dp_compute_config [i915]] DP link bw required 668250 available 1080000
>[13265.923678] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 36, dithering: 0
>[13265.923692] [drm:intel_dump_pipe_config [i915]] [CRTC:47:pipe B][modeset]
>[13265.923705] [drm:intel_dump_pipe_config [i915]] output_types: DP (0x80)
>[13265.923718] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 36, dithering: 0
>[13265.923730] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5190451, gmch_n: 8388608, link_m: 288358, link_n: 524288, tu: 64
>[13265.923742] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[13265.923753] [drm:intel_dump_pipe_config [i915]] requested mode:
>[13265.923760] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x9
>[13265.923772] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[13265.923778] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x9
>[13265.923791] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x9
>[13265.923802] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500
>[13265.923814] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[13265.923825] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[13265.923836] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[13265.923847] [drm:intel_dump_pipe_config [i915]] dpll_hw_state: ctrl1: 0x3, cfgcr1: 0x0, cfgcr2: 0x0
>[13265.923858] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[13265.923869] [drm:intel_dump_pipe_config [i915]] [PLANE:38:plane 1B] disabled, scaler_id = -1
>[13265.923880] [drm:intel_dump_pipe_config [i915]] [PLANE:41:plane 2B] disabled, scaler_id = -1
>[13265.923891] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor B] disabled, scaler_id = -1
>[13265.923904] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[13265.923917] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[13265.923931] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:47:pipe B] has [PLANE:38:plane 1B] with fb 99
>[13265.923944] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:38:plane 1B] visible 0 -> 1, off 0, on 1, ms 1
>[13265.923958] [drm:intel_find_shared_dpll [i915]] [CRTC:47:pipe B] allocated DPLL 1
>[13265.923971] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[13265.923980] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:37:pipe A] 00000000c85dec7a state to 0000000059ed298d
>[13265.923993] [drm:skl_compute_wm [i915]] [PLANE:38:plane 1B] ddb (0 - 0) -> (0 - 860)
>[13265.924003] [drm:skl_compute_wm [i915]] [PLANE:44:cursor B] ddb (0 - 0) -> (860 - 892)
>[13265.924009] [drm:drm_atomic_commit [drm]] committing 0000000059ed298d
>[13266.923772] [drm:intel_power_well_enable [i915]] enabling power well 2
>[13266.923856] [drm:intel_atomic_commit_tail [i915]] [ENCODER:48:DDI A]
>[13266.923919] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI B]
>[13266.923977] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[13266.924031] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[13266.924082] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DDI C]
>[13266.924131] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST A]
>[13266.924179] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST B]
>[13266.924228] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI D]
>[13266.924275] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[13266.924322] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[13266.924377] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[13266.924433] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[13266.924487] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[13266.924540] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[13266.924602] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 2, on? 0) for crtc 47
>[13266.924659] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[13266.924831] [drm:intel_power_well_enable [i915]] enabling DDI B IO power well
>[13266.925443] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13266.926681] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13266.927916] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13266.929162] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13266.930399] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13266.931256] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[13266.932231] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[13266.932286] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[13266.932337] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[13266.932386] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[13266.951074] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[13266.951087] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[13266.969803] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[13266.970126] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:56:DP-1] Link Training Passed at Link Rate = 270000, Lane count = 4
>[13266.970516] [drm:intel_enable_pipe [i915]] enabling pipe B
>[13266.970546] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS
>[13266.970558] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:56:DP-1], [ENCODER:55:DDI B]
>[13266.970569] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[13266.970582] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[13266.987336] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:56:DP-1]
>[13266.987353] [drm:intel_atomic_commit_tail [i915]] [CRTC:47:pipe B]
>[13266.987373] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[13266.987382] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000059ed298d
>[13266.987387] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000059ed298d
>[13266.987401] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[13266.987406] [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000059ed298d
>[13266.987411] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:47:pipe B] 00000000bd3c0152 state to 0000000059ed298d
>[13266.987416] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:38:plane 1B] 00000000ab8e9814 state to 0000000059ed298d
>[13266.987420] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for CRTC state 00000000bd3c0152
>[13266.987424] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 00000000ab8e9814 to [NOCRTC]
>[13266.987428] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for plane state 00000000ab8e9814
>[13266.987431] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:47:pipe B] to 0000000059ed298d
>[13266.987436] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:56:DP-1] 00000000de6d4337 state to 0000000059ed298d
>[13266.987439] [drm:drm_atomic_set_crtc_for_connector [drm]] Link connector state 00000000de6d4337 to [NOCRTC]
>[13266.987443] [drm:drm_atomic_check_only [drm]] checking 0000000059ed298d
>[13266.987446] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:47:pipe B] mode changed
>[13266.987448] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:47:pipe B] enable changed
>[13266.987450] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:47:pipe B] active changed
>[13266.987452] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:56:DP-1]
>[13266.987454] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Disabling [CONNECTOR:56:DP-1]
>[13266.987457] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:47:pipe B] needs all connectors, enable: n, active: n
>[13266.987461] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:47:pipe B] to 0000000059ed298d
>[13266.987477] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[13266.987490] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[13266.987504] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:47:pipe B] has [PLANE:38:plane 1B] with fb -1
>[13266.987517] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:38:plane 1B] visible 1 -> 0, off 1, on 0, ms 1
>[13266.987523] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:37:pipe A] 000000002b48c403 state to 0000000059ed298d
>[13266.987534] [drm:skl_compute_wm [i915]] [PLANE:38:plane 1B] ddb (0 - 860) -> (0 - 0)
>[13266.987543] [drm:skl_compute_wm [i915]] [PLANE:44:cursor B] ddb (860 - 892) -> (0 - 0)
>[13266.987549] [drm:drm_atomic_commit [drm]] committing 0000000059ed298d
>[13266.987568] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[13266.987581] [drm:i915_audio_component_get_eld [i915]] Not valid for port B
>[13266.987599] [drm:intel_disable_pipe [i915]] disabling pipe B
>[13267.006243] [drm:intel_power_well_disable [i915]] disabling DDI B IO power well
>[13267.006262] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 2, on? 1) for crtc 47
>[13267.006277] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[13267.006299] [drm:intel_atomic_commit_tail [i915]] [ENCODER:48:DDI A]
>[13267.006312] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI B]
>[13267.006325] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[13267.006337] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[13267.006349] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DDI C]
>[13267.006360] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST A]
>[13267.006372] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST B]
>[13267.006383] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI D]
>[13267.006394] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[13267.006405] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[13267.006417] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:56:DP-1]
>[13267.006431] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[13267.006443] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[13267.006456] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[13267.006468] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[13267.006480] [drm:intel_power_well_disable [i915]] disabling power well 2
>[13267.006496] [drm:intel_atomic_commit_tail [i915]] [CRTC:47:pipe B]
>[13267.006504] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000059ed298d
>[13267.006511] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000059ed298d
>[13267.006566] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[13267.006572] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:56:DP-1]
>[13267.006578] [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000059ed298d
>[13267.006584] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:47:pipe B] 00000000604357f6 state to 0000000059ed298d
>[13267.006590] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:38:plane 1B] 000000005906dec2 state to 0000000059ed298d
>[13267.006595] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [MODE:1920x1080] for CRTC state 00000000604357f6
>[13267.006600] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 000000005906dec2 to [CRTC:47:pipe B]
>[13267.006604] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:98] for plane state 000000005906dec2
>[13267.006609] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:47:pipe B] to 0000000059ed298d
>[13267.006614] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:56:DP-1] 00000000d1e5643f state to 0000000059ed298d
>[13267.006618] [drm:drm_atomic_set_crtc_for_connector [drm]] Link connector state 00000000d1e5643f to [CRTC:47:pipe B]
>[13267.006622] [drm:drm_atomic_check_only [drm]] checking 0000000059ed298d
>[13267.006626] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:47:pipe B] mode changed
>[13267.006628] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:47:pipe B] enable changed
>[13267.006631] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:47:pipe B] active changed
>[13267.006633] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:56:DP-1]
>[13267.006636] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:56:DP-1] using [ENCODER:55:DDI B] on [CRTC:47:pipe B]
>[13267.006638] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:47:pipe B] needs all connectors, enable: y, active: y
>[13267.006643] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:47:pipe B] to 0000000059ed298d
>[13267.006647] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:47:pipe B] to 0000000059ed298d
>[13267.006663] [drm:intel_atomic_check [i915]] [CONNECTOR:56:DP-1] checking for sink bpp constrains
>[13267.006679] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 148500KHz
>[13267.006697] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 4 clock 270000 bpp 36
>[13267.006710] [drm:intel_dp_compute_config [i915]] DP link bw required 668250 available 1080000
>[13267.006725] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 36, dithering: 0
>[13267.006739] [drm:intel_dump_pipe_config [i915]] [CRTC:47:pipe B][modeset]
>[13267.006752] [drm:intel_dump_pipe_config [i915]] output_types: DP (0x80)
>[13267.006764] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 36, dithering: 0
>[13267.006777] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5190451, gmch_n: 8388608, link_m: 288358, link_n: 524288, tu: 64
>[13267.006789] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[13267.006800] [drm:intel_dump_pipe_config [i915]] requested mode:
>[13267.006807] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x9
>[13267.006818] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[13267.006825] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x9
>[13267.006837] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x9
>[13267.006849] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500
>[13267.006860] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[13267.006872] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[13267.006883] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[13267.006894] [drm:intel_dump_pipe_config [i915]] dpll_hw_state: ctrl1: 0x3, cfgcr1: 0x0, cfgcr2: 0x0
>[13267.006905] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[13267.006916] [drm:intel_dump_pipe_config [i915]] [PLANE:38:plane 1B] disabled, scaler_id = -1
>[13267.006927] [drm:intel_dump_pipe_config [i915]] [PLANE:41:plane 2B] disabled, scaler_id = -1
>[13267.006938] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor B] disabled, scaler_id = -1
>[13267.006952] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[13267.006964] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[13267.006978] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:47:pipe B] has [PLANE:38:plane 1B] with fb 98
>[13267.006991] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:38:plane 1B] visible 0 -> 1, off 0, on 1, ms 1
>[13267.007005] [drm:intel_find_shared_dpll [i915]] [CRTC:47:pipe B] allocated DPLL 1
>[13267.007017] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[13267.007025] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:37:pipe A] 00000000c85dec7a state to 0000000059ed298d
>[13267.007037] [drm:skl_compute_wm [i915]] [PLANE:38:plane 1B] ddb (0 - 0) -> (0 - 860)
>[13267.007047] [drm:skl_compute_wm [i915]] [PLANE:44:cursor B] ddb (0 - 0) -> (860 - 892)
>[13267.007054] [drm:drm_atomic_commit [drm]] committing 0000000059ed298d
>[13268.006826] [drm:intel_power_well_enable [i915]] enabling power well 2
>[13268.006910] [drm:intel_atomic_commit_tail [i915]] [ENCODER:48:DDI A]
>[13268.006974] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI B]
>[13268.007031] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[13268.007084] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[13268.007135] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DDI C]
>[13268.007185] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST A]
>[13268.007234] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST B]
>[13268.007283] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI D]
>[13268.007331] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[13268.007379] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[13268.007435] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[13268.007491] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[13268.007544] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[13268.007597] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[13268.007660] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 2, on? 0) for crtc 47
>[13268.007715] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[13268.007856] [drm:intel_power_well_enable [i915]] enabling DDI B IO power well
>[13268.008448] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13268.009635] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13268.010818] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13268.012047] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13268.013306] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13268.014163] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[13268.015137] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[13268.015192] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[13268.015244] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[13268.015295] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[13268.033943] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[13268.033973] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[13268.052706] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[13268.053029] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:56:DP-1] Link Training Passed at Link Rate = 270000, Lane count = 4
>[13268.053419] [drm:intel_enable_pipe [i915]] enabling pipe B
>[13268.053448] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS
>[13268.053461] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:56:DP-1], [ENCODER:55:DDI B]
>[13268.053472] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[13268.053485] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[13268.070225] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:56:DP-1]
>[13268.070241] [drm:intel_atomic_commit_tail [i915]] [CRTC:47:pipe B]
>[13268.070261] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[13268.070270] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000059ed298d
>[13268.070276] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000059ed298d
>[13268.070288] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[13268.070294] [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000059ed298d
>[13268.070299] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:47:pipe B] 00000000bd3c0152 state to 0000000059ed298d
>[13268.070303] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:38:plane 1B] 00000000c4c517e9 state to 0000000059ed298d
>[13268.070308] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for CRTC state 00000000bd3c0152
>[13268.070312] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 00000000c4c517e9 to [NOCRTC]
>[13268.070315] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for plane state 00000000c4c517e9
>[13268.070319] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:47:pipe B] to 0000000059ed298d
>[13268.070323] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:56:DP-1] 000000005a636f37 state to 0000000059ed298d
>[13268.070327] [drm:drm_atomic_set_crtc_for_connector [drm]] Link connector state 000000005a636f37 to [NOCRTC]
>[13268.070331] [drm:drm_atomic_check_only [drm]] checking 0000000059ed298d
>[13268.070334] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:47:pipe B] mode changed
>[13268.070336] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:47:pipe B] enable changed
>[13268.070338] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:47:pipe B] active changed
>[13268.070340] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:56:DP-1]
>[13268.070342] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Disabling [CONNECTOR:56:DP-1]
>[13268.070345] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:47:pipe B] needs all connectors, enable: n, active: n
>[13268.070349] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:47:pipe B] to 0000000059ed298d
>[13268.070364] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[13268.070378] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[13268.070392] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:47:pipe B] has [PLANE:38:plane 1B] with fb -1
>[13268.070404] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:38:plane 1B] visible 1 -> 0, off 1, on 0, ms 1
>[13268.070410] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:37:pipe A] 000000002b48c403 state to 0000000059ed298d
>[13268.070421] [drm:skl_compute_wm [i915]] [PLANE:38:plane 1B] ddb (0 - 860) -> (0 - 0)
>[13268.070431] [drm:skl_compute_wm [i915]] [PLANE:44:cursor B] ddb (860 - 892) -> (0 - 0)
>[13268.070436] [drm:drm_atomic_commit [drm]] committing 0000000059ed298d
>[13268.070456] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[13268.070469] [drm:i915_audio_component_get_eld [i915]] Not valid for port B
>[13268.070486] [drm:intel_disable_pipe [i915]] disabling pipe B
>[13268.088884] [drm:intel_power_well_disable [i915]] disabling DDI B IO power well
>[13268.088902] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 2, on? 1) for crtc 47
>[13268.088917] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[13268.088940] [drm:intel_atomic_commit_tail [i915]] [ENCODER:48:DDI A]
>[13268.088953] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI B]
>[13268.088966] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[13268.088978] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[13268.088990] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DDI C]
>[13268.089002] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST A]
>[13268.089013] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST B]
>[13268.089024] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI D]
>[13268.089035] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[13268.089046] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[13268.089058] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:56:DP-1]
>[13268.089071] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[13268.089084] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[13268.089097] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[13268.089109] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[13268.089121] [drm:intel_power_well_disable [i915]] disabling power well 2
>[13268.089136] [drm:intel_atomic_commit_tail [i915]] [CRTC:47:pipe B]
>[13268.089145] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000059ed298d
>[13268.089151] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000059ed298d
>[13268.089206] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[13268.089213] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:56:DP-1]
>[13268.089219] [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000059ed298d
>[13268.089225] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:47:pipe B] 00000000604357f6 state to 0000000059ed298d
>[13268.089230] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:38:plane 1B] 00000000ab8e9814 state to 0000000059ed298d
>[13268.089235] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [MODE:1920x1080] for CRTC state 00000000604357f6
>[13268.089240] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 00000000ab8e9814 to [CRTC:47:pipe B]
>[13268.089244] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:99] for plane state 00000000ab8e9814
>[13268.089249] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:47:pipe B] to 0000000059ed298d
>[13268.089254] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:56:DP-1] 00000000de6d4337 state to 0000000059ed298d
>[13268.089258] [drm:drm_atomic_set_crtc_for_connector [drm]] Link connector state 00000000de6d4337 to [CRTC:47:pipe B]
>[13268.089262] [drm:drm_atomic_check_only [drm]] checking 0000000059ed298d
>[13268.089266] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:47:pipe B] mode changed
>[13268.089268] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:47:pipe B] enable changed
>[13268.089271] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:47:pipe B] active changed
>[13268.089273] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:56:DP-1]
>[13268.089276] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:56:DP-1] using [ENCODER:55:DDI B] on [CRTC:47:pipe B]
>[13268.089278] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:47:pipe B] needs all connectors, enable: y, active: y
>[13268.089282] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:47:pipe B] to 0000000059ed298d
>[13268.089287] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:47:pipe B] to 0000000059ed298d
>[13268.089303] [drm:intel_atomic_check [i915]] [CONNECTOR:56:DP-1] checking for sink bpp constrains
>[13268.089319] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 148500KHz
>[13268.089337] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 4 clock 270000 bpp 36
>[13268.089350] [drm:intel_dp_compute_config [i915]] DP link bw required 668250 available 1080000
>[13268.089365] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 36, dithering: 0
>[13268.089380] [drm:intel_dump_pipe_config [i915]] [CRTC:47:pipe B][modeset]
>[13268.089393] [drm:intel_dump_pipe_config [i915]] output_types: DP (0x80)
>[13268.089405] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 36, dithering: 0
>[13268.089418] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5190451, gmch_n: 8388608, link_m: 288358, link_n: 524288, tu: 64
>[13268.089430] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[13268.089441] [drm:intel_dump_pipe_config [i915]] requested mode:
>[13268.089447] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x9
>[13268.089459] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[13268.089465] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x9
>[13268.089478] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x9
>[13268.089489] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500
>[13268.089501] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[13268.089512] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[13268.089523] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[13268.089534] [drm:intel_dump_pipe_config [i915]] dpll_hw_state: ctrl1: 0x3, cfgcr1: 0x0, cfgcr2: 0x0
>[13268.089545] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[13268.089556] [drm:intel_dump_pipe_config [i915]] [PLANE:38:plane 1B] disabled, scaler_id = -1
>[13268.089567] [drm:intel_dump_pipe_config [i915]] [PLANE:41:plane 2B] disabled, scaler_id = -1
>[13268.089578] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor B] disabled, scaler_id = -1
>[13268.089592] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[13268.089605] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[13268.089619] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:47:pipe B] has [PLANE:38:plane 1B] with fb 99
>[13268.089631] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:38:plane 1B] visible 0 -> 1, off 0, on 1, ms 1
>[13268.089645] [drm:intel_find_shared_dpll [i915]] [CRTC:47:pipe B] allocated DPLL 1
>[13268.089658] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[13268.089666] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:37:pipe A] 00000000c85dec7a state to 0000000059ed298d
>[13268.089677] [drm:skl_compute_wm [i915]] [PLANE:38:plane 1B] ddb (0 - 0) -> (0 - 860)
>[13268.089688] [drm:skl_compute_wm [i915]] [PLANE:44:cursor B] ddb (0 - 0) -> (860 - 892)
>[13268.089694] [drm:drm_atomic_commit [drm]] committing 0000000059ed298d
>[13269.089459] [drm:intel_power_well_enable [i915]] enabling power well 2
>[13269.089544] [drm:intel_atomic_commit_tail [i915]] [ENCODER:48:DDI A]
>[13269.089606] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI B]
>[13269.089664] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[13269.089718] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[13269.089770] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DDI C]
>[13269.089820] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST A]
>[13269.089870] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST B]
>[13269.089920] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI D]
>[13269.089969] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[13269.090018] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[13269.090073] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[13269.090131] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[13269.090185] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[13269.090237] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[13269.090301] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 2, on? 0) for crtc 47
>[13269.090357] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[13269.090498] [drm:intel_power_well_enable [i915]] enabling DDI B IO power well
>[13269.091090] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13269.092324] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13269.093569] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13269.094797] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13269.096035] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13269.096910] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[13269.097885] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[13269.097940] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[13269.097991] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[13269.098041] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[13269.116683] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[13269.116699] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[13269.135400] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[13269.135722] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:56:DP-1] Link Training Passed at Link Rate = 270000, Lane count = 4
>[13269.136097] [drm:intel_enable_pipe [i915]] enabling pipe B
>[13269.136143] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS
>[13269.136155] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:56:DP-1], [ENCODER:55:DDI B]
>[13269.136166] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[13269.136180] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[13269.152864] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:56:DP-1]
>[13269.152880] [drm:intel_atomic_commit_tail [i915]] [CRTC:47:pipe B]
>[13269.152901] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[13269.152910] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000059ed298d
>[13269.152915] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000059ed298d
>[13269.152929] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[13269.152934] [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000059ed298d
>[13269.152939] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:47:pipe B] 00000000bd3c0152 state to 0000000059ed298d
>[13269.152943] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:38:plane 1B] 000000005906dec2 state to 0000000059ed298d
>[13269.152947] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for CRTC state 00000000bd3c0152
>[13269.152951] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 000000005906dec2 to [NOCRTC]
>[13269.152955] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for plane state 000000005906dec2
>[13269.152959] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:47:pipe B] to 0000000059ed298d
>[13269.152963] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:56:DP-1] 00000000f8eadac6 state to 0000000059ed298d
>[13269.152967] [drm:drm_atomic_set_crtc_for_connector [drm]] Link connector state 00000000f8eadac6 to [NOCRTC]
>[13269.152970] [drm:drm_atomic_check_only [drm]] checking 0000000059ed298d
>[13269.152974] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:47:pipe B] mode changed
>[13269.152976] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:47:pipe B] enable changed
>[13269.152978] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:47:pipe B] active changed
>[13269.152980] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:56:DP-1]
>[13269.152982] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Disabling [CONNECTOR:56:DP-1]
>[13269.152984] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:47:pipe B] needs all connectors, enable: n, active: n
>[13269.152988] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:47:pipe B] to 0000000059ed298d
>[13269.153004] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[13269.153017] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[13269.153031] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:47:pipe B] has [PLANE:38:plane 1B] with fb -1
>[13269.153044] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:38:plane 1B] visible 1 -> 0, off 1, on 0, ms 1
>[13269.153050] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:37:pipe A] 000000002b48c403 state to 0000000059ed298d
>[13269.153061] [drm:skl_compute_wm [i915]] [PLANE:38:plane 1B] ddb (0 - 860) -> (0 - 0)
>[13269.153071] [drm:skl_compute_wm [i915]] [PLANE:44:cursor B] ddb (860 - 892) -> (0 - 0)
>[13269.153076] [drm:drm_atomic_commit [drm]] committing 0000000059ed298d
>[13269.153096] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[13269.153109] [drm:i915_audio_component_get_eld [i915]] Not valid for port B
>[13269.153126] [drm:intel_disable_pipe [i915]] disabling pipe B
>[13269.171590] [drm:intel_power_well_disable [i915]] disabling DDI B IO power well
>[13269.171608] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 2, on? 1) for crtc 47
>[13269.171623] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[13269.171645] [drm:intel_atomic_commit_tail [i915]] [ENCODER:48:DDI A]
>[13269.171658] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI B]
>[13269.171671] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[13269.171683] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[13269.171695] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DDI C]
>[13269.171707] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST A]
>[13269.171718] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST B]
>[13269.171729] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI D]
>[13269.171740] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[13269.171751] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[13269.171764] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:56:DP-1]
>[13269.171777] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[13269.171789] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[13269.171802] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[13269.171813] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[13269.171826] [drm:intel_power_well_disable [i915]] disabling power well 2
>[13269.171841] [drm:intel_atomic_commit_tail [i915]] [CRTC:47:pipe B]
>[13269.171849] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000059ed298d
>[13269.171856] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000059ed298d
>[13269.171911] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[13269.171917] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:56:DP-1]
>[13269.171923] [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000059ed298d
>[13269.171929] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:47:pipe B] 00000000604357f6 state to 0000000059ed298d
>[13269.171935] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:38:plane 1B] 00000000c4c517e9 state to 0000000059ed298d
>[13269.171940] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [MODE:1920x1080] for CRTC state 00000000604357f6
>[13269.171944] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 00000000c4c517e9 to [CRTC:47:pipe B]
>[13269.171949] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:98] for plane state 00000000c4c517e9
>[13269.171953] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:47:pipe B] to 0000000059ed298d
>[13269.171958] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:56:DP-1] 000000005a636f37 state to 0000000059ed298d
>[13269.171962] [drm:drm_atomic_set_crtc_for_connector [drm]] Link connector state 000000005a636f37 to [CRTC:47:pipe B]
>[13269.171967] [drm:drm_atomic_check_only [drm]] checking 0000000059ed298d
>[13269.171970] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:47:pipe B] mode changed
>[13269.171973] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:47:pipe B] enable changed
>[13269.171975] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:47:pipe B] active changed
>[13269.171977] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:56:DP-1]
>[13269.171980] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:56:DP-1] using [ENCODER:55:DDI B] on [CRTC:47:pipe B]
>[13269.171982] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:47:pipe B] needs all connectors, enable: y, active: y
>[13269.171987] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:47:pipe B] to 0000000059ed298d
>[13269.171991] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:47:pipe B] to 0000000059ed298d
>[13269.172007] [drm:intel_atomic_check [i915]] [CONNECTOR:56:DP-1] checking for sink bpp constrains
>[13269.172023] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 148500KHz
>[13269.172041] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 4 clock 270000 bpp 36
>[13269.172054] [drm:intel_dp_compute_config [i915]] DP link bw required 668250 available 1080000
>[13269.172069] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 36, dithering: 0
>[13269.172083] [drm:intel_dump_pipe_config [i915]] [CRTC:47:pipe B][modeset]
>[13269.172097] [drm:intel_dump_pipe_config [i915]] output_types: DP (0x80)
>[13269.172109] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 36, dithering: 0
>[13269.172122] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5190451, gmch_n: 8388608, link_m: 288358, link_n: 524288, tu: 64
>[13269.172134] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[13269.172145] [drm:intel_dump_pipe_config [i915]] requested mode:
>[13269.172152] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x9
>[13269.172164] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[13269.172170] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x9
>[13269.172183] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x9
>[13269.172194] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500
>[13269.172206] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[13269.172218] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[13269.172229] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[13269.172240] [drm:intel_dump_pipe_config [i915]] dpll_hw_state: ctrl1: 0x3, cfgcr1: 0x0, cfgcr2: 0x0
>[13269.172250] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[13269.172261] [drm:intel_dump_pipe_config [i915]] [PLANE:38:plane 1B] disabled, scaler_id = -1
>[13269.172272] [drm:intel_dump_pipe_config [i915]] [PLANE:41:plane 2B] disabled, scaler_id = -1
>[13269.172283] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor B] disabled, scaler_id = -1
>[13269.172297] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[13269.172309] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[13269.172323] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:47:pipe B] has [PLANE:38:plane 1B] with fb 98
>[13269.172336] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:38:plane 1B] visible 0 -> 1, off 0, on 1, ms 1
>[13269.172350] [drm:intel_find_shared_dpll [i915]] [CRTC:47:pipe B] allocated DPLL 1
>[13269.172362] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[13269.172370] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:37:pipe A] 00000000c85dec7a state to 0000000059ed298d
>[13269.172382] [drm:skl_compute_wm [i915]] [PLANE:38:plane 1B] ddb (0 - 0) -> (0 - 860)
>[13269.172392] [drm:skl_compute_wm [i915]] [PLANE:44:cursor B] ddb (0 - 0) -> (860 - 892)
>[13269.172398] [drm:drm_atomic_commit [drm]] committing 0000000059ed298d
>[13270.172167] [drm:intel_power_well_enable [i915]] enabling power well 2
>[13270.172250] [drm:intel_atomic_commit_tail [i915]] [ENCODER:48:DDI A]
>[13270.172314] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI B]
>[13270.172371] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[13270.172425] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[13270.172477] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DDI C]
>[13270.172528] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST A]
>[13270.172577] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST B]
>[13270.172627] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI D]
>[13270.172676] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[13270.172770] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[13270.172836] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[13270.172913] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[13270.172968] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[13270.173029] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[13270.173094] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 2, on? 0) for crtc 47
>[13270.173152] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[13270.173293] [drm:intel_power_well_enable [i915]] enabling DDI B IO power well
>[13270.173886] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13270.175123] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13270.176361] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13270.177552] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13270.178790] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13270.179647] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[13270.180621] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[13270.180676] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[13270.180758] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[13270.180817] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[13270.199473] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[13270.199487] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[13270.217307] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[13270.217629] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:56:DP-1] Link Training Passed at Link Rate = 270000, Lane count = 4
>[13270.218003] [drm:intel_enable_pipe [i915]] enabling pipe B
>[13270.218019] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS
>[13270.218031] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:56:DP-1], [ENCODER:55:DDI B]
>[13270.218042] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[13270.218055] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[13270.234808] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:56:DP-1]
>[13270.234824] [drm:intel_atomic_commit_tail [i915]] [CRTC:47:pipe B]
>[13270.234845] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[13270.234854] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000059ed298d
>[13270.234859] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000059ed298d
>[13270.234872] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[13270.234878] [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000059ed298d
>[13270.234883] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:47:pipe B] 00000000bd3c0152 state to 0000000059ed298d
>[13270.234887] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:38:plane 1B] 00000000ab8e9814 state to 0000000059ed298d
>[13270.234891] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for CRTC state 00000000bd3c0152
>[13270.234895] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 00000000ab8e9814 to [NOCRTC]
>[13270.234899] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for plane state 00000000ab8e9814
>[13270.234902] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:47:pipe B] to 0000000059ed298d
>[13270.234906] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:56:DP-1] 00000000d1e5643f state to 0000000059ed298d
>[13270.234910] [drm:drm_atomic_set_crtc_for_connector [drm]] Link connector state 00000000d1e5643f to [NOCRTC]
>[13270.234914] [drm:drm_atomic_check_only [drm]] checking 0000000059ed298d
>[13270.234917] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:47:pipe B] mode changed
>[13270.234919] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:47:pipe B] enable changed
>[13270.234921] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:47:pipe B] active changed
>[13270.234923] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:56:DP-1]
>[13270.234925] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Disabling [CONNECTOR:56:DP-1]
>[13270.234928] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:47:pipe B] needs all connectors, enable: n, active: n
>[13270.234931] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:47:pipe B] to 0000000059ed298d
>[13270.234947] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[13270.234961] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[13270.234975] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:47:pipe B] has [PLANE:38:plane 1B] with fb -1
>[13270.234988] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:38:plane 1B] visible 1 -> 0, off 1, on 0, ms 1
>[13270.234994] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:37:pipe A] 000000002b48c403 state to 0000000059ed298d
>[13270.235005] [drm:skl_compute_wm [i915]] [PLANE:38:plane 1B] ddb (0 - 860) -> (0 - 0)
>[13270.235015] [drm:skl_compute_wm [i915]] [PLANE:44:cursor B] ddb (860 - 892) -> (0 - 0)
>[13270.235020] [drm:drm_atomic_commit [drm]] committing 0000000059ed298d
>[13270.235039] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[13270.235052] [drm:i915_audio_component_get_eld [i915]] Not valid for port B
>[13270.235069] [drm:intel_disable_pipe [i915]] disabling pipe B
>[13270.252918] [drm:intel_power_well_disable [i915]] disabling DDI B IO power well
>[13270.252936] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 2, on? 1) for crtc 47
>[13270.252951] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[13270.252974] [drm:intel_atomic_commit_tail [i915]] [ENCODER:48:DDI A]
>[13270.252988] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI B]
>[13270.253001] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[13270.253012] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[13270.253024] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DDI C]
>[13270.253035] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST A]
>[13270.253046] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST B]
>[13270.253057] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI D]
>[13270.253068] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[13270.253079] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[13270.253092] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:56:DP-1]
>[13270.253105] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[13270.253118] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[13270.253130] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[13270.253142] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[13270.253155] [drm:intel_power_well_disable [i915]] disabling power well 2
>[13270.253170] [drm:intel_atomic_commit_tail [i915]] [CRTC:47:pipe B]
>[13270.253179] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000059ed298d
>[13270.253185] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000059ed298d
>[13270.253241] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[13270.253247] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:56:DP-1]
>[13270.253253] [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000059ed298d
>[13270.253259] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:47:pipe B] 00000000604357f6 state to 0000000059ed298d
>[13270.253264] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:38:plane 1B] 000000005906dec2 state to 0000000059ed298d
>[13270.253270] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [MODE:1920x1080] for CRTC state 00000000604357f6
>[13270.253274] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 000000005906dec2 to [CRTC:47:pipe B]
>[13270.253279] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:99] for plane state 000000005906dec2
>[13270.253284] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:47:pipe B] to 0000000059ed298d
>[13270.253288] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:56:DP-1] 00000000f8eadac6 state to 0000000059ed298d
>[13270.253292] [drm:drm_atomic_set_crtc_for_connector [drm]] Link connector state 00000000f8eadac6 to [CRTC:47:pipe B]
>[13270.253297] [drm:drm_atomic_check_only [drm]] checking 0000000059ed298d
>[13270.253301] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:47:pipe B] mode changed
>[13270.253303] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:47:pipe B] enable changed
>[13270.253305] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:47:pipe B] active changed
>[13270.253308] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:56:DP-1]
>[13270.253310] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:56:DP-1] using [ENCODER:55:DDI B] on [CRTC:47:pipe B]
>[13270.253313] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:47:pipe B] needs all connectors, enable: y, active: y
>[13270.253317] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:47:pipe B] to 0000000059ed298d
>[13270.253322] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:47:pipe B] to 0000000059ed298d
>[13270.253338] [drm:intel_atomic_check [i915]] [CONNECTOR:56:DP-1] checking for sink bpp constrains
>[13270.253354] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 148500KHz
>[13270.253372] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 4 clock 270000 bpp 36
>[13270.253385] [drm:intel_dp_compute_config [i915]] DP link bw required 668250 available 1080000
>[13270.253399] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 36, dithering: 0
>[13270.253414] [drm:intel_dump_pipe_config [i915]] [CRTC:47:pipe B][modeset]
>[13270.253427] [drm:intel_dump_pipe_config [i915]] output_types: DP (0x80)
>[13270.253439] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 36, dithering: 0
>[13270.253452] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5190451, gmch_n: 8388608, link_m: 288358, link_n: 524288, tu: 64
>[13270.253463] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[13270.253475] [drm:intel_dump_pipe_config [i915]] requested mode:
>[13270.253481] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x9
>[13270.253493] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[13270.253499] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x9
>[13270.253512] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x9
>[13270.253523] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500
>[13270.253535] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[13270.253546] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[13270.253557] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[13270.253569] [drm:intel_dump_pipe_config [i915]] dpll_hw_state: ctrl1: 0x3, cfgcr1: 0x0, cfgcr2: 0x0
>[13270.253579] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[13270.253591] [drm:intel_dump_pipe_config [i915]] [PLANE:38:plane 1B] disabled, scaler_id = -1
>[13270.253601] [drm:intel_dump_pipe_config [i915]] [PLANE:41:plane 2B] disabled, scaler_id = -1
>[13270.253612] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor B] disabled, scaler_id = -1
>[13270.253626] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[13270.253639] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[13270.253653] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:47:pipe B] has [PLANE:38:plane 1B] with fb 99
>[13270.253665] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:38:plane 1B] visible 0 -> 1, off 0, on 1, ms 1
>[13270.253679] [drm:intel_find_shared_dpll [i915]] [CRTC:47:pipe B] allocated DPLL 1
>[13270.253692] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[13270.253700] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:37:pipe A] 00000000c85dec7a state to 0000000059ed298d
>[13270.253711] [drm:skl_compute_wm [i915]] [PLANE:38:plane 1B] ddb (0 - 0) -> (0 - 860)
>[13270.253722] [drm:skl_compute_wm [i915]] [PLANE:44:cursor B] ddb (0 - 0) -> (860 - 892)
>[13270.253728] [drm:drm_atomic_commit [drm]] committing 0000000059ed298d
>[13271.253497] [drm:intel_power_well_enable [i915]] enabling power well 2
>[13271.253580] [drm:intel_atomic_commit_tail [i915]] [ENCODER:48:DDI A]
>[13271.253644] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI B]
>[13271.253701] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[13271.253755] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[13271.253806] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DDI C]
>[13271.253856] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST A]
>[13271.253905] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST B]
>[13271.253954] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI D]
>[13271.254002] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[13271.254049] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[13271.254104] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[13271.254160] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[13271.254213] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[13271.254265] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[13271.254327] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 2, on? 0) for crtc 47
>[13271.254383] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[13271.254524] [drm:intel_power_well_enable [i915]] enabling DDI B IO power well
>[13271.255116] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13271.256357] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13271.257608] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13271.258835] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13271.260069] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13271.260995] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[13271.261970] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[13271.262026] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[13271.262078] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[13271.262128] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[13271.280820] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[13271.280850] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[13271.299550] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[13271.299873] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:56:DP-1] Link Training Passed at Link Rate = 270000, Lane count = 4
>[13271.300262] [drm:intel_enable_pipe [i915]] enabling pipe B
>[13271.300293] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS
>[13271.300305] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:56:DP-1], [ENCODER:55:DDI B]
>[13271.300317] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[13271.300330] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[13271.317073] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:56:DP-1]
>[13271.317089] [drm:intel_atomic_commit_tail [i915]] [CRTC:47:pipe B]
>[13271.317110] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[13271.317118] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000059ed298d
>[13271.317124] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000059ed298d
>[13271.317137] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[13271.317142] [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000059ed298d
>[13271.317148] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:47:pipe B] 00000000bd3c0152 state to 0000000059ed298d
>[13271.317152] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:38:plane 1B] 00000000c4c517e9 state to 0000000059ed298d
>[13271.317156] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for CRTC state 00000000bd3c0152
>[13271.317160] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 00000000c4c517e9 to [NOCRTC]
>[13271.317164] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for plane state 00000000c4c517e9
>[13271.317168] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:47:pipe B] to 0000000059ed298d
>[13271.317172] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:56:DP-1] 00000000de6d4337 state to 0000000059ed298d
>[13271.317175] [drm:drm_atomic_set_crtc_for_connector [drm]] Link connector state 00000000de6d4337 to [NOCRTC]
>[13271.317179] [drm:drm_atomic_check_only [drm]] checking 0000000059ed298d
>[13271.317182] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:47:pipe B] mode changed
>[13271.317185] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:47:pipe B] enable changed
>[13271.317187] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:47:pipe B] active changed
>[13271.317189] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:56:DP-1]
>[13271.317191] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Disabling [CONNECTOR:56:DP-1]
>[13271.317193] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:47:pipe B] needs all connectors, enable: n, active: n
>[13271.317197] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:47:pipe B] to 0000000059ed298d
>[13271.317213] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[13271.317226] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[13271.317240] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:47:pipe B] has [PLANE:38:plane 1B] with fb -1
>[13271.317253] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:38:plane 1B] visible 1 -> 0, off 1, on 0, ms 1
>[13271.317259] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:37:pipe A] 000000002b48c403 state to 0000000059ed298d
>[13271.317270] [drm:skl_compute_wm [i915]] [PLANE:38:plane 1B] ddb (0 - 860) -> (0 - 0)
>[13271.317279] [drm:skl_compute_wm [i915]] [PLANE:44:cursor B] ddb (860 - 892) -> (0 - 0)
>[13271.317284] [drm:drm_atomic_commit [drm]] committing 0000000059ed298d
>[13271.317304] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[13271.317317] [drm:i915_audio_component_get_eld [i915]] Not valid for port B
>[13271.317334] [drm:intel_disable_pipe [i915]] disabling pipe B
>[13271.335569] [drm:intel_power_well_disable [i915]] disabling DDI B IO power well
>[13271.335587] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 2, on? 1) for crtc 47
>[13271.335602] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[13271.335624] [drm:intel_atomic_commit_tail [i915]] [ENCODER:48:DDI A]
>[13271.335638] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI B]
>[13271.335651] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[13271.335663] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[13271.335674] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DDI C]
>[13271.335686] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST A]
>[13271.335697] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST B]
>[13271.335708] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI D]
>[13271.335719] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[13271.335731] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[13271.335743] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:56:DP-1]
>[13271.335756] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[13271.335769] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[13271.335782] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[13271.335794] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[13271.335806] [drm:intel_power_well_disable [i915]] disabling power well 2
>[13271.335821] [drm:intel_atomic_commit_tail [i915]] [CRTC:47:pipe B]
>[13271.335830] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000059ed298d
>[13271.335836] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000059ed298d
>[13271.335895] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[13271.335901] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:56:DP-1]
>[13271.335907] [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000059ed298d
>[13271.335913] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:47:pipe B] 00000000604357f6 state to 0000000059ed298d
>[13271.335918] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:38:plane 1B] 00000000ab8e9814 state to 0000000059ed298d
>[13271.335924] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [MODE:1920x1080] for CRTC state 00000000604357f6
>[13271.335928] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 00000000ab8e9814 to [CRTC:47:pipe B]
>[13271.335933] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:98] for plane state 00000000ab8e9814
>[13271.335937] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:47:pipe B] to 0000000059ed298d
>[13271.335942] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:56:DP-1] 00000000d1e5643f state to 0000000059ed298d
>[13271.335946] [drm:drm_atomic_set_crtc_for_connector [drm]] Link connector state 00000000d1e5643f to [CRTC:47:pipe B]
>[13271.335950] [drm:drm_atomic_check_only [drm]] checking 0000000059ed298d
>[13271.335954] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:47:pipe B] mode changed
>[13271.335956] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:47:pipe B] enable changed
>[13271.335959] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:47:pipe B] active changed
>[13271.335961] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:56:DP-1]
>[13271.335964] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:56:DP-1] using [ENCODER:55:DDI B] on [CRTC:47:pipe B]
>[13271.335966] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:47:pipe B] needs all connectors, enable: y, active: y
>[13271.335970] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:47:pipe B] to 0000000059ed298d
>[13271.335975] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:47:pipe B] to 0000000059ed298d
>[13271.335991] [drm:intel_atomic_check [i915]] [CONNECTOR:56:DP-1] checking for sink bpp constrains
>[13271.336006] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 148500KHz
>[13271.336024] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 4 clock 270000 bpp 36
>[13271.336038] [drm:intel_dp_compute_config [i915]] DP link bw required 668250 available 1080000
>[13271.336052] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 36, dithering: 0
>[13271.336066] [drm:intel_dump_pipe_config [i915]] [CRTC:47:pipe B][modeset]
>[13271.336079] [drm:intel_dump_pipe_config [i915]] output_types: DP (0x80)
>[13271.336092] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 36, dithering: 0
>[13271.336104] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5190451, gmch_n: 8388608, link_m: 288358, link_n: 524288, tu: 64
>[13271.336116] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[13271.336127] [drm:intel_dump_pipe_config [i915]] requested mode:
>[13271.336134] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x9
>[13271.336146] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[13271.336152] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x9
>[13271.336164] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x9
>[13271.336176] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500
>[13271.336187] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[13271.336198] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[13271.336209] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[13271.336220] [drm:intel_dump_pipe_config [i915]] dpll_hw_state: ctrl1: 0x3, cfgcr1: 0x0, cfgcr2: 0x0
>[13271.336231] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[13271.336242] [drm:intel_dump_pipe_config [i915]] [PLANE:38:plane 1B] disabled, scaler_id = -1
>[13271.336253] [drm:intel_dump_pipe_config [i915]] [PLANE:41:plane 2B] disabled, scaler_id = -1
>[13271.336264] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor B] disabled, scaler_id = -1
>[13271.336278] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[13271.336290] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[13271.336304] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:47:pipe B] has [PLANE:38:plane 1B] with fb 98
>[13271.336317] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:38:plane 1B] visible 0 -> 1, off 0, on 1, ms 1
>[13271.336331] [drm:intel_find_shared_dpll [i915]] [CRTC:47:pipe B] allocated DPLL 1
>[13271.336344] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[13271.336351] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:37:pipe A] 00000000c85dec7a state to 0000000059ed298d
>[13271.336363] [drm:skl_compute_wm [i915]] [PLANE:38:plane 1B] ddb (0 - 0) -> (0 - 860)
>[13271.336373] [drm:skl_compute_wm [i915]] [PLANE:44:cursor B] ddb (0 - 0) -> (860 - 892)
>[13271.336379] [drm:drm_atomic_commit [drm]] committing 0000000059ed298d
>[13272.336148] [drm:intel_power_well_enable [i915]] enabling power well 2
>[13272.336232] [drm:intel_atomic_commit_tail [i915]] [ENCODER:48:DDI A]
>[13272.336297] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI B]
>[13272.336355] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[13272.336410] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[13272.336462] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DDI C]
>[13272.336512] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST A]
>[13272.336562] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST B]
>[13272.336612] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI D]
>[13272.336661] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[13272.336709] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[13272.336803] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[13272.336868] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[13272.336930] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[13272.336986] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[13272.337057] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 2, on? 0) for crtc 47
>[13272.337117] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[13272.337260] [drm:intel_power_well_enable [i915]] enabling DDI B IO power well
>[13272.337855] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13272.339090] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13272.340333] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13272.341526] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13272.342761] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13272.343617] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[13272.344591] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[13272.344646] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[13272.344697] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[13272.344776] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[13272.363431] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[13272.363460] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[13272.381197] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[13272.381374] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:56:DP-1] Link Training Passed at Link Rate = 270000, Lane count = 4
>[13272.381748] [drm:intel_enable_pipe [i915]] enabling pipe B
>[13272.381788] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS
>[13272.381801] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:56:DP-1], [ENCODER:55:DDI B]
>[13272.381812] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[13272.381826] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[13272.398578] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:56:DP-1]
>[13272.398594] [drm:intel_atomic_commit_tail [i915]] [CRTC:47:pipe B]
>[13272.398615] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[13272.398623] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000059ed298d
>[13272.398629] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000059ed298d
>[13272.398642] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[13272.398647] [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000059ed298d
>[13272.398652] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:47:pipe B] 00000000bd3c0152 state to 0000000059ed298d
>[13272.398657] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:38:plane 1B] 000000005906dec2 state to 0000000059ed298d
>[13272.398661] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for CRTC state 00000000bd3c0152
>[13272.398665] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 000000005906dec2 to [NOCRTC]
>[13272.398668] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for plane state 000000005906dec2
>[13272.398672] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:47:pipe B] to 0000000059ed298d
>[13272.398676] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:56:DP-1] 000000005a636f37 state to 0000000059ed298d
>[13272.398680] [drm:drm_atomic_set_crtc_for_connector [drm]] Link connector state 000000005a636f37 to [NOCRTC]
>[13272.398684] [drm:drm_atomic_check_only [drm]] checking 0000000059ed298d
>[13272.398687] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:47:pipe B] mode changed
>[13272.398690] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:47:pipe B] enable changed
>[13272.398692] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:47:pipe B] active changed
>[13272.398694] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:56:DP-1]
>[13272.398696] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Disabling [CONNECTOR:56:DP-1]
>[13272.398698] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:47:pipe B] needs all connectors, enable: n, active: n
>[13272.398702] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:47:pipe B] to 0000000059ed298d
>[13272.398718] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[13272.398731] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[13272.398745] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:47:pipe B] has [PLANE:38:plane 1B] with fb -1
>[13272.398758] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:38:plane 1B] visible 1 -> 0, off 1, on 0, ms 1
>[13272.398764] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:37:pipe A] 000000002b48c403 state to 0000000059ed298d
>[13272.398775] [drm:skl_compute_wm [i915]] [PLANE:38:plane 1B] ddb (0 - 860) -> (0 - 0)
>[13272.398785] [drm:skl_compute_wm [i915]] [PLANE:44:cursor B] ddb (860 - 892) -> (0 - 0)
>[13272.398790] [drm:drm_atomic_commit [drm]] committing 0000000059ed298d
>[13272.398810] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[13272.398824] [drm:i915_audio_component_get_eld [i915]] Not valid for port B
>[13272.398840] [drm:intel_disable_pipe [i915]] disabling pipe B
>[13272.415574] [drm:intel_power_well_disable [i915]] disabling DDI B IO power well
>[13272.415592] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 2, on? 1) for crtc 47
>[13272.415607] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[13272.415629] [drm:intel_atomic_commit_tail [i915]] [ENCODER:48:DDI A]
>[13272.415643] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI B]
>[13272.415656] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[13272.415668] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[13272.415680] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DDI C]
>[13272.415691] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST A]
>[13272.415702] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST B]
>[13272.415713] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI D]
>[13272.415724] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[13272.415736] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[13272.415748] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:56:DP-1]
>[13272.415761] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[13272.415774] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[13272.415786] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[13272.415798] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[13272.415811] [drm:intel_power_well_disable [i915]] disabling power well 2
>[13272.415826] [drm:intel_atomic_commit_tail [i915]] [CRTC:47:pipe B]
>[13272.415834] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000059ed298d
>[13272.415841] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000059ed298d
>[13272.415897] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[13272.415903] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:56:DP-1]
>[13272.415909] [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000059ed298d
>[13272.415915] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:47:pipe B] 00000000604357f6 state to 0000000059ed298d
>[13272.415920] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:38:plane 1B] 00000000c4c517e9 state to 0000000059ed298d
>[13272.415925] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [MODE:1920x1080] for CRTC state 00000000604357f6
>[13272.415930] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 00000000c4c517e9 to [CRTC:47:pipe B]
>[13272.415934] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:99] for plane state 00000000c4c517e9
>[13272.415939] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:47:pipe B] to 0000000059ed298d
>[13272.415944] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:56:DP-1] 00000000de6d4337 state to 0000000059ed298d
>[13272.415948] [drm:drm_atomic_set_crtc_for_connector [drm]] Link connector state 00000000de6d4337 to [CRTC:47:pipe B]
>[13272.415952] [drm:drm_atomic_check_only [drm]] checking 0000000059ed298d
>[13272.415956] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:47:pipe B] mode changed
>[13272.415959] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:47:pipe B] enable changed
>[13272.415961] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:47:pipe B] active changed
>[13272.415963] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:56:DP-1]
>[13272.415966] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:56:DP-1] using [ENCODER:55:DDI B] on [CRTC:47:pipe B]
>[13272.415968] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:47:pipe B] needs all connectors, enable: y, active: y
>[13272.415972] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:47:pipe B] to 0000000059ed298d
>[13272.415977] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:47:pipe B] to 0000000059ed298d
>[13272.415993] [drm:intel_atomic_check [i915]] [CONNECTOR:56:DP-1] checking for sink bpp constrains
>[13272.416009] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 148500KHz
>[13272.416027] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 4 clock 270000 bpp 36
>[13272.416040] [drm:intel_dp_compute_config [i915]] DP link bw required 668250 available 1080000
>[13272.416054] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 36, dithering: 0
>[13272.416069] [drm:intel_dump_pipe_config [i915]] [CRTC:47:pipe B][modeset]
>[13272.416082] [drm:intel_dump_pipe_config [i915]] output_types: DP (0x80)
>[13272.416094] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 36, dithering: 0
>[13272.416107] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5190451, gmch_n: 8388608, link_m: 288358, link_n: 524288, tu: 64
>[13272.416119] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[13272.416130] [drm:intel_dump_pipe_config [i915]] requested mode:
>[13272.416137] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x9
>[13272.416149] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[13272.416155] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x9
>[13272.416167] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x9
>[13272.416179] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500
>[13272.416190] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[13272.416202] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[13272.416212] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[13272.416223] [drm:intel_dump_pipe_config [i915]] dpll_hw_state: ctrl1: 0x3, cfgcr1: 0x0, cfgcr2: 0x0
>[13272.416234] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[13272.416245] [drm:intel_dump_pipe_config [i915]] [PLANE:38:plane 1B] disabled, scaler_id = -1
>[13272.416256] [drm:intel_dump_pipe_config [i915]] [PLANE:41:plane 2B] disabled, scaler_id = -1
>[13272.416267] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor B] disabled, scaler_id = -1
>[13272.416281] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[13272.416294] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[13272.416308] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:47:pipe B] has [PLANE:38:plane 1B] with fb 99
>[13272.416320] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:38:plane 1B] visible 0 -> 1, off 0, on 1, ms 1
>[13272.416334] [drm:intel_find_shared_dpll [i915]] [CRTC:47:pipe B] allocated DPLL 1
>[13272.416347] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[13272.416354] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:37:pipe A] 00000000c85dec7a state to 0000000059ed298d
>[13272.416366] [drm:skl_compute_wm [i915]] [PLANE:38:plane 1B] ddb (0 - 0) -> (0 - 860)
>[13272.416376] [drm:skl_compute_wm [i915]] [PLANE:44:cursor B] ddb (0 - 0) -> (860 - 892)
>[13272.416383] [drm:drm_atomic_commit [drm]] committing 0000000059ed298d
>[13273.416154] [drm:intel_power_well_enable [i915]] enabling power well 2
>[13273.416238] [drm:intel_atomic_commit_tail [i915]] [ENCODER:48:DDI A]
>[13273.416303] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI B]
>[13273.416361] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[13273.416415] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[13273.416466] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DDI C]
>[13273.416517] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST A]
>[13273.416567] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST B]
>[13273.416616] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI D]
>[13273.416665] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[13273.416714] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[13273.416809] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[13273.416874] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[13273.416935] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[13273.416992] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[13273.417059] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 2, on? 0) for crtc 47
>[13273.417121] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[13273.417264] [drm:intel_power_well_enable [i915]] enabling DDI B IO power well
>[13273.417858] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13273.419092] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13273.420328] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13273.421519] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13273.422756] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13273.423613] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[13273.424588] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[13273.424642] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[13273.424693] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[13273.424774] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[13273.443444] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[13273.443458] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[13273.461284] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[13273.461607] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:56:DP-1] Link Training Passed at Link Rate = 270000, Lane count = 4
>[13273.461997] [drm:intel_enable_pipe [i915]] enabling pipe B
>[13273.462027] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS
>[13273.462039] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:56:DP-1], [ENCODER:55:DDI B]
>[13273.462051] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe B, 36 bytes ELD
>[13273.462064] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[13273.478814] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:56:DP-1]
>[13273.478831] [drm:intel_atomic_commit_tail [i915]] [CRTC:47:pipe B]
>[13273.478851] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[13273.478860] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000059ed298d
>[13273.478866] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000059ed298d
>[13273.478879] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[13273.478884] [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000059ed298d
>[13273.478889] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:47:pipe B] 00000000bd3c0152 state to 0000000059ed298d
>[13273.478894] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:38:plane 1B] 00000000ab8e9814 state to 0000000059ed298d
>[13273.478898] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for CRTC state 00000000bd3c0152
>[13273.478902] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 00000000ab8e9814 to [NOCRTC]
>[13273.478906] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for plane state 00000000ab8e9814
>[13273.478910] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:47:pipe B] to 0000000059ed298d
>[13273.478914] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:56:DP-1] 00000000f8eadac6 state to 0000000059ed298d
>[13273.478918] [drm:drm_atomic_set_crtc_for_connector [drm]] Link connector state 00000000f8eadac6 to [NOCRTC]
>[13273.478921] [drm:drm_atomic_check_only [drm]] checking 0000000059ed298d
>[13273.478925] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:47:pipe B] mode changed
>[13273.478927] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:47:pipe B] enable changed
>[13273.478929] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:47:pipe B] active changed
>[13273.478931] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:56:DP-1]
>[13273.478933] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Disabling [CONNECTOR:56:DP-1]
>[13273.478935] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:47:pipe B] needs all connectors, enable: n, active: n
>[13273.478939] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:47:pipe B] to 0000000059ed298d
>[13273.478955] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[13273.478969] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[13273.478983] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:47:pipe B] has [PLANE:38:plane 1B] with fb -1
>[13273.478995] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:38:plane 1B] visible 1 -> 0, off 1, on 0, ms 1
>[13273.479001] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:37:pipe A] 000000002b48c403 state to 0000000059ed298d
>[13273.479012] [drm:skl_compute_wm [i915]] [PLANE:38:plane 1B] ddb (0 - 860) -> (0 - 0)
>[13273.479022] [drm:skl_compute_wm [i915]] [PLANE:44:cursor B] ddb (860 - 892) -> (0 - 0)
>[13273.479027] [drm:drm_atomic_commit [drm]] committing 0000000059ed298d
>[13273.479047] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe B
>[13273.479060] [drm:i915_audio_component_get_eld [i915]] Not valid for port B
>[13273.479076] [drm:intel_disable_pipe [i915]] disabling pipe B
>[13273.495572] [drm:intel_power_well_disable [i915]] disabling DDI B IO power well
>[13273.495591] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 2, on? 1) for crtc 47
>[13273.495606] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[13273.495628] [drm:intel_atomic_commit_tail [i915]] [ENCODER:48:DDI A]
>[13273.495642] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI B]
>[13273.495655] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[13273.495667] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[13273.495679] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DDI C]
>[13273.495690] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST A]
>[13273.495702] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST B]
>[13273.495713] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI D]
>[13273.495724] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[13273.495735] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[13273.495747] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:56:DP-1]
>[13273.495760] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[13273.495773] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[13273.495785] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[13273.495797] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[13273.495810] [drm:intel_power_well_disable [i915]] disabling power well 2
>[13273.495825] [drm:intel_atomic_commit_tail [i915]] [CRTC:47:pipe B]
>[13273.495833] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000059ed298d
>[13273.495840] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000059ed298d
>[13273.495889] [drm:drm_mode_addfb2 [drm]] [FB:98]
>[13273.495899] [drm:drm_mode_addfb2 [drm]] [FB:99]
>[13273.511512] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[13273.511521] [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000059ed298d
>[13273.511528] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:37:pipe A] 00000000604357f6 state to 0000000059ed298d
>[13273.511535] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000c4c517e9 state to 0000000059ed298d
>[13273.511540] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for CRTC state 00000000604357f6
>[13273.511544] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 00000000c4c517e9 to [NOCRTC]
>[13273.511548] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for plane state 00000000c4c517e9
>[13273.511553] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:37:pipe A] to 0000000059ed298d
>[13273.511558] [drm:drm_atomic_check_only [drm]] checking 0000000059ed298d
>[13273.511564] [drm:drm_atomic_commit [drm]] committing 0000000059ed298d
>[13273.511576] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000059ed298d
>[13273.511581] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000059ed298d
>[13273.511587] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[13273.511592] [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000059ed298d
>[13273.511596] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:47:pipe B] 000000002b48c403 state to 0000000059ed298d
>[13273.511601] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:38:plane 1B] 00000000dbafe848 state to 0000000059ed298d
>[13273.511605] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for CRTC state 000000002b48c403
>[13273.511609] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 00000000dbafe848 to [NOCRTC]
>[13273.511612] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for plane state 00000000dbafe848
>[13273.511616] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:47:pipe B] to 0000000059ed298d
>[13273.511620] [drm:drm_atomic_check_only [drm]] checking 0000000059ed298d
>[13273.511625] [drm:drm_atomic_commit [drm]] committing 0000000059ed298d
>[13273.511632] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000059ed298d
>[13273.511636] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000059ed298d
>[13273.511642] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[13273.511648] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:61:DP-2]
>[13273.511652] [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000059ed298d
>[13273.511657] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:37:pipe A] 00000000bd3c0152 state to 0000000059ed298d
>[13273.511661] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 000000005906dec2 state to 0000000059ed298d
>[13273.511665] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [MODE:1920x1200] for CRTC state 00000000bd3c0152
>[13273.511669] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 000000005906dec2 to [CRTC:37:pipe A]
>[13273.511673] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:98] for plane state 000000005906dec2
>[13273.511677] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:37:pipe A] to 0000000059ed298d
>[13273.511681] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:61:DP-2] 000000005a636f37 state to 0000000059ed298d
>[13273.511685] [drm:drm_atomic_set_crtc_for_connector [drm]] Link connector state 000000005a636f37 to [CRTC:37:pipe A]
>[13273.511690] [drm:drm_atomic_check_only [drm]] checking 0000000059ed298d
>[13273.511695] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:37:pipe A] mode changed
>[13273.511697] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:37:pipe A] enable changed
>[13273.511700] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:37:pipe A] active changed
>[13273.511702] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:61:DP-2]
>[13273.511705] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:61:DP-2] using [ENCODER:60:DDI C] on [CRTC:37:pipe A]
>[13273.511707] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:37:pipe A] needs all connectors, enable: y, active: y
>[13273.511712] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:37:pipe A] to 0000000059ed298d
>[13273.511716] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:37:pipe A] to 0000000059ed298d
>[13273.511736] [drm:intel_atomic_check [i915]] [CONNECTOR:61:DP-2] checking for sink bpp constrains
>[13273.511751] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[13273.511767] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[13273.511786] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[13273.511799] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[13273.511814] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[13273.511828] [drm:intel_dump_pipe_config [i915]] [CRTC:37:pipe A][modeset]
>[13273.511841] [drm:intel_dump_pipe_config [i915]] output_types: DP (0x80)
>[13273.511854] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[13273.511867] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[13273.511879] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[13273.511890] [drm:intel_dump_pipe_config [i915]] requested mode:
>[13273.511897] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[13273.511909] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[13273.511915] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[13273.511927] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[13273.511939] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[13273.511950] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[13273.511962] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[13273.511973] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[13273.511984] [drm:intel_dump_pipe_config [i915]] dpll_hw_state: ctrl1: 0x3, cfgcr1: 0x0, cfgcr2: 0x0
>[13273.511995] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[13273.512006] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 1A] disabled, scaler_id = -1
>[13273.512017] [drm:intel_dump_pipe_config [i915]] [PLANE:31:plane 2A] disabled, scaler_id = -1
>[13273.512027] [drm:intel_dump_pipe_config [i915]] [PLANE:34:cursor A] disabled, scaler_id = -1
>[13273.512041] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[13273.512054] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[13273.512069] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:37:pipe A] has [PLANE:28:plane 1A] with fb 98
>[13273.512081] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 0 -> 1, off 0, on 1, ms 1
>[13273.512095] [drm:intel_find_shared_dpll [i915]] [CRTC:37:pipe A] allocated DPLL 1
>[13273.512108] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[13273.512116] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:47:pipe B] 00000000c85dec7a state to 0000000059ed298d
>[13273.512128] [drm:skl_compute_wm [i915]] [PLANE:28:plane 1A] ddb (0 - 0) -> (0 - 860)
>[13273.512138] [drm:skl_compute_wm [i915]] [PLANE:34:cursor A] ddb (0 - 0) -> (860 - 892)
>[13273.512144] [drm:drm_atomic_commit [drm]] committing 0000000059ed298d
>[13273.512471] [drm:intel_power_well_enable [i915]] enabling power well 2
>[13273.512491] [drm:intel_atomic_commit_tail [i915]] [ENCODER:48:DDI A]
>[13273.512504] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI B]
>[13273.512516] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[13273.512528] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[13273.512540] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DDI C]
>[13273.512551] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST A]
>[13273.512562] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST B]
>[13273.512573] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI D]
>[13273.512584] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[13273.512595] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[13273.512608] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[13273.512621] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[13273.512633] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[13273.512645] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[13273.512660] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 37
>[13273.512673] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[13273.512766] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well
>[13273.513791] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[13273.513803] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[13273.513815] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[13273.513828] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[13273.514403] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 04000000
>[13273.514414] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[13273.514425] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[13273.514992] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[13273.515004] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[13273.515877] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[13273.516199] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:61:DP-2] Link Training Passed at Link Rate = 162000, Lane count = 4
>[13273.516547] [drm:intel_enable_pipe [i915]] enabling pipe A
>[13273.516600] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS
>[13273.516602] [drm] Reducing the compressed framebuffer size. This may lead to less power savings than a non-reduced-size. Try to increase stolen memory size if available in BIOS.
>[13273.516616] [drm:intel_fbc_enable [i915]] reserved 4608000 bytes of contiguous stolen space for FBC, threshold: 2
>[13273.516629] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[13273.533372] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:61:DP-2]
>[13273.533390] [drm:intel_atomic_commit_tail [i915]] [CRTC:37:pipe A]
>[13273.533414] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[13273.533424] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000059ed298d
>[13273.533431] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000059ed298d
>[13273.533440] [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000059ed298d
>[13273.533446] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:37:pipe A] 000000002b48c403 state to 0000000059ed298d
>[13273.533451] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000ab8e9814 state to 0000000059ed298d
>[13273.533455] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 00000000ab8e9814 to [CRTC:37:pipe A]
>[13273.533460] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:99] for plane state 00000000ab8e9814
>[13273.533464] [drm:drm_atomic_check_only [drm]] checking 0000000059ed298d
>[13273.533482] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:37:pipe A] has [PLANE:28:plane 1A] with fb 99
>[13273.533498] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>[13273.533506] [drm:drm_atomic_nonblocking_commit [drm]] committing 0000000059ed298d nonblocking
>[13273.550016] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000059ed298d
>[13273.550025] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000059ed298d
>[13273.550136] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[13273.550145] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:61:DP-2]
>[13273.550153] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000006855391c
>[13273.550162] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:37:pipe A] 0000000008dd7b22 state to 000000006855391c
>[13273.550169] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 000000000505d5b6 state to 000000006855391c
>[13273.550175] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [MODE:1920x1200] for CRTC state 0000000008dd7b22
>[13273.550181] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 000000000505d5b6 to [CRTC:37:pipe A]
>[13273.550186] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:98] for plane state 000000000505d5b6
>[13273.550192] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:37:pipe A] to 000000006855391c
>[13273.550198] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:61:DP-2] 000000005c22c52e state to 000000006855391c
>[13273.550203] [drm:drm_atomic_set_crtc_for_connector [drm]] Link connector state 000000005c22c52e to [NOCRTC]
>[13273.550208] [drm:drm_atomic_set_crtc_for_connector [drm]] Link connector state 000000005c22c52e to [CRTC:37:pipe A]
>[13273.550214] [drm:drm_atomic_check_only [drm]] checking 000000006855391c
>[13273.550219] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:61:DP-2]
>[13273.550223] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:61:DP-2] keeps [ENCODER:60:DDI C], now on [CRTC:37:pipe A]
>[13273.550246] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:37:pipe A] has [PLANE:28:plane 1A] with fb 98
>[13273.550266] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>[13273.550275] [drm:drm_atomic_commit [drm]] committing 000000006855391c
>[13274.550869] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000006855391c
>[13274.550899] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000006855391c
>[13274.550960] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[13274.550985] [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000059ed298d
>[13274.551010] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:37:pipe A] 000000002b48c403 state to 0000000059ed298d
>[13274.551031] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000ab8e9814 state to 0000000059ed298d
>[13274.551051] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for CRTC state 000000002b48c403
>[13274.551069] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 00000000ab8e9814 to [NOCRTC]
>[13274.551087] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for plane state 00000000ab8e9814
>[13274.551105] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:37:pipe A] to 0000000059ed298d
>[13274.551125] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:61:DP-2] 00000000de6d4337 state to 0000000059ed298d
>[13274.551143] [drm:drm_atomic_set_crtc_for_connector [drm]] Link connector state 00000000de6d4337 to [NOCRTC]
>[13274.551161] [drm:drm_atomic_check_only [drm]] checking 0000000059ed298d
>[13274.551176] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:37:pipe A] mode changed
>[13274.551187] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:37:pipe A] enable changed
>[13274.551196] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:37:pipe A] active changed
>[13274.551206] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:61:DP-2]
>[13274.551216] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Disabling [CONNECTOR:61:DP-2]
>[13274.551226] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:37:pipe A] needs all connectors, enable: n, active: n
>[13274.551245] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:37:pipe A] to 0000000059ed298d
>[13274.551324] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[13274.551392] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[13274.551459] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:37:pipe A] has [PLANE:28:plane 1A] with fb -1
>[13274.551520] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 0, off 1, on 0, ms 1
>[13274.551550] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:47:pipe B] 00000000bd3c0152 state to 0000000059ed298d
>[13274.551600] [drm:skl_compute_wm [i915]] [PLANE:28:plane 1A] ddb (0 - 860) -> (0 - 0)
>[13274.551645] [drm:skl_compute_wm [i915]] [PLANE:34:cursor A] ddb (860 - 892) -> (0 - 0)
>[13274.551669] [drm:drm_atomic_commit [drm]] committing 0000000059ed298d
>[13274.551766] [drm:intel_disable_pipe [i915]] disabling pipe A
>[13274.567735] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well
>[13274.567805] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[13274.567869] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 37
>[13274.567925] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[13274.567996] [drm:intel_atomic_commit_tail [i915]] [ENCODER:48:DDI A]
>[13274.568051] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI B]
>[13274.568103] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[13274.568152] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[13274.568200] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DDI C]
>[13274.568249] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST A]
>[13274.568294] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST B]
>[13274.568339] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI D]
>[13274.568384] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[13274.568429] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[13274.568480] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:61:DP-2]
>[13274.568532] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[13274.568583] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[13274.568633] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[13274.568681] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[13274.568762] [drm:intel_power_well_disable [i915]] disabling power well 2
>[13274.568829] [drm:intel_atomic_commit_tail [i915]] [CRTC:37:pipe A]
>[13274.568874] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000059ed298d
>[13274.568906] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000059ed298d
>[13274.569154] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[13274.569183] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:61:DP-2]
>[13274.569209] [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000059ed298d
>[13274.569237] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:37:pipe A] 00000000c85dec7a state to 0000000059ed298d
>[13274.569261] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000c4c517e9 state to 0000000059ed298d
>[13274.569285] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [MODE:1920x1200] for CRTC state 00000000c85dec7a
>[13274.569305] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 00000000c4c517e9 to [CRTC:37:pipe A]
>[13274.569325] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:99] for plane state 00000000c4c517e9
>[13274.569344] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:37:pipe A] to 0000000059ed298d
>[13274.569364] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:61:DP-2] 000000005a636f37 state to 0000000059ed298d
>[13274.569382] [drm:drm_atomic_set_crtc_for_connector [drm]] Link connector state 000000005a636f37 to [CRTC:37:pipe A]
>[13274.569402] [drm:drm_atomic_check_only [drm]] checking 0000000059ed298d
>[13274.569418] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:37:pipe A] mode changed
>[13274.569430] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:37:pipe A] enable changed
>[13274.569440] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:37:pipe A] active changed
>[13274.569452] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:61:DP-2]
>[13274.569462] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:61:DP-2] using [ENCODER:60:DDI C] on [CRTC:37:pipe A]
>[13274.569474] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:37:pipe A] needs all connectors, enable: y, active: y
>[13274.569493] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:37:pipe A] to 0000000059ed298d
>[13274.569513] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:37:pipe A] to 0000000059ed298d
>[13274.569581] [drm:intel_atomic_check [i915]] [CONNECTOR:61:DP-2] checking for sink bpp constrains
>[13274.569642] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[13274.569708] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[13274.569781] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[13274.569836] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[13274.569896] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[13274.569955] [drm:intel_dump_pipe_config [i915]] [CRTC:37:pipe A][modeset]
>[13274.570011] [drm:intel_dump_pipe_config [i915]] output_types: DP (0x80)
>[13274.570063] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[13274.570115] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[13274.570164] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[13274.570213] [drm:intel_dump_pipe_config [i915]] requested mode:
>[13274.570241] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[13274.570292] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[13274.570318] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[13274.570372] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[13274.570421] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[13274.570469] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[13274.570517] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[13274.570564] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[13274.570611] [drm:intel_dump_pipe_config [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[13274.570657] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[13274.570703] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 1A] disabled, scaler_id = -1
>[13274.570751] [drm:intel_dump_pipe_config [i915]] [PLANE:31:plane 2A] disabled, scaler_id = -1
>[13274.570797] [drm:intel_dump_pipe_config [i915]] [PLANE:34:cursor A] disabled, scaler_id = -1
>[13274.570856] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[13274.570910] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[13274.570968] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:37:pipe A] has [PLANE:28:plane 1A] with fb 99
>[13274.571021] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 0 -> 1, off 0, on 1, ms 1
>[13274.571079] [drm:intel_find_shared_dpll [i915]] [CRTC:37:pipe A] allocated DPLL 1
>[13274.571133] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[13274.571168] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:47:pipe B] 00000000604357f6 state to 0000000059ed298d
>[13274.571217] [drm:skl_compute_wm [i915]] [PLANE:28:plane 1A] ddb (0 - 0) -> (0 - 860)
>[13274.571260] [drm:skl_compute_wm [i915]] [PLANE:34:cursor A] ddb (0 - 0) -> (860 - 892)
>[13274.571289] [drm:drm_atomic_commit [drm]] committing 0000000059ed298d
>[13275.569379] [drm:intel_power_well_enable [i915]] enabling power well 2
>[13275.569463] [drm:intel_atomic_commit_tail [i915]] [ENCODER:48:DDI A]
>[13275.569528] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI B]
>[13275.569585] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[13275.569639] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[13275.569690] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DDI C]
>[13275.569740] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST A]
>[13275.569790] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST B]
>[13275.569839] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI D]
>[13275.569888] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[13275.569936] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[13275.569992] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[13275.570049] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[13275.570104] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[13275.570156] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[13275.570219] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 37
>[13275.570276] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[13275.570417] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well
>[13275.571519] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[13275.571573] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[13275.571623] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[13275.571673] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[13275.572316] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[13275.572365] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[13275.573318] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[13275.573696] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:61:DP-2] Link Training Passed at Link Rate = 162000, Lane count = 4
>[13275.574183] [drm:intel_enable_pipe [i915]] enabling pipe A
>[13275.574285] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS
>[13275.574290] [drm] Reducing the compressed framebuffer size. This may lead to less power savings than a non-reduced-size. Try to increase stolen memory size if available in BIOS.
>[13275.574346] [drm:intel_fbc_enable [i915]] reserved 4608000 bytes of contiguous stolen space for FBC, threshold: 2
>[13275.574397] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[13275.591059] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:61:DP-2]
>[13275.591131] [drm:intel_atomic_commit_tail [i915]] [CRTC:37:pipe A]
>[13275.591211] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[13275.591249] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000059ed298d
>[13275.591275] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000059ed298d
>[13275.591335] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[13275.591359] [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000059ed298d
>[13275.591384] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:37:pipe A] 00000000bd3c0152 state to 0000000059ed298d
>[13275.591404] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 000000005906dec2 state to 0000000059ed298d
>[13275.591424] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for CRTC state 00000000bd3c0152
>[13275.591442] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 000000005906dec2 to [NOCRTC]
>[13275.591460] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for plane state 000000005906dec2
>[13275.591478] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:37:pipe A] to 0000000059ed298d
>[13275.591497] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:61:DP-2] 00000000409178cb state to 0000000059ed298d
>[13275.591515] [drm:drm_atomic_set_crtc_for_connector [drm]] Link connector state 00000000409178cb to [NOCRTC]
>[13275.591532] [drm:drm_atomic_check_only [drm]] checking 0000000059ed298d
>[13275.591547] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:37:pipe A] mode changed
>[13275.591558] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:37:pipe A] enable changed
>[13275.591568] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:37:pipe A] active changed
>[13275.591578] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:61:DP-2]
>[13275.591587] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Disabling [CONNECTOR:61:DP-2]
>[13275.591597] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:37:pipe A] needs all connectors, enable: n, active: n
>[13275.591616] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:37:pipe A] to 0000000059ed298d
>[13275.591691] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[13275.591756] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[13275.591821] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:37:pipe A] has [PLANE:28:plane 1A] with fb -1
>[13275.591881] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 0, off 1, on 0, ms 1
>[13275.591910] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:47:pipe B] 000000002b48c403 state to 0000000059ed298d
>[13275.591959] [drm:skl_compute_wm [i915]] [PLANE:28:plane 1A] ddb (0 - 860) -> (0 - 0)
>[13275.592005] [drm:skl_compute_wm [i915]] [PLANE:34:cursor A] ddb (860 - 892) -> (0 - 0)
>[13275.592028] [drm:drm_atomic_commit [drm]] committing 0000000059ed298d
>[13275.592123] [drm:intel_disable_pipe [i915]] disabling pipe A
>[13275.608053] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well
>[13275.608123] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[13275.608188] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 37
>[13275.608244] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[13275.608316] [drm:intel_atomic_commit_tail [i915]] [ENCODER:48:DDI A]
>[13275.608372] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI B]
>[13275.608426] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[13275.608477] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[13275.608526] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DDI C]
>[13275.608576] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST A]
>[13275.608624] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST B]
>[13275.608671] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI D]
>[13275.608750] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[13275.608809] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[13275.608873] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:61:DP-2]
>[13275.608936] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[13275.608995] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[13275.609050] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[13275.609103] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[13275.609157] [drm:intel_power_well_disable [i915]] disabling power well 2
>[13275.609216] [drm:intel_atomic_commit_tail [i915]] [CRTC:37:pipe A]
>[13275.609254] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000059ed298d
>[13275.609283] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000059ed298d
>[13275.609501] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[13275.609526] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:61:DP-2]
>[13275.609551] [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000059ed298d
>[13275.609578] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:37:pipe A] 00000000604357f6 state to 0000000059ed298d
>[13275.609599] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000ab8e9814 state to 0000000059ed298d
>[13275.609623] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [MODE:1920x1200] for CRTC state 00000000604357f6
>[13275.609642] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 00000000ab8e9814 to [CRTC:37:pipe A]
>[13275.609662] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:98] for plane state 00000000ab8e9814
>[13275.609679] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:37:pipe A] to 0000000059ed298d
>[13275.609700] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:61:DP-2] 00000000de6d4337 state to 0000000059ed298d
>[13275.609717] [drm:drm_atomic_set_crtc_for_connector [drm]] Link connector state 00000000de6d4337 to [CRTC:37:pipe A]
>[13275.609735] [drm:drm_atomic_check_only [drm]] checking 0000000059ed298d
>[13275.609750] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:37:pipe A] mode changed
>[13275.609762] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:37:pipe A] enable changed
>[13275.609771] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:37:pipe A] active changed
>[13275.609781] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:61:DP-2]
>[13275.609792] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:61:DP-2] using [ENCODER:60:DDI C] on [CRTC:37:pipe A]
>[13275.609803] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:37:pipe A] needs all connectors, enable: y, active: y
>[13275.609821] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:37:pipe A] to 0000000059ed298d
>[13275.609842] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:37:pipe A] to 0000000059ed298d
>[13275.609906] [drm:intel_atomic_check [i915]] [CONNECTOR:61:DP-2] checking for sink bpp constrains
>[13275.609966] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[13275.610029] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[13275.610101] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[13275.610155] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[13275.610214] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[13275.610271] [drm:intel_dump_pipe_config [i915]] [CRTC:37:pipe A][modeset]
>[13275.610326] [drm:intel_dump_pipe_config [i915]] output_types: DP (0x80)
>[13275.610378] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[13275.610430] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[13275.610478] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[13275.610526] [drm:intel_dump_pipe_config [i915]] requested mode:
>[13275.610552] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[13275.610603] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[13275.610627] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[13275.610679] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[13275.610726] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[13275.610774] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[13275.610821] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[13275.610867] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[13275.610913] [drm:intel_dump_pipe_config [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[13275.610959] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[13275.611003] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 1A] disabled, scaler_id = -1
>[13275.611049] [drm:intel_dump_pipe_config [i915]] [PLANE:31:plane 2A] disabled, scaler_id = -1
>[13275.611093] [drm:intel_dump_pipe_config [i915]] [PLANE:34:cursor A] disabled, scaler_id = -1
>[13275.611151] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[13275.611203] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[13275.611261] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:37:pipe A] has [PLANE:28:plane 1A] with fb 98
>[13275.611313] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 0 -> 1, off 0, on 1, ms 1
>[13275.611371] [drm:intel_find_shared_dpll [i915]] [CRTC:37:pipe A] allocated DPLL 1
>[13275.611424] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[13275.611457] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:47:pipe B] 00000000c85dec7a state to 0000000059ed298d
>[13275.611507] [drm:skl_compute_wm [i915]] [PLANE:28:plane 1A] ddb (0 - 0) -> (0 - 860)
>[13275.611549] [drm:skl_compute_wm [i915]] [PLANE:34:cursor A] ddb (0 - 0) -> (860 - 892)
>[13275.611575] [drm:drm_atomic_commit [drm]] committing 0000000059ed298d
>[13276.609734] [drm:intel_power_well_enable [i915]] enabling power well 2
>[13276.609817] [drm:intel_atomic_commit_tail [i915]] [ENCODER:48:DDI A]
>[13276.609881] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI B]
>[13276.609937] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[13276.609991] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[13276.610041] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DDI C]
>[13276.610091] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST A]
>[13276.610141] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST B]
>[13276.610190] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI D]
>[13276.610239] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[13276.610288] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[13276.610344] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[13276.610399] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[13276.610454] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[13276.610506] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[13276.610569] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 37
>[13276.610626] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[13276.610766] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well
>[13276.611869] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[13276.611923] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[13276.611973] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[13276.612023] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[13276.612667] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[13276.612716] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[13276.613687] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[13276.614066] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:61:DP-2] Link Training Passed at Link Rate = 162000, Lane count = 4
>[13276.614553] [drm:intel_enable_pipe [i915]] enabling pipe A
>[13276.614655] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS
>[13276.614659] [drm] Reducing the compressed framebuffer size. This may lead to less power savings than a non-reduced-size. Try to increase stolen memory size if available in BIOS.
>[13276.614716] [drm:intel_fbc_enable [i915]] reserved 4608000 bytes of contiguous stolen space for FBC, threshold: 2
>[13276.614768] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[13276.631447] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:61:DP-2]
>[13276.631520] [drm:intel_atomic_commit_tail [i915]] [CRTC:37:pipe A]
>[13276.631599] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[13276.631637] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000059ed298d
>[13276.631663] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000059ed298d
>[13276.631722] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[13276.631747] [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000059ed298d
>[13276.631771] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:37:pipe A] 000000002b48c403 state to 0000000059ed298d
>[13276.631792] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000c4c517e9 state to 0000000059ed298d
>[13276.631813] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for CRTC state 000000002b48c403
>[13276.631831] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 00000000c4c517e9 to [NOCRTC]
>[13276.631850] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for plane state 00000000c4c517e9
>[13276.631869] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:37:pipe A] to 0000000059ed298d
>[13276.631888] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:61:DP-2] 00000000d1e5643f state to 0000000059ed298d
>[13276.631906] [drm:drm_atomic_set_crtc_for_connector [drm]] Link connector state 00000000d1e5643f to [NOCRTC]
>[13276.631924] [drm:drm_atomic_check_only [drm]] checking 0000000059ed298d
>[13276.631939] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:37:pipe A] mode changed
>[13276.631950] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:37:pipe A] enable changed
>[13276.631960] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:37:pipe A] active changed
>[13276.631970] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:61:DP-2]
>[13276.631979] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Disabling [CONNECTOR:61:DP-2]
>[13276.631989] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:37:pipe A] needs all connectors, enable: n, active: n
>[13276.632008] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:37:pipe A] to 0000000059ed298d
>[13276.632082] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[13276.632147] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[13276.632213] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:37:pipe A] has [PLANE:28:plane 1A] with fb -1
>[13276.632273] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 0, off 1, on 0, ms 1
>[13276.632303] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:47:pipe B] 00000000bd3c0152 state to 0000000059ed298d
>[13276.632353] [drm:skl_compute_wm [i915]] [PLANE:28:plane 1A] ddb (0 - 860) -> (0 - 0)
>[13276.632401] [drm:skl_compute_wm [i915]] [PLANE:34:cursor A] ddb (860 - 892) -> (0 - 0)
>[13276.632425] [drm:drm_atomic_commit [drm]] committing 0000000059ed298d
>[13276.632519] [drm:intel_disable_pipe [i915]] disabling pipe A
>[13276.648458] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well
>[13276.648528] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[13276.648592] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 37
>[13276.648648] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[13276.648719] [drm:intel_atomic_commit_tail [i915]] [ENCODER:48:DDI A]
>[13276.648805] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI B]
>[13276.648867] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[13276.648926] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[13276.648980] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DDI C]
>[13276.649034] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST A]
>[13276.649081] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST B]
>[13276.649135] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI D]
>[13276.649182] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[13276.649229] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[13276.649282] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:61:DP-2]
>[13276.649336] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[13276.649387] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[13276.649439] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[13276.649488] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[13276.649539] [drm:intel_power_well_disable [i915]] disabling power well 2
>[13276.649597] [drm:intel_atomic_commit_tail [i915]] [CRTC:37:pipe A]
>[13276.649635] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000059ed298d
>[13276.649663] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000059ed298d
>[13276.649872] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[13276.649897] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:61:DP-2]
>[13276.649922] [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000059ed298d
>[13276.649948] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:37:pipe A] 00000000c85dec7a state to 0000000059ed298d
>[13276.649970] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 000000005906dec2 state to 0000000059ed298d
>[13276.649993] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [MODE:1920x1200] for CRTC state 00000000c85dec7a
>[13276.650013] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 000000005906dec2 to [CRTC:37:pipe A]
>[13276.650032] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:99] for plane state 000000005906dec2
>[13276.650049] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:37:pipe A] to 0000000059ed298d
>[13276.650070] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:61:DP-2] 00000000409178cb state to 0000000059ed298d
>[13276.650087] [drm:drm_atomic_set_crtc_for_connector [drm]] Link connector state 00000000409178cb to [CRTC:37:pipe A]
>[13276.650106] [drm:drm_atomic_check_only [drm]] checking 0000000059ed298d
>[13276.650120] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:37:pipe A] mode changed
>[13276.650132] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:37:pipe A] enable changed
>[13276.650141] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:37:pipe A] active changed
>[13276.650152] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:61:DP-2]
>[13276.650162] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:61:DP-2] using [ENCODER:60:DDI C] on [CRTC:37:pipe A]
>[13276.650173] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:37:pipe A] needs all connectors, enable: y, active: y
>[13276.650191] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:37:pipe A] to 0000000059ed298d
>[13276.650213] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:37:pipe A] to 0000000059ed298d
>[13276.650277] [drm:intel_atomic_check [i915]] [CONNECTOR:61:DP-2] checking for sink bpp constrains
>[13276.650335] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[13276.650398] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[13276.650472] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[13276.650527] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[13276.650586] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[13276.650643] [drm:intel_dump_pipe_config [i915]] [CRTC:37:pipe A][modeset]
>[13276.650698] [drm:intel_dump_pipe_config [i915]] output_types: DP (0x80)
>[13276.650750] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[13276.650801] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[13276.650850] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[13276.650898] [drm:intel_dump_pipe_config [i915]] requested mode:
>[13276.650925] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[13276.650975] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[13276.651000] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[13276.651053] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[13276.651100] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[13276.651148] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[13276.651195] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[13276.651241] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[13276.651287] [drm:intel_dump_pipe_config [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[13276.651333] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[13276.651377] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 1A] disabled, scaler_id = -1
>[13276.651423] [drm:intel_dump_pipe_config [i915]] [PLANE:31:plane 2A] disabled, scaler_id = -1
>[13276.651469] [drm:intel_dump_pipe_config [i915]] [PLANE:34:cursor A] disabled, scaler_id = -1
>[13276.651526] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[13276.651577] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[13276.651634] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:37:pipe A] has [PLANE:28:plane 1A] with fb 99
>[13276.651686] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 0 -> 1, off 0, on 1, ms 1
>[13276.651744] [drm:intel_find_shared_dpll [i915]] [CRTC:37:pipe A] allocated DPLL 1
>[13276.651797] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[13276.651830] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:47:pipe B] 00000000604357f6 state to 0000000059ed298d
>[13276.651877] [drm:skl_compute_wm [i915]] [PLANE:28:plane 1A] ddb (0 - 0) -> (0 - 860)
>[13276.651919] [drm:skl_compute_wm [i915]] [PLANE:34:cursor A] ddb (0 - 0) -> (860 - 892)
>[13276.651946] [drm:drm_atomic_commit [drm]] committing 0000000059ed298d
>[13277.650099] [drm:intel_power_well_enable [i915]] enabling power well 2
>[13277.650183] [drm:intel_atomic_commit_tail [i915]] [ENCODER:48:DDI A]
>[13277.650246] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI B]
>[13277.650303] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[13277.650356] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[13277.650408] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DDI C]
>[13277.650458] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST A]
>[13277.650508] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST B]
>[13277.650557] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI D]
>[13277.650606] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[13277.650654] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[13277.650709] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[13277.650764] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[13277.650818] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[13277.650870] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[13277.650933] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 37
>[13277.650989] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[13277.651132] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well
>[13277.652236] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[13277.652289] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[13277.652339] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[13277.652389] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[13277.653075] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 04000000
>[13277.653139] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[13277.653195] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[13277.653840] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[13277.653892] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[13277.654833] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[13277.655211] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:61:DP-2] Link Training Passed at Link Rate = 162000, Lane count = 4
>[13277.655698] [drm:intel_enable_pipe [i915]] enabling pipe A
>[13277.655801] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS
>[13277.655806] [drm] Reducing the compressed framebuffer size. This may lead to less power savings than a non-reduced-size. Try to increase stolen memory size if available in BIOS.
>[13277.655862] [drm:intel_fbc_enable [i915]] reserved 4608000 bytes of contiguous stolen space for FBC, threshold: 2
>[13277.655913] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[13277.672575] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:61:DP-2]
>[13277.672649] [drm:intel_atomic_commit_tail [i915]] [CRTC:37:pipe A]
>[13277.672728] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[13277.672796] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000059ed298d
>[13277.672831] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000059ed298d
>[13277.672898] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[13277.672925] [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000059ed298d
>[13277.672954] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:37:pipe A] 00000000bd3c0152 state to 0000000059ed298d
>[13277.672976] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000ab8e9814 state to 0000000059ed298d
>[13277.672998] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for CRTC state 00000000bd3c0152
>[13277.673020] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 00000000ab8e9814 to [NOCRTC]
>[13277.673040] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for plane state 00000000ab8e9814
>[13277.673060] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:37:pipe A] to 0000000059ed298d
>[13277.673083] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:61:DP-2] 000000005a636f37 state to 0000000059ed298d
>[13277.673103] [drm:drm_atomic_set_crtc_for_connector [drm]] Link connector state 000000005a636f37 to [NOCRTC]
>[13277.673122] [drm:drm_atomic_check_only [drm]] checking 0000000059ed298d
>[13277.673140] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:37:pipe A] mode changed
>[13277.673151] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:37:pipe A] enable changed
>[13277.673163] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:37:pipe A] active changed
>[13277.673176] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:61:DP-2]
>[13277.673186] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Disabling [CONNECTOR:61:DP-2]
>[13277.673196] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:37:pipe A] needs all connectors, enable: n, active: n
>[13277.673217] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:37:pipe A] to 0000000059ed298d
>[13277.673294] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[13277.673361] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[13277.673430] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:37:pipe A] has [PLANE:28:plane 1A] with fb -1
>[13277.673492] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 0, off 1, on 0, ms 1
>[13277.673523] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:47:pipe B] 000000002b48c403 state to 0000000059ed298d
>[13277.673575] [drm:skl_compute_wm [i915]] [PLANE:28:plane 1A] ddb (0 - 860) -> (0 - 0)
>[13277.673623] [drm:skl_compute_wm [i915]] [PLANE:34:cursor A] ddb (860 - 892) -> (0 - 0)
>[13277.673649] [drm:drm_atomic_commit [drm]] committing 0000000059ed298d
>[13277.673746] [drm:intel_disable_pipe [i915]] disabling pipe A
>[13277.691530] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well
>[13277.691600] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[13277.691663] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 37
>[13277.691719] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[13277.691790] [drm:intel_atomic_commit_tail [i915]] [ENCODER:48:DDI A]
>[13277.691845] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI B]
>[13277.691896] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[13277.691947] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[13277.691995] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DDI C]
>[13277.692045] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST A]
>[13277.692092] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST B]
>[13277.692137] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI D]
>[13277.692184] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[13277.692230] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[13277.692283] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:61:DP-2]
>[13277.692337] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[13277.692389] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[13277.692440] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[13277.692489] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[13277.692538] [drm:intel_power_well_disable [i915]] disabling power well 2
>[13277.692594] [drm:intel_atomic_commit_tail [i915]] [CRTC:37:pipe A]
>[13277.692631] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000059ed298d
>[13277.692656] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000059ed298d
>[13277.692893] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[13277.692920] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:61:DP-2]
>[13277.692946] [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000059ed298d
>[13277.692975] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:37:pipe A] 00000000604357f6 state to 0000000059ed298d
>[13277.692998] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000c4c517e9 state to 0000000059ed298d
>[13277.693022] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [MODE:1920x1200] for CRTC state 00000000604357f6
>[13277.693044] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 00000000c4c517e9 to [CRTC:37:pipe A]
>[13277.693064] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:98] for plane state 00000000c4c517e9
>[13277.693083] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:37:pipe A] to 0000000059ed298d
>[13277.693105] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:61:DP-2] 00000000d1e5643f state to 0000000059ed298d
>[13277.693122] [drm:drm_atomic_set_crtc_for_connector [drm]] Link connector state 00000000d1e5643f to [CRTC:37:pipe A]
>[13277.693143] [drm:drm_atomic_check_only [drm]] checking 0000000059ed298d
>[13277.693159] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:37:pipe A] mode changed
>[13277.693171] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:37:pipe A] enable changed
>[13277.693183] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:37:pipe A] active changed
>[13277.693194] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:61:DP-2]
>[13277.693205] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:61:DP-2] using [ENCODER:60:DDI C] on [CRTC:37:pipe A]
>[13277.693216] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:37:pipe A] needs all connectors, enable: y, active: y
>[13277.693235] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:37:pipe A] to 0000000059ed298d
>[13277.693257] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:37:pipe A] to 0000000059ed298d
>[13277.693323] [drm:intel_atomic_check [i915]] [CONNECTOR:61:DP-2] checking for sink bpp constrains
>[13277.693384] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[13277.693448] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[13277.693521] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[13277.693576] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[13277.693636] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[13277.693694] [drm:intel_dump_pipe_config [i915]] [CRTC:37:pipe A][modeset]
>[13277.693750] [drm:intel_dump_pipe_config [i915]] output_types: DP (0x80)
>[13277.693803] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[13277.693856] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[13277.693905] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[13277.693953] [drm:intel_dump_pipe_config [i915]] requested mode:
>[13277.693982] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[13277.694034] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[13277.694061] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[13277.694115] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[13277.694165] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[13277.694215] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[13277.694264] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[13277.694311] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[13277.694359] [drm:intel_dump_pipe_config [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[13277.694405] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[13277.694451] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 1A] disabled, scaler_id = -1
>[13277.694499] [drm:intel_dump_pipe_config [i915]] [PLANE:31:plane 2A] disabled, scaler_id = -1
>[13277.694545] [drm:intel_dump_pipe_config [i915]] [PLANE:34:cursor A] disabled, scaler_id = -1
>[13277.694604] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[13277.694656] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[13277.694716] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:37:pipe A] has [PLANE:28:plane 1A] with fb 98
>[13277.694770] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 0 -> 1, off 0, on 1, ms 1
>[13277.694829] [drm:intel_find_shared_dpll [i915]] [CRTC:37:pipe A] allocated DPLL 1
>[13277.694883] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[13277.694918] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:47:pipe B] 00000000c85dec7a state to 0000000059ed298d
>[13277.694967] [drm:skl_compute_wm [i915]] [PLANE:28:plane 1A] ddb (0 - 0) -> (0 - 860)
>[13277.695011] [drm:skl_compute_wm [i915]] [PLANE:34:cursor A] ddb (0 - 0) -> (860 - 892)
>[13277.695040] [drm:drm_atomic_commit [drm]] committing 0000000059ed298d
>[13278.693119] [drm:intel_power_well_enable [i915]] enabling power well 2
>[13278.693202] [drm:intel_atomic_commit_tail [i915]] [ENCODER:48:DDI A]
>[13278.693266] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI B]
>[13278.693323] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[13278.693378] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[13278.693430] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DDI C]
>[13278.693481] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST A]
>[13278.693531] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST B]
>[13278.693580] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI D]
>[13278.693628] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[13278.693676] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[13278.693732] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[13278.693789] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[13278.693843] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[13278.693895] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[13278.693957] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 37
>[13278.694014] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[13278.694154] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well
>[13278.695257] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[13278.695310] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[13278.695359] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[13278.695408] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[13278.696050] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[13278.696099] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[13278.697086] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[13278.697466] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:61:DP-2] Link Training Passed at Link Rate = 162000, Lane count = 4
>[13278.697952] [drm:intel_enable_pipe [i915]] enabling pipe A
>[13278.698055] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS
>[13278.698060] [drm] Reducing the compressed framebuffer size. This may lead to less power savings than a non-reduced-size. Try to increase stolen memory size if available in BIOS.
>[13278.698116] [drm:intel_fbc_enable [i915]] reserved 4608000 bytes of contiguous stolen space for FBC, threshold: 2
>[13278.698168] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[13278.714828] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:61:DP-2]
>[13278.714900] [drm:intel_atomic_commit_tail [i915]] [CRTC:37:pipe A]
>[13278.714979] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[13278.715016] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000059ed298d
>[13278.715043] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000059ed298d
>[13278.715101] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[13278.715126] [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000059ed298d
>[13278.715151] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:37:pipe A] 000000002b48c403 state to 0000000059ed298d
>[13278.715172] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 000000005906dec2 state to 0000000059ed298d
>[13278.715193] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for CRTC state 000000002b48c403
>[13278.715212] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 000000005906dec2 to [NOCRTC]
>[13278.715230] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for plane state 000000005906dec2
>[13278.715247] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:37:pipe A] to 0000000059ed298d
>[13278.715267] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:61:DP-2] 00000000de6d4337 state to 0000000059ed298d
>[13278.715284] [drm:drm_atomic_set_crtc_for_connector [drm]] Link connector state 00000000de6d4337 to [NOCRTC]
>[13278.715302] [drm:drm_atomic_check_only [drm]] checking 0000000059ed298d
>[13278.715317] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:37:pipe A] mode changed
>[13278.715328] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:37:pipe A] enable changed
>[13278.715337] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:37:pipe A] active changed
>[13278.715347] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:61:DP-2]
>[13278.715356] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Disabling [CONNECTOR:61:DP-2]
>[13278.715367] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:37:pipe A] needs all connectors, enable: n, active: n
>[13278.715385] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:37:pipe A] to 0000000059ed298d
>[13278.715460] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[13278.715523] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[13278.715588] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:37:pipe A] has [PLANE:28:plane 1A] with fb -1
>[13278.715648] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 0, off 1, on 0, ms 1
>[13278.715677] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:47:pipe B] 00000000bd3c0152 state to 0000000059ed298d
>[13278.715727] [drm:skl_compute_wm [i915]] [PLANE:28:plane 1A] ddb (0 - 860) -> (0 - 0)
>[13278.715773] [drm:skl_compute_wm [i915]] [PLANE:34:cursor A] ddb (860 - 892) -> (0 - 0)
>[13278.715796] [drm:drm_atomic_commit [drm]] committing 0000000059ed298d
>[13278.715891] [drm:intel_disable_pipe [i915]] disabling pipe A
>[13278.731863] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well
>[13278.731933] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[13278.731996] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 37
>[13278.732052] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[13278.732124] [drm:intel_atomic_commit_tail [i915]] [ENCODER:48:DDI A]
>[13278.732179] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI B]
>[13278.732231] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[13278.732279] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[13278.732328] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DDI C]
>[13278.732376] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST A]
>[13278.732422] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST B]
>[13278.732467] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI D]
>[13278.732512] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[13278.732557] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[13278.732609] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:61:DP-2]
>[13278.732660] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[13278.732711] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[13278.732791] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[13278.732851] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[13278.732910] [drm:intel_power_well_disable [i915]] disabling power well 2
>[13278.732972] [drm:intel_atomic_commit_tail [i915]] [CRTC:37:pipe A]
>[13278.733013] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000059ed298d
>[13278.733041] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000059ed298d
>[13278.733254] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[13278.733281] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:61:DP-2]
>[13278.733307] [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000059ed298d
>[13278.733335] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:37:pipe A] 00000000c85dec7a state to 0000000059ed298d
>[13278.733358] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000ab8e9814 state to 0000000059ed298d
>[13278.733382] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [MODE:1920x1200] for CRTC state 00000000c85dec7a
>[13278.733404] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 00000000ab8e9814 to [CRTC:37:pipe A]
>[13278.733425] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:99] for plane state 00000000ab8e9814
>[13278.733444] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:37:pipe A] to 0000000059ed298d
>[13278.733465] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:61:DP-2] 000000005a636f37 state to 0000000059ed298d
>[13278.733482] [drm:drm_atomic_set_crtc_for_connector [drm]] Link connector state 000000005a636f37 to [CRTC:37:pipe A]
>[13278.733503] [drm:drm_atomic_check_only [drm]] checking 0000000059ed298d
>[13278.733519] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:37:pipe A] mode changed
>[13278.733529] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:37:pipe A] enable changed
>[13278.733540] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:37:pipe A] active changed
>[13278.733551] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:61:DP-2]
>[13278.733562] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:61:DP-2] using [ENCODER:60:DDI C] on [CRTC:37:pipe A]
>[13278.733572] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:37:pipe A] needs all connectors, enable: y, active: y
>[13278.733593] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:37:pipe A] to 0000000059ed298d
>[13278.733614] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:37:pipe A] to 0000000059ed298d
>[13278.733680] [drm:intel_atomic_check [i915]] [CONNECTOR:61:DP-2] checking for sink bpp constrains
>[13278.733742] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[13278.733806] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[13278.733880] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[13278.733936] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[13278.733996] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[13278.734055] [drm:intel_dump_pipe_config [i915]] [CRTC:37:pipe A][modeset]
>[13278.734111] [drm:intel_dump_pipe_config [i915]] output_types: DP (0x80)
>[13278.734164] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[13278.734216] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[13278.734266] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[13278.734315] [drm:intel_dump_pipe_config [i915]] requested mode:
>[13278.734343] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[13278.734392] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[13278.734420] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[13278.734472] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[13278.734521] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[13278.734569] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[13278.734617] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[13278.734665] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[13278.734712] [drm:intel_dump_pipe_config [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[13278.734759] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[13278.734805] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 1A] disabled, scaler_id = -1
>[13278.734852] [drm:intel_dump_pipe_config [i915]] [PLANE:31:plane 2A] disabled, scaler_id = -1
>[13278.734897] [drm:intel_dump_pipe_config [i915]] [PLANE:34:cursor A] disabled, scaler_id = -1
>[13278.734956] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[13278.735010] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[13278.735069] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:37:pipe A] has [PLANE:28:plane 1A] with fb 99
>[13278.735122] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 0 -> 1, off 0, on 1, ms 1
>[13278.735181] [drm:intel_find_shared_dpll [i915]] [CRTC:37:pipe A] allocated DPLL 1
>[13278.735234] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[13278.735270] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:47:pipe B] 00000000604357f6 state to 0000000059ed298d
>[13278.735319] [drm:skl_compute_wm [i915]] [PLANE:28:plane 1A] ddb (0 - 0) -> (0 - 860)
>[13278.735363] [drm:skl_compute_wm [i915]] [PLANE:34:cursor A] ddb (0 - 0) -> (860 - 892)
>[13278.735398] [drm:drm_atomic_commit [drm]] committing 0000000059ed298d
>[13279.733483] [drm:intel_power_well_enable [i915]] enabling power well 2
>[13279.733566] [drm:intel_atomic_commit_tail [i915]] [ENCODER:48:DDI A]
>[13279.733629] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI B]
>[13279.733685] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[13279.733739] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[13279.733790] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DDI C]
>[13279.733840] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST A]
>[13279.733889] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST B]
>[13279.733938] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI D]
>[13279.733987] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[13279.734036] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[13279.734091] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[13279.734147] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[13279.734200] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[13279.734253] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[13279.734316] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 37
>[13279.734373] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[13279.734514] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well
>[13279.735616] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[13279.735670] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[13279.735720] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[13279.735770] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[13279.736414] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[13279.736461] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[13279.737400] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[13279.737777] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:61:DP-2] Link Training Passed at Link Rate = 162000, Lane count = 4
>[13279.738264] [drm:intel_enable_pipe [i915]] enabling pipe A
>[13279.738366] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS
>[13279.738371] [drm] Reducing the compressed framebuffer size. This may lead to less power savings than a non-reduced-size. Try to increase stolen memory size if available in BIOS.
>[13279.738426] [drm:intel_fbc_enable [i915]] reserved 4608000 bytes of contiguous stolen space for FBC, threshold: 2
>[13279.738476] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[13279.755156] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:61:DP-2]
>[13279.755230] [drm:intel_atomic_commit_tail [i915]] [CRTC:37:pipe A]
>[13279.755309] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[13279.755346] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000059ed298d
>[13279.755371] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000059ed298d
>[13279.755431] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[13279.755456] [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000059ed298d
>[13279.755481] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:37:pipe A] 00000000bd3c0152 state to 0000000059ed298d
>[13279.755502] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000c4c517e9 state to 0000000059ed298d
>[13279.755523] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for CRTC state 00000000bd3c0152
>[13279.755541] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 00000000c4c517e9 to [NOCRTC]
>[13279.755560] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for plane state 00000000c4c517e9
>[13279.755578] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:37:pipe A] to 0000000059ed298d
>[13279.755598] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:61:DP-2] 00000000409178cb state to 0000000059ed298d
>[13279.755616] [drm:drm_atomic_set_crtc_for_connector [drm]] Link connector state 00000000409178cb to [NOCRTC]
>[13279.755633] [drm:drm_atomic_check_only [drm]] checking 0000000059ed298d
>[13279.755649] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:37:pipe A] mode changed
>[13279.755660] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:37:pipe A] enable changed
>[13279.755669] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:37:pipe A] active changed
>[13279.755679] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:61:DP-2]
>[13279.755688] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Disabling [CONNECTOR:61:DP-2]
>[13279.755699] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:37:pipe A] needs all connectors, enable: n, active: n
>[13279.755718] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:37:pipe A] to 0000000059ed298d
>[13279.755793] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[13279.755857] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[13279.755922] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:37:pipe A] has [PLANE:28:plane 1A] with fb -1
>[13279.755981] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 0, off 1, on 0, ms 1
>[13279.756009] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:47:pipe B] 000000002b48c403 state to 0000000059ed298d
>[13279.756060] [drm:skl_compute_wm [i915]] [PLANE:28:plane 1A] ddb (0 - 860) -> (0 - 0)
>[13279.756107] [drm:skl_compute_wm [i915]] [PLANE:34:cursor A] ddb (860 - 892) -> (0 - 0)
>[13279.756129] [drm:drm_atomic_commit [drm]] committing 0000000059ed298d
>[13279.756224] [drm:intel_disable_pipe [i915]] disabling pipe A
>[13279.772205] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well
>[13279.772275] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[13279.772338] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 37
>[13279.772394] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[13279.772465] [drm:intel_atomic_commit_tail [i915]] [ENCODER:48:DDI A]
>[13279.772520] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI B]
>[13279.772572] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[13279.772622] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[13279.772671] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DDI C]
>[13279.772753] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST A]
>[13279.772810] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST B]
>[13279.772865] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI D]
>[13279.772917] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[13279.772970] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[13279.773027] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:61:DP-2]
>[13279.773084] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[13279.773137] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[13279.773193] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[13279.773242] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[13279.773295] [drm:intel_power_well_disable [i915]] disabling power well 2
>[13279.773352] [drm:intel_atomic_commit_tail [i915]] [CRTC:37:pipe A]
>[13279.773390] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000059ed298d
>[13279.773418] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000059ed298d
>[13279.773661] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[13279.773687] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:61:DP-2]
>[13279.773711] [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000059ed298d
>[13279.773737] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:37:pipe A] 00000000604357f6 state to 0000000059ed298d
>[13279.773760] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 000000005906dec2 state to 0000000059ed298d
>[13279.773782] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [MODE:1920x1200] for CRTC state 00000000604357f6
>[13279.773804] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 000000005906dec2 to [CRTC:37:pipe A]
>[13279.773822] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:98] for plane state 000000005906dec2
>[13279.773840] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:37:pipe A] to 0000000059ed298d
>[13279.773861] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:61:DP-2] 00000000de6d4337 state to 0000000059ed298d
>[13279.773877] [drm:drm_atomic_set_crtc_for_connector [drm]] Link connector state 00000000de6d4337 to [CRTC:37:pipe A]
>[13279.773897] [drm:drm_atomic_check_only [drm]] checking 0000000059ed298d
>[13279.773913] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:37:pipe A] mode changed
>[13279.773923] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:37:pipe A] enable changed
>[13279.773932] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:37:pipe A] active changed
>[13279.773944] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:61:DP-2]
>[13279.773954] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:61:DP-2] using [ENCODER:60:DDI C] on [CRTC:37:pipe A]
>[13279.773964] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:37:pipe A] needs all connectors, enable: y, active: y
>[13279.773982] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:37:pipe A] to 0000000059ed298d
>[13279.774003] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:37:pipe A] to 0000000059ed298d
>[13279.774068] [drm:intel_atomic_check [i915]] [CONNECTOR:61:DP-2] checking for sink bpp constrains
>[13279.774128] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[13279.774190] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[13279.774263] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[13279.774318] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[13279.774377] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[13279.774434] [drm:intel_dump_pipe_config [i915]] [CRTC:37:pipe A][modeset]
>[13279.774489] [drm:intel_dump_pipe_config [i915]] output_types: DP (0x80)
>[13279.774541] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[13279.774593] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[13279.774642] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[13279.774690] [drm:intel_dump_pipe_config [i915]] requested mode:
>[13279.774717] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[13279.774768] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[13279.774793] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[13279.774870] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[13279.774939] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[13279.775015] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[13279.775083] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[13279.775149] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[13279.775195] [drm:intel_dump_pipe_config [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[13279.775241] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[13279.775287] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 1A] disabled, scaler_id = -1
>[13279.775332] [drm:intel_dump_pipe_config [i915]] [PLANE:31:plane 2A] disabled, scaler_id = -1
>[13279.775377] [drm:intel_dump_pipe_config [i915]] [PLANE:34:cursor A] disabled, scaler_id = -1
>[13279.775435] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[13279.775487] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[13279.775545] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:37:pipe A] has [PLANE:28:plane 1A] with fb 98
>[13279.775596] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 0 -> 1, off 0, on 1, ms 1
>[13279.775654] [drm:intel_find_shared_dpll [i915]] [CRTC:37:pipe A] allocated DPLL 1
>[13279.775706] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[13279.775741] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:47:pipe B] 00000000c85dec7a state to 0000000059ed298d
>[13279.775789] [drm:skl_compute_wm [i915]] [PLANE:28:plane 1A] ddb (0 - 0) -> (0 - 860)
>[13279.775831] [drm:skl_compute_wm [i915]] [PLANE:34:cursor A] ddb (0 - 0) -> (860 - 892)
>[13279.775858] [drm:drm_atomic_commit [drm]] committing 0000000059ed298d
>[13280.773890] [drm:intel_power_well_enable [i915]] enabling power well 2
>[13280.773974] [drm:intel_atomic_commit_tail [i915]] [ENCODER:48:DDI A]
>[13280.774038] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI B]
>[13280.774096] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[13280.774151] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[13280.774203] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DDI C]
>[13280.774253] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST A]
>[13280.774302] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST B]
>[13280.774352] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI D]
>[13280.774400] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[13280.774448] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[13280.774503] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[13280.774560] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[13280.774613] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[13280.774666] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[13280.774728] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 37
>[13280.774785] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[13280.774925] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well
>[13280.776028] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[13280.776082] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[13280.776131] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[13280.776182] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[13280.776861] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 04000000
>[13280.776923] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[13280.776980] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[13280.777631] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[13280.777684] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[13280.778624] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[13280.779002] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:61:DP-2] Link Training Passed at Link Rate = 162000, Lane count = 4
>[13280.779489] [drm:intel_enable_pipe [i915]] enabling pipe A
>[13280.779592] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS
>[13280.779597] [drm] Reducing the compressed framebuffer size. This may lead to less power savings than a non-reduced-size. Try to increase stolen memory size if available in BIOS.
>[13280.779653] [drm:intel_fbc_enable [i915]] reserved 4608000 bytes of contiguous stolen space for FBC, threshold: 2
>[13280.779706] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[13280.796360] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:61:DP-2]
>[13280.796433] [drm:intel_atomic_commit_tail [i915]] [CRTC:37:pipe A]
>[13280.796513] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[13280.796550] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000059ed298d
>[13280.796576] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000059ed298d
>[13280.796635] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[13280.796660] [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000059ed298d
>[13280.796685] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:37:pipe A] 000000002b48c403 state to 0000000059ed298d
>[13280.796744] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000ab8e9814 state to 0000000059ed298d
>[13280.796770] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for CRTC state 000000002b48c403
>[13280.796798] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 00000000ab8e9814 to [NOCRTC]
>[13280.796822] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for plane state 00000000ab8e9814
>[13280.796846] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:37:pipe A] to 0000000059ed298d
>[13280.796871] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:61:DP-2] 000000005a636f37 state to 0000000059ed298d
>[13280.796891] [drm:drm_atomic_set_crtc_for_connector [drm]] Link connector state 000000005a636f37 to [NOCRTC]
>[13280.796911] [drm:drm_atomic_check_only [drm]] checking 0000000059ed298d
>[13280.796933] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:37:pipe A] mode changed
>[13280.796948] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:37:pipe A] enable changed
>[13280.796960] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:37:pipe A] active changed
>[13280.796974] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:61:DP-2]
>[13280.796987] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Disabling [CONNECTOR:61:DP-2]
>[13280.797000] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:37:pipe A] needs all connectors, enable: n, active: n
>[13280.797021] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:37:pipe A] to 0000000059ed298d
>[13280.797101] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[13280.797167] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[13280.797235] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:37:pipe A] has [PLANE:28:plane 1A] with fb -1
>[13280.797297] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 0, off 1, on 0, ms 1
>[13280.797328] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:47:pipe B] 00000000bd3c0152 state to 0000000059ed298d
>[13280.797380] [drm:skl_compute_wm [i915]] [PLANE:28:plane 1A] ddb (0 - 860) -> (0 - 0)
>[13280.797429] [drm:skl_compute_wm [i915]] [PLANE:34:cursor A] ddb (860 - 892) -> (0 - 0)
>[13280.797454] [drm:drm_atomic_commit [drm]] committing 0000000059ed298d
>[13280.797552] [drm:intel_disable_pipe [i915]] disabling pipe A
>[13280.815546] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well
>[13280.815616] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[13280.815679] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 37
>[13280.815757] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[13280.815828] [drm:intel_atomic_commit_tail [i915]] [ENCODER:48:DDI A]
>[13280.815883] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI B]
>[13280.815934] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[13280.815984] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[13280.816032] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DDI C]
>[13280.816081] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST A]
>[13280.816127] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST B]
>[13280.816172] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI D]
>[13280.816217] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[13280.816261] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[13280.816313] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:61:DP-2]
>[13280.816365] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[13280.816416] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[13280.816465] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[13280.816513] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[13280.816562] [drm:intel_power_well_disable [i915]] disabling power well 2
>[13280.816619] [drm:intel_atomic_commit_tail [i915]] [CRTC:37:pipe A]
>[13280.816654] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000059ed298d
>[13280.816680] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000059ed298d
>[13280.816920] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[13280.816946] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:61:DP-2]
>[13280.816972] [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000059ed298d
>[13280.817001] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:37:pipe A] 00000000c85dec7a state to 0000000059ed298d
>[13280.817023] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000c4c517e9 state to 0000000059ed298d
>[13280.817047] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [MODE:1920x1200] for CRTC state 00000000c85dec7a
>[13280.817068] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 00000000c4c517e9 to [CRTC:37:pipe A]
>[13280.817087] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:99] for plane state 00000000c4c517e9
>[13280.817106] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:37:pipe A] to 0000000059ed298d
>[13280.817127] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:61:DP-2] 00000000409178cb state to 0000000059ed298d
>[13280.817145] [drm:drm_atomic_set_crtc_for_connector [drm]] Link connector state 00000000409178cb to [CRTC:37:pipe A]
>[13280.817165] [drm:drm_atomic_check_only [drm]] checking 0000000059ed298d
>[13280.817181] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:37:pipe A] mode changed
>[13280.817193] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:37:pipe A] enable changed
>[13280.817203] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:37:pipe A] active changed
>[13280.817215] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:61:DP-2]
>[13280.817226] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:61:DP-2] using [ENCODER:60:DDI C] on [CRTC:37:pipe A]
>[13280.817237] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:37:pipe A] needs all connectors, enable: y, active: y
>[13280.817256] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:37:pipe A] to 0000000059ed298d
>[13280.817278] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:37:pipe A] to 0000000059ed298d
>[13280.817344] [drm:intel_atomic_check [i915]] [CONNECTOR:61:DP-2] checking for sink bpp constrains
>[13280.817404] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[13280.817468] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[13280.817542] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[13280.817598] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[13280.817659] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[13280.817717] [drm:intel_dump_pipe_config [i915]] [CRTC:37:pipe A][modeset]
>[13280.817773] [drm:intel_dump_pipe_config [i915]] output_types: DP (0x80)
>[13280.817826] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[13280.817879] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[13280.817928] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[13280.817977] [drm:intel_dump_pipe_config [i915]] requested mode:
>[13280.818005] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[13280.818056] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[13280.818082] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[13280.818134] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[13280.818182] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[13280.818230] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[13280.818278] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[13280.818325] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[13280.818372] [drm:intel_dump_pipe_config [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[13280.818419] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[13280.818465] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 1A] disabled, scaler_id = -1
>[13280.818513] [drm:intel_dump_pipe_config [i915]] [PLANE:31:plane 2A] disabled, scaler_id = -1
>[13280.818559] [drm:intel_dump_pipe_config [i915]] [PLANE:34:cursor A] disabled, scaler_id = -1
>[13280.818618] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[13280.818671] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[13280.818730] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:37:pipe A] has [PLANE:28:plane 1A] with fb 99
>[13280.818783] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 0 -> 1, off 0, on 1, ms 1
>[13280.818842] [drm:intel_find_shared_dpll [i915]] [CRTC:37:pipe A] allocated DPLL 1
>[13280.818896] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[13280.818931] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:47:pipe B] 00000000604357f6 state to 0000000059ed298d
>[13280.818980] [drm:skl_compute_wm [i915]] [PLANE:28:plane 1A] ddb (0 - 0) -> (0 - 860)
>[13280.819026] [drm:skl_compute_wm [i915]] [PLANE:34:cursor A] ddb (0 - 0) -> (860 - 892)
>[13280.819053] [drm:drm_atomic_commit [drm]] committing 0000000059ed298d
>[13281.817154] [drm:intel_power_well_enable [i915]] enabling power well 2
>[13281.817238] [drm:intel_atomic_commit_tail [i915]] [ENCODER:48:DDI A]
>[13281.817302] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI B]
>[13281.817358] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[13281.817412] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[13281.817463] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DDI C]
>[13281.817513] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST A]
>[13281.817561] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST B]
>[13281.817610] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI D]
>[13281.817657] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[13281.817704] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[13281.817759] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[13281.817815] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[13281.817868] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[13281.817920] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[13281.817982] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 37
>[13281.818039] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[13281.818180] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well
>[13281.819285] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[13281.819339] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[13281.819388] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[13281.819437] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[13281.820078] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 04000000
>[13281.820124] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[13281.820170] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[13281.820840] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[13281.820906] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[13281.821863] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[13281.822244] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:61:DP-2] Link Training Passed at Link Rate = 162000, Lane count = 4
>[13281.822731] [drm:intel_enable_pipe [i915]] enabling pipe A
>[13281.822831] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS
>[13281.822835] [drm] Reducing the compressed framebuffer size. This may lead to less power savings than a non-reduced-size. Try to increase stolen memory size if available in BIOS.
>[13281.822891] [drm:intel_fbc_enable [i915]] reserved 4608000 bytes of contiguous stolen space for FBC, threshold: 2
>[13281.822942] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[13281.839599] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:61:DP-2]
>[13281.839673] [drm:intel_atomic_commit_tail [i915]] [CRTC:37:pipe A]
>[13281.839775] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[13281.839813] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000059ed298d
>[13281.839839] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000059ed298d
>[13281.839897] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[13281.839922] [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000059ed298d
>[13281.839946] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:37:pipe A] 00000000bd3c0152 state to 0000000059ed298d
>[13281.839967] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 000000005906dec2 state to 0000000059ed298d
>[13281.839987] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for CRTC state 00000000bd3c0152
>[13281.840005] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 000000005906dec2 to [NOCRTC]
>[13281.840023] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for plane state 000000005906dec2
>[13281.840041] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:37:pipe A] to 0000000059ed298d
>[13281.840061] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:61:DP-2] 0000000056bf571a state to 0000000059ed298d
>[13281.840079] [drm:drm_atomic_set_crtc_for_connector [drm]] Link connector state 0000000056bf571a to [NOCRTC]
>[13281.840096] [drm:drm_atomic_check_only [drm]] checking 0000000059ed298d
>[13281.840111] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:37:pipe A] mode changed
>[13281.840122] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:37:pipe A] enable changed
>[13281.840131] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:37:pipe A] active changed
>[13281.840141] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:61:DP-2]
>[13281.840151] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Disabling [CONNECTOR:61:DP-2]
>[13281.840161] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:37:pipe A] needs all connectors, enable: n, active: n
>[13281.840180] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:37:pipe A] to 0000000059ed298d
>[13281.840255] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[13281.840319] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[13281.840383] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:37:pipe A] has [PLANE:28:plane 1A] with fb -1
>[13281.840441] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 0, off 1, on 0, ms 1
>[13281.840471] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:47:pipe B] 000000002b48c403 state to 0000000059ed298d
>[13281.840520] [drm:skl_compute_wm [i915]] [PLANE:28:plane 1A] ddb (0 - 860) -> (0 - 0)
>[13281.840566] [drm:skl_compute_wm [i915]] [PLANE:34:cursor A] ddb (860 - 892) -> (0 - 0)
>[13281.840590] [drm:drm_atomic_commit [drm]] committing 0000000059ed298d
>[13281.840680] [drm:intel_disable_pipe [i915]] disabling pipe A
>[13281.858046] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well
>[13281.858116] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[13281.858180] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 37
>[13281.858236] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[13281.858307] [drm:intel_atomic_commit_tail [i915]] [ENCODER:48:DDI A]
>[13281.858362] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI B]
>[13281.858413] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[13281.858462] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[13281.858510] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DDI C]
>[13281.858558] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST A]
>[13281.858604] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST B]
>[13281.858649] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI D]
>[13281.858695] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[13281.858740] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[13281.858792] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:61:DP-2]
>[13281.858844] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[13281.858896] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[13281.858946] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[13281.858995] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[13281.859044] [drm:intel_power_well_disable [i915]] disabling power well 2
>[13281.859101] [drm:intel_atomic_commit_tail [i915]] [CRTC:37:pipe A]
>[13281.859137] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000059ed298d
>[13281.859162] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000059ed298d
>[13281.859370] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[13281.859395] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:61:DP-2]
>[13281.859419] [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000059ed298d
>[13281.859443] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:37:pipe A] 00000000604357f6 state to 0000000059ed298d
>[13281.859465] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000ab8e9814 state to 0000000059ed298d
>[13281.859487] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [MODE:1920x1200] for CRTC state 00000000604357f6
>[13281.859507] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 00000000ab8e9814 to [CRTC:37:pipe A]
>[13281.859525] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:98] for plane state 00000000ab8e9814
>[13281.859543] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:37:pipe A] to 0000000059ed298d
>[13281.859562] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:61:DP-2] 000000005a636f37 state to 0000000059ed298d
>[13281.859578] [drm:drm_atomic_set_crtc_for_connector [drm]] Link connector state 000000005a636f37 to [CRTC:37:pipe A]
>[13281.859597] [drm:drm_atomic_check_only [drm]] checking 0000000059ed298d
>[13281.859611] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:37:pipe A] mode changed
>[13281.859622] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:37:pipe A] enable changed
>[13281.859631] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:37:pipe A] active changed
>[13281.859642] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:61:DP-2]
>[13281.859652] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:61:DP-2] using [ENCODER:60:DDI C] on [CRTC:37:pipe A]
>[13281.859662] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:37:pipe A] needs all connectors, enable: y, active: y
>[13281.859680] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:37:pipe A] to 0000000059ed298d
>[13281.859700] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:37:pipe A] to 0000000059ed298d
>[13281.859764] [drm:intel_atomic_check [i915]] [CONNECTOR:61:DP-2] checking for sink bpp constrains
>[13281.859824] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[13281.859885] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[13281.859958] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[13281.860012] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[13281.860070] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[13281.860128] [drm:intel_dump_pipe_config [i915]] [CRTC:37:pipe A][modeset]
>[13281.860181] [drm:intel_dump_pipe_config [i915]] output_types: DP (0x80)
>[13281.860233] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[13281.860285] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[13281.860333] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[13281.860380] [drm:intel_dump_pipe_config [i915]] requested mode:
>[13281.860407] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[13281.860455] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[13281.860480] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[13281.860531] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[13281.860579] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[13281.860625] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[13281.860671] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[13281.860750] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[13281.860808] [drm:intel_dump_pipe_config [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[13281.860863] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[13281.860915] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 1A] disabled, scaler_id = -1
>[13281.860966] [drm:intel_dump_pipe_config [i915]] [PLANE:31:plane 2A] disabled, scaler_id = -1
>[13281.861016] [drm:intel_dump_pipe_config [i915]] [PLANE:34:cursor A] disabled, scaler_id = -1
>[13281.861079] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[13281.861137] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[13281.861200] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:37:pipe A] has [PLANE:28:plane 1A] with fb 98
>[13281.861258] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 0 -> 1, off 0, on 1, ms 1
>[13281.861321] [drm:intel_find_shared_dpll [i915]] [CRTC:37:pipe A] allocated DPLL 1
>[13281.861378] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[13281.861417] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:47:pipe B] 00000000c85dec7a state to 0000000059ed298d
>[13281.861470] [drm:skl_compute_wm [i915]] [PLANE:28:plane 1A] ddb (0 - 0) -> (0 - 860)
>[13281.861518] [drm:skl_compute_wm [i915]] [PLANE:34:cursor A] ddb (0 - 0) -> (860 - 892)
>[13281.861549] [drm:drm_atomic_commit [drm]] committing 0000000059ed298d
>[13282.859605] [drm:intel_power_well_enable [i915]] enabling power well 2
>[13282.859688] [drm:intel_atomic_commit_tail [i915]] [ENCODER:48:DDI A]
>[13282.859754] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI B]
>[13282.859811] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[13282.859865] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[13282.859917] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DDI C]
>[13282.859967] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST A]
>[13282.860016] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST B]
>[13282.860066] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI D]
>[13282.860115] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[13282.860163] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[13282.860219] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[13282.860277] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[13282.860331] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[13282.860383] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[13282.860446] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 37
>[13282.860503] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[13282.860644] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well
>[13282.861792] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[13282.861853] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[13282.861905] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[13282.861956] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[13282.862600] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[13282.862649] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[13282.863588] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[13282.863970] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:61:DP-2] Link Training Passed at Link Rate = 162000, Lane count = 4
>[13282.864460] [drm:intel_enable_pipe [i915]] enabling pipe A
>[13282.864557] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS
>[13282.864561] [drm] Reducing the compressed framebuffer size. This may lead to less power savings than a non-reduced-size. Try to increase stolen memory size if available in BIOS.
>[13282.864618] [drm:intel_fbc_enable [i915]] reserved 4608000 bytes of contiguous stolen space for FBC, threshold: 2
>[13282.864669] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[13282.881328] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:61:DP-2]
>[13282.881400] [drm:intel_atomic_commit_tail [i915]] [CRTC:37:pipe A]
>[13282.881479] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[13282.881516] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000059ed298d
>[13282.881542] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000059ed298d
>[13282.881602] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[13282.881627] [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000059ed298d
>[13282.881652] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:37:pipe A] 000000002b48c403 state to 0000000059ed298d
>[13282.881673] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000c4c517e9 state to 0000000059ed298d
>[13282.881693] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for CRTC state 000000002b48c403
>[13282.881711] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 00000000c4c517e9 to [NOCRTC]
>[13282.881730] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for plane state 00000000c4c517e9
>[13282.881748] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:37:pipe A] to 0000000059ed298d
>[13282.881767] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:61:DP-2] 00000000d1e5643f state to 0000000059ed298d
>[13282.881785] [drm:drm_atomic_set_crtc_for_connector [drm]] Link connector state 00000000d1e5643f to [NOCRTC]
>[13282.881803] [drm:drm_atomic_check_only [drm]] checking 0000000059ed298d
>[13282.881818] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:37:pipe A] mode changed
>[13282.881829] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:37:pipe A] enable changed
>[13282.881839] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:37:pipe A] active changed
>[13282.881848] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:61:DP-2]
>[13282.881857] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Disabling [CONNECTOR:61:DP-2]
>[13282.881868] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:37:pipe A] needs all connectors, enable: n, active: n
>[13282.881887] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:37:pipe A] to 0000000059ed298d
>[13282.881962] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[13282.882026] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[13282.882091] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:37:pipe A] has [PLANE:28:plane 1A] with fb -1
>[13282.882150] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 0, off 1, on 0, ms 1
>[13282.882179] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:47:pipe B] 00000000bd3c0152 state to 0000000059ed298d
>[13282.882230] [drm:skl_compute_wm [i915]] [PLANE:28:plane 1A] ddb (0 - 860) -> (0 - 0)
>[13282.882276] [drm:skl_compute_wm [i915]] [PLANE:34:cursor A] ddb (860 - 892) -> (0 - 0)
>[13282.882301] [drm:drm_atomic_commit [drm]] committing 0000000059ed298d
>[13282.882395] [drm:intel_disable_pipe [i915]] disabling pipe A
>[13282.900653] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well
>[13282.900722] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[13282.900835] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 37
>[13282.900901] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[13282.900980] [drm:intel_atomic_commit_tail [i915]] [ENCODER:48:DDI A]
>[13282.901036] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI B]
>[13282.901091] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[13282.901142] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[13282.901193] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DDI C]
>[13282.901243] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST A]
>[13282.901292] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST B]
>[13282.901339] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI D]
>[13282.901387] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[13282.901434] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[13282.901488] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:61:DP-2]
>[13282.901543] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[13282.901598] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[13282.901650] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[13282.901701] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[13282.901752] [drm:intel_power_well_disable [i915]] disabling power well 2
>[13282.901810] [drm:intel_atomic_commit_tail [i915]] [CRTC:37:pipe A]
>[13282.901848] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000059ed298d
>[13282.901875] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000059ed298d
>[13282.902076] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[13282.902102] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:61:DP-2]
>[13282.902126] [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000059ed298d
>[13282.902153] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:37:pipe A] 00000000c85dec7a state to 0000000059ed298d
>[13282.902175] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 000000005906dec2 state to 0000000059ed298d
>[13282.902199] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [MODE:1920x1200] for CRTC state 00000000c85dec7a
>[13282.902218] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 000000005906dec2 to [CRTC:37:pipe A]
>[13282.902238] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:99] for plane state 000000005906dec2
>[13282.902256] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:37:pipe A] to 0000000059ed298d
>[13282.902276] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:61:DP-2] 0000000056bf571a state to 0000000059ed298d
>[13282.902294] [drm:drm_atomic_set_crtc_for_connector [drm]] Link connector state 0000000056bf571a to [CRTC:37:pipe A]
>[13282.902312] [drm:drm_atomic_check_only [drm]] checking 0000000059ed298d
>[13282.902327] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:37:pipe A] mode changed
>[13282.902339] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:37:pipe A] enable changed
>[13282.902348] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:37:pipe A] active changed
>[13282.902359] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:61:DP-2]
>[13282.902370] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:61:DP-2] using [ENCODER:60:DDI C] on [CRTC:37:pipe A]
>[13282.902381] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:37:pipe A] needs all connectors, enable: y, active: y
>[13282.902398] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:37:pipe A] to 0000000059ed298d
>[13282.902419] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:37:pipe A] to 0000000059ed298d
>[13282.902484] [drm:intel_atomic_check [i915]] [CONNECTOR:61:DP-2] checking for sink bpp constrains
>[13282.902544] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[13282.902607] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[13282.902678] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[13282.902732] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[13282.902790] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[13282.902847] [drm:intel_dump_pipe_config [i915]] [CRTC:37:pipe A][modeset]
>[13282.902901] [drm:intel_dump_pipe_config [i915]] output_types: DP (0x80)
>[13282.902953] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[13282.903005] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[13282.903053] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[13282.903102] [drm:intel_dump_pipe_config [i915]] requested mode:
>[13282.903129] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[13282.903178] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[13282.903203] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[13282.903256] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[13282.903304] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[13282.903351] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[13282.903399] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[13282.903445] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[13282.903490] [drm:intel_dump_pipe_config [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[13282.903536] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[13282.903580] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 1A] disabled, scaler_id = -1
>[13282.903626] [drm:intel_dump_pipe_config [i915]] [PLANE:31:plane 2A] disabled, scaler_id = -1
>[13282.903671] [drm:intel_dump_pipe_config [i915]] [PLANE:34:cursor A] disabled, scaler_id = -1
>[13282.903729] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[13282.903781] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[13282.903840] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:37:pipe A] has [PLANE:28:plane 1A] with fb 99
>[13282.903892] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 0 -> 1, off 0, on 1, ms 1
>[13282.903949] [drm:intel_find_shared_dpll [i915]] [CRTC:37:pipe A] allocated DPLL 1
>[13282.904001] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[13282.904035] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:47:pipe B] 00000000604357f6 state to 0000000059ed298d
>[13282.904083] [drm:skl_compute_wm [i915]] [PLANE:28:plane 1A] ddb (0 - 0) -> (0 - 860)
>[13282.904125] [drm:skl_compute_wm [i915]] [PLANE:34:cursor A] ddb (0 - 0) -> (860 - 892)
>[13282.904153] [drm:drm_atomic_commit [drm]] committing 0000000059ed298d
>[13283.902307] [drm:intel_power_well_enable [i915]] enabling power well 2
>[13283.902390] [drm:intel_atomic_commit_tail [i915]] [ENCODER:48:DDI A]
>[13283.902454] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI B]
>[13283.902511] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[13283.902564] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[13283.902616] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DDI C]
>[13283.902666] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST A]
>[13283.902715] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST B]
>[13283.902764] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI D]
>[13283.902813] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[13283.902862] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[13283.902917] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[13283.902974] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[13283.903028] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[13283.903081] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[13283.903145] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 37
>[13283.903201] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[13283.903342] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well
>[13283.904444] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[13283.904498] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[13283.904549] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[13283.904598] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[13283.905255] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[13283.905307] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[13283.906250] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[13283.906628] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:61:DP-2] Link Training Passed at Link Rate = 162000, Lane count = 4
>[13283.907115] [drm:intel_enable_pipe [i915]] enabling pipe A
>[13283.907218] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS
>[13283.907223] [drm] Reducing the compressed framebuffer size. This may lead to less power savings than a non-reduced-size. Try to increase stolen memory size if available in BIOS.
>[13283.907278] [drm:intel_fbc_enable [i915]] reserved 4608000 bytes of contiguous stolen space for FBC, threshold: 2
>[13283.907330] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[13283.923989] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:61:DP-2]
>[13283.924061] [drm:intel_atomic_commit_tail [i915]] [CRTC:37:pipe A]
>[13283.924140] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[13283.924178] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000059ed298d
>[13283.924203] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000059ed298d
>[13283.924262] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[13283.924287] [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000059ed298d
>[13283.924311] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:37:pipe A] 00000000bd3c0152 state to 0000000059ed298d
>[13283.924332] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000ab8e9814 state to 0000000059ed298d
>[13283.924352] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for CRTC state 00000000bd3c0152
>[13283.924370] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 00000000ab8e9814 to [NOCRTC]
>[13283.924388] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for plane state 00000000ab8e9814
>[13283.924407] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:37:pipe A] to 0000000059ed298d
>[13283.924427] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:61:DP-2] 00000000409178cb state to 0000000059ed298d
>[13283.924445] [drm:drm_atomic_set_crtc_for_connector [drm]] Link connector state 00000000409178cb to [NOCRTC]
>[13283.924462] [drm:drm_atomic_check_only [drm]] checking 0000000059ed298d
>[13283.924477] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:37:pipe A] mode changed
>[13283.924488] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:37:pipe A] enable changed
>[13283.924498] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:37:pipe A] active changed
>[13283.924508] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:61:DP-2]
>[13283.924517] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Disabling [CONNECTOR:61:DP-2]
>[13283.924527] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:37:pipe A] needs all connectors, enable: n, active: n
>[13283.924547] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:37:pipe A] to 0000000059ed298d
>[13283.924622] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[13283.924685] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[13283.924790] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:37:pipe A] has [PLANE:28:plane 1A] with fb -1
>[13283.924858] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 0, off 1, on 0, ms 1
>[13283.924896] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:47:pipe B] 000000002b48c403 state to 0000000059ed298d
>[13283.924947] [drm:skl_compute_wm [i915]] [PLANE:28:plane 1A] ddb (0 - 860) -> (0 - 0)
>[13283.924995] [drm:skl_compute_wm [i915]] [PLANE:34:cursor A] ddb (860 - 892) -> (0 - 0)
>[13283.925025] [drm:drm_atomic_commit [drm]] committing 0000000059ed298d
>[13283.925121] [drm:intel_disable_pipe [i915]] disabling pipe A
>[13283.942133] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well
>[13283.942203] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[13283.942265] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 37
>[13283.942321] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[13283.942391] [drm:intel_atomic_commit_tail [i915]] [ENCODER:48:DDI A]
>[13283.942445] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI B]
>[13283.942496] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[13283.942545] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[13283.942593] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DDI C]
>[13283.942641] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST A]
>[13283.942687] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST B]
>[13283.942732] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI D]
>[13283.942776] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[13283.942821] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[13283.942872] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:61:DP-2]
>[13283.942924] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[13283.942975] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[13283.943024] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[13283.943072] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[13283.943121] [drm:intel_power_well_disable [i915]] disabling power well 2
>[13283.943177] [drm:intel_atomic_commit_tail [i915]] [CRTC:37:pipe A]
>[13283.943213] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000059ed298d
>[13283.943239] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000059ed298d
>[13283.943450] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[13283.943475] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:61:DP-2]
>[13283.943499] [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000059ed298d
>[13283.943524] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:37:pipe A] 00000000604357f6 state to 0000000059ed298d
>[13283.943545] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000c4c517e9 state to 0000000059ed298d
>[13283.943567] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [MODE:1920x1200] for CRTC state 00000000604357f6
>[13283.943586] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 00000000c4c517e9 to [CRTC:37:pipe A]
>[13283.943604] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:98] for plane state 00000000c4c517e9
>[13283.943623] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:37:pipe A] to 0000000059ed298d
>[13283.943642] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:61:DP-2] 00000000d1e5643f state to 0000000059ed298d
>[13283.943658] [drm:drm_atomic_set_crtc_for_connector [drm]] Link connector state 00000000d1e5643f to [CRTC:37:pipe A]
>[13283.943676] [drm:drm_atomic_check_only [drm]] checking 0000000059ed298d
>[13283.943691] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:37:pipe A] mode changed
>[13283.943701] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:37:pipe A] enable changed
>[13283.943710] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:37:pipe A] active changed
>[13283.943721] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:61:DP-2]
>[13283.943731] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:61:DP-2] using [ENCODER:60:DDI C] on [CRTC:37:pipe A]
>[13283.943741] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:37:pipe A] needs all connectors, enable: y, active: y
>[13283.943759] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:37:pipe A] to 0000000059ed298d
>[13283.943778] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:37:pipe A] to 0000000059ed298d
>[13283.943842] [drm:intel_atomic_check [i915]] [CONNECTOR:61:DP-2] checking for sink bpp constrains
>[13283.943899] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[13283.943961] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[13283.944033] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[13283.944087] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[13283.944143] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[13283.944200] [drm:intel_dump_pipe_config [i915]] [CRTC:37:pipe A][modeset]
>[13283.944253] [drm:intel_dump_pipe_config [i915]] output_types: DP (0x80)
>[13283.944304] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[13283.944355] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[13283.944402] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[13283.944447] [drm:intel_dump_pipe_config [i915]] requested mode:
>[13283.944474] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[13283.944521] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[13283.944547] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[13283.944597] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[13283.944644] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[13283.944690] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[13283.944779] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[13283.944837] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[13283.944891] [drm:intel_dump_pipe_config [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[13283.944940] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[13283.944992] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 1A] disabled, scaler_id = -1
>[13283.945042] [drm:intel_dump_pipe_config [i915]] [PLANE:31:plane 2A] disabled, scaler_id = -1
>[13283.945094] [drm:intel_dump_pipe_config [i915]] [PLANE:34:cursor A] disabled, scaler_id = -1
>[13283.945155] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[13283.945212] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[13283.945274] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:37:pipe A] has [PLANE:28:plane 1A] with fb 98
>[13283.945331] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 0 -> 1, off 0, on 1, ms 1
>[13283.945393] [drm:intel_find_shared_dpll [i915]] [CRTC:37:pipe A] allocated DPLL 1
>[13283.945451] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[13283.945489] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:47:pipe B] 00000000c85dec7a state to 0000000059ed298d
>[13283.945544] [drm:skl_compute_wm [i915]] [PLANE:28:plane 1A] ddb (0 - 0) -> (0 - 860)
>[13283.945592] [drm:skl_compute_wm [i915]] [PLANE:34:cursor A] ddb (0 - 0) -> (860 - 892)
>[13283.945624] [drm:drm_atomic_commit [drm]] committing 0000000059ed298d
>[13284.943678] [drm:intel_power_well_enable [i915]] enabling power well 2
>[13284.943761] [drm:intel_atomic_commit_tail [i915]] [ENCODER:48:DDI A]
>[13284.943825] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI B]
>[13284.943883] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[13284.943937] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[13284.943990] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DDI C]
>[13284.944041] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST A]
>[13284.944091] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST B]
>[13284.944141] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI D]
>[13284.944190] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[13284.944237] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[13284.944292] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[13284.944349] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[13284.944403] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[13284.944454] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[13284.944517] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 37
>[13284.944573] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[13284.944715] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well
>[13284.945852] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[13284.945905] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[13284.945954] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[13284.946003] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[13284.946655] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 04000000
>[13284.946702] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[13284.946747] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[13284.947379] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[13284.947426] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[13284.948364] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[13284.948780] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:61:DP-2] Link Training Passed at Link Rate = 162000, Lane count = 4
>[13284.949300] [drm:intel_enable_pipe [i915]] enabling pipe A
>[13284.949391] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS
>[13284.949396] [drm] Reducing the compressed framebuffer size. This may lead to less power savings than a non-reduced-size. Try to increase stolen memory size if available in BIOS.
>[13284.949456] [drm:intel_fbc_enable [i915]] reserved 4608000 bytes of contiguous stolen space for FBC, threshold: 2
>[13284.949509] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[13284.966149] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:61:DP-2]
>[13284.966222] [drm:intel_atomic_commit_tail [i915]] [CRTC:37:pipe A]
>[13284.966302] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[13284.966340] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000059ed298d
>[13284.966365] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000059ed298d
>[13284.966423] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[13284.966448] [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000059ed298d
>[13284.966472] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:37:pipe A] 000000002b48c403 state to 0000000059ed298d
>[13284.966494] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 000000005906dec2 state to 0000000059ed298d
>[13284.966513] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for CRTC state 000000002b48c403
>[13284.966532] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 000000005906dec2 to [NOCRTC]
>[13284.966550] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for plane state 000000005906dec2
>[13284.966568] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:37:pipe A] to 0000000059ed298d
>[13284.966588] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:61:DP-2] 000000005a636f37 state to 0000000059ed298d
>[13284.966606] [drm:drm_atomic_set_crtc_for_connector [drm]] Link connector state 000000005a636f37 to [NOCRTC]
>[13284.966623] [drm:drm_atomic_check_only [drm]] checking 0000000059ed298d
>[13284.966639] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:37:pipe A] mode changed
>[13284.966649] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:37:pipe A] enable changed
>[13284.966659] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:37:pipe A] active changed
>[13284.966669] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:61:DP-2]
>[13284.966678] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Disabling [CONNECTOR:61:DP-2]
>[13284.966688] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:37:pipe A] needs all connectors, enable: n, active: n
>[13284.966707] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:37:pipe A] to 0000000059ed298d
>[13284.966782] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[13284.966847] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[13284.966913] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:37:pipe A] has [PLANE:28:plane 1A] with fb -1
>[13284.966972] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 0, off 1, on 0, ms 1
>[13284.967002] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:47:pipe B] 00000000bd3c0152 state to 0000000059ed298d
>[13284.967052] [drm:skl_compute_wm [i915]] [PLANE:28:plane 1A] ddb (0 - 860) -> (0 - 0)
>[13284.967098] [drm:skl_compute_wm [i915]] [PLANE:34:cursor A] ddb (860 - 892) -> (0 - 0)
>[13284.967122] [drm:drm_atomic_commit [drm]] committing 0000000059ed298d
>[13284.967217] [drm:intel_disable_pipe [i915]] disabling pipe A
>[13284.983556] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well
>[13284.983626] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[13284.983689] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 37
>[13284.983745] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[13284.983815] [drm:intel_atomic_commit_tail [i915]] [ENCODER:48:DDI A]
>[13284.983871] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI B]
>[13284.983922] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[13284.983973] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[13284.984021] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DDI C]
>[13284.984070] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST A]
>[13284.984116] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST B]
>[13284.984161] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI D]
>[13284.984207] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[13284.984252] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[13284.984304] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:61:DP-2]
>[13284.984356] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[13284.984406] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[13284.984456] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[13284.984505] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[13284.984553] [drm:intel_power_well_disable [i915]] disabling power well 2
>[13284.984611] [drm:intel_atomic_commit_tail [i915]] [CRTC:37:pipe A]
>[13284.984647] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000059ed298d
>[13284.984673] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000059ed298d
>[13284.984916] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[13284.984943] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:61:DP-2]
>[13284.984969] [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000059ed298d
>[13284.984997] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:37:pipe A] 00000000c85dec7a state to 0000000059ed298d
>[13284.985020] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000ab8e9814 state to 0000000059ed298d
>[13284.985044] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [MODE:1920x1200] for CRTC state 00000000c85dec7a
>[13284.985065] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 00000000ab8e9814 to [CRTC:37:pipe A]
>[13284.985086] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:99] for plane state 00000000ab8e9814
>[13284.985106] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:37:pipe A] to 0000000059ed298d
>[13284.985128] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:61:DP-2] 00000000409178cb state to 0000000059ed298d
>[13284.985146] [drm:drm_atomic_set_crtc_for_connector [drm]] Link connector state 00000000409178cb to [CRTC:37:pipe A]
>[13284.985167] [drm:drm_atomic_check_only [drm]] checking 0000000059ed298d
>[13284.985184] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:37:pipe A] mode changed
>[13284.985197] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:37:pipe A] enable changed
>[13284.985206] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:37:pipe A] active changed
>[13284.985218] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:61:DP-2]
>[13284.985232] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:61:DP-2] using [ENCODER:60:DDI C] on [CRTC:37:pipe A]
>[13284.985243] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:37:pipe A] needs all connectors, enable: y, active: y
>[13284.985261] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:37:pipe A] to 0000000059ed298d
>[13284.985283] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:37:pipe A] to 0000000059ed298d
>[13284.985351] [drm:intel_atomic_check [i915]] [CONNECTOR:61:DP-2] checking for sink bpp constrains
>[13284.985412] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[13284.985477] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[13284.985551] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[13284.985607] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[13284.985668] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[13284.985726] [drm:intel_dump_pipe_config [i915]] [CRTC:37:pipe A][modeset]
>[13284.985781] [drm:intel_dump_pipe_config [i915]] output_types: DP (0x80)
>[13284.985834] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[13284.985886] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[13284.985935] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[13284.985984] [drm:intel_dump_pipe_config [i915]] requested mode:
>[13284.986012] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[13284.986063] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[13284.986090] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[13284.986141] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[13284.986189] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[13284.986238] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[13284.986286] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[13284.986333] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[13284.986380] [drm:intel_dump_pipe_config [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[13284.986426] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[13284.986473] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 1A] disabled, scaler_id = -1
>[13284.986520] [drm:intel_dump_pipe_config [i915]] [PLANE:31:plane 2A] disabled, scaler_id = -1
>[13284.986566] [drm:intel_dump_pipe_config [i915]] [PLANE:34:cursor A] disabled, scaler_id = -1
>[13284.986625] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[13284.986678] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[13284.986737] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:37:pipe A] has [PLANE:28:plane 1A] with fb 99
>[13284.986790] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 0 -> 1, off 0, on 1, ms 1
>[13284.986849] [drm:intel_find_shared_dpll [i915]] [CRTC:37:pipe A] allocated DPLL 1
>[13284.986903] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[13284.986938] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:47:pipe B] 00000000604357f6 state to 0000000059ed298d
>[13284.986986] [drm:skl_compute_wm [i915]] [PLANE:28:plane 1A] ddb (0 - 0) -> (0 - 860)
>[13284.987028] [drm:skl_compute_wm [i915]] [PLANE:34:cursor A] ddb (0 - 0) -> (860 - 892)
>[13284.987056] [drm:drm_atomic_commit [drm]] committing 0000000059ed298d
>[13285.985152] [drm:intel_power_well_enable [i915]] enabling power well 2
>[13285.985235] [drm:intel_atomic_commit_tail [i915]] [ENCODER:48:DDI A]
>[13285.985299] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI B]
>[13285.985357] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[13285.985411] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[13285.985463] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DDI C]
>[13285.985515] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST A]
>[13285.985564] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST B]
>[13285.985613] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI D]
>[13285.985662] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[13285.985710] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[13285.985765] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[13285.985821] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[13285.985874] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[13285.985926] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[13285.985989] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 37
>[13285.986045] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[13285.986186] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well
>[13285.987286] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[13285.987339] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[13285.987389] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[13285.987438] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[13285.988082] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[13285.988131] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[13285.989086] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[13285.989466] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:61:DP-2] Link Training Passed at Link Rate = 162000, Lane count = 4
>[13285.989956] [drm:intel_enable_pipe [i915]] enabling pipe A
>[13285.990056] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS
>[13285.990060] [drm] Reducing the compressed framebuffer size. This may lead to less power savings than a non-reduced-size. Try to increase stolen memory size if available in BIOS.
>[13285.990117] [drm:intel_fbc_enable [i915]] reserved 4608000 bytes of contiguous stolen space for FBC, threshold: 2
>[13285.990169] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[13286.006828] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:61:DP-2]
>[13286.006900] [drm:intel_atomic_commit_tail [i915]] [CRTC:37:pipe A]
>[13286.006980] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[13286.007017] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000059ed298d
>[13286.007043] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000059ed298d
>[13286.007101] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[13286.007126] [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000059ed298d
>[13286.007150] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:37:pipe A] 00000000bd3c0152 state to 0000000059ed298d
>[13286.007171] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000c4c517e9 state to 0000000059ed298d
>[13286.007191] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for CRTC state 00000000bd3c0152
>[13286.007209] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 00000000c4c517e9 to [NOCRTC]
>[13286.007228] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for plane state 00000000c4c517e9
>[13286.007246] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:37:pipe A] to 0000000059ed298d
>[13286.007265] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:61:DP-2] 0000000056bf571a state to 0000000059ed298d
>[13286.007283] [drm:drm_atomic_set_crtc_for_connector [drm]] Link connector state 0000000056bf571a to [NOCRTC]
>[13286.007301] [drm:drm_atomic_check_only [drm]] checking 0000000059ed298d
>[13286.007316] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:37:pipe A] mode changed
>[13286.007327] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:37:pipe A] enable changed
>[13286.007336] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:37:pipe A] active changed
>[13286.007346] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:61:DP-2]
>[13286.007355] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Disabling [CONNECTOR:61:DP-2]
>[13286.007366] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:37:pipe A] needs all connectors, enable: n, active: n
>[13286.007385] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:37:pipe A] to 0000000059ed298d
>[13286.007459] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[13286.007523] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[13286.007589] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:37:pipe A] has [PLANE:28:plane 1A] with fb -1
>[13286.007649] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 0, off 1, on 0, ms 1
>[13286.007679] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:47:pipe B] 000000002b48c403 state to 0000000059ed298d
>[13286.007728] [drm:skl_compute_wm [i915]] [PLANE:28:plane 1A] ddb (0 - 860) -> (0 - 0)
>[13286.007774] [drm:skl_compute_wm [i915]] [PLANE:34:cursor A] ddb (860 - 892) -> (0 - 0)
>[13286.007797] [drm:drm_atomic_commit [drm]] committing 0000000059ed298d
>[13286.007891] [drm:intel_disable_pipe [i915]] disabling pipe A
>[13286.023868] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well
>[13286.023938] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[13286.024002] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 37
>[13286.024059] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[13286.024131] [drm:intel_atomic_commit_tail [i915]] [ENCODER:48:DDI A]
>[13286.024186] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI B]
>[13286.024237] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[13286.024287] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[13286.024336] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DDI C]
>[13286.024385] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST A]
>[13286.024432] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST B]
>[13286.024478] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI D]
>[13286.024524] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[13286.024569] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[13286.024621] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:61:DP-2]
>[13286.024675] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[13286.024758] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[13286.024818] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[13286.024877] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[13286.024936] [drm:intel_power_well_disable [i915]] disabling power well 2
>[13286.025001] [drm:intel_atomic_commit_tail [i915]] [CRTC:37:pipe A]
>[13286.025046] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000059ed298d
>[13286.025076] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000059ed298d
>[13286.025292] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[13286.025320] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:61:DP-2]
>[13286.025346] [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000059ed298d
>[13286.025373] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:37:pipe A] 00000000604357f6 state to 0000000059ed298d
>[13286.025396] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 000000005906dec2 state to 0000000059ed298d
>[13286.025422] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [MODE:1920x1200] for CRTC state 00000000604357f6
>[13286.025443] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 000000005906dec2 to [CRTC:37:pipe A]
>[13286.025464] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:98] for plane state 000000005906dec2
>[13286.025483] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:37:pipe A] to 0000000059ed298d
>[13286.025506] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:61:DP-2] 000000005a636f37 state to 0000000059ed298d
>[13286.025524] [drm:drm_atomic_set_crtc_for_connector [drm]] Link connector state 000000005a636f37 to [CRTC:37:pipe A]
>[13286.025544] [drm:drm_atomic_check_only [drm]] checking 0000000059ed298d
>[13286.025559] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:37:pipe A] mode changed
>[13286.025572] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:37:pipe A] enable changed
>[13286.025581] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:37:pipe A] active changed
>[13286.025592] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:61:DP-2]
>[13286.025604] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:61:DP-2] using [ENCODER:60:DDI C] on [CRTC:37:pipe A]
>[13286.025614] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:37:pipe A] needs all connectors, enable: y, active: y
>[13286.025634] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:37:pipe A] to 0000000059ed298d
>[13286.025656] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:37:pipe A] to 0000000059ed298d
>[13286.025723] [drm:intel_atomic_check [i915]] [CONNECTOR:61:DP-2] checking for sink bpp constrains
>[13286.025784] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[13286.025848] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[13286.025923] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[13286.025979] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[13286.026039] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[13286.026097] [drm:intel_dump_pipe_config [i915]] [CRTC:37:pipe A][modeset]
>[13286.026154] [drm:intel_dump_pipe_config [i915]] output_types: DP (0x80)
>[13286.026208] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[13286.026262] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[13286.026311] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[13286.026360] [drm:intel_dump_pipe_config [i915]] requested mode:
>[13286.026388] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[13286.026439] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[13286.026465] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[13286.026519] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[13286.026568] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[13286.026617] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[13286.026665] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[13286.026713] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[13286.026760] [drm:intel_dump_pipe_config [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[13286.026807] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[13286.026853] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 1A] disabled, scaler_id = -1
>[13286.026901] [drm:intel_dump_pipe_config [i915]] [PLANE:31:plane 2A] disabled, scaler_id = -1
>[13286.026947] [drm:intel_dump_pipe_config [i915]] [PLANE:34:cursor A] disabled, scaler_id = -1
>[13286.027006] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[13286.027059] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[13286.027118] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:37:pipe A] has [PLANE:28:plane 1A] with fb 98
>[13286.027170] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 0 -> 1, off 0, on 1, ms 1
>[13286.027229] [drm:intel_find_shared_dpll [i915]] [CRTC:37:pipe A] allocated DPLL 1
>[13286.027282] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[13286.027317] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:47:pipe B] 00000000c85dec7a state to 0000000059ed298d
>[13286.027366] [drm:skl_compute_wm [i915]] [PLANE:28:plane 1A] ddb (0 - 0) -> (0 - 860)
>[13286.027409] [drm:skl_compute_wm [i915]] [PLANE:34:cursor A] ddb (0 - 0) -> (860 - 892)
>[13286.027437] [drm:drm_atomic_commit [drm]] committing 0000000059ed298d
>[13287.025523] [drm:intel_power_well_enable [i915]] enabling power well 2
>[13287.025606] [drm:intel_atomic_commit_tail [i915]] [ENCODER:48:DDI A]
>[13287.025669] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI B]
>[13287.025728] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[13287.025782] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[13287.025834] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DDI C]
>[13287.025885] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST A]
>[13287.025935] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST B]
>[13287.025984] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI D]
>[13287.026033] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[13287.026082] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[13287.026137] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[13287.026194] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[13287.026248] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[13287.026300] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[13287.026363] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 37
>[13287.026419] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[13287.026560] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well
>[13287.027664] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[13287.027718] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[13287.027767] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[13287.027816] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[13287.028459] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[13287.028508] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[13287.029493] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[13287.029872] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:61:DP-2] Link Training Passed at Link Rate = 162000, Lane count = 4
>[13287.030359] [drm:intel_enable_pipe [i915]] enabling pipe A
>[13287.030461] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS
>[13287.030466] [drm] Reducing the compressed framebuffer size. This may lead to less power savings than a non-reduced-size. Try to increase stolen memory size if available in BIOS.
>[13287.030522] [drm:intel_fbc_enable [i915]] reserved 4608000 bytes of contiguous stolen space for FBC, threshold: 2
>[13287.030574] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[13287.047229] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:61:DP-2]
>[13287.047302] [drm:intel_atomic_commit_tail [i915]] [CRTC:37:pipe A]
>[13287.047381] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[13287.047419] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000059ed298d
>[13287.047445] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000059ed298d
>[13287.047504] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[13287.047529] [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000059ed298d
>[13287.047554] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:37:pipe A] 000000002b48c403 state to 0000000059ed298d
>[13287.047575] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000ab8e9814 state to 0000000059ed298d
>[13287.047595] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for CRTC state 000000002b48c403
>[13287.047613] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 00000000ab8e9814 to [NOCRTC]
>[13287.047631] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for plane state 00000000ab8e9814
>[13287.047650] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:37:pipe A] to 0000000059ed298d
>[13287.047670] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:61:DP-2] 00000000d1e5643f state to 0000000059ed298d
>[13287.047688] [drm:drm_atomic_set_crtc_for_connector [drm]] Link connector state 00000000d1e5643f to [NOCRTC]
>[13287.047705] [drm:drm_atomic_check_only [drm]] checking 0000000059ed298d
>[13287.047720] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:37:pipe A] mode changed
>[13287.047731] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:37:pipe A] enable changed
>[13287.047741] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:37:pipe A] active changed
>[13287.047751] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:61:DP-2]
>[13287.047760] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Disabling [CONNECTOR:61:DP-2]
>[13287.047770] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:37:pipe A] needs all connectors, enable: n, active: n
>[13287.047789] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:37:pipe A] to 0000000059ed298d
>[13287.047864] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[13287.047928] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[13287.047992] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:37:pipe A] has [PLANE:28:plane 1A] with fb -1
>[13287.048050] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 0, off 1, on 0, ms 1
>[13287.048078] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:47:pipe B] 00000000bd3c0152 state to 0000000059ed298d
>[13287.048129] [drm:skl_compute_wm [i915]] [PLANE:28:plane 1A] ddb (0 - 860) -> (0 - 0)
>[13287.048175] [drm:skl_compute_wm [i915]] [PLANE:34:cursor A] ddb (860 - 892) -> (0 - 0)
>[13287.048199] [drm:drm_atomic_commit [drm]] committing 0000000059ed298d
>[13287.048293] [drm:intel_disable_pipe [i915]] disabling pipe A
>[13287.064280] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well
>[13287.064351] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[13287.064414] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 37
>[13287.064469] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[13287.064540] [drm:intel_atomic_commit_tail [i915]] [ENCODER:48:DDI A]
>[13287.064596] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI B]
>[13287.064647] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[13287.064697] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[13287.064782] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DDI C]
>[13287.064841] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST A]
>[13287.064897] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST B]
>[13287.064949] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI D]
>[13287.065001] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[13287.065053] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[13287.065112] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:61:DP-2]
>[13287.065171] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[13287.065224] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[13287.065277] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[13287.065328] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[13287.065379] [drm:intel_power_well_disable [i915]] disabling power well 2
>[13287.065437] [drm:intel_atomic_commit_tail [i915]] [CRTC:37:pipe A]
>[13287.065475] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000059ed298d
>[13287.065502] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000059ed298d
>[13287.065713] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[13287.065739] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:61:DP-2]
>[13287.065764] [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000059ed298d
>[13287.065790] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:37:pipe A] 00000000c85dec7a state to 0000000059ed298d
>[13287.065812] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000c4c517e9 state to 0000000059ed298d
>[13287.065835] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [MODE:1920x1200] for CRTC state 00000000c85dec7a
>[13287.065854] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 00000000c4c517e9 to [CRTC:37:pipe A]
>[13287.065874] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:99] for plane state 00000000c4c517e9
>[13287.065893] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:37:pipe A] to 0000000059ed298d
>[13287.065914] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:61:DP-2] 0000000056bf571a state to 0000000059ed298d
>[13287.065930] [drm:drm_atomic_set_crtc_for_connector [drm]] Link connector state 0000000056bf571a to [CRTC:37:pipe A]
>[13287.065950] [drm:drm_atomic_check_only [drm]] checking 0000000059ed298d
>[13287.065964] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:37:pipe A] mode changed
>[13287.065976] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:37:pipe A] enable changed
>[13287.065985] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:37:pipe A] active changed
>[13287.065996] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:61:DP-2]
>[13287.066007] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:61:DP-2] using [ENCODER:60:DDI C] on [CRTC:37:pipe A]
>[13287.066017] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:37:pipe A] needs all connectors, enable: y, active: y
>[13287.066035] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:37:pipe A] to 0000000059ed298d
>[13287.066056] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:37:pipe A] to 0000000059ed298d
>[13287.066120] [drm:intel_atomic_check [i915]] [CONNECTOR:61:DP-2] checking for sink bpp constrains
>[13287.066180] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[13287.066242] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[13287.066314] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[13287.066368] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[13287.066427] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[13287.066484] [drm:intel_dump_pipe_config [i915]] [CRTC:37:pipe A][modeset]
>[13287.066539] [drm:intel_dump_pipe_config [i915]] output_types: DP (0x80)
>[13287.066590] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[13287.066642] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[13287.066690] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[13287.066738] [drm:intel_dump_pipe_config [i915]] requested mode:
>[13287.066765] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[13287.066816] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[13287.066841] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[13287.066894] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[13287.066942] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[13287.066990] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[13287.067038] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[13287.067085] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[13287.067130] [drm:intel_dump_pipe_config [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[13287.067176] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[13287.067222] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 1A] disabled, scaler_id = -1
>[13287.067268] [drm:intel_dump_pipe_config [i915]] [PLANE:31:plane 2A] disabled, scaler_id = -1
>[13287.067313] [drm:intel_dump_pipe_config [i915]] [PLANE:34:cursor A] disabled, scaler_id = -1
>[13287.067370] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[13287.067422] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[13287.067479] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:37:pipe A] has [PLANE:28:plane 1A] with fb 99
>[13287.067530] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 0 -> 1, off 0, on 1, ms 1
>[13287.067588] [drm:intel_find_shared_dpll [i915]] [CRTC:37:pipe A] allocated DPLL 1
>[13287.067641] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[13287.067675] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:47:pipe B] 00000000604357f6 state to 0000000059ed298d
>[13287.067722] [drm:skl_compute_wm [i915]] [PLANE:28:plane 1A] ddb (0 - 0) -> (0 - 860)
>[13287.067764] [drm:skl_compute_wm [i915]] [PLANE:34:cursor A] ddb (0 - 0) -> (860 - 892)
>[13287.067791] [drm:drm_atomic_commit [drm]] committing 0000000059ed298d
>[13288.065955] [drm:intel_power_well_enable [i915]] enabling power well 2
>[13288.066037] [drm:intel_atomic_commit_tail [i915]] [ENCODER:48:DDI A]
>[13288.066101] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI B]
>[13288.066158] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[13288.066213] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[13288.066267] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DDI C]
>[13288.066318] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST A]
>[13288.066369] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST B]
>[13288.066420] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI D]
>[13288.066469] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[13288.066518] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[13288.066573] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[13288.066630] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[13288.066684] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[13288.066736] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[13288.066799] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 37
>[13288.066856] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[13288.066999] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well
>[13288.068103] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[13288.068157] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[13288.068207] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[13288.068256] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[13288.068942] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 04000000
>[13288.068992] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[13288.069040] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[13288.069674] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[13288.069721] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[13288.070658] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[13288.071035] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:61:DP-2] Link Training Passed at Link Rate = 162000, Lane count = 4
>[13288.071521] [drm:intel_enable_pipe [i915]] enabling pipe A
>[13288.071625] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS
>[13288.071630] [drm] Reducing the compressed framebuffer size. This may lead to less power savings than a non-reduced-size. Try to increase stolen memory size if available in BIOS.
>[13288.071686] [drm:intel_fbc_enable [i915]] reserved 4608000 bytes of contiguous stolen space for FBC, threshold: 2
>[13288.071737] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[13288.088394] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:61:DP-2]
>[13288.088467] [drm:intel_atomic_commit_tail [i915]] [CRTC:37:pipe A]
>[13288.088546] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[13288.088583] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000059ed298d
>[13288.088608] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000059ed298d
>[13288.088667] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[13288.088725] [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000059ed298d
>[13288.088753] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:37:pipe A] 00000000bd3c0152 state to 0000000059ed298d
>[13288.088780] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 000000005906dec2 state to 0000000059ed298d
>[13288.088810] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for CRTC state 00000000bd3c0152
>[13288.088834] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 000000005906dec2 to [NOCRTC]
>[13288.088859] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for plane state 000000005906dec2
>[13288.088882] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:37:pipe A] to 0000000059ed298d
>[13288.088904] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:61:DP-2] 000000005a636f37 state to 0000000059ed298d
>[13288.088927] [drm:drm_atomic_set_crtc_for_connector [drm]] Link connector state 000000005a636f37 to [NOCRTC]
>[13288.088948] [drm:drm_atomic_check_only [drm]] checking 0000000059ed298d
>[13288.088966] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:37:pipe A] mode changed
>[13288.088977] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:37:pipe A] enable changed
>[13288.088988] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:37:pipe A] active changed
>[13288.088999] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:61:DP-2]
>[13288.089009] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Disabling [CONNECTOR:61:DP-2]
>[13288.089020] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:37:pipe A] needs all connectors, enable: n, active: n
>[13288.089041] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:37:pipe A] to 0000000059ed298d
>[13288.089117] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[13288.089183] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[13288.089251] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:37:pipe A] has [PLANE:28:plane 1A] with fb -1
>[13288.089312] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 0, off 1, on 0, ms 1
>[13288.089343] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:47:pipe B] 000000002b48c403 state to 0000000059ed298d
>[13288.089394] [drm:skl_compute_wm [i915]] [PLANE:28:plane 1A] ddb (0 - 860) -> (0 - 0)
>[13288.089443] [drm:skl_compute_wm [i915]] [PLANE:34:cursor A] ddb (860 - 892) -> (0 - 0)
>[13288.089469] [drm:drm_atomic_commit [drm]] committing 0000000059ed298d
>[13288.089566] [drm:intel_disable_pipe [i915]] disabling pipe A
>[13288.107542] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well
>[13288.107613] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[13288.107676] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 37
>[13288.107733] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[13288.107805] [drm:intel_atomic_commit_tail [i915]] [ENCODER:48:DDI A]
>[13288.107860] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI B]
>[13288.107913] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[13288.107964] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[13288.108012] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DDI C]
>[13288.108062] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST A]
>[13288.108109] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST B]
>[13288.108156] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI D]
>[13288.108202] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[13288.108248] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[13288.108301] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:61:DP-2]
>[13288.108354] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[13288.108405] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[13288.108456] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[13288.108504] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[13288.108554] [drm:intel_power_well_disable [i915]] disabling power well 2
>[13288.108611] [drm:intel_atomic_commit_tail [i915]] [CRTC:37:pipe A]
>[13288.108646] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000059ed298d
>[13288.108673] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000059ed298d
>[13288.108962] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[13288.108990] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:61:DP-2]
>[13288.109016] [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000059ed298d
>[13288.109044] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:37:pipe A] 00000000604357f6 state to 0000000059ed298d
>[13288.109068] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000ab8e9814 state to 0000000059ed298d
>[13288.109092] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [MODE:1920x1200] for CRTC state 00000000604357f6
>[13288.109112] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 00000000ab8e9814 to [CRTC:37:pipe A]
>[13288.109132] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:98] for plane state 00000000ab8e9814
>[13288.109151] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:37:pipe A] to 0000000059ed298d
>[13288.109173] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:61:DP-2] 00000000d1e5643f state to 0000000059ed298d
>[13288.109191] [drm:drm_atomic_set_crtc_for_connector [drm]] Link connector state 00000000d1e5643f to [CRTC:37:pipe A]
>[13288.109212] [drm:drm_atomic_check_only [drm]] checking 0000000059ed298d
>[13288.109229] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:37:pipe A] mode changed
>[13288.109242] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:37:pipe A] enable changed
>[13288.109251] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:37:pipe A] active changed
>[13288.109264] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:61:DP-2]
>[13288.109275] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:61:DP-2] using [ENCODER:60:DDI C] on [CRTC:37:pipe A]
>[13288.109286] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:37:pipe A] needs all connectors, enable: y, active: y
>[13288.109304] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:37:pipe A] to 0000000059ed298d
>[13288.109326] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:37:pipe A] to 0000000059ed298d
>[13288.109393] [drm:intel_atomic_check [i915]] [CONNECTOR:61:DP-2] checking for sink bpp constrains
>[13288.109454] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[13288.109517] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[13288.109591] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[13288.109646] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[13288.109705] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[13288.109763] [drm:intel_dump_pipe_config [i915]] [CRTC:37:pipe A][modeset]
>[13288.109819] [drm:intel_dump_pipe_config [i915]] output_types: DP (0x80)
>[13288.109871] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 24, dithering: 0
>[13288.109923] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[13288.109973] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[13288.110022] [drm:intel_dump_pipe_config [i915]] requested mode:
>[13288.110050] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[13288.110102] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[13288.110128] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[13288.110182] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[13288.110232] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[13288.110281] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[13288.110329] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[13288.110378] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[13288.110425] [drm:intel_dump_pipe_config [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[13288.110472] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[13288.110518] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 1A] disabled, scaler_id = -1
>[13288.110566] [drm:intel_dump_pipe_config [i915]] [PLANE:31:plane 2A] disabled, scaler_id = -1
>[13288.110612] [drm:intel_dump_pipe_config [i915]] [PLANE:34:cursor A] disabled, scaler_id = -1
>[13288.110672] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[13288.110725] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[13288.110786] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:37:pipe A] has [PLANE:28:plane 1A] with fb 98
>[13288.110840] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 0 -> 1, off 0, on 1, ms 1
>[13288.110899] [drm:intel_find_shared_dpll [i915]] [CRTC:37:pipe A] allocated DPLL 1
>[13288.110952] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[13288.110987] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:47:pipe B] 00000000c85dec7a state to 0000000059ed298d
>[13288.111037] [drm:skl_compute_wm [i915]] [PLANE:28:plane 1A] ddb (0 - 0) -> (0 - 860)
>[13288.111081] [drm:skl_compute_wm [i915]] [PLANE:34:cursor A] ddb (0 - 0) -> (860 - 892)
>[13288.111108] [drm:drm_atomic_commit [drm]] committing 0000000059ed298d
>[13289.109195] [drm:intel_power_well_enable [i915]] enabling power well 2
>[13289.109277] [drm:intel_atomic_commit_tail [i915]] [ENCODER:48:DDI A]
>[13289.109340] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI B]
>[13289.109397] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[13289.109451] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[13289.109502] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DDI C]
>[13289.109553] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST A]
>[13289.109603] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST B]
>[13289.109653] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI D]
>[13289.109702] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[13289.109750] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[13289.109806] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[13289.109863] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[13289.109917] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[13289.109970] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[13289.110033] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 37
>[13289.110090] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[13289.110232] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well
>[13289.111336] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[13289.111389] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[13289.111439] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[13289.111489] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[13289.112130] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 04000000
>[13289.112177] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[13289.112223] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[13289.112889] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[13289.112957] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[13289.113905] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[13289.114287] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:61:DP-2] Link Training Passed at Link Rate = 162000, Lane count = 4
>[13289.114776] [drm:intel_enable_pipe [i915]] enabling pipe A
>[13289.114875] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS
>[13289.114880] [drm] Reducing the compressed framebuffer size. This may lead to less power savings than a non-reduced-size. Try to increase stolen memory size if available in BIOS.
>[13289.114936] [drm:intel_fbc_enable [i915]] reserved 4608000 bytes of contiguous stolen space for FBC, threshold: 2
>[13289.114987] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[13289.131636] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:61:DP-2]
>[13289.131709] [drm:intel_atomic_commit_tail [i915]] [CRTC:37:pipe A]
>[13289.131789] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[13289.131827] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000059ed298d
>[13289.131853] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000059ed298d
>[13289.131912] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[13289.131938] [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000059ed298d
>[13289.131963] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:37:pipe A] 000000002b48c403 state to 0000000059ed298d
>[13289.131984] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000c4c517e9 state to 0000000059ed298d
>[13289.132005] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for CRTC state 000000002b48c403
>[13289.132023] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 00000000c4c517e9 to [NOCRTC]
>[13289.132042] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for plane state 00000000c4c517e9
>[13289.132061] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:37:pipe A] to 0000000059ed298d
>[13289.132080] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:61:DP-2] 00000000de6d4337 state to 0000000059ed298d
>[13289.132099] [drm:drm_atomic_set_crtc_for_connector [drm]] Link connector state 00000000de6d4337 to [NOCRTC]
>[13289.132116] [drm:drm_atomic_check_only [drm]] checking 0000000059ed298d
>[13289.132132] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:37:pipe A] mode changed
>[13289.132143] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:37:pipe A] enable changed
>[13289.132153] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:37:pipe A] active changed
>[13289.132162] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:61:DP-2]
>[13289.132172] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Disabling [CONNECTOR:61:DP-2]
>[13289.132182] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:37:pipe A] needs all connectors, enable: n, active: n
>[13289.132201] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:37:pipe A] to 0000000059ed298d
>[13289.132275] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[13289.132339] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[13289.132404] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:37:pipe A] has [PLANE:28:plane 1A] with fb -1
>[13289.132462] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 0, off 1, on 0, ms 1
>[13289.132491] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:47:pipe B] 00000000bd3c0152 state to 0000000059ed298d
>[13289.132540] [drm:skl_compute_wm [i915]] [PLANE:28:plane 1A] ddb (0 - 860) -> (0 - 0)
>[13289.132586] [drm:skl_compute_wm [i915]] [PLANE:34:cursor A] ddb (860 - 892) -> (0 - 0)
>[13289.132610] [drm:drm_atomic_commit [drm]] committing 0000000059ed298d
>[13289.132704] [drm:intel_disable_pipe [i915]] disabling pipe A
>[13289.148928] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well
>[13289.148998] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[13289.149062] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 37
>[13289.149120] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[13289.149192] [drm:intel_atomic_commit_tail [i915]] [ENCODER:48:DDI A]
>[13289.149248] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI B]
>[13289.149300] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[13289.149351] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[13289.149400] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DDI C]
>[13289.149449] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST A]
>[13289.149496] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST B]
>[13289.149541] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI D]
>[13289.149587] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[13289.149633] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[13289.149685] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:61:DP-2]
>[13289.149737] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[13289.149789] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[13289.149839] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[13289.149888] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[13289.149936] [drm:intel_power_well_disable [i915]] disabling power well 2
>[13289.149993] [drm:intel_atomic_commit_tail [i915]] [CRTC:37:pipe A]
>[13289.150029] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000059ed298d
>[13289.150055] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000059ed298d
>[13289.150197] [drm:drm_mode_addfb2 [drm]] [FB:98]
>[13289.150233] [drm:drm_mode_addfb2 [drm]] [FB:99]
>[13289.166805] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[13289.166813] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000a6ac6587
>[13289.166819] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:37:pipe A] 00000000c85dec7a state to 00000000a6ac6587
>[13289.166824] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000ab8e9814 state to 00000000a6ac6587
>[13289.166828] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for CRTC state 00000000c85dec7a
>[13289.166832] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 00000000ab8e9814 to [NOCRTC]
>[13289.166836] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for plane state 00000000ab8e9814
>[13289.166839] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:37:pipe A] to 00000000a6ac6587
>[13289.166844] [drm:drm_atomic_check_only [drm]] checking 00000000a6ac6587
>[13289.166850] [drm:drm_atomic_commit [drm]] committing 00000000a6ac6587
>[13289.166862] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000a6ac6587
>[13289.166866] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000a6ac6587
>[13289.166871] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[13289.166875] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000a6ac6587
>[13289.166879] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:47:pipe B] 000000002b48c403 state to 00000000a6ac6587
>[13289.166883] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:38:plane 1B] 00000000c4c517e9 state to 00000000a6ac6587
>[13289.166886] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for CRTC state 000000002b48c403
>[13289.166889] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 00000000c4c517e9 to [NOCRTC]
>[13289.166893] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for plane state 00000000c4c517e9
>[13289.166896] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:47:pipe B] to 00000000a6ac6587
>[13289.166899] [drm:drm_atomic_check_only [drm]] checking 00000000a6ac6587
>[13289.166903] [drm:drm_atomic_commit [drm]] committing 00000000a6ac6587
>[13289.166910] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000a6ac6587
>[13289.166913] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000a6ac6587
>[13289.166918] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[13289.166923] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:61:DP-2]
>[13289.166927] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000a6ac6587
>[13289.166931] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:47:pipe B] 00000000bd3c0152 state to 00000000a6ac6587
>[13289.166934] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:38:plane 1B] 000000005906dec2 state to 00000000a6ac6587
>[13289.166938] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [MODE:1920x1200] for CRTC state 00000000bd3c0152
>[13289.166941] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 000000005906dec2 to [CRTC:47:pipe B]
>[13289.166945] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:98] for plane state 000000005906dec2
>[13289.166948] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:47:pipe B] to 00000000a6ac6587
>[13289.166952] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:61:DP-2] 000000005a636f37 state to 00000000a6ac6587
>[13289.166955] [drm:drm_atomic_set_crtc_for_connector [drm]] Link connector state 000000005a636f37 to [CRTC:47:pipe B]
>[13289.166960] [drm:drm_atomic_check_only [drm]] checking 00000000a6ac6587
>[13289.166964] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:47:pipe B] mode changed
>[13289.166966] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:47:pipe B] enable changed
>[13289.166968] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:47:pipe B] active changed
>[13289.166970] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:61:DP-2]
>[13289.166972] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:61:DP-2] using [ENCODER:60:DDI C] on [CRTC:47:pipe B]
>[13289.166974] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:47:pipe B] needs all connectors, enable: y, active: y
>[13289.166978] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:47:pipe B] to 00000000a6ac6587
>[13289.166983] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:47:pipe B] to 00000000a6ac6587
>[13289.167000] [drm:intel_atomic_check [i915]] [CONNECTOR:61:DP-2] checking for sink bpp constrains
>[13289.167013] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[13289.167027] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[13289.167043] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[13289.167054] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[13289.167067] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[13289.167079] [drm:intel_dump_pipe_config [i915]] [CRTC:47:pipe B][modeset]
>[13289.167090] [drm:intel_dump_pipe_config [i915]] output_types: DP (0x80)
>[13289.167101] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[13289.167112] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[13289.167122] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[13289.167132] [drm:intel_dump_pipe_config [i915]] requested mode:
>[13289.167138] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[13289.167148] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[13289.167153] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[13289.167164] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[13289.167174] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[13289.167184] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[13289.167193] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[13289.167203] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[13289.167213] [drm:intel_dump_pipe_config [i915]] dpll_hw_state: ctrl1: 0x3, cfgcr1: 0x0, cfgcr2: 0x0
>[13289.167222] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[13289.167232] [drm:intel_dump_pipe_config [i915]] [PLANE:38:plane 1B] disabled, scaler_id = -1
>[13289.167241] [drm:intel_dump_pipe_config [i915]] [PLANE:41:plane 2B] disabled, scaler_id = -1
>[13289.167250] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor B] disabled, scaler_id = -1
>[13289.167262] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[13289.167273] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[13289.167286] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:47:pipe B] has [PLANE:38:plane 1B] with fb 98
>[13289.167297] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:38:plane 1B] visible 0 -> 1, off 0, on 1, ms 1
>[13289.167309] [drm:intel_find_shared_dpll [i915]] [CRTC:47:pipe B] allocated DPLL 1
>[13289.167320] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[13289.167327] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:37:pipe A] 00000000604357f6 state to 00000000a6ac6587
>[13289.167337] [drm:skl_compute_wm [i915]] [PLANE:38:plane 1B] ddb (0 - 0) -> (0 - 860)
>[13289.167346] [drm:skl_compute_wm [i915]] [PLANE:44:cursor B] ddb (0 - 0) -> (860 - 892)
>[13289.167351] [drm:drm_atomic_commit [drm]] committing 00000000a6ac6587
>[13289.167630] [drm:intel_power_well_enable [i915]] enabling power well 2
>[13289.167647] [drm:intel_atomic_commit_tail [i915]] [ENCODER:48:DDI A]
>[13289.167659] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI B]
>[13289.167669] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[13289.167679] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[13289.167689] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DDI C]
>[13289.167699] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST A]
>[13289.167708] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST B]
>[13289.167718] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI D]
>[13289.167727] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[13289.167737] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[13289.167747] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[13289.167759] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[13289.167769] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[13289.167780] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[13289.167792] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 2, on? 0) for crtc 47
>[13289.167804] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[13289.167888] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well
>[13289.168920] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[13289.168951] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[13289.168963] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[13289.168975] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[13289.169570] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 04000000
>[13289.169598] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[13289.169609] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[13289.170174] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[13289.170201] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[13289.171071] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[13289.171393] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:61:DP-2] Link Training Passed at Link Rate = 162000, Lane count = 4
>[13289.171748] [drm:intel_enable_pipe [i915]] enabling pipe B
>[13289.171794] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS
>[13289.188582] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:61:DP-2]
>[13289.188599] [drm:intel_atomic_commit_tail [i915]] [CRTC:47:pipe B]
>[13289.188621] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[13289.188631] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000a6ac6587
>[13289.188637] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000a6ac6587
>[13289.188645] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000a6ac6587
>[13289.188651] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:47:pipe B] 000000002b48c403 state to 00000000a6ac6587
>[13289.188656] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:38:plane 1B] 00000000dbafe848 state to 00000000a6ac6587
>[13289.188660] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 00000000dbafe848 to [CRTC:47:pipe B]
>[13289.188664] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:99] for plane state 00000000dbafe848
>[13289.188669] [drm:drm_atomic_check_only [drm]] checking 00000000a6ac6587
>[13289.188695] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:47:pipe B] has [PLANE:38:plane 1B] with fb 99
>[13289.188710] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:38:plane 1B] visible 1 -> 1, off 0, on 0, ms 0
>[13289.189105] [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000a6ac6587 nonblocking
>[13289.205226] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000a6ac6587
>[13289.205233] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000a6ac6587
>[13289.205328] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[13289.205353] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:61:DP-2]
>[13289.205361] [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000059e36985
>[13289.205370] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:47:pipe B] 0000000043cb4c64 state to 0000000059e36985
>[13289.205376] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:38:plane 1B] 000000002969d135 state to 0000000059e36985
>[13289.205384] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [MODE:1920x1200] for CRTC state 0000000043cb4c64
>[13289.205389] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 000000002969d135 to [CRTC:47:pipe B]
>[13289.205395] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:98] for plane state 000000002969d135
>[13289.205400] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:47:pipe B] to 0000000059e36985
>[13289.205406] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:61:DP-2] 00000000d7ded903 state to 0000000059e36985
>[13289.205412] [drm:drm_atomic_set_crtc_for_connector [drm]] Link connector state 00000000d7ded903 to [NOCRTC]
>[13289.205417] [drm:drm_atomic_set_crtc_for_connector [drm]] Link connector state 00000000d7ded903 to [CRTC:47:pipe B]
>[13289.205423] [drm:drm_atomic_check_only [drm]] checking 0000000059e36985
>[13289.205428] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:61:DP-2]
>[13289.205431] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:61:DP-2] keeps [ENCODER:60:DDI C], now on [CRTC:47:pipe B]
>[13289.205455] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:47:pipe B] has [PLANE:38:plane 1B] with fb 98
>[13289.205474] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:38:plane 1B] visible 1 -> 1, off 0, on 0, ms 0
>[13289.205484] [drm:drm_atomic_commit [drm]] committing 0000000059e36985
>[13290.206066] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000059e36985
>[13290.206097] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000059e36985
>[13290.206157] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[13290.206182] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000a6ac6587
>[13290.206206] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:47:pipe B] 000000002b48c403 state to 00000000a6ac6587
>[13290.206226] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:38:plane 1B] 00000000dbafe848 state to 00000000a6ac6587
>[13290.206246] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for CRTC state 000000002b48c403
>[13290.206264] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 00000000dbafe848 to [NOCRTC]
>[13290.206283] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for plane state 00000000dbafe848
>[13290.206301] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:47:pipe B] to 00000000a6ac6587
>[13290.206321] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:61:DP-2] 00000000d1e5643f state to 00000000a6ac6587
>[13290.206339] [drm:drm_atomic_set_crtc_for_connector [drm]] Link connector state 00000000d1e5643f to [NOCRTC]
>[13290.206356] [drm:drm_atomic_check_only [drm]] checking 00000000a6ac6587
>[13290.206372] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:47:pipe B] mode changed
>[13290.206383] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:47:pipe B] enable changed
>[13290.206392] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:47:pipe B] active changed
>[13290.206402] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:61:DP-2]
>[13290.206411] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Disabling [CONNECTOR:61:DP-2]
>[13290.206421] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:47:pipe B] needs all connectors, enable: n, active: n
>[13290.206440] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:47:pipe B] to 00000000a6ac6587
>[13290.206519] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[13290.206588] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[13290.206655] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:47:pipe B] has [PLANE:38:plane 1B] with fb -1
>[13290.206714] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:38:plane 1B] visible 1 -> 0, off 1, on 0, ms 1
>[13290.206743] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:37:pipe A] 00000000bd3c0152 state to 00000000a6ac6587
>[13290.206794] [drm:skl_compute_wm [i915]] [PLANE:38:plane 1B] ddb (0 - 860) -> (0 - 0)
>[13290.206839] [drm:skl_compute_wm [i915]] [PLANE:44:cursor B] ddb (860 - 892) -> (0 - 0)
>[13290.206862] [drm:drm_atomic_commit [drm]] committing 00000000a6ac6587
>[13290.206957] [drm:intel_disable_pipe [i915]] disabling pipe B
>[13290.223554] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well
>[13290.223625] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 2, on? 1) for crtc 47
>[13290.223686] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[13290.223759] [drm:intel_atomic_commit_tail [i915]] [ENCODER:48:DDI A]
>[13290.223814] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI B]
>[13290.223865] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[13290.223913] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[13290.223960] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DDI C]
>[13290.224009] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST A]
>[13290.224056] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST B]
>[13290.224101] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI D]
>[13290.224146] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[13290.224191] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[13290.224243] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:61:DP-2]
>[13290.224296] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[13290.224347] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[13290.224397] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[13290.224445] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[13290.224495] [drm:intel_power_well_disable [i915]] disabling power well 2
>[13290.224552] [drm:intel_atomic_commit_tail [i915]] [CRTC:47:pipe B]
>[13290.224586] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000a6ac6587
>[13290.224613] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000a6ac6587
>[13290.224867] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[13290.224896] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:61:DP-2]
>[13290.224923] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000a6ac6587
>[13290.224949] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:47:pipe B] 00000000604357f6 state to 00000000a6ac6587
>[13290.224974] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:38:plane 1B] 00000000c4c517e9 state to 00000000a6ac6587
>[13290.224997] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [MODE:1920x1200] for CRTC state 00000000604357f6
>[13290.225018] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 00000000c4c517e9 to [CRTC:47:pipe B]
>[13290.225039] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:99] for plane state 00000000c4c517e9
>[13290.225059] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:47:pipe B] to 00000000a6ac6587
>[13290.225081] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:61:DP-2] 000000005a636f37 state to 00000000a6ac6587
>[13290.225099] [drm:drm_atomic_set_crtc_for_connector [drm]] Link connector state 000000005a636f37 to [CRTC:47:pipe B]
>[13290.225121] [drm:drm_atomic_check_only [drm]] checking 00000000a6ac6587
>[13290.225137] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:47:pipe B] mode changed
>[13290.225150] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:47:pipe B] enable changed
>[13290.225159] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:47:pipe B] active changed
>[13290.225172] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:61:DP-2]
>[13290.225185] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:61:DP-2] using [ENCODER:60:DDI C] on [CRTC:47:pipe B]
>[13290.225195] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:47:pipe B] needs all connectors, enable: y, active: y
>[13290.225214] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:47:pipe B] to 00000000a6ac6587
>[13290.225237] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:47:pipe B] to 00000000a6ac6587
>[13290.225303] [drm:intel_atomic_check [i915]] [CONNECTOR:61:DP-2] checking for sink bpp constrains
>[13290.225365] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[13290.225429] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[13290.225504] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[13290.225560] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[13290.225621] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[13290.225688] [drm:intel_dump_pipe_config [i915]] [CRTC:47:pipe B][modeset]
>[13290.225744] [drm:intel_dump_pipe_config [i915]] output_types: DP (0x80)
>[13290.225797] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[13290.225849] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[13290.225899] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[13290.225947] [drm:intel_dump_pipe_config [i915]] requested mode:
>[13290.225977] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[13290.226026] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[13290.226054] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[13290.226107] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[13290.226157] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[13290.226206] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[13290.226255] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[13290.226302] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[13290.226349] [drm:intel_dump_pipe_config [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[13290.226395] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[13290.226442] [drm:intel_dump_pipe_config [i915]] [PLANE:38:plane 1B] disabled, scaler_id = -1
>[13290.226488] [drm:intel_dump_pipe_config [i915]] [PLANE:41:plane 2B] disabled, scaler_id = -1
>[13290.226535] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor B] disabled, scaler_id = -1
>[13290.226593] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[13290.226646] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[13290.226705] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:47:pipe B] has [PLANE:38:plane 1B] with fb 99
>[13290.226758] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:38:plane 1B] visible 0 -> 1, off 0, on 1, ms 1
>[13290.226816] [drm:intel_find_shared_dpll [i915]] [CRTC:47:pipe B] allocated DPLL 1
>[13290.226869] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[13290.226919] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:37:pipe A] 00000000c85dec7a state to 00000000a6ac6587
>[13290.226970] [drm:skl_compute_wm [i915]] [PLANE:38:plane 1B] ddb (0 - 0) -> (0 - 860)
>[13290.227014] [drm:skl_compute_wm [i915]] [PLANE:44:cursor B] ddb (0 - 0) -> (860 - 892)
>[13290.227041] [drm:drm_atomic_commit [drm]] committing 00000000a6ac6587
>[13291.225106] [drm:intel_power_well_enable [i915]] enabling power well 2
>[13291.225190] [drm:intel_atomic_commit_tail [i915]] [ENCODER:48:DDI A]
>[13291.225253] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI B]
>[13291.225310] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[13291.225363] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[13291.225414] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DDI C]
>[13291.225464] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST A]
>[13291.225514] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST B]
>[13291.225563] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI D]
>[13291.225611] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[13291.225658] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[13291.225713] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[13291.225769] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[13291.225821] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[13291.225873] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[13291.225936] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 2, on? 0) for crtc 47
>[13291.225991] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[13291.226132] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well
>[13291.227235] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[13291.227288] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[13291.227337] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[13291.227386] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[13291.228028] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[13291.228076] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[13291.229039] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[13291.229431] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:61:DP-2] Link Training Passed at Link Rate = 162000, Lane count = 4
>[13291.229936] [drm:intel_enable_pipe [i915]] enabling pipe B
>[13291.230009] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS
>[13291.246785] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:61:DP-2]
>[13291.246858] [drm:intel_atomic_commit_tail [i915]] [CRTC:47:pipe B]
>[13291.246937] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[13291.246974] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000a6ac6587
>[13291.246999] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000a6ac6587
>[13291.247057] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[13291.247082] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000a6ac6587
>[13291.247107] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:47:pipe B] 000000002b48c403 state to 00000000a6ac6587
>[13291.247127] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:38:plane 1B] 000000005906dec2 state to 00000000a6ac6587
>[13291.247146] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for CRTC state 000000002b48c403
>[13291.247164] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 000000005906dec2 to [NOCRTC]
>[13291.247182] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for plane state 000000005906dec2
>[13291.247200] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:47:pipe B] to 00000000a6ac6587
>[13291.247220] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:61:DP-2] 0000000056bf571a state to 00000000a6ac6587
>[13291.247237] [drm:drm_atomic_set_crtc_for_connector [drm]] Link connector state 0000000056bf571a to [NOCRTC]
>[13291.247255] [drm:drm_atomic_check_only [drm]] checking 00000000a6ac6587
>[13291.247270] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:47:pipe B] mode changed
>[13291.247281] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:47:pipe B] enable changed
>[13291.247290] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:47:pipe B] active changed
>[13291.247300] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:61:DP-2]
>[13291.247309] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Disabling [CONNECTOR:61:DP-2]
>[13291.247319] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:47:pipe B] needs all connectors, enable: n, active: n
>[13291.247338] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:47:pipe B] to 00000000a6ac6587
>[13291.247413] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[13291.247476] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[13291.247541] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:47:pipe B] has [PLANE:38:plane 1B] with fb -1
>[13291.247601] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:38:plane 1B] visible 1 -> 0, off 1, on 0, ms 1
>[13291.247630] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:37:pipe A] 00000000bd3c0152 state to 00000000a6ac6587
>[13291.247679] [drm:skl_compute_wm [i915]] [PLANE:38:plane 1B] ddb (0 - 860) -> (0 - 0)
>[13291.247725] [drm:skl_compute_wm [i915]] [PLANE:44:cursor B] ddb (860 - 892) -> (0 - 0)
>[13291.247749] [drm:drm_atomic_commit [drm]] committing 00000000a6ac6587
>[13291.247843] [drm:intel_disable_pipe [i915]] disabling pipe B
>[13291.263809] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well
>[13291.263881] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 2, on? 1) for crtc 47
>[13291.263943] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[13291.264017] [drm:intel_atomic_commit_tail [i915]] [ENCODER:48:DDI A]
>[13291.264072] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI B]
>[13291.264123] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[13291.264171] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[13291.264218] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DDI C]
>[13291.264267] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST A]
>[13291.264313] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST B]
>[13291.264358] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI D]
>[13291.264403] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[13291.264447] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[13291.264499] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:61:DP-2]
>[13291.264552] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[13291.264603] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[13291.264652] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[13291.264701] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[13291.264784] [drm:intel_power_well_disable [i915]] disabling power well 2
>[13291.264853] [drm:intel_atomic_commit_tail [i915]] [CRTC:47:pipe B]
>[13291.264896] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000a6ac6587
>[13291.264927] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000a6ac6587
>[13291.265143] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[13291.265169] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:61:DP-2]
>[13291.265196] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000a6ac6587
>[13291.265223] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:47:pipe B] 00000000604357f6 state to 00000000a6ac6587
>[13291.265247] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:38:plane 1B] 00000000dbafe848 state to 00000000a6ac6587
>[13291.265272] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [MODE:1920x1200] for CRTC state 00000000604357f6
>[13291.265294] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 00000000dbafe848 to [CRTC:47:pipe B]
>[13291.265315] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:98] for plane state 00000000dbafe848
>[13291.265335] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:47:pipe B] to 00000000a6ac6587
>[13291.265357] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:61:DP-2] 00000000d1e5643f state to 00000000a6ac6587
>[13291.265376] [drm:drm_atomic_set_crtc_for_connector [drm]] Link connector state 00000000d1e5643f to [CRTC:47:pipe B]
>[13291.265398] [drm:drm_atomic_check_only [drm]] checking 00000000a6ac6587
>[13291.265414] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:47:pipe B] mode changed
>[13291.265427] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:47:pipe B] enable changed
>[13291.265436] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:47:pipe B] active changed
>[13291.265448] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:61:DP-2]
>[13291.265460] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:61:DP-2] using [ENCODER:60:DDI C] on [CRTC:47:pipe B]
>[13291.265471] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:47:pipe B] needs all connectors, enable: y, active: y
>[13291.265490] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:47:pipe B] to 00000000a6ac6587
>[13291.265512] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:47:pipe B] to 00000000a6ac6587
>[13291.265579] [drm:intel_atomic_check [i915]] [CONNECTOR:61:DP-2] checking for sink bpp constrains
>[13291.265641] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[13291.265705] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[13291.265779] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[13291.265834] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[13291.265894] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[13291.265952] [drm:intel_dump_pipe_config [i915]] [CRTC:47:pipe B][modeset]
>[13291.266007] [drm:intel_dump_pipe_config [i915]] output_types: DP (0x80)
>[13291.266060] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[13291.266114] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[13291.266164] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[13291.266212] [drm:intel_dump_pipe_config [i915]] requested mode:
>[13291.266241] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[13291.266291] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[13291.266317] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[13291.266371] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[13291.266420] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[13291.266470] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[13291.266517] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[13291.266565] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[13291.266612] [drm:intel_dump_pipe_config [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[13291.266659] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[13291.266706] [drm:intel_dump_pipe_config [i915]] [PLANE:38:plane 1B] disabled, scaler_id = -1
>[13291.266753] [drm:intel_dump_pipe_config [i915]] [PLANE:41:plane 2B] disabled, scaler_id = -1
>[13291.266800] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor B] disabled, scaler_id = -1
>[13291.266858] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[13291.266911] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[13291.266970] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:47:pipe B] has [PLANE:38:plane 1B] with fb 98
>[13291.267023] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:38:plane 1B] visible 0 -> 1, off 0, on 1, ms 1
>[13291.267082] [drm:intel_find_shared_dpll [i915]] [CRTC:47:pipe B] allocated DPLL 1
>[13291.267137] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[13291.267170] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:37:pipe A] 00000000c85dec7a state to 00000000a6ac6587
>[13291.267220] [drm:skl_compute_wm [i915]] [PLANE:38:plane 1B] ddb (0 - 0) -> (0 - 860)
>[13291.267264] [drm:skl_compute_wm [i915]] [PLANE:44:cursor B] ddb (0 - 0) -> (860 - 892)
>[13291.267292] [drm:drm_atomic_commit [drm]] committing 00000000a6ac6587
>[13292.265372] [drm:intel_power_well_enable [i915]] enabling power well 2
>[13292.265455] [drm:intel_atomic_commit_tail [i915]] [ENCODER:48:DDI A]
>[13292.265518] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI B]
>[13292.265576] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[13292.265630] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[13292.265682] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DDI C]
>[13292.265733] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST A]
>[13292.265783] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST B]
>[13292.265833] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI D]
>[13292.265883] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[13292.265932] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[13292.265987] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[13292.266044] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[13292.266099] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[13292.266151] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[13292.266214] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 2, on? 0) for crtc 47
>[13292.266270] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[13292.266412] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well
>[13292.267514] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[13292.267567] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[13292.267618] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[13292.267667] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[13292.268311] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[13292.268359] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[13292.269309] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[13292.269688] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:61:DP-2] Link Training Passed at Link Rate = 162000, Lane count = 4
>[13292.270192] [drm:intel_enable_pipe [i915]] enabling pipe B
>[13292.270277] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS
>[13292.287067] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:61:DP-2]
>[13292.287141] [drm:intel_atomic_commit_tail [i915]] [CRTC:47:pipe B]
>[13292.287221] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[13292.287258] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000a6ac6587
>[13292.287284] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000a6ac6587
>[13292.287343] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[13292.287367] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000a6ac6587
>[13292.287392] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:47:pipe B] 000000002b48c403 state to 00000000a6ac6587
>[13292.287412] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:38:plane 1B] 00000000c4c517e9 state to 00000000a6ac6587
>[13292.287432] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for CRTC state 000000002b48c403
>[13292.287451] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 00000000c4c517e9 to [NOCRTC]
>[13292.287470] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for plane state 00000000c4c517e9
>[13292.287488] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:47:pipe B] to 00000000a6ac6587
>[13292.287508] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:61:DP-2] 00000000409178cb state to 00000000a6ac6587
>[13292.287526] [drm:drm_atomic_set_crtc_for_connector [drm]] Link connector state 00000000409178cb to [NOCRTC]
>[13292.287544] [drm:drm_atomic_check_only [drm]] checking 00000000a6ac6587
>[13292.287559] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:47:pipe B] mode changed
>[13292.287570] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:47:pipe B] enable changed
>[13292.287579] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:47:pipe B] active changed
>[13292.287589] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:61:DP-2]
>[13292.287598] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Disabling [CONNECTOR:61:DP-2]
>[13292.287608] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:47:pipe B] needs all connectors, enable: n, active: n
>[13292.287627] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:47:pipe B] to 00000000a6ac6587
>[13292.287703] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[13292.287768] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[13292.287834] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:47:pipe B] has [PLANE:38:plane 1B] with fb -1
>[13292.287894] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:38:plane 1B] visible 1 -> 0, off 1, on 0, ms 1
>[13292.287923] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:37:pipe A] 00000000bd3c0152 state to 00000000a6ac6587
>[13292.287974] [drm:skl_compute_wm [i915]] [PLANE:38:plane 1B] ddb (0 - 860) -> (0 - 0)
>[13292.288020] [drm:skl_compute_wm [i915]] [PLANE:44:cursor B] ddb (860 - 892) -> (0 - 0)
>[13292.288044] [drm:drm_atomic_commit [drm]] committing 00000000a6ac6587
>[13292.288140] [drm:intel_disable_pipe [i915]] disabling pipe B
>[13292.303970] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well
>[13292.304043] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 2, on? 1) for crtc 47
>[13292.304104] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[13292.304177] [drm:intel_atomic_commit_tail [i915]] [ENCODER:48:DDI A]
>[13292.304232] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI B]
>[13292.304283] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[13292.304332] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[13292.304380] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DDI C]
>[13292.304429] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST A]
>[13292.304476] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST B]
>[13292.304522] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI D]
>[13292.304568] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[13292.304613] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[13292.304665] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:61:DP-2]
>[13292.304718] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[13292.304801] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[13292.304860] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[13292.304918] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[13292.304973] [drm:intel_power_well_disable [i915]] disabling power well 2
>[13292.305036] [drm:intel_atomic_commit_tail [i915]] [CRTC:47:pipe B]
>[13292.305074] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000a6ac6587
>[13292.305102] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000a6ac6587
>[13292.305321] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[13292.305348] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:61:DP-2]
>[13292.305373] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000a6ac6587
>[13292.305400] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:47:pipe B] 00000000604357f6 state to 00000000a6ac6587
>[13292.305424] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:38:plane 1B] 000000005906dec2 state to 00000000a6ac6587
>[13292.305448] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [MODE:1920x1200] for CRTC state 00000000604357f6
>[13292.305468] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 000000005906dec2 to [CRTC:47:pipe B]
>[13292.305490] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:99] for plane state 000000005906dec2
>[13292.305510] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:47:pipe B] to 00000000a6ac6587
>[13292.305533] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:61:DP-2] 0000000056bf571a state to 00000000a6ac6587
>[13292.305552] [drm:drm_atomic_set_crtc_for_connector [drm]] Link connector state 0000000056bf571a to [CRTC:47:pipe B]
>[13292.305573] [drm:drm_atomic_check_only [drm]] checking 00000000a6ac6587
>[13292.305589] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:47:pipe B] mode changed
>[13292.305600] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:47:pipe B] enable changed
>[13292.305611] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:47:pipe B] active changed
>[13292.305622] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:61:DP-2]
>[13292.305635] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:61:DP-2] using [ENCODER:60:DDI C] on [CRTC:47:pipe B]
>[13292.305645] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:47:pipe B] needs all connectors, enable: y, active: y
>[13292.305664] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:47:pipe B] to 00000000a6ac6587
>[13292.305686] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:47:pipe B] to 00000000a6ac6587
>[13292.305752] [drm:intel_atomic_check [i915]] [CONNECTOR:61:DP-2] checking for sink bpp constrains
>[13292.305814] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[13292.305880] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[13292.305953] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[13292.306017] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[13292.306076] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[13292.306136] [drm:intel_dump_pipe_config [i915]] [CRTC:47:pipe B][modeset]
>[13292.306191] [drm:intel_dump_pipe_config [i915]] output_types: DP (0x80)
>[13292.306245] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[13292.306298] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[13292.306348] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[13292.306397] [drm:intel_dump_pipe_config [i915]] requested mode:
>[13292.306427] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[13292.306477] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[13292.306505] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[13292.306558] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[13292.306609] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[13292.306658] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[13292.306708] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[13292.306755] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[13292.306804] [drm:intel_dump_pipe_config [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[13292.306851] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[13292.306899] [drm:intel_dump_pipe_config [i915]] [PLANE:38:plane 1B] disabled, scaler_id = -1
>[13292.306946] [drm:intel_dump_pipe_config [i915]] [PLANE:41:plane 2B] disabled, scaler_id = -1
>[13292.306993] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor B] disabled, scaler_id = -1
>[13292.307051] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[13292.307104] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[13292.307163] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:47:pipe B] has [PLANE:38:plane 1B] with fb 99
>[13292.307215] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:38:plane 1B] visible 0 -> 1, off 0, on 1, ms 1
>[13292.307273] [drm:intel_find_shared_dpll [i915]] [CRTC:47:pipe B] allocated DPLL 1
>[13292.307327] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[13292.307377] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:37:pipe A] 00000000c85dec7a state to 00000000a6ac6587
>[13292.307429] [drm:skl_compute_wm [i915]] [PLANE:38:plane 1B] ddb (0 - 0) -> (0 - 860)
>[13292.307473] [drm:skl_compute_wm [i915]] [PLANE:44:cursor B] ddb (0 - 0) -> (860 - 892)
>[13292.307500] [drm:drm_atomic_commit [drm]] committing 00000000a6ac6587
>[13293.305558] [drm:intel_power_well_enable [i915]] enabling power well 2
>[13293.305641] [drm:intel_atomic_commit_tail [i915]] [ENCODER:48:DDI A]
>[13293.305705] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI B]
>[13293.305762] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[13293.305816] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[13293.305867] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DDI C]
>[13293.305917] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST A]
>[13293.305966] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST B]
>[13293.306015] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI D]
>[13293.306064] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[13293.306112] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[13293.306167] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[13293.306224] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[13293.306277] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[13293.306330] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[13293.306393] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 2, on? 0) for crtc 47
>[13293.306450] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[13293.306592] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well
>[13293.307695] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[13293.307748] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[13293.307798] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[13293.307848] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[13293.308488] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 04000000
>[13293.308534] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[13293.308579] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[13293.309233] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[13293.309282] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[13293.310222] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[13293.310557] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:61:DP-2] Link Training Passed at Link Rate = 162000, Lane count = 4
>[13293.310923] [drm:intel_enable_pipe [i915]] enabling pipe B
>[13293.310944] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS
>[13293.327710] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:61:DP-2]
>[13293.327731] [drm:intel_atomic_commit_tail [i915]] [CRTC:47:pipe B]
>[13293.327756] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[13293.327767] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000a6ac6587
>[13293.327774] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000a6ac6587
>[13293.327791] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[13293.327797] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000a6ac6587
>[13293.327804] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:47:pipe B] 000000002b48c403 state to 00000000a6ac6587
>[13293.327809] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:38:plane 1B] 00000000dbafe848 state to 00000000a6ac6587
>[13293.327814] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for CRTC state 000000002b48c403
>[13293.327819] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 00000000dbafe848 to [NOCRTC]
>[13293.327824] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for plane state 00000000dbafe848
>[13293.327829] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:47:pipe B] to 00000000a6ac6587
>[13293.327834] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:61:DP-2] 00000000572650ad state to 00000000a6ac6587
>[13293.327839] [drm:drm_atomic_set_crtc_for_connector [drm]] Link connector state 00000000572650ad to [NOCRTC]
>[13293.327844] [drm:drm_atomic_check_only [drm]] checking 00000000a6ac6587
>[13293.327848] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:47:pipe B] mode changed
>[13293.327850] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:47:pipe B] enable changed
>[13293.327853] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:47:pipe B] active changed
>[13293.327855] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:61:DP-2]
>[13293.327858] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Disabling [CONNECTOR:61:DP-2]
>[13293.327860] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:47:pipe B] needs all connectors, enable: n, active: n
>[13293.327865] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:47:pipe B] to 00000000a6ac6587
>[13293.327886] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[13293.327903] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[13293.327920] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:47:pipe B] has [PLANE:38:plane 1B] with fb -1
>[13293.327936] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:38:plane 1B] visible 1 -> 0, off 1, on 0, ms 1
>[13293.327944] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:37:pipe A] 00000000bd3c0152 state to 00000000a6ac6587
>[13293.327958] [drm:skl_compute_wm [i915]] [PLANE:38:plane 1B] ddb (0 - 860) -> (0 - 0)
>[13293.327970] [drm:skl_compute_wm [i915]] [PLANE:44:cursor B] ddb (860 - 892) -> (0 - 0)
>[13293.327976] [drm:drm_atomic_commit [drm]] committing 00000000a6ac6587
>[13293.328003] [drm:intel_disable_pipe [i915]] disabling pipe B
>[13293.344870] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well
>[13293.344897] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 2, on? 1) for crtc 47
>[13293.344919] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[13293.344950] [drm:intel_atomic_commit_tail [i915]] [ENCODER:48:DDI A]
>[13293.344970] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI B]
>[13293.344989] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[13293.345006] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[13293.345024] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DDI C]
>[13293.345041] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST A]
>[13293.345058] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST B]
>[13293.345074] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI D]
>[13293.345090] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[13293.345107] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[13293.345126] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:61:DP-2]
>[13293.345145] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[13293.345163] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[13293.345181] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[13293.345198] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[13293.345217] [drm:intel_power_well_disable [i915]] disabling power well 2
>[13293.345238] [drm:intel_atomic_commit_tail [i915]] [CRTC:47:pipe B]
>[13293.345251] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000a6ac6587
>[13293.345261] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000a6ac6587
>[13293.345369] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[13293.345380] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:61:DP-2]
>[13293.345390] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000a6ac6587
>[13293.345399] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:47:pipe B] 00000000604357f6 state to 00000000a6ac6587
>[13293.345408] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:38:plane 1B] 00000000c4c517e9 state to 00000000a6ac6587
>[13293.345417] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [MODE:1920x1200] for CRTC state 00000000604357f6
>[13293.345425] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 00000000c4c517e9 to [CRTC:47:pipe B]
>[13293.345432] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:98] for plane state 00000000c4c517e9
>[13293.345440] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:47:pipe B] to 00000000a6ac6587
>[13293.345448] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:61:DP-2] 00000000409178cb state to 00000000a6ac6587
>[13293.345454] [drm:drm_atomic_set_crtc_for_connector [drm]] Link connector state 00000000409178cb to [CRTC:47:pipe B]
>[13293.345462] [drm:drm_atomic_check_only [drm]] checking 00000000a6ac6587
>[13293.345468] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:47:pipe B] mode changed
>[13293.345472] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:47:pipe B] enable changed
>[13293.345476] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:47:pipe B] active changed
>[13293.345480] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:61:DP-2]
>[13293.345484] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:61:DP-2] using [ENCODER:60:DDI C] on [CRTC:47:pipe B]
>[13293.345488] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:47:pipe B] needs all connectors, enable: y, active: y
>[13293.345495] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:47:pipe B] to 00000000a6ac6587
>[13293.345504] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:47:pipe B] to 00000000a6ac6587
>[13293.345530] [drm:intel_atomic_check [i915]] [CONNECTOR:61:DP-2] checking for sink bpp constrains
>[13293.345555] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[13293.345581] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[13293.345610] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[13293.345632] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[13293.345656] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[13293.345679] [drm:intel_dump_pipe_config [i915]] [CRTC:47:pipe B][modeset]
>[13293.345702] [drm:intel_dump_pipe_config [i915]] output_types: DP (0x80)
>[13293.345723] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[13293.345744] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[13293.345763] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[13293.345782] [drm:intel_dump_pipe_config [i915]] requested mode:
>[13293.345793] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[13293.345813] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[13293.345823] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[13293.345844] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[13293.345864] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[13293.345883] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[13293.345902] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[13293.345920] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[13293.345939] [drm:intel_dump_pipe_config [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[13293.345957] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[13293.345975] [drm:intel_dump_pipe_config [i915]] [PLANE:38:plane 1B] disabled, scaler_id = -1
>[13293.345994] [drm:intel_dump_pipe_config [i915]] [PLANE:41:plane 2B] disabled, scaler_id = -1
>[13293.346012] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor B] disabled, scaler_id = -1
>[13293.346035] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[13293.346055] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[13293.346079] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:47:pipe B] has [PLANE:38:plane 1B] with fb 98
>[13293.346100] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:38:plane 1B] visible 0 -> 1, off 0, on 1, ms 1
>[13293.346123] [drm:intel_find_shared_dpll [i915]] [CRTC:47:pipe B] allocated DPLL 1
>[13293.346145] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[13293.346158] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:37:pipe A] 00000000c85dec7a state to 00000000a6ac6587
>[13293.346178] [drm:skl_compute_wm [i915]] [PLANE:38:plane 1B] ddb (0 - 0) -> (0 - 860)
>[13293.346195] [drm:skl_compute_wm [i915]] [PLANE:44:cursor B] ddb (0 - 0) -> (860 - 892)
>[13293.346205] [drm:drm_atomic_commit [drm]] committing 00000000a6ac6587
>[13294.345618] [drm:intel_power_well_enable [i915]] enabling power well 2
>[13294.345701] [drm:intel_atomic_commit_tail [i915]] [ENCODER:48:DDI A]
>[13294.345765] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI B]
>[13294.345822] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[13294.345875] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[13294.345927] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DDI C]
>[13294.345977] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST A]
>[13294.346026] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST B]
>[13294.346075] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI D]
>[13294.346124] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[13294.346172] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[13294.346227] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[13294.346283] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[13294.346337] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[13294.346388] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[13294.346450] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 2, on? 0) for crtc 47
>[13294.346507] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[13294.346648] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well
>[13294.347751] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[13294.347804] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[13294.347853] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[13294.347901] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[13294.348542] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[13294.348591] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[13294.349555] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[13294.349936] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:61:DP-2] Link Training Passed at Link Rate = 162000, Lane count = 4
>[13294.350441] [drm:intel_enable_pipe [i915]] enabling pipe B
>[13294.350524] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS
>[13294.367289] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:61:DP-2]
>[13294.367362] [drm:intel_atomic_commit_tail [i915]] [CRTC:47:pipe B]
>[13294.367441] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[13294.367478] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000a6ac6587
>[13294.367503] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000a6ac6587
>[13294.367562] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[13294.367586] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000a6ac6587
>[13294.367612] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:47:pipe B] 000000002b48c403 state to 00000000a6ac6587
>[13294.367633] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:38:plane 1B] 000000005906dec2 state to 00000000a6ac6587
>[13294.367653] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for CRTC state 000000002b48c403
>[13294.367671] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 000000005906dec2 to [NOCRTC]
>[13294.367689] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for plane state 000000005906dec2
>[13294.367707] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:47:pipe B] to 00000000a6ac6587
>[13294.367727] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:61:DP-2] 000000005a636f37 state to 00000000a6ac6587
>[13294.367745] [drm:drm_atomic_set_crtc_for_connector [drm]] Link connector state 000000005a636f37 to [NOCRTC]
>[13294.367763] [drm:drm_atomic_check_only [drm]] checking 00000000a6ac6587
>[13294.367778] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:47:pipe B] mode changed
>[13294.367789] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:47:pipe B] enable changed
>[13294.367798] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:47:pipe B] active changed
>[13294.367808] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:61:DP-2]
>[13294.367817] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Disabling [CONNECTOR:61:DP-2]
>[13294.367827] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:47:pipe B] needs all connectors, enable: n, active: n
>[13294.367846] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:47:pipe B] to 00000000a6ac6587
>[13294.367920] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[13294.367984] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[13294.368050] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:47:pipe B] has [PLANE:38:plane 1B] with fb -1
>[13294.368109] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:38:plane 1B] visible 1 -> 0, off 1, on 0, ms 1
>[13294.368138] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:37:pipe A] 00000000bd3c0152 state to 00000000a6ac6587
>[13294.368189] [drm:skl_compute_wm [i915]] [PLANE:38:plane 1B] ddb (0 - 860) -> (0 - 0)
>[13294.368235] [drm:skl_compute_wm [i915]] [PLANE:44:cursor B] ddb (860 - 892) -> (0 - 0)
>[13294.368258] [drm:drm_atomic_commit [drm]] committing 00000000a6ac6587
>[13294.368352] [drm:intel_disable_pipe [i915]] disabling pipe B
>[13294.384417] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well
>[13294.384489] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 2, on? 1) for crtc 47
>[13294.384551] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[13294.384624] [drm:intel_atomic_commit_tail [i915]] [ENCODER:48:DDI A]
>[13294.384679] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI B]
>[13294.384762] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[13294.384820] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[13294.384877] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DDI C]
>[13294.384931] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST A]
>[13294.384980] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST B]
>[13294.385027] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI D]
>[13294.385075] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[13294.385121] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[13294.385176] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:61:DP-2]
>[13294.385231] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[13294.385284] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[13294.385336] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[13294.385387] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[13294.385438] [drm:intel_power_well_disable [i915]] disabling power well 2
>[13294.385497] [drm:intel_atomic_commit_tail [i915]] [CRTC:47:pipe B]
>[13294.385532] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000a6ac6587
>[13294.385561] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000a6ac6587
>[13294.385805] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[13294.385830] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:61:DP-2]
>[13294.385856] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000a6ac6587
>[13294.385883] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:47:pipe B] 00000000604357f6 state to 00000000a6ac6587
>[13294.385904] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:38:plane 1B] 00000000dbafe848 state to 00000000a6ac6587
>[13294.385927] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [MODE:1920x1200] for CRTC state 00000000604357f6
>[13294.385947] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 00000000dbafe848 to [CRTC:47:pipe B]
>[13294.385967] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:99] for plane state 00000000dbafe848
>[13294.385986] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:47:pipe B] to 00000000a6ac6587
>[13294.386007] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:61:DP-2] 00000000572650ad state to 00000000a6ac6587
>[13294.386024] [drm:drm_atomic_set_crtc_for_connector [drm]] Link connector state 00000000572650ad to [CRTC:47:pipe B]
>[13294.386044] [drm:drm_atomic_check_only [drm]] checking 00000000a6ac6587
>[13294.386059] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:47:pipe B] mode changed
>[13294.386069] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:47:pipe B] enable changed
>[13294.386079] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:47:pipe B] active changed
>[13294.386090] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:61:DP-2]
>[13294.386100] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:61:DP-2] using [ENCODER:60:DDI C] on [CRTC:47:pipe B]
>[13294.386110] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:47:pipe B] needs all connectors, enable: y, active: y
>[13294.386129] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:47:pipe B] to 00000000a6ac6587
>[13294.386149] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:47:pipe B] to 00000000a6ac6587
>[13294.386216] [drm:intel_atomic_check [i915]] [CONNECTOR:61:DP-2] checking for sink bpp constrains
>[13294.386275] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[13294.386338] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[13294.386410] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[13294.386465] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[13294.386523] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[13294.386580] [drm:intel_dump_pipe_config [i915]] [CRTC:47:pipe B][modeset]
>[13294.386635] [drm:intel_dump_pipe_config [i915]] output_types: DP (0x80)
>[13294.386687] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[13294.386739] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[13294.386788] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[13294.386836] [drm:intel_dump_pipe_config [i915]] requested mode:
>[13294.386872] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[13294.386920] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[13294.386946] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[13294.386999] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[13294.387049] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[13294.387096] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[13294.387144] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[13294.387190] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[13294.387237] [drm:intel_dump_pipe_config [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[13294.387282] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[13294.387329] [drm:intel_dump_pipe_config [i915]] [PLANE:38:plane 1B] disabled, scaler_id = -1
>[13294.387374] [drm:intel_dump_pipe_config [i915]] [PLANE:41:plane 2B] disabled, scaler_id = -1
>[13294.387420] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor B] disabled, scaler_id = -1
>[13294.387478] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[13294.387530] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[13294.387589] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:47:pipe B] has [PLANE:38:plane 1B] with fb 99
>[13294.387642] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:38:plane 1B] visible 0 -> 1, off 0, on 1, ms 1
>[13294.387699] [drm:intel_find_shared_dpll [i915]] [CRTC:47:pipe B] allocated DPLL 1
>[13294.387752] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[13294.387801] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:37:pipe A] 00000000c85dec7a state to 00000000a6ac6587
>[13294.387852] [drm:skl_compute_wm [i915]] [PLANE:38:plane 1B] ddb (0 - 0) -> (0 - 860)
>[13294.387896] [drm:skl_compute_wm [i915]] [PLANE:44:cursor B] ddb (0 - 0) -> (860 - 892)
>[13294.387922] [drm:drm_atomic_commit [drm]] committing 00000000a6ac6587
>[13295.386036] [drm:intel_power_well_enable [i915]] enabling power well 2
>[13295.386119] [drm:intel_atomic_commit_tail [i915]] [ENCODER:48:DDI A]
>[13295.386183] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI B]
>[13295.386241] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[13295.386296] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[13295.386348] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DDI C]
>[13295.386398] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST A]
>[13295.386447] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST B]
>[13295.386495] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI D]
>[13295.386544] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[13295.386592] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[13295.386647] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[13295.386703] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[13295.386757] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[13295.386810] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[13295.386873] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 2, on? 0) for crtc 47
>[13295.386929] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[13295.387070] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well
>[13295.388174] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[13295.388228] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[13295.388279] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[13295.388328] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[13295.389013] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[13295.389079] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[13295.390034] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[13295.390419] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:61:DP-2] Link Training Passed at Link Rate = 162000, Lane count = 4
>[13295.390925] [drm:intel_enable_pipe [i915]] enabling pipe B
>[13295.391005] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS
>[13295.407768] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:61:DP-2]
>[13295.407842] [drm:intel_atomic_commit_tail [i915]] [CRTC:47:pipe B]
>[13295.407921] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[13295.407957] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000a6ac6587
>[13295.407984] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000a6ac6587
>[13295.408044] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[13295.408068] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000a6ac6587
>[13295.408094] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:47:pipe B] 000000002b48c403 state to 00000000a6ac6587
>[13295.408116] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:38:plane 1B] 00000000c4c517e9 state to 00000000a6ac6587
>[13295.408137] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for CRTC state 000000002b48c403
>[13295.408156] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 00000000c4c517e9 to [NOCRTC]
>[13295.408176] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for plane state 00000000c4c517e9
>[13295.408194] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:47:pipe B] to 00000000a6ac6587
>[13295.408214] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:61:DP-2] 0000000056bf571a state to 00000000a6ac6587
>[13295.408232] [drm:drm_atomic_set_crtc_for_connector [drm]] Link connector state 0000000056bf571a to [NOCRTC]
>[13295.408250] [drm:drm_atomic_check_only [drm]] checking 00000000a6ac6587
>[13295.408265] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:47:pipe B] mode changed
>[13295.408276] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:47:pipe B] enable changed
>[13295.408286] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:47:pipe B] active changed
>[13295.408296] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:61:DP-2]
>[13295.408305] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Disabling [CONNECTOR:61:DP-2]
>[13295.408315] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:47:pipe B] needs all connectors, enable: n, active: n
>[13295.408334] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:47:pipe B] to 00000000a6ac6587
>[13295.408408] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[13295.408473] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[13295.408539] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:47:pipe B] has [PLANE:38:plane 1B] with fb -1
>[13295.408598] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:38:plane 1B] visible 1 -> 0, off 1, on 0, ms 1
>[13295.408628] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:37:pipe A] 00000000bd3c0152 state to 00000000a6ac6587
>[13295.408677] [drm:skl_compute_wm [i915]] [PLANE:38:plane 1B] ddb (0 - 860) -> (0 - 0)
>[13295.408762] [drm:skl_compute_wm [i915]] [PLANE:44:cursor B] ddb (860 - 892) -> (0 - 0)
>[13295.408799] [drm:drm_atomic_commit [drm]] committing 00000000a6ac6587
>[13295.408901] [drm:intel_disable_pipe [i915]] disabling pipe B
>[13295.426134] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well
>[13295.426206] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 2, on? 1) for crtc 47
>[13295.426266] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[13295.426339] [drm:intel_atomic_commit_tail [i915]] [ENCODER:48:DDI A]
>[13295.426393] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI B]
>[13295.426444] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[13295.426492] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[13295.426539] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DDI C]
>[13295.426588] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST A]
>[13295.426633] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST B]
>[13295.426679] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI D]
>[13295.426724] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[13295.426769] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[13295.426821] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:61:DP-2]
>[13295.426873] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[13295.426925] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[13295.426975] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[13295.427024] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[13295.427073] [drm:intel_power_well_disable [i915]] disabling power well 2
>[13295.427130] [drm:intel_atomic_commit_tail [i915]] [CRTC:47:pipe B]
>[13295.427164] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000a6ac6587
>[13295.427190] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000a6ac6587
>[13295.427403] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[13295.427428] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:61:DP-2]
>[13295.427454] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000a6ac6587
>[13295.427479] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:47:pipe B] 00000000604357f6 state to 00000000a6ac6587
>[13295.427500] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:38:plane 1B] 000000005906dec2 state to 00000000a6ac6587
>[13295.427522] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [MODE:1920x1200] for CRTC state 00000000604357f6
>[13295.427541] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 000000005906dec2 to [CRTC:47:pipe B]
>[13295.427560] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:98] for plane state 000000005906dec2
>[13295.427578] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:47:pipe B] to 00000000a6ac6587
>[13295.427598] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:61:DP-2] 000000005a636f37 state to 00000000a6ac6587
>[13295.427615] [drm:drm_atomic_set_crtc_for_connector [drm]] Link connector state 000000005a636f37 to [CRTC:47:pipe B]
>[13295.427634] [drm:drm_atomic_check_only [drm]] checking 00000000a6ac6587
>[13295.427648] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:47:pipe B] mode changed
>[13295.427659] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:47:pipe B] enable changed
>[13295.427668] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:47:pipe B] active changed
>[13295.427678] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:61:DP-2]
>[13295.427689] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:61:DP-2] using [ENCODER:60:DDI C] on [CRTC:47:pipe B]
>[13295.427699] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:47:pipe B] needs all connectors, enable: y, active: y
>[13295.427717] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:47:pipe B] to 00000000a6ac6587
>[13295.427737] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:47:pipe B] to 00000000a6ac6587
>[13295.427802] [drm:intel_atomic_check [i915]] [CONNECTOR:61:DP-2] checking for sink bpp constrains
>[13295.427862] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[13295.427925] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[13295.427997] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[13295.428051] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[13295.428109] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[13295.428166] [drm:intel_dump_pipe_config [i915]] [CRTC:47:pipe B][modeset]
>[13295.428219] [drm:intel_dump_pipe_config [i915]] output_types: DP (0x80)
>[13295.428269] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[13295.428320] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[13295.428368] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[13295.428414] [drm:intel_dump_pipe_config [i915]] requested mode:
>[13295.428440] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[13295.428487] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[13295.428512] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[13295.428563] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[13295.428610] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[13295.428656] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[13295.428702] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[13295.428783] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[13295.428838] [drm:intel_dump_pipe_config [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[13295.428892] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[13295.428942] [drm:intel_dump_pipe_config [i915]] [PLANE:38:plane 1B] disabled, scaler_id = -1
>[13295.428994] [drm:intel_dump_pipe_config [i915]] [PLANE:41:plane 2B] disabled, scaler_id = -1
>[13295.429044] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor B] disabled, scaler_id = -1
>[13295.429107] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[13295.429163] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[13295.429226] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:47:pipe B] has [PLANE:38:plane 1B] with fb 98
>[13295.429284] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:38:plane 1B] visible 0 -> 1, off 0, on 1, ms 1
>[13295.429346] [drm:intel_find_shared_dpll [i915]] [CRTC:47:pipe B] allocated DPLL 1
>[13295.429405] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[13295.429441] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:37:pipe A] 00000000c85dec7a state to 00000000a6ac6587
>[13295.429495] [drm:skl_compute_wm [i915]] [PLANE:38:plane 1B] ddb (0 - 0) -> (0 - 860)
>[13295.429542] [drm:skl_compute_wm [i915]] [PLANE:44:cursor B] ddb (0 - 0) -> (860 - 892)
>[13295.429574] [drm:drm_atomic_commit [drm]] committing 00000000a6ac6587
>[13296.427639] [drm:intel_power_well_enable [i915]] enabling power well 2
>[13296.427722] [drm:intel_atomic_commit_tail [i915]] [ENCODER:48:DDI A]
>[13296.427786] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI B]
>[13296.427843] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[13296.427897] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[13296.427949] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DDI C]
>[13296.427999] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST A]
>[13296.428049] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST B]
>[13296.428098] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI D]
>[13296.428146] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[13296.428194] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[13296.428249] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[13296.428305] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[13296.428359] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[13296.428411] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[13296.428474] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 2, on? 0) for crtc 47
>[13296.428530] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[13296.428672] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well
>[13296.429836] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[13296.429891] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[13296.429941] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[13296.429990] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[13296.430630] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 04000000
>[13296.430676] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[13296.430722] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[13296.431354] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[13296.431401] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[13296.432338] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[13296.432717] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:61:DP-2] Link Training Passed at Link Rate = 162000, Lane count = 4
>[13296.433239] [drm:intel_enable_pipe [i915]] enabling pipe B
>[13296.433306] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS
>[13296.450079] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:61:DP-2]
>[13296.450153] [drm:intel_atomic_commit_tail [i915]] [CRTC:47:pipe B]
>[13296.450232] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[13296.450269] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000a6ac6587
>[13296.450294] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000a6ac6587
>[13296.450353] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[13296.450377] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000a6ac6587
>[13296.450402] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:47:pipe B] 000000002b48c403 state to 00000000a6ac6587
>[13296.450423] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:38:plane 1B] 00000000dbafe848 state to 00000000a6ac6587
>[13296.450443] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for CRTC state 000000002b48c403
>[13296.450461] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 00000000dbafe848 to [NOCRTC]
>[13296.450479] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for plane state 00000000dbafe848
>[13296.450497] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:47:pipe B] to 00000000a6ac6587
>[13296.450516] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:61:DP-2] 00000000409178cb state to 00000000a6ac6587
>[13296.450534] [drm:drm_atomic_set_crtc_for_connector [drm]] Link connector state 00000000409178cb to [NOCRTC]
>[13296.450552] [drm:drm_atomic_check_only [drm]] checking 00000000a6ac6587
>[13296.450567] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:47:pipe B] mode changed
>[13296.450578] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:47:pipe B] enable changed
>[13296.450587] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:47:pipe B] active changed
>[13296.450597] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:61:DP-2]
>[13296.450607] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Disabling [CONNECTOR:61:DP-2]
>[13296.450617] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:47:pipe B] needs all connectors, enable: n, active: n
>[13296.450636] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:47:pipe B] to 00000000a6ac6587
>[13296.450710] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[13296.450774] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[13296.450839] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:47:pipe B] has [PLANE:38:plane 1B] with fb -1
>[13296.450898] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:38:plane 1B] visible 1 -> 0, off 1, on 0, ms 1
>[13296.450927] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:37:pipe A] 00000000bd3c0152 state to 00000000a6ac6587
>[13296.450978] [drm:skl_compute_wm [i915]] [PLANE:38:plane 1B] ddb (0 - 860) -> (0 - 0)
>[13296.451025] [drm:skl_compute_wm [i915]] [PLANE:44:cursor B] ddb (860 - 892) -> (0 - 0)
>[13296.451049] [drm:drm_atomic_commit [drm]] committing 00000000a6ac6587
>[13296.451144] [drm:intel_disable_pipe [i915]] disabling pipe B
>[13296.467525] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well
>[13296.467597] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 2, on? 1) for crtc 47
>[13296.467658] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[13296.467731] [drm:intel_atomic_commit_tail [i915]] [ENCODER:48:DDI A]
>[13296.467786] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI B]
>[13296.467837] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[13296.467886] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[13296.467934] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DDI C]
>[13296.467982] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST A]
>[13296.468028] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST B]
>[13296.468074] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI D]
>[13296.468119] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[13296.468164] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[13296.468216] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:61:DP-2]
>[13296.468269] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[13296.468321] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[13296.468370] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[13296.468419] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[13296.468469] [drm:intel_power_well_disable [i915]] disabling power well 2
>[13296.468527] [drm:intel_atomic_commit_tail [i915]] [CRTC:47:pipe B]
>[13296.468561] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000a6ac6587
>[13296.468587] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000a6ac6587
>[13296.468831] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[13296.468859] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:61:DP-2]
>[13296.468885] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000a6ac6587
>[13296.468914] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:47:pipe B] 00000000604357f6 state to 00000000a6ac6587
>[13296.468937] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:38:plane 1B] 00000000c4c517e9 state to 00000000a6ac6587
>[13296.468962] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [MODE:1920x1200] for CRTC state 00000000604357f6
>[13296.468983] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 00000000c4c517e9 to [CRTC:47:pipe B]
>[13296.469005] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:99] for plane state 00000000c4c517e9
>[13296.469025] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:47:pipe B] to 00000000a6ac6587
>[13296.469048] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:61:DP-2] 0000000056bf571a state to 00000000a6ac6587
>[13296.469066] [drm:drm_atomic_set_crtc_for_connector [drm]] Link connector state 0000000056bf571a to [CRTC:47:pipe B]
>[13296.469087] [drm:drm_atomic_check_only [drm]] checking 00000000a6ac6587
>[13296.469103] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:47:pipe B] mode changed
>[13296.469115] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:47:pipe B] enable changed
>[13296.469127] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:47:pipe B] active changed
>[13296.469138] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:61:DP-2]
>[13296.469149] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:61:DP-2] using [ENCODER:60:DDI C] on [CRTC:47:pipe B]
>[13296.469162] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:47:pipe B] needs all connectors, enable: y, active: y
>[13296.469180] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:47:pipe B] to 00000000a6ac6587
>[13296.469202] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:47:pipe B] to 00000000a6ac6587
>[13296.469269] [drm:intel_atomic_check [i915]] [CONNECTOR:61:DP-2] checking for sink bpp constrains
>[13296.469331] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[13296.469396] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[13296.469470] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[13296.469525] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[13296.469586] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[13296.469645] [drm:intel_dump_pipe_config [i915]] [CRTC:47:pipe B][modeset]
>[13296.469701] [drm:intel_dump_pipe_config [i915]] output_types: DP (0x80)
>[13296.469753] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[13296.469806] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[13296.469855] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[13296.469904] [drm:intel_dump_pipe_config [i915]] requested mode:
>[13296.469933] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[13296.469983] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[13296.470010] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[13296.470064] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[13296.470114] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[13296.470164] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[13296.470212] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[13296.470261] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[13296.470308] [drm:intel_dump_pipe_config [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[13296.470355] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[13296.470402] [drm:intel_dump_pipe_config [i915]] [PLANE:38:plane 1B] disabled, scaler_id = -1
>[13296.470450] [drm:intel_dump_pipe_config [i915]] [PLANE:41:plane 2B] disabled, scaler_id = -1
>[13296.470497] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor B] disabled, scaler_id = -1
>[13296.470555] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[13296.470609] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[13296.470670] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:47:pipe B] has [PLANE:38:plane 1B] with fb 99
>[13296.470725] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:38:plane 1B] visible 0 -> 1, off 0, on 1, ms 1
>[13296.470784] [drm:intel_find_shared_dpll [i915]] [CRTC:47:pipe B] allocated DPLL 1
>[13296.470839] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[13296.470872] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:37:pipe A] 00000000c85dec7a state to 00000000a6ac6587
>[13296.470923] [drm:skl_compute_wm [i915]] [PLANE:38:plane 1B] ddb (0 - 0) -> (0 - 860)
>[13296.470966] [drm:skl_compute_wm [i915]] [PLANE:44:cursor B] ddb (0 - 0) -> (860 - 892)
>[13296.470995] [drm:drm_atomic_commit [drm]] committing 00000000a6ac6587
>[13297.469068] [drm:intel_power_well_enable [i915]] enabling power well 2
>[13297.469151] [drm:intel_atomic_commit_tail [i915]] [ENCODER:48:DDI A]
>[13297.469215] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI B]
>[13297.469273] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[13297.469326] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[13297.469378] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DDI C]
>[13297.469428] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST A]
>[13297.469479] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST B]
>[13297.469528] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI D]
>[13297.469577] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[13297.469625] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[13297.469680] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[13297.469736] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[13297.469790] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[13297.469842] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[13297.469905] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 2, on? 0) for crtc 47
>[13297.469961] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[13297.470103] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well
>[13297.471204] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[13297.471257] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[13297.471307] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[13297.471356] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[13297.471999] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 04000000
>[13297.472045] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[13297.472091] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[13297.472761] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[13297.472818] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[13297.473763] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[13297.474141] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:61:DP-2] Link Training Passed at Link Rate = 162000, Lane count = 4
>[13297.474643] [drm:intel_enable_pipe [i915]] enabling pipe B
>[13297.474730] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS
>[13297.491499] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:61:DP-2]
>[13297.491573] [drm:intel_atomic_commit_tail [i915]] [CRTC:47:pipe B]
>[13297.491651] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[13297.491689] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000a6ac6587
>[13297.491714] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000a6ac6587
>[13297.491772] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[13297.491797] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000a6ac6587
>[13297.491821] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:47:pipe B] 000000002b48c403 state to 00000000a6ac6587
>[13297.491842] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:38:plane 1B] 000000005906dec2 state to 00000000a6ac6587
>[13297.491862] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for CRTC state 000000002b48c403
>[13297.491880] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 000000005906dec2 to [NOCRTC]
>[13297.491898] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for plane state 000000005906dec2
>[13297.491916] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:47:pipe B] to 00000000a6ac6587
>[13297.491936] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:61:DP-2] 00000000572650ad state to 00000000a6ac6587
>[13297.491954] [drm:drm_atomic_set_crtc_for_connector [drm]] Link connector state 00000000572650ad to [NOCRTC]
>[13297.491971] [drm:drm_atomic_check_only [drm]] checking 00000000a6ac6587
>[13297.491987] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:47:pipe B] mode changed
>[13297.491998] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:47:pipe B] enable changed
>[13297.492007] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:47:pipe B] active changed
>[13297.492017] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:61:DP-2]
>[13297.492027] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Disabling [CONNECTOR:61:DP-2]
>[13297.492037] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:47:pipe B] needs all connectors, enable: n, active: n
>[13297.492056] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:47:pipe B] to 00000000a6ac6587
>[13297.492131] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[13297.492194] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[13297.492259] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:47:pipe B] has [PLANE:38:plane 1B] with fb -1
>[13297.492319] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:38:plane 1B] visible 1 -> 0, off 1, on 0, ms 1
>[13297.492348] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:37:pipe A] 00000000bd3c0152 state to 00000000a6ac6587
>[13297.492398] [drm:skl_compute_wm [i915]] [PLANE:38:plane 1B] ddb (0 - 860) -> (0 - 0)
>[13297.492443] [drm:skl_compute_wm [i915]] [PLANE:44:cursor B] ddb (860 - 892) -> (0 - 0)
>[13297.492467] [drm:drm_atomic_commit [drm]] committing 00000000a6ac6587
>[13297.492561] [drm:intel_disable_pipe [i915]] disabling pipe B
>[13297.508588] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well
>[13297.508659] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 2, on? 1) for crtc 47
>[13297.508721] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[13297.508825] [drm:intel_atomic_commit_tail [i915]] [ENCODER:48:DDI A]
>[13297.508891] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI B]
>[13297.508952] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[13297.509006] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[13297.509056] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DDI C]
>[13297.509107] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST A]
>[13297.509156] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST B]
>[13297.509204] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI D]
>[13297.509251] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[13297.509299] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[13297.509353] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:61:DP-2]
>[13297.509408] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[13297.509462] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[13297.509514] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[13297.509566] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[13297.509617] [drm:intel_power_well_disable [i915]] disabling power well 2
>[13297.509676] [drm:intel_atomic_commit_tail [i915]] [CRTC:47:pipe B]
>[13297.509712] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000a6ac6587
>[13297.509741] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000a6ac6587
>[13297.509953] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[13297.509980] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:61:DP-2]
>[13297.510005] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000a6ac6587
>[13297.510031] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:47:pipe B] 00000000604357f6 state to 00000000a6ac6587
>[13297.510053] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:38:plane 1B] 00000000dbafe848 state to 00000000a6ac6587
>[13297.510076] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [MODE:1920x1200] for CRTC state 00000000604357f6
>[13297.510094] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 00000000dbafe848 to [CRTC:47:pipe B]
>[13297.510115] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:98] for plane state 00000000dbafe848
>[13297.510133] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:47:pipe B] to 00000000a6ac6587
>[13297.510154] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:61:DP-2] 00000000409178cb state to 00000000a6ac6587
>[13297.510173] [drm:drm_atomic_set_crtc_for_connector [drm]] Link connector state 00000000409178cb to [CRTC:47:pipe B]
>[13297.510192] [drm:drm_atomic_check_only [drm]] checking 00000000a6ac6587
>[13297.510207] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:47:pipe B] mode changed
>[13297.510218] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:47:pipe B] enable changed
>[13297.510228] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:47:pipe B] active changed
>[13297.510240] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:61:DP-2]
>[13297.510250] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:61:DP-2] using [ENCODER:60:DDI C] on [CRTC:47:pipe B]
>[13297.510260] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:47:pipe B] needs all connectors, enable: y, active: y
>[13297.510279] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:47:pipe B] to 00000000a6ac6587
>[13297.510299] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:47:pipe B] to 00000000a6ac6587
>[13297.510365] [drm:intel_atomic_check [i915]] [CONNECTOR:61:DP-2] checking for sink bpp constrains
>[13297.510426] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[13297.510490] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[13297.510562] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[13297.510615] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[13297.510674] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[13297.510730] [drm:intel_dump_pipe_config [i915]] [CRTC:47:pipe B][modeset]
>[13297.510786] [drm:intel_dump_pipe_config [i915]] output_types: DP (0x80)
>[13297.510837] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[13297.510889] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[13297.510938] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[13297.510987] [drm:intel_dump_pipe_config [i915]] requested mode:
>[13297.511014] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[13297.511063] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[13297.511088] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[13297.511141] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[13297.511189] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[13297.511237] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[13297.511283] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[13297.511329] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[13297.511375] [drm:intel_dump_pipe_config [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[13297.511421] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[13297.511466] [drm:intel_dump_pipe_config [i915]] [PLANE:38:plane 1B] disabled, scaler_id = -1
>[13297.511511] [drm:intel_dump_pipe_config [i915]] [PLANE:41:plane 2B] disabled, scaler_id = -1
>[13297.511555] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor B] disabled, scaler_id = -1
>[13297.511612] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[13297.511664] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[13297.511722] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:47:pipe B] has [PLANE:38:plane 1B] with fb 98
>[13297.511774] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:38:plane 1B] visible 0 -> 1, off 0, on 1, ms 1
>[13297.511832] [drm:intel_find_shared_dpll [i915]] [CRTC:47:pipe B] allocated DPLL 1
>[13297.511885] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[13297.511917] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:37:pipe A] 00000000c85dec7a state to 00000000a6ac6587
>[13297.511965] [drm:skl_compute_wm [i915]] [PLANE:38:plane 1B] ddb (0 - 0) -> (0 - 860)
>[13297.512007] [drm:skl_compute_wm [i915]] [PLANE:44:cursor B] ddb (0 - 0) -> (860 - 892)
>[13297.512033] [drm:drm_atomic_commit [drm]] committing 00000000a6ac6587
>[13298.510189] [drm:intel_power_well_enable [i915]] enabling power well 2
>[13298.510273] [drm:intel_atomic_commit_tail [i915]] [ENCODER:48:DDI A]
>[13298.510336] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI B]
>[13298.510393] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[13298.510448] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[13298.510500] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DDI C]
>[13298.510550] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST A]
>[13298.510599] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST B]
>[13298.510648] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI D]
>[13298.510696] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[13298.510743] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[13298.510798] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[13298.510854] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[13298.510907] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[13298.510960] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[13298.511023] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 2, on? 0) for crtc 47
>[13298.511079] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[13298.511220] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well
>[13298.512321] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[13298.512374] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[13298.512423] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[13298.512473] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[13298.513118] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[13298.513169] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[13298.514109] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[13298.514487] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:61:DP-2] Link Training Passed at Link Rate = 162000, Lane count = 4
>[13298.514990] [drm:intel_enable_pipe [i915]] enabling pipe B
>[13298.515077] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS
>[13298.531848] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:61:DP-2]
>[13298.531922] [drm:intel_atomic_commit_tail [i915]] [CRTC:47:pipe B]
>[13298.532002] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[13298.532039] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000a6ac6587
>[13298.532065] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000a6ac6587
>[13298.532123] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[13298.532148] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000a6ac6587
>[13298.532173] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:47:pipe B] 000000002b48c403 state to 00000000a6ac6587
>[13298.532193] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:38:plane 1B] 00000000c4c517e9 state to 00000000a6ac6587
>[13298.532214] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for CRTC state 000000002b48c403
>[13298.532232] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 00000000c4c517e9 to [NOCRTC]
>[13298.532251] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for plane state 00000000c4c517e9
>[13298.532269] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:47:pipe B] to 00000000a6ac6587
>[13298.532288] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:61:DP-2] 00000000d1e5643f state to 00000000a6ac6587
>[13298.532306] [drm:drm_atomic_set_crtc_for_connector [drm]] Link connector state 00000000d1e5643f to [NOCRTC]
>[13298.532323] [drm:drm_atomic_check_only [drm]] checking 00000000a6ac6587
>[13298.532339] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:47:pipe B] mode changed
>[13298.532349] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:47:pipe B] enable changed
>[13298.532359] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:47:pipe B] active changed
>[13298.532369] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:61:DP-2]
>[13298.532378] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Disabling [CONNECTOR:61:DP-2]
>[13298.532388] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:47:pipe B] needs all connectors, enable: n, active: n
>[13298.532407] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:47:pipe B] to 00000000a6ac6587
>[13298.532482] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[13298.532546] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[13298.532611] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:47:pipe B] has [PLANE:38:plane 1B] with fb -1
>[13298.532671] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:38:plane 1B] visible 1 -> 0, off 1, on 0, ms 1
>[13298.532734] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:37:pipe A] 00000000bd3c0152 state to 00000000a6ac6587
>[13298.532789] [drm:skl_compute_wm [i915]] [PLANE:38:plane 1B] ddb (0 - 860) -> (0 - 0)
>[13298.532845] [drm:skl_compute_wm [i915]] [PLANE:44:cursor B] ddb (860 - 892) -> (0 - 0)
>[13298.532877] [drm:drm_atomic_commit [drm]] committing 00000000a6ac6587
>[13298.532976] [drm:intel_disable_pipe [i915]] disabling pipe B
>[13298.549571] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well
>[13298.549643] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 2, on? 1) for crtc 47
>[13298.549704] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[13298.549777] [drm:intel_atomic_commit_tail [i915]] [ENCODER:48:DDI A]
>[13298.549832] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI B]
>[13298.549883] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[13298.549931] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[13298.549978] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DDI C]
>[13298.550027] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST A]
>[13298.550073] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST B]
>[13298.550119] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI D]
>[13298.550164] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[13298.550209] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[13298.550262] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:61:DP-2]
>[13298.550314] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[13298.550365] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[13298.550415] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[13298.550463] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[13298.550512] [drm:intel_power_well_disable [i915]] disabling power well 2
>[13298.550569] [drm:intel_atomic_commit_tail [i915]] [CRTC:47:pipe B]
>[13298.550603] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000a6ac6587
>[13298.550630] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000a6ac6587
>[13298.550839] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[13298.550864] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:61:DP-2]
>[13298.550889] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000a6ac6587
>[13298.550913] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:47:pipe B] 00000000604357f6 state to 00000000a6ac6587
>[13298.550935] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:38:plane 1B] 000000005906dec2 state to 00000000a6ac6587
>[13298.550957] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [MODE:1920x1200] for CRTC state 00000000604357f6
>[13298.550977] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 000000005906dec2 to [CRTC:47:pipe B]
>[13298.550996] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:99] for plane state 000000005906dec2
>[13298.551015] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:47:pipe B] to 00000000a6ac6587
>[13298.551035] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:61:DP-2] 00000000572650ad state to 00000000a6ac6587
>[13298.551052] [drm:drm_atomic_set_crtc_for_connector [drm]] Link connector state 00000000572650ad to [CRTC:47:pipe B]
>[13298.551071] [drm:drm_atomic_check_only [drm]] checking 00000000a6ac6587
>[13298.551085] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:47:pipe B] mode changed
>[13298.551095] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:47:pipe B] enable changed
>[13298.551103] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:47:pipe B] active changed
>[13298.551114] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:61:DP-2]
>[13298.551124] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:61:DP-2] using [ENCODER:60:DDI C] on [CRTC:47:pipe B]
>[13298.551134] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:47:pipe B] needs all connectors, enable: y, active: y
>[13298.551151] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:47:pipe B] to 00000000a6ac6587
>[13298.551171] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:47:pipe B] to 00000000a6ac6587
>[13298.551236] [drm:intel_atomic_check [i915]] [CONNECTOR:61:DP-2] checking for sink bpp constrains
>[13298.551295] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[13298.551357] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[13298.551429] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[13298.551482] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[13298.551540] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[13298.551597] [drm:intel_dump_pipe_config [i915]] [CRTC:47:pipe B][modeset]
>[13298.551649] [drm:intel_dump_pipe_config [i915]] output_types: DP (0x80)
>[13298.551699] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[13298.551750] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[13298.551798] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[13298.551844] [drm:intel_dump_pipe_config [i915]] requested mode:
>[13298.551871] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[13298.551919] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[13298.551944] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[13298.551995] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[13298.552043] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[13298.552090] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[13298.552136] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[13298.552181] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[13298.552227] [drm:intel_dump_pipe_config [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[13298.552271] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[13298.552316] [drm:intel_dump_pipe_config [i915]] [PLANE:38:plane 1B] disabled, scaler_id = -1
>[13298.552361] [drm:intel_dump_pipe_config [i915]] [PLANE:41:plane 2B] disabled, scaler_id = -1
>[13298.552405] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor B] disabled, scaler_id = -1
>[13298.552462] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[13298.552513] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[13298.552570] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:47:pipe B] has [PLANE:38:plane 1B] with fb 99
>[13298.552622] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:38:plane 1B] visible 0 -> 1, off 0, on 1, ms 1
>[13298.552678] [drm:intel_find_shared_dpll [i915]] [CRTC:47:pipe B] allocated DPLL 1
>[13298.552766] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[13298.552809] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:37:pipe A] 00000000c85dec7a state to 00000000a6ac6587
>[13298.552868] [drm:skl_compute_wm [i915]] [PLANE:38:plane 1B] ddb (0 - 0) -> (0 - 860)
>[13298.552916] [drm:skl_compute_wm [i915]] [PLANE:44:cursor B] ddb (0 - 0) -> (860 - 892)
>[13298.552949] [drm:drm_atomic_commit [drm]] committing 00000000a6ac6587
>[13299.551062] [drm:intel_power_well_enable [i915]] enabling power well 2
>[13299.551145] [drm:intel_atomic_commit_tail [i915]] [ENCODER:48:DDI A]
>[13299.551210] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI B]
>[13299.551268] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[13299.551323] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[13299.551375] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DDI C]
>[13299.551426] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST A]
>[13299.551476] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST B]
>[13299.551525] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI D]
>[13299.551574] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[13299.551622] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[13299.551678] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[13299.551734] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[13299.551787] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[13299.551839] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[13299.551901] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 2, on? 0) for crtc 47
>[13299.551957] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[13299.552098] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well
>[13299.553204] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[13299.553258] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[13299.553308] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[13299.553357] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[13299.554002] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[13299.554051] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[13299.554989] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[13299.555367] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:61:DP-2] Link Training Passed at Link Rate = 162000, Lane count = 4
>[13299.555870] [drm:intel_enable_pipe [i915]] enabling pipe B
>[13299.555958] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS
>[13299.572727] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:61:DP-2]
>[13299.572819] [drm:intel_atomic_commit_tail [i915]] [CRTC:47:pipe B]
>[13299.572898] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[13299.572936] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000a6ac6587
>[13299.572962] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000a6ac6587
>[13299.573021] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[13299.573045] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000a6ac6587
>[13299.573069] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:47:pipe B] 000000002b48c403 state to 00000000a6ac6587
>[13299.573090] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:38:plane 1B] 00000000dbafe848 state to 00000000a6ac6587
>[13299.573111] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for CRTC state 000000002b48c403
>[13299.573129] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 00000000dbafe848 to [NOCRTC]
>[13299.573148] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for plane state 00000000dbafe848
>[13299.573167] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:47:pipe B] to 00000000a6ac6587
>[13299.573187] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:61:DP-2] 0000000056bf571a state to 00000000a6ac6587
>[13299.573205] [drm:drm_atomic_set_crtc_for_connector [drm]] Link connector state 0000000056bf571a to [NOCRTC]
>[13299.573223] [drm:drm_atomic_check_only [drm]] checking 00000000a6ac6587
>[13299.573238] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:47:pipe B] mode changed
>[13299.573249] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:47:pipe B] enable changed
>[13299.573258] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:47:pipe B] active changed
>[13299.573267] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:61:DP-2]
>[13299.573277] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Disabling [CONNECTOR:61:DP-2]
>[13299.573287] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:47:pipe B] needs all connectors, enable: n, active: n
>[13299.573306] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:47:pipe B] to 00000000a6ac6587
>[13299.573380] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[13299.573444] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[13299.573510] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:47:pipe B] has [PLANE:38:plane 1B] with fb -1
>[13299.573569] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:38:plane 1B] visible 1 -> 0, off 1, on 0, ms 1
>[13299.573597] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:37:pipe A] 00000000bd3c0152 state to 00000000a6ac6587
>[13299.573647] [drm:skl_compute_wm [i915]] [PLANE:38:plane 1B] ddb (0 - 860) -> (0 - 0)
>[13299.573694] [drm:skl_compute_wm [i915]] [PLANE:44:cursor B] ddb (860 - 892) -> (0 - 0)
>[13299.573717] [drm:drm_atomic_commit [drm]] committing 00000000a6ac6587
>[13299.573811] [drm:intel_disable_pipe [i915]] disabling pipe B
>[13299.591544] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well
>[13299.591615] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 2, on? 1) for crtc 47
>[13299.591677] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[13299.591751] [drm:intel_atomic_commit_tail [i915]] [ENCODER:48:DDI A]
>[13299.591807] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI B]
>[13299.591859] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[13299.591907] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[13299.591955] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DDI C]
>[13299.592004] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST A]
>[13299.592050] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST B]
>[13299.592095] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI D]
>[13299.592141] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[13299.592186] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[13299.592238] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:61:DP-2]
>[13299.592290] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[13299.592341] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[13299.592390] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[13299.592437] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[13299.592487] [drm:intel_power_well_disable [i915]] disabling power well 2
>[13299.592543] [drm:intel_atomic_commit_tail [i915]] [CRTC:47:pipe B]
>[13299.592577] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000a6ac6587
>[13299.592604] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000a6ac6587
>[13299.592846] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[13299.592875] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:61:DP-2]
>[13299.592902] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000a6ac6587
>[13299.592930] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:47:pipe B] 00000000604357f6 state to 00000000a6ac6587
>[13299.592953] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:38:plane 1B] 00000000c4c517e9 state to 00000000a6ac6587
>[13299.592979] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [MODE:1920x1200] for CRTC state 00000000604357f6
>[13299.592999] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 00000000c4c517e9 to [CRTC:47:pipe B]
>[13299.593021] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:98] for plane state 00000000c4c517e9
>[13299.593040] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:47:pipe B] to 00000000a6ac6587
>[13299.593061] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:61:DP-2] 00000000d1e5643f state to 00000000a6ac6587
>[13299.593080] [drm:drm_atomic_set_crtc_for_connector [drm]] Link connector state 00000000d1e5643f to [CRTC:47:pipe B]
>[13299.593100] [drm:drm_atomic_check_only [drm]] checking 00000000a6ac6587
>[13299.593117] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:47:pipe B] mode changed
>[13299.593128] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:47:pipe B] enable changed
>[13299.593137] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:47:pipe B] active changed
>[13299.593150] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:61:DP-2]
>[13299.593161] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:61:DP-2] using [ENCODER:60:DDI C] on [CRTC:47:pipe B]
>[13299.593173] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:47:pipe B] needs all connectors, enable: y, active: y
>[13299.593191] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:47:pipe B] to 00000000a6ac6587
>[13299.593212] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:47:pipe B] to 00000000a6ac6587
>[13299.593278] [drm:intel_atomic_check [i915]] [CONNECTOR:61:DP-2] checking for sink bpp constrains
>[13299.593340] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[13299.593405] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[13299.593478] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[13299.593533] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[13299.593594] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[13299.593653] [drm:intel_dump_pipe_config [i915]] [CRTC:47:pipe B][modeset]
>[13299.593708] [drm:intel_dump_pipe_config [i915]] output_types: DP (0x80)
>[13299.593759] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[13299.593813] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[13299.593863] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[13299.593913] [drm:intel_dump_pipe_config [i915]] requested mode:
>[13299.593941] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[13299.593991] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[13299.594018] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[13299.594071] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[13299.594120] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[13299.594169] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[13299.594218] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[13299.594266] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[13299.594313] [drm:intel_dump_pipe_config [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[13299.594360] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[13299.594406] [drm:intel_dump_pipe_config [i915]] [PLANE:38:plane 1B] disabled, scaler_id = -1
>[13299.594453] [drm:intel_dump_pipe_config [i915]] [PLANE:41:plane 2B] disabled, scaler_id = -1
>[13299.594499] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor B] disabled, scaler_id = -1
>[13299.594557] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[13299.594609] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[13299.594668] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:47:pipe B] has [PLANE:38:plane 1B] with fb 98
>[13299.594721] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:38:plane 1B] visible 0 -> 1, off 0, on 1, ms 1
>[13299.594779] [drm:intel_find_shared_dpll [i915]] [CRTC:47:pipe B] allocated DPLL 1
>[13299.594833] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[13299.594866] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:37:pipe A] 00000000c85dec7a state to 00000000a6ac6587
>[13299.594915] [drm:skl_compute_wm [i915]] [PLANE:38:plane 1B] ddb (0 - 0) -> (0 - 860)
>[13299.594959] [drm:skl_compute_wm [i915]] [PLANE:44:cursor B] ddb (0 - 0) -> (860 - 892)
>[13299.594986] [drm:drm_atomic_commit [drm]] committing 00000000a6ac6587
>[13300.593077] [drm:intel_power_well_enable [i915]] enabling power well 2
>[13300.593160] [drm:intel_atomic_commit_tail [i915]] [ENCODER:48:DDI A]
>[13300.593223] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI B]
>[13300.593279] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[13300.593333] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[13300.593385] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DDI C]
>[13300.593435] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST A]
>[13300.593484] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST B]
>[13300.593534] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI D]
>[13300.593582] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[13300.593630] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[13300.593685] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[13300.593741] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[13300.593795] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[13300.593847] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[13300.593910] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 2, on? 0) for crtc 47
>[13300.593966] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[13300.594108] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well
>[13300.595211] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[13300.595265] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[13300.595314] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[13300.595363] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[13300.596003] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 04000000
>[13300.596049] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[13300.596094] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[13300.596761] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[13300.596818] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[13300.597761] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[13300.598137] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:61:DP-2] Link Training Passed at Link Rate = 162000, Lane count = 4
>[13300.598640] [drm:intel_enable_pipe [i915]] enabling pipe B
>[13300.598728] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS
>[13300.615497] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:61:DP-2]
>[13300.615571] [drm:intel_atomic_commit_tail [i915]] [CRTC:47:pipe B]
>[13300.615649] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[13300.615687] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000a6ac6587
>[13300.615713] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000a6ac6587
>[13300.615771] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[13300.615795] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000a6ac6587
>[13300.615820] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:47:pipe B] 000000002b48c403 state to 00000000a6ac6587
>[13300.615841] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:38:plane 1B] 000000005906dec2 state to 00000000a6ac6587
>[13300.615862] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for CRTC state 000000002b48c403
>[13300.615880] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 000000005906dec2 to [NOCRTC]
>[13300.615899] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for plane state 000000005906dec2
>[13300.615917] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:47:pipe B] to 00000000a6ac6587
>[13300.615936] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:61:DP-2] 00000000409178cb state to 00000000a6ac6587
>[13300.615954] [drm:drm_atomic_set_crtc_for_connector [drm]] Link connector state 00000000409178cb to [NOCRTC]
>[13300.615971] [drm:drm_atomic_check_only [drm]] checking 00000000a6ac6587
>[13300.615986] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:47:pipe B] mode changed
>[13300.615997] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:47:pipe B] enable changed
>[13300.616006] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:47:pipe B] active changed
>[13300.616016] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:61:DP-2]
>[13300.616025] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Disabling [CONNECTOR:61:DP-2]
>[13300.616035] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:47:pipe B] needs all connectors, enable: n, active: n
>[13300.616055] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:47:pipe B] to 00000000a6ac6587
>[13300.616129] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[13300.616193] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[13300.616259] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:47:pipe B] has [PLANE:38:plane 1B] with fb -1
>[13300.616318] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:38:plane 1B] visible 1 -> 0, off 1, on 0, ms 1
>[13300.616347] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:37:pipe A] 00000000bd3c0152 state to 00000000a6ac6587
>[13300.616398] [drm:skl_compute_wm [i915]] [PLANE:38:plane 1B] ddb (0 - 860) -> (0 - 0)
>[13300.616443] [drm:skl_compute_wm [i915]] [PLANE:44:cursor B] ddb (860 - 892) -> (0 - 0)
>[13300.616467] [drm:drm_atomic_commit [drm]] committing 00000000a6ac6587
>[13300.616561] [drm:intel_disable_pipe [i915]] disabling pipe B
>[13300.632587] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well
>[13300.632659] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 2, on? 1) for crtc 47
>[13300.632721] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[13300.632826] [drm:intel_atomic_commit_tail [i915]] [ENCODER:48:DDI A]
>[13300.632892] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI B]
>[13300.632955] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[13300.633009] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[13300.633060] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DDI C]
>[13300.633112] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST A]
>[13300.633161] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST B]
>[13300.633210] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI D]
>[13300.633260] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[13300.633308] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[13300.633364] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:61:DP-2]
>[13300.633419] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[13300.633474] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[13300.633527] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[13300.633579] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[13300.633630] [drm:intel_power_well_disable [i915]] disabling power well 2
>[13300.633690] [drm:intel_atomic_commit_tail [i915]] [CRTC:47:pipe B]
>[13300.633725] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000a6ac6587
>[13300.633753] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000a6ac6587
>[13300.633960] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[13300.633986] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:61:DP-2]
>[13300.634011] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000a6ac6587
>[13300.634037] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:47:pipe B] 00000000604357f6 state to 00000000a6ac6587
>[13300.634059] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:38:plane 1B] 00000000dbafe848 state to 00000000a6ac6587
>[13300.634082] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [MODE:1920x1200] for CRTC state 00000000604357f6
>[13300.634100] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 00000000dbafe848 to [CRTC:47:pipe B]
>[13300.634120] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:99] for plane state 00000000dbafe848
>[13300.634138] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:47:pipe B] to 00000000a6ac6587
>[13300.634158] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:61:DP-2] 0000000056bf571a state to 00000000a6ac6587
>[13300.634176] [drm:drm_atomic_set_crtc_for_connector [drm]] Link connector state 0000000056bf571a to [CRTC:47:pipe B]
>[13300.634195] [drm:drm_atomic_check_only [drm]] checking 00000000a6ac6587
>[13300.634210] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:47:pipe B] mode changed
>[13300.634221] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:47:pipe B] enable changed
>[13300.634230] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:47:pipe B] active changed
>[13300.634241] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:61:DP-2]
>[13300.634252] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:61:DP-2] using [ENCODER:60:DDI C] on [CRTC:47:pipe B]
>[13300.634262] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:47:pipe B] needs all connectors, enable: y, active: y
>[13300.634280] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:47:pipe B] to 00000000a6ac6587
>[13300.634300] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:47:pipe B] to 00000000a6ac6587
>[13300.634365] [drm:intel_atomic_check [i915]] [CONNECTOR:61:DP-2] checking for sink bpp constrains
>[13300.634426] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[13300.634489] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[13300.634562] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[13300.634616] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[13300.634675] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[13300.634732] [drm:intel_dump_pipe_config [i915]] [CRTC:47:pipe B][modeset]
>[13300.634787] [drm:intel_dump_pipe_config [i915]] output_types: DP (0x80)
>[13300.634838] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[13300.634890] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[13300.634938] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[13300.634986] [drm:intel_dump_pipe_config [i915]] requested mode:
>[13300.635013] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[13300.635063] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[13300.635088] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[13300.635141] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[13300.635189] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[13300.635238] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[13300.635285] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[13300.635331] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[13300.635378] [drm:intel_dump_pipe_config [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[13300.635424] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[13300.635470] [drm:intel_dump_pipe_config [i915]] [PLANE:38:plane 1B] disabled, scaler_id = -1
>[13300.635515] [drm:intel_dump_pipe_config [i915]] [PLANE:41:plane 2B] disabled, scaler_id = -1
>[13300.635560] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor B] disabled, scaler_id = -1
>[13300.635618] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[13300.635670] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[13300.635729] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:47:pipe B] has [PLANE:38:plane 1B] with fb 99
>[13300.635780] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:38:plane 1B] visible 0 -> 1, off 0, on 1, ms 1
>[13300.635838] [drm:intel_find_shared_dpll [i915]] [CRTC:47:pipe B] allocated DPLL 1
>[13300.635891] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[13300.635923] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:37:pipe A] 00000000c85dec7a state to 00000000a6ac6587
>[13300.635972] [drm:skl_compute_wm [i915]] [PLANE:38:plane 1B] ddb (0 - 0) -> (0 - 860)
>[13300.636014] [drm:skl_compute_wm [i915]] [PLANE:44:cursor B] ddb (0 - 0) -> (860 - 892)
>[13300.636040] [drm:drm_atomic_commit [drm]] committing 00000000a6ac6587
>[13301.634191] [drm:intel_power_well_enable [i915]] enabling power well 2
>[13301.634274] [drm:intel_atomic_commit_tail [i915]] [ENCODER:48:DDI A]
>[13301.634339] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI B]
>[13301.634397] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[13301.634451] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[13301.634503] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DDI C]
>[13301.634554] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST A]
>[13301.634603] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST B]
>[13301.634653] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI D]
>[13301.634701] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[13301.634750] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[13301.634805] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[13301.634861] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[13301.634914] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[13301.634966] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[13301.635029] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 2, on? 0) for crtc 47
>[13301.635086] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[13301.635227] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well
>[13301.636329] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[13301.636382] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[13301.636431] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[13301.636480] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[13301.637124] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[13301.637176] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[13301.638116] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[13301.638494] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:61:DP-2] Link Training Passed at Link Rate = 162000, Lane count = 4
>[13301.638998] [drm:intel_enable_pipe [i915]] enabling pipe B
>[13301.639084] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS
>[13301.655856] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:61:DP-2]
>[13301.655929] [drm:intel_atomic_commit_tail [i915]] [CRTC:47:pipe B]
>[13301.656007] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[13301.656044] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000a6ac6587
>[13301.656071] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000a6ac6587
>[13301.656129] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[13301.656154] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000a6ac6587
>[13301.656178] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:47:pipe B] 000000002b48c403 state to 00000000a6ac6587
>[13301.656199] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:38:plane 1B] 00000000c4c517e9 state to 00000000a6ac6587
>[13301.656220] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for CRTC state 000000002b48c403
>[13301.656239] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 00000000c4c517e9 to [NOCRTC]
>[13301.656257] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for plane state 00000000c4c517e9
>[13301.656275] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:47:pipe B] to 00000000a6ac6587
>[13301.656295] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:61:DP-2] 000000005a636f37 state to 00000000a6ac6587
>[13301.656313] [drm:drm_atomic_set_crtc_for_connector [drm]] Link connector state 000000005a636f37 to [NOCRTC]
>[13301.656330] [drm:drm_atomic_check_only [drm]] checking 00000000a6ac6587
>[13301.656346] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:47:pipe B] mode changed
>[13301.656356] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:47:pipe B] enable changed
>[13301.656365] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:47:pipe B] active changed
>[13301.656375] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:61:DP-2]
>[13301.656384] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Disabling [CONNECTOR:61:DP-2]
>[13301.656394] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:47:pipe B] needs all connectors, enable: n, active: n
>[13301.656412] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:47:pipe B] to 00000000a6ac6587
>[13301.656486] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[13301.656551] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[13301.656616] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:47:pipe B] has [PLANE:38:plane 1B] with fb -1
>[13301.656676] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:38:plane 1B] visible 1 -> 0, off 1, on 0, ms 1
>[13301.656739] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:37:pipe A] 00000000bd3c0152 state to 00000000a6ac6587
>[13301.656791] [drm:skl_compute_wm [i915]] [PLANE:38:plane 1B] ddb (0 - 860) -> (0 - 0)
>[13301.656846] [drm:skl_compute_wm [i915]] [PLANE:44:cursor B] ddb (860 - 892) -> (0 - 0)
>[13301.656880] [drm:drm_atomic_commit [drm]] committing 00000000a6ac6587
>[13301.656978] [drm:intel_disable_pipe [i915]] disabling pipe B
>[13301.674154] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well
>[13301.674225] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 2, on? 1) for crtc 47
>[13301.674285] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[13301.674358] [drm:intel_atomic_commit_tail [i915]] [ENCODER:48:DDI A]
>[13301.674413] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI B]
>[13301.674464] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[13301.674512] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[13301.674560] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DDI C]
>[13301.674609] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST A]
>[13301.674656] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST B]
>[13301.674702] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI D]
>[13301.674747] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[13301.674793] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[13301.674845] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:61:DP-2]
>[13301.674897] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[13301.674948] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[13301.674998] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[13301.675046] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[13301.675095] [drm:intel_power_well_disable [i915]] disabling power well 2
>[13301.675152] [drm:intel_atomic_commit_tail [i915]] [CRTC:47:pipe B]
>[13301.675186] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000a6ac6587
>[13301.675213] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000a6ac6587
>[13301.675446] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[13301.675472] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:61:DP-2]
>[13301.675497] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000a6ac6587
>[13301.675522] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:47:pipe B] 00000000604357f6 state to 00000000a6ac6587
>[13301.675544] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:38:plane 1B] 000000005906dec2 state to 00000000a6ac6587
>[13301.675566] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [MODE:1920x1200] for CRTC state 00000000604357f6
>[13301.675586] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 000000005906dec2 to [CRTC:47:pipe B]
>[13301.675605] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:98] for plane state 000000005906dec2
>[13301.675623] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:47:pipe B] to 00000000a6ac6587
>[13301.675643] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:61:DP-2] 00000000409178cb state to 00000000a6ac6587
>[13301.675659] [drm:drm_atomic_set_crtc_for_connector [drm]] Link connector state 00000000409178cb to [CRTC:47:pipe B]
>[13301.675678] [drm:drm_atomic_check_only [drm]] checking 00000000a6ac6587
>[13301.675693] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:47:pipe B] mode changed
>[13301.675703] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:47:pipe B] enable changed
>[13301.675711] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:47:pipe B] active changed
>[13301.675722] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:61:DP-2]
>[13301.675732] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:61:DP-2] using [ENCODER:60:DDI C] on [CRTC:47:pipe B]
>[13301.675742] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:47:pipe B] needs all connectors, enable: y, active: y
>[13301.675760] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:47:pipe B] to 00000000a6ac6587
>[13301.675779] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:47:pipe B] to 00000000a6ac6587
>[13301.675843] [drm:intel_atomic_check [i915]] [CONNECTOR:61:DP-2] checking for sink bpp constrains
>[13301.675903] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[13301.675965] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[13301.676037] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[13301.676091] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[13301.676148] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[13301.676204] [drm:intel_dump_pipe_config [i915]] [CRTC:47:pipe B][modeset]
>[13301.676257] [drm:intel_dump_pipe_config [i915]] output_types: DP (0x80)
>[13301.676307] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[13301.676357] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[13301.676405] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[13301.676451] [drm:intel_dump_pipe_config [i915]] requested mode:
>[13301.676478] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[13301.676525] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[13301.676550] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[13301.676601] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[13301.676648] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[13301.676694] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[13301.676774] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[13301.676831] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[13301.676886] [drm:intel_dump_pipe_config [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[13301.676935] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[13301.676987] [drm:intel_dump_pipe_config [i915]] [PLANE:38:plane 1B] disabled, scaler_id = -1
>[13301.677038] [drm:intel_dump_pipe_config [i915]] [PLANE:41:plane 2B] disabled, scaler_id = -1
>[13301.677089] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor B] disabled, scaler_id = -1
>[13301.677150] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[13301.677208] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[13301.677270] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:47:pipe B] has [PLANE:38:plane 1B] with fb 98
>[13301.677328] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:38:plane 1B] visible 0 -> 1, off 0, on 1, ms 1
>[13301.677391] [drm:intel_find_shared_dpll [i915]] [CRTC:47:pipe B] allocated DPLL 1
>[13301.677449] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[13301.677486] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:37:pipe A] 00000000c85dec7a state to 00000000a6ac6587
>[13301.677541] [drm:skl_compute_wm [i915]] [PLANE:38:plane 1B] ddb (0 - 0) -> (0 - 860)
>[13301.677589] [drm:skl_compute_wm [i915]] [PLANE:44:cursor B] ddb (0 - 0) -> (860 - 892)
>[13301.677620] [drm:drm_atomic_commit [drm]] committing 00000000a6ac6587
>[13302.675678] [drm:intel_power_well_enable [i915]] enabling power well 2
>[13302.675761] [drm:intel_atomic_commit_tail [i915]] [ENCODER:48:DDI A]
>[13302.675825] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI B]
>[13302.675882] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[13302.675936] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[13302.675988] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DDI C]
>[13302.676038] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST A]
>[13302.676088] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST B]
>[13302.676137] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI D]
>[13302.676186] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[13302.676234] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[13302.676290] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[13302.676347] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[13302.676401] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[13302.676452] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[13302.676515] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 2, on? 0) for crtc 47
>[13302.676571] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[13302.676714] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well
>[13302.677870] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[13302.677924] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[13302.677974] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[13302.678022] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[13302.678666] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[13302.678714] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[13302.679651] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[13302.680029] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:61:DP-2] Link Training Passed at Link Rate = 162000, Lane count = 4
>[13302.680532] [drm:intel_enable_pipe [i915]] enabling pipe B
>[13302.680619] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS
>[13302.697383] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:61:DP-2]
>[13302.697457] [drm:intel_atomic_commit_tail [i915]] [CRTC:47:pipe B]
>[13302.697536] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[13302.697574] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000a6ac6587
>[13302.697600] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000a6ac6587
>[13302.697658] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[13302.697682] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000a6ac6587
>[13302.697707] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:47:pipe B] 000000002b48c403 state to 00000000a6ac6587
>[13302.697728] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:38:plane 1B] 00000000dbafe848 state to 00000000a6ac6587
>[13302.697748] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for CRTC state 000000002b48c403
>[13302.697767] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 00000000dbafe848 to [NOCRTC]
>[13302.697785] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for plane state 00000000dbafe848
>[13302.697803] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:47:pipe B] to 00000000a6ac6587
>[13302.697822] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:61:DP-2] 00000000d1e5643f state to 00000000a6ac6587
>[13302.697840] [drm:drm_atomic_set_crtc_for_connector [drm]] Link connector state 00000000d1e5643f to [NOCRTC]
>[13302.697857] [drm:drm_atomic_check_only [drm]] checking 00000000a6ac6587
>[13302.697873] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:47:pipe B] mode changed
>[13302.697883] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:47:pipe B] enable changed
>[13302.697893] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:47:pipe B] active changed
>[13302.697903] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:61:DP-2]
>[13302.697912] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Disabling [CONNECTOR:61:DP-2]
>[13302.697922] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:47:pipe B] needs all connectors, enable: n, active: n
>[13302.697941] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:47:pipe B] to 00000000a6ac6587
>[13302.698016] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[13302.698079] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[13302.698146] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:47:pipe B] has [PLANE:38:plane 1B] with fb -1
>[13302.698204] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:38:plane 1B] visible 1 -> 0, off 1, on 0, ms 1
>[13302.698234] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:37:pipe A] 00000000bd3c0152 state to 00000000a6ac6587
>[13302.698284] [drm:skl_compute_wm [i915]] [PLANE:38:plane 1B] ddb (0 - 860) -> (0 - 0)
>[13302.698330] [drm:skl_compute_wm [i915]] [PLANE:44:cursor B] ddb (860 - 892) -> (0 - 0)
>[13302.698353] [drm:drm_atomic_commit [drm]] committing 00000000a6ac6587
>[13302.698448] [drm:intel_disable_pipe [i915]] disabling pipe B
>[13302.716657] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well
>[13302.716742] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 2, on? 1) for crtc 47
>[13302.716848] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[13302.716929] [drm:intel_atomic_commit_tail [i915]] [ENCODER:48:DDI A]
>[13302.716990] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI B]
>[13302.717044] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[13302.717096] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[13302.717145] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DDI C]
>[13302.717196] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST A]
>[13302.717243] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST B]
>[13302.717291] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI D]
>[13302.717338] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[13302.717385] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[13302.717438] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:61:DP-2]
>[13302.717493] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[13302.717546] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[13302.717598] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[13302.717648] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[13302.717700] [drm:intel_power_well_disable [i915]] disabling power well 2
>[13302.717759] [drm:intel_atomic_commit_tail [i915]] [CRTC:47:pipe B]
>[13302.717795] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000a6ac6587
>[13302.717823] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000a6ac6587
>[13302.718034] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[13302.718060] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:61:DP-2]
>[13302.718084] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000a6ac6587
>[13302.718109] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:47:pipe B] 00000000604357f6 state to 00000000a6ac6587
>[13302.718131] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:38:plane 1B] 00000000c4c517e9 state to 00000000a6ac6587
>[13302.718154] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [MODE:1920x1200] for CRTC state 00000000604357f6
>[13302.718173] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 00000000c4c517e9 to [CRTC:47:pipe B]
>[13302.718193] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:99] for plane state 00000000c4c517e9
>[13302.718211] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:47:pipe B] to 00000000a6ac6587
>[13302.718231] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:61:DP-2] 000000005a636f37 state to 00000000a6ac6587
>[13302.718249] [drm:drm_atomic_set_crtc_for_connector [drm]] Link connector state 000000005a636f37 to [CRTC:47:pipe B]
>[13302.718267] [drm:drm_atomic_check_only [drm]] checking 00000000a6ac6587
>[13302.718283] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:47:pipe B] mode changed
>[13302.718294] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:47:pipe B] enable changed
>[13302.718303] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:47:pipe B] active changed
>[13302.718314] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:61:DP-2]
>[13302.718325] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:61:DP-2] using [ENCODER:60:DDI C] on [CRTC:47:pipe B]
>[13302.718335] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:47:pipe B] needs all connectors, enable: y, active: y
>[13302.718354] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:47:pipe B] to 00000000a6ac6587
>[13302.718375] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:47:pipe B] to 00000000a6ac6587
>[13302.718439] [drm:intel_atomic_check [i915]] [CONNECTOR:61:DP-2] checking for sink bpp constrains
>[13302.718500] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[13302.718563] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[13302.718637] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[13302.718691] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[13302.718751] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[13302.718808] [drm:intel_dump_pipe_config [i915]] [CRTC:47:pipe B][modeset]
>[13302.718864] [drm:intel_dump_pipe_config [i915]] output_types: DP (0x80)
>[13302.718915] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[13302.718968] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[13302.719016] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[13302.719063] [drm:intel_dump_pipe_config [i915]] requested mode:
>[13302.719090] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[13302.719139] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[13302.719164] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[13302.719217] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[13302.719266] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[13302.719314] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[13302.719361] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[13302.719408] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[13302.719454] [drm:intel_dump_pipe_config [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[13302.719500] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[13302.719545] [drm:intel_dump_pipe_config [i915]] [PLANE:38:plane 1B] disabled, scaler_id = -1
>[13302.719592] [drm:intel_dump_pipe_config [i915]] [PLANE:41:plane 2B] disabled, scaler_id = -1
>[13302.719637] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor B] disabled, scaler_id = -1
>[13302.719694] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[13302.719746] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[13302.719805] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:47:pipe B] has [PLANE:38:plane 1B] with fb 99
>[13302.719857] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:38:plane 1B] visible 0 -> 1, off 0, on 1, ms 1
>[13302.719916] [drm:intel_find_shared_dpll [i915]] [CRTC:47:pipe B] allocated DPLL 1
>[13302.719968] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[13302.720000] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:37:pipe A] 00000000c85dec7a state to 00000000a6ac6587
>[13302.720049] [drm:skl_compute_wm [i915]] [PLANE:38:plane 1B] ddb (0 - 0) -> (0 - 860)
>[13302.720090] [drm:skl_compute_wm [i915]] [PLANE:44:cursor B] ddb (0 - 0) -> (860 - 892)
>[13302.720117] [drm:drm_atomic_commit [drm]] committing 00000000a6ac6587
>[13303.718277] [drm:intel_power_well_enable [i915]] enabling power well 2
>[13303.718362] [drm:intel_atomic_commit_tail [i915]] [ENCODER:48:DDI A]
>[13303.718424] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI B]
>[13303.718480] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[13303.718535] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[13303.718587] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DDI C]
>[13303.718637] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST A]
>[13303.718687] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST B]
>[13303.718737] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI D]
>[13303.718786] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[13303.718835] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[13303.718892] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[13303.718948] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[13303.719003] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[13303.719055] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[13303.719118] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 2, on? 0) for crtc 47
>[13303.719174] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[13303.719316] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well
>[13303.720420] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[13303.720474] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[13303.720525] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[13303.720576] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[13303.721265] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 04000000
>[13303.721327] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[13303.721383] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[13303.722030] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[13303.722083] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[13303.723023] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[13303.723403] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:61:DP-2] Link Training Passed at Link Rate = 162000, Lane count = 4
>[13303.723908] [drm:intel_enable_pipe [i915]] enabling pipe B
>[13303.723992] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS
>[13303.740775] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:61:DP-2]
>[13303.740848] [drm:intel_atomic_commit_tail [i915]] [CRTC:47:pipe B]
>[13303.740927] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[13303.740966] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000a6ac6587
>[13303.740992] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000a6ac6587
>[13303.741059] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[13303.741084] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000a6ac6587
>[13303.741109] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:47:pipe B] 000000002b48c403 state to 00000000a6ac6587
>[13303.741130] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:38:plane 1B] 000000005906dec2 state to 00000000a6ac6587
>[13303.741151] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for CRTC state 000000002b48c403
>[13303.741169] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 000000005906dec2 to [NOCRTC]
>[13303.741187] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for plane state 000000005906dec2
>[13303.741206] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:47:pipe B] to 00000000a6ac6587
>[13303.741226] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:61:DP-2] 0000000056bf571a state to 00000000a6ac6587
>[13303.741244] [drm:drm_atomic_set_crtc_for_connector [drm]] Link connector state 0000000056bf571a to [NOCRTC]
>[13303.741261] [drm:drm_atomic_check_only [drm]] checking 00000000a6ac6587
>[13303.741277] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:47:pipe B] mode changed
>[13303.741287] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:47:pipe B] enable changed
>[13303.741297] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:47:pipe B] active changed
>[13303.741307] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:61:DP-2]
>[13303.741316] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Disabling [CONNECTOR:61:DP-2]
>[13303.741327] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:47:pipe B] needs all connectors, enable: n, active: n
>[13303.741346] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:47:pipe B] to 00000000a6ac6587
>[13303.741421] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[13303.741485] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[13303.741550] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:47:pipe B] has [PLANE:38:plane 1B] with fb -1
>[13303.741608] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:38:plane 1B] visible 1 -> 0, off 1, on 0, ms 1
>[13303.741637] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:37:pipe A] 00000000bd3c0152 state to 00000000a6ac6587
>[13303.741688] [drm:skl_compute_wm [i915]] [PLANE:38:plane 1B] ddb (0 - 860) -> (0 - 0)
>[13303.741733] [drm:skl_compute_wm [i915]] [PLANE:44:cursor B] ddb (860 - 892) -> (0 - 0)
>[13303.741757] [drm:drm_atomic_commit [drm]] committing 00000000a6ac6587
>[13303.741851] [drm:intel_disable_pipe [i915]] disabling pipe B
>[13303.759550] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well
>[13303.759622] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 2, on? 1) for crtc 47
>[13303.759684] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[13303.759757] [drm:intel_atomic_commit_tail [i915]] [ENCODER:48:DDI A]
>[13303.759812] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI B]
>[13303.759863] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[13303.759913] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[13303.759961] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DDI C]
>[13303.760011] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST A]
>[13303.760058] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST B]
>[13303.760103] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI D]
>[13303.760149] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[13303.760194] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[13303.760246] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:61:DP-2]
>[13303.760300] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[13303.760351] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[13303.760401] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[13303.760449] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[13303.760499] [drm:intel_power_well_disable [i915]] disabling power well 2
>[13303.760556] [drm:intel_atomic_commit_tail [i915]] [CRTC:47:pipe B]
>[13303.760590] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000a6ac6587
>[13303.760617] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000a6ac6587
>[13303.760909] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[13303.760950] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:61:DP-2]
>[13303.760990] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000a6ac6587
>[13303.761023] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:47:pipe B] 00000000604357f6 state to 00000000a6ac6587
>[13303.761047] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:38:plane 1B] 00000000dbafe848 state to 00000000a6ac6587
>[13303.761072] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [MODE:1920x1200] for CRTC state 00000000604357f6
>[13303.761092] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 00000000dbafe848 to [CRTC:47:pipe B]
>[13303.761113] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:98] for plane state 00000000dbafe848
>[13303.761132] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:47:pipe B] to 00000000a6ac6587
>[13303.761154] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:61:DP-2] 00000000d1e5643f state to 00000000a6ac6587
>[13303.761172] [drm:drm_atomic_set_crtc_for_connector [drm]] Link connector state 00000000d1e5643f to [CRTC:47:pipe B]
>[13303.761193] [drm:drm_atomic_check_only [drm]] checking 00000000a6ac6587
>[13303.761209] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:47:pipe B] mode changed
>[13303.761221] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:47:pipe B] enable changed
>[13303.761232] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:47:pipe B] active changed
>[13303.761244] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:61:DP-2]
>[13303.761255] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:61:DP-2] using [ENCODER:60:DDI C] on [CRTC:47:pipe B]
>[13303.761267] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:47:pipe B] needs all connectors, enable: y, active: y
>[13303.761286] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:47:pipe B] to 00000000a6ac6587
>[13303.761307] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:47:pipe B] to 00000000a6ac6587
>[13303.761375] [drm:intel_atomic_check [i915]] [CONNECTOR:61:DP-2] checking for sink bpp constrains
>[13303.761437] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[13303.761502] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[13303.761576] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[13303.761631] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[13303.761691] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[13303.761749] [drm:intel_dump_pipe_config [i915]] [CRTC:47:pipe B][modeset]
>[13303.761806] [drm:intel_dump_pipe_config [i915]] output_types: DP (0x80)
>[13303.761858] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[13303.761910] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[13303.761960] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[13303.762009] [drm:intel_dump_pipe_config [i915]] requested mode:
>[13303.762037] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[13303.762089] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[13303.762116] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[13303.762170] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[13303.762220] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[13303.762269] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[13303.762318] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[13303.762365] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[13303.762412] [drm:intel_dump_pipe_config [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[13303.762459] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[13303.762506] [drm:intel_dump_pipe_config [i915]] [PLANE:38:plane 1B] disabled, scaler_id = -1
>[13303.762553] [drm:intel_dump_pipe_config [i915]] [PLANE:41:plane 2B] disabled, scaler_id = -1
>[13303.762599] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor B] disabled, scaler_id = -1
>[13303.762658] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[13303.762712] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[13303.762775] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:47:pipe B] has [PLANE:38:plane 1B] with fb 98
>[13303.762829] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:38:plane 1B] visible 0 -> 1, off 0, on 1, ms 1
>[13303.762888] [drm:intel_find_shared_dpll [i915]] [CRTC:47:pipe B] allocated DPLL 1
>[13303.762942] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe B
>[13303.762975] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:37:pipe A] 00000000c85dec7a state to 00000000a6ac6587
>[13303.763025] [drm:skl_compute_wm [i915]] [PLANE:38:plane 1B] ddb (0 - 0) -> (0 - 860)
>[13303.763068] [drm:skl_compute_wm [i915]] [PLANE:44:cursor B] ddb (0 - 0) -> (860 - 892)
>[13303.763096] [drm:drm_atomic_commit [drm]] committing 00000000a6ac6587
>[13304.761130] [drm:intel_power_well_enable [i915]] enabling power well 2
>[13304.761213] [drm:intel_atomic_commit_tail [i915]] [ENCODER:48:DDI A]
>[13304.761277] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI B]
>[13304.761335] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[13304.761390] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[13304.761442] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DDI C]
>[13304.761493] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST A]
>[13304.761543] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST B]
>[13304.761593] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI D]
>[13304.761642] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[13304.761690] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[13304.761746] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[13304.761803] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[13304.761856] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[13304.761909] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[13304.761971] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 2, on? 0) for crtc 47
>[13304.762027] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[13304.762168] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well
>[13304.763273] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[13304.763326] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[13304.763376] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[13304.763425] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[13304.764069] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 04000000
>[13304.764115] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[13304.764161] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[13304.764832] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[13304.764900] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[13304.765855] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[13304.766239] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:61:DP-2] Link Training Passed at Link Rate = 162000, Lane count = 4
>[13304.766746] [drm:intel_enable_pipe [i915]] enabling pipe B
>[13304.766824] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS
>[13304.783586] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:61:DP-2]
>[13304.783659] [drm:intel_atomic_commit_tail [i915]] [CRTC:47:pipe B]
>[13304.783738] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[13304.783775] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000a6ac6587
>[13304.783801] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000a6ac6587
>[13304.783860] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[13304.783885] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000a6ac6587
>[13304.783909] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:47:pipe B] 000000002b48c403 state to 00000000a6ac6587
>[13304.783931] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:38:plane 1B] 00000000c4c517e9 state to 00000000a6ac6587
>[13304.783951] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for CRTC state 000000002b48c403
>[13304.783970] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 00000000c4c517e9 to [NOCRTC]
>[13304.783989] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for plane state 00000000c4c517e9
>[13304.784007] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:47:pipe B] to 00000000a6ac6587
>[13304.784026] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:61:DP-2] 00000000572650ad state to 00000000a6ac6587
>[13304.784044] [drm:drm_atomic_set_crtc_for_connector [drm]] Link connector state 00000000572650ad to [NOCRTC]
>[13304.784061] [drm:drm_atomic_check_only [drm]] checking 00000000a6ac6587
>[13304.784076] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:47:pipe B] mode changed
>[13304.784087] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:47:pipe B] enable changed
>[13304.784096] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:47:pipe B] active changed
>[13304.784107] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:61:DP-2]
>[13304.784116] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Disabling [CONNECTOR:61:DP-2]
>[13304.784126] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:47:pipe B] needs all connectors, enable: n, active: n
>[13304.784145] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:47:pipe B] to 00000000a6ac6587
>[13304.784220] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[13304.784282] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[13304.784347] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:47:pipe B] has [PLANE:38:plane 1B] with fb -1
>[13304.784405] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:38:plane 1B] visible 1 -> 0, off 1, on 0, ms 1
>[13304.784434] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:37:pipe A] 00000000bd3c0152 state to 00000000a6ac6587
>[13304.784484] [drm:skl_compute_wm [i915]] [PLANE:38:plane 1B] ddb (0 - 860) -> (0 - 0)
>[13304.784530] [drm:skl_compute_wm [i915]] [PLANE:44:cursor B] ddb (860 - 892) -> (0 - 0)
>[13304.784553] [drm:drm_atomic_commit [drm]] committing 00000000a6ac6587
>[13304.784648] [drm:intel_disable_pipe [i915]] disabling pipe B
>[13304.800693] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well
>[13304.800785] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 2, on? 1) for crtc 47
>[13304.800847] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[13304.800919] [drm:intel_atomic_commit_tail [i915]] [ENCODER:48:DDI A]
>[13304.800974] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI B]
>[13304.801023] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[13304.801071] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[13304.801118] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DDI C]
>[13304.801166] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST A]
>[13304.801211] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST B]
>[13304.801256] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI D]
>[13304.801300] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[13304.801345] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[13304.801396] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:61:DP-2]
>[13304.801449] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[13304.801500] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[13304.801550] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[13304.801597] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[13304.801646] [drm:intel_power_well_disable [i915]] disabling power well 2
>[13304.801703] [drm:intel_atomic_commit_tail [i915]] [CRTC:47:pipe B]
>[13304.801737] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000a6ac6587
>[13304.801762] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000a6ac6587
>[13304.803119] [IGT] kms_flip: exiting, ret=0
>[13304.803476] [drm:intel_power_well_disable [i915]] disabling DC off
>[13304.803529] [drm:skl_enable_dc6 [i915]] Enabling DC6
>[13304.803577] [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>[13304.804012] [drm:intel_power_well_disable [i915]] disabling always-on
>[13304.842020] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000006855391c
>[13304.842051] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000b3bcf4ff state to 000000006855391c
>[13304.842075] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 2A] 000000000efdb0b1 state to 000000006855391c
>[13304.842094] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 000000000efdb0b1 to [NOCRTC]
>[13304.842114] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for plane state 000000000efdb0b1
>[13304.842132] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:34:cursor A] 000000003b96db3d state to 000000006855391c
>[13304.842149] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 000000003b96db3d to [NOCRTC]
>[13304.842167] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for plane state 000000003b96db3d
>[13304.842184] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:38:plane 1B] 0000000081fe3291 state to 000000006855391c
>[13304.842201] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:41:plane 2B] 000000006097095e state to 000000006855391c
>[13304.842217] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 000000006097095e to [NOCRTC]
>[13304.842234] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for plane state 000000006097095e
>[13304.842251] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:44:cursor B] 00000000c95a556c state to 000000006855391c
>[13304.842267] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 00000000c95a556c to [NOCRTC]
>[13304.842283] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for plane state 00000000c95a556c
>[13304.842302] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:37:pipe A] 0000000052fcd53d state to 000000006855391c
>[13304.842325] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [MODE:1920x1080] for CRTC state 0000000052fcd53d
>[13304.842342] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 00000000b3bcf4ff to [CRTC:37:pipe A]
>[13304.842359] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:115] for plane state 00000000b3bcf4ff
>[13304.842377] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:37:pipe A] to 000000006855391c
>[13304.842397] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:56:DP-1] 000000006b45dc93 state to 000000006855391c
>[13304.842414] [drm:drm_atomic_set_crtc_for_connector [drm]] Link connector state 000000006b45dc93 to [CRTC:37:pipe A]
>[13304.842432] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:47:pipe B] 00000000612a648b state to 000000006855391c
>[13304.842450] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [MODE:1920x1200] for CRTC state 00000000612a648b
>[13304.842466] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 0000000081fe3291 to [CRTC:47:pipe B]
>[13304.842483] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:115] for plane state 0000000081fe3291
>[13304.842500] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:47:pipe B] to 000000006855391c
>[13304.842518] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:61:DP-2] 000000009ac4a60d state to 000000006855391c
>[13304.842535] [drm:drm_atomic_set_crtc_for_connector [drm]] Link connector state 000000009ac4a60d to [CRTC:47:pipe B]
>[13304.842551] [drm:drm_atomic_check_only [drm]] checking 000000006855391c
>[13304.842568] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:37:pipe A] mode changed
>[13304.842579] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:37:pipe A] enable changed
>[13304.842589] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:37:pipe A] active changed
>[13304.842598] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:47:pipe B] mode changed
>[13304.842607] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:47:pipe B] enable changed
>[13304.842617] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:47:pipe B] active changed
>[13304.842629] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:56:DP-1]
>[13304.842640] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:56:DP-1] using [ENCODER:55:DDI B] on [CRTC:37:pipe A]
>[13304.842649] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:61:DP-2]
>[13304.842659] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:61:DP-2] using [ENCODER:60:DDI C] on [CRTC:47:pipe B]
>[13304.842669] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:37:pipe A] needs all connectors, enable: y, active: y
>[13304.842689] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:37:pipe A] to 000000006855391c
>[13304.842700] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:47:pipe B] needs all connectors, enable: y, active: y
>[13304.842718] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:47:pipe B] to 000000006855391c
>[13304.842739] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:37:pipe A] to 000000006855391c
>[13304.842815] [drm:intel_atomic_check [i915]] [CONNECTOR:56:DP-1] checking for sink bpp constrains
>[13304.842886] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 148500KHz
>[13304.842967] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 4 clock 270000 bpp 36
>[13304.843027] [drm:intel_dp_compute_config [i915]] DP link bw required 668250 available 1080000
>[13304.843091] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 36, dithering: 0
>[13304.843152] [drm:intel_dump_pipe_config [i915]] [CRTC:37:pipe A][modeset]
>[13304.843210] [drm:intel_dump_pipe_config [i915]] output_types: DP (0x80)
>[13304.843265] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 36, dithering: 0
>[13304.843317] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5190451, gmch_n: 8388608, link_m: 288358, link_n: 524288, tu: 64
>[13304.843369] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[13304.843418] [drm:intel_dump_pipe_config [i915]] requested mode:
>[13304.843448] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x9
>[13304.843501] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[13304.843528] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x9
>[13304.843584] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x9
>[13304.843636] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500
>[13304.843686] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[13304.843736] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[13304.843783] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[13304.843832] [drm:intel_dump_pipe_config [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[13304.843880] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[13304.843928] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 1A] disabled, scaler_id = -1
>[13304.843976] [drm:intel_dump_pipe_config [i915]] [PLANE:31:plane 2A] disabled, scaler_id = -1
>[13304.844024] [drm:intel_dump_pipe_config [i915]] [PLANE:34:cursor A] disabled, scaler_id = -1
>[13304.844053] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:47:pipe B] to 000000006855391c
>[13304.844115] [drm:intel_atomic_check [i915]] [CONNECTOR:61:DP-2] checking for sink bpp constrains
>[13304.844171] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[13304.844232] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[13304.844304] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[13304.844358] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[13304.844416] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[13304.844473] [drm:intel_dump_pipe_config [i915]] [CRTC:47:pipe B][modeset]
>[13304.844527] [drm:intel_dump_pipe_config [i915]] output_types: DP (0x80)
>[13304.844578] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[13304.844630] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[13304.844679] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[13304.844765] [drm:intel_dump_pipe_config [i915]] requested mode:
>[13304.844807] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[13304.844866] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[13304.844901] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[13304.844963] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[13304.845021] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[13304.845079] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[13304.845135] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[13304.845191] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[13304.845246] [drm:intel_dump_pipe_config [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[13304.845302] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[13304.845358] [drm:intel_dump_pipe_config [i915]] [PLANE:38:plane 1B] disabled, scaler_id = -1
>[13304.845413] [drm:intel_dump_pipe_config [i915]] [PLANE:41:plane 2B] disabled, scaler_id = -1
>[13304.845468] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor B] disabled, scaler_id = -1
>[13304.845535] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[13304.845597] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[13304.845665] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:37:pipe A] has [PLANE:28:plane 1A] with fb 115
>[13304.845727] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 0 -> 1, off 0, on 1, ms 1
>[13304.845789] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:47:pipe B] has [PLANE:38:plane 1B] with fb 115
>[13304.845848] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:38:plane 1B] visible 0 -> 1, off 0, on 1, ms 1
>[13304.845914] [drm:intel_find_shared_dpll [i915]] [CRTC:37:pipe A] allocated DPLL 1
>[13304.845975] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[13304.846038] [drm:intel_find_shared_dpll [i915]] [CRTC:47:pipe B] allocated DPLL 2
>[13304.846097] [drm:intel_reference_shared_dpll [i915]] using DPLL 2 for pipe B
>[13304.846155] [drm:skl_compute_wm [i915]] [PLANE:28:plane 1A] ddb (0 - 0) -> (0 - 438)
>[13304.846203] [drm:skl_compute_wm [i915]] [PLANE:34:cursor A] ddb (0 - 0) -> (438 - 446)
>[13304.846251] [drm:skl_compute_wm [i915]] [PLANE:38:plane 1B] ddb (0 - 0) -> (446 - 884)
>[13304.846303] [drm:skl_compute_wm [i915]] [PLANE:44:cursor B] ddb (0 - 0) -> (884 - 892)
>[13304.846339] [drm:drm_atomic_commit [drm]] committing 000000006855391c
>[13304.846416] [drm:intel_power_well_enable [i915]] enabling always-on
>[13304.846429] [drm:intel_power_well_enable [i915]] enabling DC off
>[13304.846722] [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>[13304.846753] [drm:intel_power_well_enable [i915]] enabling power well 2
>[13304.846769] [drm:intel_disable_sagv [i915]] Disabling the SAGV
>[13304.846787] [drm:intel_atomic_commit_tail [i915]] [ENCODER:48:DDI A]
>[13304.846818] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI B]
>[13304.846848] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[13304.846860] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[13304.846872] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DDI C]
>[13304.846884] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST A]
>[13304.846896] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST B]
>[13304.846923] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI D]
>[13304.846935] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[13304.846946] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[13304.846958] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[13304.846971] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[13304.846983] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[13304.846995] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[13304.847009] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 37
>[13304.847021] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[13304.847107] [drm:intel_power_well_enable [i915]] enabling DDI B IO power well
>[13304.847666] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13304.848815] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13304.849963] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13304.851095] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13304.852226] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13304.853230] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13304.854361] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13304.855080] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] too many retries, giving up
>[13304.855495] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13304.856614] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13304.857733] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13304.858853] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13304.859970] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13304.861079] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13304.862188] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13304.862887] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] too many retries, giving up
>[13304.864395] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13304.865500] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13304.866601] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13304.867708] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13304.868810] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13304.869913] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13304.871004] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13304.871683] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] too many retries, giving up
>[13304.872101] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13304.873184] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13304.874068] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13304.875162] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13304.876252] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13304.877195] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13304.878283] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13304.878959] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] too many retries, giving up
>[13304.880595] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13304.881825] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13304.883043] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13304.884268] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13304.885031] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[13304.885951] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[13304.885974] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[13304.885995] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[13304.886016] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[13304.904608] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[13304.904634] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[13304.922364] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[13304.922692] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:56:DP-1] Link Training Passed at Link Rate = 270000, Lane count = 4
>[13304.923056] [drm:intel_enable_pipe [i915]] enabling pipe A
>[13304.923080] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS
>[13304.923096] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:56:DP-1], [ENCODER:55:DDI B]
>[13304.923110] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[13304.923126] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[13304.923152] [drm:intel_fbc_enable [i915]] reserved 8294400 bytes of contiguous stolen space for FBC, threshold: 1
>[13304.923165] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[13304.923192] [drm:intel_enable_shared_dpll [i915]] enable DPLL 2 (active 2, on? 0) for crtc 47
>[13304.923205] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 2
>[13304.923292] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well
>[13304.924315] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[13304.924329] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[13304.924342] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[13304.924355] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[13304.924938] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[13304.924952] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[13304.925825] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[13304.926146] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:61:DP-2] Link Training Passed at Link Rate = 162000, Lane count = 4
>[13304.926505] [drm:intel_enable_pipe [i915]] enabling pipe B
>[13304.926547] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS
>[13304.943355] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:56:DP-1]
>[13304.943371] [drm:intel_atomic_commit_tail [i915]] [CRTC:37:pipe A]
>[13304.943392] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[13304.943412] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:61:DP-2]
>[13304.943426] [drm:intel_atomic_commit_tail [i915]] [CRTC:47:pipe B]
>[13304.943444] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[13304.943454] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000006855391c
>[13304.943460] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000006855391c
>[13304.943464] [drm:drm_fb_helper_hotplug_event.part.33 [drm_kms_helper]] 
>[13304.943466] [drm:drm_setup_crtcs [drm_kms_helper]] 
>[13304.943469] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:49:eDP-1]
>[13304.943483] [drm:intel_dp_detect [i915]] [CONNECTOR:49:eDP-1]
>[13304.943498] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>[13304.943510] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[13304.943522] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[13304.943589] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[13304.943655] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle
>[13304.943896] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 00000000 control 00000060
>[13304.943962] [drm:wait_panel_status [i915]] Wait complete
>[13304.944197] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x00000000 PP_CONTROL: 0x00000068
>[13304.944255] [drm:edp_panel_vdd_on [i915]] eDP port A panel power wasn't enabled
>[13305.046098] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010
>[13305.046166] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[13305.046227] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0
>[13305.046315] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[13305.149586] [drm:drm_dp_read_desc [drm_kms_helper]] DP sink: OUI 00-1c-f8 dev-ID q\006UA\022\001 HW-rev 10.0 SW-rev 1.41 quirks 0x0000
>[13305.150767] [drm:drm_add_display_info [drm]] non_desktop set to 0
>[13305.150799] [drm:drm_add_edid_modes [drm]] ELD: no CEA Extension found
>[13305.150819] [drm:drm_add_display_info [drm]] non_desktop set to 0
>[13305.150859] [drm:drm_mode_debug_printmodeline [drm]] Modeline 51:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa
>[13305.150878] [drm:drm_mode_prune_invalid [drm]] Not using 1920x1080 mode: CLOCK_HIGH
>[13305.150893] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:56:DP-1]
>[13305.150967] [drm:intel_dp_detect [i915]] [CONNECTOR:56:DP-1]
>[13305.151387] [drm:lspcon_wake_native_aux_ch [i915]] Native AUX CH up, DPCD version: 1.2
>[13305.151498] [drm:lspcon_resume [i915]] LSPCON recovering in PCON mode after 0 ms
>[13305.151935] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13305.153202] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13305.154475] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13305.155739] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13305.157018] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13305.157907] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[13305.158380] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 00 00 04 00 0f 00 04
>[13305.159153] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>[13305.159207] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000
>[13305.159257] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000
>[13305.159657] [drm:drm_dp_read_desc [drm_kms_helper]] DP branch: OUI 00-60-ad dev-ID MC2800 HW-rev 2.2 SW-rev 1.72 quirks 0x0000
>[13305.160006] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[13305.160800] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13305.162089] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13305.163361] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13305.164623] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13305.165901] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13305.167159] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13305.168430] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13305.169632] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13305.170896] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13305.172294] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13305.173632] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13305.175029] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13305.176422] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13305.177752] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13305.179149] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13305.180547] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13305.181944] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13305.183201] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13305.184473] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13305.185728] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13305.186992] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13305.188390] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13305.189717] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13305.191107] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13305.192496] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13305.193874] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13305.195270] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13305.196662] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13305.198050] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13305.198895] [drm:drm_detect_monitor_audio [drm]] Monitor has basic audio support
>[13305.199215] [drm:drm_add_display_info [drm]] non_desktop set to 0
>[13305.199234] [drm:drm_add_display_info [drm]] HDMI: DVI dual 0, max TMDS clock 225000 kHz
>[13305.199257] [drm:drm_add_edid_modes [drm]] ELD monitor BOBCAT2800
>[13305.199273] [drm:drm_add_edid_modes [drm]] HDMI: latency present 0 0, video latency 0 0, audio latency 0 0
>[13305.199287] [drm:drm_add_edid_modes [drm]] ELD size 36, SAD count 1
>[13305.199302] [drm:drm_add_display_info [drm]] non_desktop set to 0
>[13305.199315] [drm:drm_add_display_info [drm]] HDMI: DVI dual 0, max TMDS clock 225000 kHz
>[13305.199734] [drm:drm_mode_debug_printmodeline [drm]] Modeline 139:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[13305.199750] [drm:drm_mode_prune_invalid [drm]] Not using 720x480i mode: H_ILLEGAL
>[13305.199767] [drm:drm_mode_debug_printmodeline [drm]] Modeline 140:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[13305.199781] [drm:drm_mode_prune_invalid [drm]] Not using 720x576i mode: H_ILLEGAL
>[13305.199797] [drm:drm_mode_debug_printmodeline [drm]] Modeline 160:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[13305.199810] [drm:drm_mode_prune_invalid [drm]] Not using 720x480i mode: H_ILLEGAL
>[13305.199827] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:56:DP-1] probed modes :
>[13305.199844] [drm:drm_mode_debug_printmodeline [drm]] Modeline 74:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x9
>[13305.199859] [drm:drm_mode_debug_printmodeline [drm]] Modeline 81:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x40 0x9
>[13305.199873] [drm:drm_mode_debug_printmodeline [drm]] Modeline 75:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[13305.199888] [drm:drm_mode_debug_printmodeline [drm]] Modeline 120:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[13305.199902] [drm:drm_mode_debug_printmodeline [drm]] Modeline 76:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[13305.199917] [drm:drm_mode_debug_printmodeline [drm]] Modeline 121:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[13305.199931] [drm:drm_mode_debug_printmodeline [drm]] Modeline 109:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[13305.199946] [drm:drm_mode_debug_printmodeline [drm]] Modeline 114:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[13305.199960] [drm:drm_mode_debug_printmodeline [drm]] Modeline 116:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[13305.199975] [drm:drm_mode_debug_printmodeline [drm]] Modeline 132:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[13305.199990] [drm:drm_mode_debug_printmodeline [drm]] Modeline 80:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[13305.200004] [drm:drm_mode_debug_printmodeline [drm]] Modeline 87:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[13305.200018] [drm:drm_mode_debug_printmodeline [drm]] Modeline 79:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[13305.200033] [drm:drm_mode_debug_printmodeline [drm]] Modeline 82:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[13305.200047] [drm:drm_mode_debug_printmodeline [drm]] Modeline 77:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[13305.200061] [drm:drm_mode_debug_printmodeline [drm]] Modeline 122:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[13305.200076] [drm:drm_mode_debug_printmodeline [drm]] Modeline 113:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[13305.200090] [drm:drm_mode_debug_printmodeline [drm]] Modeline 88:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[13305.200104] [drm:drm_mode_debug_printmodeline [drm]] Modeline 89:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[13305.200119] [drm:drm_mode_debug_printmodeline [drm]] Modeline 90:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[13305.200133] [drm:drm_mode_debug_printmodeline [drm]] Modeline 83:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[13305.200147] [drm:drm_mode_debug_printmodeline [drm]] Modeline 110:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[13305.200162] [drm:drm_mode_debug_printmodeline [drm]] Modeline 123:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[13305.200176] [drm:drm_mode_debug_printmodeline [drm]] Modeline 78:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[13305.200191] [drm:drm_mode_debug_printmodeline [drm]] Modeline 84:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[13305.200205] [drm:drm_mode_debug_printmodeline [drm]] Modeline 124:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[13305.200219] [drm:drm_mode_debug_printmodeline [drm]] Modeline 85:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[13305.200233] [drm:drm_mode_debug_printmodeline [drm]] Modeline 86:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[13305.200243] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:61:DP-2]
>[13305.200306] [drm:intel_dp_detect [i915]] [CONNECTOR:61:DP-2]
>[13305.200846] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 00 02 02 06 05 00 00 00
>[13305.201237] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>[13305.201294] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[13305.201345] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[13305.201736] [drm:drm_dp_read_desc [drm_kms_helper]] DP sink: OUI 00-00-00 dev-ID  HW-rev 0.0 SW-rev 0.0 quirks 0x0000
>[13305.201787] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[13305.205709] [drm:drm_add_display_info [drm]] non_desktop set to 0
>[13305.205733] [drm:drm_add_edid_modes [drm]] ELD: no CEA Extension found
>[13305.205751] [drm:drm_add_display_info [drm]] non_desktop set to 0
>[13305.205893] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:61:DP-2] probed modes :
>[13305.205915] [drm:drm_mode_debug_printmodeline [drm]] Modeline 91:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[13305.205933] [drm:drm_mode_debug_printmodeline [drm]] Modeline 95:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0xa
>[13305.205948] [drm:drm_mode_debug_printmodeline [drm]] Modeline 103:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[13305.205964] [drm:drm_mode_debug_printmodeline [drm]] Modeline 92:"1680x1050" 60 146250 1680 1784 1960 2240 1050 1053 1059 1089 0x40 0x6
>[13305.205980] [drm:drm_mode_debug_printmodeline [drm]] Modeline 96:"1600x900" 60 108000 1600 1624 1704 1800 900 901 904 1000 0x40 0x5
>[13305.205994] [drm:drm_mode_debug_printmodeline [drm]] Modeline 104:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[13305.206010] [drm:drm_mode_debug_printmodeline [drm]] Modeline 93:"1440x900" 60 106500 1440 1520 1672 1904 900 903 909 934 0x40 0x6
>[13305.206024] [drm:drm_mode_debug_printmodeline [drm]] Modeline 94:"1280x800" 60 83500 1280 1352 1480 1680 800 803 809 831 0x40 0x6
>[13305.206039] [drm:drm_mode_debug_printmodeline [drm]] Modeline 97:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[13305.206054] [drm:drm_mode_debug_printmodeline [drm]] Modeline 112:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[13305.206069] [drm:drm_mode_debug_printmodeline [drm]] Modeline 105:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[13305.206083] [drm:drm_mode_debug_printmodeline [drm]] Modeline 111:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[13305.206093] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:64:HDMI-A-1]
>[13305.206151] [drm:intel_hdmi_detect [i915]] [CONNECTOR:64:HDMI-A-1]
>[13305.206583] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[13305.206631] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[13305.206964] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[13305.207059] [drm:drm_do_probe_ddc_edid [drm]] drm: skipping non-existent adapter i915 gmbus dpc
>[13305.207479] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[13305.207522] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[13305.207927] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[13305.207990] [drm:drm_dp_dual_mode_detect [drm_kms_helper]] DP dual mode HDMI ID:  (err -6)
>[13305.208001] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:64:HDMI-A-1] disconnected
>[13305.208011] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:67:DP-3]
>[13305.208059] [drm:intel_dp_detect [i915]] [CONNECTOR:67:DP-3]
>[13305.208103] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:67:DP-3] disconnected
>[13305.208112] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:70:HDMI-A-2]
>[13305.208156] [drm:intel_hdmi_detect [i915]] [CONNECTOR:70:HDMI-A-2]
>[13305.228414] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0050 w(1)
>[13305.228469] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK on first message, retry
>[13305.248715] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0050 w(1)
>[13305.248833] [drm:drm_do_probe_ddc_edid [drm]] drm: skipping non-existent adapter i915 gmbus dpd
>[13305.269825] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0040 w(1)
>[13305.269891] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK on first message, retry
>[13305.290654] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0040 w(1)
>[13305.290745] [drm:drm_dp_dual_mode_detect [drm_kms_helper]] DP dual mode HDMI ID:  (err -6)
>[13305.290759] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:70:HDMI-A-2] disconnected
>[13305.290773] [drm:drm_setup_crtcs [drm_kms_helper]] connector 49 enabled? yes
>[13305.290783] [drm:drm_setup_crtcs [drm_kms_helper]] connector 56 enabled? yes
>[13305.290793] [drm:drm_setup_crtcs [drm_kms_helper]] connector 61 enabled? yes
>[13305.290802] [drm:drm_setup_crtcs [drm_kms_helper]] connector 64 enabled? no
>[13305.290812] [drm:drm_setup_crtcs [drm_kms_helper]] connector 67 enabled? no
>[13305.290821] [drm:drm_setup_crtcs [drm_kms_helper]] connector 70 enabled? no
>[13305.290893] [drm:intel_fb_initial_config [i915]] Not using firmware configuration
>[13305.290906] [drm:drm_setup_crtcs [drm_kms_helper]] looking for cmdline mode on connector 49
>[13305.290916] [drm:drm_setup_crtcs [drm_kms_helper]] looking for preferred mode on connector 49 0
>[13305.290926] [drm:drm_setup_crtcs [drm_kms_helper]] found mode none
>[13305.290935] [drm:drm_setup_crtcs [drm_kms_helper]] looking for cmdline mode on connector 56
>[13305.290945] [drm:drm_setup_crtcs [drm_kms_helper]] looking for preferred mode on connector 56 0
>[13305.290954] [drm:drm_setup_crtcs [drm_kms_helper]] found mode 1920x1080
>[13305.290963] [drm:drm_setup_crtcs [drm_kms_helper]] looking for cmdline mode on connector 61
>[13305.290973] [drm:drm_setup_crtcs [drm_kms_helper]] looking for preferred mode on connector 61 0
>[13305.290982] [drm:drm_setup_crtcs [drm_kms_helper]] found mode 1920x1200
>[13305.290992] [drm:drm_setup_crtcs [drm_kms_helper]] picking CRTCs for 1920x1200 config
>[13305.291010] [drm:drm_setup_crtcs [drm_kms_helper]] desired mode 1920x1080 set on crtc 37 (0,0)
>[13305.291021] [drm:drm_setup_crtcs [drm_kms_helper]] desired mode 1920x1200 set on crtc 47 (0,0)
>[13305.291058] [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000059ed298d
>[13305.291085] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 000000009ece5c45 state to 0000000059ed298d
>[13305.291110] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:37:pipe A] 000000002b48c403 state to 0000000059ed298d
>[13305.291130] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 2A] 00000000a098866e state to 0000000059ed298d
>[13305.291149] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 00000000a098866e to [NOCRTC]
>[13305.291168] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for plane state 00000000a098866e
>[13305.291186] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:34:cursor A] 00000000edce41ff state to 0000000059ed298d
>[13305.291203] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 00000000edce41ff to [NOCRTC]
>[13305.291221] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for plane state 00000000edce41ff
>[13305.291238] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:38:plane 1B] 00000000a8a46f59 state to 0000000059ed298d
>[13305.291256] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:47:pipe B] 00000000bd3c0152 state to 0000000059ed298d
>[13305.291273] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:41:plane 2B] 00000000c2d4c763 state to 0000000059ed298d
>[13305.291289] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 00000000c2d4c763 to [NOCRTC]
>[13305.291306] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for plane state 00000000c2d4c763
>[13305.291323] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:44:cursor B] 00000000f7ae9d5b state to 0000000059ed298d
>[13305.291339] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 00000000f7ae9d5b to [NOCRTC]
>[13305.291355] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for plane state 00000000f7ae9d5b
>[13305.291376] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [MODE:1920x1080] for CRTC state 000000002b48c403
>[13305.291393] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 000000009ece5c45 to [CRTC:37:pipe A]
>[13305.291410] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:115] for plane state 000000009ece5c45
>[13305.291428] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:37:pipe A] to 0000000059ed298d
>[13305.291447] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:56:DP-1] 00000000572650ad state to 0000000059ed298d
>[13305.291465] [drm:drm_atomic_set_crtc_for_connector [drm]] Link connector state 00000000572650ad to [NOCRTC]
>[13305.291481] [drm:drm_atomic_set_crtc_for_connector [drm]] Link connector state 00000000572650ad to [CRTC:37:pipe A]
>[13305.291500] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [MODE:1920x1200] for CRTC state 00000000bd3c0152
>[13305.291517] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 00000000a8a46f59 to [CRTC:47:pipe B]
>[13305.291534] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:115] for plane state 00000000a8a46f59
>[13305.291551] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:47:pipe B] to 0000000059ed298d
>[13305.291568] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:61:DP-2] 00000000f8eadac6 state to 0000000059ed298d
>[13305.291586] [drm:drm_atomic_set_crtc_for_connector [drm]] Link connector state 00000000f8eadac6 to [NOCRTC]
>[13305.291603] [drm:drm_atomic_set_crtc_for_connector [drm]] Link connector state 00000000f8eadac6 to [CRTC:47:pipe B]
>[13305.291620] [drm:drm_atomic_check_only [drm]] checking 0000000059ed298d
>[13305.291638] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:56:DP-1]
>[13305.291651] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:56:DP-1] keeps [ENCODER:55:DDI B], now on [CRTC:37:pipe A]
>[13305.291661] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:61:DP-2]
>[13305.291671] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:61:DP-2] keeps [ENCODER:60:DDI C], now on [CRTC:47:pipe B]
>[13305.291751] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:37:pipe A] has [PLANE:28:plane 1A] with fb 115
>[13305.291817] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>[13305.291882] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:47:pipe B] has [PLANE:38:plane 1B] with fb 115
>[13305.291941] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:38:plane 1B] visible 1 -> 1, off 0, on 0, ms 0
>[13305.291976] [drm:drm_atomic_commit [drm]] committing 0000000059ed298d
>[13305.306517] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000059ed298d
>[13305.306551] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000059ed298d
>[13305.325006] [IGT] kms_flip: executing
>[13305.373166] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:49:eDP-1]
>[13305.373248] [drm:intel_dp_detect [i915]] [CONNECTOR:49:eDP-1]
>[13305.373341] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>[13305.373407] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[13305.373468] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[13305.374187] [drm:drm_dp_read_desc [drm_kms_helper]] DP sink: OUI 00-1c-f8 dev-ID q\006UA\022\001 HW-rev 10.0 SW-rev 1.41 quirks 0x0000
>[13305.375376] [drm:drm_add_display_info [drm]] non_desktop set to 0
>[13305.375409] [drm:drm_add_edid_modes [drm]] ELD: no CEA Extension found
>[13305.375432] [drm:drm_add_display_info [drm]] non_desktop set to 0
>[13305.375477] [drm:drm_mode_debug_printmodeline [drm]] Modeline 99:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa
>[13305.375498] [drm:drm_mode_prune_invalid [drm]] Not using 1920x1080 mode: CLOCK_HIGH
>[13305.375532] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:56:DP-1]
>[13305.375612] [drm:intel_dp_detect [i915]] [CONNECTOR:56:DP-1]
>[13305.376042] [drm:lspcon_wake_native_aux_ch [i915]] Native AUX CH up, DPCD version: 1.2
>[13305.376160] [drm:lspcon_resume [i915]] LSPCON recovering in PCON mode after 0 ms
>[13305.376600] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13305.377823] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13305.379095] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13305.380354] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13305.381555] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13305.382447] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[13305.382920] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 00 00 04 00 0f 00 04
>[13305.383694] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>[13305.383748] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000
>[13305.383798] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000
>[13305.384200] [drm:drm_dp_read_desc [drm_kms_helper]] DP branch: OUI 00-60-ad dev-ID MC2800 HW-rev 2.2 SW-rev 1.72 quirks 0x0000
>[13305.384549] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[13305.385363] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13305.386636] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13305.387905] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13305.389195] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13305.390469] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13305.391730] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13305.393008] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13305.394280] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13305.395545] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13305.396951] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13305.398354] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13305.399747] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13305.401179] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13305.402579] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13305.403979] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13305.405384] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13305.406774] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13305.408027] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13305.409337] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13305.410611] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13305.411874] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13305.413280] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13305.414679] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13305.416078] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13305.417541] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13305.418936] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13305.420328] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13305.421660] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13305.423049] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13305.423891] [drm:drm_detect_monitor_audio [drm]] Monitor has basic audio support
>[13305.424212] [drm:drm_add_display_info [drm]] non_desktop set to 0
>[13305.424230] [drm:drm_add_display_info [drm]] HDMI: DVI dual 0, max TMDS clock 225000 kHz
>[13305.424253] [drm:drm_add_edid_modes [drm]] ELD monitor BOBCAT2800
>[13305.424270] [drm:drm_add_edid_modes [drm]] HDMI: latency present 0 0, video latency 0 0, audio latency 0 0
>[13305.424283] [drm:drm_add_edid_modes [drm]] ELD size 36, SAD count 1
>[13305.424297] [drm:drm_add_display_info [drm]] non_desktop set to 0
>[13305.424311] [drm:drm_add_display_info [drm]] HDMI: DVI dual 0, max TMDS clock 225000 kHz
>[13305.424761] [drm:drm_mode_debug_printmodeline [drm]] Modeline 139:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[13305.424789] [drm:drm_mode_prune_invalid [drm]] Not using 720x480i mode: H_ILLEGAL
>[13305.424809] [drm:drm_mode_debug_printmodeline [drm]] Modeline 140:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[13305.424831] [drm:drm_mode_prune_invalid [drm]] Not using 720x576i mode: H_ILLEGAL
>[13305.424855] [drm:drm_mode_debug_printmodeline [drm]] Modeline 160:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[13305.424873] [drm:drm_mode_prune_invalid [drm]] Not using 720x480i mode: H_ILLEGAL
>[13305.424896] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:56:DP-1] probed modes :
>[13305.424923] [drm:drm_mode_debug_printmodeline [drm]] Modeline 74:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x9
>[13305.424952] [drm:drm_mode_debug_printmodeline [drm]] Modeline 81:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x40 0x9
>[13305.424988] [drm:drm_mode_debug_printmodeline [drm]] Modeline 75:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[13305.425018] [drm:drm_mode_debug_printmodeline [drm]] Modeline 120:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[13305.425048] [drm:drm_mode_debug_printmodeline [drm]] Modeline 76:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[13305.425076] [drm:drm_mode_debug_printmodeline [drm]] Modeline 121:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[13305.425105] [drm:drm_mode_debug_printmodeline [drm]] Modeline 109:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[13305.425122] [drm:drm_mode_debug_printmodeline [drm]] Modeline 114:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[13305.425140] [drm:drm_mode_debug_printmodeline [drm]] Modeline 116:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[13305.425154] [drm:drm_mode_debug_printmodeline [drm]] Modeline 132:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[13305.425170] [drm:drm_mode_debug_printmodeline [drm]] Modeline 80:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[13305.425187] [drm:drm_mode_debug_printmodeline [drm]] Modeline 87:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[13305.425203] [drm:drm_mode_debug_printmodeline [drm]] Modeline 79:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[13305.425218] [drm:drm_mode_debug_printmodeline [drm]] Modeline 82:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[13305.425235] [drm:drm_mode_debug_printmodeline [drm]] Modeline 77:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[13305.425250] [drm:drm_mode_debug_printmodeline [drm]] Modeline 122:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[13305.425267] [drm:drm_mode_debug_printmodeline [drm]] Modeline 113:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[13305.425283] [drm:drm_mode_debug_printmodeline [drm]] Modeline 88:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[13305.425298] [drm:drm_mode_debug_printmodeline [drm]] Modeline 89:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[13305.425314] [drm:drm_mode_debug_printmodeline [drm]] Modeline 90:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[13305.425331] [drm:drm_mode_debug_printmodeline [drm]] Modeline 83:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[13305.425346] [drm:drm_mode_debug_printmodeline [drm]] Modeline 110:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[13305.425362] [drm:drm_mode_debug_printmodeline [drm]] Modeline 123:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[13305.425378] [drm:drm_mode_debug_printmodeline [drm]] Modeline 78:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[13305.425394] [drm:drm_mode_debug_printmodeline [drm]] Modeline 84:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[13305.425408] [drm:drm_mode_debug_printmodeline [drm]] Modeline 124:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[13305.425425] [drm:drm_mode_debug_printmodeline [drm]] Modeline 85:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[13305.425440] [drm:drm_mode_debug_printmodeline [drm]] Modeline 86:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[13305.425481] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:61:DP-2]
>[13305.425546] [drm:intel_dp_detect [i915]] [CONNECTOR:61:DP-2]
>[13305.426067] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 00 02 02 06 05 00 00 00
>[13305.426405] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>[13305.426456] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[13305.426504] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[13305.426891] [drm:drm_dp_read_desc [drm_kms_helper]] DP sink: OUI 00-00-00 dev-ID  HW-rev 0.0 SW-rev 0.0 quirks 0x0000
>[13305.426940] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[13305.430891] [drm:drm_add_display_info [drm]] non_desktop set to 0
>[13305.430915] [drm:drm_add_edid_modes [drm]] ELD: no CEA Extension found
>[13305.430932] [drm:drm_add_display_info [drm]] non_desktop set to 0
>[13305.431076] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:61:DP-2] probed modes :
>[13305.431097] [drm:drm_mode_debug_printmodeline [drm]] Modeline 91:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[13305.431115] [drm:drm_mode_debug_printmodeline [drm]] Modeline 95:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0xa
>[13305.431131] [drm:drm_mode_debug_printmodeline [drm]] Modeline 103:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[13305.431146] [drm:drm_mode_debug_printmodeline [drm]] Modeline 92:"1680x1050" 60 146250 1680 1784 1960 2240 1050 1053 1059 1089 0x40 0x6
>[13305.431161] [drm:drm_mode_debug_printmodeline [drm]] Modeline 96:"1600x900" 60 108000 1600 1624 1704 1800 900 901 904 1000 0x40 0x5
>[13305.431175] [drm:drm_mode_debug_printmodeline [drm]] Modeline 104:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[13305.431190] [drm:drm_mode_debug_printmodeline [drm]] Modeline 93:"1440x900" 60 106500 1440 1520 1672 1904 900 903 909 934 0x40 0x6
>[13305.431204] [drm:drm_mode_debug_printmodeline [drm]] Modeline 94:"1280x800" 60 83500 1280 1352 1480 1680 800 803 809 831 0x40 0x6
>[13305.431219] [drm:drm_mode_debug_printmodeline [drm]] Modeline 97:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[13305.431233] [drm:drm_mode_debug_printmodeline [drm]] Modeline 112:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[13305.431248] [drm:drm_mode_debug_printmodeline [drm]] Modeline 105:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[13305.431262] [drm:drm_mode_debug_printmodeline [drm]] Modeline 111:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[13305.431288] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:64:HDMI-A-1]
>[13305.431346] [drm:intel_hdmi_detect [i915]] [CONNECTOR:64:HDMI-A-1]
>[13305.431902] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[13305.431951] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[13305.432349] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[13305.432422] [drm:drm_do_probe_ddc_edid [drm]] drm: skipping non-existent adapter i915 gmbus dpc
>[13305.432963] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[13305.433033] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[13305.433454] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[13305.433518] [drm:drm_dp_dual_mode_detect [drm_kms_helper]] DP dual mode HDMI ID:  (err -6)
>[13305.433530] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:64:HDMI-A-1] disconnected
>[13305.433554] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:67:DP-3]
>[13305.433603] [drm:intel_dp_detect [i915]] [CONNECTOR:67:DP-3]
>[13305.433649] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:67:DP-3] disconnected
>[13305.433665] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:70:HDMI-A-2]
>[13305.433710] [drm:intel_hdmi_detect [i915]] [CONNECTOR:70:HDMI-A-2]
>[13305.454004] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0050 w(1)
>[13305.454060] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK on first message, retry
>[13305.474638] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0050 w(1)
>[13305.474720] [drm:drm_do_probe_ddc_edid [drm]] drm: skipping non-existent adapter i915 gmbus dpd
>[13305.495001] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0040 w(1)
>[13305.495063] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK on first message, retry
>[13305.515409] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0040 w(1)
>[13305.515483] [drm:drm_dp_dual_mode_detect [drm_kms_helper]] DP dual mode HDMI ID:  (err -6)
>[13305.515497] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:70:HDMI-A-2] disconnected
>[13305.516291] [IGT] kms_flip: starting subtest plain-flip-fb-recreate-interruptible
>[13305.516839] [drm:drm_mode_addfb2 [drm]] [FB:72]
>[13305.516883] [drm:drm_mode_addfb2 [drm]] [FB:100]
>[13305.572073] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[13305.572084] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000000c9d9950
>[13305.572092] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:37:pipe A] 0000000023ca96d4 state to 000000000c9d9950
>[13305.572100] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 000000005548a7b9 state to 000000000c9d9950
>[13305.572106] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for CRTC state 0000000023ca96d4
>[13305.572111] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 000000005548a7b9 to [NOCRTC]
>[13305.572116] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for plane state 000000005548a7b9
>[13305.572121] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:37:pipe A] to 000000000c9d9950
>[13305.572128] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:56:DP-1] 000000005e0fafdb state to 000000000c9d9950
>[13305.572133] [drm:drm_atomic_set_crtc_for_connector [drm]] Link connector state 000000005e0fafdb to [NOCRTC]
>[13305.572138] [drm:drm_atomic_check_only [drm]] checking 000000000c9d9950
>[13305.572144] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:37:pipe A] mode changed
>[13305.572147] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:37:pipe A] enable changed
>[13305.572150] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:37:pipe A] active changed
>[13305.572153] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:56:DP-1]
>[13305.572155] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Disabling [CONNECTOR:56:DP-1]
>[13305.572158] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:37:pipe A] needs all connectors, enable: n, active: n
>[13305.572163] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:37:pipe A] to 000000000c9d9950
>[13305.572191] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[13305.572209] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[13305.572228] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:37:pipe A] has [PLANE:28:plane 1A] with fb -1
>[13305.572245] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 0, off 1, on 0, ms 1
>[13305.572255] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:47:pipe B] 0000000008271548 state to 000000000c9d9950
>[13305.572262] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:38:plane 1B] 0000000092f5bca8 state to 000000000c9d9950
>[13305.572277] [drm:skl_compute_wm [i915]] [PLANE:28:plane 1A] ddb (0 - 438) -> (0 - 0)
>[13305.572290] [drm:skl_compute_wm [i915]] [PLANE:34:cursor A] ddb (438 - 446) -> (0 - 0)
>[13305.572303] [drm:skl_compute_wm [i915]] [PLANE:38:plane 1B] ddb (446 - 884) -> (0 - 860)
>[13305.572315] [drm:skl_compute_wm [i915]] [PLANE:44:cursor B] ddb (884 - 892) -> (860 - 892)
>[13305.572321] [drm:drm_atomic_commit [drm]] committing 000000000c9d9950
>[13305.572354] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[13305.572372] [drm:i915_audio_component_get_eld [i915]] Not valid for port B
>[13305.572398] [drm:intel_disable_pipe [i915]] disabling pipe A
>[13305.573285] [drm:intel_power_well_disable [i915]] disabling DDI B IO power well
>[13305.573305] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[13305.573323] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 37
>[13305.573339] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[13305.573363] [drm:intel_atomic_commit_tail [i915]] [ENCODER:48:DDI A]
>[13305.573379] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI B]
>[13305.573394] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[13305.573408] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[13305.573421] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DDI C]
>[13305.573435] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST A]
>[13305.573447] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST B]
>[13305.573460] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI D]
>[13305.573473] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[13305.573485] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[13305.573500] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:56:DP-1]
>[13305.573514] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[13305.573529] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[13305.573543] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[13305.573557] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[13305.577180] [drm:intel_atomic_commit_tail [i915]] [CRTC:37:pipe A]
>[13305.577198] [drm:intel_enable_sagv [i915]] Enabling the SAGV
>[13305.577211] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000000c9d9950
>[13305.577219] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000000c9d9950
>[13305.577236] [drm:drm_mode_setcrtc [drm]] [CRTC:47:pipe B]
>[13305.577242] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000001c79d1f4
>[13305.577249] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:47:pipe B] 00000000774c8cae state to 000000001c79d1f4
>[13305.577255] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:38:plane 1B] 00000000c8b50d56 state to 000000001c79d1f4
>[13305.577260] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for CRTC state 00000000774c8cae
>[13305.577264] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 00000000c8b50d56 to [NOCRTC]
>[13305.577269] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for plane state 00000000c8b50d56
>[13305.577273] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:47:pipe B] to 000000001c79d1f4
>[13305.577279] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:61:DP-2] 000000003437c456 state to 000000001c79d1f4
>[13305.577284] [drm:drm_atomic_set_crtc_for_connector [drm]] Link connector state 000000003437c456 to [NOCRTC]
>[13305.577288] [drm:drm_atomic_check_only [drm]] checking 000000001c79d1f4
>[13305.577293] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:47:pipe B] mode changed
>[13305.577296] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:47:pipe B] enable changed
>[13305.577299] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:47:pipe B] active changed
>[13305.577301] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:61:DP-2]
>[13305.577303] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Disabling [CONNECTOR:61:DP-2]
>[13305.577306] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:47:pipe B] needs all connectors, enable: n, active: n
>[13305.577311] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:47:pipe B] to 000000001c79d1f4
>[13305.577332] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[13305.577348] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[13305.577365] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:47:pipe B] has [PLANE:38:plane 1B] with fb -1
>[13305.577379] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:38:plane 1B] visible 1 -> 0, off 1, on 0, ms 1
>[13305.577387] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:37:pipe A] 0000000092d73ad1 state to 000000001c79d1f4
>[13305.577400] [drm:skl_compute_wm [i915]] [PLANE:38:plane 1B] ddb (0 - 860) -> (0 - 0)
>[13305.577412] [drm:skl_compute_wm [i915]] [PLANE:44:cursor B] ddb (860 - 892) -> (0 - 0)
>[13305.577418] [drm:drm_atomic_commit [drm]] committing 000000001c79d1f4
>[13305.577444] [drm:intel_disable_pipe [i915]] disabling pipe B
>[13305.594622] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well
>[13305.594640] [drm:intel_disable_shared_dpll [i915]] disable DPLL 2 (active 2, on? 1) for crtc 47
>[13305.594654] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 2
>[13305.594676] [drm:intel_atomic_commit_tail [i915]] [ENCODER:48:DDI A]
>[13305.594689] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI B]
>[13305.594700] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[13305.594711] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[13305.594721] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DDI C]
>[13305.594732] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST A]
>[13305.594742] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST B]
>[13305.594752] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI D]
>[13305.594762] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[13305.594772] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[13305.594784] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:61:DP-2]
>[13305.594795] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[13305.594807] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[13305.594818] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[13305.594828] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[13305.594841] [drm:intel_power_well_disable [i915]] disabling power well 2
>[13305.594856] [drm:intel_atomic_commit_tail [i915]] [CRTC:47:pipe B]
>[13305.594867] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000001c79d1f4
>[13305.594874] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000001c79d1f4
>[13305.594889] [drm:drm_mode_setcrtc [drm]] [CRTC:37:pipe A]
>[13305.594896] [drm:drm_mode_setcrtc [drm]] [CONNECTOR:56:DP-1]
>[13305.594902] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000001c79d1f4
>[13305.594908] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:37:pipe A] 000000005ce0965a state to 000000001c79d1f4
>[13305.594913] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 000000003722f193 state to 000000001c79d1f4
>[13305.594918] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [MODE:1920x1080] for CRTC state 000000005ce0965a
>[13305.594922] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 000000003722f193 to [CRTC:37:pipe A]
>[13305.594926] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:72] for plane state 000000003722f193
>[13305.594930] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:37:pipe A] to 000000001c79d1f4
>[13305.594935] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:56:DP-1] 00000000b260dc28 state to 000000001c79d1f4
>[13305.594939] [drm:drm_atomic_set_crtc_for_connector [drm]] Link connector state 00000000b260dc28 to [CRTC:37:pipe A]
>[13305.594944] [drm:drm_atomic_check_only [drm]] checking 000000001c79d1f4
>[13305.594948] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:37:pipe A] mode changed
>[13305.594950] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:37:pipe A] enable changed
>[13305.594952] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:37:pipe A] active changed
>[13305.594955] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:56:DP-1]
>[13305.594957] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:56:DP-1] using [ENCODER:55:DDI B] on [CRTC:37:pipe A]
>[13305.594959] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:37:pipe A] needs all connectors, enable: y, active: y
>[13305.594963] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:37:pipe A] to 000000001c79d1f4
>[13305.594967] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:37:pipe A] to 000000001c79d1f4
>[13305.594982] [drm:intel_atomic_check [i915]] [CONNECTOR:56:DP-1] checking for sink bpp constrains
>[13305.594996] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 148500KHz
>[13305.595013] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 4 clock 270000 bpp 36
>[13305.595025] [drm:intel_dp_compute_config [i915]] DP link bw required 668250 available 1080000
>[13305.595038] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 36, dithering: 0
>[13305.595051] [drm:intel_dump_pipe_config [i915]] [CRTC:37:pipe A][modeset]
>[13305.595063] [drm:intel_dump_pipe_config [i915]] output_types: DP (0x80)
>[13305.595075] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 36, dithering: 0
>[13305.595086] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5190451, gmch_n: 8388608, link_m: 288358, link_n: 524288, tu: 64
>[13305.595096] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[13305.595107] [drm:intel_dump_pipe_config [i915]] requested mode:
>[13305.595113] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x9
>[13305.595124] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[13305.595129] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x9
>[13305.595140] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x9
>[13305.595151] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500
>[13305.595161] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[13305.595171] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[13305.595181] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[13305.595192] [drm:intel_dump_pipe_config [i915]] dpll_hw_state: ctrl1: 0x3, cfgcr1: 0x0, cfgcr2: 0x0
>[13305.595201] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[13305.595211] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 1A] disabled, scaler_id = -1
>[13305.595221] [drm:intel_dump_pipe_config [i915]] [PLANE:31:plane 2A] disabled, scaler_id = -1
>[13305.595231] [drm:intel_dump_pipe_config [i915]] [PLANE:34:cursor A] disabled, scaler_id = -1
>[13305.595244] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[13305.595255] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[13305.595269] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:37:pipe A] has [PLANE:28:plane 1A] with fb 72
>[13305.595280] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 0 -> 1, off 0, on 1, ms 1
>[13305.595293] [drm:intel_find_shared_dpll [i915]] [CRTC:37:pipe A] allocated DPLL 1
>[13305.595304] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[13305.595312] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:47:pipe B] 00000000783a3c54 state to 000000001c79d1f4
>[13305.595323] [drm:skl_compute_wm [i915]] [PLANE:28:plane 1A] ddb (0 - 0) -> (0 - 860)
>[13305.595332] [drm:skl_compute_wm [i915]] [PLANE:34:cursor A] ddb (0 - 0) -> (860 - 892)
>[13305.595338] [drm:drm_atomic_commit [drm]] committing 000000001c79d1f4
>[13305.595736] [drm:intel_power_well_enable [i915]] enabling power well 2
>[13305.595754] [drm:intel_atomic_commit_tail [i915]] [ENCODER:48:DDI A]
>[13305.595766] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI B]
>[13305.595777] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[13305.595788] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[13305.595798] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DDI C]
>[13305.595808] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST A]
>[13305.595818] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST B]
>[13305.595828] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI D]
>[13305.595838] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[13305.595848] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[13305.595859] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[13305.595871] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[13305.595882] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[13305.595893] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[13305.595907] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 37
>[13305.595918] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[13305.596004] [drm:intel_power_well_enable [i915]] enabling DDI B IO power well
>[13305.596561] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13305.597716] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13305.599003] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13305.600278] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13305.601404] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13305.602107] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[13305.603007] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[13305.603033] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[13305.603044] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[13305.603055] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[13305.621719] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[13305.621733] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[13305.639468] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[13305.639643] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:56:DP-1] Link Training Passed at Link Rate = 270000, Lane count = 4
>[13305.640001] [drm:intel_enable_pipe [i915]] enabling pipe A
>[13305.640028] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS
>[13305.640041] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:56:DP-1], [ENCODER:55:DDI B]
>[13305.640053] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[13305.640066] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[13305.640087] [drm:intel_fbc_enable [i915]] reserved 8294400 bytes of contiguous stolen space for FBC, threshold: 1
>[13305.640099] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[13305.656966] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:56:DP-1]
>[13305.656984] [drm:intel_atomic_commit_tail [i915]] [CRTC:37:pipe A]
>[13305.657006] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[13305.657018] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000001c79d1f4
>[13305.657024] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000001c79d1f4
>[13305.940198] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000873a3bca
>[13305.940236] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:37:pipe A] 00000000604357f6 state to 00000000873a3bca
>[13305.940263] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 0000000069adce0f state to 00000000873a3bca
>[13305.940284] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 0000000069adce0f to [CRTC:37:pipe A]
>[13305.940306] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:100] for plane state 0000000069adce0f
>[13305.940327] [drm:drm_atomic_check_only [drm]] checking 00000000873a3bca
>[13305.940425] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:37:pipe A] has [PLANE:28:plane 1A] with fb 100
>[13305.940501] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>[13305.940540] [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000873a3bca nonblocking
>[13305.956929] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000873a3bca
>[13305.956964] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000873a3bca
>[13305.957007] [drm:drm_mode_addfb2 [drm]] [FB:73]
>[13305.957061] [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000099b1e95b
>[13305.957094] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:37:pipe A] 0000000052fcd53d state to 0000000099b1e95b
>[13305.957119] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000c95a556c state to 0000000099b1e95b
>[13305.957140] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 00000000c95a556c to [CRTC:37:pipe A]
>[13305.957162] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:73] for plane state 00000000c95a556c
>[13305.957182] [drm:drm_atomic_check_only [drm]] checking 0000000099b1e95b
>[13305.957281] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:37:pipe A] has [PLANE:28:plane 1A] with fb 73
>[13305.957356] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>[13305.957394] [drm:drm_atomic_nonblocking_commit [drm]] committing 0000000099b1e95b nonblocking
>[13305.973612] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000099b1e95b
>[13305.973647] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000099b1e95b
>[13305.973700] [drm:drm_mode_addfb2 [drm]] [FB:72]
>[13305.973750] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000e880ab74
>[13305.973783] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:37:pipe A] 00000000612a648b state to 00000000e880ab74
>[13305.973808] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 000000006097095e state to 00000000e880ab74
>[13305.973829] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 000000006097095e to [CRTC:37:pipe A]
>[13305.973851] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:72] for plane state 000000006097095e
>[13305.973872] [drm:drm_atomic_check_only [drm]] checking 00000000e880ab74
>[13305.973970] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:37:pipe A] has [PLANE:28:plane 1A] with fb 72
>[13305.974048] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>[13305.974087] [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000e880ab74 nonblocking
>[13305.990165] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000e880ab74
>[13305.990200] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000e880ab74
>[13305.990275] [drm:drm_mode_addfb2 [drm]] [FB:100]
>[13305.990325] [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000001fbffed
>[13305.990357] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:37:pipe A] 0000000043cb4c64 state to 0000000001fbffed
>[13305.990381] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 0000000081fe3291 state to 0000000001fbffed
>[13305.990402] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 0000000081fe3291 to [CRTC:37:pipe A]
>[13305.990424] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:100] for plane state 0000000081fe3291
>[13305.990445] [drm:drm_atomic_check_only [drm]] checking 0000000001fbffed
>[13305.990543] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:37:pipe A] has [PLANE:28:plane 1A] with fb 100
>[13305.990618] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>[13305.990657] [drm:drm_atomic_nonblocking_commit [drm]] committing 0000000001fbffed nonblocking
>[13306.006945] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000001fbffed
>[13306.006981] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000001fbffed
>[13306.007051] [drm:drm_mode_addfb2 [drm]] [FB:73]
>[13306.007103] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000006202e550
>[13306.007135] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:37:pipe A] 0000000008dd7b22 state to 000000006202e550
>[13306.007161] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 000000003b96db3d state to 000000006202e550
>[13306.007183] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 000000003b96db3d to [CRTC:37:pipe A]
>[13306.007204] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:73] for plane state 000000003b96db3d
>[13306.007226] [drm:drm_atomic_check_only [drm]] checking 000000006202e550
>[13306.007323] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:37:pipe A] has [PLANE:28:plane 1A] with fb 73
>[13306.007400] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>[13306.007440] [drm:drm_atomic_nonblocking_commit [drm]] committing 000000006202e550 nonblocking
>[13306.023613] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000006202e550
>[13306.023648] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000006202e550
>[13306.023725] [drm:drm_mode_addfb2 [drm]] [FB:72]
>[13306.023791] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000b714ca26
>[13306.023822] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:37:pipe A] 000000007b1f6733 state to 00000000b714ca26
>[13306.023847] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 000000000efdb0b1 state to 00000000b714ca26
>[13306.023868] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 000000000efdb0b1 to [CRTC:37:pipe A]
>[13306.023891] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:72] for plane state 000000000efdb0b1
>[13306.023912] [drm:drm_atomic_check_only [drm]] checking 00000000b714ca26
>[13306.024010] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:37:pipe A] has [PLANE:28:plane 1A] with fb 72
>[13306.024086] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>[13306.024126] [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000b714ca26 nonblocking
>[13306.040240] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000b714ca26
>[13306.040275] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000b714ca26
>[13306.040350] [drm:drm_mode_addfb2 [drm]] [FB:100]
>[13306.040402] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000004cdc04ee
>[13306.040434] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:37:pipe A] 00000000fd63c90d state to 000000004cdc04ee
>[13306.040459] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000b3bcf4ff state to 000000004cdc04ee
>[13306.040480] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 00000000b3bcf4ff to [CRTC:37:pipe A]
>[13306.040501] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:100] for plane state 00000000b3bcf4ff
>[13306.040522] [drm:drm_atomic_check_only [drm]] checking 000000004cdc04ee
>[13306.040619] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:37:pipe A] has [PLANE:28:plane 1A] with fb 100
>[13306.040695] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>[13306.040804] [drm:drm_atomic_nonblocking_commit [drm]] committing 000000004cdc04ee nonblocking
>[13306.056947] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000004cdc04ee
>[13306.056982] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000004cdc04ee
>[13306.057058] [drm:drm_mode_addfb2 [drm]] [FB:73]
>[13306.057110] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000004cdc04ee
>[13306.057142] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:37:pipe A] 0000000018046d93 state to 000000004cdc04ee
>[13306.057168] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 000000007d914018 state to 000000004cdc04ee
>[13306.057189] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 000000007d914018 to [CRTC:37:pipe A]
>[13306.057211] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:73] for plane state 000000007d914018
>[13306.057233] [drm:drm_atomic_check_only [drm]] checking 000000004cdc04ee
>[13306.057331] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:37:pipe A] has [PLANE:28:plane 1A] with fb 73
>[13306.057407] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>[13306.057446] [drm:drm_atomic_nonblocking_commit [drm]] committing 000000004cdc04ee nonblocking
>[13306.073565] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000004cdc04ee
>[13306.073601] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000004cdc04ee
>[13306.073682] [drm:drm_mode_addfb2 [drm]] [FB:72]
>[13306.073732] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000b714ca26
>[13306.073765] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:37:pipe A] 0000000024d204e2 state to 00000000b714ca26
>[13306.073790] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000a17ff7bd state to 00000000b714ca26
>[13306.073812] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 00000000a17ff7bd to [CRTC:37:pipe A]
>[13306.073834] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:72] for plane state 00000000a17ff7bd
>[13306.073854] [drm:drm_atomic_check_only [drm]] checking 00000000b714ca26
>[13306.073952] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:37:pipe A] has [PLANE:28:plane 1A] with fb 72
>[13306.074028] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>[13306.074067] [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000b714ca26 nonblocking
>[13306.090245] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000b714ca26
>[13306.090281] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000b714ca26
>[13306.090372] [drm:drm_mode_addfb2 [drm]] [FB:100]
>[13306.090423] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000006202e550
>[13306.090455] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:37:pipe A] 00000000fae58dee state to 000000006202e550
>[13306.090481] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 0000000013d9d6f7 state to 000000006202e550
>[13306.090503] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 0000000013d9d6f7 to [CRTC:37:pipe A]
>[13306.090525] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:100] for plane state 0000000013d9d6f7
>[13306.090546] [drm:drm_atomic_check_only [drm]] checking 000000006202e550
>[13306.090645] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:37:pipe A] has [PLANE:28:plane 1A] with fb 100
>[13306.090719] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>[13306.090759] [drm:drm_atomic_nonblocking_commit [drm]] committing 000000006202e550 nonblocking
>[13306.106944] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000006202e550
>[13306.106979] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000006202e550
>[13306.107055] [drm:drm_mode_addfb2 [drm]] [FB:73]
>[13306.107106] [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000001fbffed
>[13306.107138] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:37:pipe A] 00000000e1fcf8a7 state to 0000000001fbffed
>[13306.107163] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000074d8bfc state to 0000000001fbffed
>[13306.107184] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 00000000074d8bfc to [CRTC:37:pipe A]
>[13306.107206] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:73] for plane state 00000000074d8bfc
>[13306.107226] [drm:drm_atomic_check_only [drm]] checking 0000000001fbffed
>[13306.107324] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:37:pipe A] has [PLANE:28:plane 1A] with fb 73
>[13306.107399] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>[13306.107437] [drm:drm_atomic_nonblocking_commit [drm]] committing 0000000001fbffed nonblocking
>[13306.123474] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000001fbffed
>[13306.123508] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000001fbffed
>[13306.123575] [drm:drm_mode_addfb2 [drm]] [FB:72]
>[13306.123626] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000e880ab74
>[13306.123658] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:37:pipe A] 0000000081e9cf65 state to 00000000e880ab74
>[13306.123683] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000164f3c87 state to 00000000e880ab74
>[13306.123704] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 00000000164f3c87 to [CRTC:37:pipe A]
>[13306.123726] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:72] for plane state 00000000164f3c87
>[13306.123748] [drm:drm_atomic_check_only [drm]] checking 00000000e880ab74
>[13306.123846] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:37:pipe A] has [PLANE:28:plane 1A] with fb 72
>[13306.123923] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>[13306.123962] [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000e880ab74 nonblocking
>[13306.140253] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000e880ab74
>[13306.140286] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000e880ab74
>[13306.140434] [drm:drm_mode_addfb2 [drm]] [FB:100]
>[13306.140486] [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000099b1e95b
>[13306.140518] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:37:pipe A] 00000000d9d9b155 state to 0000000099b1e95b
>[13306.140544] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000ce970e68 state to 0000000099b1e95b
>[13306.140566] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 00000000ce970e68 to [CRTC:37:pipe A]
>[13306.140588] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:100] for plane state 00000000ce970e68
>[13306.140609] [drm:drm_atomic_check_only [drm]] checking 0000000099b1e95b
>[13306.140709] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:37:pipe A] has [PLANE:28:plane 1A] with fb 100
>[13306.140851] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>[13306.140908] [drm:drm_atomic_nonblocking_commit [drm]] committing 0000000099b1e95b nonblocking
>[13306.156961] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000099b1e95b
>[13306.156996] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000099b1e95b
>[13306.157070] [drm:drm_mode_addfb2 [drm]] [FB:73]
>[13306.157121] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000006855391c
>[13306.157154] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:37:pipe A] 000000006794fe06 state to 000000006855391c
>[13306.157180] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 000000005ce6f262 state to 000000006855391c
>[13306.157201] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 000000005ce6f262 to [CRTC:37:pipe A]
>[13306.157223] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:73] for plane state 000000005ce6f262
>[13306.157248] [drm:drm_atomic_check_only [drm]] checking 000000006855391c
>[13306.157347] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:37:pipe A] has [PLANE:28:plane 1A] with fb 73
>[13306.157422] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>[13306.157461] [drm:drm_atomic_nonblocking_commit [drm]] committing 000000006855391c nonblocking
>[13306.173552] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000006855391c
>[13306.173588] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000006855391c
>[13306.173669] [drm:drm_mode_addfb2 [drm]] [FB:72]
>[13306.173720] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000289ae621
>[13306.173752] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:37:pipe A] 00000000195b8dec state to 00000000289ae621
>[13306.173778] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000dc745b11 state to 00000000289ae621
>[13306.173800] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 00000000dc745b11 to [CRTC:37:pipe A]
>[13306.173822] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:72] for plane state 00000000dc745b11
>[13306.173843] [drm:drm_atomic_check_only [drm]] checking 00000000289ae621
>[13306.173941] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:37:pipe A] has [PLANE:28:plane 1A] with fb 72
>[13306.174015] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>[13306.174054] [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000289ae621 nonblocking
>[13306.190266] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000289ae621
>[13306.190301] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000289ae621
>[13306.190375] [drm:drm_mode_addfb2 [drm]] [FB:100]
>[13306.190426] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000673f18d0
>[13306.190457] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:37:pipe A] 00000000831a44cb state to 00000000673f18d0
>[13306.190482] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000f9695a62 state to 00000000673f18d0
>[13306.190504] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 00000000f9695a62 to [CRTC:37:pipe A]
>[13306.190526] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:100] for plane state 00000000f9695a62
>[13306.190547] [drm:drm_atomic_check_only [drm]] checking 00000000673f18d0
>[13306.190645] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:37:pipe A] has [PLANE:28:plane 1A] with fb 100
>[13306.190720] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>[13306.190759] [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000673f18d0 nonblocking
>[13306.206968] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000673f18d0
>[13306.207003] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000673f18d0
>[13306.207094] [drm:drm_mode_addfb2 [drm]] [FB:73]
>[13306.207146] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000c3c6da0f
>[13306.207179] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:37:pipe A] 00000000c29fdde8 state to 00000000c3c6da0f
>[13306.207204] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 000000000a70eae1 state to 00000000c3c6da0f
>[13306.207226] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 000000000a70eae1 to [CRTC:37:pipe A]
>[13306.207248] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:73] for plane state 000000000a70eae1
>[13306.207268] [drm:drm_atomic_check_only [drm]] checking 00000000c3c6da0f
>[13306.207367] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:37:pipe A] has [PLANE:28:plane 1A] with fb 73
>[13306.207440] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>[13306.207479] [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000c3c6da0f nonblocking
>[13306.223584] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000c3c6da0f
>[13306.223620] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000c3c6da0f
>[13306.223695] [drm:drm_mode_addfb2 [drm]] [FB:72]
>[13306.223747] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000001b090ced
>[13306.223779] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:37:pipe A] 000000002bdcbc00 state to 000000001b090ced
>[13306.223804] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 0000000031e1c40e state to 000000001b090ced
>[13306.223824] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 0000000031e1c40e to [CRTC:37:pipe A]
>[13306.223846] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:72] for plane state 0000000031e1c40e
>[13306.223867] [drm:drm_atomic_check_only [drm]] checking 000000001b090ced
>[13306.223968] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:37:pipe A] has [PLANE:28:plane 1A] with fb 72
>[13306.224043] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>[13306.224083] [drm:drm_atomic_nonblocking_commit [drm]] committing 000000001b090ced nonblocking
>[13306.240296] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000001b090ced
>[13306.240342] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000001b090ced
>[13306.240379] [drm:drm_mode_addfb2 [drm]] [FB:100]
>[13306.240422] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000007852f633
>[13306.240450] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:37:pipe A] 00000000f9e84c52 state to 000000007852f633
>[13306.240473] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 000000005eab7aa1 state to 000000007852f633
>[13306.240492] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 000000005eab7aa1 to [CRTC:37:pipe A]
>[13306.240514] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:100] for plane state 000000005eab7aa1
>[13306.240534] [drm:drm_atomic_check_only [drm]] checking 000000007852f633
>[13306.240624] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:37:pipe A] has [PLANE:28:plane 1A] with fb 100
>[13306.240712] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>[13306.240791] [drm:drm_atomic_nonblocking_commit [drm]] committing 000000007852f633 nonblocking
>[13306.256823] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000007852f633
>[13306.256869] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000007852f633
>[13306.256904] [drm:drm_mode_addfb2 [drm]] [FB:73]
>[13306.256952] [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000008c5b470
>[13306.256980] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:37:pipe A] 00000000cb5b7a04 state to 0000000008c5b470
>[13306.257003] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 000000005803cffc state to 0000000008c5b470
>[13306.257022] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 000000005803cffc to [CRTC:37:pipe A]
>[13306.257041] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:73] for plane state 000000005803cffc
>[13306.257061] [drm:drm_atomic_check_only [drm]] checking 0000000008c5b470
>[13306.257151] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:37:pipe A] has [PLANE:28:plane 1A] with fb 73
>[13306.257220] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>[13306.257259] [drm:drm_atomic_nonblocking_commit [drm]] committing 0000000008c5b470 nonblocking
>[13306.273589] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000008c5b470
>[13306.273624] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000008c5b470
>[13306.273700] [drm:drm_mode_addfb2 [drm]] [FB:72]
>[13306.273752] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000188bde80
>[13306.273784] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:37:pipe A] 00000000c1b3338d state to 00000000188bde80
>[13306.273810] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 000000003d0ae175 state to 00000000188bde80
>[13306.273832] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 000000003d0ae175 to [CRTC:37:pipe A]
>[13306.273854] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:72] for plane state 000000003d0ae175
>[13306.273875] [drm:drm_atomic_check_only [drm]] checking 00000000188bde80
>[13306.273973] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:37:pipe A] has [PLANE:28:plane 1A] with fb 72
>[13306.274048] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>[13306.274089] [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000188bde80 nonblocking
>[13306.290236] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000188bde80
>[13306.290271] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000188bde80
>[13306.290347] [drm:drm_mode_addfb2 [drm]] [FB:100]
>[13306.290398] [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000073c6a779
>[13306.290430] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:37:pipe A] 000000001a4a0b46 state to 0000000073c6a779
>[13306.290454] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 0000000075b6acb3 state to 0000000073c6a779
>[13306.290475] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 0000000075b6acb3 to [CRTC:37:pipe A]
>[13306.290497] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:100] for plane state 0000000075b6acb3
>[13306.290517] [drm:drm_atomic_check_only [drm]] checking 0000000073c6a779
>[13306.290616] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:37:pipe A] has [PLANE:28:plane 1A] with fb 100
>[13306.290692] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>[13306.290730] [drm:drm_atomic_nonblocking_commit [drm]] committing 0000000073c6a779 nonblocking
>[13306.306945] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000073c6a779
>[13306.306981] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000073c6a779
>[13306.307055] [drm:drm_mode_addfb2 [drm]] [FB:73]
>[13306.307106] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000011dd8b1
>[13306.307138] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:37:pipe A] 0000000031aec332 state to 00000000011dd8b1
>[13306.307163] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000c3574e6c state to 00000000011dd8b1
>[13306.307184] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 00000000c3574e6c to [CRTC:37:pipe A]
>[13306.307205] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:73] for plane state 00000000c3574e6c
>[13306.307227] [drm:drm_atomic_check_only [drm]] checking 00000000011dd8b1
>[13306.307325] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:37:pipe A] has [PLANE:28:plane 1A] with fb 73
>[13306.307400] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>[13306.307440] [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000011dd8b1 nonblocking
>[13306.323479] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000011dd8b1
>[13306.323514] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000011dd8b1
>[13306.323637] [drm:drm_mode_addfb2 [drm]] [FB:72]
>[13306.323688] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000f82ab298
>[13306.323720] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:37:pipe A] 000000008778a908 state to 00000000f82ab298
>[13306.323745] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000f78a2987 state to 00000000f82ab298
>[13306.323766] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 00000000f78a2987 to [CRTC:37:pipe A]
>[13306.323788] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:72] for plane state 00000000f78a2987
>[13306.323809] [drm:drm_atomic_check_only [drm]] checking 00000000f82ab298
>[13306.323908] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:37:pipe A] has [PLANE:28:plane 1A] with fb 72
>[13306.323983] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>[13306.324023] [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000f82ab298 nonblocking
>[13306.326651] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[13306.326733] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[13306.326856] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[13306.327356] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 00 00 04 00 0f 00 04
>[13306.327729] [drm:i915_hotplug_work_func [i915]] running encoder hotplug functions
>[13306.327795] [drm:i915_hotplug_work_func [i915]] Connector DP-1 (pin 5) received hotplug event.
>[13306.327856] [drm:intel_dp_detect [i915]] [CONNECTOR:56:DP-1]
>[13306.328273] [drm:lspcon_wake_native_aux_ch [i915]] Native AUX CH up, DPCD version: 1.2
>[13306.328387] [drm:lspcon_resume [i915]] LSPCON recovering in PCON mode after 0 ms
>[13306.328843] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13306.330123] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13306.331389] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13306.332643] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13306.333909] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13306.334790] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[13306.335263] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 00 00 04 00 0f 00 04
>[13306.335621] [drm:i915_hotplug_work_func [i915]] [CONNECTOR:56:DP-1] status updated from connected to disconnected
>[13306.340142] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000f82ab298
>[13306.340172] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000f82ab298
>[13306.340249] [drm:drm_mode_addfb2 [drm]] [FB:100]
>[13306.340294] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000bddb5861
>[13306.340323] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:37:pipe A] 00000000c587e801 state to 00000000bddb5861
>[13306.340345] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 000000006f595d3b state to 00000000bddb5861
>[13306.340364] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 000000006f595d3b to [CRTC:37:pipe A]
>[13306.340384] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:100] for plane state 000000006f595d3b
>[13306.340402] [drm:drm_atomic_check_only [drm]] checking 00000000bddb5861
>[13306.340485] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:37:pipe A] has [PLANE:28:plane 1A] with fb 100
>[13306.340552] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>[13306.340587] [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000bddb5861 nonblocking
>[13306.356808] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000bddb5861
>[13306.356836] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000bddb5861
>[13306.356894] [drm:drm_mode_addfb2 [drm]] [FB:73]
>[13306.356937] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000007a29ba0a
>[13306.356965] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:37:pipe A] 00000000833a4b1e state to 000000007a29ba0a
>[13306.356987] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 000000009a8bbc2f state to 000000007a29ba0a
>[13306.357006] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 000000009a8bbc2f to [CRTC:37:pipe A]
>[13306.357025] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:73] for plane state 000000009a8bbc2f
>[13306.357043] [drm:drm_atomic_check_only [drm]] checking 000000007a29ba0a
>[13306.357125] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:37:pipe A] has [PLANE:28:plane 1A] with fb 73
>[13306.357192] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>[13306.357228] [drm:drm_atomic_nonblocking_commit [drm]] committing 000000007a29ba0a nonblocking
>[13306.373478] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000007a29ba0a
>[13306.373508] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000007a29ba0a
>[13306.373567] [drm:drm_mode_addfb2 [drm]] [FB:72]
>[13306.373610] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000007a29ba0a
>[13306.373638] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:37:pipe A] 00000000e3a36978 state to 000000007a29ba0a
>[13306.373661] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 0000000004dbc7e6 state to 000000007a29ba0a
>[13306.373679] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 0000000004dbc7e6 to [CRTC:37:pipe A]
>[13306.373698] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:72] for plane state 0000000004dbc7e6
>[13306.373717] [drm:drm_atomic_check_only [drm]] checking 000000007a29ba0a
>[13306.373798] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:37:pipe A] has [PLANE:28:plane 1A] with fb 72
>[13306.373865] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>[13306.373898] [drm:drm_atomic_nonblocking_commit [drm]] committing 000000007a29ba0a nonblocking
>[13306.390145] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000007a29ba0a
>[13306.390175] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000007a29ba0a
>[13306.390233] [drm:drm_mode_addfb2 [drm]] [FB:100]
>[13306.390277] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000bddb5861
>[13306.390305] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:37:pipe A] 000000004b26cc25 state to 00000000bddb5861
>[13306.390326] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000539aef60 state to 00000000bddb5861
>[13306.390345] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 00000000539aef60 to [CRTC:37:pipe A]
>[13306.390364] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:100] for plane state 00000000539aef60
>[13306.390382] [drm:drm_atomic_check_only [drm]] checking 00000000bddb5861
>[13306.390463] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:37:pipe A] has [PLANE:28:plane 1A] with fb 100
>[13306.390529] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>[13306.390562] [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000bddb5861 nonblocking
>[13306.406807] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000bddb5861
>[13306.406837] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000bddb5861
>[13306.406895] [drm:drm_mode_addfb2 [drm]] [FB:73]
>[13306.406938] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000f82ab298
>[13306.406966] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:37:pipe A] 000000002b4a57bf state to 00000000f82ab298
>[13306.406988] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 0000000004dbc7e6 state to 00000000f82ab298
>[13306.407006] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 0000000004dbc7e6 to [CRTC:37:pipe A]
>[13306.407025] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:73] for plane state 0000000004dbc7e6
>[13306.407044] [drm:drm_atomic_check_only [drm]] checking 00000000f82ab298
>[13306.407124] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:37:pipe A] has [PLANE:28:plane 1A] with fb 73
>[13306.407192] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>[13306.407224] [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000f82ab298 nonblocking
>[13306.423479] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000f82ab298
>[13306.423508] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000f82ab298
>[13306.423574] [drm:drm_mode_addfb2 [drm]] [FB:72]
>[13306.423616] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000011dd8b1
>[13306.423644] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:37:pipe A] 00000000ae46a5f1 state to 00000000011dd8b1
>[13306.423666] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 000000009a8bbc2f state to 00000000011dd8b1
>[13306.423684] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 000000009a8bbc2f to [CRTC:37:pipe A]
>[13306.423704] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:72] for plane state 000000009a8bbc2f
>[13306.423723] [drm:drm_atomic_check_only [drm]] checking 00000000011dd8b1
>[13306.423803] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:37:pipe A] has [PLANE:28:plane 1A] with fb 72
>[13306.423871] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>[13306.423903] [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000011dd8b1 nonblocking
>[13306.440144] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000011dd8b1
>[13306.440173] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000011dd8b1
>[13306.440233] [drm:drm_mode_addfb2 [drm]] [FB:100]
>[13306.440276] [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000073c6a779
>[13306.440303] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:37:pipe A] 0000000047f25d70 state to 0000000073c6a779
>[13306.440326] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 000000006f595d3b state to 0000000073c6a779
>[13306.440344] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 000000006f595d3b to [CRTC:37:pipe A]
>[13306.440363] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:100] for plane state 000000006f595d3b
>[13306.440381] [drm:drm_atomic_check_only [drm]] checking 0000000073c6a779
>[13306.440462] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:37:pipe A] has [PLANE:28:plane 1A] with fb 100
>[13306.440529] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>[13306.440564] [drm:drm_atomic_nonblocking_commit [drm]] committing 0000000073c6a779 nonblocking
>[13306.456819] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000073c6a779
>[13306.456849] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000073c6a779
>[13306.456887] [drm:drm_mode_addfb2 [drm]] [FB:73]
>[13306.456930] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000188bde80
>[13306.456958] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:37:pipe A] 00000000c4c6bc67 state to 00000000188bde80
>[13306.456979] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000f78a2987 state to 00000000188bde80
>[13306.456997] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 00000000f78a2987 to [CRTC:37:pipe A]
>[13306.457016] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:73] for plane state 00000000f78a2987
>[13306.457034] [drm:drm_atomic_check_only [drm]] checking 00000000188bde80
>[13306.457115] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:37:pipe A] has [PLANE:28:plane 1A] with fb 73
>[13306.457182] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>[13306.457215] [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000188bde80 nonblocking
>[13306.473475] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000188bde80
>[13306.473506] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000188bde80
>[13306.473564] [drm:drm_mode_addfb2 [drm]] [FB:72]
>[13306.473607] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000004973833f
>[13306.473634] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:37:pipe A] 0000000047f25d70 state to 000000004973833f
>[13306.473657] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000c3574e6c state to 000000004973833f
>[13306.473676] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 00000000c3574e6c to [CRTC:37:pipe A]
>[13306.473695] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:72] for plane state 00000000c3574e6c
>[13306.473714] [drm:drm_atomic_check_only [drm]] checking 000000004973833f
>[13306.473795] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:37:pipe A] has [PLANE:28:plane 1A] with fb 72
>[13306.473861] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>[13306.473894] [drm:drm_atomic_nonblocking_commit [drm]] committing 000000004973833f nonblocking
>[13306.490145] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000004973833f
>[13306.490175] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000004973833f
>[13306.490232] [drm:drm_mode_addfb2 [drm]] [FB:100]
>[13306.490275] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000cbf564d9
>[13306.490303] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:37:pipe A] 00000000ae46a5f1 state to 00000000cbf564d9
>[13306.490325] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 0000000075b6acb3 state to 00000000cbf564d9
>[13306.490344] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 0000000075b6acb3 to [CRTC:37:pipe A]
>[13306.490362] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:100] for plane state 0000000075b6acb3
>[13306.490381] [drm:drm_atomic_check_only [drm]] checking 00000000cbf564d9
>[13306.490461] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:37:pipe A] has [PLANE:28:plane 1A] with fb 100
>[13306.490527] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>[13306.490560] [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000cbf564d9 nonblocking
>[13306.506818] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000cbf564d9
>[13306.506847] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000cbf564d9
>[13306.506944] [drm:drm_mode_addfb2 [drm]] [FB:73]
>[13306.506987] [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000023c1b2e4
>[13306.507015] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:37:pipe A] 000000002b4a57bf state to 0000000023c1b2e4
>[13306.507037] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 000000003d0ae175 state to 0000000023c1b2e4
>[13306.507056] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 000000003d0ae175 to [CRTC:37:pipe A]
>[13306.507075] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:73] for plane state 000000003d0ae175
>[13306.507094] [drm:drm_atomic_check_only [drm]] checking 0000000023c1b2e4
>[13306.507175] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:37:pipe A] has [PLANE:28:plane 1A] with fb 73
>[13306.507241] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>[13306.507275] [drm:drm_atomic_nonblocking_commit [drm]] committing 0000000023c1b2e4 nonblocking
>[13306.523474] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000023c1b2e4
>[13306.523503] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000023c1b2e4
>[13306.523569] [drm:drm_mode_addfb2 [drm]] [FB:72]
>[13306.523612] [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000059e36985
>[13306.523641] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:37:pipe A] 00000000831a44cb state to 0000000059e36985
>[13306.523663] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000a412ccc0 state to 0000000059e36985
>[13306.523681] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 00000000a412ccc0 to [CRTC:37:pipe A]
>[13306.523701] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:72] for plane state 00000000a412ccc0
>[13306.523719] [drm:drm_atomic_check_only [drm]] checking 0000000059e36985
>[13306.523800] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:37:pipe A] has [PLANE:28:plane 1A] with fb 72
>[13306.523866] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>[13306.523901] [drm:drm_atomic_nonblocking_commit [drm]] committing 0000000059e36985 nonblocking
>[13306.540145] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000059e36985
>[13306.540176] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000059e36985
>[13306.540234] [drm:drm_mode_addfb2 [drm]] [FB:100]
>[13306.540276] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000673f18d0
>[13306.540304] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:37:pipe A] 00000000195b8dec state to 00000000673f18d0
>[13306.540326] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000acbdfc95 state to 00000000673f18d0
>[13306.540345] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 00000000acbdfc95 to [CRTC:37:pipe A]
>[13306.540364] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:100] for plane state 00000000acbdfc95
>[13306.540382] [drm:drm_atomic_check_only [drm]] checking 00000000673f18d0
>[13306.540464] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:37:pipe A] has [PLANE:28:plane 1A] with fb 100
>[13306.540530] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>[13306.540563] [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000673f18d0 nonblocking
>[13306.556807] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000673f18d0
>[13306.556837] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000673f18d0
>[13306.556900] [drm:drm_mode_addfb2 [drm]] [FB:73]
>[13306.556945] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000a9dfda4c
>[13306.556972] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:37:pipe A] 0000000090a16d29 state to 00000000a9dfda4c
>[13306.556995] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 000000000a70eae1 state to 00000000a9dfda4c
>[13306.557014] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 000000000a70eae1 to [CRTC:37:pipe A]
>[13306.557033] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:73] for plane state 000000000a70eae1
>[13306.557051] [drm:drm_atomic_check_only [drm]] checking 00000000a9dfda4c
>[13306.557132] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:37:pipe A] has [PLANE:28:plane 1A] with fb 73
>[13306.557197] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>[13306.557230] [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000a9dfda4c nonblocking
>[13306.573478] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000a9dfda4c
>[13306.573508] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000a9dfda4c
>[13306.573567] [drm:drm_mode_addfb2 [drm]] [FB:72]
>[13306.573611] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000002b10bb9a
>[13306.573639] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:37:pipe A] 000000007316cf84 state to 000000002b10bb9a
>[13306.573662] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 000000005548a7b9 state to 000000002b10bb9a
>[13306.573681] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 000000005548a7b9 to [CRTC:37:pipe A]
>[13306.573700] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:72] for plane state 000000005548a7b9
>[13306.573718] [drm:drm_atomic_check_only [drm]] checking 000000002b10bb9a
>[13306.573799] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:37:pipe A] has [PLANE:28:plane 1A] with fb 72
>[13306.573866] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>[13306.573899] [drm:drm_atomic_nonblocking_commit [drm]] committing 000000002b10bb9a nonblocking
>[13306.590115] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000002b10bb9a
>[13306.590145] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000002b10bb9a
>[13306.590207] [drm:drm_mode_addfb2 [drm]] [FB:100]
>[13306.590250] [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000050b677f5
>[13306.590278] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:37:pipe A] 000000005a4eaefe state to 0000000050b677f5
>[13306.590300] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 0000000092f5bca8 state to 0000000050b677f5
>[13306.590318] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 0000000092f5bca8 to [CRTC:37:pipe A]
>[13306.590337] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:100] for plane state 0000000092f5bca8
>[13306.590355] [drm:drm_atomic_check_only [drm]] checking 0000000050b677f5
>[13306.590436] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:37:pipe A] has [PLANE:28:plane 1A] with fb 100
>[13306.590503] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>[13306.590536] [drm:drm_atomic_nonblocking_commit [drm]] committing 0000000050b677f5 nonblocking
>[13306.606811] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000050b677f5
>[13306.606840] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000050b677f5
>[13306.606901] [drm:drm_mode_addfb2 [drm]] [FB:73]
>[13306.606944] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000a8e115ec
>[13306.606971] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:37:pipe A] 000000007316cf84 state to 00000000a8e115ec
>[13306.606993] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000352e03e1 state to 00000000a8e115ec
>[13306.607012] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 00000000352e03e1 to [CRTC:37:pipe A]
>[13306.607031] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:73] for plane state 00000000352e03e1
>[13306.607049] [drm:drm_atomic_check_only [drm]] checking 00000000a8e115ec
>[13306.607132] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:37:pipe A] has [PLANE:28:plane 1A] with fb 73
>[13306.607200] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>[13306.607233] [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000a8e115ec nonblocking
>[13306.623612] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000a8e115ec
>[13306.623645] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000a8e115ec
>[13306.623714] [drm:drm_mode_addfb2 [drm]] [FB:72]
>[13306.623761] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000655b7f4f
>[13306.623790] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:37:pipe A] 0000000090a16d29 state to 00000000655b7f4f
>[13306.623812] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 0000000037564a37 state to 00000000655b7f4f
>[13306.623830] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 0000000037564a37 to [CRTC:37:pipe A]
>[13306.623849] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:72] for plane state 0000000037564a37
>[13306.623868] [drm:drm_atomic_check_only [drm]] checking 00000000655b7f4f
>[13306.623957] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:37:pipe A] has [PLANE:28:plane 1A] with fb 72
>[13306.624022] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>[13306.624059] [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000655b7f4f nonblocking
>[13306.640280] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000655b7f4f
>[13306.640312] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000655b7f4f
>[13306.640396] [drm:drm_mode_addfb2 [drm]] [FB:100]
>[13306.640443] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000e117d8ac
>[13306.640472] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:37:pipe A] 00000000c29fdde8 state to 00000000e117d8ac
>[13306.640494] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 0000000098d195b5 state to 00000000e117d8ac
>[13306.640513] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 0000000098d195b5 to [CRTC:37:pipe A]
>[13306.640532] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:100] for plane state 0000000098d195b5
>[13306.640550] [drm:drm_atomic_check_only [drm]] checking 00000000e117d8ac
>[13306.640640] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:37:pipe A] has [PLANE:28:plane 1A] with fb 100
>[13306.640706] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>[13306.640788] [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000e117d8ac nonblocking
>[13306.656924] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000e117d8ac
>[13306.656970] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000e117d8ac
>[13306.657009] [drm:drm_mode_addfb2 [drm]] [FB:73]
>[13306.657055] [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000008c5b470
>[13306.657083] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:37:pipe A] 00000000e95167d1 state to 0000000008c5b470
>[13306.657106] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000965dbc45 state to 0000000008c5b470
>[13306.657125] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 00000000965dbc45 to [CRTC:37:pipe A]
>[13306.657145] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:73] for plane state 00000000965dbc45
>[13306.657164] [drm:drm_atomic_check_only [drm]] checking 0000000008c5b470
>[13306.657254] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:37:pipe A] has [PLANE:28:plane 1A] with fb 73
>[13306.657326] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>[13306.657363] [drm:drm_atomic_nonblocking_commit [drm]] committing 0000000008c5b470 nonblocking
>[13306.673625] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000008c5b470
>[13306.673673] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000008c5b470
>[13306.673712] [drm:drm_mode_addfb2 [drm]] [FB:72]
>[13306.673756] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000007852f633
>[13306.673784] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:37:pipe A] 00000000011eb43e state to 000000007852f633
>[13306.673807] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 000000006fbd100d state to 000000007852f633
>[13306.673827] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 000000006fbd100d to [CRTC:37:pipe A]
>[13306.673846] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:72] for plane state 000000006fbd100d
>[13306.673865] [drm:drm_atomic_check_only [drm]] checking 000000007852f633
>[13306.673955] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:37:pipe A] has [PLANE:28:plane 1A] with fb 72
>[13306.674028] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>[13306.674064] [drm:drm_atomic_nonblocking_commit [drm]] committing 000000007852f633 nonblocking
>[13306.690306] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000007852f633
>[13306.690355] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000007852f633
>[13306.690456] [drm:drm_mode_addfb2 [drm]] [FB:100]
>[13306.690500] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000ae93f5ae
>[13306.690528] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:37:pipe A] 00000000aa74ea7e state to 00000000ae93f5ae
>[13306.690550] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 000000008dc332e1 state to 00000000ae93f5ae
>[13306.690570] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 000000008dc332e1 to [CRTC:37:pipe A]
>[13306.690590] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:100] for plane state 000000008dc332e1
>[13306.690609] [drm:drm_atomic_check_only [drm]] checking 00000000ae93f5ae
>[13306.690701] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:37:pipe A] has [PLANE:28:plane 1A] with fb 100
>[13306.690771] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>[13306.690808] [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000ae93f5ae nonblocking
>[13306.706914] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000ae93f5ae
>[13306.706961] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000ae93f5ae
>[13306.706999] [drm:drm_mode_addfb2 [drm]] [FB:73]
>[13306.707042] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000005b581ca4
>[13306.707070] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:37:pipe A] 00000000011eb43e state to 000000005b581ca4
>[13306.707092] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 0000000048a9246d state to 000000005b581ca4
>[13306.707111] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 0000000048a9246d to [CRTC:37:pipe A]
>[13306.707133] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:73] for plane state 0000000048a9246d
>[13306.707152] [drm:drm_atomic_check_only [drm]] checking 000000005b581ca4
>[13306.707244] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:37:pipe A] has [PLANE:28:plane 1A] with fb 73
>[13306.707314] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>[13306.707350] [drm:drm_atomic_nonblocking_commit [drm]] committing 000000005b581ca4 nonblocking
>[13306.723629] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000005b581ca4
>[13306.723675] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000005b581ca4
>[13306.723714] [drm:drm_mode_addfb2 [drm]] [FB:72]
>[13306.723759] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000005b581ca4
>[13306.723790] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:37:pipe A] 00000000e95167d1 state to 000000005b581ca4
>[13306.723812] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000cb2cac9c state to 000000005b581ca4
>[13306.723831] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 00000000cb2cac9c to [CRTC:37:pipe A]
>[13306.723850] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:72] for plane state 00000000cb2cac9c
>[13306.723869] [drm:drm_atomic_check_only [drm]] checking 000000005b581ca4
>[13306.723961] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:37:pipe A] has [PLANE:28:plane 1A] with fb 72
>[13306.724032] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>[13306.724069] [drm:drm_atomic_nonblocking_commit [drm]] committing 000000005b581ca4 nonblocking
>[13306.740256] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000005b581ca4
>[13306.740302] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000005b581ca4
>[13306.740340] [drm:drm_mode_addfb2 [drm]] [FB:100]
>[13306.740384] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000ae93f5ae
>[13306.740412] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:37:pipe A] 00000000cb5b7a04 state to 00000000ae93f5ae
>[13306.740434] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000ad15f8ed state to 00000000ae93f5ae
>[13306.740454] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 00000000ad15f8ed to [CRTC:37:pipe A]
>[13306.740474] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:100] for plane state 00000000ad15f8ed
>[13306.740493] [drm:drm_atomic_check_only [drm]] checking 00000000ae93f5ae
>[13306.740583] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:37:pipe A] has [PLANE:28:plane 1A] with fb 100
>[13306.740655] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>[13306.740704] [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000ae93f5ae nonblocking
>[13306.756964] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000ae93f5ae
>[13306.757010] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000ae93f5ae
>[13306.757048] [drm:drm_mode_addfb2 [drm]] [FB:73]
>[13306.757090] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000007852f633
>[13306.757118] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:37:pipe A] 00000000f9e84c52 state to 000000007852f633
>[13306.757141] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 000000000ea4b8e9 state to 000000007852f633
>[13306.757162] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 000000000ea4b8e9 to [CRTC:37:pipe A]
>[13306.757182] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:73] for plane state 000000000ea4b8e9
>[13306.757201] [drm:drm_atomic_check_only [drm]] checking 000000007852f633
>[13306.757292] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:37:pipe A] has [PLANE:28:plane 1A] with fb 73
>[13306.757363] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>[13306.757402] [drm:drm_atomic_nonblocking_commit [drm]] committing 000000007852f633 nonblocking
>[13306.773589] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000007852f633
>[13306.773632] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000007852f633
>[13306.773667] [drm:drm_mode_addfb2 [drm]] [FB:72]
>[13306.773707] [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000008c5b470
>[13306.773732] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:37:pipe A] 00000000cb62b58f state to 0000000008c5b470
>[13306.773752] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000bdd3b7ee state to 0000000008c5b470
>[13306.773768] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 00000000bdd3b7ee to [CRTC:37:pipe A]
>[13306.773786] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:72] for plane state 00000000bdd3b7ee
>[13306.773804] [drm:drm_atomic_check_only [drm]] checking 0000000008c5b470
>[13306.773885] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:37:pipe A] has [PLANE:28:plane 1A] with fb 72
>[13306.773948] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>[13306.773981] [drm:drm_atomic_nonblocking_commit [drm]] committing 0000000008c5b470 nonblocking
>[13306.790309] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000008c5b470
>[13306.790355] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000008c5b470
>[13306.790393] [drm:drm_mode_addfb2 [drm]] [FB:100]
>[13306.790435] [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000008c5b470
>[13306.790462] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:37:pipe A] 00000000eab1f375 state to 0000000008c5b470
>[13306.790485] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 0000000050eb1774 state to 0000000008c5b470
>[13306.790505] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 0000000050eb1774 to [CRTC:37:pipe A]
>[13306.790525] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:100] for plane state 0000000050eb1774
>[13306.790544] [drm:drm_atomic_check_only [drm]] checking 0000000008c5b470
>[13306.790635] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:37:pipe A] has [PLANE:28:plane 1A] with fb 100
>[13306.790709] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>[13306.790746] [drm:drm_atomic_nonblocking_commit [drm]] committing 0000000008c5b470 nonblocking
>[13306.806901] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000008c5b470
>[13306.806933] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000008c5b470
>[13306.807004] [drm:drm_mode_addfb2 [drm]] [FB:73]
>[13306.807051] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000ecd5a468
>[13306.807079] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:37:pipe A] 000000007e2acc52 state to 00000000ecd5a468
>[13306.807101] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 000000002362502f state to 00000000ecd5a468
>[13306.807120] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 000000002362502f to [CRTC:37:pipe A]
>[13306.807139] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:73] for plane state 000000002362502f
>[13306.807157] [drm:drm_atomic_check_only [drm]] checking 00000000ecd5a468
>[13306.807246] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:37:pipe A] has [PLANE:28:plane 1A] with fb 73
>[13306.807313] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>[13306.807348] [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000ecd5a468 nonblocking
>[13306.823619] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000ecd5a468
>[13306.823651] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000ecd5a468
>[13306.823719] [drm:drm_mode_addfb2 [drm]] [FB:72]
>[13306.823765] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000519f591b
>[13306.823794] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:37:pipe A] 000000002ecb330c state to 00000000519f591b
>[13306.823817] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000a818d5d5 state to 00000000519f591b
>[13306.823835] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 00000000a818d5d5 to [CRTC:37:pipe A]
>[13306.823855] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:72] for plane state 00000000a818d5d5
>[13306.823874] [drm:drm_atomic_check_only [drm]] checking 00000000519f591b
>[13306.823962] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:37:pipe A] has [PLANE:28:plane 1A] with fb 72
>[13306.824029] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>[13306.824066] [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000519f591b nonblocking
>[13306.840141] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000519f591b
>[13306.840177] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000519f591b
>[13306.840246] [drm:drm_mode_addfb2 [drm]] [FB:100]
>[13306.840297] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000519f591b
>[13306.840330] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:37:pipe A] 00000000c3f4c3f2 state to 00000000519f591b
>[13306.840354] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 000000006542467b state to 00000000519f591b
>[13306.840375] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 000000006542467b to [CRTC:37:pipe A]
>[13306.840397] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:100] for plane state 000000006542467b
>[13306.840419] [drm:drm_atomic_check_only [drm]] checking 00000000519f591b
>[13306.840516] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:37:pipe A] has [PLANE:28:plane 1A] with fb 100
>[13306.840591] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>[13306.840630] [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000519f591b nonblocking
>[13306.856938] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000519f591b
>[13306.856970] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000519f591b
>[13306.857039] [drm:drm_mode_addfb2 [drm]] [FB:73]
>[13306.857086] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000ecd5a468
>[13306.857115] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:37:pipe A] 000000002ecb330c state to 00000000ecd5a468
>[13306.857137] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000c3e87dde state to 00000000ecd5a468
>[13306.857155] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 00000000c3e87dde to [CRTC:37:pipe A]
>[13306.857174] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:73] for plane state 00000000c3e87dde
>[13306.857193] [drm:drm_atomic_check_only [drm]] checking 00000000ecd5a468
>[13306.857282] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:37:pipe A] has [PLANE:28:plane 1A] with fb 73
>[13306.857372] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>[13306.857412] [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000ecd5a468 nonblocking
>[13306.873589] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000ecd5a468
>[13306.873621] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000ecd5a468
>[13306.873691] [drm:drm_mode_addfb2 [drm]] [FB:72]
>[13306.873737] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000006930b708
>[13306.873766] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:37:pipe A] 000000007e2acc52 state to 000000006930b708
>[13306.873788] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000be77e3d8 state to 000000006930b708
>[13306.873807] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 00000000be77e3d8 to [CRTC:37:pipe A]
>[13306.873826] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:72] for plane state 00000000be77e3d8
>[13306.873844] [drm:drm_atomic_check_only [drm]] checking 000000006930b708
>[13306.873934] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:37:pipe A] has [PLANE:28:plane 1A] with fb 72
>[13306.874004] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>[13306.874040] [drm:drm_atomic_nonblocking_commit [drm]] committing 000000006930b708 nonblocking
>[13306.890153] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000006930b708
>[13306.890187] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000006930b708
>[13306.890306] [drm:drm_mode_addfb2 [drm]] [FB:100]
>[13306.890356] [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000018d8a6eb
>[13306.890388] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:37:pipe A] 00000000c3397572 state to 0000000018d8a6eb
>[13306.890413] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 000000007b859555 state to 0000000018d8a6eb
>[13306.890434] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 000000007b859555 to [CRTC:37:pipe A]
>[13306.890455] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:100] for plane state 000000007b859555
>[13306.890477] [drm:drm_atomic_check_only [drm]] checking 0000000018d8a6eb
>[13306.890575] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:37:pipe A] has [PLANE:28:plane 1A] with fb 100
>[13306.890651] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>[13306.890691] [drm:drm_atomic_nonblocking_commit [drm]] committing 0000000018d8a6eb nonblocking
>[13306.906928] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000018d8a6eb
>[13306.906965] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000018d8a6eb
>[13306.907036] [drm:drm_mode_addfb2 [drm]] [FB:73]
>[13306.907088] [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000018d8a6eb
>[13306.907121] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:37:pipe A] 00000000490de0c7 state to 0000000018d8a6eb
>[13306.907147] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 0000000040ed3e2b state to 0000000018d8a6eb
>[13306.907169] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 0000000040ed3e2b to [CRTC:37:pipe A]
>[13306.907191] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:73] for plane state 0000000040ed3e2b
>[13306.907212] [drm:drm_atomic_check_only [drm]] checking 0000000018d8a6eb
>[13306.907311] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:37:pipe A] has [PLANE:28:plane 1A] with fb 73
>[13306.907386] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>[13306.907425] [drm:drm_atomic_nonblocking_commit [drm]] committing 0000000018d8a6eb nonblocking
>[13306.923625] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000018d8a6eb
>[13306.923661] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000018d8a6eb
>[13306.923733] [drm:drm_mode_addfb2 [drm]] [FB:72]
>[13306.923784] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000006930b708
>[13306.923819] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:37:pipe A] 0000000060dc7769 state to 000000006930b708
>[13306.923844] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000f91cfa69 state to 000000006930b708
>[13306.923865] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 00000000f91cfa69 to [CRTC:37:pipe A]
>[13306.923886] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:72] for plane state 00000000f91cfa69
>[13306.923907] [drm:drm_atomic_check_only [drm]] checking 000000006930b708
>[13306.924007] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:37:pipe A] has [PLANE:28:plane 1A] with fb 72
>[13306.924081] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>[13306.924119] [drm:drm_atomic_nonblocking_commit [drm]] committing 000000006930b708 nonblocking
>[13306.940240] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000006930b708
>[13306.940275] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000006930b708
>[13306.940363] [drm:drm_mode_addfb2 [drm]] [FB:100]
>[13306.940409] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000ecd5a468
>[13306.940438] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:37:pipe A] 00000000a2fe8a32 state to 00000000ecd5a468
>[13306.940460] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 000000005c025013 state to 00000000ecd5a468
>[13306.940479] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 000000005c025013 to [CRTC:37:pipe A]
>[13306.940499] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:100] for plane state 000000005c025013
>[13306.940518] [drm:drm_atomic_check_only [drm]] checking 00000000ecd5a468
>[13306.940607] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:37:pipe A] has [PLANE:28:plane 1A] with fb 100
>[13306.940674] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>[13306.940758] [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000ecd5a468 nonblocking
>[13306.956943] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000ecd5a468
>[13306.956980] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000ecd5a468
>[13306.957051] [drm:drm_mode_addfb2 [drm]] [FB:73]
>[13306.957102] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000519f591b
>[13306.957135] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:37:pipe A] 00000000cec4efc9 state to 00000000519f591b
>[13306.957160] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 000000009a9ec329 state to 00000000519f591b
>[13306.957181] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 000000009a9ec329 to [CRTC:37:pipe A]
>[13306.957202] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:73] for plane state 000000009a9ec329
>[13306.957224] [drm:drm_atomic_check_only [drm]] checking 00000000519f591b
>[13306.957322] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:37:pipe A] has [PLANE:28:plane 1A] with fb 73
>[13306.957398] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>[13306.957439] [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000519f591b nonblocking
>[13306.973492] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000519f591b
>[13306.973527] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000519f591b
>[13306.973598] [drm:drm_mode_addfb2 [drm]] [FB:72]
>[13306.973649] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000519f591b
>[13306.973681] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:37:pipe A] 000000004c9825e5 state to 00000000519f591b
>[13306.973705] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000fb0e84d4 state to 00000000519f591b
>[13306.973727] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 00000000fb0e84d4 to [CRTC:37:pipe A]
>[13306.973748] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:72] for plane state 00000000fb0e84d4
>[13306.973769] [drm:drm_atomic_check_only [drm]] checking 00000000519f591b
>[13306.973868] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:37:pipe A] has [PLANE:28:plane 1A] with fb 72
>[13306.973943] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>[13306.973983] [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000519f591b nonblocking
>[13306.990270] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000519f591b
>[13306.990307] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000519f591b
>[13306.990379] [drm:drm_mode_addfb2 [drm]] [FB:100]
>[13306.990429] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000ecd5a468
>[13306.990461] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:37:pipe A] 000000007e4dcb27 state to 00000000ecd5a468
>[13306.990487] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 000000001e7dfef6 state to 00000000ecd5a468
>[13306.990508] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 000000001e7dfef6 to [CRTC:37:pipe A]
>[13306.990530] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:100] for plane state 000000001e7dfef6
>[13306.990550] [drm:drm_atomic_check_only [drm]] checking 00000000ecd5a468
>[13306.990649] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:37:pipe A] has [PLANE:28:plane 1A] with fb 100
>[13306.990725] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>[13306.990764] [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000ecd5a468 nonblocking
>[13307.006952] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000ecd5a468
>[13307.006987] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000ecd5a468
>[13307.007069] [drm:drm_mode_addfb2 [drm]] [FB:73]
>[13307.007120] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000006930b708
>[13307.007152] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:37:pipe A] 0000000020fe975a state to 000000006930b708
>[13307.007177] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000f576052d state to 000000006930b708
>[13307.007199] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 00000000f576052d to [CRTC:37:pipe A]
>[13307.007221] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:73] for plane state 00000000f576052d
>[13307.007242] [drm:drm_atomic_check_only [drm]] checking 000000006930b708
>[13307.007339] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:37:pipe A] has [PLANE:28:plane 1A] with fb 73
>[13307.007414] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>[13307.007453] [drm:drm_atomic_nonblocking_commit [drm]] committing 000000006930b708 nonblocking
>[13307.023580] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000006930b708
>[13307.023616] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000006930b708
>[13307.023691] [drm:drm_mode_addfb2 [drm]] [FB:72]
>[13307.023743] [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000039b5c9bd
>[13307.023775] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:37:pipe A] 000000004b26cc25 state to 0000000039b5c9bd
>[13307.023800] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 000000008524721e state to 0000000039b5c9bd
>[13307.023821] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 000000008524721e to [CRTC:37:pipe A]
>[13307.023842] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:72] for plane state 000000008524721e
>[13307.023863] [drm:drm_atomic_check_only [drm]] checking 0000000039b5c9bd
>[13307.023961] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:37:pipe A] has [PLANE:28:plane 1A] with fb 72
>[13307.024034] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>[13307.024074] [drm:drm_atomic_nonblocking_commit [drm]] committing 0000000039b5c9bd nonblocking
>[13307.040285] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000039b5c9bd
>[13307.040321] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000039b5c9bd
>[13307.040397] [drm:drm_mode_addfb2 [drm]] [FB:100]
>[13307.040449] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000003d7cb2d5
>[13307.040480] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:37:pipe A] 000000006b24b9fc state to 000000003d7cb2d5
>[13307.040506] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 000000005ef6bffe state to 000000003d7cb2d5
>[13307.040528] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 000000005ef6bffe to [CRTC:37:pipe A]
>[13307.040550] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:100] for plane state 000000005ef6bffe
>[13307.040570] [drm:drm_atomic_check_only [drm]] checking 000000003d7cb2d5
>[13307.040672] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:37:pipe A] has [PLANE:28:plane 1A] with fb 100
>[13307.040802] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>[13307.040874] [drm:drm_atomic_nonblocking_commit [drm]] committing 000000003d7cb2d5 nonblocking
>[13307.056907] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000003d7cb2d5
>[13307.056944] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000003d7cb2d5
>[13307.057019] [drm:drm_mode_addfb2 [drm]] [FB:73]
>[13307.057071] [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000090f0f9e4
>[13307.057103] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:37:pipe A] 0000000009db94e4 state to 0000000090f0f9e4
>[13307.057128] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000f6d6481c state to 0000000090f0f9e4
>[13307.057150] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 00000000f6d6481c to [CRTC:37:pipe A]
>[13307.057171] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:73] for plane state 00000000f6d6481c
>[13307.057192] [drm:drm_atomic_check_only [drm]] checking 0000000090f0f9e4
>[13307.057291] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:37:pipe A] has [PLANE:28:plane 1A] with fb 73
>[13307.057365] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>[13307.057406] [drm:drm_atomic_nonblocking_commit [drm]] committing 0000000090f0f9e4 nonblocking
>[13307.073621] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000090f0f9e4
>[13307.073657] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000090f0f9e4
>[13307.073780] [drm:drm_mode_addfb2 [drm]] [FB:72]
>[13307.073830] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000289ae621
>[13307.073862] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:37:pipe A] 000000006794fe06 state to 00000000289ae621
>[13307.073888] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000526a3ced state to 00000000289ae621
>[13307.073909] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 00000000526a3ced to [CRTC:37:pipe A]
>[13307.073931] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:72] for plane state 00000000526a3ced
>[13307.073952] [drm:drm_atomic_check_only [drm]] checking 00000000289ae621
>[13307.074050] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:37:pipe A] has [PLANE:28:plane 1A] with fb 72
>[13307.074124] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>[13307.074163] [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000289ae621 nonblocking
>[13307.090277] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000289ae621
>[13307.090311] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000289ae621
>[13307.090387] [drm:drm_mode_addfb2 [drm]] [FB:100]
>[13307.090439] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000006855391c
>[13307.090471] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:37:pipe A] 00000000d9d9b155 state to 000000006855391c
>[13307.090495] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000013da2e3 state to 000000006855391c
>[13307.090517] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 00000000013da2e3 to [CRTC:37:pipe A]
>[13307.090538] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:100] for plane state 00000000013da2e3
>[13307.090560] [drm:drm_atomic_check_only [drm]] checking 000000006855391c
>[13307.090661] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:37:pipe A] has [PLANE:28:plane 1A] with fb 100
>[13307.090735] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>[13307.090774] [drm:drm_atomic_nonblocking_commit [drm]] committing 000000006855391c nonblocking
>[13307.106926] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000006855391c
>[13307.106961] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000006855391c
>[13307.107036] [drm:drm_mode_addfb2 [drm]] [FB:73]
>[13307.107088] [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000099b1e95b
>[13307.107120] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:37:pipe A] 0000000081e9cf65 state to 0000000099b1e95b
>[13307.107145] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000dac4373f state to 0000000099b1e95b
>[13307.107166] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 00000000dac4373f to [CRTC:37:pipe A]
>[13307.107188] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:73] for plane state 00000000dac4373f
>[13307.107209] [drm:drm_atomic_check_only [drm]] checking 0000000099b1e95b
>[13307.107307] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:37:pipe A] has [PLANE:28:plane 1A] with fb 73
>[13307.107381] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>[13307.107421] [drm:drm_atomic_nonblocking_commit [drm]] committing 0000000099b1e95b nonblocking
>[13307.110644] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00400000, dig 0x10101110, pins 0x00000040
>[13307.110722] [drm:intel_hpd_irq_handler [i915]] digital hpd port C - short
>[13307.110833] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port C - short
>[13307.111341] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 00 02 02 06 03 00 00 00
>[13307.123441] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000099b1e95b
>[13307.123469] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000099b1e95b
>[13307.123543] [drm:drm_mode_addfb2 [drm]] [FB:72]
>[13307.123589] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000e880ab74
>[13307.123618] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:37:pipe A] 00000000e1fcf8a7 state to 00000000e880ab74
>[13307.123641] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 000000005322e91b state to 00000000e880ab74
>[13307.123660] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 000000005322e91b to [CRTC:37:pipe A]
>[13307.123679] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:72] for plane state 000000005322e91b
>[13307.123698] [drm:drm_atomic_check_only [drm]] checking 00000000e880ab74
>[13307.123781] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:37:pipe A] has [PLANE:28:plane 1A] with fb 72
>[13307.123849] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>[13307.123885] [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000e880ab74 nonblocking
>[13307.140262] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000e880ab74
>[13307.140293] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000e880ab74
>[13307.140363] [drm:drm_mode_addfb2 [drm]] [FB:100]
>[13307.140409] [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000001fbffed
>[13307.140437] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:37:pipe A] 00000000fae58dee state to 0000000001fbffed
>[13307.140460] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 000000002969d135 state to 0000000001fbffed
>[13307.140479] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 000000002969d135 to [CRTC:37:pipe A]
>[13307.140498] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:100] for plane state 000000002969d135
>[13307.140517] [drm:drm_atomic_check_only [drm]] checking 0000000001fbffed
>[13307.140606] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:37:pipe A] has [PLANE:28:plane 1A] with fb 100
>[13307.140672] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>[13307.140758] [drm:drm_atomic_nonblocking_commit [drm]] committing 0000000001fbffed nonblocking
>[13307.156953] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000001fbffed
>[13307.156984] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000001fbffed
>[13307.157058] [drm:drm_mode_addfb2 [drm]] [FB:73]
>[13307.157105] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000006202e550
>[13307.157136] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:37:pipe A] 0000000024d204e2 state to 000000006202e550
>[13307.157159] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000731b73cd state to 000000006202e550
>[13307.157177] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 00000000731b73cd to [CRTC:37:pipe A]
>[13307.157197] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:73] for plane state 00000000731b73cd
>[13307.157216] [drm:drm_atomic_check_only [drm]] checking 000000006202e550
>[13307.157306] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:37:pipe A] has [PLANE:28:plane 1A] with fb 73
>[13307.157373] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>[13307.157409] [drm:drm_atomic_nonblocking_commit [drm]] committing 000000006202e550 nonblocking
>[13307.173562] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000006202e550
>[13307.173594] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000006202e550
>[13307.173668] [drm:drm_mode_addfb2 [drm]] [FB:72]
>[13307.173714] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000b714ca26
>[13307.173742] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:37:pipe A] 0000000018046d93 state to 00000000b714ca26
>[13307.173764] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000f537d65b state to 00000000b714ca26
>[13307.173783] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 00000000f537d65b to [CRTC:37:pipe A]
>[13307.173802] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:72] for plane state 00000000f537d65b
>[13307.173821] [drm:drm_atomic_check_only [drm]] checking 00000000b714ca26
>[13307.173911] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:37:pipe A] has [PLANE:28:plane 1A] with fb 72
>[13307.173977] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>[13307.174013] [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000b714ca26 nonblocking
>[13307.190275] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000b714ca26
>[13307.190307] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000b714ca26
>[13307.190377] [drm:drm_mode_addfb2 [drm]] [FB:100]
>[13307.190423] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000004cdc04ee
>[13307.190452] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:37:pipe A] 00000000fd63c90d state to 000000004cdc04ee
>[13307.190474] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000b4b233b5 state to 000000004cdc04ee
>[13307.190493] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 00000000b4b233b5 to [CRTC:37:pipe A]
>[13307.190512] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:100] for plane state 00000000b4b233b5
>[13307.190531] [drm:drm_atomic_check_only [drm]] checking 000000004cdc04ee
>[13307.190620] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:37:pipe A] has [PLANE:28:plane 1A] with fb 100
>[13307.190686] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>[13307.190722] [drm:drm_atomic_nonblocking_commit [drm]] committing 000000004cdc04ee nonblocking
>[13307.206853] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000004cdc04ee
>[13307.206884] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000004cdc04ee
>[13307.206963] [drm:drm_mode_addfb2 [drm]] [FB:73]
>[13307.207011] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000004cdc04ee
>[13307.207040] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:37:pipe A] 000000007b1f6733 state to 000000004cdc04ee
>[13307.207061] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 000000002632017f state to 000000004cdc04ee
>[13307.207080] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 000000002632017f to [CRTC:37:pipe A]
>[13307.207099] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:73] for plane state 000000002632017f
>[13307.207118] [drm:drm_atomic_check_only [drm]] checking 000000004cdc04ee
>[13307.207209] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:37:pipe A] has [PLANE:28:plane 1A] with fb 73
>[13307.207275] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>[13307.207310] [drm:drm_atomic_nonblocking_commit [drm]] committing 000000004cdc04ee nonblocking
>[13307.223589] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000004cdc04ee
>[13307.223625] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000004cdc04ee
>[13307.223698] [drm:drm_mode_addfb2 [drm]] [FB:72]
>[13307.223748] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000b714ca26
>[13307.223780] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:37:pipe A] 0000000008dd7b22 state to 00000000b714ca26
>[13307.223805] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000369edf06 state to 00000000b714ca26
>[13307.223825] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 00000000369edf06 to [CRTC:37:pipe A]
>[13307.223847] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:72] for plane state 00000000369edf06
>[13307.223868] [drm:drm_atomic_check_only [drm]] checking 00000000b714ca26
>[13307.223967] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:37:pipe A] has [PLANE:28:plane 1A] with fb 72
>[13307.224041] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>[13307.224080] [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000b714ca26 nonblocking
>[13307.240288] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000b714ca26
>[13307.240339] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000b714ca26
>[13307.240410] [drm:drm_mode_addfb2 [drm]] [FB:100]
>[13307.240457] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000797fb672
>[13307.240486] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:37:pipe A] 00000000d5a4f9c2 state to 00000000797fb672
>[13307.240508] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000e4648534 state to 00000000797fb672
>[13307.240527] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 00000000e4648534 to [CRTC:37:pipe A]
>[13307.240547] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:100] for plane state 00000000e4648534
>[13307.240565] [drm:drm_atomic_check_only [drm]] checking 00000000797fb672
>[13307.240656] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:37:pipe A] has [PLANE:28:plane 1A] with fb 100
>[13307.240726] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>[13307.240792] [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000797fb672 nonblocking
>[13307.256898] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000797fb672
>[13307.256932] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000797fb672
>[13307.257066] [drm:drm_mode_addfb2 [drm]] [FB:73]
>[13307.257118] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000009d28d480
>[13307.257150] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:37:pipe A] 00000000ac4c4e48 state to 000000009d28d480
>[13307.257175] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 000000004265ae89 state to 000000009d28d480
>[13307.257196] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 000000004265ae89 to [CRTC:37:pipe A]
>[13307.257218] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:73] for plane state 000000004265ae89
>[13307.257240] [drm:drm_atomic_check_only [drm]] checking 000000009d28d480
>[13307.257339] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:37:pipe A] has [PLANE:28:plane 1A] with fb 73
>[13307.257414] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>[13307.257453] [drm:drm_atomic_nonblocking_commit [drm]] committing 000000009d28d480 nonblocking
>[13307.273590] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000009d28d480
>[13307.273625] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000009d28d480
>[13307.273701] [drm:drm_mode_addfb2 [drm]] [FB:72]
>[13307.273753] [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000018d8a6eb
>[13307.273784] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:37:pipe A] 00000000c0842b5f state to 0000000018d8a6eb
>[13307.273810] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 000000000d969d9a state to 0000000018d8a6eb
>[13307.273831] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 000000000d969d9a to [CRTC:37:pipe A]
>[13307.273852] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:72] for plane state 000000000d969d9a
>[13307.273873] [drm:drm_atomic_check_only [drm]] checking 0000000018d8a6eb
>[13307.273970] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:37:pipe A] has [PLANE:28:plane 1A] with fb 72
>[13307.274042] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>[13307.274082] [drm:drm_atomic_nonblocking_commit [drm]] committing 0000000018d8a6eb nonblocking
>[13307.290157] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000018d8a6eb
>[13307.290191] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000018d8a6eb
>[13307.290273] [drm:drm_mode_addfb2 [drm]] [FB:100]
>[13307.290325] [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000018d8a6eb
>[13307.290357] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:37:pipe A] 0000000079c36b37 state to 0000000018d8a6eb
>[13307.290382] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 000000009713ae7d state to 0000000018d8a6eb
>[13307.290404] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 000000009713ae7d to [CRTC:37:pipe A]
>[13307.290426] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:100] for plane state 000000009713ae7d
>[13307.290447] [drm:drm_atomic_check_only [drm]] checking 0000000018d8a6eb
>[13307.290545] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:37:pipe A] has [PLANE:28:plane 1A] with fb 100
>[13307.290620] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>[13307.290659] [drm:drm_atomic_nonblocking_commit [drm]] committing 0000000018d8a6eb nonblocking
>[13307.306928] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000018d8a6eb
>[13307.306964] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000018d8a6eb
>[13307.307036] [drm:drm_mode_addfb2 [drm]] [FB:73]
>[13307.307088] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000006930b708
>[13307.307119] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:37:pipe A] 00000000ae5bcee3 state to 000000006930b708
>[13307.307144] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000affa3c56 state to 000000006930b708
>[13307.307165] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 00000000affa3c56 to [CRTC:37:pipe A]
>[13307.307187] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:73] for plane state 00000000affa3c56
>[13307.307208] [drm:drm_atomic_check_only [drm]] checking 000000006930b708
>[13307.307305] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:37:pipe A] has [PLANE:28:plane 1A] with fb 73
>[13307.307381] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>[13307.307421] [drm:drm_atomic_nonblocking_commit [drm]] committing 000000006930b708 nonblocking
>[13307.323628] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000006930b708
>[13307.323663] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000006930b708
>[13307.323743] [drm:drm_mode_addfb2 [drm]] [FB:72]
>[13307.323794] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000ecd5a468
>[13307.323826] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:37:pipe A] 00000000644f71c0 state to 00000000ecd5a468
>[13307.323852] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000bdd7538d state to 00000000ecd5a468
>[13307.323874] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 00000000bdd7538d to [CRTC:37:pipe A]
>[13307.323895] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:72] for plane state 00000000bdd7538d
>[13307.323916] [drm:drm_atomic_check_only [drm]] checking 00000000ecd5a468
>[13307.324015] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:37:pipe A] has [PLANE:28:plane 1A] with fb 72
>[13307.324089] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>[13307.324128] [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000ecd5a468 nonblocking
>[13307.340249] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000ecd5a468
>[13307.340286] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000ecd5a468
>[13307.340359] [drm:drm_mode_addfb2 [drm]] [FB:100]
>[13307.340410] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000519f591b
>[13307.340441] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:37:pipe A] 00000000e6172a1a state to 00000000519f591b
>[13307.340466] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000a8a36f80 state to 00000000519f591b
>[13307.340487] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 00000000a8a36f80 to [CRTC:37:pipe A]
>[13307.340509] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:100] for plane state 00000000a8a36f80
>[13307.340529] [drm:drm_atomic_check_only [drm]] checking 00000000519f591b
>[13307.340628] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:37:pipe A] has [PLANE:28:plane 1A] with fb 100
>[13307.340704] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>[13307.340797] [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000519f591b nonblocking
>[13307.356959] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000519f591b
>[13307.356995] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000519f591b
>[13307.357064] [drm:drm_mode_addfb2 [drm]] [FB:73]
>[13307.357115] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000519f591b
>[13307.357147] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:37:pipe A] 00000000644f71c0 state to 00000000519f591b
>[13307.357172] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 0000000058082892 state to 00000000519f591b
>[13307.357193] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 0000000058082892 to [CRTC:37:pipe A]
>[13307.357215] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:73] for plane state 0000000058082892
>[13307.357236] [drm:drm_atomic_check_only [drm]] checking 00000000519f591b
>[13307.357335] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:37:pipe A] has [PLANE:28:plane 1A] with fb 73
>[13307.357413] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>[13307.357452] [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000519f591b nonblocking
>[13307.373487] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000519f591b
>[13307.373521] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000519f591b
>[13307.373589] [drm:drm_mode_addfb2 [drm]] [FB:72]
>[13307.373640] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000ecd5a468
>[13307.373672] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:37:pipe A] 00000000ae5bcee3 state to 00000000ecd5a468
>[13307.373697] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 0000000065c83b50 state to 00000000ecd5a468
>[13307.373718] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 0000000065c83b50 to [CRTC:37:pipe A]
>[13307.373740] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:72] for plane state 0000000065c83b50
>[13307.373760] [drm:drm_atomic_check_only [drm]] checking 00000000ecd5a468
>[13307.373859] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:37:pipe A] has [PLANE:28:plane 1A] with fb 72
>[13307.373933] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>[13307.373973] [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000ecd5a468 nonblocking
>[13307.390258] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000ecd5a468
>[13307.390308] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000ecd5a468
>[13307.390381] [drm:drm_mode_addfb2 [drm]] [FB:100]
>[13307.390433] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000006930b708
>[13307.390465] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:37:pipe A] 0000000079c36b37 state to 000000006930b708
>[13307.390491] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 0000000058082892 state to 000000006930b708
>[13307.390513] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 0000000058082892 to [CRTC:37:pipe A]
>[13307.390535] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:100] for plane state 0000000058082892
>[13307.390557] [drm:drm_atomic_check_only [drm]] checking 000000006930b708
>[13307.390656] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:37:pipe A] has [PLANE:28:plane 1A] with fb 100
>[13307.390731] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>[13307.390771] [drm:drm_atomic_nonblocking_commit [drm]] committing 000000006930b708 nonblocking
>[13307.406955] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000006930b708
>[13307.407002] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000006930b708
>[13307.407073] [drm:drm_mode_addfb2 [drm]] [FB:73]
>[13307.407124] [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000018d8a6eb
>[13307.407157] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:37:pipe A] 00000000c0842b5f state to 0000000018d8a6eb
>[13307.407182] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000a8a36f80 state to 0000000018d8a6eb
>[13307.407203] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 00000000a8a36f80 to [CRTC:37:pipe A]
>[13307.407225] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:73] for plane state 00000000a8a36f80
>[13307.407246] [drm:drm_atomic_check_only [drm]] checking 0000000018d8a6eb
>[13307.407344] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:37:pipe A] has [PLANE:28:plane 1A] with fb 73
>[13307.407420] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>[13307.407460] [drm:drm_atomic_nonblocking_commit [drm]] committing 0000000018d8a6eb nonblocking
>[13307.423584] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000018d8a6eb
>[13307.423619] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000018d8a6eb
>[13307.423691] [drm:drm_mode_addfb2 [drm]] [FB:72]
>[13307.423742] [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000044644630
>[13307.423774] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:37:pipe A] 00000000e3a36978 state to 0000000044644630
>[13307.423799] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 0000000082e1e0e3 state to 0000000044644630
>[13307.423821] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 0000000082e1e0e3 to [CRTC:37:pipe A]
>[13307.423842] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:72] for plane state 0000000082e1e0e3
>[13307.423863] [drm:drm_atomic_check_only [drm]] checking 0000000044644630
>[13307.423962] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:37:pipe A] has [PLANE:28:plane 1A] with fb 72
>[13307.424035] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>[13307.424074] [drm:drm_atomic_nonblocking_commit [drm]] committing 0000000044644630 nonblocking
>[13307.440288] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000044644630
>[13307.440323] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000044644630
>[13307.440444] [drm:drm_mode_addfb2 [drm]] [FB:100]
>[13307.440496] [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000044644630
>[13307.440528] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:37:pipe A] 00000000833a4b1e state to 0000000044644630
>[13307.440554] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 0000000057809ef2 state to 0000000044644630
>[13307.440575] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 0000000057809ef2 to [CRTC:37:pipe A]
>[13307.440596] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:100] for plane state 0000000057809ef2
>[13307.440617] [drm:drm_atomic_check_only [drm]] checking 0000000044644630
>[13307.440716] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:37:pipe A] has [PLANE:28:plane 1A] with fb 100
>[13307.440821] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>[13307.440869] [drm:drm_atomic_nonblocking_commit [drm]] committing 0000000044644630 nonblocking
>[13307.456838] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000044644630
>[13307.456874] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000044644630
>[13307.456946] [drm:drm_mode_addfb2 [drm]] [FB:73]
>[13307.456997] [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000039b5c9bd
>[13307.457028] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:37:pipe A] 00000000c587e801 state to 0000000039b5c9bd
>[13307.457053] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000fd3dae45 state to 0000000039b5c9bd
>[13307.457075] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 00000000fd3dae45 to [CRTC:37:pipe A]
>[13307.457097] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:73] for plane state 00000000fd3dae45
>[13307.457118] [drm:drm_atomic_check_only [drm]] checking 0000000039b5c9bd
>[13307.457218] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:37:pipe A] has [PLANE:28:plane 1A] with fb 73
>[13307.457293] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>[13307.457332] [drm:drm_atomic_nonblocking_commit [drm]] committing 0000000039b5c9bd nonblocking
>[13307.473610] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000039b5c9bd
>[13307.473646] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000039b5c9bd
>[13307.473716] [drm:drm_mode_addfb2 [drm]] [FB:72]
>[13307.473769] [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000018d8a6eb
>[13307.473801] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:37:pipe A] 0000000020fe975a state to 0000000018d8a6eb
>[13307.473825] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000bdd7538d state to 0000000018d8a6eb
>[13307.473847] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 00000000bdd7538d to [CRTC:37:pipe A]
>[13307.473868] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:72] for plane state 00000000bdd7538d
>[13307.473888] [drm:drm_atomic_check_only [drm]] checking 0000000018d8a6eb
>[13307.473988] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:37:pipe A] has [PLANE:28:plane 1A] with fb 72
>[13307.474063] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>[13307.474103] [drm:drm_atomic_nonblocking_commit [drm]] committing 0000000018d8a6eb nonblocking
>[13307.490300] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000018d8a6eb
>[13307.490335] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000018d8a6eb
>[13307.490413] [drm:drm_mode_addfb2 [drm]] [FB:100]
>[13307.490463] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000006930b708
>[13307.490495] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:37:pipe A] 000000007e4dcb27 state to 000000006930b708
>[13307.490521] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000affa3c56 state to 000000006930b708
>[13307.490543] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 00000000affa3c56 to [CRTC:37:pipe A]
>[13307.490564] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:100] for plane state 00000000affa3c56
>[13307.490585] [drm:drm_atomic_check_only [drm]] checking 000000006930b708
>[13307.490684] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:37:pipe A] has [PLANE:28:plane 1A] with fb 100
>[13307.490759] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>[13307.490798] [drm:drm_atomic_nonblocking_commit [drm]] committing 000000006930b708 nonblocking
>[13307.506905] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000006930b708
>[13307.506941] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000006930b708
>[13307.507011] [drm:drm_mode_addfb2 [drm]] [FB:73]
>[13307.507062] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000ecd5a468
>[13307.507095] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:37:pipe A] 000000004c9825e5 state to 00000000ecd5a468
>[13307.507119] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 000000009713ae7d state to 00000000ecd5a468
>[13307.507141] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 000000009713ae7d to [CRTC:37:pipe A]
>[13307.507162] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:73] for plane state 000000009713ae7d
>[13307.507184] [drm:drm_atomic_check_only [drm]] checking 00000000ecd5a468
>[13307.507282] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:37:pipe A] has [PLANE:28:plane 1A] with fb 73
>[13307.507356] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>[13307.507396] [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000ecd5a468 nonblocking
>[13307.523607] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000ecd5a468
>[13307.523642] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000ecd5a468
>[13307.523713] [drm:drm_mode_addfb2 [drm]] [FB:72]
>[13307.523763] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000519f591b
>[13307.523795] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:37:pipe A] 00000000cec4efc9 state to 00000000519f591b
>[13307.523821] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 000000000d969d9a state to 00000000519f591b
>[13307.523842] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 000000000d969d9a to [CRTC:37:pipe A]
>[13307.523864] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:72] for plane state 000000000d969d9a
>[13307.523884] [drm:drm_atomic_check_only [drm]] checking 00000000519f591b
>[13307.523983] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:37:pipe A] has [PLANE:28:plane 1A] with fb 72
>[13307.524058] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>[13307.524097] [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000519f591b nonblocking
>[13307.540161] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000519f591b
>[13307.540191] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000519f591b
>[13307.540267] [drm:drm_mode_addfb2 [drm]] [FB:100]
>[13307.540313] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000519f591b
>[13307.540342] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:37:pipe A] 00000000a2fe8a32 state to 00000000519f591b
>[13307.540365] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000f576052d state to 00000000519f591b
>[13307.540384] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 00000000f576052d to [CRTC:37:pipe A]
>[13307.540404] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:100] for plane state 00000000f576052d
>[13307.540423] [drm:drm_atomic_check_only [drm]] checking 00000000519f591b
>[13307.540512] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:37:pipe A] has [PLANE:28:plane 1A] with fb 100
>[13307.540581] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>[13307.540617] [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000519f591b nonblocking
>[13307.556930] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000519f591b
>[13307.556962] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000519f591b
>[13307.557029] [drm:drm_mode_addfb2 [drm]] [FB:73]
>[13307.557075] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000ecd5a468
>[13307.557103] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:37:pipe A] 0000000060dc7769 state to 00000000ecd5a468
>[13307.557125] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 000000001e7dfef6 state to 00000000ecd5a468
>[13307.557144] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 000000001e7dfef6 to [CRTC:37:pipe A]
>[13307.557164] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:73] for plane state 000000001e7dfef6
>[13307.557183] [drm:drm_atomic_check_only [drm]] checking 00000000ecd5a468
>[13307.557271] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:37:pipe A] has [PLANE:28:plane 1A] with fb 73
>[13307.557339] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>[13307.557374] [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000ecd5a468 nonblocking
>[13307.573611] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000ecd5a468
>[13307.573642] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000ecd5a468
>[13307.573712] [drm:drm_mode_addfb2 [drm]] [FB:72]
>[13307.573758] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000006930b708
>[13307.573787] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:37:pipe A] 00000000490de0c7 state to 000000006930b708
>[13307.573809] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000fb0e84d4 state to 000000006930b708
>[13307.573828] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 00000000fb0e84d4 to [CRTC:37:pipe A]
>[13307.573848] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:72] for plane state 00000000fb0e84d4
>[13307.573867] [drm:drm_atomic_check_only [drm]] checking 000000006930b708
>[13307.573956] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:37:pipe A] has [PLANE:28:plane 1A] with fb 72
>[13307.574024] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>[13307.574059] [drm:drm_atomic_nonblocking_commit [drm]] committing 000000006930b708 nonblocking
>[13307.590185] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000006930b708
>[13307.590216] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000006930b708
>[13307.590291] [drm:drm_mode_addfb2 [drm]] [FB:100]
>[13307.590356] [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000018d8a6eb
>[13307.590389] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:37:pipe A] 00000000c3397572 state to 0000000018d8a6eb
>[13307.590415] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 000000009a9ec329 state to 0000000018d8a6eb
>[13307.590436] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 000000009a9ec329 to [CRTC:37:pipe A]
>[13307.590458] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:100] for plane state 000000009a9ec329
>[13307.590480] [drm:drm_atomic_check_only [drm]] checking 0000000018d8a6eb
>[13307.590579] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:37:pipe A] has [PLANE:28:plane 1A] with fb 100
>[13307.590654] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>[13307.590692] [drm:drm_atomic_nonblocking_commit [drm]] committing 0000000018d8a6eb nonblocking
>[13307.606917] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000018d8a6eb
>[13307.606949] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000018d8a6eb
>[13307.607019] [drm:drm_mode_addfb2 [drm]] [FB:73]
>[13307.607066] [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000018d8a6eb
>[13307.607096] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:37:pipe A] 000000007e2acc52 state to 0000000018d8a6eb
>[13307.607119] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 000000005c025013 state to 0000000018d8a6eb
>[13307.607138] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 000000005c025013 to [CRTC:37:pipe A]
>[13307.607157] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:73] for plane state 000000005c025013
>[13307.607175] [drm:drm_atomic_check_only [drm]] checking 0000000018d8a6eb
>[13307.607266] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:37:pipe A] has [PLANE:28:plane 1A] with fb 73
>[13307.607332] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>[13307.607367] [drm:drm_atomic_nonblocking_commit [drm]] committing 0000000018d8a6eb nonblocking
>[13307.623608] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000018d8a6eb
>[13307.623641] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000018d8a6eb
>[13307.623714] [drm:drm_mode_addfb2 [drm]] [FB:72]
>[13307.623760] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000006930b708
>[13307.623789] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:37:pipe A] 000000002ecb330c state to 000000006930b708
>[13307.623812] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000f91cfa69 state to 000000006930b708
>[13307.623831] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 00000000f91cfa69 to [CRTC:37:pipe A]
>[13307.623850] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:72] for plane state 00000000f91cfa69
>[13307.623868] [drm:drm_atomic_check_only [drm]] checking 000000006930b708
>[13307.623959] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:37:pipe A] has [PLANE:28:plane 1A] with fb 72
>[13307.624027] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>[13307.624062] [drm:drm_atomic_nonblocking_commit [drm]] committing 000000006930b708 nonblocking
>[13307.640114] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000006930b708
>[13307.640148] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000006930b708
>[13307.640247] [drm:drm_mode_addfb2 [drm]] [FB:100]
>[13307.640297] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000ecd5a468
>[13307.640329] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:37:pipe A] 00000000c3f4c3f2 state to 00000000ecd5a468
>[13307.640354] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 0000000040ed3e2b state to 00000000ecd5a468
>[13307.640375] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 0000000040ed3e2b to [CRTC:37:pipe A]
>[13307.640397] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:100] for plane state 0000000040ed3e2b
>[13307.640418] [drm:drm_atomic_check_only [drm]] checking 00000000ecd5a468
>[13307.640516] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:37:pipe A] has [PLANE:28:plane 1A] with fb 100
>[13307.640589] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>[13307.640628] [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000ecd5a468 nonblocking
>[13307.656927] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000ecd5a468
>[13307.656961] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000ecd5a468
>[13307.657036] [drm:drm_mode_addfb2 [drm]] [FB:73]
>[13307.657086] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000519f591b
>[13307.657118] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:37:pipe A] 000000002ecb330c state to 00000000519f591b
>[13307.657143] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 000000007b859555 state to 00000000519f591b
>[13307.657165] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 000000007b859555 to [CRTC:37:pipe A]
>[13307.657187] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:73] for plane state 000000007b859555
>[13307.657208] [drm:drm_atomic_check_only [drm]] checking 00000000519f591b
>[13307.657305] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:37:pipe A] has [PLANE:28:plane 1A] with fb 73
>[13307.657381] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>[13307.657420] [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000519f591b nonblocking
>[13307.673618] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000519f591b
>[13307.673650] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000519f591b
>[13307.673720] [drm:drm_mode_addfb2 [drm]] [FB:72]
>[13307.673767] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000519f591b
>[13307.673796] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:37:pipe A] 000000007e2acc52 state to 00000000519f591b
>[13307.673819] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000be77e3d8 state to 00000000519f591b
>[13307.673837] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 00000000be77e3d8 to [CRTC:37:pipe A]
>[13307.673856] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:72] for plane state 00000000be77e3d8
>[13307.673875] [drm:drm_atomic_check_only [drm]] checking 00000000519f591b
>[13307.673964] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:37:pipe A] has [PLANE:28:plane 1A] with fb 72
>[13307.674030] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>[13307.674069] [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000519f591b nonblocking
>[13307.690170] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000519f591b
>[13307.690205] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000519f591b
>[13307.690280] [drm:drm_mode_addfb2 [drm]] [FB:100]
>[13307.690332] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000ecd5a468
>[13307.690364] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:37:pipe A] 00000000c3397572 state to 00000000ecd5a468
>[13307.690390] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000c3e87dde state to 00000000ecd5a468
>[13307.690411] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 00000000c3e87dde to [CRTC:37:pipe A]
>[13307.690432] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:100] for plane state 00000000c3e87dde
>[13307.690453] [drm:drm_atomic_check_only [drm]] checking 00000000ecd5a468
>[13307.690552] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:37:pipe A] has [PLANE:28:plane 1A] with fb 100
>[13307.690626] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>[13307.690665] [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000ecd5a468 nonblocking
>[13307.706939] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000ecd5a468
>[13307.706975] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000ecd5a468
>[13307.707046] [drm:drm_mode_addfb2 [drm]] [FB:73]
>[13307.707097] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000006930b708
>[13307.707129] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:37:pipe A] 00000000490de0c7 state to 000000006930b708
>[13307.707154] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 000000006542467b state to 000000006930b708
>[13307.707174] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 000000006542467b to [CRTC:37:pipe A]
>[13307.707196] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:73] for plane state 000000006542467b
>[13307.707217] [drm:drm_atomic_check_only [drm]] checking 000000006930b708
>[13307.707315] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:37:pipe A] has [PLANE:28:plane 1A] with fb 73
>[13307.707390] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>[13307.707430] [drm:drm_atomic_nonblocking_commit [drm]] committing 000000006930b708 nonblocking
>[13307.723621] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000006930b708
>[13307.723655] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000006930b708
>[13307.723734] [drm:drm_mode_addfb2 [drm]] [FB:72]
>[13307.723786] [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000018d8a6eb
>[13307.723818] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:37:pipe A] 0000000060dc7769 state to 0000000018d8a6eb
>[13307.723842] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000a818d5d5 state to 0000000018d8a6eb
>[13307.723863] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 00000000a818d5d5 to [CRTC:37:pipe A]
>[13307.723885] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:72] for plane state 00000000a818d5d5
>[13307.723906] [drm:drm_atomic_check_only [drm]] checking 0000000018d8a6eb
>[13307.724004] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:37:pipe A] has [PLANE:28:plane 1A] with fb 72
>[13307.724079] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>[13307.724119] [drm:drm_atomic_nonblocking_commit [drm]] committing 0000000018d8a6eb nonblocking
>[13307.740269] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000018d8a6eb
>[13307.740304] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000018d8a6eb
>[13307.740378] [drm:drm_mode_addfb2 [drm]] [FB:100]
>[13307.740429] [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000018d8a6eb
>[13307.740461] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:37:pipe A] 00000000a2fe8a32 state to 0000000018d8a6eb
>[13307.740486] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 000000002362502f state to 0000000018d8a6eb
>[13307.740507] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 000000002362502f to [CRTC:37:pipe A]
>[13307.740529] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:100] for plane state 000000002362502f
>[13307.740549] [drm:drm_atomic_check_only [drm]] checking 0000000018d8a6eb
>[13307.740647] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:37:pipe A] has [PLANE:28:plane 1A] with fb 100
>[13307.740722] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>[13307.740811] [drm:drm_atomic_nonblocking_commit [drm]] committing 0000000018d8a6eb nonblocking
>[13307.756959] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000018d8a6eb
>[13307.756992] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000018d8a6eb
>[13307.757069] [drm:drm_mode_addfb2 [drm]] [FB:73]
>[13307.757120] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000006930b708
>[13307.757151] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:37:pipe A] 00000000cec4efc9 state to 000000006930b708
>[13307.757175] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 000000002b08a22c state to 000000006930b708
>[13307.757196] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 000000002b08a22c to [CRTC:37:pipe A]
>[13307.757217] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:73] for plane state 000000002b08a22c
>[13307.757238] [drm:drm_atomic_check_only [drm]] checking 000000006930b708
>[13307.757351] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:37:pipe A] has [PLANE:28:plane 1A] with fb 73
>[13307.757418] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>[13307.757453] [drm:drm_atomic_nonblocking_commit [drm]] committing 000000006930b708 nonblocking
>[13307.773588] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000006930b708
>[13307.773623] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000006930b708
>[13307.773696] [drm:drm_mode_addfb2 [drm]] [FB:72]
>[13307.773748] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000ecd5a468
>[13307.773780] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:37:pipe A] 000000004c9825e5 state to 00000000ecd5a468
>[13307.773806] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 000000000bd4600c state to 00000000ecd5a468
>[13307.773828] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 000000000bd4600c to [CRTC:37:pipe A]
>[13307.773850] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:72] for plane state 000000000bd4600c
>[13307.773871] [drm:drm_atomic_check_only [drm]] checking 00000000ecd5a468
>[13307.773969] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:37:pipe A] has [PLANE:28:plane 1A] with fb 72
>[13307.774043] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>[13307.774081] [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000ecd5a468 nonblocking
>[13307.790276] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000ecd5a468
>[13307.790311] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000ecd5a468
>[13307.790397] [drm:drm_mode_addfb2 [drm]] [FB:100]
>[13307.790445] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000519f591b
>[13307.790474] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:37:pipe A] 000000007e4dcb27 state to 00000000519f591b
>[13307.790496] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 000000004c5b16ae state to 00000000519f591b
>[13307.790518] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 000000004c5b16ae to [CRTC:37:pipe A]
>[13307.790537] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:100] for plane state 000000004c5b16ae
>[13307.790555] [drm:drm_atomic_check_only [drm]] checking 00000000519f591b
>[13307.790646] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:37:pipe A] has [PLANE:28:plane 1A] with fb 100
>[13307.790712] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>[13307.790747] [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000519f591b nonblocking
>[13307.806916] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000519f591b
>[13307.806951] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000519f591b
>[13307.807023] [drm:drm_mode_addfb2 [drm]] [FB:73]
>[13307.807074] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000519f591b
>[13307.807105] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:37:pipe A] 0000000020fe975a state to 00000000519f591b
>[13307.807130] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000558f1f92 state to 00000000519f591b
>[13307.807152] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 00000000558f1f92 to [CRTC:37:pipe A]
>[13307.807175] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:73] for plane state 00000000558f1f92
>[13307.807196] [drm:drm_atomic_check_only [drm]] checking 00000000519f591b
>[13307.807295] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:37:pipe A] has [PLANE:28:plane 1A] with fb 73
>[13307.807369] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>[13307.807409] [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000519f591b nonblocking
>[13307.823618] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000519f591b
>[13307.823654] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000519f591b
>[13307.823774] [drm:drm_mode_addfb2 [drm]] [FB:72]
>[13307.823824] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000ecd5a468
>[13307.823856] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:37:pipe A] 00000000c0842b5f state to 00000000ecd5a468
>[13307.823880] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000bc105fbf state to 00000000ecd5a468
>[13307.823901] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 00000000bc105fbf to [CRTC:37:pipe A]
>[13307.823922] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:72] for plane state 00000000bc105fbf
>[13307.823943] [drm:drm_atomic_check_only [drm]] checking 00000000ecd5a468
>[13307.824041] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:37:pipe A] has [PLANE:28:plane 1A] with fb 72
>[13307.824119] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>[13307.824159] [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000ecd5a468 nonblocking
>[13307.840142] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000ecd5a468
>[13307.840177] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000ecd5a468
>[13307.840246] [drm:drm_mode_addfb2 [drm]] [FB:100]
>[13307.840295] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000006930b708
>[13307.840327] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:37:pipe A] 0000000079c36b37 state to 000000006930b708
>[13307.840351] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000af091620 state to 000000006930b708
>[13307.840372] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 00000000af091620 to [CRTC:37:pipe A]
>[13307.840393] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:100] for plane state 00000000af091620
>[13307.840414] [drm:drm_atomic_check_only [drm]] checking 000000006930b708
>[13307.840513] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:37:pipe A] has [PLANE:28:plane 1A] with fb 100
>[13307.840588] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>[13307.840627] [drm:drm_atomic_nonblocking_commit [drm]] committing 000000006930b708 nonblocking
>[13307.856939] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000006930b708
>[13307.856975] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000006930b708
>[13307.857046] [drm:drm_mode_addfb2 [drm]] [FB:73]
>[13307.857098] [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000018d8a6eb
>[13307.857130] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:37:pipe A] 00000000ae5bcee3 state to 0000000018d8a6eb
>[13307.857156] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000cbad2bda state to 0000000018d8a6eb
>[13307.857178] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 00000000cbad2bda to [CRTC:37:pipe A]
>[13307.857199] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:73] for plane state 00000000cbad2bda
>[13307.857221] [drm:drm_atomic_check_only [drm]] checking 0000000018d8a6eb
>[13307.857335] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:37:pipe A] has [PLANE:28:plane 1A] with fb 73
>[13307.857402] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>[13307.857438] [drm:drm_atomic_nonblocking_commit [drm]] committing 0000000018d8a6eb nonblocking
>[13307.873621] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000018d8a6eb
>[13307.873657] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000018d8a6eb
>[13307.873727] [drm:drm_mode_addfb2 [drm]] [FB:72]
>[13307.873780] [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000018d8a6eb
>[13307.873812] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:37:pipe A] 00000000644f71c0 state to 0000000018d8a6eb
>[13307.873839] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 000000006f717a2c state to 0000000018d8a6eb
>[13307.873860] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 000000006f717a2c to [CRTC:37:pipe A]
>[13307.873882] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:72] for plane state 000000006f717a2c
>[13307.873903] [drm:drm_atomic_check_only [drm]] checking 0000000018d8a6eb
>[13307.874001] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:37:pipe A] has [PLANE:28:plane 1A] with fb 72
>[13307.874080] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>[13307.874120] [drm:drm_atomic_nonblocking_commit [drm]] committing 0000000018d8a6eb nonblocking
>[13307.890147] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000018d8a6eb
>[13307.890178] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000018d8a6eb
>[13307.890244] [drm:drm_mode_addfb2 [drm]] [FB:100]
>[13307.890289] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000006930b708
>[13307.890317] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:37:pipe A] 00000000e6172a1a state to 000000006930b708
>[13307.890340] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 000000004ca12d46 state to 000000006930b708
>[13307.890360] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 000000004ca12d46 to [CRTC:37:pipe A]
>[13307.890379] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:100] for plane state 000000004ca12d46
>[13307.890398] [drm:drm_atomic_check_only [drm]] checking 000000006930b708
>[13307.890487] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:37:pipe A] has [PLANE:28:plane 1A] with fb 100
>[13307.890556] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>[13307.890591] [drm:drm_atomic_nonblocking_commit [drm]] committing 000000006930b708 nonblocking
>[13307.906933] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000006930b708
>[13307.906967] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000006930b708
>[13307.907039] [drm:drm_mode_addfb2 [drm]] [FB:73]
>[13307.907091] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000ecd5a468
>[13307.907123] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:37:pipe A] 00000000644f71c0 state to 00000000ecd5a468
>[13307.907148] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 000000006f717a2c state to 00000000ecd5a468
>[13307.907169] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 000000006f717a2c to [CRTC:37:pipe A]
>[13307.907190] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:73] for plane state 000000006f717a2c
>[13307.907211] [drm:drm_atomic_check_only [drm]] checking 00000000ecd5a468
>[13307.907310] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:37:pipe A] has [PLANE:28:plane 1A] with fb 73
>[13307.907386] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>[13307.907424] [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000ecd5a468 nonblocking
>[13307.923622] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000ecd5a468
>[13307.923657] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000ecd5a468
>[13307.923732] [drm:drm_mode_addfb2 [drm]] [FB:72]
>[13307.923784] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000519f591b
>[13307.923819] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:37:pipe A] 00000000ae5bcee3 state to 00000000519f591b
>[13307.923844] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000cbad2bda state to 00000000519f591b
>[13307.923866] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 00000000cbad2bda to [CRTC:37:pipe A]
>[13307.923888] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:72] for plane state 00000000cbad2bda
>[13307.923909] [drm:drm_atomic_check_only [drm]] checking 00000000519f591b
>[13307.924008] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:37:pipe A] has [PLANE:28:plane 1A] with fb 72
>[13307.924083] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>[13307.924121] [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000519f591b nonblocking
>[13307.940229] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000519f591b
>[13307.940264] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000519f591b
>[13307.940336] [drm:drm_mode_addfb2 [drm]] [FB:100]
>[13307.940388] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000519f591b
>[13307.940421] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:37:pipe A] 0000000079c36b37 state to 00000000519f591b
>[13307.940446] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000af091620 state to 00000000519f591b
>[13307.940467] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 00000000af091620 to [CRTC:37:pipe A]
>[13307.940489] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:100] for plane state 00000000af091620
>[13307.940511] [drm:drm_atomic_check_only [drm]] checking 00000000519f591b
>[13307.940609] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:37:pipe A] has [PLANE:28:plane 1A] with fb 100
>[13307.940683] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>[13307.940793] [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000519f591b nonblocking
>[13307.956949] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000519f591b
>[13307.956984] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000519f591b
>[13307.957056] [drm:drm_mode_addfb2 [drm]] [FB:73]
>[13307.957108] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000ecd5a468
>[13307.957140] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:37:pipe A] 00000000c0842b5f state to 00000000ecd5a468
>[13307.957166] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000bc105fbf state to 00000000ecd5a468
>[13307.957187] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 00000000bc105fbf to [CRTC:37:pipe A]
>[13307.957208] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:73] for plane state 00000000bc105fbf
>[13307.957229] [drm:drm_atomic_check_only [drm]] checking 00000000ecd5a468
>[13307.957326] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:37:pipe A] has [PLANE:28:plane 1A] with fb 73
>[13307.957401] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>[13307.957440] [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000ecd5a468 nonblocking
>[13307.973633] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000ecd5a468
>[13307.973667] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000ecd5a468
>[13307.973747] [drm:drm_mode_addfb2 [drm]] [FB:72]
>[13307.973798] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000006930b708
>[13307.973830] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:37:pipe A] 0000000020fe975a state to 000000006930b708
>[13307.973855] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000558f1f92 state to 000000006930b708
>[13307.973876] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 00000000558f1f92 to [CRTC:37:pipe A]
>[13307.973897] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:72] for plane state 00000000558f1f92
>[13307.973918] [drm:drm_atomic_check_only [drm]] checking 000000006930b708
>[13307.974016] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:37:pipe A] has [PLANE:28:plane 1A] with fb 72
>[13307.974092] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>[13307.974131] [drm:drm_atomic_nonblocking_commit [drm]] committing 000000006930b708 nonblocking
>[13307.990253] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000006930b708
>[13307.990288] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000006930b708
>[13307.990360] [drm:drm_mode_addfb2 [drm]] [FB:100]
>[13307.990411] [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000018d8a6eb
>[13307.990442] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:37:pipe A] 000000007e4dcb27 state to 0000000018d8a6eb
>[13307.990466] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 000000004c5b16ae state to 0000000018d8a6eb
>[13307.990487] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 000000004c5b16ae to [CRTC:37:pipe A]
>[13307.990509] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:100] for plane state 000000004c5b16ae
>[13307.990530] [drm:drm_atomic_check_only [drm]] checking 0000000018d8a6eb
>[13307.990627] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:37:pipe A] has [PLANE:28:plane 1A] with fb 100
>[13307.990702] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>[13307.990741] [drm:drm_atomic_nonblocking_commit [drm]] committing 0000000018d8a6eb nonblocking
>[13308.006941] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000018d8a6eb
>[13308.006977] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000018d8a6eb
>[13308.007096] [drm:drm_mode_addfb2 [drm]] [FB:73]
>[13308.007147] [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000018d8a6eb
>[13308.007179] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:37:pipe A] 000000004c9825e5 state to 0000000018d8a6eb
>[13308.007204] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 000000000bd4600c state to 0000000018d8a6eb
>[13308.007225] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 000000000bd4600c to [CRTC:37:pipe A]
>[13308.007247] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:73] for plane state 000000000bd4600c
>[13308.007268] [drm:drm_atomic_check_only [drm]] checking 0000000018d8a6eb
>[13308.007366] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:37:pipe A] has [PLANE:28:plane 1A] with fb 73
>[13308.007442] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>[13308.007484] [drm:drm_atomic_nonblocking_commit [drm]] committing 0000000018d8a6eb nonblocking
>[13308.023452] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000018d8a6eb
>[13308.023486] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000018d8a6eb
>[13308.023535] [drm:drm_mode_addfb2 [drm]] [FB:72]
>[13308.023586] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000006930b708
>[13308.023617] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:37:pipe A] 00000000cec4efc9 state to 000000006930b708
>[13308.023643] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 000000002b08a22c state to 000000006930b708
>[13308.023663] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 000000002b08a22c to [CRTC:37:pipe A]
>[13308.023685] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:72] for plane state 000000002b08a22c
>[13308.023706] [drm:drm_atomic_check_only [drm]] checking 000000006930b708
>[13308.023805] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:37:pipe A] has [PLANE:28:plane 1A] with fb 72
>[13308.023881] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>[13308.023920] [drm:drm_atomic_nonblocking_commit [drm]] committing 000000006930b708 nonblocking
>[13308.040274] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000006930b708
>[13308.040310] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000006930b708
>[13308.040380] [drm:drm_mode_addfb2 [drm]] [FB:100]
>[13308.040430] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000ecd5a468
>[13308.040462] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:37:pipe A] 00000000a2fe8a32 state to 00000000ecd5a468
>[13308.040487] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 000000002362502f state to 00000000ecd5a468
>[13308.040508] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 000000002362502f to [CRTC:37:pipe A]
>[13308.040530] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:100] for plane state 000000002362502f
>[13308.040551] [drm:drm_atomic_check_only [drm]] checking 00000000ecd5a468
>[13308.040649] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:37:pipe A] has [PLANE:28:plane 1A] with fb 100
>[13308.040724] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>[13308.040806] [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000ecd5a468 nonblocking
>[13308.056964] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000ecd5a468
>[13308.056996] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000ecd5a468
>[13308.057066] [drm:drm_mode_addfb2 [drm]] [FB:73]
>[13308.057125] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000519f591b
>[13308.057154] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:37:pipe A] 0000000060dc7769 state to 00000000519f591b
>[13308.057177] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000a818d5d5 state to 00000000519f591b
>[13308.057196] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 00000000a818d5d5 to [CRTC:37:pipe A]
>[13308.057215] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:73] for plane state 00000000a818d5d5
>[13308.057234] [drm:drm_atomic_check_only [drm]] checking 00000000519f591b
>[13308.057346] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:37:pipe A] has [PLANE:28:plane 1A] with fb 73
>[13308.057421] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>[13308.057460] [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000519f591b nonblocking
>[13308.073576] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000519f591b
>[13308.073611] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000519f591b
>[13308.073684] [drm:drm_mode_addfb2 [drm]] [FB:72]
>[13308.073736] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000519f591b
>[13308.073768] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:37:pipe A] 00000000490de0c7 state to 00000000519f591b
>[13308.073794] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 000000006542467b state to 00000000519f591b
>[13308.073816] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 000000006542467b to [CRTC:37:pipe A]
>[13308.073838] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:72] for plane state 000000006542467b
>[13308.073859] [drm:drm_atomic_check_only [drm]] checking 00000000519f591b
>[13308.073956] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:37:pipe A] has [PLANE:28:plane 1A] with fb 72
>[13308.074030] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>[13308.074069] [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000519f591b nonblocking
>[13308.090289] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000519f591b
>[13308.090324] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000519f591b
>[13308.090397] [drm:drm_mode_addfb2 [drm]] [FB:100]
>[13308.090449] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000ecd5a468
>[13308.090480] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:37:pipe A] 00000000c3397572 state to 00000000ecd5a468
>[13308.090505] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000c3e87dde state to 00000000ecd5a468
>[13308.090527] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 00000000c3e87dde to [CRTC:37:pipe A]
>[13308.090548] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:100] for plane state 00000000c3e87dde
>[13308.090568] [drm:drm_atomic_check_only [drm]] checking 00000000ecd5a468
>[13308.090666] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:37:pipe A] has [PLANE:28:plane 1A] with fb 100
>[13308.090739] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>[13308.090779] [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000ecd5a468 nonblocking
>[13308.106809] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000ecd5a468
>[13308.106844] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000ecd5a468
>[13308.106914] [drm:drm_mode_addfb2 [drm]] [FB:73]
>[13308.106965] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000006930b708
>[13308.106997] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:37:pipe A] 000000007e2acc52 state to 000000006930b708
>[13308.107022] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000be77e3d8 state to 000000006930b708
>[13308.107043] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 00000000be77e3d8 to [CRTC:37:pipe A]
>[13308.107065] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:73] for plane state 00000000be77e3d8
>[13308.107086] [drm:drm_atomic_check_only [drm]] checking 000000006930b708
>[13308.107184] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:37:pipe A] has [PLANE:28:plane 1A] with fb 73
>[13308.107258] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>[13308.107298] [drm:drm_atomic_nonblocking_commit [drm]] committing 000000006930b708 nonblocking
>[13308.123603] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000006930b708
>[13308.123635] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000006930b708
>[13308.123704] [drm:drm_mode_addfb2 [drm]] [FB:72]
>[13308.123749] [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000018d8a6eb
>[13308.123778] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:37:pipe A] 000000002ecb330c state to 0000000018d8a6eb
>[13308.123800] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 000000007b859555 state to 0000000018d8a6eb
>[13308.123818] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 000000007b859555 to [CRTC:37:pipe A]
>[13308.123837] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:72] for plane state 000000007b859555
>[13308.123856] [drm:drm_atomic_check_only [drm]] checking 0000000018d8a6eb
>[13308.123945] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:37:pipe A] has [PLANE:28:plane 1A] with fb 72
>[13308.124012] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>[13308.124048] [drm:drm_atomic_nonblocking_commit [drm]] committing 0000000018d8a6eb nonblocking
>[13308.140186] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000018d8a6eb
>[13308.140217] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000018d8a6eb
>[13308.140313] [drm:drm_mode_addfb2 [drm]] [FB:100]
>[13308.140368] [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000018d8a6eb
>[13308.140402] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:37:pipe A] 00000000c3f4c3f2 state to 0000000018d8a6eb
>[13308.140427] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 0000000040ed3e2b state to 0000000018d8a6eb
>[13308.140448] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 0000000040ed3e2b to [CRTC:37:pipe A]
>[13308.140469] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:100] for plane state 0000000040ed3e2b
>[13308.140490] [drm:drm_atomic_check_only [drm]] checking 0000000018d8a6eb
>[13308.140590] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:37:pipe A] has [PLANE:28:plane 1A] with fb 100
>[13308.140676] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>[13308.140792] [drm:drm_atomic_nonblocking_commit [drm]] committing 0000000018d8a6eb nonblocking
>[13308.156932] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000018d8a6eb
>[13308.156968] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000018d8a6eb
>[13308.157043] [drm:drm_mode_addfb2 [drm]] [FB:73]
>[13308.157094] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000009dc7ed89
>[13308.157126] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:37:pipe A] 00000000b2b7499b state to 000000009dc7ed89
>[13308.157152] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 000000004c1825de state to 000000009dc7ed89
>[13308.157172] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 000000004c1825de to [CRTC:37:pipe A]
>[13308.157194] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:73] for plane state 000000004c1825de
>[13308.157215] [drm:drm_atomic_check_only [drm]] checking 000000009dc7ed89
>[13308.157313] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:37:pipe A] has [PLANE:28:plane 1A] with fb 73
>[13308.157389] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>[13308.157429] [drm:drm_atomic_nonblocking_commit [drm]] committing 000000009dc7ed89 nonblocking
>[13308.173626] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000009dc7ed89
>[13308.173662] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000009dc7ed89
>[13308.173736] [drm:drm_mode_addfb2 [drm]] [FB:72]
>[13308.173787] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000007f979b23
>[13308.173820] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:37:pipe A] 0000000042f548ae state to 000000007f979b23
>[13308.173845] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000f667123e state to 000000007f979b23
>[13308.173866] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 00000000f667123e to [CRTC:37:pipe A]
>[13308.173887] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:72] for plane state 00000000f667123e
>[13308.173908] [drm:drm_atomic_check_only [drm]] checking 000000007f979b23
>[13308.174007] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:37:pipe A] has [PLANE:28:plane 1A] with fb 72
>[13308.174083] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>[13308.174126] [drm:drm_atomic_nonblocking_commit [drm]] committing 000000007f979b23 nonblocking
>[13308.190150] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000007f979b23
>[13308.190185] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000007f979b23
>[13308.190266] [drm:drm_mode_addfb2 [drm]] [FB:100]
>[13308.190317] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000008f74eebc
>[13308.190349] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:37:pipe A] 00000000213b1f1a state to 000000008f74eebc
>[13308.190375] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 000000004c1825de state to 000000008f74eebc
>[13308.190396] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 000000004c1825de to [CRTC:37:pipe A]
>[13308.190418] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:100] for plane state 000000004c1825de
>[13308.190438] [drm:drm_atomic_check_only [drm]] checking 000000008f74eebc
>[13308.190537] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:37:pipe A] has [PLANE:28:plane 1A] with fb 100
>[13308.190611] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>[13308.190650] [drm:drm_atomic_nonblocking_commit [drm]] committing 000000008f74eebc nonblocking
>[13308.206929] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000008f74eebc
>[13308.206966] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000008f74eebc
>[13308.207039] [drm:drm_mode_addfb2 [drm]] [FB:73]
>[13308.207090] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000003f377fa3
>[13308.207122] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:37:pipe A] 00000000f3c6fe05 state to 000000003f377fa3
>[13308.207147] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000f6d6481c state to 000000003f377fa3
>[13308.207168] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 00000000f6d6481c to [CRTC:37:pipe A]
>[13308.207189] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:73] for plane state 00000000f6d6481c
>[13308.207211] [drm:drm_atomic_check_only [drm]] checking 000000003f377fa3
>[13308.207310] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:37:pipe A] has [PLANE:28:plane 1A] with fb 73
>[13308.207386] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>[13308.207425] [drm:drm_atomic_nonblocking_commit [drm]] committing 000000003f377fa3 nonblocking
>[13308.223616] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000003f377fa3
>[13308.223653] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000003f377fa3
>[13308.223728] [drm:drm_mode_addfb2 [drm]] [FB:72]
>[13308.223780] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000245f0117
>[13308.223815] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:37:pipe A] 000000002184f5e2 state to 00000000245f0117
>[13308.223841] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 000000005ef6bffe state to 00000000245f0117
>[13308.223861] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 000000005ef6bffe to [CRTC:37:pipe A]
>[13308.223883] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:72] for plane state 000000005ef6bffe
>[13308.223904] [drm:drm_atomic_check_only [drm]] checking 00000000245f0117
>[13308.224004] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:37:pipe A] has [PLANE:28:plane 1A] with fb 72
>[13308.224080] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>[13308.224119] [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000245f0117 nonblocking
>[13308.240237] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000245f0117
>[13308.240274] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000245f0117
>[13308.240349] [drm:drm_mode_addfb2 [drm]] [FB:100]
>[13308.240399] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000193cf942
>[13308.240430] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:37:pipe A] 00000000d936250f state to 00000000193cf942
>[13308.240456] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 0000000002fd31f0 state to 00000000193cf942
>[13308.240477] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 0000000002fd31f0 to [CRTC:37:pipe A]
>[13308.240499] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:100] for plane state 0000000002fd31f0
>[13308.240520] [drm:drm_atomic_check_only [drm]] checking 00000000193cf942
>[13308.240618] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:37:pipe A] has [PLANE:28:plane 1A] with fb 100
>[13308.240692] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>[13308.240781] [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000193cf942 nonblocking
>[13308.256934] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000193cf942
>[13308.256969] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000193cf942
>[13308.257045] [drm:drm_mode_addfb2 [drm]] [FB:73]
>[13308.257096] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000e972e416
>[13308.257129] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:37:pipe A] 0000000022c80d23 state to 00000000e972e416
>[13308.257155] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000d83083fb state to 00000000e972e416
>[13308.257176] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 00000000d83083fb to [CRTC:37:pipe A]
>[13308.257197] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:73] for plane state 00000000d83083fb
>[13308.257219] [drm:drm_atomic_check_only [drm]] checking 00000000e972e416
>[13308.257319] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:37:pipe A] has [PLANE:28:plane 1A] with fb 73
>[13308.257393] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>[13308.257433] [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000e972e416 nonblocking
>[13308.273580] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000e972e416
>[13308.273615] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000e972e416
>[13308.273700] [drm:drm_mode_addfb2 [drm]] [FB:72]
>[13308.273751] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000003113364d
>[13308.273782] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:37:pipe A] 000000001c6b455e state to 000000003113364d
>[13308.273807] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000ff49a3f2 state to 000000003113364d
>[13308.273828] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 00000000ff49a3f2 to [CRTC:37:pipe A]
>[13308.273850] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:72] for plane state 00000000ff49a3f2
>[13308.273870] [drm:drm_atomic_check_only [drm]] checking 000000003113364d
>[13308.273969] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:37:pipe A] has [PLANE:28:plane 1A] with fb 72
>[13308.274045] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>[13308.274084] [drm:drm_atomic_nonblocking_commit [drm]] committing 000000003113364d nonblocking
>[13308.290252] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000003113364d
>[13308.290287] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000003113364d
>[13308.290363] [drm:drm_mode_addfb2 [drm]] [FB:100]
>[13308.290414] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000e86b104f
>[13308.290447] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:37:pipe A] 000000000cf8a9a7 state to 00000000e86b104f
>[13308.290473] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000f47f78a4 state to 00000000e86b104f
>[13308.290495] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 00000000f47f78a4 to [CRTC:37:pipe A]
>[13308.290517] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:100] for plane state 00000000f47f78a4
>[13308.290540] [drm:drm_atomic_check_only [drm]] checking 00000000e86b104f
>[13308.290639] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:37:pipe A] has [PLANE:28:plane 1A] with fb 100
>[13308.290713] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>[13308.290752] [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000e86b104f nonblocking
>[13308.306946] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000e86b104f
>[13308.306981] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000e86b104f
>[13308.307057] [drm:drm_mode_addfb2 [drm]] [FB:73]
>[13308.307125] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000e38ac766
>[13308.307157] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:37:pipe A] 00000000ce9444b0 state to 00000000e38ac766
>[13308.307183] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000143cb18f state to 00000000e38ac766
>[13308.307204] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 00000000143cb18f to [CRTC:37:pipe A]
>[13308.307225] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:73] for plane state 00000000143cb18f
>[13308.307247] [drm:drm_atomic_check_only [drm]] checking 00000000e38ac766
>[13308.307346] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:37:pipe A] has [PLANE:28:plane 1A] with fb 73
>[13308.307421] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>[13308.307461] [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000e38ac766 nonblocking
>[13308.323574] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000e38ac766
>[13308.323610] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000e38ac766
>[13308.323684] [drm:drm_mode_addfb2 [drm]] [FB:72]
>[13308.323735] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000e38ac766
>[13308.323769] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:37:pipe A] 00000000e46ed63a state to 00000000e38ac766
>[13308.323794] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000a91e1945 state to 00000000e38ac766
>[13308.323815] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 00000000a91e1945 to [CRTC:37:pipe A]
>[13308.323836] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:72] for plane state 00000000a91e1945
>[13308.323857] [drm:drm_atomic_check_only [drm]] checking 00000000e38ac766
>[13308.323957] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:37:pipe A] has [PLANE:28:plane 1A] with fb 72
>[13308.324032] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>[13308.324071] [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000e38ac766 nonblocking
>[13308.340274] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000e38ac766
>[13308.340309] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000e38ac766
>[13308.340381] [drm:drm_mode_addfb2 [drm]] [FB:100]
>[13308.340431] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000006202e550
>[13308.340463] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:37:pipe A] 0000000043cb4c64 state to 000000006202e550
>[13308.340488] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 000000000505d5b6 state to 000000006202e550
>[13308.340508] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 000000000505d5b6 to [CRTC:37:pipe A]
>[13308.340530] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:100] for plane state 000000000505d5b6
>[13308.340551] [drm:drm_atomic_check_only [drm]] checking 000000006202e550
>[13308.340650] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:37:pipe A] has [PLANE:28:plane 1A] with fb 100
>[13308.340725] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>[13308.340799] [drm:drm_atomic_nonblocking_commit [drm]] committing 000000006202e550 nonblocking
>[13308.356813] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000006202e550
>[13308.356848] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000006202e550
>[13308.356888] [drm:drm_mode_addfb2 [drm]] [FB:73]
>[13308.356938] [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000001fbffed
>[13308.356971] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:37:pipe A] 00000000612a648b state to 0000000001fbffed
>[13308.356997] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000369edf06 state to 0000000001fbffed
>[13308.357018] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 00000000369edf06 to [CRTC:37:pipe A]
>[13308.357040] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:73] for plane state 00000000369edf06
>[13308.357061] [drm:drm_atomic_check_only [drm]] checking 0000000001fbffed
>[13308.357160] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:37:pipe A] has [PLANE:28:plane 1A] with fb 73
>[13308.357235] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>[13308.357274] [drm:drm_atomic_nonblocking_commit [drm]] committing 0000000001fbffed nonblocking
>[13308.373600] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000001fbffed
>[13308.373636] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000001fbffed
>[13308.373759] [drm:drm_mode_addfb2 [drm]] [FB:72]
>[13308.373811] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000008fe4fc91
>[13308.373844] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:37:pipe A] 00000000cb88a4b0 state to 000000008fe4fc91
>[13308.373868] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 000000006796213d state to 000000008fe4fc91
>[13308.373889] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 000000006796213d to [CRTC:37:pipe A]
>[13308.373910] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:72] for plane state 000000006796213d
>[13308.373931] [drm:drm_atomic_check_only [drm]] checking 000000008fe4fc91
>[13308.374030] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:37:pipe A] has [PLANE:28:plane 1A] with fb 72
>[13308.374105] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>[13308.374145] [drm:drm_atomic_nonblocking_commit [drm]] committing 000000008fe4fc91 nonblocking
>[13308.390318] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000008fe4fc91
>[13308.390351] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000008fe4fc91
>[13308.390423] [drm:drm_mode_addfb2 [drm]] [FB:100]
>[13308.390482] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000b31330e6
>[13308.390511] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:37:pipe A] 000000000c66833c state to 00000000b31330e6
>[13308.390534] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000c4c2d3e9 state to 00000000b31330e6
>[13308.390553] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 00000000c4c2d3e9 to [CRTC:37:pipe A]
>[13308.390573] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:100] for plane state 00000000c4c2d3e9
>[13308.390592] [drm:drm_atomic_check_only [drm]] checking 00000000b31330e6
>[13308.390682] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:37:pipe A] has [PLANE:28:plane 1A] with fb 100
>[13308.390748] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>[13308.390784] [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000b31330e6 nonblocking
>[13308.406896] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000b31330e6
>[13308.406932] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000b31330e6
>[13308.407003] [drm:drm_mode_addfb2 [drm]] [FB:73]
>[13308.407053] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000ead6bec5
>[13308.407085] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:37:pipe A] 00000000c222c39a state to 00000000ead6bec5
>[13308.407110] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000219950b0 state to 00000000ead6bec5
>[13308.407132] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 00000000219950b0 to [CRTC:37:pipe A]
>[13308.407153] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:73] for plane state 00000000219950b0
>[13308.407174] [drm:drm_atomic_check_only [drm]] checking 00000000ead6bec5
>[13308.407272] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:37:pipe A] has [PLANE:28:plane 1A] with fb 73
>[13308.407346] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>[13308.407386] [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000ead6bec5 nonblocking
>[13308.408848] [drm:edp_panel_vdd_off_sync [i915]] Turning eDP port A VDD off
>[13308.409157] [drm:edp_panel_vdd_off_sync [i915]] PP_STATUS: 0x00000000 PP_CONTROL: 0x00000060
>[13308.416508] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010
>[13308.416589] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[13308.416661] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0
>[13308.416787] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[13308.423605] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000ead6bec5
>[13308.423641] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000ead6bec5
>[13308.423722] [drm:drm_mode_addfb2 [drm]] [FB:72]
>[13308.423773] [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000000301df0
>[13308.423806] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:37:pipe A] 000000006b1613d2 state to 0000000000301df0
>[13308.423831] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 0000000042a6601f state to 0000000000301df0
>[13308.423853] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 0000000042a6601f to [CRTC:37:pipe A]
>[13308.423874] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:72] for plane state 0000000042a6601f
>[13308.423896] [drm:drm_atomic_check_only [drm]] checking 0000000000301df0
>[13308.423994] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:37:pipe A] has [PLANE:28:plane 1A] with fb 72
>[13308.424077] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x00200000, dig 0x10101011, pins 0x00000020
>[13308.424155] [drm:intel_hpd_irq_handler [i915]] digital hpd port B - short
>[13308.424233] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>[13308.424273] [drm:drm_atomic_nonblocking_commit [drm]] committing 0000000000301df0 nonblocking
>[13308.424344] [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port B - short
>[13308.424936] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 00 00 04 00 0f 00 04
>[13308.425730] [drm:i915_hotplug_work_func [i915]] running encoder hotplug functions
>[13308.425790] [drm:i915_hotplug_work_func [i915]] Connector DP-1 (pin 5) received hotplug event.
>[13308.425850] [drm:intel_dp_detect [i915]] [CONNECTOR:56:DP-1]
>[13308.426263] [drm:lspcon_wake_native_aux_ch [i915]] Native AUX CH up, DPCD version: 1.2
>[13308.426372] [drm:lspcon_resume [i915]] LSPCON recovering in PCON mode after 0 ms
>[13308.426809] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13308.428074] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13308.429380] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13308.430615] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13308.431874] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13308.432697] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[13308.433197] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 00 00 04 00 0f 00 04
>[13308.433964] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>[13308.434018] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000
>[13308.434069] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000
>[13308.434465] [drm:drm_dp_read_desc [drm_kms_helper]] DP branch: OUI 00-60-ad dev-ID MC2800 HW-rev 2.2 SW-rev 1.72 quirks 0x0000
>[13308.434813] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[13308.435582] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13308.436861] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13308.438104] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13308.439302] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13308.440081] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000000301df0
>[13308.440113] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000000301df0
>[13308.440148] [drm:drm_mode_addfb2 [drm]] [FB:100]
>[13308.440597] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13308.441831] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13308.443071] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13308.444335] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13308.445531] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13308.446924] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13308.448316] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13308.449646] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13308.451031] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13308.452420] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13308.453793] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13308.455182] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13308.456570] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13308.457828] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13308.459098] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13308.460287] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13308.461472] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13308.462864] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13308.464254] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13308.465583] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13308.466979] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13308.468367] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13308.469684] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13308.471073] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13308.472462] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13308.473283] [drm:drm_detect_monitor_audio [drm]] Monitor has basic audio support
>[13308.473653] [drm:i915_hotplug_work_func [i915]] [CONNECTOR:56:DP-1] status updated from disconnected to connected
>[13308.473684] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000006930b708
>[13308.473713] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:37:pipe A] 00000000c3f4c3f2 state to 000000006930b708
>[13308.473736] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000f91cfa69 state to 000000006930b708
>[13308.473754] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 00000000f91cfa69 to [CRTC:37:pipe A]
>[13308.473773] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:100] for plane state 00000000f91cfa69
>[13308.473791] [drm:drm_atomic_check_only [drm]] checking 000000006930b708
>[13308.473870] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:37:pipe A] has [PLANE:28:plane 1A] with fb 100
>[13308.473933] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>[13308.473965] [drm:drm_atomic_nonblocking_commit [drm]] committing 000000006930b708 nonblocking
>[13308.490147] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000006930b708
>[13308.490176] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000006930b708
>[13308.493089] [IGT] kms_flip: exiting, ret=99
>[13308.493170] [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000023c1b2e4
>[13308.493202] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:37:pipe A] 000000008778a908 state to 0000000023c1b2e4
>[13308.493226] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:37:pipe A] to 0000000023c1b2e4
>[13308.493248] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:56:DP-1] 0000000056b7d1c0 state to 0000000023c1b2e4
>[13308.493268] [drm:drm_atomic_check_only [drm]] checking 0000000023c1b2e4
>[13308.493288] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:56:DP-1]
>[13308.493301] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:56:DP-1] keeps [ENCODER:55:DDI B], now on [CRTC:37:pipe A]
>[13308.493330] [drm:drm_atomic_commit [drm]] committing 0000000023c1b2e4
>[13308.506839] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000023c1b2e4
>[13308.506869] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000023c1b2e4
>[13308.533956] [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000023c1b2e4
>[13308.533989] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000dece0c09 state to 0000000023c1b2e4
>[13308.534013] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:37:pipe A] 0000000031aec332 state to 0000000023c1b2e4
>[13308.534033] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for plane state 00000000dece0c09
>[13308.534051] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 00000000dece0c09 to [NOCRTC]
>[13308.534070] [drm:drm_atomic_check_only [drm]] checking 0000000023c1b2e4
>[13308.534150] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:37:pipe A] has [PLANE:28:plane 1A] with fb -1
>[13308.534217] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 0, off 1, on 0, ms 0
>[13308.534274] [drm:skl_compute_wm [i915]] [PLANE:28:plane 1A] ddb (0 - 860) -> (0 - 0)
>[13308.534299] [drm:drm_atomic_commit [drm]] committing 0000000023c1b2e4
>[13308.540174] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000023c1b2e4
>[13308.540204] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000023c1b2e4
>[13308.540314] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000e86b104f
>[13308.540345] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 000000000874ecc4 state to 00000000e86b104f
>[13308.540368] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 2A] 00000000fe89f899 state to 00000000e86b104f
>[13308.540387] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 00000000fe89f899 to [NOCRTC]
>[13308.540406] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for plane state 00000000fe89f899
>[13308.540425] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:34:cursor A] 000000008932bcb0 state to 00000000e86b104f
>[13308.540442] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 000000008932bcb0 to [NOCRTC]
>[13308.540459] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for plane state 000000008932bcb0
>[13308.540477] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:38:plane 1B] 00000000669837ce state to 00000000e86b104f
>[13308.540494] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:41:plane 2B] 0000000067d079be state to 00000000e86b104f
>[13308.540511] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 0000000067d079be to [NOCRTC]
>[13308.540528] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for plane state 0000000067d079be
>[13308.540545] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:44:cursor B] 000000009ef2f77c state to 00000000e86b104f
>[13308.540561] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 000000009ef2f77c to [NOCRTC]
>[13308.540577] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for plane state 000000009ef2f77c
>[13308.540597] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:37:pipe A] 00000000341fcb19 state to 00000000e86b104f
>[13308.540619] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [MODE:1920x1080] for CRTC state 00000000341fcb19
>[13308.540636] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 000000000874ecc4 to [CRTC:37:pipe A]
>[13308.540653] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:115] for plane state 000000000874ecc4
>[13308.540671] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:37:pipe A] to 00000000e86b104f
>[13308.540732] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:56:DP-1] 000000001e5b6419 state to 00000000e86b104f
>[13308.540776] [drm:drm_atomic_set_crtc_for_connector [drm]] Link connector state 000000001e5b6419 to [NOCRTC]
>[13308.540809] [drm:drm_atomic_set_crtc_for_connector [drm]] Link connector state 000000001e5b6419 to [CRTC:37:pipe A]
>[13308.540843] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:47:pipe B] 00000000237ac47b state to 00000000e86b104f
>[13308.540884] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [MODE:1920x1200] for CRTC state 00000000237ac47b
>[13308.540917] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 00000000669837ce to [CRTC:47:pipe B]
>[13308.540955] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:115] for plane state 00000000669837ce
>[13308.540987] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:47:pipe B] to 00000000e86b104f
>[13308.541028] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:61:DP-2] 00000000eef50389 state to 00000000e86b104f
>[13308.541059] [drm:drm_atomic_set_crtc_for_connector [drm]] Link connector state 00000000eef50389 to [CRTC:47:pipe B]
>[13308.541096] [drm:drm_atomic_check_only [drm]] checking 00000000e86b104f
>[13308.541120] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:47:pipe B] mode changed
>[13308.541134] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:47:pipe B] enable changed
>[13308.541153] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:47:pipe B] active changed
>[13308.541173] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:56:DP-1]
>[13308.541190] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:56:DP-1] keeps [ENCODER:55:DDI B], now on [CRTC:37:pipe A]
>[13308.541202] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:61:DP-2]
>[13308.541228] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:61:DP-2] using [ENCODER:60:DDI C] on [CRTC:47:pipe B]
>[13308.541250] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:47:pipe B] needs all connectors, enable: y, active: y
>[13308.541282] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:47:pipe B] to 00000000e86b104f
>[13308.541323] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:47:pipe B] to 00000000e86b104f
>[13308.541425] [drm:intel_atomic_check [i915]] [CONNECTOR:61:DP-2] checking for sink bpp constrains
>[13308.541502] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[13308.541590] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[13308.541687] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[13308.541755] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[13308.541839] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[13308.541912] [drm:intel_dump_pipe_config [i915]] [CRTC:47:pipe B][modeset]
>[13308.541991] [drm:intel_dump_pipe_config [i915]] output_types: DP (0x80)
>[13308.542057] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[13308.542132] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[13308.542196] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[13308.542266] [drm:intel_dump_pipe_config [i915]] requested mode:
>[13308.542302] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[13308.542373] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[13308.542407] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[13308.542481] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[13308.542544] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[13308.542614] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[13308.542675] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[13308.542744] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[13308.542805] [drm:intel_dump_pipe_config [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[13308.542873] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[13308.542933] [drm:intel_dump_pipe_config [i915]] [PLANE:38:plane 1B] disabled, scaler_id = -1
>[13308.543003] [drm:intel_dump_pipe_config [i915]] [PLANE:41:plane 2B] disabled, scaler_id = -1
>[13308.543063] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor B] disabled, scaler_id = -1
>[13308.543144] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[13308.543210] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[13308.543292] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:37:pipe A] has [PLANE:28:plane 1A] with fb 115
>[13308.543358] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 0 -> 1, off 0, on 1, ms 0
>[13308.543432] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:47:pipe B] has [PLANE:38:plane 1B] with fb 115
>[13308.543494] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:38:plane 1B] visible 0 -> 1, off 0, on 1, ms 1
>[13308.543575] [drm:intel_find_shared_dpll [i915]] [CRTC:47:pipe B] allocated DPLL 2
>[13308.543641] [drm:intel_reference_shared_dpll [i915]] using DPLL 2 for pipe B
>[13308.543722] [drm:skl_compute_wm [i915]] [PLANE:28:plane 1A] ddb (0 - 0) -> (0 - 438)
>[13308.543786] [drm:skl_compute_wm [i915]] [PLANE:34:cursor A] ddb (860 - 892) -> (438 - 446)
>[13308.543855] [drm:skl_compute_wm [i915]] [PLANE:38:plane 1B] ddb (0 - 0) -> (446 - 884)
>[13308.543917] [drm:skl_compute_wm [i915]] [PLANE:44:cursor B] ddb (0 - 0) -> (884 - 892)
>[13308.543959] [drm:drm_atomic_commit [drm]] committing 00000000e86b104f
>[13308.544068] [drm:intel_disable_sagv [i915]] Disabling the SAGV
>[13308.544157] [drm:intel_atomic_commit_tail [i915]] [ENCODER:48:DDI A]
>[13308.544225] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI B]
>[13308.544299] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[13308.544362] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[13308.544432] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DDI C]
>[13308.544492] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST A]
>[13308.544560] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST B]
>[13308.544620] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI D]
>[13308.544690] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[13308.544768] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[13308.544849] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[13308.544931] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[13308.545013] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[13308.545091] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[13308.557253] [drm:intel_enable_shared_dpll [i915]] enable DPLL 2 (active 2, on? 0) for crtc 47
>[13308.557319] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 2
>[13308.557474] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well
>[13308.558614] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[13308.558670] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[13308.558723] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[13308.558774] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[13308.559444] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 04000000
>[13308.559491] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 1
>[13308.559537] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[13308.560196] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[13308.560244] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[13308.561240] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[13308.561636] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:61:DP-2] Link Training Passed at Link Rate = 162000, Lane count = 4
>[13308.562276] [drm:intel_enable_pipe [i915]] enabling pipe B
>[13308.562369] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS
>[13308.579205] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:61:DP-2]
>[13308.579282] [drm:intel_atomic_commit_tail [i915]] [CRTC:47:pipe B]
>[13308.579369] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[13308.579417] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000e86b104f
>[13308.579451] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000e86b104f
>[13308.579470] [drm:drm_fb_helper_hotplug_event.part.33 [drm_kms_helper]] 
>[13308.579480] [drm:drm_setup_crtcs [drm_kms_helper]] 
>[13308.579494] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:49:eDP-1]
>[13308.579561] [drm:intel_dp_detect [i915]] [CONNECTOR:49:eDP-1]
>[13308.579629] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>[13308.579688] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[13308.579742] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[13308.579853] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[13308.579959] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle
>[13309.017262] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 00000000 control 00000060
>[13309.017393] [drm:wait_panel_status [i915]] Wait complete
>[13309.017688] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x00000000 PP_CONTROL: 0x00000068
>[13309.017803] [drm:edp_panel_vdd_on [i915]] eDP port A panel power wasn't enabled
>[13309.119637] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010
>[13309.119719] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[13309.119792] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1
>[13309.119915] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[13309.225571] [drm:drm_dp_read_desc [drm_kms_helper]] DP sink: OUI 00-1c-f8 dev-ID q\006UA\022\001 HW-rev 10.0 SW-rev 1.41 quirks 0x0000
>[13309.226749] [drm:drm_add_display_info [drm]] non_desktop set to 0
>[13309.226779] [drm:drm_add_edid_modes [drm]] ELD: no CEA Extension found
>[13309.226798] [drm:drm_add_display_info [drm]] non_desktop set to 0
>[13309.226840] [drm:drm_mode_debug_printmodeline [drm]] Modeline 98:"1920x1080" 60 141000 1920 1936 1952 2104 1080 1083 1097 1116 0x48 0xa
>[13309.226859] [drm:drm_mode_prune_invalid [drm]] Not using 1920x1080 mode: CLOCK_HIGH
>[13309.226873] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:56:DP-1]
>[13309.226948] [drm:intel_dp_detect [i915]] [CONNECTOR:56:DP-1]
>[13309.227369] [drm:lspcon_wake_native_aux_ch [i915]] Native AUX CH up, DPCD version: 1.2
>[13309.227480] [drm:lspcon_resume [i915]] LSPCON recovering in PCON mode after 0 ms
>[13309.227916] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13309.229186] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13309.230459] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13309.231722] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13309.233004] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13309.233892] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[13309.234364] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 00 00 04 00 0f 00 04
>[13309.235132] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>[13309.235187] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000
>[13309.235237] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000
>[13309.235637] [drm:drm_dp_read_desc [drm_kms_helper]] DP branch: OUI 00-60-ad dev-ID MC2800 HW-rev 2.2 SW-rev 1.72 quirks 0x0000
>[13309.235984] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[13309.236776] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13309.238066] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13309.239337] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13309.240594] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13309.241866] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13309.243120] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13309.244397] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13309.245647] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13309.246911] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13309.248312] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13309.249648] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13309.251043] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13309.252443] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13309.253820] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13309.255218] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13309.256622] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13309.258019] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13309.259276] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13309.260554] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13309.261830] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13309.263098] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13309.264495] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13309.265870] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13309.267267] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13309.268661] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13309.270063] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13309.271462] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13309.272870] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13309.274260] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13309.275107] [drm:drm_detect_monitor_audio [drm]] Monitor has basic audio support
>[13309.275434] [drm:drm_add_display_info [drm]] non_desktop set to 0
>[13309.275455] [drm:drm_add_display_info [drm]] HDMI: DVI dual 0, max TMDS clock 225000 kHz
>[13309.275482] [drm:drm_add_edid_modes [drm]] ELD monitor BOBCAT2800
>[13309.275502] [drm:drm_add_edid_modes [drm]] HDMI: latency present 0 0, video latency 0 0, audio latency 0 0
>[13309.275518] [drm:drm_add_edid_modes [drm]] ELD size 36, SAD count 1
>[13309.275534] [drm:drm_add_display_info [drm]] non_desktop set to 0
>[13309.275549] [drm:drm_add_display_info [drm]] HDMI: DVI dual 0, max TMDS clock 225000 kHz
>[13309.276013] [drm:drm_mode_debug_printmodeline [drm]] Modeline 139:"720x480i" 0 13500 720 739 801 858 480 488 494 525 0x40 0x101a
>[13309.276031] [drm:drm_mode_prune_invalid [drm]] Not using 720x480i mode: H_ILLEGAL
>[13309.276051] [drm:drm_mode_debug_printmodeline [drm]] Modeline 140:"720x576i" 0 13500 720 732 795 864 576 580 586 625 0x40 0x101a
>[13309.276067] [drm:drm_mode_prune_invalid [drm]] Not using 720x576i mode: H_ILLEGAL
>[13309.276086] [drm:drm_mode_debug_printmodeline [drm]] Modeline 160:"720x480i" 60 13514 720 739 801 858 480 488 494 525 0x40 0x101a
>[13309.276101] [drm:drm_mode_prune_invalid [drm]] Not using 720x480i mode: H_ILLEGAL
>[13309.276120] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:56:DP-1] probed modes :
>[13309.276138] [drm:drm_mode_debug_printmodeline [drm]] Modeline 74:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x9
>[13309.276155] [drm:drm_mode_debug_printmodeline [drm]] Modeline 81:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x40 0x9
>[13309.276172] [drm:drm_mode_debug_printmodeline [drm]] Modeline 75:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[13309.276188] [drm:drm_mode_debug_printmodeline [drm]] Modeline 120:"1920x1080" 60 148352 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0x5
>[13309.276205] [drm:drm_mode_debug_printmodeline [drm]] Modeline 76:"1920x1080i" 60 74250 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[13309.276221] [drm:drm_mode_debug_printmodeline [drm]] Modeline 121:"1920x1080i" 60 74176 1920 2008 2052 2200 1080 1084 1094 1125 0x40 0x15
>[13309.276237] [drm:drm_mode_debug_printmodeline [drm]] Modeline 109:"1920x1080" 50 148500 1920 2448 2492 2640 1080 1084 1089 1125 0x40 0x5
>[13309.276253] [drm:drm_mode_debug_printmodeline [drm]] Modeline 114:"1920x1080i" 50 74250 1920 2448 2492 2640 1080 1084 1094 1125 0x40 0x15
>[13309.276270] [drm:drm_mode_debug_printmodeline [drm]] Modeline 116:"1920x1080" 24 74250 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[13309.276286] [drm:drm_mode_debug_printmodeline [drm]] Modeline 132:"1920x1080" 24 74176 1920 2558 2602 2750 1080 1084 1089 1125 0x40 0x5
>[13309.276302] [drm:drm_mode_debug_printmodeline [drm]] Modeline 80:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[13309.276318] [drm:drm_mode_debug_printmodeline [drm]] Modeline 87:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[13309.276334] [drm:drm_mode_debug_printmodeline [drm]] Modeline 79:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[13309.276350] [drm:drm_mode_debug_printmodeline [drm]] Modeline 82:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[13309.276366] [drm:drm_mode_debug_printmodeline [drm]] Modeline 77:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[13309.276382] [drm:drm_mode_debug_printmodeline [drm]] Modeline 122:"1280x720" 60 74176 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[13309.276398] [drm:drm_mode_debug_printmodeline [drm]] Modeline 113:"1280x720" 50 74250 1280 1720 1760 1980 720 725 730 750 0x40 0x5
>[13309.276414] [drm:drm_mode_debug_printmodeline [drm]] Modeline 88:"1024x768" 75 78750 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[13309.276430] [drm:drm_mode_debug_printmodeline [drm]] Modeline 89:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[13309.276446] [drm:drm_mode_debug_printmodeline [drm]] Modeline 90:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[13309.276462] [drm:drm_mode_debug_printmodeline [drm]] Modeline 83:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[13309.276478] [drm:drm_mode_debug_printmodeline [drm]] Modeline 110:"720x576" 50 27000 720 732 796 864 576 581 586 625 0x40 0xa
>[13309.276493] [drm:drm_mode_debug_printmodeline [drm]] Modeline 123:"720x480" 60 27027 720 736 798 858 480 489 495 525 0x40 0xa
>[13309.276509] [drm:drm_mode_debug_printmodeline [drm]] Modeline 78:"720x480" 60 27000 720 736 798 858 480 489 495 525 0x40 0xa
>[13309.276525] [drm:drm_mode_debug_printmodeline [drm]] Modeline 84:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[13309.276540] [drm:drm_mode_debug_printmodeline [drm]] Modeline 124:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[13309.276556] [drm:drm_mode_debug_printmodeline [drm]] Modeline 85:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[13309.276572] [drm:drm_mode_debug_printmodeline [drm]] Modeline 86:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[13309.276583] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:61:DP-2]
>[13309.276652] [drm:intel_dp_detect [i915]] [CONNECTOR:61:DP-2]
>[13309.277215] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 00 02 02 06 03 00 00 00
>[13309.277564] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>[13309.277621] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[13309.277676] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[13309.278066] [drm:drm_dp_read_desc [drm_kms_helper]] DP sink: OUI 00-00-00 dev-ID  HW-rev 0.0 SW-rev 0.0 quirks 0x0000
>[13309.278120] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[13309.278499] [drm:intel_dp_check_link_status [i915]] DDI C: channel EQ not ok, retraining
>[13309.279457] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[13309.279506] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[13309.279554] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[13309.279603] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[13309.280249] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[13309.280296] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[13309.281243] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[13309.281622] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:61:DP-2] Link Training Passed at Link Rate = 162000, Lane count = 4
>[13309.299964] [drm:drm_add_display_info [drm]] non_desktop set to 0
>[13309.299990] [drm:drm_add_edid_modes [drm]] ELD: no CEA Extension found
>[13309.300008] [drm:drm_add_display_info [drm]] non_desktop set to 0
>[13309.300154] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:61:DP-2] probed modes :
>[13309.300177] [drm:drm_mode_debug_printmodeline [drm]] Modeline 91:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[13309.300195] [drm:drm_mode_debug_printmodeline [drm]] Modeline 95:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x40 0xa
>[13309.300211] [drm:drm_mode_debug_printmodeline [drm]] Modeline 103:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[13309.300226] [drm:drm_mode_debug_printmodeline [drm]] Modeline 92:"1680x1050" 60 146250 1680 1784 1960 2240 1050 1053 1059 1089 0x40 0x6
>[13309.300242] [drm:drm_mode_debug_printmodeline [drm]] Modeline 96:"1600x900" 60 108000 1600 1624 1704 1800 900 901 904 1000 0x40 0x5
>[13309.300256] [drm:drm_mode_debug_printmodeline [drm]] Modeline 104:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[13309.300271] [drm:drm_mode_debug_printmodeline [drm]] Modeline 93:"1440x900" 60 106500 1440 1520 1672 1904 900 903 909 934 0x40 0x6
>[13309.300286] [drm:drm_mode_debug_printmodeline [drm]] Modeline 94:"1280x800" 60 83500 1280 1352 1480 1680 800 803 809 831 0x40 0x6
>[13309.300300] [drm:drm_mode_debug_printmodeline [drm]] Modeline 97:"1280x720" 60 74250 1280 1390 1430 1650 720 725 730 750 0x40 0x5
>[13309.300315] [drm:drm_mode_debug_printmodeline [drm]] Modeline 112:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[13309.300330] [drm:drm_mode_debug_printmodeline [drm]] Modeline 105:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[13309.300344] [drm:drm_mode_debug_printmodeline [drm]] Modeline 111:"640x480" 60 25175 640 656 752 800 480 490 492 525 0x40 0xa
>[13309.300355] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:64:HDMI-A-1]
>[13309.300416] [drm:intel_hdmi_detect [i915]] [CONNECTOR:64:HDMI-A-1]
>[13309.300943] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[13309.300996] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[13309.301414] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[13309.301486] [drm:drm_do_probe_ddc_edid [drm]] drm: skipping non-existent adapter i915 gmbus dpc
>[13309.301936] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[13309.301981] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[13309.302410] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[13309.302473] [drm:drm_dp_dual_mode_detect [drm_kms_helper]] DP dual mode HDMI ID:  (err -6)
>[13309.302484] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:64:HDMI-A-1] disconnected
>[13309.302494] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:67:DP-3]
>[13309.302543] [drm:intel_dp_detect [i915]] [CONNECTOR:67:DP-3]
>[13309.302587] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:67:DP-3] disconnected
>[13309.302596] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:70:HDMI-A-2]
>[13309.302641] [drm:intel_hdmi_detect [i915]] [CONNECTOR:70:HDMI-A-2]
>[13309.322911] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0050 w(1)
>[13309.322973] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK on first message, retry
>[13309.343308] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0050 w(1)
>[13309.343410] [drm:drm_do_probe_ddc_edid [drm]] drm: skipping non-existent adapter i915 gmbus dpd
>[13309.363799] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0040 w(1)
>[13309.363861] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK on first message, retry
>[13309.384054] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0040 w(1)
>[13309.384144] [drm:drm_dp_dual_mode_detect [drm_kms_helper]] DP dual mode HDMI ID:  (err -6)
>[13309.384158] [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:70:HDMI-A-2] disconnected
>[13309.384171] [drm:drm_setup_crtcs [drm_kms_helper]] connector 49 enabled? yes
>[13309.384180] [drm:drm_setup_crtcs [drm_kms_helper]] connector 56 enabled? yes
>[13309.384189] [drm:drm_setup_crtcs [drm_kms_helper]] connector 61 enabled? yes
>[13309.384198] [drm:drm_setup_crtcs [drm_kms_helper]] connector 64 enabled? no
>[13309.384208] [drm:drm_setup_crtcs [drm_kms_helper]] connector 67 enabled? no
>[13309.384216] [drm:drm_setup_crtcs [drm_kms_helper]] connector 70 enabled? no
>[13309.384283] [drm:intel_fb_initial_config [i915]] Not using firmware configuration
>[13309.384295] [drm:drm_setup_crtcs [drm_kms_helper]] looking for cmdline mode on connector 49
>[13309.384305] [drm:drm_setup_crtcs [drm_kms_helper]] looking for preferred mode on connector 49 0
>[13309.384314] [drm:drm_setup_crtcs [drm_kms_helper]] found mode none
>[13309.384323] [drm:drm_setup_crtcs [drm_kms_helper]] looking for cmdline mode on connector 56
>[13309.384332] [drm:drm_setup_crtcs [drm_kms_helper]] looking for preferred mode on connector 56 0
>[13309.384341] [drm:drm_setup_crtcs [drm_kms_helper]] found mode 1920x1080
>[13309.384350] [drm:drm_setup_crtcs [drm_kms_helper]] looking for cmdline mode on connector 61
>[13309.384359] [drm:drm_setup_crtcs [drm_kms_helper]] looking for preferred mode on connector 61 0
>[13309.384368] [drm:drm_setup_crtcs [drm_kms_helper]] found mode 1920x1200
>[13309.384377] [drm:drm_setup_crtcs [drm_kms_helper]] picking CRTCs for 1920x1200 config
>[13309.384394] [drm:drm_setup_crtcs [drm_kms_helper]] desired mode 1920x1080 set on crtc 37 (0,0)
>[13309.384405] [drm:drm_setup_crtcs [drm_kms_helper]] desired mode 1920x1200 set on crtc 47 (0,0)
>[13309.384437] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000e0242f28
>[13309.384464] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 0000000023de7ce9 state to 00000000e0242f28
>[13309.384486] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:37:pipe A] 0000000008271548 state to 00000000e0242f28
>[13309.384505] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 2A] 00000000db53944b state to 00000000e0242f28
>[13309.384522] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 00000000db53944b to [NOCRTC]
>[13309.384540] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for plane state 00000000db53944b
>[13309.384558] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:34:cursor A] 000000007bb8e7ab state to 00000000e0242f28
>[13309.384573] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 000000007bb8e7ab to [NOCRTC]
>[13309.384589] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for plane state 000000007bb8e7ab
>[13309.384605] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:38:plane 1B] 00000000dcaf2eb1 state to 00000000e0242f28
>[13309.384622] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:47:pipe B] 0000000023ca96d4 state to 00000000e0242f28
>[13309.384638] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:41:plane 2B] 0000000005c4a1b8 state to 00000000e0242f28
>[13309.384653] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 0000000005c4a1b8 to [NOCRTC]
>[13309.384668] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for plane state 0000000005c4a1b8
>[13309.384717] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:44:cursor B] 000000000b62c1b6 state to 00000000e0242f28
>[13309.384732] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 000000000b62c1b6 to [NOCRTC]
>[13309.384757] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for plane state 000000000b62c1b6
>[13309.384787] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [MODE:1920x1080] for CRTC state 0000000008271548
>[13309.384810] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 0000000023de7ce9 to [CRTC:37:pipe A]
>[13309.384833] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:115] for plane state 0000000023de7ce9
>[13309.384857] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:37:pipe A] to 00000000e0242f28
>[13309.384882] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:56:DP-1] 000000005a7d1818 state to 00000000e0242f28
>[13309.384906] [drm:drm_atomic_set_crtc_for_connector [drm]] Link connector state 000000005a7d1818 to [NOCRTC]
>[13309.384928] [drm:drm_atomic_set_crtc_for_connector [drm]] Link connector state 000000005a7d1818 to [CRTC:37:pipe A]
>[13309.384954] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [MODE:1920x1200] for CRTC state 0000000023ca96d4
>[13309.384977] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 00000000dcaf2eb1 to [CRTC:47:pipe B]
>[13309.385001] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:115] for plane state 00000000dcaf2eb1
>[13309.385026] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:47:pipe B] to 00000000e0242f28
>[13309.385048] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:61:DP-2] 00000000b8dc24c5 state to 00000000e0242f28
>[13309.385072] [drm:drm_atomic_set_crtc_for_connector [drm]] Link connector state 00000000b8dc24c5 to [NOCRTC]
>[13309.385095] [drm:drm_atomic_set_crtc_for_connector [drm]] Link connector state 00000000b8dc24c5 to [CRTC:47:pipe B]
>[13309.385119] [drm:drm_atomic_check_only [drm]] checking 00000000e0242f28
>[13309.385143] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:56:DP-1]
>[13309.385158] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:56:DP-1] keeps [ENCODER:55:DDI B], now on [CRTC:37:pipe A]
>[13309.385168] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:61:DP-2]
>[13309.385180] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:61:DP-2] keeps [ENCODER:60:DDI C], now on [CRTC:47:pipe B]
>[13309.385256] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:37:pipe A] has [PLANE:28:plane 1A] with fb 115
>[13309.385321] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>[13309.385388] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:47:pipe B] has [PLANE:38:plane 1B] with fb 115
>[13309.385453] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:38:plane 1B] visible 1 -> 1, off 0, on 0, ms 0
>[13309.385497] [drm:drm_atomic_commit [drm]] committing 00000000e0242f28
>[13309.396461] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000e0242f28
>[13309.396494] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000e0242f28
>[13309.413707] [IGT] gem_exec_reloc: executing
>[13309.453075] Setting dangerous option reset - tainting kernel
>[13309.453223] [IGT] gem_exec_reloc: starting subtest readonly-32
>[13312.248836] [drm:edp_panel_vdd_off_sync [i915]] Turning eDP port A VDD off
>[13312.249080] [drm:edp_panel_vdd_off_sync [i915]] PP_STATUS: 0x00000000 PP_CONTROL: 0x00000060
>[13312.256245] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010
>[13312.256261] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[13312.256274] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0
>[13312.256331] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[13336.154783] watchdog: BUG: soft lockup - CPU#11 stuck for 23s! [gem_exec_reloc:5002]
>[13336.154786] Modules linked in: asix usbnet mii ip6table_filter ip6_tables cmac bnep iptable_filter binfmt_misc nls_iso8859_1 snd_hda_codec_hdmi 8250_dw snd_hda_codec_realtek snd_hda_codec_generic intel_rapl x86_pkg_temp_thermal intel_powerclamp coretemp kvm_intel snd_hda_intel kvm snd_hda_codec irqbypass snd_hda_core crct10dif_pclmul snd_hwdep crc32_pclmul ghash_clmulni_intel snd_pcm pcbc snd_seq_midi snd_seq_midi_event snd_rawmidi aesni_intel btusb aes_x86_64 snd_seq btrtl iwlwifi crypto_simd btbcm glue_helper snd_seq_device btintel cryptd idma64 snd_timer bluetooth virt_dma snd intel_cstate intel_lpss_pci input_leds ecdh_generic cfg80211 soundcore intel_rapl_perf serio_raw intel_pch_thermal intel_lpss wmi_bmof tpm_crb mac_hid acpi_pad parport_pc ppdev lp parport ip_tables x_tables autofs4 hid_generic
>[13336.154806]  usbhid i915 i2c_algo_bit prime_numbers drm_kms_helper syscopyarea sysfillrect sysimgblt fb_sys_fops drm e1000e psmouse ahci ptp libahci pps_core wmi i2c_hid video hid
>[13336.154811] CPU: 11 PID: 5002 Comm: gem_exec_reloc Tainted: G     U  W    L   4.15.0-rc5-drm-tip-ww52-commit-42a41a5+ #1
>[13336.154812] Hardware name: Intel Corporation CoffeeLake Client Platform/CoffeeLake S UDIMM RVP, BIOS CNLSFWR1.R00.X095.A04.1707240838 07/24/2017
>[13336.154828] RIP: 0010:i915_exit+0x44/0x174 [i915]
>[13336.154829] RSP: 0018:ffffb4eb86a0f8e8 EFLAGS: 00050246 ORIG_RAX: ffffffffffffff11
>[13336.154829] RAX: 0000000000000000 RBX: ffffb4eb86a0fb70 RCX: 0000000000000000
>[13336.154830] RDX: 0000000000000000 RSI: 0000000000000000 RDI: 0000000000000ff8
>[13336.154830] RBP: ffff89a25893e3c0 R08: 0000000000000400 R09: 0000000005a6a888
>[13336.154831] R10: ffff89a25893e3c0 R11: 0000000000000001 R12: 00007f6ff209f210
>[13336.154831] R13: 00007f6ff209f110 R14: ffffb4eb86a0f9f8 R15: ffff89a253c2cc40
>[13336.154831] FS:  00007f703ff3a880(0000) GS:ffff89a25d4c0000(0000) knlGS:0000000000000000
>[13336.154832] CS:  0010 DS: 0000 ES: 0000 CR0: 0000000080050033
>[13336.154832] CR2: 00007f6ff209f110 CR3: 00000003405f8005 CR4: 00000000003606e0
>[13336.154833] DR0: 0000000000000000 DR1: 0000000000000000 DR2: 0000000000000000
>[13336.154833] DR3: 0000000000000000 DR6: 00000000fffe0ff0 DR7: 0000000000000400
>[13336.154833] Call Trace:
>[13336.154848]  i915_gem_do_execbuffer+0x599/0x1060 [i915]
>[13336.154850]  ? shmem_getpage_gfp+0x79a/0xcb0
>[13336.154852]  ? get_page_from_freelist+0x93e/0x1200
>[13336.154853]  ? get_page_from_freelist+0x282/0x1200
>[13336.154864]  i915_gem_execbuffer2+0xee/0x360 [i915]
>[13336.154873]  ? i915_gem_execbuffer+0x2d0/0x2d0 [i915]
>[13336.154878]  drm_ioctl_kernel+0x65/0xb0 [drm]
>[13336.154883]  drm_ioctl+0x2e5/0x3e0 [drm]
>[13336.154892]  ? i915_gem_execbuffer+0x2d0/0x2d0 [i915]
>[13336.154894]  do_vfs_ioctl+0x9f/0x5f0
>[13336.154896]  SyS_ioctl+0x74/0x80
>[13336.154898]  entry_SYSCALL_64_fastpath+0x1e/0x81
>[13336.154899] RIP: 0033:0x7f703e4494b7
>[13336.154899] RSP: 002b:00007ffc5a519008 EFLAGS: 00000246 ORIG_RAX: 0000000000000010
>[13336.154900] RAX: ffffffffffffffda RBX: 0000000000000003 RCX: 00007f703e4494b7
>[13336.154900] RDX: 00007ffc5a5190c0 RSI: 0000000040406469 RDI: 0000000000000003
>[13336.154900] RBP: 00007f6f3d34e000 R08: ffffffffffffffff R09: 0000000000000000
>[13336.154901] R10: 0000000000000487 R11: 0000000000000246 R12: 0000000100000000
>[13336.154901] R13: 00007ffc5a519080 R14: 0000000000000100 R15: 0000000008000000
>[13336.154902] Code: ff ff ff e9 42 aa f1 ff b9 f2 ff ff ff e9 4a aa f1 ff b8 f2 ff ff ff 40 30 f6 e9 4d c2 f2 ff b8 f2 ff ff ff 30 d2 e9 52 c2 f2 ff <ba> f2 ff ff ff e9 08 dd f2 ff b8 f2 ff ff ff e9 b9 e1 f2 ff b8 
>[13389.769543] [IGT] gem_exec_reloc: exiting, ret=0
>[13389.808795] [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000000c9060d5
>[13389.808825] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000642297cb state to 000000000c9060d5
>[13389.808848] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:37:pipe A] 00000000c85dec7a state to 000000000c9060d5
>[13389.808867] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 2A] 00000000f2dfac7d state to 000000000c9060d5
>[13389.808883] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 00000000f2dfac7d to [NOCRTC]
>[13389.808900] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for plane state 00000000f2dfac7d
>[13389.808917] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:34:cursor A] 00000000635b6cc5 state to 000000000c9060d5
>[13389.808932] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 00000000635b6cc5 to [NOCRTC]
>[13389.808947] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for plane state 00000000635b6cc5
>[13389.808963] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:38:plane 1B] 0000000083abc19d state to 000000000c9060d5
>[13389.808979] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:47:pipe B] 00000000ba1798da state to 000000000c9060d5
>[13389.808995] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:41:plane 2B] 000000003820da89 state to 000000000c9060d5
>[13389.809009] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 000000003820da89 to [NOCRTC]
>[13389.809024] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for plane state 000000003820da89
>[13389.809040] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:44:cursor B] 000000006811d9f1 state to 000000000c9060d5
>[13389.809055] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 000000006811d9f1 to [NOCRTC]
>[13389.809069] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for plane state 000000006811d9f1
>[13389.809090] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [MODE:1920x1080] for CRTC state 00000000c85dec7a
>[13389.809105] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 00000000642297cb to [CRTC:37:pipe A]
>[13389.809121] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:115] for plane state 00000000642297cb
>[13389.809137] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:37:pipe A] to 000000000c9060d5
>[13389.809155] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:56:DP-1] 00000000196eb59e state to 000000000c9060d5
>[13389.809171] [drm:drm_atomic_set_crtc_for_connector [drm]] Link connector state 00000000196eb59e to [NOCRTC]
>[13389.809186] [drm:drm_atomic_set_crtc_for_connector [drm]] Link connector state 00000000196eb59e to [CRTC:37:pipe A]
>[13389.809204] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [MODE:1920x1200] for CRTC state 00000000ba1798da
>[13389.809219] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 0000000083abc19d to [CRTC:47:pipe B]
>[13389.809233] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:115] for plane state 0000000083abc19d
>[13389.809248] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:47:pipe B] to 000000000c9060d5
>[13389.809265] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:61:DP-2] 00000000749bfb4e state to 000000000c9060d5
>[13389.809280] [drm:drm_atomic_set_crtc_for_connector [drm]] Link connector state 00000000749bfb4e to [NOCRTC]
>[13389.809295] [drm:drm_atomic_set_crtc_for_connector [drm]] Link connector state 00000000749bfb4e to [CRTC:47:pipe B]
>[13389.809310] [drm:drm_atomic_check_only [drm]] checking 000000000c9060d5
>[13389.809331] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:56:DP-1]
>[13389.809342] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:56:DP-1] keeps [ENCODER:55:DDI B], now on [CRTC:37:pipe A]
>[13389.809351] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:61:DP-2]
>[13389.809361] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:61:DP-2] keeps [ENCODER:60:DDI C], now on [CRTC:47:pipe B]
>[13389.809442] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:37:pipe A] has [PLANE:28:plane 1A] with fb 115
>[13389.809502] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>[13389.809559] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:47:pipe B] has [PLANE:38:plane 1B] with fb 115
>[13389.809612] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:38:plane 1B] visible 1 -> 1, off 0, on 0, ms 0
>[13389.809646] [drm:drm_atomic_commit [drm]] committing 000000000c9060d5
>[13389.823552] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000000c9060d5
>[13389.823587] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000000c9060d5
>[13389.888557] [IGT] gem_exec_suspend: executing
>[13389.933003] Setting dangerous option reset - tainting kernel
>[13389.933848] Setting dangerous option reset - tainting kernel
>[13389.933910] [IGT] gem_exec_suspend: starting subtest hang-S3
>[13390.305889] PM: suspend entry (deep)
>[13390.305892] PM: Syncing filesystems ... done.
>[13390.310801] Freezing user space processes ... (elapsed 0.001 seconds) done.
>[13390.312470] OOM killer disabled.
>[13390.312471] Freezing remaining freezable tasks ... (elapsed 0.001 seconds) done.
>[13390.313755] Suspending console(s) (use no_console_suspend to debug)
>[13390.651625] e1000e: EEE TX LPI TIMER: 00000011
>[13390.652038] [drm:intel_power_well_enable [i915]] enabling DDI A/E IO power well
>[13390.652072] [drm:intel_power_well_enable [i915]] enabling DDI D IO power well
>[13390.652742] sd 3:0:0:0: [sda] Synchronizing SCSI cache
>[13390.652895] sd 3:0:0:0: [sda] Stopping disk
>[13394.744749] missed_breadcrumb rcs0 missed breadcrumb at intel_breadcrumbs_hangcheck+0x59/0x80 [i915]
>[13394.744752] missed_breadcrumb 	current seqno 2853b5, last 2853b7, hangcheck 2853b5 [992 ms], inflight 2
>[13394.744753] missed_breadcrumb 	Reset count: 38 (global 0)
>[13394.744754] missed_breadcrumb 	Requests:
>[13394.744756] missed_breadcrumb 		first  2853b6 [2:807] prio=0 @ 4476ms: gem_exec_suspen[5006]/0
>[13394.744758] missed_breadcrumb 		last   2853b7 [0:b] prio=-1024 @ 4096ms: [kernel]
>[13394.744760] missed_breadcrumb 		active 2853b6 [2:807] prio=0 @ 4476ms: gem_exec_suspen[5006]/0
>[13394.744762] missed_breadcrumb 		[head 0300, postfix 0358, tail 0378, batch 0x00000000_0004e000]
>[13394.744765] missed_breadcrumb 	RING_START: 0x000f6000 [0x000f6000]
>[13394.744767] missed_breadcrumb 	RING_HEAD:  0x00000340 [0x000002d8]
>[13394.744768] missed_breadcrumb 	RING_TAIL:  0x00000378 [0x00000378]
>[13394.744770] missed_breadcrumb 	RING_CTL:   0x00003001
>[13394.744772] missed_breadcrumb 	RING_MODE:  0x00000000
>[13394.744774] missed_breadcrumb 	ACTHD:  0x00000000_0004eb00
>[13394.744776] missed_breadcrumb 	BBADDR: 0x00000000_0004e04d
>[13394.744778] missed_breadcrumb 	DMA_FADDR: 0x00000000_0004eb00
>[13394.744779] missed_breadcrumb 	IPEIR: 0x00000000
>[13394.744780] missed_breadcrumb 	IPEHR: 0x02800000
>[13394.744782] missed_breadcrumb 	Execlist status: 0x00024049 001feda1
>[13394.744784] missed_breadcrumb 	Execlist CSB read 4 [-1 cached], write 4 [4 from hws], interrupt posted? no
>[13394.744786] missed_breadcrumb 		ELSP[0] count=1, rq: 2853b6 [2:807] prio=0 @ 4476ms: gem_exec_suspen[5006]/0
>[13394.744788] missed_breadcrumb 		ELSP[1] count=1, rq: 2853b7 [0:b] prio=-1024 @ 4096ms: [kernel]
>[13394.744789] missed_breadcrumb 		HW active? 0x1
>[13394.744790] missed_breadcrumb 		E 2853b6 [2:807] prio=0 @ 4476ms: gem_exec_suspen[5006]/0
>[13394.744791] missed_breadcrumb 		E 2853b7 [0:b] prio=-1024 @ 4096ms: [kernel]
>[13394.744793] missed_breadcrumb 	kworker/u24:10 [5020] waiting for 2853b6
>[13394.744794] missed_breadcrumb 	RING_IMR: fffffefe
>[13394.744795] missed_breadcrumb IRQ? 0x1 (breadcrumbs? yes) (execlists? no)
>[13394.744796] missed_breadcrumb HWSP:
>[13394.744799] missed_breadcrumb 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
>[13394.744800] missed_breadcrumb *
>[13394.744803] missed_breadcrumb 00000040 00000001 00000000 00008002 001feda1 00000018 001feda1 00000001 00000000
>[13394.744805] missed_breadcrumb 00000060 00008002 001feda1 00000018 001feda1 00000000 00000000 00000000 00000004
>[13394.744807] missed_breadcrumb 00000080 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
>[13394.744808] missed_breadcrumb *
>[13394.744810] missed_breadcrumb 000000c0 002853b5 00000000 00000000 00000000 00000000 00000000 00000000 00000000
>[13394.744812] missed_breadcrumb 000000e0 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
>[13394.744812] missed_breadcrumb *
>[13394.744821] missed_breadcrumb Idle? no
>[13407.775342] [drm] GPU HANG: ecode 9:0:0xfd57ffff, in gem_exec_suspen [5006], reason: No progress on rcs0, action: reset
>[13407.775410] i915 0000:00:02.0: Resetting rcs0 after gpu hang
>[13407.775497] [drm:i915_gem_reset_engine [i915]] context gem_exec_suspen[5006]/0 marked guilty (score 10) banned? no
>[13407.775509] [drm:i915_gem_reset_engine [i915]] resetting rcs0 to restart from tail of request 0x2853b6
>[13407.775533] [drm:gen8_init_common_ring [i915]] Execlists enabled for rcs0
>[13407.775550] [drm:init_workarounds_ring [i915]] rcs0: Number of context specific w/a: 14
>[13407.775816] [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000045de3ffe
>[13407.775822] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:37:pipe A] 000000009da7b28a state to 0000000045de3ffe
>[13407.775827] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:47:pipe B] 00000000c9b9252e state to 0000000045de3ffe
>[13407.775832] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 000000003ca57d4c state to 0000000045de3ffe
>[13407.775836] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 2A] 00000000b1044218 state to 0000000045de3ffe
>[13407.775840] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:34:cursor A] 00000000e6a5836e state to 0000000045de3ffe
>[13407.775844] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:38:plane 1B] 00000000eee3a0f1 state to 0000000045de3ffe
>[13407.775847] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:41:plane 2B] 0000000036bc30be state to 0000000045de3ffe
>[13407.775851] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:44:cursor B] 00000000e0063903 state to 0000000045de3ffe
>[13407.775856] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:49:eDP-1] 00000000bdecfa11 state to 0000000045de3ffe
>[13407.775860] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:56:DP-1] 000000003e4f0aba state to 0000000045de3ffe
>[13407.775863] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:61:DP-2] 00000000f41a1457 state to 0000000045de3ffe
>[13407.775867] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:64:HDMI-A-1] 00000000397b1939 state to 0000000045de3ffe
>[13407.775871] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:67:DP-3] 00000000d9bd96c0 state to 0000000045de3ffe
>[13407.775875] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:70:HDMI-A-2] 0000000067b35101 state to 0000000045de3ffe
>[13407.775879] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000efeb3c9c
>[13407.775883] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:37:pipe A] 000000009b605e0f state to 00000000efeb3c9c
>[13407.775887] [drm:drm_atomic_set_mode_prop_for_crtc [drm]] Set [NOMODE] for CRTC state 000000009b605e0f
>[13407.775890] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000e8360f9a state to 00000000efeb3c9c
>[13407.775894] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:37:pipe A] to 00000000efeb3c9c
>[13407.775898] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:56:DP-1] 000000006dfba5a9 state to 00000000efeb3c9c
>[13407.775902] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:47:pipe B] 00000000783a3c54 state to 00000000efeb3c9c
>[13407.775906] [drm:drm_atomic_set_mode_prop_for_crtc [drm]] Set [NOMODE] for CRTC state 00000000783a3c54
>[13407.775909] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:38:plane 1B] 00000000e0580072 state to 00000000efeb3c9c
>[13407.775913] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:47:pipe B] to 00000000efeb3c9c
>[13407.775917] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:61:DP-2] 00000000033a2b53 state to 00000000efeb3c9c
>[13407.775920] [drm:drm_atomic_set_crtc_for_connector [drm]] Link connector state 000000006dfba5a9 to [NOCRTC]
>[13407.775924] [drm:drm_atomic_set_crtc_for_connector [drm]] Link connector state 00000000033a2b53 to [NOCRTC]
>[13407.775927] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 00000000e8360f9a to [NOCRTC]
>[13407.775930] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for plane state 00000000e8360f9a
>[13407.775934] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 00000000e0580072 to [NOCRTC]
>[13407.775937] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for plane state 00000000e0580072
>[13407.775941] [drm:drm_atomic_check_only [drm]] checking 00000000efeb3c9c
>[13407.775946] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:37:pipe A] mode changed
>[13407.775949] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:37:pipe A] enable changed
>[13407.775951] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:37:pipe A] active changed
>[13407.775953] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:47:pipe B] mode changed
>[13407.775954] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:47:pipe B] enable changed
>[13407.775956] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:47:pipe B] active changed
>[13407.775958] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:56:DP-1]
>[13407.775960] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Disabling [CONNECTOR:56:DP-1]
>[13407.775962] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:61:DP-2]
>[13407.775964] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Disabling [CONNECTOR:61:DP-2]
>[13407.775966] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:37:pipe A] needs all connectors, enable: n, active: n
>[13407.775970] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:37:pipe A] to 00000000efeb3c9c
>[13407.775973] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:47:pipe B] needs all connectors, enable: n, active: n
>[13407.775977] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:47:pipe B] to 00000000efeb3c9c
>[13407.775994] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[13407.776008] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[13407.776023] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:37:pipe A] has [PLANE:28:plane 1A] with fb -1
>[13407.776036] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 0, off 1, on 0, ms 1
>[13407.776048] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:47:pipe B] has [PLANE:38:plane 1B] with fb -1
>[13407.776060] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:38:plane 1B] visible 1 -> 0, off 1, on 0, ms 1
>[13407.776072] [drm:skl_compute_wm [i915]] [PLANE:28:plane 1A] ddb (0 - 438) -> (0 - 0)
>[13407.776082] [drm:skl_compute_wm [i915]] [PLANE:34:cursor A] ddb (438 - 446) -> (0 - 0)
>[13407.776091] [drm:skl_compute_wm [i915]] [PLANE:38:plane 1B] ddb (446 - 884) -> (0 - 0)
>[13407.776101] [drm:skl_compute_wm [i915]] [PLANE:44:cursor B] ddb (884 - 892) -> (0 - 0)
>[13407.776106] [drm:drm_atomic_commit [drm]] committing 00000000efeb3c9c
>[13407.776127] [drm:hsw_audio_codec_disable [i915]] Disable audio codec on pipe A
>[13407.776143] [drm:intel_disable_pipe [i915]] disabling pipe A
>[13407.792381] [drm:__intel_fbc_disable [i915]] Disabling FBC on pipe A
>[13407.792401] [drm:intel_disable_shared_dpll [i915]] disable DPLL 1 (active 1, on? 1) for crtc 37
>[13407.792418] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 1
>[13407.792445] [drm:intel_disable_pipe [i915]] disabling pipe B
>[13407.795309] [drm:intel_disable_shared_dpll [i915]] disable DPLL 2 (active 2, on? 1) for crtc 47
>[13407.795328] [drm:intel_disable_shared_dpll [i915]] disabling DPLL 2
>[13407.795354] [drm:intel_atomic_commit_tail [i915]] [ENCODER:48:DDI A]
>[13407.795370] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI B]
>[13407.795386] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[13407.795400] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[13407.795413] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DDI C]
>[13407.795427] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST A]
>[13407.795441] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST B]
>[13407.795454] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI D]
>[13407.795468] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[13407.795481] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[13407.795496] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:56:DP-1]
>[13407.795511] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:61:DP-2]
>[13407.795526] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[13407.795541] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[13407.795555] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[13407.795569] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[13407.795586] [drm:intel_atomic_commit_tail [i915]] [CRTC:37:pipe A]
>[13407.795603] [drm:intel_atomic_commit_tail [i915]] [CRTC:47:pipe B]
>[13407.795617] [drm:intel_enable_sagv [i915]] Enabling the SAGV
>[13407.795629] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000efeb3c9c
>[13407.795637] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000efeb3c9c
>[13407.796419] PM: Some devices failed to suspend, or early wake event detected
>[13407.796763] [drm:intel_opregion_setup [i915]] graphic opregion physical addr: 0x8cb14018
>[13407.796800] [drm:intel_opregion_setup [i915]] Public ACPI methods supported
>[13407.796826] [drm:intel_opregion_setup [i915]] SWSCI supported
>[13407.797745] serial 00:06: activated
>[13407.798455] [drm:intel_opregion_setup [i915]] SWSCI GBDA callbacks 00000cb3, SBCB callbacks 00300483
>[13407.798471] [drm:intel_opregion_setup [i915]] ASLE supported
>[13407.798487] [drm:intel_opregion_setup [i915]] ASLE extension supported
>[13407.798502] [drm:intel_opregion_setup [i915]] Found valid VBT in ACPI OpRegion (Mailbox #4)
>[13407.799649] [drm:intel_dp_init_panel_power_sequencer_registers [i915]] panel power sequencer register settings: PP_ON 0x7d00001, PP_OFF 0x1f40001, PP_DIV 0x60
>[13407.799843] sd 3:0:0:0: [sda] Starting disk
>[13407.800015] [drm:lspcon_wake_native_aux_ch [i915]] Native AUX CH up, DPCD version: 1.2
>[13407.800089] [drm:lspcon_resume [i915]] LSPCON recovering in PCON mode after 0 ms
>[13407.800507] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13407.801753] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13407.802965] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13407.804120] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13407.805277] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13407.806081] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[13407.806165] [drm:intel_uc_fw_upload [i915]] HuC fw load i915/kbl_huc_ver02_00_1810.bin
>[13407.806185] [drm:intel_uc_fw_upload [i915]] HuC fw load PENDING
>[13407.806859] [drm:huc_ucode_xfer [i915]] HuC DMA transfer wait over with ret 0
>[13407.806880] [drm:intel_uc_fw_upload [i915]] HuC fw load SUCCESS
>[13407.806881] [drm] HuC: Loaded firmware i915/kbl_huc_ver02_00_1810.bin (version 2.0)
>[13407.806907] [drm:intel_uc_fw_upload [i915]] GuC fw load i915/kbl_guc_ver9_39.bin
>[13407.806925] [drm:intel_uc_fw_upload [i915]] GuC fw load PENDING
>[13407.807297] [drm:guc_fw_xfer [i915]] GuC DMA status 0x10
>[13407.809883] [drm:guc_fw_xfer [i915]] GuC status 0x8002f0ec
>[13407.809902] [drm:intel_uc_fw_upload [i915]] GuC fw load SUCCESS
>[13407.809903] [drm] GuC: Loaded firmware i915/kbl_guc_ver9_39.bin (version 9.39)
>[13407.810020] i915 0000:00:02.0: GuC firmware version 9.39
>[13407.810021] i915 0000:00:02.0: GuC submission enabled
>[13407.810022] i915 0000:00:02.0: HuC enabled
>[13407.810085] [drm:gen8_init_common_ring [i915]] Execlists enabled for rcs0
>[13407.810116] [drm:init_workarounds_ring [i915]] rcs0: Number of context specific w/a: 14
>[13407.810161] [drm:gen8_init_common_ring [i915]] Execlists enabled for bcs0
>[13407.810206] [drm:gen8_init_common_ring [i915]] Execlists enabled for vcs0
>[13407.810256] [drm:gen8_init_common_ring [i915]] Execlists enabled for vecs0
>[13407.810549] [drm:intel_dump_cdclk_state [i915]] Current CDCLK 337500 kHz, VCO 8100000 kHz, ref 24000 kHz, voltage level 0
>[13407.811097] [drm:intel_modeset_setup_hw_state [i915]] pipe A active planes 0x0
>[13407.811120] [drm:intel_modeset_setup_hw_state [i915]] pipe A active planes 0x0
>[13407.811142] [drm:intel_modeset_setup_hw_state [i915]] pipe A active planes 0x0
>[13407.811163] [drm:intel_modeset_setup_hw_state [i915]] [CRTC:37:pipe A] hw state readout: disabled
>[13407.811184] [drm:intel_modeset_setup_hw_state [i915]] pipe B active planes 0x0
>[13407.811204] [drm:intel_modeset_setup_hw_state [i915]] pipe B active planes 0x0
>[13407.811224] [drm:intel_modeset_setup_hw_state [i915]] pipe B active planes 0x0
>[13407.811243] [drm:intel_modeset_setup_hw_state [i915]] [CRTC:47:pipe B] hw state readout: disabled
>[13407.811263] [drm:intel_modeset_setup_hw_state [i915]] DPLL 0 hw state readout: crtc_mask 0x00000000, on 1
>[13407.811282] [drm:intel_modeset_setup_hw_state [i915]] DPLL 1 hw state readout: crtc_mask 0x00000000, on 0
>[13407.811302] [drm:intel_modeset_setup_hw_state [i915]] DPLL 2 hw state readout: crtc_mask 0x00000000, on 0
>[13407.811321] [drm:intel_modeset_setup_hw_state [i915]] DPLL 3 hw state readout: crtc_mask 0x00000000, on 0
>[13407.811360] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:48:DDI A] hw state readout: disabled, pipe A
>[13407.811382] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:55:DDI B] hw state readout: disabled, pipe A
>[13407.811404] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:57:DP-MST A] hw state readout: disabled, pipe A
>[13407.811425] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:58:DP-MST B] hw state readout: disabled, pipe B
>[13407.811447] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:60:DDI C] hw state readout: disabled, pipe A
>[13407.811468] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:62:DP-MST A] hw state readout: disabled, pipe A
>[13407.811489] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:63:DP-MST B] hw state readout: disabled, pipe B
>[13407.811510] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:66:DDI D] hw state readout: disabled, pipe A
>[13407.811531] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:68:DP-MST A] hw state readout: disabled, pipe A
>[13407.811552] [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:69:DP-MST B] hw state readout: disabled, pipe B
>[13407.811574] [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:49:eDP-1] hw state readout: disabled
>[13407.811595] [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:56:DP-1] hw state readout: disabled
>[13407.811617] [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:61:DP-2] hw state readout: disabled
>[13407.811638] [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:64:HDMI-A-1] hw state readout: disabled
>[13407.811660] [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:67:DP-3] hw state readout: disabled
>[13407.811682] [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:70:HDMI-A-2] hw state readout: disabled
>[13407.811710] [drm:intel_dump_pipe_config [i915]] [CRTC:37:pipe A][setup_hw_state]
>[13407.811735] [drm:intel_dump_pipe_config [i915]] output_types:  (0x0)
>[13407.811759] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 0, dithering: 0
>[13407.811783] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[13407.811805] [drm:intel_dump_pipe_config [i915]] requested mode:
>[13407.811818] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[13407.811841] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[13407.811853] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[13407.811877] [drm:intel_dump_pipe_config [i915]] crtc timings: 0 0 0 0 0 0 0 0 0, type: 0x0 flags: 0x0
>[13407.811900] [drm:intel_dump_pipe_config [i915]] port clock: 0, pipe src size: 0x0, pixel rate 0
>[13407.811922] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[13407.811943] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[13407.811964] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[13407.811986] [drm:intel_dump_pipe_config [i915]] dpll_hw_state: ctrl1: 0x0, cfgcr1: 0x0, cfgcr2: 0x0
>[13407.812007] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[13407.812029] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 1A] disabled, scaler_id = -1
>[13407.812050] [drm:intel_dump_pipe_config [i915]] [PLANE:31:plane 2A] disabled, scaler_id = -1
>[13407.812071] [drm:intel_dump_pipe_config [i915]] [PLANE:34:cursor A] disabled, scaler_id = -1
>[13407.812092] [drm:intel_dump_pipe_config [i915]] [CRTC:47:pipe B][setup_hw_state]
>[13407.812113] [drm:intel_dump_pipe_config [i915]] output_types:  (0x0)
>[13407.812134] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 0, dithering: 0
>[13407.812155] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[13407.812176] [drm:intel_dump_pipe_config [i915]] requested mode:
>[13407.812188] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[13407.812209] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[13407.812221] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[13407.812243] [drm:intel_dump_pipe_config [i915]] crtc timings: 0 0 0 0 0 0 0 0 0, type: 0x0 flags: 0x0
>[13407.812265] [drm:intel_dump_pipe_config [i915]] port clock: 0, pipe src size: 0x0, pixel rate 0
>[13407.812286] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[13407.812307] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[13407.812328] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[13407.812349] [drm:intel_dump_pipe_config [i915]] dpll_hw_state: ctrl1: 0x0, cfgcr1: 0x0, cfgcr2: 0x0
>[13407.812369] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[13407.812390] [drm:intel_dump_pipe_config [i915]] [PLANE:38:plane 1B] disabled, scaler_id = -1
>[13407.812411] [drm:intel_dump_pipe_config [i915]] [PLANE:41:plane 2B] disabled, scaler_id = -1
>[13407.812432] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor B] disabled, scaler_id = -1
>[13407.812458] [drm:intel_modeset_setup_hw_state [i915]] DPLL 0 enabled but not in use, disabling
>[13407.812496] [drm:intel_power_well_disable [i915]] disabling DDI D IO power well
>[13407.812517] [drm:intel_power_well_disable [i915]] disabling DDI C IO power well
>[13407.812537] [drm:intel_power_well_disable [i915]] disabling DDI B IO power well
>[13407.812561] [drm:intel_power_well_disable [i915]] disabling DDI A/E IO power well
>[13407.812581] [drm:intel_power_well_disable [i915]] disabling power well 2
>[13407.812600] [drm:drm_atomic_check_only [drm]] checking 0000000045de3ffe
>[13407.812608] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:37:pipe A] mode changed
>[13407.812612] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:37:pipe A] enable changed
>[13407.812617] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:37:pipe A] active changed
>[13407.812621] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:47:pipe B] mode changed
>[13407.812625] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:47:pipe B] enable changed
>[13407.812629] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:47:pipe B] active changed
>[13407.812635] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:49:eDP-1]
>[13407.812639] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Disabling [CONNECTOR:49:eDP-1]
>[13407.812643] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:56:DP-1]
>[13407.812648] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:56:DP-1] keeps [ENCODER:55:DDI B], now on [CRTC:37:pipe A]
>[13407.812652] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:61:DP-2]
>[13407.812656] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:61:DP-2] keeps [ENCODER:60:DDI C], now on [CRTC:47:pipe B]
>[13407.812661] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:64:HDMI-A-1]
>[13407.812666] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Disabling [CONNECTOR:64:HDMI-A-1]
>[13407.812678] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:67:DP-3]
>[13407.812684] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Disabling [CONNECTOR:67:DP-3]
>[13407.812688] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:70:HDMI-A-2]
>[13407.812692] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Disabling [CONNECTOR:70:HDMI-A-2]
>[13407.812696] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:37:pipe A] needs all connectors, enable: y, active: y
>[13407.812708] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:37:pipe A] to 0000000045de3ffe
>[13407.812713] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:47:pipe B] needs all connectors, enable: y, active: y
>[13407.812725] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:47:pipe B] to 0000000045de3ffe
>[13407.812740] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:37:pipe A] to 0000000045de3ffe
>[13407.812770] [drm:intel_atomic_check [i915]] [CONNECTOR:56:DP-1] checking for sink bpp constrains
>[13407.812803] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 540000 pixel clock 148500KHz
>[13407.812839] [drm:intel_dp_compute_config [i915]] DP link bw 0a rate select 00 lane count 4 clock 270000 bpp 36
>[13407.812864] [drm:intel_dp_compute_config [i915]] DP link bw required 668250 available 1080000
>[13407.812892] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 36, dithering: 0
>[13407.812919] [drm:intel_dump_pipe_config [i915]] [CRTC:37:pipe A][modeset]
>[13407.812945] [drm:intel_dump_pipe_config [i915]] output_types: DP (0x80)
>[13407.812970] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: A, pipe bpp: 36, dithering: 0
>[13407.812994] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5190451, gmch_n: 8388608, link_m: 288358, link_n: 524288, tu: 64
>[13407.813017] [drm:intel_dump_pipe_config [i915]] audio: 1, infoframes: 0
>[13407.813039] [drm:intel_dump_pipe_config [i915]] requested mode:
>[13407.813052] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x9
>[13407.813075] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[13407.813087] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1080" 60 148500 1920 2008 2052 2200 1080 1084 1089 1125 0x48 0x9
>[13407.813111] [drm:intel_dump_pipe_config [i915]] crtc timings: 148500 1920 2008 2052 2200 1080 1084 1089 1125, type: 0x48 flags: 0x9
>[13407.813134] [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1080, pixel rate 148500
>[13407.813156] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[13407.813178] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[13407.813200] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[13407.813221] [drm:intel_dump_pipe_config [i915]] dpll_hw_state: ctrl1: 0x3, cfgcr1: 0x0, cfgcr2: 0x0
>[13407.813242] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[13407.813263] [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 1A] disabled, scaler_id = -1
>[13407.813285] [drm:intel_dump_pipe_config [i915]] [PLANE:31:plane 2A] disabled, scaler_id = -1
>[13407.813306] [drm:intel_dump_pipe_config [i915]] [PLANE:34:cursor A] disabled, scaler_id = -1
>[13407.813318] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:47:pipe B] to 0000000045de3ffe
>[13407.813345] [drm:intel_atomic_check [i915]] [CONNECTOR:61:DP-2] checking for sink bpp constrains
>[13407.813369] [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 24
>[13407.813396] [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max bw 270000 pixel clock 154000KHz
>[13407.813428] [drm:intel_dp_compute_config [i915]] DP link bw 06 rate select 00 lane count 4 clock 162000 bpp 24
>[13407.813453] [drm:intel_dp_compute_config [i915]] DP link bw required 462000 available 648000
>[13407.813479] [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>[13407.813504] [drm:intel_dump_pipe_config [i915]] [CRTC:47:pipe B][modeset]
>[13407.813527] [drm:intel_dump_pipe_config [i915]] output_types: DP (0x80)
>[13407.813550] [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 24, dithering: 0
>[13407.813573] [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 5980766, gmch_n: 8388608, link_m: 249198, link_n: 262144, tu: 64
>[13407.813595] [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>[13407.813616] [drm:intel_dump_pipe_config [i915]] requested mode:
>[13407.813628] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[13407.813651] [drm:intel_dump_pipe_config [i915]] adjusted mode:
>[13407.813663] [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1200" 60 154000 1920 1968 2000 2080 1200 1203 1209 1235 0x48 0x9
>[13407.813686] [drm:intel_dump_pipe_config [i915]] crtc timings: 154000 1920 1968 2000 2080 1200 1203 1209 1235, type: 0x48 flags: 0x9
>[13407.813708] [drm:intel_dump_pipe_config [i915]] port clock: 162000, pipe src size: 1920x1200, pixel rate 154000
>[13407.813730] [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>[13407.813751] [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>[13407.813773] [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>[13407.813793] [drm:intel_dump_pipe_config [i915]] dpll_hw_state: ctrl1: 0x5, cfgcr1: 0x0, cfgcr2: 0x0
>[13407.813814] [drm:intel_dump_pipe_config [i915]] planes on this crtc
>[13407.813835] [drm:intel_dump_pipe_config [i915]] [PLANE:38:plane 1B] disabled, scaler_id = -1
>[13407.813855] [drm:intel_dump_pipe_config [i915]] [PLANE:41:plane 2B] disabled, scaler_id = -1
>[13407.813876] [drm:intel_dump_pipe_config [i915]] [PLANE:44:cursor B] disabled, scaler_id = -1
>[13407.813902] [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>[13407.813926] [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>[13407.813954] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:37:pipe A] has [PLANE:28:plane 1A] with fb 115
>[13407.813979] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 0 -> 1, off 0, on 1, ms 1
>[13407.814003] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:47:pipe B] has [PLANE:38:plane 1B] with fb 115
>[13407.814026] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:38:plane 1B] visible 0 -> 1, off 0, on 1, ms 1
>[13407.814053] [drm:intel_find_shared_dpll [i915]] [CRTC:37:pipe A] allocated DPLL 1
>[13407.814078] [drm:intel_reference_shared_dpll [i915]] using DPLL 1 for pipe A
>[13407.814103] [drm:intel_find_shared_dpll [i915]] [CRTC:47:pipe B] allocated DPLL 2
>[13407.814126] [drm:intel_reference_shared_dpll [i915]] using DPLL 2 for pipe B
>[13407.814150] [drm:skl_compute_wm [i915]] [PLANE:28:plane 1A] ddb (0 - 0) -> (0 - 438)
>[13407.814170] [drm:skl_compute_wm [i915]] [PLANE:34:cursor A] ddb (0 - 0) -> (438 - 446)
>[13407.814190] [drm:skl_compute_wm [i915]] [PLANE:38:plane 1B] ddb (0 - 0) -> (446 - 884)
>[13407.814209] [drm:skl_compute_wm [i915]] [PLANE:44:cursor B] ddb (0 - 0) -> (884 - 892)
>[13407.814221] [drm:drm_atomic_commit [drm]] committing 0000000045de3ffe
>[13407.814254] [drm:intel_power_well_enable [i915]] enabling power well 2
>[13407.814282] [drm:intel_disable_sagv [i915]] Disabling the SAGV
>[13407.814319] [drm:intel_atomic_commit_tail [i915]] [ENCODER:48:DDI A]
>[13407.814344] [drm:intel_atomic_commit_tail [i915]] [ENCODER:55:DDI B]
>[13407.814368] [drm:intel_atomic_commit_tail [i915]] [ENCODER:57:DP-MST A]
>[13407.814391] [drm:intel_atomic_commit_tail [i915]] [ENCODER:58:DP-MST B]
>[13407.814414] [drm:intel_atomic_commit_tail [i915]] [ENCODER:60:DDI C]
>[13407.814436] [drm:intel_atomic_commit_tail [i915]] [ENCODER:62:DP-MST A]
>[13407.814458] [drm:intel_atomic_commit_tail [i915]] [ENCODER:63:DP-MST B]
>[13407.814479] [drm:intel_atomic_commit_tail [i915]] [ENCODER:66:DDI D]
>[13407.814500] [drm:intel_atomic_commit_tail [i915]] [ENCODER:68:DP-MST A]
>[13407.814522] [drm:intel_atomic_commit_tail [i915]] [ENCODER:69:DP-MST B]
>[13407.814546] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:49:eDP-1]
>[13407.814571] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:64:HDMI-A-1]
>[13407.814595] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:67:DP-3]
>[13407.814618] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:70:HDMI-A-2]
>[13407.814641] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 0
>[13407.814663] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[13407.814685] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[13407.814707] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 3
>[13407.814735] [drm:intel_enable_shared_dpll [i915]] enable DPLL 1 (active 1, on? 0) for crtc 37
>[13407.814760] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 1
>[13407.814863] [drm:intel_power_well_enable [i915]] enabling DDI B IO power well
>[13407.815432] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13407.816593] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13407.817764] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13407.818924] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13407.820090] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13407.820866] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[13407.821790] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[13407.821814] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[13407.821837] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[13407.821860] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[13407.840395] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[13407.840419] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS3
>[13407.858962] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[13407.859294] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:56:DP-1] Link Training Passed at Link Rate = 270000, Lane count = 4
>[13407.859774] [drm:intel_enable_pipe [i915]] enabling pipe A
>[13407.859803] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS
>[13407.859823] [drm:intel_audio_codec_enable [i915]] ELD on [CONNECTOR:56:DP-1], [ENCODER:55:DDI B]
>[13407.859842] [drm:hsw_audio_codec_enable [i915]] Enable audio codec on pipe A, 36 bytes ELD
>[13407.859862] [drm:hsw_audio_config_update [i915]] using automatic Maud, Naud
>[13407.859905] [drm:intel_fbc_enable [i915]] reserved 8294400 bytes of contiguous stolen space for FBC, threshold: 1
>[13407.859923] [drm:intel_fbc_enable [i915]] Enabling FBC on pipe A
>[13407.859975] [drm:intel_enable_shared_dpll [i915]] enable DPLL 2 (active 2, on? 0) for crtc 47
>[13407.859992] [drm:intel_enable_shared_dpll [i915]] enabling DPLL 2
>[13407.860086] [drm:intel_power_well_enable [i915]] enabling DDI C IO power well
>[13407.861271] [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>[13407.861289] [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>[13407.861305] [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>[13407.861328] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>[13407.861907] [drm:intel_dp_start_link_train [i915]] clock recovery OK
>[13407.861922] [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>[13407.862816] [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>[13407.863152] [drm:intel_dp_start_link_train [i915]] [CONNECTOR:61:DP-2] Link Training Passed at Link Rate = 162000, Lane count = 4
>[13407.863606] [drm:intel_enable_pipe [i915]] enabling pipe B
>[13407.863643] [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS
>[13407.880373] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:56:DP-1]
>[13407.880389] [drm:intel_atomic_commit_tail [i915]] [CRTC:37:pipe A]
>[13407.880428] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 1
>[13407.880448] [drm:verify_connector_state.isra.111 [i915]] [CONNECTOR:61:DP-2]
>[13407.880462] [drm:intel_atomic_commit_tail [i915]] [CRTC:47:pipe B]
>[13407.880497] [drm:verify_single_dpll_state.isra.112 [i915]] DPLL 2
>[13407.880507] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000045de3ffe
>[13407.880514] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000045de3ffe
>[13407.880949] [drm:intel_opregion_register [i915]] 6 outputs detected
>[13407.880964] [drm:intel_dp_detect [i915]] [CONNECTOR:49:eDP-1]
>[13407.880977] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>[13407.880989] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[13407.881000] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[13407.881055] [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>[13407.881120] [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle
>[13407.881364] [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 00000000 control 00000060
>[13407.881429] [drm:wait_panel_status [i915]] Wait complete
>[13407.881654] [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x00000000 PP_CONTROL: 0x00000068
>[13407.881712] [drm:edp_panel_vdd_on [i915]] eDP port A panel power wasn't enabled
>[13407.983538] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010
>[13407.983572] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[13407.983602] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0
>[13407.983641] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[13408.024724] atkbd serio0: Failed to deactivate keyboard on isa0060/serio0
>[13408.089346] [drm:drm_dp_read_desc [drm_kms_helper]] DP sink: OUI 00-1c-f8 dev-ID q\006UA\022\001 HW-rev 10.0 SW-rev 1.41 quirks 0x0000
>[13408.090568] [drm:drm_helper_hpd_irq_event [drm_kms_helper]] [CONNECTOR:49:eDP-1] status updated from connected to connected
>[13408.090609] [drm:intel_dp_detect [i915]] [CONNECTOR:56:DP-1]
>[13408.090987] [drm:lspcon_wake_native_aux_ch [i915]] Native AUX CH up, DPCD version: 1.2
>[13408.091075] [drm:lspcon_resume [i915]] LSPCON recovering in PCON mode after 0 ms
>[13408.091498] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13408.092681] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13408.093905] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13408.095231] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13408.096406] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13408.097186] [drm:lspcon_wait_mode [i915]] Current LSPCON mode PCON
>[13408.097618] [drm:intel_dp_read_dpcd [i915]] DPCD: 12 14 c4 01 01 15 01 81 00 00 04 00 0f 00 04
>[13408.098341] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>[13408.098373] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000, 540000
>[13408.098404] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000, 540000
>[13408.098784] [drm:drm_dp_read_desc [drm_kms_helper]] DP branch: OUI 00-60-ad dev-ID MC2800 HW-rev 2.2 SW-rev 1.72 quirks 0x0000
>[13408.099101] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[13408.099849] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13408.101020] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13408.102194] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13408.103359] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13408.104532] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13408.105691] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13408.106864] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13408.108037] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13408.109202] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13408.110556] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13408.111857] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13408.113157] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13408.114453] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13408.115745] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13408.116952] OOM killer enabled.
>[13408.116953] Restarting tasks ... 
>[13408.117044] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13408.117406] done.
>[13408.118403] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13408.119686] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13408.120842] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13408.122010] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13408.123176] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13408.124335] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13408.125631] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13408.126916] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13408.128200] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13408.129487] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13408.130778] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13408.132085] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13408.133440] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13408.134744] [drm:drm_dp_i2c_do_msg [drm_kms_helper]] native defer
>[13408.135509] [drm:drm_detect_monitor_audio [drm]] Monitor has basic audio support
>[13408.135780] ata3: SATA link down (SStatus 4 SControl 300)
>[13408.135821] [drm:drm_helper_hpd_irq_event [drm_kms_helper]] [CONNECTOR:56:DP-1] status updated from connected to connected
>[13408.135882] [drm:intel_dp_detect [i915]] [CONNECTOR:61:DP-2]
>[13408.135886] ata2: SATA link down (SStatus 4 SControl 300)
>[13408.135988] ata4: SATA link up 6.0 Gbps (SStatus 133 SControl 300)
>[13408.136399] [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 01 01 00 01 00 02 02 06 05 00 00 00
>[13408.136799] [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>[13408.136848] [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>[13408.136895] [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>[13408.136899] ata4.00: configured for UDMA/133
>[13408.136964] ata4.00: Enabling discard_zeroes_data
>[13408.137301] [drm:drm_dp_read_desc [drm_kms_helper]] DP sink: OUI 00-00-00 dev-ID  HW-rev 0.0 SW-rev 0.0 quirks 0x0000
>[13408.137349] [drm:intel_dp_detect [i915]] Sink is not MST capable
>[13408.141246] [drm:drm_helper_hpd_irq_event [drm_kms_helper]] [CONNECTOR:61:DP-2] status updated from connected to connected
>[13408.141298] [drm:intel_hdmi_detect [i915]] [CONNECTOR:64:HDMI-A-1]
>[13408.142074] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[13408.142115] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[13408.142527] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0050 w(1)
>[13408.142620] [drm:drm_do_probe_ddc_edid [drm]] drm: skipping non-existent adapter i915 gmbus dpc
>[13408.143171] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[13408.143202] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK on first message, retry
>[13408.143692] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] NAK for addr: 0040 w(1)
>[13408.143755] [drm:drm_dp_dual_mode_detect [drm_kms_helper]] DP dual mode HDMI ID:  (err -6)
>[13408.143764] [drm:drm_helper_hpd_irq_event [drm_kms_helper]] [CONNECTOR:64:HDMI-A-1] status updated from disconnected to disconnected
>[13408.143797] [drm:intel_dp_detect [i915]] [CONNECTOR:67:DP-3]
>[13408.143839] [drm:drm_helper_hpd_irq_event [drm_kms_helper]] [CONNECTOR:67:DP-3] status updated from disconnected to disconnected
>[13408.143871] [drm:intel_hdmi_detect [i915]] [CONNECTOR:70:HDMI-A-2]
>[13408.146320] PM: suspend exit
>[13408.154272] [IGT] gem_exec_suspend: exiting, ret=99
>[13408.164676] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0050 w(1)
>[13408.164754] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK on first message, retry
>[13408.176825] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000e972e416
>[13408.176856] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000d83083fb state to 00000000e972e416
>[13408.176880] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:37:pipe A] 000000009c55f210 state to 00000000e972e416
>[13408.176900] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 2A] 00000000ff49a3f2 state to 00000000e972e416
>[13408.176917] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 00000000ff49a3f2 to [NOCRTC]
>[13408.176936] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for plane state 00000000ff49a3f2
>[13408.176954] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:34:cursor A] 000000005ef6bffe state to 00000000e972e416
>[13408.176971] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 000000005ef6bffe to [NOCRTC]
>[13408.176987] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for plane state 000000005ef6bffe
>[13408.177005] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:38:plane 1B] 0000000002fd31f0 state to 00000000e972e416
>[13408.177022] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:47:pipe B] 00000000341fcb19 state to 00000000e972e416
>[13408.177039] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:41:plane 2B] 00000000f47f78a4 state to 00000000e972e416
>[13408.177055] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 00000000f47f78a4 to [NOCRTC]
>[13408.177071] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for plane state 00000000f47f78a4
>[13408.177088] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:44:cursor B] 00000000143cb18f state to 00000000e972e416
>[13408.177104] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 00000000143cb18f to [NOCRTC]
>[13408.177120] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for plane state 00000000143cb18f
>[13408.177144] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [MODE:1920x1080] for CRTC state 000000009c55f210
>[13408.177160] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 00000000d83083fb to [CRTC:37:pipe A]
>[13408.177178] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:115] for plane state 00000000d83083fb
>[13408.177198] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000e972e416
>[13408.185549] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0050 w(1)
>[13408.185651] [drm:drm_do_probe_ddc_edid [drm]] drm: skipping non-existent adapter i915 gmbus dpd
>[13408.206603] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0040 w(1)
>[13408.206669] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK on first message, retry
>[13408.227475] [drm:gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] NAK for addr: 0040 w(1)
>[13408.227543] [drm:drm_dp_dual_mode_detect [drm_kms_helper]] DP dual mode HDMI ID:  (err -6)
>[13408.227563] [drm:drm_helper_hpd_irq_event [drm_kms_helper]] [CONNECTOR:70:HDMI-A-2] status updated from disconnected to disconnected
>[13408.227630] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000143cb18f state to 00000000e972e416
>[13408.227659] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:37:pipe A] 00000000341fcb19 state to 00000000e972e416
>[13408.227681] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 2A] 00000000f47f78a4 state to 00000000e972e416
>[13408.227700] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 00000000f47f78a4 to [NOCRTC]
>[13408.227720] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for plane state 00000000f47f78a4
>[13408.227738] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:34:cursor A] 0000000002fd31f0 state to 00000000e972e416
>[13408.227755] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 0000000002fd31f0 to [NOCRTC]
>[13408.227773] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for plane state 0000000002fd31f0
>[13408.227791] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:38:plane 1B] 000000005ef6bffe state to 00000000e972e416
>[13408.227809] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:47:pipe B] 000000009c55f210 state to 00000000e972e416
>[13408.227826] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:41:plane 2B] 00000000ff49a3f2 state to 00000000e972e416
>[13408.227842] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 00000000ff49a3f2 to [NOCRTC]
>[13408.227858] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for plane state 00000000ff49a3f2
>[13408.227875] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:44:cursor B] 00000000d83083fb state to 00000000e972e416
>[13408.227891] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 00000000d83083fb to [NOCRTC]
>[13408.227908] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for plane state 00000000d83083fb
>[13408.227931] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [MODE:1920x1080] for CRTC state 00000000341fcb19
>[13408.227948] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 00000000143cb18f to [CRTC:37:pipe A]
>[13408.227965] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:115] for plane state 00000000143cb18f
>[13408.227983] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:37:pipe A] to 00000000e972e416
>[13408.228002] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:56:DP-1] 0000000077ec9a3c state to 00000000e972e416
>[13408.228020] [drm:drm_atomic_set_crtc_for_connector [drm]] Link connector state 0000000077ec9a3c to [NOCRTC]
>[13408.228036] [drm:drm_atomic_set_crtc_for_connector [drm]] Link connector state 0000000077ec9a3c to [CRTC:37:pipe A]
>[13408.228056] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [MODE:1920x1200] for CRTC state 000000009c55f210
>[13408.228072] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 000000005ef6bffe to [CRTC:47:pipe B]
>[13408.228089] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:115] for plane state 000000005ef6bffe
>[13408.228106] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:47:pipe B] to 00000000e972e416
>[13408.228123] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:61:DP-2] 00000000e5b18dee state to 00000000e972e416
>[13408.228140] [drm:drm_atomic_set_crtc_for_connector [drm]] Link connector state 00000000e5b18dee to [NOCRTC]
>[13408.228157] [drm:drm_atomic_set_crtc_for_connector [drm]] Link connector state 00000000e5b18dee to [CRTC:47:pipe B]
>[13408.228174] [drm:drm_atomic_check_only [drm]] checking 00000000e972e416
>[13408.228194] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:56:DP-1]
>[13408.228207] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:56:DP-1] keeps [ENCODER:55:DDI B], now on [CRTC:37:pipe A]
>[13408.228217] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:61:DP-2]
>[13408.228227] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:61:DP-2] keeps [ENCODER:60:DDI C], now on [CRTC:47:pipe B]
>[13408.228307] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:37:pipe A] has [PLANE:28:plane 1A] with fb 115
>[13408.228376] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>[13408.228439] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:47:pipe B] has [PLANE:38:plane 1B] with fb 115
>[13408.228498] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:38:plane 1B] visible 1 -> 1, off 0, on 0, ms 0
>[13408.228534] [drm:drm_atomic_commit [drm]] committing 00000000e972e416
>[13408.243243] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000e972e416
>[13408.243276] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000e972e416
>[13408.262682] [IGT] gem_shrink: executing
>[13408.349064] [IGT] gem_shrink: starting subtest mmap-cpu-oom
>[13408.400715] atkbd serio0: Failed to enable keyboard on isa0060/serio0
>[13409.971204] asix 1-6:1.0 enx00106031c272: link up, 100Mbps, full-duplex, lpa 0xC5E1
>[13411.324702] [drm:edp_panel_vdd_off_sync [i915]] Turning eDP port A VDD off
>[13411.324785] [drm:edp_panel_vdd_off_sync [i915]] PP_STATUS: 0x00000000 PP_CONTROL: 0x00000060
>[13411.331940] [drm:gen8_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010
>[13411.331954] [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>[13411.331967] [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0
>[13411.331992] [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>[13453.781211] gem_shrink invoked oom-killer: gfp_mask=0x14200ca(GFP_HIGHUSER_MOVABLE), nodemask=(null), order=0, oom_score_adj=1000
>[13453.781212] gem_shrink cpuset=/ mems_allowed=0
>[13453.781216] CPU: 2 PID: 5216 Comm: gem_shrink Tainted: G     U  W    L   4.15.0-rc5-drm-tip-ww52-commit-42a41a5+ #1
>[13453.781216] Hardware name: Intel Corporation CoffeeLake Client Platform/CoffeeLake S UDIMM RVP, BIOS CNLSFWR1.R00.X095.A04.1707240838 07/24/2017
>[13453.781217] Call Trace:
>[13453.781222]  dump_stack+0x5c/0x85
>[13453.781225]  dump_header+0x6b/0x27c
>[13453.781227]  oom_kill_process+0x239/0x440
>[13453.781228]  ? oom_badness+0xeb/0x160
>[13453.781229]  out_of_memory+0x10f/0x480
>[13453.781231]  __alloc_pages_slowpath+0xcd6/0xdb0
>[13453.781233]  ? __switch_to+0x12f/0x460
>[13453.781235]  __alloc_pages_nodemask+0x263/0x280
>[13453.781236]  filemap_fault+0x2e2/0x600
>[13453.781238]  ? filemap_map_pages+0x188/0x370
>[13453.781240]  ext4_filemap_fault+0x2c/0x3b
>[13453.781242]  __do_fault+0x19/0xc0
>[13453.781244]  __handle_mm_fault+0xbe2/0x1120
>[13453.781246]  handle_mm_fault+0xc4/0x1b0
>[13453.781247]  __do_page_fault+0x268/0x500
>[13453.781249]  ? exit_to_usermode_loop+0x61/0xc0
>[13453.781251]  ? page_fault+0x36/0x60
>[13453.781253]  page_fault+0x4c/0x60
>[13453.781254] RIP: 0033:0x7f7f77a72cf0
>[13453.781255] RSP: 002b:00007ffe77c13168 EFLAGS: 00010246
>[13453.781256] RAX: ffffffffffffffff RBX: 00000000ffffffff RCX: ffffffffffffff78
>[13453.781256] RDX: 00007ffe77c131a0 RSI: 00000000400c645f RDI: 0000000000000004
>[13453.781257] RBP: 00007ffe77c131a0 R08: ffffffffffffffff R09: 0000000000000000
>[13453.781258] R10: 0000000000000022 R11: 0000000000000246 R12: 00000000400c645f
>[13453.781258] R13: 0000000000000004 R14: 0000000000000004 R15: 0000000000000000
>[13453.781259] Mem-Info:
>[13453.781262] active_anon:3661971 inactive_anon:305065 isolated_anon:1674
>                active_file:81 inactive_file:104 isolated_file:0
>                unevictable:0 dirty:1 writeback:0 unstable:0
>                slab_reclaimable:8465 slab_unreclaimable:18107
>                mapped:440507 shmem:440409 pagetables:24987 bounce:0
>                free:34576 free_pcp:1 free_cma:0
>[13453.781264] Node 0 active_anon:14647884kB inactive_anon:1220260kB active_file:324kB inactive_file:416kB unevictable:0kB isolated(anon):6696kB isolated(file):0kB mapped:1762028kB dirty:4kB writeback:0kB shmem:1761636kB shmem_thp: 0kB shmem_pmdmapped: 0kB anon_thp: 7505920kB writeback_tmp:0kB unstable:0kB all_unreclaimable? no
>[13453.781265] Node 0 DMA free:15884kB min:64kB low:80kB high:96kB active_anon:0kB inactive_anon:0kB active_file:0kB inactive_file:0kB unevictable:0kB writepending:0kB present:15992kB managed:15884kB mlocked:0kB kernel_stack:0kB pagetables:0kB bounce:0kB free_pcp:0kB local_pcp:0kB free_cma:0kB
>[13453.781267] lowmem_reserve[]: 0 2123 15891 15891 15891
>[13453.781269] Node 0 DMA32 free:64080kB min:9020kB low:11272kB high:13524kB active_anon:2127180kB inactive_anon:12624kB active_file:380kB inactive_file:76kB unevictable:0kB writepending:0kB present:2280216kB managed:2214464kB mlocked:0kB kernel_stack:64kB pagetables:4192kB bounce:0kB free_pcp:0kB local_pcp:0kB free_cma:0kB
>[13453.781271] lowmem_reserve[]: 0 0 13767 13767 13767
>[13453.781273] Node 0 Normal free:58340kB min:58496kB low:73120kB high:87744kB active_anon:12519980kB inactive_anon:1206812kB active_file:1056kB inactive_file:548kB unevictable:0kB writepending:0kB present:14385152kB managed:14101416kB mlocked:0kB kernel_stack:10784kB pagetables:95756kB bounce:0kB free_pcp:0kB local_pcp:0kB free_cma:0kB
>[13453.781275] lowmem_reserve[]: 0 0 0 0 0
>[13453.781277] Node 0 DMA: 1*4kB (U) 1*8kB (U) 2*16kB (U) 1*32kB (U) 1*64kB (U) 1*128kB (U) 1*256kB (U) 0*512kB 1*1024kB (U) 1*2048kB (M) 3*4096kB (M) = 15884kB
>[13453.781283] Node 0 DMA32: 33*4kB (UME) 85*8kB (UME) 95*16kB (UME) 67*32kB (UME) 31*64kB (UME) 8*128kB (UE) 2*256kB (U) 0*512kB 55*1024kB (M) 0*2048kB 0*4096kB = 64316kB
>[13453.781289] Node 0 Normal: 74*4kB (UME) 8*8kB (UM) 12*16kB (UMH) 5*32kB (UM) 5*64kB (UM) 0*128kB 3*256kB (UM) 20*512kB (ME) 46*1024kB (M) 0*2048kB 0*4096kB = 59144kB
>[13453.781296] Node 0 hugepages_total=0 hugepages_free=0 hugepages_surp=0 hugepages_size=1048576kB
>[13453.781297] Node 0 hugepages_total=0 hugepages_free=0 hugepages_surp=0 hugepages_size=2048kB
>[13453.781297] 442021 total pagecache pages
>[13453.781299] 1111 pages in swap cache
>[13453.781300] Swap cache stats: add 9040862, delete 9040029, find 86540/121082
>[13453.781300] Free swap  = 0kB
>[13453.781301] Total swap = 16642044kB
>[13453.781301] 4170340 pages RAM
>[13453.781301] 0 pages HighMem/MovableOnly
>[13453.781302] 87399 pages reserved
>[13453.781302] 0 pages cma reserved
>[13453.781302] 0 pages hwpoisoned
>[13453.781303] [ pid ]   uid  tgid total_vm      rss pgtables_bytes swapents oom_score_adj name
>[13453.781308] [  310]     0   310    21354        0   184320      821             0 systemd-journal
>[13453.781309] [  334]     0   334    11563        1   110592      505         -1000 systemd-udevd
>[13453.781310] [  818]   100   818    31893        0   151552      162             0 systemd-timesyn
>[13453.781311] [ 1011]     0  1011     7523        0   102400       68             0 cgmanager
>[13453.781312] [ 1012]     0  1012   105135        0   319488      495             0 ModemManager
>[13453.781313] [ 1014]   104  1014    64102        0   135168      439             0 rsyslogd
>[13453.781314] [ 1019]     0  1019     7776        1   110592       74             0 cron
>[13453.781315] [ 1021]   114  1021    94398        0   364544      453             0 whoopsie
>[13453.781317] [ 1023]     0  1023     8030        0   110592      103             0 bluetoothd
>[13453.781318] [ 1031]   120  1031    11285        0   135168      110             0 avahi-daemon
>[13453.781319] [ 1034]   106  1034    10923        1   131072      228          -900 dbus-daemon
>[13453.781319] [ 1048]   120  1048    11253        0   126976       87             0 avahi-daemon
>[13453.781320] [ 1066]     0  1066   117005        0   356352      676             0 NetworkManager
>[13453.781321] [ 1067]     0  1067    43334       32   188416      170             0 thermald
>[13453.781322] [ 1071]     0  1071     1097        0    53248       68             0 acpid
>[13453.781323] [ 1073]     0  1073    11109        0   131072      155             0 systemd-logind
>[13453.781324] [ 1076]     0  1076   208609        0   270336     3392             0 snapd
>[13453.781325] [ 1109]     0  1109    71028        0   196608      218             0 polkitd
>[13453.781326] [ 1120]     0  1120     4884       22    81920       50             0 irqbalance
>[13453.781327] [ 1170]   102  1170    11889       21   126976      110             0 systemd-resolve
>[13453.781328] [ 1181]     0  1181    19059        0   196608      138             0 login
>[13453.781329] [ 1193]  1000  1193    28137       81   258048    13781             0 python
>[13453.781330] [ 1224]     0  1224     1124        0    53248       23             0 sshguard-journa
>[13453.781331] [ 1226]     0  1226    42435        1   258048      105             0 journalctl
>[13453.781332] [ 1227]     0  1227     3901        0    61440      125             0 sshguard
>[13453.781333] [ 1228]     0  1228    16956        1   172032      186         -1000 sshd
>[13453.781334] [ 1309]  1000  1309    15719        1   155648      282             0 systemd
>[13453.781335] [ 1311]  1000  1311    22338        0   204800      578             0 (sd-pam)
>[13453.781336] [ 1319]  1000  1319    10750        0   131072      127             0 dbus-daemon
>[13453.781337] [ 1369]  1000  1369    46920        0   143360      193             0 dconf-service
>[13453.781338] [ 1413]  1000  1413    70873        0   188416      704             0 gvfsd
>[13453.781339] [ 1418]  1000  1418    87552        0   167936      709             0 gvfsd-fuse
>[13453.781340] [ 1441]  1000  1441     5633        0    86016      460             0 bash
>[13453.781342] [ 1723]     0  1723    13605        1   147456      259             0 systemd
>[13453.781343] [ 1724]     0  1724    59204        0   221184      589             0 (sd-pam)
>[13453.781344] [ 1731]     0  1731    10750        0   131072      131             0 dbus-daemon
>[13453.781345] [ 1759]     0  1759    46856        0   131072      132             0 dconf-service
>[13453.781345] [ 1762]     0  1762    70873        0   184320      195             0 gvfsd
>[13453.781346] [ 1767]     0  1767    87552        0   172032      709             0 gvfsd-fuse
>[13453.781348] [ 3811]  1000  3811     7374        0    98304      158             0 tmux
>[13453.781349] [ 3812]  1000  3812     5651        1    94208      480             0 bash
>[13453.781350] [ 3827]     0  3827     7350       39   102400       83             0 tmux
>[13453.781351] [ 3828]     0  3828     5644        1    90112      471             0 bash
>[13453.781352] [ 4634]     0  4634    26497        1   249856      251             0 sshd
>[13453.781353] [ 4698]  1000  4698    26497        1   245760      262             0 sshd
>[13453.781354] [ 4699]  1000  4699     3219        1    73728       49             0 sftp-server
>[13453.781356] [ 4716]     0  4716    26497        1   245760      251             0 sshd
>[13453.781356] [ 4780]  1000  4780    26497        0   237568      260             0 sshd
>[13453.781357] [ 4781]  1000  4781     5631        1    81920      455             0 bash
>[13453.781358] [ 4793]  1000  4793     5197        1    77824       82             0 tmux
>[13453.781359] [ 4794]     0  4794    26497        1   249856      251             0 sshd
>[13453.781360] [ 4836]  1000  4836    26497        1   241664      275             0 sshd
>[13453.781361] [ 4837]  1000  4837     3219        1    73728       73             0 sftp-server
>[13453.781362] [ 4848]     0  4848    26497        1   245760      252             0 sshd
>[13453.781363] [ 4890]  1000  4890    26497        0   237568      257             0 sshd
>[13453.781364] [ 4891]  1000  4891     5631        1    90112      455             0 bash
>[13453.781365] [ 4903]     0  4903    15776        1   172032      127             0 sudo
>[13453.781366] [ 4904]     0  4904    15673        1   167936      117             0 su
>[13453.781367] [ 4905]     0  4905     5297        1    81920      124             0 bash
>[13453.781368] [ 4919]     0  4919     5197        1    86016       82             0 tmux
>[13453.781369] [ 4920]     0  4920     3450        0    77824       36             0 dmesg
>[13453.781370] [ 4921]  1000  4921     5652        1    81920      482             0 bash
>[13453.781373] [ 5057]     0  5057    15776        0   176128      127             0 sudo
>[13453.781374] [ 5058]     0  5058    11250       14   126976       81          1000 gem_shrink
>[13453.781375] [ 5059]     0  5059   109554    25590   741376    50869          1000 gem_shrink
>[13453.781376] [ 5060]     0  5060   142322    61323  1110016    61328          1000 gem_shrink
>[13453.781377] [ 5061]     0  5061   109554    31138   864256    60651          1000 gem_shrink
>[13453.781378] [ 5062]     0  5062   109554    14564   712704    58433          1000 gem_shrink
>[13453.781379] [ 5063]     0  5063   109554    13802   696320    57253          1000 gem_shrink
>[13453.781380] [ 5064]     0  5064   109554    21018   720896    53031          1000 gem_shrink
>[13453.781381] [ 5065]     0  5065   109554    39877   880640    54241          1000 gem_shrink
>[13453.781382] [ 5066]     0  5066    76786     6786   577536    49479          1000 gem_shrink
>[13453.781383] [ 5067]     0  5067   109554    16499   663552    50432          1000 gem_shrink
>[13453.781384] [ 5068]     0  5068   109554    17610   720896    56409          1000 gem_shrink
>[13453.781385] [ 5069]     0  5069    76786    14674   630784    47960          1000 gem_shrink
>[13453.781386] [ 5070]     0  5070   109554    14364   659456    52052          1000 gem_shrink
>[13453.781387] [ 5071]     0  5071    76786    15107   643072    49291          1000 gem_shrink
>[13453.781387] [ 5072]     0  5072    76786     8916   557056    44631          1000 gem_shrink
>[13453.781389] [ 5073]     0  5073    76786    12553   561152    41455          1000 gem_shrink
>[13453.781390] [ 5074]     0  5074    76786     6662   507904    40532          1000 gem_shrink
>[13453.781391] [ 5075]     0  5075    76786    19088   643072    45006          1000 gem_shrink
>[13453.781392] [ 5076]     0  5076    76786    14082   573440    41557          1000 gem_shrink
>[13453.781393] [ 5077]     0  5077    76786    19910   651264    45572          1000 gem_shrink
>[13453.781393] [ 5078]     0  5078   109554    25303   671744    42837          1000 gem_shrink
>[13453.781394] [ 5079]     0  5079    76786    15672   651264    49906          1000 gem_shrink
>[13453.781396] [ 5080]     0  5080   109554    22929   684032    46398          1000 gem_shrink
>[13453.781396] [ 5081]     0  5081   109554    20054   671744    47834          1000 gem_shrink
>[13453.781397] [ 5082]     0  5082   109554    22201   655360    43636          1000 gem_shrink
>[13453.781398] [ 5083]     0  5083   109554    29629   745472    47477          1000 gem_shrink
>[13453.781399] [ 5084]     0  5084    77243    19224   651264    46423          1000 gem_shrink
>[13453.781400] [ 5085]     0  5085   109554    24726   704512    47315          1000 gem_shrink
>[13453.781401] [ 5086]     0  5086    76786    18534   618496    42645          1000 gem_shrink
>[13453.781402] [ 5087]     0  5087   142322    56136  1024000    55837          1000 gem_shrink
>[13453.781403] [ 5088]     0  5088    76786    19065   618496    42265          1000 gem_shrink
>[13453.781404] [ 5089]     0  5089    76786     6792   528384    43130          1000 gem_shrink
>[13453.781405] [ 5090]     0  5090    76786     6301   569344    48912          1000 gem_shrink
>[13453.781406] [ 5091]     0  5091    76786     9207   589824    48593          1000 gem_shrink
>[13453.781407] [ 5092]     0  5092   109554    42034   761856    36996          1000 gem_shrink
>[13453.781408] [ 5093]     0  5093    76786     2073   487424    42949          1000 gem_shrink
>[13453.781409] [ 5094]     0  5094   109554    26202   729088    48658          1000 gem_shrink
>[13453.781410] [ 5095]     0  5095   109554    43417   892928    52370          1000 gem_shrink
>[13453.781411] [ 5096]     0  5096   109554    50086   909312    47339          1000 gem_shrink
>[13453.781412] [ 5097]     0  5097    76786    11136   557056    42295          1000 gem_shrink
>[13453.781413] [ 5098]     0  5098    76786    16485   634880    46908          1000 gem_shrink
>[13453.781414] [ 5099]     0  5099    76786      280   475136    43042          1000 gem_shrink
>[13453.781414] [ 5100]     0  5100    76786    21016   606208    38813          1000 gem_shrink
>[13453.781415] [ 5101]     0  5101   142322    53041   933888    47421          1000 gem_shrink
>[13453.781416] [ 5102]     0  5102   109554    25358   716800    47920          1000 gem_shrink
>[13453.781417] [ 5103]     0  5103   109554    29655   692224    40864          1000 gem_shrink
>[13453.781418] [ 5104]     0  5104    76786    30674   651264    34542          1000 gem_shrink
>[13453.781419] [ 5105]     0  5105   109554    19425   688128    50291          1000 gem_shrink
>[13453.781420] [ 5106]     0  5106    76788    23579   651264    42065          1000 gem_shrink
>[13453.781421] [ 5107]     0  5107    76786    15633   544768    36427          1000 gem_shrink
>[13453.781422] [ 5108]     0  5108    76786    11241   520192    37868          1000 gem_shrink
>[13453.781423] [ 5109]     0  5109    76786     9624   507904    37730          1000 gem_shrink
>[13453.781424] [ 5110]     0  5110   109554    14868   655360    51205          1000 gem_shrink
>[13453.781425] [ 5111]     0  5111   109554    21481   667648    45682          1000 gem_shrink
>[13453.781425] [ 5112]     0  5112    76786    24605   602112    34579          1000 gem_shrink
>[13453.781426] [ 5113]     0  5113    76786    21664   606208    37927          1000 gem_shrink
>[13453.781427] [ 5114]     0  5114    76786    16651   540672    35089          1000 gem_shrink
>[13453.781428] [ 5115]     0  5115    76786     7184   466944    34935          1000 gem_shrink
>[13453.781429] [ 5116]     0  5116    76786    16430   532480    34282          1000 gem_shrink
>[13453.781430] [ 5117]     0  5117    76786     1135   393216    31890          1000 gem_shrink
>[13453.781431] [ 5118]     0  5118    76786    30486   651264    34652          1000 gem_shrink
>[13453.781431] [ 5119]     0  5119    76786    20490   573440    35165          1000 gem_shrink
>[13453.781432] [ 5120]     0  5120    76786    18906   573440    36751          1000 gem_shrink
>[13453.781433] [ 5121]     0  5121    76786    27384   643072    37129          1000 gem_shrink
>[13453.781434] [ 5122]     0  5122    76786     4442   434176    33955          1000 gem_shrink
>[13453.781435] [ 5123]     0  5123    76786    12574   487424    32136          1000 gem_shrink
>[13453.781436] [ 5124]     0  5124    76786    27212   598016    31259          1000 gem_shrink
>[13453.781437] [ 5125]     0  5125    76786     3774   409600    31325          1000 gem_shrink
>[13453.781438] [ 5126]     0  5126    76786     5647   401408    28619          1000 gem_shrink
>[13453.781439] [ 5127]     0  5127    76786    10207   430080    27361          1000 gem_shrink
>[13453.781440] [ 5128]     0  5128    76786    14920   487424    30022          1000 gem_shrink
>[13453.781440] [ 5129]     0  5129   109554    32239   667648    35188          1000 gem_shrink
>[13453.781441] [ 5130]     0  5130    76786    17026   483328    27353          1000 gem_shrink
>[13453.781442] [ 5131]     0  5131   109554    39660   700416    31561          1000 gem_shrink
>[13453.781443] [ 5132]     0  5132    76786    28696   614400    31848          1000 gem_shrink
>[13453.781444] [ 5133]     0  5133    76786    23336   561152    30714          1000 gem_shrink
>[13453.781445] [ 5134]     0  5134    76786    32012   614400    28524          1000 gem_shrink
>[13453.781446] [ 5135]     0  5135    76786    31305   610304    28990          1000 gem_shrink
>[13453.781447] [ 5136]     0  5136    76786     8785   450560    31472          1000 gem_shrink
>[13453.781448] [ 5137]     0  5137    76786    26749   651264    38832          1000 gem_shrink
>[13453.781449] [ 5138]     0  5138    76786     5486   434176    32521          1000 gem_shrink
>[13453.781450] [ 5139]     0  5139    76786    11687   425984    25685          1000 gem_shrink
>[13453.781451] [ 5140]     0  5140   109554    50340   761856    28979          1000 gem_shrink
>[13453.781452] [ 5141]     0  5141    44018    10292   372736    20930          1000 gem_shrink
>[13453.781453] [ 5142]     0  5142    44018     1900   315392    21967          1000 gem_shrink
>[13453.781453] [ 5143]     0  5143    76786    11502   401408    22486          1000 gem_shrink
>[13453.781454] [ 5144]     0  5144    76786    25985   520192    22927          1000 gem_shrink
>[13453.781455] [ 5145]     0  5145    76786    14249   430080    23718          1000 gem_shrink
>[13453.781456] [ 5146]     0  5146    76786    25480   524288    23922          1000 gem_shrink
>[13453.781457] [ 5147]     0  5147   109554    42770   659456    23315          1000 gem_shrink
>[13453.781458] [ 5148]     0  5148   109554    34091   733184    41398          1000 gem_shrink
>[13453.781459] [ 5149]     0  5149    76786    27560   507904    19736          1000 gem_shrink
>[13453.781460] [ 5150]     0  5150    44018     6820   364544    23303          1000 gem_shrink
>[13453.781461] [ 5151]     0  5151    44018     5980   315392    17962          1000 gem_shrink
>[13453.781462] [ 5152]     0  5152    76786    35082   585728    21948          1000 gem_shrink
>[13453.781463] [ 5153]     0  5153    76786    42631   626688    19597          1000 gem_shrink
>[13453.781463] [ 5154]     0  5154    76786    15970   425984    21172          1000 gem_shrink
>[13453.781464] [ 5155]     0  5155    76786    35468   561152    18699          1000 gem_shrink
>[13453.781465] [ 5156]     0  5156    44018     9262   339968    17550          1000 gem_shrink
>[13453.781466] [ 5157]     0  5157    44018     4813   303104    17513          1000 gem_shrink
>[13453.781467] [ 5158]     0  5158    44018    13804   372736    17357          1000 gem_shrink
>[13453.781468] [ 5159]     0  5159    44018     7906   335872    18388          1000 gem_shrink
>[13453.781469] [ 5160]     0  5160    76786    18629   389120    14197          1000 gem_shrink
>[13453.781470] [ 5161]     0  5161    76786    42690   630784    20013          1000 gem_shrink
>[13453.781471] [ 5162]     0  5162    44018    12780   368640    17905          1000 gem_shrink
>[13453.781471] [ 5163]     0  5163    76786    33146   536576    17619          1000 gem_shrink
>[13453.781472] [ 5164]     0  5164    76786    39053   540672    12285          1000 gem_shrink
>[13453.781473] [ 5165]     0  5165    76786    50776   647168    14316          1000 gem_shrink
>[13453.781474] [ 5166]     0  5166    76786    31604   475136    11519          1000 gem_shrink
>[13453.781475] [ 5167]     0  5167    76786    25875   487424    19056          1000 gem_shrink
>[13453.781476] [ 5168]     0  5168    44018     5273   237568     8854          1000 gem_shrink
>[13453.781477] [ 5169]     0  5169    44018     7413   270336    10708          1000 gem_shrink
>[13453.781478] [ 5170]     0  5170    76786    27302   479232    16641          1000 gem_shrink
>[13453.781479] [ 5171]     0  5171    44018    16487   327680     9056          1000 gem_shrink
>[13453.781480] [ 5172]     0  5172    76786    51506   614400     9132          1000 gem_shrink
>[13453.781481] [ 5173]     0  5173    44018     3972   241664    10638          1000 gem_shrink
>[13453.781482] [ 5174]     0  5174    44018     7108   266240    10538          1000 gem_shrink
>[13453.781483] [ 5175]     0  5175    76786    56864   647168     7697          1000 gem_shrink
>[13453.781484] [ 5176]     0  5176    76786    39896   520192     9176          1000 gem_shrink
>[13453.781485] [ 5177]     0  5177    44018     6545   249856     8878          1000 gem_shrink
>[13453.781486] [ 5178]     0  5178    44018     7005   225280     5874          1000 gem_shrink
>[13453.781487] [ 5179]     0  5179    44018    25608   364544     4468          1000 gem_shrink
>[13453.781488] [ 5180]     0  5180    76786    38065   466944     4435          1000 gem_shrink
>[13453.781489] [ 5181]     0  5181    76786    35378   462848     6653          1000 gem_shrink
>[13453.781489] [ 5182]     0  5182    44018    23673   360448     5710          1000 gem_shrink
>[13453.781490] [ 5183]     0  5183    44018    11459   262144     5986          1000 gem_shrink
>[13453.781491] [ 5184]     0  5184    76786       13   389120       82          1000 gem_shrink
>[13453.781492] [ 5185]     0  5185   109554     6337   704512       83          1000 gem_shrink
>[13453.781493] [ 5186]     0  5186   142322     7406   974848       90          1000 gem_shrink
>[13453.781494] [ 5192]     0  5192    76786     8409   458752       83          1000 gem_shrink
>[13453.781495] [ 5193]     0  5193    76786    14837   507904       82          1000 gem_shrink
>[13453.781496] [ 5194]     0  5194    76786     9449   466944       82          1000 gem_shrink
>[13453.781497] [ 5195]     0  5195    76786    22003   565248       83          1000 gem_shrink
>[13453.781498] [ 5202]     0  5202    44018       26   122880       69          1000 gem_shrink
>[13453.781499] [ 5204]     0  5204    44018     9558   200704       63          1000 gem_shrink
>[13453.781499] [ 5205]     0  5205    44018     3199   151552       59          1000 gem_shrink
>[13453.781500] [ 5206]     0  5206    44018    32804   389120       59          1000 gem_shrink
>[13453.781501] [ 5207]     0  5207    76786       36   389120       59          1000 gem_shrink
>[13453.781502] [ 5208]     0  5208    76786       35   389120       60          1000 gem_shrink
>[13453.781502] [ 5209]     0  5209    44018    21995   299008       59          1000 gem_shrink
>[13453.781503] [ 5210]     0  5210    44018    20138   286720       59          1000 gem_shrink
>[13453.781504] [ 5211]     0  5211    44018    16941   262144       60          1000 gem_shrink
>[13453.781505] [ 5212]     0  5212    44018    10913   212992       59          1000 gem_shrink
>[13453.781506] [ 5213]     0  5213    44018       36   122880       59          1000 gem_shrink
>[13453.781507] [ 5214]     0  5214    44018    32767   385024       60          1000 gem_shrink
>[13453.781508] [ 5215]     0  5215    44018    27238   344064       60          1000 gem_shrink
>[13453.781509] [ 5216]     0  5216    44018     1834   139264       60          1000 gem_shrink
>[13453.781510] [ 5217]     0  5217    44018    17440   266240       59          1000 gem_shrink
>[13453.781510] [ 5218]     0  5218    44018    32804   389120       59          1000 gem_shrink
>[13453.781511] [ 5219]     0  5219    44018    30852   372736       59          1000 gem_shrink
>[13453.781512] [ 5220]     0  5220    44018     1907   139264       60          1000 gem_shrink
>[13453.781513] [ 5221]     0  5221    76786     1270   401408       60          1000 gem_shrink
>[13453.781514] [ 5222]     0  5222    76786     9189   462848       60          1000 gem_shrink
>[13453.781515] [ 5223]     0  5223    76786    10161   471040       59          1000 gem_shrink
>[13453.781515] [ 5224]     0  5224    44018    12592   225280       59          1000 gem_shrink
>[13453.781516] [ 5225]     0  5225    44018       35   389120       60          1000 gem_shrink
>[13453.781517] [ 5226]     0  5226    44018    31400   376832       61          1000 gem_shrink
>[13453.781518] [ 5227]     0  5227    44018       33   122880       62          1000 gem_shrink
>[13453.781519] [ 5228]     0  5228    44018    18168   270336       59          1000 gem_shrink
>[13453.781519] [ 5229]     0  5229    44018    23154   311296       59          1000 gem_shrink
>[13453.781520] [ 5230]     0  5230    76786       36   389120       59          1000 gem_shrink
>[13453.781521] [ 5231]     0  5231    44018    13621   233472       60          1000 gem_shrink
>[13453.781522] [ 5232]     0  5232    44018     8881   196608       59          1000 gem_shrink
>[13453.781523] [ 5233]     0  5233    44018    10911   212992       59          1000 gem_shrink
>[13453.781524] [ 5234]     0  5234    44018    12879   229376       59          1000 gem_shrink
>[13453.781525] [ 5235]     0  5235    44018    32804   389120       59          1000 gem_shrink
>[13453.781525] [ 5236]     0  5236    44018    13560   233472       59          1000 gem_shrink
>[13453.781526] [ 5237]     0  5237    44018    32804   389120       59          1000 gem_shrink
>[13453.781527] [ 5238]     0  5238    44018    11536   217088       59          1000 gem_shrink
>[13453.781528] [ 5239]     0  5239    44018    32484   385024       60          1000 gem_shrink
>[13453.781529] [ 5240]     0  5240    44018       36   122880       59          1000 gem_shrink
>[13453.781529] [ 5241]     0  5241    44018     4158   159744       59          1000 gem_shrink
>[13453.781530] [ 5242]     0  5242    44018     8245   192512       59          1000 gem_shrink
>[13453.781531] [ 5243]     0  5243    44018       36   389120       59          1000 gem_shrink
>[13453.781532] [ 5244]     0  5244    44018    32804   389120       59          1000 gem_shrink
>[13453.781533] [ 5245]     0  5245    44018    15877   249856       60          1000 gem_shrink
>[13453.781534] [ 5246]     0  5246    44018      266   126976       59          1000 gem_shrink
>[13453.781535] [ 5247]     0  5247    44018    10637   208896       59          1000 gem_shrink
>[13453.781536] [ 5248]     0  5248    44018       36   122880       59          1000 gem_shrink
>[13453.781537] [ 5249]     0  5249    44018    30091   364544       59          1000 gem_shrink
>[13453.781538] [ 5250]     0  5250    44018       35   389120       60          1000 gem_shrink
>[13453.781538] [ 5251]     0  5251    44018    12067   221184       60          1000 gem_shrink
>[13453.781539] [ 5252]     0  5252    44018    32804   389120       59          1000 gem_shrink
>[13453.781540] [ 5253]     0  5253    44018    22839   307200       59          1000 gem_shrink
>[13453.781541] [ 5254]     0  5254    44018       36   122880       59          1000 gem_shrink
>[13453.781542] [ 5255]     0  5255    44018    26846   339968       60          1000 gem_shrink
>[13453.781543] [ 5256]     0  5256    44018    18022   270336       59          1000 gem_shrink
>[13453.781543] [ 5257]     0  5257    44018       36   122880       59          1000 gem_shrink
>[13453.781544] [ 5258]     0  5258    44018     7538   184320       59          1000 gem_shrink
>[13453.781545] [ 5259]     0  5259    44018     3286   151552       73          1000 gem_shrink
>[13453.781546] [ 5260]     0  5260    44018    11204   212992       73          1000 gem_shrink
>[13453.781547] [ 5261]     0  5261    44018     7969   188416       73          1000 gem_shrink
>[13453.781548] [ 5262]     0  5262    44018    25196   327680       73          1000 gem_shrink
>[13453.781549] [ 5263]     0  5263    44018     1899   139264       73          1000 gem_shrink
>[13453.781550] [ 5264]     0  5264    44018     2164   143360       73          1000 gem_shrink
>[13453.781551] [ 5265]     0  5265    44018     4605   163840       73          1000 gem_shrink
>[13453.781552] [ 5266]     0  5266    44018     6717   180224       73          1000 gem_shrink
>[13453.781553] [ 5267]     0  5267    44018     2097   143360       73          1000 gem_shrink
>[13453.781553] [ 5268]     0  5268    44018    14239   237568       73          1000 gem_shrink
>[13453.781554] [ 5269]     0  5269    44018    16219   253952       73          1000 gem_shrink
>[13453.781555] [ 5270]     0  5270    44018     2691   147456       73          1000 gem_shrink
>[13453.781556] [ 5271]     0  5271    44018    17142   262144       73          1000 gem_shrink
>[13453.781557] [ 5272]     0  5272    44018     2823   147456       73          1000 gem_shrink
>[13453.781558] [ 5273]     0  5273    44018    14109   237568       73          1000 gem_shrink
>[13453.781559] [ 5274]     0  5274    44018     3417   151552       73          1000 gem_shrink
>[13453.781560] [ 5275]     0  5275    44018     1021   135168       73          1000 gem_shrink
>[13453.781561] [ 5276]     0  5276    44018     5131   167936       73          1000 gem_shrink
>[13453.781562] [ 5277]     0  5277    44018     9686   204800       73          1000 gem_shrink
>[13453.781563] [ 5278]     0  5278    44018     6123   172032       73          1000 gem_shrink
>[13453.781564] [ 5279]     0  5279    44018     3087   151552       73          1000 gem_shrink
>[13453.781565] [ 5280]     0  5280    44018     8762   196608       73          1000 gem_shrink
>[13453.781567] [ 5281]     0  5281    44018     8959   196608       73          1000 gem_shrink
>[13453.781568] [ 5282]     0  5282    44018     1569   139264       73          1000 gem_shrink
>[13453.781569] [ 5283]     0  5283    44018     6055   172032       73          1000 gem_shrink
>[13453.781570] [ 5284]     0  5284    44018     2295   143360       73          1000 gem_shrink
>[13453.781571] [ 5285]     0  5285    11250       15   122880       80          1000 gem_shrink
>[13453.781572] [ 5286]     0  5286    44018     2882   147456       73          1000 gem_shrink
>[13453.781573] [ 5287]     0  5287    11250       16   122880       79          1000 gem_shrink
>[13453.781574] [ 5288]     0  5288    44018       77   126976       72          1000 gem_shrink
>[13453.781575] [ 5289]     0  5289    44018     1077   135168       72          1000 gem_shrink
>[13453.781576] [ 5290]     0  5290    11250       14   114688       81          1000 gem_shrink
>[13453.781577] [ 5291]     0  5291    44018    15494   249856       72          1000 gem_shrink
>[13453.781578] [ 5292]     0  5292    44018    10742   212992       72          1000 gem_shrink
>[13453.781579] [ 5293]     0  5293    11250       14   114688       81          1000 gem_shrink
>[13453.781579] [ 5294]     0  5294    44018     4538   159744       72          1000 gem_shrink
>[13453.781580] [ 5295]     0  5295    44018     6716   180224       72          1000 gem_shrink
>[13453.781581] [ 5296]     0  5296    44018     1239   135168       72          1000 gem_shrink
>[13453.781582] [ 5297]     0  5297    44018     5788   172032       72          1000 gem_shrink
>[13453.781583] [ 5298]     0  5298    44018    17804   266240       72          1000 gem_shrink
>[13453.781584] [ 5299]     0  5299    44018    10147   204800       72          1000 gem_shrink
>[13453.781585] [ 5300]     0  5300    44018     8498   192512       72          1000 gem_shrink
>[13453.781587] [ 5301]     0  5301    44018     9224   200704       72          1000 gem_shrink
>[13453.781588] [ 5302]     0  5302    44018    25922   331776       72          1000 gem_shrink
>[13453.781589] [ 5303]     0  5303    44018    12062   221184       72          1000 gem_shrink
>[13453.781589] [ 5304]     0  5304    44018      243   126976       72          1000 gem_shrink
>[13453.781591] [ 5305]     0  5305    44018    12524   225280       72          1000 gem_shrink
>[13453.781592] [ 5306]     0  5306    44018     4138   159744       72          1000 gem_shrink
>[13453.781593] [ 5307]     0  5307    44018     4011   155648       72          1000 gem_shrink
>[13453.781594] [ 5308]     0  5308    44018     9951   204800       72          1000 gem_shrink
>[13453.781595] [ 5309]     0  5309    44018      550   131072       72          1000 gem_shrink
>[13453.781595] [ 5310]     0  5310    44018     2680   147456       72          1000 gem_shrink
>[13453.781596] [ 5311]     0  5311    44018     6585   176128       72          1000 gem_shrink
>[13453.781598] [ 5312]     0  5312    44018     2889   147456       72          1000 gem_shrink
>[13453.781599] [ 5313]     0  5313    44018     2559   147456       72          1000 gem_shrink
>[13453.781600] [ 5314]     0  5314    44018     1041   135168       72          1000 gem_shrink
>[13453.781600] [ 5315]     0  5315    44018     2135   143360       72          1000 gem_shrink
>[13453.781602] [ 5316]     0  5316    44018     7970   188416       72          1000 gem_shrink
>[13453.781603] [ 5317]     0  5317    44018    17211   262144       72          1000 gem_shrink
>[13453.781603] [ 5318]     0  5318    44018     8300   192512       72          1000 gem_shrink
>[13453.781604] [ 5319]     0  5319    44018    14240   237568       72          1000 gem_shrink
>[13453.781605] [ 5320]     0  5320    44018     5922   172032       72          1000 gem_shrink
>[13453.781606] [ 5321]     0  5321    44018    16155   253952       72          1000 gem_shrink
>[13453.781612] Out of memory: Kill process 5060 (gem_shrink) score 1014 or sacrifice child
>[13453.781618] Killed process 5060 (gem_shrink) total-vm:569288kB, anon-rss:245280kB, file-rss:12kB, shmem-rss:0kB
>[13453.798824] oom_reaper: reaped process 5060 (gem_shrink), now anon-rss:0kB, file-rss:0kB, shmem-rss:0kB
>[13454.777436] gem_shrink invoked oom-killer: gfp_mask=0x14200d2(GFP_HIGHUSER|__GFP_RECLAIMABLE), nodemask=(null), order=0, oom_score_adj=1000
>[13454.777437] gem_shrink cpuset=/ mems_allowed=0
>[13454.777440] CPU: 11 PID: 5272 Comm: gem_shrink Tainted: G     U  W    L   4.15.0-rc5-drm-tip-ww52-commit-42a41a5+ #1
>[13454.777441] Hardware name: Intel Corporation CoffeeLake Client Platform/CoffeeLake S UDIMM RVP, BIOS CNLSFWR1.R00.X095.A04.1707240838 07/24/2017
>[13454.777442] Call Trace:
>[13454.777447]  dump_stack+0x5c/0x85
>[13454.777450]  dump_header+0x6b/0x27c
>[13454.777451]  oom_kill_process+0x239/0x440
>[13454.777453]  ? oom_badness+0xeb/0x160
>[13454.777454]  out_of_memory+0x10f/0x480
>[13454.777456]  __alloc_pages_slowpath+0xcd6/0xdb0
>[13454.777458]  __alloc_pages_nodemask+0x263/0x280
>[13454.777460]  alloc_pages_vma+0x7c/0x1e0
>[13454.777461]  shmem_alloc_page+0x78/0xc0
>[13454.777463]  ? __radix_tree_create+0x168/0x1f0
>[13454.777464]  ? __radix_tree_insert+0x45/0x240
>[13454.777465]  shmem_alloc_and_acct_page+0x7a/0x1d0
>[13454.777466]  shmem_getpage_gfp+0x194/0xcb0
>[13454.777468]  shmem_fault+0x9c/0x1f0
>[13454.777470]  ? current_time+0x32/0x70
>[13454.777471]  ? file_update_time+0x60/0x110
>[13454.777473]  __do_fault+0x19/0xc0
>[13454.777475]  __handle_mm_fault+0x9e4/0x1120
>[13454.777477]  handle_mm_fault+0xc4/0x1b0
>[13454.777479]  __do_page_fault+0x268/0x500
>[13454.777481]  ? exit_to_usermode_loop+0x61/0xc0
>[13454.777483]  ? page_fault+0x36/0x60
>[13454.777484]  page_fault+0x4c/0x60
>[13454.777486] RIP: 0033:0x404335
>[13454.777486] RSP: 002b:00007ffe77c131c0 EFLAGS: 00010212
>[13454.777487] RAX: 00007f7f6d405000 RBX: 0000000000000004 RCX: 00000000002c9800
>[13454.777488] RDX: 0000000000000b27 RSI: 0000000000008000 RDI: 0000000000000004
>[13454.777489] RBP: 0000000000000001 R08: 0000000000000002 R09: 00007f7f767c4600
>[13454.777489] R10: 0000000000000073 R11: 0000000000000246 R12: 0000000008000000
>[13454.777489] R13: 00000000004042f0 R14: 0000000000000004 R15: 000000000000003f
>[13454.777490] Mem-Info:
>[13454.777493] active_anon:3746675 inactive_anon:213427 isolated_anon:8842
>                active_file:103 inactive_file:61 isolated_file:0
>                unevictable:0 dirty:1 writeback:0 unstable:0
>                slab_reclaimable:8434 slab_unreclaimable:18125
>                mapped:454322 shmem:454564 pagetables:25381 bounce:0
>                free:34471 free_pcp:64 free_cma:0
>[13454.777495] Node 0 active_anon:14986700kB inactive_anon:853708kB active_file:412kB inactive_file:244kB unevictable:0kB isolated(anon):35368kB isolated(file):0kB mapped:1817288kB dirty:4kB writeback:0kB shmem:1818256kB shmem_thp: 0kB shmem_pmdmapped: 0kB anon_thp: 5246976kB writeback_tmp:0kB unstable:0kB all_unreclaimable? no
>[13454.777495] Node 0 DMA free:15884kB min:64kB low:80kB high:96kB active_anon:0kB inactive_anon:0kB active_file:0kB inactive_file:0kB unevictable:0kB writepending:0kB present:15992kB managed:15884kB mlocked:0kB kernel_stack:0kB pagetables:0kB bounce:0kB free_pcp:0kB local_pcp:0kB free_cma:0kB
>[13454.777497] lowmem_reserve[]: 0 2123 15891 15891 15891
>[13454.777499] Node 0 DMA32 free:63860kB min:9020kB low:11272kB high:13524kB active_anon:2107124kB inactive_anon:32948kB active_file:0kB inactive_file:12kB unevictable:0kB writepending:0kB present:2280216kB managed:2214464kB mlocked:0kB kernel_stack:64kB pagetables:4572kB bounce:0kB free_pcp:0kB local_pcp:0kB free_cma:0kB
>[13454.777501] lowmem_reserve[]: 0 0 13767 13767 13767
>[13454.777503] Node 0 Normal free:58140kB min:58496kB low:73120kB high:87744kB active_anon:12879452kB inactive_anon:820572kB active_file:420kB inactive_file:0kB unevictable:0kB writepending:0kB present:14385152kB managed:14101416kB mlocked:0kB kernel_stack:10816kB pagetables:96952kB bounce:0kB free_pcp:256kB local_pcp:240kB free_cma:0kB
>[13454.777505] lowmem_reserve[]: 0 0 0 0 0
>[13454.777507] Node 0 DMA: 1*4kB (U) 1*8kB (U) 2*16kB (U) 1*32kB (U) 1*64kB (U) 1*128kB (U) 1*256kB (U) 0*512kB 1*1024kB (U) 1*2048kB (M) 3*4096kB (M) = 15884kB
>[13454.777514] Node 0 DMA32: 2*4kB (UM) 79*8kB (UME) 89*16kB (UME) 63*32kB (UM) 31*64kB (U) 7*128kB (UE) 3*256kB (UM) 2*512kB (M) 54*1024kB (M) 0*2048kB 0*4096kB = 64048kB
>[13454.777520] Node 0 Normal: 4*4kB (UME) 39*8kB (UME) 43*16kB (UMEH) 29*32kB (UMEH) 14*64kB (UME) 4*128kB (U) 5*256kB (UME) 9*512kB (UM) 36*1024kB (M) 4*2048kB (M) 1*4096kB (M) = 58392kB
>[13454.777528] Node 0 hugepages_total=0 hugepages_free=0 hugepages_surp=0 hugepages_size=1048576kB
>[13454.777528] Node 0 hugepages_total=0 hugepages_free=0 hugepages_surp=0 hugepages_size=2048kB
>[13454.777529] 454834 total pagecache pages
>[13454.777531] 44 pages in swap cache
>[13454.777532] Swap cache stats: add 9101568, delete 9102421, find 86655/121299
>[13454.777532] Free swap  = 0kB
>[13454.777532] Total swap = 16642044kB
>[13454.777533] 4170340 pages RAM
>[13454.777533] 0 pages HighMem/MovableOnly
>[13454.777533] 87399 pages reserved
>[13454.777534] 0 pages cma reserved
>[13454.777534] 0 pages hwpoisoned
>[13454.777534] [ pid ]   uid  tgid total_vm      rss pgtables_bytes swapents oom_score_adj name
>[13454.777541] [  310]     0   310    21354        0   184320      821             0 systemd-journal
>[13454.777543] [  334]     0   334    11563        0   110592      506         -1000 systemd-udevd
>[13454.777544] [  818]   100   818    31893        0   151552      162             0 systemd-timesyn
>[13454.777545] [ 1011]     0  1011     7523        0   102400       68             0 cgmanager
>[13454.777546] [ 1012]     0  1012   105135        0   319488      495             0 ModemManager
>[13454.777547] [ 1014]   104  1014    64102        0   135168      419             0 rsyslogd
>[13454.777548] [ 1019]     0  1019     7776        1   110592       74             0 cron
>[13454.777549] [ 1021]   114  1021    94398        0   364544      453             0 whoopsie
>[13454.777550] [ 1023]     0  1023     8030        0   110592      103             0 bluetoothd
>[13454.777551] [ 1031]   120  1031    11285        0   135168      110             0 avahi-daemon
>[13454.777552] [ 1034]   106  1034    10923        1   131072      228          -900 dbus-daemon
>[13454.777553] [ 1048]   120  1048    11253        0   126976       87             0 avahi-daemon
>[13454.777554] [ 1066]     0  1066   117005        0   356352      676             0 NetworkManager
>[13454.777555] [ 1067]     0  1067    43334        0   188416      207             0 thermald
>[13454.777555] [ 1071]     0  1071     1097        0    53248       68             0 acpid
>[13454.777556] [ 1073]     0  1073    11109        0   131072      155             0 systemd-logind
>[13454.777558] [ 1076]     0  1076   208609        0   270336     3411             0 snapd
>[13454.777559] [ 1109]     0  1109    71028        0   196608      218             0 polkitd
>[13454.777559] [ 1120]     0  1120     4884        0    81920       80             0 irqbalance
>[13454.777560] [ 1170]   102  1170    11889        0   126976      137             0 systemd-resolve
>[13454.777561] [ 1181]     0  1181    19059        0   196608      138             0 login
>[13454.777562] [ 1193]  1000  1193    28137        0   258048    13864             0 python
>[13454.777563] [ 1224]     0  1224     1124        0    53248       23             0 sshguard-journa
>[13454.777564] [ 1226]     0  1226    42435        1   258048      105             0 journalctl
>[13454.777565] [ 1227]     0  1227     3901        0    61440      125             0 sshguard
>[13454.777566] [ 1228]     0  1228    16956        1   172032      186         -1000 sshd
>[13454.777567] [ 1309]  1000  1309    15719        1   155648      282             0 systemd
>[13454.777568] [ 1311]  1000  1311    22338        0   204800      578             0 (sd-pam)
>[13454.777569] [ 1319]  1000  1319    10750        0   131072      127             0 dbus-daemon
>[13454.777570] [ 1369]  1000  1369    46920        0   143360      193             0 dconf-service
>[13454.777571] [ 1413]  1000  1413    70873        0   188416      704             0 gvfsd
>[13454.777572] [ 1418]  1000  1418    87552        0   167936      709             0 gvfsd-fuse
>[13454.777573] [ 1441]  1000  1441     5633        0    86016      460             0 bash
>[13454.777575] [ 1723]     0  1723    13605        1   147456      259             0 systemd
>[13454.777576] [ 1724]     0  1724    59204        0   221184      589             0 (sd-pam)
>[13454.777577] [ 1731]     0  1731    10750        0   131072      131             0 dbus-daemon
>[13454.777578] [ 1759]     0  1759    46856        0   131072      132             0 dconf-service
>[13454.777579] [ 1762]     0  1762    70873        0   184320      195             0 gvfsd
>[13454.777580] [ 1767]     0  1767    87552        0   172032      709             0 gvfsd-fuse
>[13454.777581] [ 3811]  1000  3811     7374        0    98304      157             0 tmux
>[13454.777583] [ 3812]  1000  3812     5651        1    94208      480             0 bash
>[13454.777584] [ 3827]     0  3827     7350        0   102400      124             0 tmux
>[13454.777585] [ 3828]     0  3828     5644        1    90112      471             0 bash
>[13454.777586] [ 4634]     0  4634    26497        1   249856      251             0 sshd
>[13454.777587] [ 4698]  1000  4698    26497        1   245760      262             0 sshd
>[13454.777588] [ 4699]  1000  4699     3219        1    73728       49             0 sftp-server
>[13454.777589] [ 4716]     0  4716    26497        1   245760      251             0 sshd
>[13454.777590] [ 4780]  1000  4780    26497        0   237568      260             0 sshd
>[13454.777591] [ 4781]  1000  4781     5631        1    81920      455             0 bash
>[13454.777592] [ 4793]  1000  4793     5197        1    77824       82             0 tmux
>[13454.777593] [ 4794]     0  4794    26497        1   249856      251             0 sshd
>[13454.777594] [ 4836]  1000  4836    26497        1   241664      275             0 sshd
>[13454.777595] [ 4837]  1000  4837     3219        1    73728       73             0 sftp-server
>[13454.777596] [ 4848]     0  4848    26497        1   245760      252             0 sshd
>[13454.777597] [ 4890]  1000  4890    26497        0   237568      257             0 sshd
>[13454.777598] [ 4891]  1000  4891     5631        1    90112      455             0 bash
>[13454.777599] [ 4903]     0  4903    15776        1   172032      127             0 sudo
>[13454.777600] [ 4904]     0  4904    15673        1   167936      117             0 su
>[13454.777601] [ 4905]     0  4905     5297        1    81920      124             0 bash
>[13454.777602] [ 4919]     0  4919     5197        1    86016       82             0 tmux
>[13454.777603] [ 4920]     0  4920     3450        0    77824       38             0 dmesg
>[13454.777604] [ 4921]  1000  4921     5652        1    81920      482             0 bash
>[13454.777608] [ 5057]     0  5057    15776        0   176128      127             0 sudo
>[13454.777609] [ 5058]     0  5058    11250       14   126976       81          1000 gem_shrink
>[13454.777610] [ 5059]     0  5059   109554    25655   741376    50869          1000 gem_shrink
>[13454.777611] [ 5061]     0  5061   109554    32111   868352    60651          1000 gem_shrink
>[13454.777612] [ 5062]     0  5062   109554    16468   749568    61210          1000 gem_shrink
>[13454.777613] [ 5063]     0  5063   109554    15946   716800    57565          1000 gem_shrink
>[13454.777614] [ 5064]     0  5064   109554    21017   720896    53031          1000 gem_shrink
>[13454.777615] [ 5065]     0  5065   109554    40125   905216    56862          1000 gem_shrink
>[13454.777616] [ 5066]     0  5066    76786     6785   577536    49479          1000 gem_shrink
>[13454.777617] [ 5067]     0  5067   109554    13936   663552    52994          1000 gem_shrink
>[13454.777618] [ 5068]     0  5068   109554    16195   720896    57823          1000 gem_shrink
>[13454.777619] [ 5069]     0  5069    76786    14673   630784    47960          1000 gem_shrink
>[13454.777620] [ 5070]     0  5070   109554    13731   659456    52684          1000 gem_shrink
>[13454.777621] [ 5071]     0  5071    76786    15106   643072    49291          1000 gem_shrink
>[13454.777622] [ 5072]     0  5072    76786    10235   565248    44631          1000 gem_shrink
>[13454.777623] [ 5073]     0  5073    76786    12552   561152    41455          1000 gem_shrink
>[13454.777624] [ 5074]     0  5074    76786     6360   507904    40833          1000 gem_shrink
>[13454.777625] [ 5075]     0  5075    76786    20603   651264    45006          1000 gem_shrink
>[13454.777625] [ 5076]     0  5076    76786    14081   573440    41557          1000 gem_shrink
>[13454.777626] [ 5077]     0  5077    76786    20077   651264    45554          1000 gem_shrink
>[13454.777627] [ 5078]     0  5078   109554    24837   671744    43302          1000 gem_shrink
>[13454.777628] [ 5079]     0  5079    76786    15672   651264    49906          1000 gem_shrink
>[13454.777629] [ 5080]     0  5080   109554    23522   688128    46398          1000 gem_shrink
>[13454.777630] [ 5081]     0  5081   109554    20053   671744    47834          1000 gem_shrink
>[13454.777631] [ 5082]     0  5082   109554    23523   671744    44625          1000 gem_shrink
>[13454.777632] [ 5083]     0  5083   109554    29628   745472    47477          1000 gem_shrink
>[13454.777632] [ 5084]     0  5084    77243    18087   651264    47559          1000 gem_shrink
>[13454.777633] [ 5085]     0  5085   109554    25055   708608    47315          1000 gem_shrink
>[13454.777634] [ 5086]     0  5086    76786    18533   618496    42645          1000 gem_shrink
>[13454.777635] [ 5087]     0  5087   142322    56333  1024000    55837          1000 gem_shrink
>[13454.777636] [ 5088]     0  5088    76786    18585   618496    42744          1000 gem_shrink
>[13454.777637] [ 5089]     0  5089    76786     6791   528384    43130          1000 gem_shrink
>[13454.777638] [ 5090]     0  5090    76786     6300   569344    48912          1000 gem_shrink
>[13454.777639] [ 5091]     0  5091    76786     9206   589824    48593          1000 gem_shrink
>[13454.777640] [ 5092]     0  5092   109554    36352   765952    43403          1000 gem_shrink
>[13454.777640] [ 5093]     0  5093    76786     2072   487424    42949          1000 gem_shrink
>[13454.777642] [ 5094]     0  5094   109554    29780   757760    48658          1000 gem_shrink
>[13454.777643] [ 5095]     0  5095   109554    44968   905216    52370          1000 gem_shrink
>[13454.777643] [ 5096]     0  5096   109554    50349   909312    47339          1000 gem_shrink
>[13454.777644] [ 5097]     0  5097    76786    11135   557056    42295          1000 gem_shrink
>[13454.777645] [ 5098]     0  5098    76786    16297   634880    47095          1000 gem_shrink
>[13454.777646] [ 5099]     0  5099    76786      279   475136    43042          1000 gem_shrink
>[13454.777647] [ 5100]     0  5100    76786    21015   606208    38813          1000 gem_shrink
>[13454.777648] [ 5101]     0  5101   142322    53040   933888    47421          1000 gem_shrink
>[13454.777649] [ 5102]     0  5102   109554    25356   716800    47921          1000 gem_shrink
>[13454.777650] [ 5103]     0  5103   109554    29918   696320    40864          1000 gem_shrink
>[13454.777651] [ 5104]     0  5104    76786    30673   651264    34542          1000 gem_shrink
>[13454.777652] [ 5105]     0  5105   109554    14363   688128    55748          1000 gem_shrink
>[13454.777652] [ 5106]     0  5106    76788    23578   651264    42066          1000 gem_shrink
>[13454.777653] [ 5107]     0  5107    76786    15320   544768    36739          1000 gem_shrink
>[13454.777654] [ 5108]     0  5108    76786    11240   520192    37868          1000 gem_shrink
>[13454.777655] [ 5109]     0  5109    76786     9623   507904    37730          1000 gem_shrink
>[13454.777656] [ 5110]     0  5110   109554    13652   655360    52420          1000 gem_shrink
>[13454.777657] [ 5111]     0  5111   109554    21744   667648    45682          1000 gem_shrink
>[13454.777658] [ 5112]     0  5112    76786    25892   610304    34579          1000 gem_shrink
>[13454.777658] [ 5113]     0  5113    76786    21663   606208    37927          1000 gem_shrink
>[13454.777659] [ 5114]     0  5114    76786    16980   544768    35089          1000 gem_shrink
>[13454.777661] [ 5115]     0  5115    76786     6973   466944    35277          1000 gem_shrink
>[13454.777662] [ 5116]     0  5116    76786    16429   532480    34282          1000 gem_shrink
>[13454.777663] [ 5117]     0  5117    76786     1266   393216    31890          1000 gem_shrink
>[13454.777664] [ 5118]     0  5118    76786    28392   651264    36745          1000 gem_shrink
>[13454.777664] [ 5119]     0  5119    76786    20489   573440    35165          1000 gem_shrink
>[13454.777665] [ 5120]     0  5120    76786    18905   573440    36751          1000 gem_shrink
>[13454.777666] [ 5121]     0  5121    76786    26977   643072    37535          1000 gem_shrink
>[13454.777667] [ 5122]     0  5122    76786     4771   438272    33955          1000 gem_shrink
>[13454.777668] [ 5123]     0  5123    76786    10773   487424    33936          1000 gem_shrink
>[13454.777669] [ 5124]     0  5124    76786    27805   602112    31259          1000 gem_shrink
>[13454.777670] [ 5125]     0  5125    76786     3772   409600    31326          1000 gem_shrink
>[13454.777671] [ 5126]     0  5126    76786     5646   401408    28619          1000 gem_shrink
>[13454.777672] [ 5127]     0  5127    76786    11839   442368    27361          1000 gem_shrink
>[13454.777672] [ 5128]     0  5128    76786    15694   495616    30022          1000 gem_shrink
>[13454.777673] [ 5129]     0  5129   109554    35025   692224    35188          1000 gem_shrink
>[13454.777674] [ 5130]     0  5130    76786    17553   487424    27353          1000 gem_shrink
>[13454.777675] [ 5131]     0  5131   109554    39405   700416    32145          1000 gem_shrink
>[13454.777676] [ 5132]     0  5132    76786    28695   614400    31848          1000 gem_shrink
>[13454.777677] [ 5133]     0  5133    76786    22947   561152    31366          1000 gem_shrink
>[13454.777678] [ 5134]     0  5134    76786    32011   614400    28524          1000 gem_shrink
>[13454.777679] [ 5135]     0  5135    76786    31304   610304    28990          1000 gem_shrink
>[13454.777680] [ 5136]     0  5136    76786     8784   450560    31472          1000 gem_shrink
>[13454.777681] [ 5137]     0  5137    76786    25882   651264    39699          1000 gem_shrink
>[13454.777682] [ 5138]     0  5138    76786     5485   434176    32521          1000 gem_shrink
>[13454.777682] [ 5139]     0  5139    76786    17341   471040    25685          1000 gem_shrink
>[13454.777683] [ 5140]     0  5140   109554    50339   761856    28979          1000 gem_shrink
>[13454.777684] [ 5141]     0  5141    44018     9868   372736    21353          1000 gem_shrink
>[13454.777685] [ 5142]     0  5142    44018     1899   315392    21967          1000 gem_shrink
>[13454.777686] [ 5143]     0  5143    76786    10446   401408    23541          1000 gem_shrink
>[13454.777687] [ 5144]     0  5144    76786    25984   520192    22927          1000 gem_shrink
>[13454.777688] [ 5145]     0  5145    76786    10662   430080    27304          1000 gem_shrink
>[13454.777689] [ 5146]     0  5146    76786    25479   524288    23922          1000 gem_shrink
>[13454.777690] [ 5147]     0  5147   109554    30476   659456    35608          1000 gem_shrink
>[13454.777691] [ 5148]     0  5148   109554    34090   733184    41398          1000 gem_shrink
>[13454.777692] [ 5149]     0  5149    76786    27559   507904    19736          1000 gem_shrink
>[13454.777693] [ 5150]     0  5150    44018     8073   376832    23303          1000 gem_shrink
>[13454.777693] [ 5151]     0  5151    44018     6095   319488    18374          1000 gem_shrink
>[13454.777694] [ 5152]     0  5152    76786    35147   585728    21948          1000 gem_shrink
>[13454.777695] [ 5153]     0  5153    76786    41715   626688    20512          1000 gem_shrink
>[13454.777696] [ 5154]     0  5154    76786    16629   430080    21172          1000 gem_shrink
>[13454.777697] [ 5155]     0  5155    76786    36523   569344    18699          1000 gem_shrink
>[13454.777698] [ 5156]     0  5156    44018     9261   339968    17550          1000 gem_shrink
>[13454.777699] [ 5157]     0  5157    44018     4812   303104    17513          1000 gem_shrink
>[13454.777700] [ 5158]     0  5158    44018    14067   376832    17357          1000 gem_shrink
>[13454.777701] [ 5159]     0  5159    44018     7905   335872    18388          1000 gem_shrink
>[13454.777702] [ 5160]     0  5160    76786    18629   389120    14197          1000 gem_shrink
>[13454.777703] [ 5161]     0  5161    76786    42689   630784    20013          1000 gem_shrink
>[13454.777704] [ 5162]     0  5162    44018    12932   372736    18214          1000 gem_shrink
>[13454.777705] [ 5163]     0  5163    76786    33145   536576    17619          1000 gem_shrink
>[13454.777706] [ 5164]     0  5164    76786    39052   540672    12285          1000 gem_shrink
>[13454.777706] [ 5165]     0  5165    76786    50841   651264    14316          1000 gem_shrink
>[13454.777707] [ 5166]     0  5166    76786    31603   475136    11519          1000 gem_shrink
>[13454.777708] [ 5167]     0  5167    76786    25874   487424    19056          1000 gem_shrink
>[13454.777709] [ 5168]     0  5168    44018     5272   237568     8854          1000 gem_shrink
>[13454.777710] [ 5169]     0  5169    44018     7412   270336    10708          1000 gem_shrink
>[13454.777711] [ 5170]     0  5170    76786    27301   479232    16641          1000 gem_shrink
>[13454.777712] [ 5171]     0  5171    44018    17674   339968     9056          1000 gem_shrink
>[13454.777713] [ 5172]     0  5172    76786    50915   614400     9722          1000 gem_shrink
>[13454.777714] [ 5173]     0  5173    44018     3971   241664    10638          1000 gem_shrink
>[13454.777715] [ 5174]     0  5174    44018    12432   307200    10538          1000 gem_shrink
>[13454.777716] [ 5175]     0  5175    76786    55471   647168     9089          1000 gem_shrink
>[13454.777717] [ 5176]     0  5176    76786    39893   520192     9178          1000 gem_shrink
>[13454.777718] [ 5177]     0  5177    44018     6676   249856     8878          1000 gem_shrink
>[13454.777719] [ 5178]     0  5178    44018     7070   229376     5874          1000 gem_shrink
>[13454.777720] [ 5179]     0  5179    44018    25607   364544     4468          1000 gem_shrink
>[13454.777721] [ 5180]     0  5180    76786    32017   466944    10482          1000 gem_shrink
>[13454.777721] [ 5181]     0  5181    76786    35971   471040     6653          1000 gem_shrink
>[13454.777722] [ 5182]     0  5182    44018    24596   368640     5710          1000 gem_shrink
>[13454.777723] [ 5183]     0  5183    44018    11458   262144     5986          1000 gem_shrink
>[13454.777724] [ 5184]     0  5184    76786       12   389120       83          1000 gem_shrink
>[13454.777725] [ 5185]     0  5185   109554     6336   704512       84          1000 gem_shrink
>[13454.777726] [ 5186]     0  5186   142322     7406   974848       90          1000 gem_shrink
>[13454.777727] [ 5192]     0  5192    76786    13553   499712       84          1000 gem_shrink
>[13454.777728] [ 5193]     0  5193    76786    15367   512000       83          1000 gem_shrink
>[13454.777729] [ 5194]     0  5194    76786     9760   471040       83          1000 gem_shrink
>[13454.777730] [ 5195]     0  5195    76786    22002   565248       84          1000 gem_shrink
>[13454.777731] [ 5202]     0  5202    44018      644   131072       70          1000 gem_shrink
>[13454.777732] [ 5204]     0  5204    44018     9557   200704       64          1000 gem_shrink
>[13454.777733] [ 5205]     0  5205    44018     7253   184320       60          1000 gem_shrink
>[13454.777733] [ 5206]     0  5206    44018    32803   389120       60          1000 gem_shrink
>[13454.777734] [ 5207]     0  5207    76786      798   397312       60          1000 gem_shrink
>[13454.777735] [ 5208]     0  5208    76786       34   389120       61          1000 gem_shrink
>[13454.777736] [ 5209]     0  5209    44018    32803   389120       60          1000 gem_shrink
>[13454.777737] [ 5210]     0  5210    44018    27540   344064       60          1000 gem_shrink
>[13454.777738] [ 5211]     0  5211    44018    18399   270336       61          1000 gem_shrink
>[13454.777739] [ 5212]     0  5212    44018    12882   229376       60          1000 gem_shrink
>[13454.777739] [ 5213]     0  5213    44018     7367   184320       60          1000 gem_shrink
>[13454.777740] [ 5214]     0  5214    44018    32766   385024       61          1000 gem_shrink
>[13454.777741] [ 5215]     0  5215    44018    27677   348160       61          1000 gem_shrink
>[13454.777742] [ 5216]     0  5216    44018     1958   139264       61          1000 gem_shrink
>[13454.777743] [ 5217]     0  5217    44018    17439   266240       60          1000 gem_shrink
>[13454.777743] [ 5218]     0  5218    76786       35   389120       60          1000 gem_shrink
>[13454.777744] [ 5219]     0  5219    44018    32803   389120       60          1000 gem_shrink
>[13454.777745] [ 5220]     0  5220    44018     2683   147456       61          1000 gem_shrink
>[13454.777746] [ 5221]     0  5221    76786     1590   405504       61          1000 gem_shrink
>[13454.777747] [ 5222]     0  5222    76786     9188   462848       61          1000 gem_shrink
>[13454.777747] [ 5223]     0  5223    76786    10434   475136       60          1000 gem_shrink
>[13454.777748] [ 5224]     0  5224    44018    17199   262144       60          1000 gem_shrink
>[13454.777749] [ 5225]     0  5225    44018       45   389120       51          1000 gem_shrink
>[13454.777750] [ 5226]     0  5226    44018    31586   376832       62          1000 gem_shrink
>[13454.777751] [ 5227]     0  5227    44018    12285   221184       63          1000 gem_shrink
>[13454.777751] [ 5228]     0  5228    44018    18167   270336       60          1000 gem_shrink
>[13454.777752] [ 5229]     0  5229    44018    23309   311296       60          1000 gem_shrink
>[13454.777753] [ 5230]     0  5230    76786     4326   425984       60          1000 gem_shrink
>[13454.777754] [ 5231]     0  5231    44018    13760   233472       61          1000 gem_shrink
>[13454.777755] [ 5232]     0  5232    44018     8993   196608       60          1000 gem_shrink
>[13454.777756] [ 5233]     0  5233    44018    10910   212992       60          1000 gem_shrink
>[13454.777756] [ 5234]     0  5234    44018    12878   229376       60          1000 gem_shrink
>[13454.777757] [ 5235]     0  5235    44018    32803   389120       60          1000 gem_shrink
>[13454.777758] [ 5236]     0  5236    44018    22476   303104       60          1000 gem_shrink
>[13454.777759] [ 5237]     0  5237    44018    32803   389120       60          1000 gem_shrink
>[13454.777760] [ 5238]     0  5238    44018    11908   221184       60          1000 gem_shrink
>[13454.777761] [ 5239]     0  5239    44018    32483   385024       61          1000 gem_shrink
>[13454.777762] [ 5240]     0  5240    44018       35   122880       60          1000 gem_shrink
>[13454.777762] [ 5241]     0  5241    44018     4157   159744       60          1000 gem_shrink
>[13454.777763] [ 5242]     0  5242    44018     8369   192512       60          1000 gem_shrink
>[13454.777764] [ 5243]     0  5243    44018       35   389120       60          1000 gem_shrink
>[13454.777765] [ 5244]     0  5244    44018    32803   389120       60          1000 gem_shrink
>[13454.777766] [ 5245]     0  5245    44018    15876   249856       61          1000 gem_shrink
>[13454.777767] [ 5246]     0  5246    44018      265   126976       60          1000 gem_shrink
>[13454.777768] [ 5247]     0  5247    44018    11736   217088       60          1000 gem_shrink
>[13454.777769] [ 5248]     0  5248    44018       35   122880       60          1000 gem_shrink
>[13454.777770] [ 5249]     0  5249    44018    30186   364544       60          1000 gem_shrink
>[13454.777770] [ 5250]     0  5250    44018       34   389120       61          1000 gem_shrink
>[13454.777771] [ 5251]     0  5251    44018    14196   237568       61          1000 gem_shrink
>[13454.777772] [ 5252]     0  5252    44018    32803   389120       60          1000 gem_shrink
>[13454.777773] [ 5253]     0  5253    44018    23335   311296       60          1000 gem_shrink
>[13454.777774] [ 5254]     0  5254    44018       35   122880       60          1000 gem_shrink
>[13454.777775] [ 5255]     0  5255    44018    32802   389120       61          1000 gem_shrink
>[13454.777776] [ 5256]     0  5256    44018    18021   270336       60          1000 gem_shrink
>[13454.777777] [ 5257]     0  5257    44018     4307   159744       60          1000 gem_shrink
>[13454.777777] [ 5258]     0  5258    44018     8588   192512       60          1000 gem_shrink
>[13454.777778] [ 5259]     0  5259    44018     3615   155648       73          1000 gem_shrink
>[13454.777780] [ 5260]     0  5260    44018    12259   225280       73          1000 gem_shrink
>[13454.777780] [ 5261]     0  5261    44018     7969   188416       73          1000 gem_shrink
>[13454.777781] [ 5262]     0  5262    44018    25196   327680       73          1000 gem_shrink
>[13454.777782] [ 5263]     0  5263    44018     1899   139264       73          1000 gem_shrink
>[13454.777783] [ 5264]     0  5264    44018     2164   143360       73          1000 gem_shrink
>[13454.777784] [ 5265]     0  5265    44018     6056   172032       73          1000 gem_shrink
>[13454.777785] [ 5266]     0  5266    44018     6717   180224       73          1000 gem_shrink
>[13454.777787] [ 5267]     0  5267    44018     2097   143360       73          1000 gem_shrink
>[13454.777787] [ 5268]     0  5268    44018    14502   241664       73          1000 gem_shrink
>[13454.777789] [ 5269]     0  5269    44018    16219   253952       73          1000 gem_shrink
>[13454.777790] [ 5270]     0  5270    44018     3020   147456       73          1000 gem_shrink
>[13454.777791] [ 5271]     0  5271    44018    17207   262144       73          1000 gem_shrink
>[13454.777792] [ 5272]     0  5272    44018     2823   147456       73          1000 gem_shrink
>[13454.777793] [ 5273]     0  5273    44018    14109   237568       73          1000 gem_shrink
>[13454.777794] [ 5274]     0  5274    44018     3417   151552       73          1000 gem_shrink
>[13454.777795] [ 5275]     0  5275    44018     1021   135168       73          1000 gem_shrink
>[13454.777796] [ 5276]     0  5276    44018     5131   167936       73          1000 gem_shrink
>[13454.777797] [ 5277]     0  5277    44018     9686   204800       73          1000 gem_shrink
>[13454.777798] [ 5278]     0  5278    44018     6123   172032       73          1000 gem_shrink
>[13454.777799] [ 5279]     0  5279    44018     3087   151552       73          1000 gem_shrink
>[13454.777800] [ 5280]     0  5280    44018     8762   196608       73          1000 gem_shrink
>[13454.777802] [ 5281]     0  5281    44018     9090   196608       73          1000 gem_shrink
>[13454.777803] [ 5282]     0  5282    44018     1569   139264       73          1000 gem_shrink
>[13454.777804] [ 5283]     0  5283    44018     6055   172032       73          1000 gem_shrink
>[13454.777805] [ 5284]     0  5284    44018     4340   159744       73          1000 gem_shrink
>[13454.777806] [ 5285]     0  5285    11250       15   122880       80          1000 gem_shrink
>[13454.777807] [ 5286]     0  5286    44018     2882   147456       73          1000 gem_shrink
>[13454.777808] [ 5287]     0  5287    11250       16   122880       79          1000 gem_shrink
>[13454.777809] [ 5288]     0  5288    44018       77   126976       72          1000 gem_shrink
>[13454.777810] [ 5289]     0  5289    44018     1076   135168       72          1000 gem_shrink
>[13454.777811] [ 5290]     0  5290    11250       14   114688       81          1000 gem_shrink
>[13454.777812] [ 5291]     0  5291    44018    15494   249856       72          1000 gem_shrink
>[13454.777813] [ 5292]     0  5292    44018    10742   212992       72          1000 gem_shrink
>[13454.777814] [ 5293]     0  5293    11250       14   114688       81          1000 gem_shrink
>[13454.777815] [ 5294]     0  5294    44018     4538   159744       72          1000 gem_shrink
>[13454.777816] [ 5295]     0  5295    44018     6716   180224       72          1000 gem_shrink
>[13454.777817] [ 5296]     0  5296    44018     2558   147456       72          1000 gem_shrink
>[13454.777818] [ 5297]     0  5297    44018     5788   172032       72          1000 gem_shrink
>[13454.777819] [ 5298]     0  5298    44018    17804   266240       72          1000 gem_shrink
>[13454.777820] [ 5299]     0  5299    44018    10147   204800       72          1000 gem_shrink
>[13454.777821] [ 5300]     0  5300    44018     8498   192512       72          1000 gem_shrink
>[13454.777822] [ 5301]     0  5301    44018    10873   212992       72          1000 gem_shrink
>[13454.777824] [ 5302]     0  5302    44018    26119   335872       72          1000 gem_shrink
>[13454.777825] [ 5303]     0  5303    44018    12325   225280       72          1000 gem_shrink
>[13454.777826] [ 5304]     0  5304    44018      506   131072       72          1000 gem_shrink
>[13454.777827] [ 5305]     0  5305    44018    12524   225280       72          1000 gem_shrink
>[13454.777828] [ 5306]     0  5306    44018     4599   163840       72          1000 gem_shrink
>[13454.777829] [ 5307]     0  5307    44018     5198   167936       72          1000 gem_shrink
>[13454.777830] [ 5308]     0  5308    44018    10280   208896       72          1000 gem_shrink
>[13454.777831] [ 5309]     0  5309    44018      549   131072       72          1000 gem_shrink
>[13454.777832] [ 5310]     0  5310    44018     2811   147456       72          1000 gem_shrink
>[13454.777833] [ 5311]     0  5311    44018     7640   188416       72          1000 gem_shrink
>[13454.777834] [ 5312]     0  5312    44018     3152   151552       72          1000 gem_shrink
>[13454.777835] [ 5313]     0  5313    44018     2559   147456       72          1000 gem_shrink
>[13454.777837] [ 5314]     0  5314    44018     2030   139264       72          1000 gem_shrink
>[13454.777838] [ 5315]     0  5315    44018     2135   143360       72          1000 gem_shrink
>[13454.777839] [ 5316]     0  5316    44018     7970   188416       72          1000 gem_shrink
>[13454.777840] [ 5317]     0  5317    44018    17211   262144       72          1000 gem_shrink
>[13454.777841] [ 5318]     0  5318    44018     8300   192512       72          1000 gem_shrink
>[13454.777842] [ 5319]     0  5319    44018    14305   241664       72          1000 gem_shrink
>[13454.777843] [ 5320]     0  5320    44018     5922   172032       72          1000 gem_shrink
>[13454.777844] [ 5321]     0  5321    44018    16285   253952       72          1000 gem_shrink
>[13454.777849] Out of memory: Kill process 5087 (gem_shrink) score 1013 or sacrifice child
>[13454.777855] Killed process 5087 (gem_shrink) total-vm:569288kB, anon-rss:225324kB, file-rss:8kB, shmem-rss:0kB
>[13454.802376] oom_reaper: reaped process 5087 (gem_shrink), now anon-rss:0kB, file-rss:0kB, shmem-rss:0kB
>[13455.404658] [IGT] gem_shrink: exiting, ret=139
>[13467.793360] [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000f4a04a67
>[13467.793368] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 000000000cfdf97e state to 00000000f4a04a67
>[13467.793374] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:37:pipe A] 00000000ae5bcee3 state to 00000000f4a04a67
>[13467.793378] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:31:plane 2A] 000000003d1d34a2 state to 00000000f4a04a67
>[13467.793382] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 000000003d1d34a2 to [NOCRTC]
>[13467.793385] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for plane state 000000003d1d34a2
>[13467.793389] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:34:cursor A] 000000001ee0d9a3 state to 00000000f4a04a67
>[13467.793392] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 000000001ee0d9a3 to [NOCRTC]
>[13467.793396] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for plane state 000000001ee0d9a3
>[13467.793400] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:38:plane 1B] 00000000bd13edbd state to 00000000f4a04a67
>[13467.793403] [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:47:pipe B] 00000000644f71c0 state to 00000000f4a04a67
>[13467.793407] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:41:plane 2B] 000000006319393a state to 00000000f4a04a67
>[13467.793410] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 000000006319393a to [NOCRTC]
>[13467.793413] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for plane state 000000006319393a
>[13467.793417] [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:44:cursor B] 000000002179dd5b state to 00000000f4a04a67
>[13467.793420] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 000000002179dd5b to [NOCRTC]
>[13467.793423] [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for plane state 000000002179dd5b
>[13467.793428] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [MODE:1920x1080] for CRTC state 00000000ae5bcee3
>[13467.793431] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 000000000cfdf97e to [CRTC:37:pipe A]
>[13467.793435] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:115] for plane state 000000000cfdf97e
>[13467.793438] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:37:pipe A] to 00000000f4a04a67
>[13467.793443] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:56:DP-1] 00000000754cd835 state to 00000000f4a04a67
>[13467.793446] [drm:drm_atomic_set_crtc_for_connector [drm]] Link connector state 00000000754cd835 to [NOCRTC]
>[13467.793450] [drm:drm_atomic_set_crtc_for_connector [drm]] Link connector state 00000000754cd835 to [CRTC:37:pipe A]
>[13467.793453] [drm:drm_atomic_set_mode_for_crtc [drm]] Set [MODE:1920x1200] for CRTC state 00000000644f71c0
>[13467.793457] [drm:drm_atomic_set_crtc_for_plane [drm]] Link plane state 00000000bd13edbd to [CRTC:47:pipe B]
>[13467.793460] [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:115] for plane state 00000000bd13edbd
>[13467.793463] [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:47:pipe B] to 00000000f4a04a67
>[13467.793467] [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:61:DP-2] 00000000ab89faa3 state to 00000000f4a04a67
>[13467.793470] [drm:drm_atomic_set_crtc_for_connector [drm]] Link connector state 00000000ab89faa3 to [NOCRTC]
>[13467.793473] [drm:drm_atomic_set_crtc_for_connector [drm]] Link connector state 00000000ab89faa3 to [CRTC:47:pipe B]
>[13467.793477] [drm:drm_atomic_check_only [drm]] checking 00000000f4a04a67
>[13467.793483] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:56:DP-1]
>[13467.793486] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:56:DP-1] keeps [ENCODER:55:DDI B], now on [CRTC:37:pipe A]
>[13467.793488] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:61:DP-2]
>[13467.793490] [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:61:DP-2] keeps [ENCODER:60:DDI C], now on [CRTC:47:pipe B]
>[13467.793512] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:37:pipe A] has [PLANE:28:plane 1A] with fb 115
>[13467.793525] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>[13467.793537] [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:47:pipe B] has [PLANE:38:plane 1B] with fb 115
>[13467.793549] [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:38:plane 1B] visible 1 -> 1, off 0, on 0, ms 0
>[13467.793558] [drm:drm_atomic_commit [drm]] committing 00000000f4a04a67
>[13467.809943] [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000f4a04a67
>[13467.809952] [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000f4a04a67

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Attachments on bug 104407: 136432 | 136433

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