Attachment 137536 Details for Bug 105177 – [PATCH] update infoframe after dig fe is turned on

[patch] [PATCH] update infoframe after dig fe is turned on

0001-drm-amd-display-update-infoframe-after-dig-fe-is-tur.patch (text/plain), 2.62 KB, created by Harry Wentland on 2018-02-22 20:19:34 UTC

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Creator: Harry Wentland

Created: 2018-02-22 20:19:34 UTC

Size: 2.62 KB

patch

obsolete

>From 2724748c24b2499edfbacb6d7ee575d8e5bf2ef1 Mon Sep 17 00:00:00 2001
>From: Eric Yang <Eric.Yang2@amd.com>
>Date: Wed, 21 Feb 2018 16:37:16 -0500
>Subject: [PATCH] drm/amd/display: update infoframe after dig fe is turned on
>
>Before dig fe is enabled, infoframe can't be programmed. So in
>suspend resume case our infoframe programmming was not going through.
>
>This change changes the sequence so that infoframe is programmed
>after.
>
>Change-Id: I5f2be964b19a2da68c9910197f8e95df5f153eb4
>Signed-off-by: Eric Yang <Eric.Yang2@amd.com>
>Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
>Acked-by: Harry Wentland <harry.wentland@amd.com>
>---
> .../amd/display/dc/dce110/dce110_hw_sequencer.c    | 23 ++++++++++++----------
> 1 file changed, 13 insertions(+), 10 deletions(-)
>
>diff --git a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
>index 0422c72a7579..4bfb3bef1893 100644
>--- a/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
>+++ b/drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
>@@ -682,15 +682,22 @@ void dce110_enable_stream(struct pipe_ctx *pipe_ctx)
> 	struct dc_crtc_timing *timing = &pipe_ctx->stream->timing;
> 	struct dc_link *link = pipe_ctx->stream->sink->link;
> 
>-	/* 1. update AVI info frame (HDMI, DP)
>-	 * we always need to update info frame
>-	*/
>+
> 	uint32_t active_total_with_borders;
> 	uint32_t early_control = 0;
> 	struct timing_generator *tg = pipe_ctx->stream_res.tg;
> 
>-	/* TODOFPGA may change to hwss.update_info_frame */
>+	/* For MST, there are multiply stream go to only one link.
>+	 * connect DIG back_end to front_end while enable_stream and
>+	 * disconnect them during disable_stream
>+	 * BY this, it is logic clean to separate stream and link */
>+	link->link_enc->funcs->connect_dig_be_to_fe(link->link_enc,
>+						    pipe_ctx->stream_res.stream_enc->id, true);
>+
>+	/* update AVI info frame (HDMI, DP)*/
>+	/* TODO: FPGA may change to hwss.update_info_frame */
> 	dce110_update_info_frame(pipe_ctx);
>+
> 	/* enable early control to avoid corruption on DP monitor*/
> 	active_total_with_borders =
> 			timing->h_addressable
>@@ -711,12 +718,8 @@ void dce110_enable_stream(struct pipe_ctx *pipe_ctx)
> 			pipe_ctx->stream_res.stream_enc->funcs->dp_audio_enable(pipe_ctx->stream_res.stream_enc);
> 	}
> 
>-	/* For MST, there are multiply stream go to only one link.
>-	 * connect DIG back_end to front_end while enable_stream and
>-	 * disconnect them during disable_stream
>-	 * BY this, it is logic clean to separate stream and link */
>-	link->link_enc->funcs->connect_dig_be_to_fe(link->link_enc,
>-						    pipe_ctx->stream_res.stream_enc->id, true);
>+
>+
> 
> }
> 
>-- 
>2.14.1
>

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Attachments on bug 105177: 137478 | 137479 | 137480 | 137510 | 137511 | 137512 | 137513 | 137514 | 137536 | 137575 | 137576 | 137577

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