Attachment 138761 Details for Bug 105949 – Revert WA 1183

[patch] Revert WA 1183

revert-1183-wa.patch (text/plain), 4.09 KB, created by Imre Deak on 2018-04-11 15:50:08 UTC

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Creator: Imre Deak

Created: 2018-04-11 15:50:08 UTC

Size: 4.09 KB

patch

obsolete

>diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
>index fb106026a1f4..032c98b3877b 100644
>--- a/drivers/gpu/drm/i915/i915_reg.h
>+++ b/drivers/gpu/drm/i915/i915_reg.h
>@@ -7113,7 +7113,6 @@ enum {
> #define  RESET_PCH_HANDSHAKE_ENABLE	(1<<4)
> 
> #define GEN8_CHICKEN_DCPR_1		_MMIO(0x46430)
>-#define   SKL_SELECT_ALTERNATE_DC_EXIT	(1 << 30)
> #define   MASK_WAKEMEM			(1 << 13)
> #define   CNL_DDI_CLOCK_REG_ACCESS_ON	(1 << 7)
> 
>@@ -8780,7 +8779,6 @@ enum skl_power_gate {
> #define  BXT_CDCLK_CD2X_DIV_SEL_2	(2 << 22)
> #define  BXT_CDCLK_CD2X_DIV_SEL_4	(3 << 22)
> #define  BXT_CDCLK_CD2X_PIPE(pipe)	((pipe) << 20)
>-#define  CDCLK_DIVMUX_CD_OVERRIDE	(1 << 19)
> #define  BXT_CDCLK_CD2X_PIPE_NONE	BXT_CDCLK_CD2X_PIPE(3)
> #define  ICL_CDCLK_CD2X_PIPE_NONE	(7 << 19)
> #define  BXT_CDCLK_SSA_PRECHARGE_ENABLE	(1 << 16)
>diff --git a/drivers/gpu/drm/i915/intel_cdclk.c b/drivers/gpu/drm/i915/intel_cdclk.c
>index dc7db8a2caf8..cced00826d45 100644
>--- a/drivers/gpu/drm/i915/intel_cdclk.c
>+++ b/drivers/gpu/drm/i915/intel_cdclk.c
>@@ -931,10 +931,16 @@ static void skl_set_preferred_cdclk_vco(struct drm_i915_private *dev_priv,
> 
> static void skl_dpll0_enable(struct drm_i915_private *dev_priv, int vco)
> {
>+	int min_cdclk = skl_calc_cdclk(0, vco);
> 	u32 val;
> 
> 	WARN_ON(vco != 8100000 && vco != 8640000);
> 
>+	/* select the minimum CDCLK before enabling DPLL 0 */
>+	val = CDCLK_FREQ_337_308 | skl_cdclk_decimal(min_cdclk);
>+	I915_WRITE(CDCLK_CTL, val);
>+	POSTING_READ(CDCLK_CTL);
>+
> 	/*
> 	 * We always enable DPLL0 with the lowest link rate possible, but still
> 	 * taking into account the VCO required to operate the eDP panel at the
>@@ -988,7 +994,7 @@ static void skl_set_cdclk(struct drm_i915_private *dev_priv,
> {
> 	int cdclk = cdclk_state->cdclk;
> 	int vco = cdclk_state->vco;
>-	u32 freq_select, cdclk_ctl;
>+	u32 freq_select;
> 	int ret;
> 
> 	mutex_lock(&dev_priv->pcu_lock);
>@@ -1003,7 +1009,7 @@ static void skl_set_cdclk(struct drm_i915_private *dev_priv,
> 		return;
> 	}
> 
>-	/* Choose frequency for this cdclk */
>+	/* set CDCLK_CTL */
> 	switch (cdclk) {
> 	default:
> 		WARN_ON(cdclk != dev_priv->cdclk.hw.bypass);
>@@ -1030,33 +1036,10 @@ static void skl_set_cdclk(struct drm_i915_private *dev_priv,
> 	    dev_priv->cdclk.hw.vco != vco)
> 		skl_dpll0_disable(dev_priv);
> 
>-	cdclk_ctl = I915_READ(CDCLK_CTL);
>-
>-	if (dev_priv->cdclk.hw.vco != vco) {
>-		/* Wa Display #1183: skl,kbl,cfl */
>-		cdclk_ctl &= ~(CDCLK_FREQ_SEL_MASK | CDCLK_FREQ_DECIMAL_MASK);
>-		cdclk_ctl |= freq_select | skl_cdclk_decimal(cdclk);
>-		I915_WRITE(CDCLK_CTL, cdclk_ctl);
>-	}
>-
>-	/* Wa Display #1183: skl,kbl,cfl */
>-	cdclk_ctl |= CDCLK_DIVMUX_CD_OVERRIDE;
>-	I915_WRITE(CDCLK_CTL, cdclk_ctl);
>-	POSTING_READ(CDCLK_CTL);
>-
> 	if (dev_priv->cdclk.hw.vco != vco)
> 		skl_dpll0_enable(dev_priv, vco);
> 
>-	/* Wa Display #1183: skl,kbl,cfl */
>-	cdclk_ctl &= ~(CDCLK_FREQ_SEL_MASK | CDCLK_FREQ_DECIMAL_MASK);
>-	I915_WRITE(CDCLK_CTL, cdclk_ctl);
>-
>-	cdclk_ctl |= freq_select | skl_cdclk_decimal(cdclk);
>-	I915_WRITE(CDCLK_CTL, cdclk_ctl);
>-
>-	/* Wa Display #1183: skl,kbl,cfl */
>-	cdclk_ctl &= ~CDCLK_DIVMUX_CD_OVERRIDE;
>-	I915_WRITE(CDCLK_CTL, cdclk_ctl);
>+	I915_WRITE(CDCLK_CTL, freq_select | skl_cdclk_decimal(cdclk));
> 	POSTING_READ(CDCLK_CTL);
> 
> 	/* inform PCU of the change */
>diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
>index 53ea564f971e..a309d6ffb638 100644
>--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
>+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
>@@ -617,11 +617,6 @@ void gen9_enable_dc5(struct drm_i915_private *dev_priv)
> 
> 	DRM_DEBUG_KMS("Enabling DC5\n");
> 
>-	/* Wa Display #1183: skl,kbl,cfl */
>-	if (IS_GEN9_BC(dev_priv))
>-		I915_WRITE(GEN8_CHICKEN_DCPR_1, I915_READ(GEN8_CHICKEN_DCPR_1) |
>-			   SKL_SELECT_ALTERNATE_DC_EXIT);
>-
> 	gen9_set_dc_state(dev_priv, DC_STATE_EN_UPTO_DC5);
> }
> 
>@@ -649,11 +644,6 @@ void skl_disable_dc6(struct drm_i915_private *dev_priv)
> {
> 	DRM_DEBUG_KMS("Disabling DC6\n");
> 
>-	/* Wa Display #1183: skl,kbl,cfl */
>-	if (IS_GEN9_BC(dev_priv))
>-		I915_WRITE(GEN8_CHICKEN_DCPR_1, I915_READ(GEN8_CHICKEN_DCPR_1) |
>-			   SKL_SELECT_ALTERNATE_DC_EXIT);
>-
> 	gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
> }
>

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Attachments on bug 105949: 138696 | 138707 | 138726 | 138761 | 138906 | 138930 | 139406

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