Attachment 141475 Details for Bug 107505 – intel: limit urb size for SKL GT1

[patch] intel: limit urb size for SKL GT1

0001-intel-limit-urb-size-for-SKL-GT1.patch (text/plain), 2.40 KB, created by Lionel Landwerlin on 2018-09-07 19:58:19 UTC

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Creator: Lionel Landwerlin

Created: 2018-09-07 19:58:19 UTC

Size: 2.40 KB

patch

obsolete

>From 6ca5358a769c85edd8eeca0d815fbe4e64965015 Mon Sep 17 00:00:00 2001
>From: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
>Date: Fri, 7 Sep 2018 15:49:37 -0400
>Subject: [PATCH] intel: limit urb size for SKL GT1
>
>The documentation puts the URB size for SKL GT1 as "128-192K". I guess
>this means we can't guess which one it is, so we have to go for the
>lower bound. This change changes the L3 programming and limits the
>allocation algorithm to 128K. I'm not completely sure this is correct
>at least it fixes a CTS test :
>
>  dEQP-GLES31.functional.geometry_shading.layered.render_with_default_layer_3d
>
>Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
>Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=107505
>---
> src/intel/common/gen_l3_config.c | 16 ++++++++++++++++
> src/intel/dev/gen_device_info.c  |  2 +-
> 2 files changed, 17 insertions(+), 1 deletion(-)
>
>diff --git a/src/intel/common/gen_l3_config.c b/src/intel/common/gen_l3_config.c
>index b977c6ab136..f9d71d1dfdf 100644
>--- a/src/intel/common/gen_l3_config.c
>+++ b/src/intel/common/gen_l3_config.c
>@@ -101,6 +101,20 @@ static const struct gen_l3_config chv_l3_configs[] = {
>    {{ 0 }}
> };
> 
>+static const struct gen_l3_config gen9_gt1_l3_configs[] = {
>+   /* SLM URB ALL DC  RO  IS   C   T */
>+   {{  0, 32, 32,  0,  0,  0,  0,  0 }},
>+   /* Below entries are untested. */
>+   {{  0, 32,  0, 16, 32,  0,  0,  0 }},
>+   {{  0, 32,  0, 16, 48,  0,  0,  0 }},
>+   {{  0, 32,  0,  0, 64,  0,  0,  0 }},
>+   {{  0, 32, 64,  0,  0,  0,  0,  0 }},
>+   {{ 16, 16, 32,  0,  0,  0,  0,  0 }},
>+   {{ 16, 16,  0, 16, 32,  0,  0,  0 }},
>+   {{ 16, 16,  0, 32, 16,  0,  0,  0 }},
>+   {{ 0 }}
>+};
>+
> /**
>  * BXT 2x6 validated L3 configurations.  \sa ivb_l3_configs.
>  */
>@@ -164,6 +178,8 @@ get_l3_configs(const struct gen_device_info *devinfo)
>    case 9:
>       if (devinfo->l3_banks == 1)
>          return bxt_2x6_l3_configs;
>+      if (devinfo->gt == 1)
>+         return gen9_gt1_l3_configs;
>       return chv_l3_configs;
> 
>    case 10:
>diff --git a/src/intel/dev/gen_device_info.c b/src/intel/dev/gen_device_info.c
>index b0ae4d18034..594ee30080d 100644
>--- a/src/intel/dev/gen_device_info.c
>+++ b/src/intel/dev/gen_device_info.c
>@@ -617,7 +617,7 @@ static const struct gen_device_info gen_device_info_skl_gt1 = {
>    .num_subslices = { 2, },
>    .num_eu_per_subslice = 6,
>    .l3_banks = 2,
>-   .urb.size = 192,
>+   .urb.size = 128,
>    .simulator_id = 12,
> };
> 
>-- 
>2.19.0.rc1
>

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