Attachment 14209 Details for Bug 14249 – Read & write VGA regs via MMIO instead of port I/O

[patch] Read & write VGA regs via MMIO instead of port I/O

i915-vga-mmio.patch (text/plain), 9.72 KB, created by Jesse Barnes on 2008-02-07 17:03:18 UTC

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Creator: Jesse Barnes

Created: 2008-02-07 17:03:18 UTC

Size: 9.72 KB

patch

obsolete

>diff --git a/linux-core/i915_drv.c b/linux-core/i915_drv.c
>index ccc061d..2e5aa13 100644
>--- a/linux-core/i915_drv.c
>+++ b/linux-core/i915_drv.c
>@@ -68,6 +68,27 @@ enum pipe {
>     PIPE_B,
> };
> 
>+int vga_use_mmio = 1;
>+
>+static u8 vga_read(struct drm_device *dev, u16 addr)
>+{
>+	struct drm_i915_private *dev_priv = dev->dev_private;
>+
>+	if (vga_use_mmio)
>+		return readb(dev_priv->vga_mmio_base + addr);
>+	else
>+		return inb(addr);
>+}
>+
>+static void vga_write(struct drm_device *dev, u16 addr, u8 val)
>+{
>+	struct drm_i915_private *dev_priv = dev->dev_private;
>+
>+	if (vga_use_mmio)
>+		writeb(val, dev_priv->vga_mmio_base + addr);
>+	else
>+		outb(val, addr);
>+}
> static bool i915_pipe_enabled(struct drm_device *dev, enum pipe pipe)
> {
> 	struct drm_i915_private *dev_priv = dev->dev_private;
>@@ -116,30 +137,34 @@ static void i915_restore_palette(struct drm_device *dev, enum pipe pipe)
> 		I915_WRITE(reg + (i << 2), array[i]);
> }
> 
>-static u8 i915_read_indexed(u16 index_port, u16 data_port, u8 reg)
>+static u8 i915_read_indexed(struct drm_device *dev, u16 index_port,
>+			    u16 data_port, u8 reg)
> {
>-	outb(reg, index_port);
>-	return inb(data_port);
>+	vga_write(dev, reg, index_port);
>+	return vga_read(dev, data_port);
> }
> 
>-static u8 i915_read_ar(u16 st01, u8 reg, u16 palette_enable)
>+static u8 i915_read_ar(struct drm_device *dev, u16 st01, u8 reg,
>+		       u16 palette_enable)
> {
>-	inb(st01);
>-	outb(palette_enable | reg, VGA_AR_INDEX);
>-	return inb(VGA_AR_DATA_READ);
>+	vga_read(dev, st01);
>+	vga_write(dev, VGA_AR_INDEX, palette_enable | reg);
>+	return vga_read(dev, VGA_AR_DATA_READ);
> }
> 
>-static void i915_write_ar(u8 st01, u8 reg, u8 val, u16 palette_enable)
>+static void i915_write_ar(struct drm_device *dev, u8 st01, u8 reg, u8 val,
>+			  u16 palette_enable)
> {
>-	inb(st01);
>-	outb(palette_enable | reg, VGA_AR_INDEX);
>-	outb(val, VGA_AR_DATA_WRITE);
>+	vga_read(dev, st01);
>+	vga_write(dev, VGA_AR_INDEX, palette_enable | reg);
>+	vga_write(dev, VGA_AR_DATA_WRITE, val);
> }
> 
>-static void i915_write_indexed(u16 index_port, u16 data_port, u8 reg, u8 val)
>+static void i915_write_indexed(struct drm_device *dev, u16 index_port,
>+			       u16 data_port, u8 reg, u8 val)
> {
>-	outb(reg, index_port);
>-	outb(val, data_port);
>+	vga_write(dev, index_port, reg);
>+	vga_write(dev, data_port, val);
> }
> 
> static void i915_save_vga(struct drm_device *dev)
>@@ -149,15 +174,15 @@ static void i915_save_vga(struct drm_device *dev)
> 	u16 cr_index, cr_data, st01;
> 
> 	/* VGA color palette registers */
>-	dev_priv->saveDACMASK = inb(VGA_DACMASK);
>+	dev_priv->saveDACMASK = vga_read(dev, VGA_DACMASK);
> 	/* DACCRX automatically increments during read */
>-	outb(0, VGA_DACRX);
>+	vga_write(dev, VGA_DACRX, 0);
> 	/* Read 3 bytes of color data from each index */
> 	for (i = 0; i < 256 * 3; i++)
>-		dev_priv->saveDACDATA[i] = inb(VGA_DACDATA);
>+		dev_priv->saveDACDATA[i] = vga_read(dev, VGA_DACDATA);
> 
> 	/* MSR bits */
>-	dev_priv->saveMSR = inb(VGA_MSR_READ);
>+	dev_priv->saveMSR = vga_read(dev, VGA_MSR_READ);
> 	if (dev_priv->saveMSR & VGA_MSR_CGA_MODE) {
> 		cr_index = VGA_CR_INDEX_CGA;
> 		cr_data = VGA_CR_DATA_CGA;
>@@ -169,40 +194,42 @@ static void i915_save_vga(struct drm_device *dev)
> 	}
> 
> 	/* CRT controller regs */
>-	i915_write_indexed(cr_index, cr_data, 0x11,
>-			   i915_read_indexed(cr_index, cr_data, 0x11) &
>+	i915_write_indexed(dev, cr_index, cr_data, 0x11,
>+			   i915_read_indexed(dev, cr_index, cr_data, 0x11) &
> 			   (~0x80));
> 	for (i = 0; i < 0x24; i++)
> 		dev_priv->saveCR[i] =
>-			i915_read_indexed(cr_index, cr_data, i);
>+			i915_read_indexed(dev, cr_index, cr_data, i);
> 	/* Make sure we don't turn off CR group 0 writes */
> 	dev_priv->saveCR[0x11] &= ~0x80;
> 
> 	/* Attribute controller registers */
>-	inb(st01);
>-	dev_priv->saveAR_INDEX = inb(VGA_AR_INDEX);
>+	vga_read(dev, st01);
>+	dev_priv->saveAR_INDEX = vga_read(dev, VGA_AR_INDEX);
> 	for (i = 0; i < 20; i++)
>-		dev_priv->saveAR[i] = i915_read_ar(st01, i, 0);
>-	inb(st01);
>-	outb(dev_priv->saveAR_INDEX, VGA_AR_INDEX);
>-	inb(st01);
>+		dev_priv->saveAR[i] = i915_read_ar(dev, st01, i, 0);
>+	vga_read(dev, st01);
>+	vga_write(dev, VGA_AR_INDEX, dev_priv->saveAR_INDEX);
>+	vga_read(dev, st01);
> 
> 	/* Graphics controller registers */
> 	for (i = 0; i < 9; i++)
> 		dev_priv->saveGR[i] =
>-			i915_read_indexed(VGA_GR_INDEX, VGA_GR_DATA, i);
>+			i915_read_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, i);
> 
>+	vga_use_mmio = 0; /* warning: ugly hack! */
> 	dev_priv->saveGR[0x10] =
>-		i915_read_indexed(VGA_GR_INDEX, VGA_GR_DATA, 0x10);
>+		i915_read_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, 0x10);
> 	dev_priv->saveGR[0x11] =
>-		i915_read_indexed(VGA_GR_INDEX, VGA_GR_DATA, 0x11);
>+		i915_read_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, 0x11);
>+	vga_use_mmio = 1;
> 	dev_priv->saveGR[0x18] =
>-		i915_read_indexed(VGA_GR_INDEX, VGA_GR_DATA, 0x18);
>+		i915_read_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, 0x18);
> 
> 	/* Sequencer registers */
> 	for (i = 0; i < 8; i++)
> 		dev_priv->saveSR[i] =
>-			i915_read_indexed(VGA_SR_INDEX, VGA_SR_DATA, i);
>+			i915_read_indexed(dev, VGA_SR_INDEX, VGA_SR_DATA, i);
> }
> 
> static void i915_restore_vga(struct drm_device *dev)
>@@ -212,7 +239,7 @@ static void i915_restore_vga(struct drm_device *dev)
> 	u16 cr_index, cr_data, st01;
> 
> 	/* MSR bits */
>-	outb(dev_priv->saveMSR, VGA_MSR_WRITE);
>+	vga_write(dev, VGA_MSR_WRITE, dev_priv->saveMSR);
> 	if (dev_priv->saveMSR & VGA_MSR_CGA_MODE) {
> 		cr_index = VGA_CR_INDEX_CGA;
> 		cr_data = VGA_CR_DATA_CGA;
>@@ -225,41 +252,45 @@ static void i915_restore_vga(struct drm_device *dev)
> 
> 	/* Sequencer registers, don't write SR07 */
> 	for (i = 0; i < 7; i++)
>-		i915_write_indexed(VGA_SR_INDEX, VGA_SR_DATA, i,
>+		i915_write_indexed(dev, VGA_SR_INDEX, VGA_SR_DATA, i,
> 				   dev_priv->saveSR[i]);
> 
> 	/* CRT controller regs */
> 	/* Enable CR group 0 writes */
>-	i915_write_indexed(cr_index, cr_data, 0x11, dev_priv->saveCR[0x11]);
>+	i915_write_indexed(dev, cr_index, cr_data, 0x11,
>+			   dev_priv->saveCR[0x11]);
> 	for (i = 0; i < 0x24; i++)
>-		i915_write_indexed(cr_index, cr_data, i, dev_priv->saveCR[i]);
>+		i915_write_indexed(dev, cr_index, cr_data, i,
>+				   dev_priv->saveCR[i]);
> 
> 	/* Graphics controller regs */
> 	for (i = 0; i < 9; i++)
>-		i915_write_indexed(VGA_GR_INDEX, VGA_GR_DATA, i,
>+		i915_write_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, i,
> 				   dev_priv->saveGR[i]);
> 
>-	i915_write_indexed(VGA_GR_INDEX, VGA_GR_DATA, 0x10,
>+	vga_use_mmio = 0; /* warning: ugly hack! */
>+	i915_write_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, 0x10,
> 			   dev_priv->saveGR[0x10]);
>-	i915_write_indexed(VGA_GR_INDEX, VGA_GR_DATA, 0x11,
>+	i915_write_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, 0x11,
> 			   dev_priv->saveGR[0x11]);
>-	i915_write_indexed(VGA_GR_INDEX, VGA_GR_DATA, 0x18,
>+	vga_use_mmio = 1;
>+	i915_write_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, 0x18,
> 			   dev_priv->saveGR[0x18]);
> 
> 	/* Attribute controller registers */
> 	for (i = 0; i < 20; i++)
>-		i915_write_ar(st01, i, dev_priv->saveAR[i], 0);
>-	inb(st01); /* switch back to index mode */
>-	outb(dev_priv->saveAR_INDEX | 0x20, VGA_AR_INDEX);
>-	inb(st01);
>+		i915_write_ar(dev, st01, i, dev_priv->saveAR[i], 0);
>+	vga_read(dev, st01); /* switch back to index mode */
>+	vga_write(dev, VGA_AR_INDEX, dev_priv->saveAR_INDEX | 0x20);
>+	vga_read(dev, st01);
> 
> 	/* VGA color palette registers */
>-	outb(dev_priv->saveDACMASK, VGA_DACMASK);
>+	vga_write(dev, VGA_DACMASK, dev_priv->saveDACMASK);
> 	/* DACCRX automatically increments during read */
>-	outb(0, VGA_DACWX);
>+	vga_write(dev, VGA_DACWX, 0);
> 	/* Read 3 bytes of color data from each index */
> 	for (i = 0; i < 256 * 3; i++)
>-		outb(dev_priv->saveDACDATA[i], VGA_DACDATA);
>+		vga_write(dev, VGA_DACDATA, dev_priv->saveDACDATA[i]);
> 
> }
> 
>@@ -276,6 +307,7 @@ static int i915_suspend(struct drm_device *dev)
> 
> 	pci_save_state(dev->pdev);
> 	pci_read_config_byte(dev->pdev, LBB, &dev_priv->saveLBB);
>+	pci_read_config_dword(dev->pdev, MMAPA, (u32 *)&dev_priv->vga_mmio_base);
> 
> 	/* Pipe & plane A info */
> 	dev_priv->savePIPEACONF = I915_READ(PIPEACONF);
>@@ -390,6 +422,7 @@ static int i915_resume(struct drm_device *dev)
> 		return -1;
> 
> 	pci_write_config_byte(dev->pdev, LBB, dev_priv->saveLBB);
>+	pci_write_config_dword(dev->pdev, MMAPA, (u32)dev_priv->vga_mmio_base);
> 
> 	/* Pipe & plane A info */
> 	/* Prime the clock */
>@@ -427,9 +460,7 @@ static int i915_resume(struct drm_device *dev)
> 		I915_WRITE(DSPATILEOFF, dev_priv->saveDSPATILEOFF);
> 	}
> 
>-	if ((dev_priv->saveDPLL_A & DPLL_VCO_ENABLE) &&
>-	    (dev_priv->saveDPLL_A & DPLL_VGA_MODE_DIS))
>-		I915_WRITE(PIPEACONF, dev_priv->savePIPEACONF);
>+	I915_WRITE(PIPEACONF, dev_priv->savePIPEACONF);
> 
> 	i915_restore_palette(dev, PIPE_A);
> 	/* Enable the plane */
>@@ -471,10 +502,9 @@ static int i915_resume(struct drm_device *dev)
> 		I915_WRITE(DSPBTILEOFF, dev_priv->saveDSPBTILEOFF);
> 	}
> 
>-	if ((dev_priv->saveDPLL_B & DPLL_VCO_ENABLE) &&
>-	    (dev_priv->saveDPLL_B & DPLL_VGA_MODE_DIS))
>-		I915_WRITE(PIPEBCONF, dev_priv->savePIPEBCONF);
>-	i915_restore_palette(dev, PIPE_A);
>+	I915_WRITE(PIPEBCONF, dev_priv->savePIPEBCONF);
>+
>+	i915_restore_palette(dev, PIPE_B);
> 	/* Enable the plane */
> 	I915_WRITE(DSPBCNTR, dev_priv->saveDSPBCNTR);
> 	I915_WRITE(DSPBBASE, I915_READ(DSPBBASE));
>diff --git a/shared-core/i915_drv.h b/shared-core/i915_drv.h
>index 8759467..60b4771 100644
>--- a/shared-core/i915_drv.h
>+++ b/shared-core/i915_drv.h
>@@ -147,8 +147,11 @@ typedef struct drm_i915_private {
> 	drm_i915_vbl_swap_t vbl_swaps;
> 	unsigned int swaps_pending;
> 
>+	void __iomem *vga_mmio_base;
>+
> 	/* Register state */
> 	u8 saveLBB;
>+	u16 saveMGGC;
> 	u32 saveDSPACNTR;
> 	u32 saveDSPBCNTR;
> 	u32 savePIPEACONF;
>@@ -356,7 +359,8 @@ extern void intel_fini_chipset_flush_compat(struct drm_device *dev);
> extern int i915_wait_ring(struct drm_device * dev, int n, const char *caller);
> 
> /* Extended config space */
>-#define LBB 0xf4
>+#define MMAPA 0x14 /* Based of MMIO space for VGA regs */
>+#define LBB 0xf4 /* Legacy backlight control */
> 
> /* VGA stuff */
>

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Attachments on bug 14249: 13941 | 13942 | 13943 | 13944 | 13945 | 13946 | 13947 | 13993 | 13994 | 13995 | 13996 | 14182 | 14199 | 14200 | 14201 | 14203 | 14204 | 14205 | 14207 | 14208 | 14209

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