Attachment 142194 Details for Bug 108503 – dmesg output from booting drm-tip, series 50843 + drop-frontbuffer-exits patch, admgpu disabled

dmesg output from booting drm-tip, series 50843 + drop-frontbuffer-exits patch, admgpu disabled

dmesg.series-50843-plus-drop-frontbuffer-exits (text/plain), 1.01 MB, created by Ronald on 2018-10-25 08:58:22 UTC

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Creator: Ronald

Created: 2018-10-25 08:58:22 UTC

Size: 1.01 MB

patch

obsolete

>Oct 25 01:15:46 Linux version 4.19.0-rc8-drm (...) (gcc version 8.2.1 20181011 (Red Hat 8.2.1-4) (GCC)) #14 SMP Thu Oct 25 01:03:10 PDT 2018
>Oct 25 01:15:46 Command line: BOOT_IMAGE=/vmlinuz-4.19.0-rc8-drm root=/dev/mapper/luks-7d238e07-c0ca-40f5-b0b8-5272c02bd87b ro rd.luks.uuid=luks-7d238e07-c0ca-40f5-b0b8-5272c02bd87b rhgb quiet intel_iommu=on LANG=en_US.UTF-8 i915.fastboot=1 drm.debug=0x1e
>Oct 25 01:15:46 x86/fpu: Supporting XSAVE feature 0x001: 'x87 floating point registers'
>Oct 25 01:15:46 x86/fpu: Supporting XSAVE feature 0x002: 'SSE registers'
>Oct 25 01:15:46 x86/fpu: Supporting XSAVE feature 0x004: 'AVX registers'
>Oct 25 01:15:46 x86/fpu: Supporting XSAVE feature 0x008: 'MPX bounds registers'
>Oct 25 01:15:46 x86/fpu: Supporting XSAVE feature 0x010: 'MPX CSR'
>Oct 25 01:15:46 x86/fpu: xstate_offset[2]:  576, xstate_sizes[2]:  256
>Oct 25 01:15:46 x86/fpu: xstate_offset[3]:  832, xstate_sizes[3]:   64
>Oct 25 01:15:46 x86/fpu: xstate_offset[4]:  896, xstate_sizes[4]:   64
>Oct 25 01:15:46 x86/fpu: Enabled xstate features 0x1f, context size is 960 bytes, using 'compacted' format.
>Oct 25 01:15:46 BIOS-provided physical RAM map:
>Oct 25 01:15:46 BIOS-e820: [mem 0x0000000000000000-0x0000000000057fff] usable
>Oct 25 01:15:46 BIOS-e820: [mem 0x0000000000058000-0x0000000000058fff] reserved
>Oct 25 01:15:46 BIOS-e820: [mem 0x0000000000059000-0x000000000009dfff] usable
>Oct 25 01:15:46 BIOS-e820: [mem 0x000000000009e000-0x00000000000fffff] reserved
>Oct 25 01:15:46 BIOS-e820: [mem 0x0000000000100000-0x0000000074024fff] usable
>Oct 25 01:15:46 BIOS-e820: [mem 0x0000000074025000-0x0000000074376fff] reserved
>Oct 25 01:15:46 BIOS-e820: [mem 0x0000000074377000-0x0000000074e07fff] usable
>Oct 25 01:15:46 BIOS-e820: [mem 0x0000000074e08000-0x0000000074e08fff] ACPI NVS
>Oct 25 01:15:46 BIOS-e820: [mem 0x0000000074e09000-0x0000000074e52fff] reserved
>Oct 25 01:15:46 BIOS-e820: [mem 0x0000000074e53000-0x000000007507dfff] usable
>Oct 25 01:15:46 BIOS-e820: [mem 0x000000007507e000-0x000000007507efff] reserved
>Oct 25 01:15:46 BIOS-e820: [mem 0x000000007507f000-0x000000007ac7efff] usable
>Oct 25 01:15:46 BIOS-e820: [mem 0x000000007ac7f000-0x000000007af4efff] reserved
>Oct 25 01:15:46 BIOS-e820: [mem 0x000000007af4f000-0x000000007af9efff] ACPI NVS
>Oct 25 01:15:46 BIOS-e820: [mem 0x000000007af9f000-0x000000007affefff] ACPI data
>Oct 25 01:15:46 BIOS-e820: [mem 0x000000007afff000-0x000000007affffff] usable
>Oct 25 01:15:46 BIOS-e820: [mem 0x000000007b000000-0x000000007fffffff] reserved
>Oct 25 01:15:46 BIOS-e820: [mem 0x00000000e00fa000-0x00000000e00fafff] reserved
>Oct 25 01:15:46 BIOS-e820: [mem 0x00000000e00fd000-0x00000000e00fdfff] reserved
>Oct 25 01:15:46 BIOS-e820: [mem 0x00000000fe000000-0x00000000fe010fff] reserved
>Oct 25 01:15:46 BIOS-e820: [mem 0x00000000ff939000-0x00000000ff968fff] reserved
>Oct 25 01:15:46 BIOS-e820: [mem 0x0000000100000000-0x000000047effffff] usable
>Oct 25 01:15:46 NX (Execute Disable) protection: active
>Oct 25 01:15:46 e820: update [mem 0x72425018-0x72433c57] usable ==> usable
>Oct 25 01:15:46 e820: update [mem 0x72425018-0x72433c57] usable ==> usable
>Oct 25 01:15:46 e820: update [mem 0x72413018-0x724240d5] usable ==> usable
>Oct 25 01:15:46 e820: update [mem 0x72413018-0x724240d5] usable ==> usable
>Oct 25 01:15:46 extended physical RAM map:
>Oct 25 01:15:46 reserve setup_data: [mem 0x0000000000000000-0x0000000000057fff] usable
>Oct 25 01:15:46 reserve setup_data: [mem 0x0000000000058000-0x0000000000058fff] reserved
>Oct 25 01:15:46 reserve setup_data: [mem 0x0000000000059000-0x000000000009dfff] usable
>Oct 25 01:15:46 reserve setup_data: [mem 0x000000000009e000-0x00000000000fffff] reserved
>Oct 25 01:15:46 reserve setup_data: [mem 0x0000000000100000-0x0000000072413017] usable
>Oct 25 01:15:46 reserve setup_data: [mem 0x0000000072413018-0x00000000724240d5] usable
>Oct 25 01:15:46 reserve setup_data: [mem 0x00000000724240d6-0x0000000072425017] usable
>Oct 25 01:15:46 reserve setup_data: [mem 0x0000000072425018-0x0000000072433c57] usable
>Oct 25 01:15:46 reserve setup_data: [mem 0x0000000072433c58-0x0000000074024fff] usable
>Oct 25 01:15:46 reserve setup_data: [mem 0x0000000074025000-0x0000000074376fff] reserved
>Oct 25 01:15:46 reserve setup_data: [mem 0x0000000074377000-0x0000000074e07fff] usable
>Oct 25 01:15:46 reserve setup_data: [mem 0x0000000074e08000-0x0000000074e08fff] ACPI NVS
>Oct 25 01:15:46 reserve setup_data: [mem 0x0000000074e09000-0x0000000074e52fff] reserved
>Oct 25 01:15:46 reserve setup_data: [mem 0x0000000074e53000-0x000000007507dfff] usable
>Oct 25 01:15:46 reserve setup_data: [mem 0x000000007507e000-0x000000007507efff] reserved
>Oct 25 01:15:46 reserve setup_data: [mem 0x000000007507f000-0x000000007ac7efff] usable
>Oct 25 01:15:46 reserve setup_data: [mem 0x000000007ac7f000-0x000000007af4efff] reserved
>Oct 25 01:15:46 reserve setup_data: [mem 0x000000007af4f000-0x000000007af9efff] ACPI NVS
>Oct 25 01:15:46 reserve setup_data: [mem 0x000000007af9f000-0x000000007affefff] ACPI data
>Oct 25 01:15:46 reserve setup_data: [mem 0x000000007afff000-0x000000007affffff] usable
>Oct 25 01:15:46 reserve setup_data: [mem 0x000000007b000000-0x000000007fffffff] reserved
>Oct 25 01:15:46 reserve setup_data: [mem 0x00000000e00fa000-0x00000000e00fafff] reserved
>Oct 25 01:15:46 reserve setup_data: [mem 0x00000000e00fd000-0x00000000e00fdfff] reserved
>Oct 25 01:15:46 reserve setup_data: [mem 0x00000000fe000000-0x00000000fe010fff] reserved
>Oct 25 01:15:46 reserve setup_data: [mem 0x00000000ff939000-0x00000000ff968fff] reserved
>Oct 25 01:15:46 reserve setup_data: [mem 0x0000000100000000-0x000000047effffff] usable
>Oct 25 01:15:46 efi: EFI v2.40 by Apple
>Oct 25 01:15:46 efi:  ACPI=0x7affe000  ACPI 2.0=0x7affe014  SMBIOS=0x7aeff000  SMBIOS 3.0=0x7aefd000 
>Oct 25 01:15:46 SMBIOS 3.0.0 present.
>Oct 25 01:15:46 DMI: Apple Inc. MacBookPro13,3/Mac-A5C67F76ED83108C, BIOS MBP133.88Z.0247.B00.1806261159 06/26/2018
>Oct 25 01:15:46 tsc: Detected 2900.000 MHz processor
>Oct 25 01:15:46 tsc: Detected 2904.000 MHz TSC
>Oct 25 01:15:46 e820: update [mem 0x00000000-0x00000fff] usable ==> reserved
>Oct 25 01:15:46 e820: remove [mem 0x000a0000-0x000fffff] usable
>Oct 25 01:15:46 last_pfn = 0x47f000 max_arch_pfn = 0x400000000
>Oct 25 01:15:46 MTRR default type: write-back
>Oct 25 01:15:46 MTRR fixed ranges enabled:
>Oct 25 01:15:46   00000-9FFFF write-back
>Oct 25 01:15:46   A0000-BFFFF uncachable
>Oct 25 01:15:46   C0000-DFFFF write-protect
>Oct 25 01:15:46   E0000-FFFFF uncachable
>Oct 25 01:15:46 MTRR variable ranges enabled:
>Oct 25 01:15:46   0 base 0080000000 mask 7F80000000 uncachable
>Oct 25 01:15:46   1 base 007C000000 mask 7FFC000000 uncachable
>Oct 25 01:15:46   2 base 007B000000 mask 7FFF000000 uncachable
>Oct 25 01:15:46   3 base 4000000000 mask 4000000000 uncachable
>Oct 25 01:15:46   4 disabled
>Oct 25 01:15:46   5 disabled
>Oct 25 01:15:46   6 disabled
>Oct 25 01:15:46   7 disabled
>Oct 25 01:15:46   8 disabled
>Oct 25 01:15:46   9 disabled
>Oct 25 01:15:46 x86/PAT: Configuration [0-7]: WB  WC  UC- UC  WB  WP  UC- WT  
>Oct 25 01:15:46 last_pfn = 0x7b000 max_arch_pfn = 0x400000000
>Oct 25 01:15:46 Base memory trampoline at [(____ptrval____)] 98000 size 24576
>Oct 25 01:15:46 Using GB pages for direct mapping
>Oct 25 01:15:46 BRK [0x3a5001000, 0x3a5001fff] PGTABLE
>Oct 25 01:15:46 BRK [0x3a5002000, 0x3a5002fff] PGTABLE
>Oct 25 01:15:46 BRK [0x3a5003000, 0x3a5003fff] PGTABLE
>Oct 25 01:15:46 BRK [0x3a5004000, 0x3a5004fff] PGTABLE
>Oct 25 01:15:46 BRK [0x3a5005000, 0x3a5005fff] PGTABLE
>Oct 25 01:15:46 BRK [0x3a5006000, 0x3a5006fff] PGTABLE
>Oct 25 01:15:46 BRK [0x3a5007000, 0x3a5007fff] PGTABLE
>Oct 25 01:15:46 BRK [0x3a5008000, 0x3a5008fff] PGTABLE
>Oct 25 01:15:46 BRK [0x3a5009000, 0x3a5009fff] PGTABLE
>Oct 25 01:15:46 BRK [0x3a500a000, 0x3a500afff] PGTABLE
>Oct 25 01:15:46 BRK [0x3a500b000, 0x3a500bfff] PGTABLE
>Oct 25 01:15:46 BRK [0x3a500c000, 0x3a500cfff] PGTABLE
>Oct 25 01:15:46 Secure boot disabled
>Oct 25 01:15:46 RAMDISK: [mem 0x3bed9000-0x3cfd1fff]
>Oct 25 01:15:46 ACPI: Early table checksum verification disabled
>Oct 25 01:15:46 ACPI: RSDP 0x000000007AFFE014 000024 (v02 APPLE )
>Oct 25 01:15:46 ACPI: XSDT 0x000000007AFC6188 0000D4 (v01 APPLE  Apple00  00000000      01000013)
>Oct 25 01:15:46 ACPI: FACP 0x000000007AFF8000 0000F4 (v05 APPLE  Apple00  00000000 Loki 0000005F)
>Oct 25 01:15:46 ACPI: DSDT 0x000000007AFEB000 00869F (v02 APPLE  MacBookP 00150001 INTL 20140424)
>Oct 25 01:15:46 ACPI: FACS 0x000000007AF9B000 000040
>Oct 25 01:15:46 ACPI: UEFI 0x000000007AF9D000 000042 (v01 INTEL  EDK2     00000002      01000013)
>Oct 25 01:15:46 ACPI: ECDT 0x000000007AFFA000 000053 (v01 APPLE  Apple00  00000001 Loki 0000005F)
>Oct 25 01:15:46 ACPI: HPET 0x000000007AFF7000 000038 (v01 APPLE  Apple00  00000001 Loki 0000005F)
>Oct 25 01:15:46 ACPI: APIC 0x000000007AFF6000 0000BC (v02 APPLE  Apple00  00000001 Loki 0000005F)
>Oct 25 01:15:46 ACPI: MCFG 0x000000007AFF5000 00003C (v01 APPLE  Apple00  00000001 Loki 0000005F)
>Oct 25 01:15:46 ACPI: SBST 0x000000007AFF4000 000030 (v01 APPLE  Apple00  00000001 Loki 0000005F)
>Oct 25 01:15:46 ACPI: SSDT 0x000000007AFEA000 000024 (v01 APPLE  SmcDppt  00001000 INTL 20140424)
>Oct 25 01:15:46 ACPI: SSDT 0x000000007AFE9000 0007FD (v02 APPLE  PEG0GFX0 00001000 INTL 20140424)
>Oct 25 01:15:46 ACPI: SSDT 0x000000007AFE8000 000024 (v01 APPLE  PEG0SSD0 00001000 INTL 20140424)
>Oct 25 01:15:46 ACPI: SSDT 0x000000007AFE5000 000031 (v01 APPLE  SsdtS3   00001000 INTL 20140424)
>Oct 25 01:15:46 ACPI: SSDT 0x000000007AFE4000 0000DD (v01 APPLE  SataAhci 00001000 INTL 20140424)
>Oct 25 01:15:46 ACPI: SSDT 0x000000007AFE3000 0000B8 (v01 APPLE  Sdxc     00001000 INTL 20140424)
>Oct 25 01:15:46 ACPI: SSDT 0x000000007AFCE000 00996E (v02 APPLE  TbtPEG12 00001000 INTL 20140424)
>Oct 25 01:15:46 ACPI: SSDT 0x000000007AFCD000 000C32 (v02 APPLE  Xhci     00001000 INTL 20140424)
>Oct 25 01:15:46 ACPI: SSDT 0x000000007AFCC000 000612 (v02 PmRef  Cpu0Ist  00003000 INTL 20140424)
>Oct 25 01:15:46 ACPI: SSDT 0x000000007AFCB000 0005AA (v02 PmRef  ApIst    00003000 INTL 20140424)
>Oct 25 01:15:46 ACPI: SSDT 0x000000007AFCA000 000295 (v02 PmRef  Cpu0Cst  00003001 INTL 20140424)
>Oct 25 01:15:46 ACPI: SSDT 0x000000007AFC9000 000119 (v02 PmRef  ApCst    00003000 INTL 20140424)
>Oct 25 01:15:46 ACPI: SSDT 0x000000007AFC8000 000EEF (v02 CpuRef CpuSsdt  00003000 INTL 20140424)
>Oct 25 01:15:46 ACPI: DMAR 0x000000007AFC7000 000160 (v01 APPLE  SKL      00000001 INTL 00000001)
>Oct 25 01:15:46 ACPI: VFCT 0x000000007AFB7000 00EC84 (v01 APPLE  Apple00  00000001 AMD  31504F47)
>Oct 25 01:15:46 ACPI: DMI detected to setup _OSI("Darwin"): Apple hardware
>Oct 25 01:15:46 ACPI: Local APIC address 0xfee00000
>Oct 25 01:15:46 No NUMA configuration found
>Oct 25 01:15:46 Faking a node at [mem 0x0000000000000000-0x000000047effffff]
>Oct 25 01:15:46 NODE_DATA(0) allocated [mem 0x47efd5000-0x47effffff]
>Oct 25 01:15:46 Zone ranges:
>Oct 25 01:15:46   DMA      [mem 0x0000000000001000-0x0000000000ffffff]
>Oct 25 01:15:46   DMA32    [mem 0x0000000001000000-0x00000000ffffffff]
>Oct 25 01:15:46   Normal   [mem 0x0000000100000000-0x000000047effffff]
>Oct 25 01:15:46   Device   empty
>Oct 25 01:15:46 Movable zone start for each node
>Oct 25 01:15:46 Early memory node ranges
>Oct 25 01:15:46   node   0: [mem 0x0000000000001000-0x0000000000057fff]
>Oct 25 01:15:46   node   0: [mem 0x0000000000059000-0x000000000009dfff]
>Oct 25 01:15:46   node   0: [mem 0x0000000000100000-0x0000000074024fff]
>Oct 25 01:15:46   node   0: [mem 0x0000000074377000-0x0000000074e07fff]
>Oct 25 01:15:46   node   0: [mem 0x0000000074e53000-0x000000007507dfff]
>Oct 25 01:15:46   node   0: [mem 0x000000007507f000-0x000000007ac7efff]
>Oct 25 01:15:46   node   0: [mem 0x000000007afff000-0x000000007affffff]
>Oct 25 01:15:46   node   0: [mem 0x0000000100000000-0x000000047effffff]
>Oct 25 01:15:46 Reserved but unavailable: 22402 pages
>Oct 25 01:15:46 Initmem setup node 0 [mem 0x0000000000001000-0x000000047effffff]
>Oct 25 01:15:46 On node 0 totalpages: 4167806
>Oct 25 01:15:46   DMA zone: 64 pages used for memmap
>Oct 25 01:15:46   DMA zone: 21 pages reserved
>Oct 25 01:15:46   DMA zone: 3996 pages, LIFO batch:0
>Oct 25 01:15:46   DMA32 zone: 7780 pages used for memmap
>Oct 25 01:15:46   DMA32 zone: 497890 pages, LIFO batch:63
>Oct 25 01:15:46   Normal zone: 57280 pages used for memmap
>Oct 25 01:15:46   Normal zone: 3665920 pages, LIFO batch:63
>Oct 25 01:15:46 Reserving Intel graphics memory at [mem 0x7c000000-0x7fffffff]
>Oct 25 01:15:46 ACPI: PM-Timer IO Port: 0x1808
>Oct 25 01:15:46 ACPI: Local APIC address 0xfee00000
>Oct 25 01:15:46 ACPI: LAPIC_NMI (acpi_id[0x01] high edge lint[0x1])
>Oct 25 01:15:46 ACPI: LAPIC_NMI (acpi_id[0x02] high edge lint[0x1])
>Oct 25 01:15:46 ACPI: LAPIC_NMI (acpi_id[0x03] high edge lint[0x1])
>Oct 25 01:15:46 ACPI: LAPIC_NMI (acpi_id[0x04] high edge lint[0x1])
>Oct 25 01:15:46 ACPI: LAPIC_NMI (acpi_id[0x05] high edge lint[0x1])
>Oct 25 01:15:46 ACPI: LAPIC_NMI (acpi_id[0x06] high edge lint[0x1])
>Oct 25 01:15:46 ACPI: LAPIC_NMI (acpi_id[0x07] high edge lint[0x1])
>Oct 25 01:15:46 ACPI: LAPIC_NMI (acpi_id[0x08] high edge lint[0x1])
>Oct 25 01:15:46 IOAPIC[0]: apic_id 2, version 32, address 0xfec00000, GSI 0-23
>Oct 25 01:15:46 ACPI: INT_SRC_OVR (bus 0 bus_irq 0 global_irq 2 dfl dfl)
>Oct 25 01:15:46 ACPI: INT_SRC_OVR (bus 0 bus_irq 9 global_irq 9 high level)
>Oct 25 01:15:46 ACPI: IRQ0 used by override.
>Oct 25 01:15:46 ACPI: IRQ9 used by override.
>Oct 25 01:15:46 Using ACPI (MADT) for SMP configuration information
>Oct 25 01:15:46 ACPI: HPET id: 0x8086a201 base: 0xfed00000
>Oct 25 01:15:46 smpboot: Allowing 8 CPUs, 0 hotplug CPUs
>Oct 25 01:15:46 PM: Registered nosave memory: [mem 0x00000000-0x00000fff]
>Oct 25 01:15:46 PM: Registered nosave memory: [mem 0x00058000-0x00058fff]
>Oct 25 01:15:46 PM: Registered nosave memory: [mem 0x0009e000-0x000fffff]
>Oct 25 01:15:46 PM: Registered nosave memory: [mem 0x72413000-0x72413fff]
>Oct 25 01:15:46 PM: Registered nosave memory: [mem 0x72424000-0x72424fff]
>Oct 25 01:15:46 PM: Registered nosave memory: [mem 0x72425000-0x72425fff]
>Oct 25 01:15:46 PM: Registered nosave memory: [mem 0x72433000-0x72433fff]
>Oct 25 01:15:46 PM: Registered nosave memory: [mem 0x74025000-0x74376fff]
>Oct 25 01:15:46 PM: Registered nosave memory: [mem 0x74e08000-0x74e08fff]
>Oct 25 01:15:46 PM: Registered nosave memory: [mem 0x74e09000-0x74e52fff]
>Oct 25 01:15:46 PM: Registered nosave memory: [mem 0x7507e000-0x7507efff]
>Oct 25 01:15:46 PM: Registered nosave memory: [mem 0x7ac7f000-0x7af4efff]
>Oct 25 01:15:46 PM: Registered nosave memory: [mem 0x7af4f000-0x7af9efff]
>Oct 25 01:15:46 PM: Registered nosave memory: [mem 0x7af9f000-0x7affefff]
>Oct 25 01:15:46 PM: Registered nosave memory: [mem 0x7b000000-0x7fffffff]
>Oct 25 01:15:46 PM: Registered nosave memory: [mem 0x80000000-0xe00f9fff]
>Oct 25 01:15:46 PM: Registered nosave memory: [mem 0xe00fa000-0xe00fafff]
>Oct 25 01:15:46 PM: Registered nosave memory: [mem 0xe00fb000-0xe00fcfff]
>Oct 25 01:15:46 PM: Registered nosave memory: [mem 0xe00fd000-0xe00fdfff]
>Oct 25 01:15:46 PM: Registered nosave memory: [mem 0xe00fe000-0xfdffffff]
>Oct 25 01:15:46 PM: Registered nosave memory: [mem 0xfe000000-0xfe010fff]
>Oct 25 01:15:46 PM: Registered nosave memory: [mem 0xfe011000-0xff938fff]
>Oct 25 01:15:46 PM: Registered nosave memory: [mem 0xff939000-0xff968fff]
>Oct 25 01:15:46 PM: Registered nosave memory: [mem 0xff969000-0xffffffff]
>Oct 25 01:15:46 [mem 0x80000000-0xe00f9fff] available for PCI devices
>Oct 25 01:15:46 Booting paravirtualized kernel on bare hardware
>Oct 25 01:15:46 clocksource: refined-jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 1910969940391419 ns
>Oct 25 01:15:46 random: get_random_bytes called from start_kernel+0x98/0x54e with crng_init=0
>Oct 25 01:15:46 setup_percpu: NR_CPUS:64 nr_cpumask_bits:64 nr_cpu_ids:8 nr_node_ids:1
>Oct 25 01:15:46 percpu: Embedded 494 pages/cpu @(____ptrval____) s1982680 r8192 d32552 u2097152
>Oct 25 01:15:46 pcpu-alloc: s1982680 r8192 d32552 u2097152 alloc=1*2097152
>Oct 25 01:15:46 pcpu-alloc: [0] 0 [0] 1 [0] 2 [0] 3 [0] 4 [0] 5 [0] 6 [0] 7 
>Oct 25 01:15:46 Built 1 zonelists, mobility grouping on.  Total pages: 4102661
>Oct 25 01:15:46 Policy zone: Normal
>Oct 25 01:15:46 Kernel command line: BOOT_IMAGE=/vmlinuz-4.19.0-rc8-drm root=/dev/mapper/luks-7d238e07-c0ca-40f5-b0b8-5272c02bd87b ro rd.luks.uuid=luks-7d238e07-c0ca-40f5-b0b8-5272c02bd87b rhgb quiet intel_iommu=on LANG=en_US.UTF-8 i915.fastboot=1 drm.debug=0x1e
>Oct 25 01:15:46 DMAR: IOMMU enabled
>Oct 25 01:15:46 Memory: 16142464K/16671224K available (14348K kernel code, 1739K rwdata, 4156K rodata, 3936K init, 17016K bss, 528760K reserved, 0K cma-reserved)
>Oct 25 01:15:46 SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
>Oct 25 01:15:46 Kernel/User page tables isolation: enabled
>Oct 25 01:15:46 ftrace: allocating 38572 entries in 151 pages
>Oct 25 01:15:46 Running RCU self tests
>Oct 25 01:15:46 rcu: Hierarchical RCU implementation.
>Oct 25 01:15:46 rcu:         RCU lockdep checking is enabled.
>Oct 25 01:15:46 rcu:         RCU restricting CPUs from NR_CPUS=64 to nr_cpu_ids=8.
>Oct 25 01:15:46         Tasks RCU enabled.
>Oct 25 01:15:46 rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
>Oct 25 01:15:46 NR_IRQS: 4352, nr_irqs: 488, preallocated irqs: 16
>Oct 25 01:15:46 rcu:         Offload RCU callbacks from CPUs: (none).
>Oct 25 01:15:46 Console: colour dummy device 80x25
>Oct 25 01:15:46 console [tty0] enabled
>Oct 25 01:15:46 Lock dependency validator: Copyright (c) 2006 Red Hat, Inc., Ingo Molnar
>Oct 25 01:15:46 ... MAX_LOCKDEP_SUBCLASSES:  8
>Oct 25 01:15:46 ... MAX_LOCK_DEPTH:          48
>Oct 25 01:15:46 ... MAX_LOCKDEP_KEYS:        8191
>Oct 25 01:15:46 ... CLASSHASH_SIZE:          4096
>Oct 25 01:15:46 ... MAX_LOCKDEP_ENTRIES:     32768
>Oct 25 01:15:46 ... MAX_LOCKDEP_CHAINS:      131072
>Oct 25 01:15:46 ... CHAINHASH_SIZE:          65536
>Oct 25 01:15:46  memory used by lock dependency info: 10463 kB
>Oct 25 01:15:46  per task-struct memory footprint: 2688 bytes
>Oct 25 01:15:46 ACPI: Core revision 20180810
>Oct 25 01:15:46 clocksource: hpet: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 79635855245 ns
>Oct 25 01:15:46 hpet clockevent registered
>Oct 25 01:15:46 APIC: Switch to symmetric I/O mode setup
>Oct 25 01:15:46 DMAR: Host address width 39
>Oct 25 01:15:46 DMAR: DRHD base: 0x000000fed90000 flags: 0x0
>Oct 25 01:15:46 DMAR: dmar0: reg_base_addr fed90000 ver 1:0 cap 1c0000c40660462 ecap 7e3ff0501e
>Oct 25 01:15:46 DMAR: DRHD base: 0x000000fed91000 flags: 0x1
>Oct 25 01:15:46 DMAR: dmar1: reg_base_addr fed91000 ver 1:0 cap d2008c40660462 ecap f050da
>Oct 25 01:15:46 DMAR: RMRR base: 0x0000007b800000 end: 0x0000007fffffff
>Oct 25 01:15:46 DMAR: ANDD device: 1 name: \_SB.PCI0.I2C0
>Oct 25 01:15:46 DMAR: ANDD device: 7 name: \_SB.PCI0.SPI0
>Oct 25 01:15:46 DMAR: ANDD device: 8 name: \_SB.PCI0.SPI1
>Oct 25 01:15:46 DMAR: ANDD device: 9 name: \_SB.PCI0.UA00
>Oct 25 01:15:46 DMAR: ANDD device: a name: \_SB.PCI0.UA01
>Oct 25 01:15:46 DMAR: ANDD device: b name: \_SB.PCI0.UA02
>Oct 25 01:15:46 DMAR-IR: IOAPIC id 2 under DRHD base  0xfed91000 IOMMU 1
>Oct 25 01:15:46 DMAR-IR: HPET id 0 under DRHD base 0xfed91000
>Oct 25 01:15:46 DMAR-IR: Queued invalidation will be enabled to support x2apic and Intr-remapping.
>Oct 25 01:15:46 DMAR-IR: Enabled IRQ remapping in x2apic mode
>Oct 25 01:15:46 x2apic enabled
>Oct 25 01:15:46 Switched APIC routing to cluster x2apic.
>Oct 25 01:15:46 ..TIMER: vector=0x30 apic1=0 pin1=2 apic2=-1 pin2=-1
>Oct 25 01:15:46 clocksource: tsc-early: mask: 0xffffffffffffffff max_cycles: 0x29dc05e54fc, max_idle_ns: 440795291716 ns
>Oct 25 01:15:46 Calibrating delay loop (skipped), value calculated using timer frequency.. 5808.00 BogoMIPS (lpj=2904000)
>Oct 25 01:15:46 pid_max: default: 32768 minimum: 301
>Oct 25 01:15:46 Security Framework initialized
>Oct 25 01:15:46 Yama: becoming mindful.
>Oct 25 01:15:46 SELinux:  Initializing.
>Oct 25 01:15:46 Dentry cache hash table entries: 2097152 (order: 12, 16777216 bytes)
>Oct 25 01:15:46 Inode-cache hash table entries: 1048576 (order: 11, 8388608 bytes)
>Oct 25 01:15:46 Mount-cache hash table entries: 32768 (order: 6, 262144 bytes)
>Oct 25 01:15:46 Mountpoint-cache hash table entries: 32768 (order: 6, 262144 bytes)
>Oct 25 01:15:46 ENERGY_PERF_BIAS: Set to 'normal', was 'performance'
>Oct 25 01:15:46 ENERGY_PERF_BIAS: View and update with x86_energy_perf_policy(8)
>Oct 25 01:15:46 mce: CPU supports 10 MCE banks
>Oct 25 01:15:46 CPU0: Thermal monitoring enabled (TM1)
>Oct 25 01:15:46 process: using mwait in idle threads
>Oct 25 01:15:46 Last level iTLB entries: 4KB 64, 2MB 8, 4MB 8
>Oct 25 01:15:46 Last level dTLB entries: 4KB 64, 2MB 0, 4MB 0, 1GB 4
>Oct 25 01:15:46 Spectre V2 : Mitigation: Full generic retpoline
>Oct 25 01:15:46 Spectre V2 : Spectre v2 / SpectreRSB mitigation: Filling RSB on context switch
>Oct 25 01:15:46 Spectre V2 : Spectre v2 mitigation: Enabling Indirect Branch Prediction Barrier
>Oct 25 01:15:46 Spectre V2 : Enabling Restricted Speculation for firmware calls
>Oct 25 01:15:46 Speculative Store Bypass: Mitigation: Speculative Store Bypass disabled via prctl and seccomp
>Oct 25 01:15:46 Freeing SMP alternatives memory: 36K
>Oct 25 01:15:46 TSC deadline timer enabled
>Oct 25 01:15:46 smpboot: CPU0: Intel(R) Core(TM) i7-6920HQ CPU @ 2.90GHz (family: 0x6, model: 0x5e, stepping: 0x3)
>Oct 25 01:15:46 Performance Events: PEBS fmt3+, Skylake events, 32-deep LBR, full-width counters, Intel PMU driver.
>Oct 25 01:15:46 ... version:                4
>Oct 25 01:15:46 ... bit width:              48
>Oct 25 01:15:46 ... generic registers:      4
>Oct 25 01:15:46 ... value mask:             0000ffffffffffff
>Oct 25 01:15:46 ... max period:             00007fffffffffff
>Oct 25 01:15:46 ... fixed-purpose events:   3
>Oct 25 01:15:46 ... event mask:             000000070000000f
>Oct 25 01:15:46 rcu: Hierarchical SRCU implementation.
>Oct 25 01:15:46 NMI watchdog: Enabled. Permanently consumes one hw-PMU counter.
>Oct 25 01:15:46 smp: Bringing up secondary CPUs ...
>Oct 25 01:15:46 x86: Booting SMP configuration:
>Oct 25 01:15:46 .... node  #0, CPUs:      #1 #2 #3 #4 #5 #6 #7
>Oct 25 01:15:46 smp: Brought up 1 node, 8 CPUs
>Oct 25 01:15:46 smpboot: Max logical packages: 1
>Oct 25 01:15:46 smpboot: Total of 8 processors activated (46464.00 BogoMIPS)
>Oct 25 01:15:46 devtmpfs: initialized
>Oct 25 01:15:46 x86/mm: Memory block size: 128MB
>Oct 25 01:15:46 PM: Registering ACPI NVS region [mem 0x74e08000-0x74e08fff] (4096 bytes)
>Oct 25 01:15:46 PM: Registering ACPI NVS region [mem 0x7af4f000-0x7af9efff] (327680 bytes)
>Oct 25 01:15:46 clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 1911260446275000 ns
>Oct 25 01:15:46 futex hash table entries: 2048 (order: 6, 262144 bytes)
>Oct 25 01:15:46 pinctrl core: initialized pinctrl subsystem
>Oct 25 01:15:46 RTC time:  8:15:43, date: 10/25/18
>Oct 25 01:15:46 NET: Registered protocol family 16
>Oct 25 01:15:46 audit: initializing netlink subsys (disabled)
>Oct 25 01:15:46 audit: type=2000 audit(1540455343.042:1): state=initialized audit_enabled=0 res=1
>Oct 25 01:15:46 cpuidle: using governor menu
>Oct 25 01:15:46 ACPI FADT declares the system doesn't support PCIe ASPM, so disable it
>Oct 25 01:15:46 ACPI: bus type PCI registered
>Oct 25 01:15:46 acpiphp: ACPI Hot Plug PCI Controller Driver version: 0.5
>Oct 25 01:15:46 PCI: MMCONFIG for domain 0000 [bus 00-ff] at [mem 0xe0000000-0xefffffff] (base 0xe0000000)
>Oct 25 01:15:46 PCI: not using MMCONFIG
>Oct 25 01:15:46 PCI: Using configuration type 1 for base access
>Oct 25 01:15:46 HugeTLB registered 1.00 GiB page size, pre-allocated 0 pages
>Oct 25 01:15:46 HugeTLB registered 2.00 MiB page size, pre-allocated 0 pages
>Oct 25 01:15:46 cryptd: max_cpu_qlen set to 1000
>Oct 25 01:15:46 ACPI: Disabled all _OSI OS vendors
>Oct 25 01:15:46 ACPI: Added _OSI(Module Device)
>Oct 25 01:15:46 ACPI: Added _OSI(Processor Device)
>Oct 25 01:15:46 ACPI: Added _OSI(3.0 _SCP Extensions)
>Oct 25 01:15:46 ACPI: Added _OSI(Processor Aggregator Device)
>Oct 25 01:15:46 ACPI: Added _OSI(Linux-Dell-Video)
>Oct 25 01:15:46 ACPI: Added _OSI(Linux-Lenovo-NV-HDMI-Audio)
>Oct 25 01:15:46 ACPI: Added _OSI(Darwin)
>Oct 25 01:15:46 ACPI: EC: EC started
>Oct 25 01:15:46 ACPI: EC: interrupt blocked
>Oct 25 01:15:46 ACPI: \: Used as first EC
>Oct 25 01:15:46 ACPI: \: GPE=0x7, EC_CMD/EC_SC=0x66, EC_DATA=0x62
>Oct 25 01:15:46 ACPI: \: Used as boot ECDT EC to handle transactions
>Oct 25 01:15:46 ACPI: 14 ACPI AML tables successfully acquired and loaded
>Oct 25 01:15:46 ACPI: BIOS _OSI(Darwin) query honored via DMI
>Oct 25 01:15:46 ACPI: [Firmware Bug]: BIOS _OSI(Linux) query ignored
>Oct 25 01:15:46 ACPI: Dynamic OEM Table Load:
>Oct 25 01:15:46 ACPI Error: AE_ALREADY_EXISTS, SSDT 0xFFFF9DF56B169800 Table is already loaded (20180810/tbdata-528)
>Oct 25 01:15:46 ACPI Error: Method parse/execution failed \_PR.CPU0.GCAP, AE_ALREADY_EXISTS (20180810/psparse-516)
>Oct 25 01:15:46 ACPI Error: Method parse/execution failed \_PR.CPU0._OSC, AE_ALREADY_EXISTS (20180810/psparse-516)
>Oct 25 01:15:46 ACPI: Marking method _OSC as Serialized because of AE_ALREADY_EXISTS error
>Oct 25 01:15:46 ACPI BIOS Error (bug): Could not resolve [\_SB.OSCP], AE_NOT_FOUND (20180810/psargs-330)
>Oct 25 01:15:46 ACPI Error: Method parse/execution failed \_PR.CPU1.GCAP, AE_NOT_FOUND (20180810/psparse-516)
>Oct 25 01:15:46 ACPI Error: Method parse/execution failed \_PR.CPU1._OSC, AE_NOT_FOUND (20180810/psparse-516)
>Oct 25 01:15:46 ACPI BIOS Error (bug): Could not resolve [\_SB.OSCP], AE_NOT_FOUND (20180810/psargs-330)
>Oct 25 01:15:46 ACPI Error: Method parse/execution failed \_PR.CPU2.GCAP, AE_NOT_FOUND (20180810/psparse-516)
>Oct 25 01:15:46 ACPI Error: Method parse/execution failed \_PR.CPU2._OSC, AE_NOT_FOUND (20180810/psparse-516)
>Oct 25 01:15:46 ACPI BIOS Error (bug): Could not resolve [\_SB.OSCP], AE_NOT_FOUND (20180810/psargs-330)
>Oct 25 01:15:46 ACPI Error: Method parse/execution failed \_PR.CPU3.GCAP, AE_NOT_FOUND (20180810/psparse-516)
>Oct 25 01:15:46 ACPI Error: Method parse/execution failed \_PR.CPU3._OSC, AE_NOT_FOUND (20180810/psparse-516)
>Oct 25 01:15:46 ACPI BIOS Error (bug): Could not resolve [\_SB.OSCP], AE_NOT_FOUND (20180810/psargs-330)
>Oct 25 01:15:46 ACPI Error: Method parse/execution failed \_PR.CPU4.GCAP, AE_NOT_FOUND (20180810/psparse-516)
>Oct 25 01:15:46 ACPI Error: Method parse/execution failed \_PR.CPU4._OSC, AE_NOT_FOUND (20180810/psparse-516)
>Oct 25 01:15:46 ACPI BIOS Error (bug): Could not resolve [\_SB.OSCP], AE_NOT_FOUND (20180810/psargs-330)
>Oct 25 01:15:46 ACPI Error: Method parse/execution failed \_PR.CPU5.GCAP, AE_NOT_FOUND (20180810/psparse-516)
>Oct 25 01:15:46 ACPI Error: Method parse/execution failed \_PR.CPU5._OSC, AE_NOT_FOUND (20180810/psparse-516)
>Oct 25 01:15:46 ACPI BIOS Error (bug): Could not resolve [\_SB.OSCP], AE_NOT_FOUND (20180810/psargs-330)
>Oct 25 01:15:46 ACPI Error: Method parse/execution failed \_PR.CPU6.GCAP, AE_NOT_FOUND (20180810/psparse-516)
>Oct 25 01:15:46 ACPI Error: Method parse/execution failed \_PR.CPU6._OSC, AE_NOT_FOUND (20180810/psparse-516)
>Oct 25 01:15:46 ACPI BIOS Error (bug): Could not resolve [\_SB.OSCP], AE_NOT_FOUND (20180810/psargs-330)
>Oct 25 01:15:46 ACPI Error: Method parse/execution failed \_PR.CPU7.GCAP, AE_NOT_FOUND (20180810/psparse-516)
>Oct 25 01:15:46 ACPI Error: Method parse/execution failed \_PR.CPU7._OSC, AE_NOT_FOUND (20180810/psparse-516)
>Oct 25 01:15:46 ACPI: Dynamic OEM Table Load:
>Oct 25 01:15:46 ACPI Error: AE_ALREADY_EXISTS, SSDT 0xFFFF9DF56B7C9400 Table is already loaded (20180810/tbdata-528)
>Oct 25 01:15:46 ACPI Error: Method parse/execution failed \_PR.CPU0.GCAP, AE_ALREADY_EXISTS (20180810/psparse-516)
>Oct 25 01:15:46 ACPI Error: Method parse/execution failed \_PR.CPU0._PDC, AE_ALREADY_EXISTS (20180810/psparse-516)
>Oct 25 01:15:46 ACPI: Marking method _PDC as Serialized because of AE_ALREADY_EXISTS error
>Oct 25 01:15:46 ACPI: Dynamic OEM Table Load:
>Oct 25 01:15:46 ACPI Error: AE_ALREADY_EXISTS, SSDT 0xFFFF9DF56B169800 Table is already loaded (20180810/tbdata-528)
>Oct 25 01:15:46 ACPI Error: Method parse/execution failed \_PR.CPU1.APPT, AE_ALREADY_EXISTS (20180810/psparse-516)
>Oct 25 01:15:46 ACPI Error: Method parse/execution failed \_PR.CPU1.GCAP, AE_ALREADY_EXISTS (20180810/psparse-516)
>Oct 25 01:15:46 ACPI Error: Method parse/execution failed \_PR.CPU1._PDC, AE_ALREADY_EXISTS (20180810/psparse-516)
>Oct 25 01:15:46 ACPI: Marking method _PDC as Serialized because of AE_ALREADY_EXISTS error
>Oct 25 01:15:46 ACPI BIOS Error (bug): Could not resolve [\_SB.OSCP], AE_NOT_FOUND (20180810/psargs-330)
>Oct 25 01:15:46 ACPI Error: Method parse/execution failed \_PR.CPU2.GCAP, AE_NOT_FOUND (20180810/psparse-516)
>Oct 25 01:15:46 ACPI Error: Method parse/execution failed \_PR.CPU2._PDC, AE_NOT_FOUND (20180810/psparse-516)
>Oct 25 01:15:46 ACPI BIOS Error (bug): Could not resolve [\_SB.OSCP], AE_NOT_FOUND (20180810/psargs-330)
>Oct 25 01:15:46 ACPI Error: Method parse/execution failed \_PR.CPU3.GCAP, AE_NOT_FOUND (20180810/psparse-516)
>Oct 25 01:15:46 ACPI Error: Method parse/execution failed \_PR.CPU3._PDC, AE_NOT_FOUND (20180810/psparse-516)
>Oct 25 01:15:46 ACPI BIOS Error (bug): Could not resolve [\_SB.OSCP], AE_NOT_FOUND (20180810/psargs-330)
>Oct 25 01:15:46 ACPI Error: Method parse/execution failed \_PR.CPU4.GCAP, AE_NOT_FOUND (20180810/psparse-516)
>Oct 25 01:15:46 ACPI Error: Method parse/execution failed \_PR.CPU4._PDC, AE_NOT_FOUND (20180810/psparse-516)
>Oct 25 01:15:46 ACPI BIOS Error (bug): Could not resolve [\_SB.OSCP], AE_NOT_FOUND (20180810/psargs-330)
>Oct 25 01:15:46 ACPI Error: Method parse/execution failed \_PR.CPU5.GCAP, AE_NOT_FOUND (20180810/psparse-516)
>Oct 25 01:15:46 ACPI Error: Method parse/execution failed \_PR.CPU5._PDC, AE_NOT_FOUND (20180810/psparse-516)
>Oct 25 01:15:46 ACPI BIOS Error (bug): Could not resolve [\_SB.OSCP], AE_NOT_FOUND (20180810/psargs-330)
>Oct 25 01:15:46 ACPI Error: Method parse/execution failed \_PR.CPU6.GCAP, AE_NOT_FOUND (20180810/psparse-516)
>Oct 25 01:15:46 ACPI Error: Method parse/execution failed \_PR.CPU6._PDC, AE_NOT_FOUND (20180810/psparse-516)
>Oct 25 01:15:46 ACPI BIOS Error (bug): Could not resolve [\_SB.OSCP], AE_NOT_FOUND (20180810/psargs-330)
>Oct 25 01:15:46 ACPI Error: Method parse/execution failed \_PR.CPU7.GCAP, AE_NOT_FOUND (20180810/psparse-516)
>Oct 25 01:15:46 ACPI Error: Method parse/execution failed \_PR.CPU7._PDC, AE_NOT_FOUND (20180810/psparse-516)
>Oct 25 01:15:46 ACPI: Interpreter enabled
>Oct 25 01:15:46 ACPI: (supports S0 S3 S4 S5)
>Oct 25 01:15:46 ACPI: Using IOAPIC for interrupt routing
>Oct 25 01:15:46 PCI: MMCONFIG for domain 0000 [bus 00-ff] at [mem 0xe0000000-0xefffffff] (base 0xe0000000)
>Oct 25 01:15:46 PCI: MMCONFIG at [mem 0xe0000000-0xefffffff] reserved in ACPI motherboard resources
>Oct 25 01:15:46 PCI: Using host bridge windows from ACPI; if necessary, use "pci=nocrs" and report a bug
>Oct 25 01:15:46 ACPI: Enabled 11 GPEs in block 00 to 7F
>Oct 25 01:15:46 ACPI: PCI Root Bridge [PCI0] (domain 0000 [bus 00-ff])
>Oct 25 01:15:46 acpi PNP0A08:00: _OSC: OS assumes control of [PCIeHotplug SHPCHotplug AER PCIeCapability LTR]
>Oct 25 01:15:46 PCI host bridge to bus 0000:00
>Oct 25 01:15:46 pci_bus 0000:00: root bus resource [io  0x0000-0x0cf7 window]
>Oct 25 01:15:46 pci_bus 0000:00: root bus resource [io  0x0d00-0xffff window]
>Oct 25 01:15:46 pci_bus 0000:00: root bus resource [mem 0x000a0000-0x000bffff window]
>Oct 25 01:15:46 pci_bus 0000:00: root bus resource [mem 0x000c0000-0x000c3fff window]
>Oct 25 01:15:46 pci_bus 0000:00: root bus resource [mem 0x000c4000-0x000c7fff window]
>Oct 25 01:15:46 pci_bus 0000:00: root bus resource [mem 0x000c8000-0x000cbfff window]
>Oct 25 01:15:46 pci_bus 0000:00: root bus resource [mem 0x000cc000-0x000cffff window]
>Oct 25 01:15:46 pci_bus 0000:00: root bus resource [mem 0x000d0000-0x000d3fff window]
>Oct 25 01:15:46 pci_bus 0000:00: root bus resource [mem 0x000d4000-0x000d7fff window]
>Oct 25 01:15:46 pci_bus 0000:00: root bus resource [mem 0x000d8000-0x000dbfff window]
>Oct 25 01:15:46 pci_bus 0000:00: root bus resource [mem 0x000dc000-0x000dffff window]
>Oct 25 01:15:46 pci_bus 0000:00: root bus resource [mem 0x000e0000-0x000e3fff window]
>Oct 25 01:15:46 pci_bus 0000:00: root bus resource [mem 0x000e4000-0x000e7fff window]
>Oct 25 01:15:46 pci_bus 0000:00: root bus resource [mem 0x000e8000-0x000ebfff window]
>Oct 25 01:15:46 pci_bus 0000:00: root bus resource [mem 0x000ec000-0x000effff window]
>Oct 25 01:15:46 pci_bus 0000:00: root bus resource [mem 0x000f0000-0x000fffff window]
>Oct 25 01:15:46 pci_bus 0000:00: root bus resource [mem 0x80000000-0xfeafffff window]
>Oct 25 01:15:46 pci_bus 0000:00: root bus resource [bus 00-ff]
>Oct 25 01:15:46 pci 0000:00:00.0: [8086:1910] type 00 class 0x060000
>Oct 25 01:15:46 pci 0000:00:01.0: [8086:1901] type 01 class 0x060400
>Oct 25 01:15:46 pci 0000:00:01.0: PME# supported from D0 D3hot D3cold
>Oct 25 01:15:46 pci 0000:00:01.1: [8086:1905] type 01 class 0x060400
>Oct 25 01:15:46 pci 0000:00:01.1: PME# supported from D0 D3hot D3cold
>Oct 25 01:15:46 pci 0000:00:01.2: [8086:1909] type 01 class 0x060400
>Oct 25 01:15:46 pci 0000:00:01.2: PME# supported from D0 D3hot D3cold
>Oct 25 01:15:46 pci 0000:00:02.0: [8086:191b] type 00 class 0x030000
>Oct 25 01:15:46 pci 0000:00:02.0: reg 0x10: [mem 0x81000000-0x81ffffff 64bit]
>Oct 25 01:15:46 pci 0000:00:02.0: reg 0x18: [mem 0xa0000000-0xafffffff 64bit pref]
>Oct 25 01:15:46 pci 0000:00:02.0: reg 0x20: [io  0x5000-0x503f]
>Oct 25 01:15:46 pci 0000:00:02.0: BAR 2: assigned to efifb
>Oct 25 01:15:46 pci 0000:00:14.0: [8086:a12f] type 00 class 0x0c0330
>Oct 25 01:15:46 pci 0000:00:14.0: reg 0x10: [mem 0x82700000-0x8270ffff 64bit]
>Oct 25 01:15:46 pci 0000:00:14.0: PME# supported from D3hot D3cold
>Oct 25 01:15:46 pci 0000:00:15.0: [8086:a160] type 00 class 0x118000
>Oct 25 01:15:46 pci 0000:00:15.0: reg 0x10: [mem 0x82728000-0x82728fff 64bit]
>Oct 25 01:15:46 pci 0000:00:16.0: [8086:a13a] type 00 class 0x078000
>Oct 25 01:15:46 pci 0000:00:16.0: reg 0x10: [mem 0x82729000-0x82729fff 64bit]
>Oct 25 01:15:46 pci 0000:00:16.0: PME# supported from D3hot
>Oct 25 01:15:46 pci 0000:00:19.0: [8086:a166] type 00 class 0x118000
>Oct 25 01:15:46 pci 0000:00:19.0: reg 0x10: [mem 0x8272a000-0x8272afff 64bit]
>Oct 25 01:15:46 pci 0000:00:1b.0: [8086:a167] type 01 class 0x060400
>Oct 25 01:15:46 pci 0000:00:1b.0: PME# supported from D0 D3hot D3cold
>Oct 25 01:15:46 pci 0000:00:1b.0: Intel SPT PCH root port ACS workaround enabled
>Oct 25 01:15:46 pci 0000:00:1c.0: [8086:a110] type 01 class 0x060400
>Oct 25 01:15:46 pci 0000:00:1c.0: PME# supported from D0 D3hot D3cold
>Oct 25 01:15:46 pci 0000:00:1c.0: Intel SPT PCH root port ACS workaround enabled
>Oct 25 01:15:46 pci 0000:00:1e.0: [8086:a127] type 00 class 0x118000
>Oct 25 01:15:46 pci 0000:00:1e.0: reg 0x10: [mem 0x8272b000-0x8272bfff 64bit]
>Oct 25 01:15:46 pci 0000:00:1e.1: [8086:a128] type 00 class 0x118000
>Oct 25 01:15:46 pci 0000:00:1e.1: reg 0x10: [mem 0x8272c000-0x8272cfff 64bit]
>Oct 25 01:15:46 pci 0000:00:1e.2: [8086:a129] type 00 class 0x118000
>Oct 25 01:15:46 pci 0000:00:1e.2: reg 0x10: [mem 0x8272d000-0x8272dfff 64bit]
>Oct 25 01:15:46 pci 0000:00:1e.3: [8086:a12a] type 00 class 0x118000
>Oct 25 01:15:46 pci 0000:00:1e.3: reg 0x10: [mem 0x8272e000-0x8272efff 64bit]
>Oct 25 01:15:46 pci 0000:00:1f.0: [8086:a151] type 00 class 0x060100
>Oct 25 01:15:46 pci 0000:00:1f.2: [8086:a121] type 00 class 0x058000
>Oct 25 01:15:46 pci 0000:00:1f.2: reg 0x10: [mem 0x82724000-0x82727fff]
>Oct 25 01:15:46 pci 0000:00:1f.3: [8086:a170] type 00 class 0x040300
>Oct 25 01:15:46 pci 0000:00:1f.3: reg 0x10: [mem 0x82720000-0x82723fff 64bit]
>Oct 25 01:15:46 pci 0000:00:1f.3: reg 0x20: [mem 0x00000000-0x0000ffff 64bit]
>Oct 25 01:15:46 pci 0000:00:1f.3: PME# supported from D3hot D3cold
>Oct 25 01:15:46 pci 0000:00:1f.4: [8086:a123] type 00 class 0x0c0500
>Oct 25 01:15:46 pci 0000:00:1f.4: reg 0x10: [mem 0x8272f000-0x8272f0ff 64bit]
>Oct 25 01:15:46 pci 0000:00:1f.4: reg 0x20: [io  0x5040-0x505f]
>Oct 25 01:15:46 pci 0000:01:00.0: [1002:67ef] type 00 class 0x030000
>Oct 25 01:15:46 pci 0000:01:00.0: reg 0x10: [mem 0xb0000000-0xbfffffff 64bit pref]
>Oct 25 01:15:46 pci 0000:01:00.0: reg 0x18: [mem 0xc0000000-0xc01fffff 64bit pref]
>Oct 25 01:15:46 pci 0000:01:00.0: reg 0x20: [io  0x4000-0x40ff]
>Oct 25 01:15:46 pci 0000:01:00.0: reg 0x24: [mem 0x82600000-0x8263ffff]
>Oct 25 01:15:46 pci 0000:01:00.0: reg 0x30: [mem 0x82640000-0x8265ffff pref]
>Oct 25 01:15:46 pci 0000:01:00.0: supports D1 D2
>Oct 25 01:15:46 pci 0000:01:00.1: [1002:aae0] type 00 class 0x040300
>Oct 25 01:15:46 pci 0000:01:00.1: reg 0x10: [mem 0x82660000-0x82663fff 64bit]
>Oct 25 01:15:46 pci 0000:01:00.1: supports D1 D2
>Oct 25 01:15:46 pci 0000:00:01.0: PCI bridge to [bus 01]
>Oct 25 01:15:46 pci 0000:00:01.0:   bridge window [io  0x4000-0x4fff]
>Oct 25 01:15:46 pci 0000:00:01.0:   bridge window [mem 0x82600000-0x826fffff]
>Oct 25 01:15:46 pci 0000:00:01.0:   bridge window [mem 0xb0000000-0xc01fffff 64bit pref]
>Oct 25 01:15:46 pci 0000:04:00.0: [8086:1578] type 01 class 0x060400
>Oct 25 01:15:46 pci 0000:04:00.0: supports D1 D2
>Oct 25 01:15:46 pci 0000:04:00.0: PME# supported from D0 D1 D2 D3hot D3cold
>Oct 25 01:15:46 pci 0000:00:01.1: PCI bridge to [bus 04-79]
>Oct 25 01:15:46 pci 0000:00:01.1:   bridge window [io  0x6000-0x9fff]
>Oct 25 01:15:46 pci 0000:00:01.1:   bridge window [mem 0x82800000-0x909fffff]
>Oct 25 01:15:46 pci 0000:00:01.1:   bridge window [mem 0xc0200000-0xce1fffff 64bit pref]
>Oct 25 01:15:46 pci 0000:05:00.0: [8086:15d3] type 01 class 0x060400
>Oct 25 01:15:46 pci 0000:05:00.0: supports D1 D2
>Oct 25 01:15:46 pci 0000:05:00.0: PME# supported from D0 D1 D2 D3hot D3cold
>Oct 25 01:15:46 pci 0000:05:01.0: [8086:15d3] type 01 class 0x060400
>Oct 25 01:15:46 pci 0000:05:01.0: supports D1 D2
>Oct 25 01:15:46 pci 0000:05:01.0: PME# supported from D0 D1 D2 D3hot D3cold
>Oct 25 01:15:46 pci 0000:05:02.0: [8086:15d3] type 01 class 0x060400
>Oct 25 01:15:46 pci 0000:05:02.0: supports D1 D2
>Oct 25 01:15:46 pci 0000:05:02.0: PME# supported from D0 D1 D2 D3hot D3cold
>Oct 25 01:15:46 pci 0000:05:04.0: [8086:15d3] type 01 class 0x060400
>Oct 25 01:15:46 pci 0000:05:04.0: supports D1 D2
>Oct 25 01:15:46 pci 0000:05:04.0: PME# supported from D0 D1 D2 D3hot D3cold
>Oct 25 01:15:46 pci 0000:04:00.0: PCI bridge to [bus 05-79]
>Oct 25 01:15:46 pci 0000:04:00.0:   bridge window [io  0x6000-0x9fff]
>Oct 25 01:15:46 pci 0000:04:00.0:   bridge window [mem 0x82800000-0x909fffff]
>Oct 25 01:15:46 pci 0000:04:00.0:   bridge window [mem 0xc0200000-0xce1fffff 64bit pref]
>Oct 25 01:15:46 pci 0000:06:00.0: [8086:15d2] type 00 class 0x088000
>Oct 25 01:15:46 pci 0000:06:00.0: reg 0x10: [mem 0x82900000-0x8293ffff]
>Oct 25 01:15:46 pci 0000:06:00.0: reg 0x14: [mem 0x82940000-0x82940fff]
>Oct 25 01:15:46 pci 0000:06:00.0: supports D1 D2
>Oct 25 01:15:46 pci 0000:06:00.0: PME# supported from D0 D1 D2 D3hot D3cold
>Oct 25 01:15:46 pci 0000:06:00.0: 8.000 Gb/s available PCIe bandwidth, limited by 2.5 GT/s x4 link at 0000:05:00.0 (capable of 31.504 Gb/s with 8 GT/s x4 link)
>Oct 25 01:15:46 pci 0000:05:00.0: PCI bridge to [bus 06]
>Oct 25 01:15:46 pci 0000:05:00.0:   bridge window [mem 0x82900000-0x829fffff]
>Oct 25 01:15:46 pci 0000:05:01.0: PCI bridge to [bus 08-40]
>Oct 25 01:15:46 pci 0000:05:01.0:   bridge window [io  0x6000-0x7fff]
>Oct 25 01:15:46 pci 0000:05:01.0:   bridge window [mem 0x82a00000-0x899fffff]
>Oct 25 01:15:46 pci 0000:05:01.0:   bridge window [mem 0xc0200000-0xc71fffff 64bit pref]
>Oct 25 01:15:46 pci 0000:07:00.0: [8086:15d4] type 00 class 0x0c0330
>Oct 25 01:15:46 pci 0000:07:00.0: reg 0x10: [mem 0x82800000-0x8280ffff]
>Oct 25 01:15:46 pci 0000:07:00.0: supports D1 D2
>Oct 25 01:15:46 pci 0000:07:00.0: PME# supported from D0 D1 D2 D3hot D3cold
>Oct 25 01:15:46 pci 0000:07:00.0: 8.000 Gb/s available PCIe bandwidth, limited by 2.5 GT/s x4 link at 0000:05:02.0 (capable of 31.504 Gb/s with 8 GT/s x4 link)
>Oct 25 01:15:46 pci 0000:05:02.0: PCI bridge to [bus 07]
>Oct 25 01:15:46 pci 0000:05:02.0:   bridge window [mem 0x82800000-0x828fffff]
>Oct 25 01:15:46 pci 0000:05:04.0: PCI bridge to [bus 41-79]
>Oct 25 01:15:46 pci 0000:05:04.0:   bridge window [io  0x8000-0x9fff]
>Oct 25 01:15:46 pci 0000:05:04.0:   bridge window [mem 0x89a00000-0x909fffff]
>Oct 25 01:15:46 pci 0000:05:04.0:   bridge window [mem 0xc7200000-0xce1fffff 64bit pref]
>Oct 25 01:15:46 pci 0000:7a:00.0: [8086:1578] type 01 class 0x060400
>Oct 25 01:15:46 pci 0000:7a:00.0: supports D1 D2
>Oct 25 01:15:46 pci 0000:7a:00.0: PME# supported from D0 D1 D2 D3hot D3cold
>Oct 25 01:15:46 pci 0000:00:01.2: PCI bridge to [bus 7a-ef]
>Oct 25 01:15:46 pci 0000:00:01.2:   bridge window [io  0xa000-0xdfff]
>Oct 25 01:15:46 pci 0000:00:01.2:   bridge window [mem 0x90a00000-0x9ebfffff]
>Oct 25 01:15:46 pci 0000:00:01.2:   bridge window [mem 0xce200000-0xdc1fffff 64bit pref]
>Oct 25 01:15:46 pci 0000:7b:00.0: [8086:15d3] type 01 class 0x060400
>Oct 25 01:15:46 pci 0000:7b:00.0: supports D1 D2
>Oct 25 01:15:46 pci 0000:7b:00.0: PME# supported from D0 D1 D2 D3hot D3cold
>Oct 25 01:15:46 pci 0000:7b:01.0: [8086:15d3] type 01 class 0x060400
>Oct 25 01:15:46 pci 0000:7b:01.0: supports D1 D2
>Oct 25 01:15:46 pci 0000:7b:01.0: PME# supported from D0 D1 D2 D3hot D3cold
>Oct 25 01:15:46 pci 0000:7b:02.0: [8086:15d3] type 01 class 0x060400
>Oct 25 01:15:46 pci 0000:7b:02.0: supports D1 D2
>Oct 25 01:15:46 pci 0000:7b:02.0: PME# supported from D0 D1 D2 D3hot D3cold
>Oct 25 01:15:46 pci 0000:7b:04.0: [8086:15d3] type 01 class 0x060400
>Oct 25 01:15:46 pci 0000:7b:04.0: supports D1 D2
>Oct 25 01:15:46 pci 0000:7b:04.0: PME# supported from D0 D1 D2 D3hot D3cold
>Oct 25 01:15:46 pci 0000:7a:00.0: PCI bridge to [bus 7b-ef]
>Oct 25 01:15:46 pci 0000:7a:00.0:   bridge window [io  0xa000-0xdfff]
>Oct 25 01:15:46 pci 0000:7a:00.0:   bridge window [mem 0x90a00000-0x9ebfffff]
>Oct 25 01:15:46 pci 0000:7a:00.0:   bridge window [mem 0xce200000-0xdc1fffff 64bit pref]
>Oct 25 01:15:46 pci 0000:7c:00.0: [8086:15d2] type 00 class 0x088000
>Oct 25 01:15:46 pci 0000:7c:00.0: reg 0x10: [mem 0x90b00000-0x90b3ffff]
>Oct 25 01:15:46 pci 0000:7c:00.0: reg 0x14: [mem 0x90b40000-0x90b40fff]
>Oct 25 01:15:46 pci 0000:7c:00.0: supports D1 D2
>Oct 25 01:15:46 pci 0000:7c:00.0: PME# supported from D0 D1 D2 D3hot D3cold
>Oct 25 01:15:46 pci 0000:7c:00.0: 8.000 Gb/s available PCIe bandwidth, limited by 2.5 GT/s x4 link at 0000:7b:00.0 (capable of 31.504 Gb/s with 8 GT/s x4 link)
>Oct 25 01:15:46 pci 0000:7b:00.0: PCI bridge to [bus 7c]
>Oct 25 01:15:46 pci 0000:7b:00.0:   bridge window [mem 0x90b00000-0x90bfffff]
>Oct 25 01:15:46 pci 0000:7b:01.0: PCI bridge to [bus 7e-b6]
>Oct 25 01:15:46 pci 0000:7b:01.0:   bridge window [io  0xa000-0xbfff]
>Oct 25 01:15:46 pci 0000:7b:01.0:   bridge window [mem 0x90c00000-0x97bfffff]
>Oct 25 01:15:46 pci 0000:7b:01.0:   bridge window [mem 0xce200000-0xd51fffff 64bit pref]
>Oct 25 01:15:46 pci 0000:7d:00.0: [8086:15d4] type 00 class 0x0c0330
>Oct 25 01:15:46 pci 0000:7d:00.0: reg 0x10: [mem 0x90a00000-0x90a0ffff]
>Oct 25 01:15:46 pci 0000:7d:00.0: supports D1 D2
>Oct 25 01:15:46 pci 0000:7d:00.0: PME# supported from D0 D1 D2 D3hot D3cold
>Oct 25 01:15:46 pci 0000:7d:00.0: 8.000 Gb/s available PCIe bandwidth, limited by 2.5 GT/s x4 link at 0000:7b:02.0 (capable of 31.504 Gb/s with 8 GT/s x4 link)
>Oct 25 01:15:46 pci 0000:7b:02.0: PCI bridge to [bus 7d]
>Oct 25 01:15:46 pci 0000:7b:02.0:   bridge window [mem 0x90a00000-0x90afffff]
>Oct 25 01:15:46 pci 0000:7b:04.0: PCI bridge to [bus b7-ef]
>Oct 25 01:15:46 pci 0000:7b:04.0:   bridge window [io  0xc000-0xdfff]
>Oct 25 01:15:46 pci 0000:7b:04.0:   bridge window [mem 0x97c00000-0x9ebfffff]
>Oct 25 01:15:46 pci 0000:7b:04.0:   bridge window [mem 0xd5200000-0xdc1fffff 64bit pref]
>Oct 25 01:15:46 pci 0000:02:00.0: [144d:a804] type 00 class 0x010802
>Oct 25 01:15:46 pci 0000:02:00.0: reg 0x10: [mem 0x82500000-0x82503fff 64bit]
>Oct 25 01:15:46 pci 0000:02:00.0: reg 0x18: [io  0x3000-0x30ff]
>Oct 25 01:15:46 pci 0000:00:1b.0: PCI bridge to [bus 02]
>Oct 25 01:15:46 pci 0000:00:1b.0:   bridge window [io  0x3000-0x3fff]
>Oct 25 01:15:46 pci 0000:00:1b.0:   bridge window [mem 0x82500000-0x825fffff]
>Oct 25 01:15:46 pci 0000:03:00.0: [14e4:43ba] type 00 class 0x028000
>Oct 25 01:15:46 pci 0000:03:00.0: reg 0x10: [mem 0x82400000-0x82407fff 64bit]
>Oct 25 01:15:46 pci 0000:03:00.0: reg 0x18: [mem 0x82000000-0x823fffff 64bit]
>Oct 25 01:15:46 pci 0000:03:00.0: supports D1 D2
>Oct 25 01:15:46 pci 0000:03:00.0: PME# supported from D0 D1 D2 D3hot D3cold
>Oct 25 01:15:46 pci 0000:03:00.0: 2.000 Gb/s available PCIe bandwidth, limited by 2.5 GT/s x1 link at 0000:00:1c.0 (capable of 7.876 Gb/s with 8 GT/s x1 link)
>Oct 25 01:15:46 pci 0000:00:1c.0: PCI bridge to [bus 03]
>Oct 25 01:15:46 pci 0000:00:1c.0:   bridge window [mem 0x82000000-0x824fffff]
>Oct 25 01:15:46 ACPI: PCI Interrupt Link [LNKA] (IRQs 1 3 4 5 6 7 10 12 14 15) *0
>Oct 25 01:15:46 ACPI: PCI Interrupt Link [LNKB] (IRQs 1 3 4 5 6 7 11 12 14 15) *0
>Oct 25 01:15:46 ACPI: PCI Interrupt Link [LNKC] (IRQs 1 3 4 5 6 7 10 12 14 15) *0
>Oct 25 01:15:46 ACPI: PCI Interrupt Link [LNKD] (IRQs 1 3 4 5 6 7 11 12 14 15) *0
>Oct 25 01:15:46 ACPI: PCI Interrupt Link [LNKE] (IRQs 1 3 4 5 6 7 10 12 14 15) *0
>Oct 25 01:15:46 ACPI: PCI Interrupt Link [LNKF] (IRQs 1 3 4 5 6 7 11 12 14 15) *0
>Oct 25 01:15:46 ACPI: PCI Interrupt Link [LNKG] (IRQs 1 3 4 5 6 7 10 12 14 15) *0
>Oct 25 01:15:46 ACPI: PCI Interrupt Link [LNKH] (IRQs 1 3 4 5 6 7 11 12 14 15) *0
>Oct 25 01:15:46 ACPI: EC: interrupt unblocked
>Oct 25 01:15:46 ACPI: EC: event unblocked
>Oct 25 01:15:46 ACPI: \_SB_.PCI0.LPCB.EC__: GPE=0x7, EC_CMD/EC_SC=0x66, EC_DATA=0x62
>Oct 25 01:15:46 ACPI: \_SB_.PCI0.LPCB.EC__: Used as boot DSDT EC to handle transactions and events
>Oct 25 01:15:46 pci 0000:00:02.0: vgaarb: setting as boot VGA device
>Oct 25 01:15:46 pci 0000:00:02.0: vgaarb: VGA device added: decodes=io+mem,owns=io+mem,locks=none
>Oct 25 01:15:46 pci 0000:01:00.0: vgaarb: VGA device added: decodes=io+mem,owns=none,locks=none
>Oct 25 01:15:46 pci 0000:00:02.0: vgaarb: no bridge control possible
>Oct 25 01:15:46 pci 0000:01:00.0: vgaarb: bridge control possible
>Oct 25 01:15:46 vgaarb: loaded
>Oct 25 01:15:46 SCSI subsystem initialized
>Oct 25 01:15:46 libata version 3.00 loaded.
>Oct 25 01:15:46 ACPI: bus type USB registered
>Oct 25 01:15:46 usbcore: registered new interface driver usbfs
>Oct 25 01:15:46 usbcore: registered new interface driver hub
>Oct 25 01:15:46 usbcore: registered new device driver usb
>Oct 25 01:15:46 pps_core: LinuxPPS API ver. 1 registered
>Oct 25 01:15:46 pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
>Oct 25 01:15:46 PTP clock support registered
>Oct 25 01:15:46 EDAC MC: Ver: 3.0.0
>Oct 25 01:15:46 Registered efivars operations
>Oct 25 01:15:46 PCI: Using ACPI for IRQ routing
>Oct 25 01:15:46 PCI: pci_cache_line_size set to 64 bytes
>Oct 25 01:15:46 e820: reserve RAM buffer [mem 0x00058000-0x0005ffff]
>Oct 25 01:15:46 e820: reserve RAM buffer [mem 0x0009e000-0x0009ffff]
>Oct 25 01:15:46 e820: reserve RAM buffer [mem 0x72413018-0x73ffffff]
>Oct 25 01:15:46 e820: reserve RAM buffer [mem 0x72425018-0x73ffffff]
>Oct 25 01:15:46 e820: reserve RAM buffer [mem 0x74025000-0x77ffffff]
>Oct 25 01:15:46 e820: reserve RAM buffer [mem 0x74e08000-0x77ffffff]
>Oct 25 01:15:46 e820: reserve RAM buffer [mem 0x7507e000-0x77ffffff]
>Oct 25 01:15:46 e820: reserve RAM buffer [mem 0x7ac7f000-0x7bffffff]
>Oct 25 01:15:46 e820: reserve RAM buffer [mem 0x7b000000-0x7bffffff]
>Oct 25 01:15:46 e820: reserve RAM buffer [mem 0x47f000000-0x47fffffff]
>Oct 25 01:15:46 NetLabel: Initializing
>Oct 25 01:15:46 NetLabel:  domain hash size = 128
>Oct 25 01:15:46 NetLabel:  protocols = UNLABELED CIPSOv4 CALIPSO
>Oct 25 01:15:46 NetLabel:  unlabeled traffic allowed by default
>Oct 25 01:15:46 hpet0: at MMIO 0xfed00000, IRQs 2, 8, 0, 0, 0, 0, 0, 0
>Oct 25 01:15:46 hpet0: 8 comparators, 64-bit 24.000000 MHz counter
>Oct 25 01:15:46 clocksource: Switched to clocksource tsc-early
>Oct 25 01:15:46 VFS: Disk quotas dquot_6.6.0
>Oct 25 01:15:46 VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
>Oct 25 01:15:46 pnp: PnP ACPI init
>Oct 25 01:15:46 system 00:00: [io  0xffff] has been reserved
>Oct 25 01:15:46 system 00:00: [io  0x1800-0x18fe] has been reserved
>Oct 25 01:15:46 system 00:00: [io  0x0800-0x087f] has been reserved
>Oct 25 01:15:46 system 00:00: Plug and Play ACPI device, IDs PNP0c02 (active)
>Oct 25 01:15:46 pnp 00:01: Plug and Play ACPI device, IDs PNP0b00 (active)
>Oct 25 01:15:46 pnp 00:02: Plug and Play ACPI device, IDs APP000b (active)
>Oct 25 01:15:46 system 00:03: [mem 0xfed10000-0xfed17fff] has been reserved
>Oct 25 01:15:46 system 00:03: [mem 0xfed18000-0xfed18fff] has been reserved
>Oct 25 01:15:46 system 00:03: [mem 0xfed19000-0xfed19fff] has been reserved
>Oct 25 01:15:46 system 00:03: [mem 0xe0000000-0xefffffff] could not be reserved
>Oct 25 01:15:46 system 00:03: [mem 0xfd000000-0xfe7fffff] could not be reserved
>Oct 25 01:15:46 system 00:03: [mem 0xfed20000-0xfed3ffff] has been reserved
>Oct 25 01:15:46 system 00:03: [mem 0xfed90000-0xfed93fff] could not be reserved
>Oct 25 01:15:46 system 00:03: [mem 0xfed45000-0xfed8ffff] has been reserved
>Oct 25 01:15:46 system 00:03: [mem 0xff000000-0xffffffff] could not be reserved
>Oct 25 01:15:46 system 00:03: [mem 0xfee00000-0xfeefffff] has been reserved
>Oct 25 01:15:46 system 00:03: Plug and Play ACPI device, IDs PNP0c02 (active)
>Oct 25 01:15:46 system 00:04: [mem 0x20000000-0x201fffff] could not be reserved
>Oct 25 01:15:46 system 00:04: [mem 0x40000000-0x401fffff] could not be reserved
>Oct 25 01:15:46 system 00:04: Plug and Play ACPI device, IDs PNP0c01 (active)
>Oct 25 01:15:46 pnp: PnP ACPI: found 5 devices
>Oct 25 01:15:46 pci 0000:00:02.0: assigning 5 device properties
>Oct 25 01:15:46 pci 0000:01:00.0: assigning 44 device properties
>Oct 25 01:15:46 pci 0000:06:00.0: assigning 8 device properties
>Oct 25 01:15:46 pci 0000:7c:00.0: assigning 8 device properties
>Oct 25 01:15:46 pci 0000:00:1f.3: assigning 5 device properties
>Oct 25 01:15:46 clocksource: acpi_pm: mask: 0xffffff max_cycles: 0xffffff, max_idle_ns: 2085701024 ns
>Oct 25 01:15:46 pci 0000:05:02.0: bridge window [io  0x1000-0x0fff] to [bus 07] add_size 1000
>Oct 25 01:15:46 pci 0000:05:02.0: bridge window [mem 0x00100000-0x000fffff 64bit pref] to [bus 07] add_size 200000 add_align 100000
>Oct 25 01:15:46 pci 0000:7b:02.0: bridge window [io  0x1000-0x0fff] to [bus 7d] add_size 1000
>Oct 25 01:15:46 pci 0000:7b:02.0: bridge window [mem 0x00100000-0x000fffff 64bit pref] to [bus 7d] add_size 200000 add_align 100000
>Oct 25 01:15:46 pci 0000:00:1f.3: BAR 4: assigned [mem 0x80000000-0x8000ffff 64bit]
>Oct 25 01:15:46 pci 0000:00:01.0: PCI bridge to [bus 01]
>Oct 25 01:15:46 pci 0000:00:01.0:   bridge window [io  0x4000-0x4fff]
>Oct 25 01:15:46 pci 0000:00:01.0:   bridge window [mem 0x82600000-0x826fffff]
>Oct 25 01:15:46 pci 0000:00:01.0:   bridge window [mem 0xb0000000-0xc01fffff 64bit pref]
>Oct 25 01:15:46 pci 0000:05:02.0: BAR 15: no space for [mem size 0x00200000 64bit pref]
>Oct 25 01:15:46 pci 0000:05:02.0: BAR 15: failed to assign [mem size 0x00200000 64bit pref]
>Oct 25 01:15:46 pci 0000:05:02.0: BAR 13: no space for [io  size 0x1000]
>Oct 25 01:15:46 pci 0000:05:02.0: BAR 13: failed to assign [io  size 0x1000]
>Oct 25 01:15:46 pci 0000:05:02.0: BAR 15: no space for [mem size 0x00200000 64bit pref]
>Oct 25 01:15:46 pci 0000:05:02.0: BAR 15: failed to assign [mem size 0x00200000 64bit pref]
>Oct 25 01:15:46 pci 0000:05:02.0: BAR 13: no space for [io  size 0x1000]
>Oct 25 01:15:46 pci 0000:05:02.0: BAR 13: failed to assign [io  size 0x1000]
>Oct 25 01:15:46 pci 0000:05:00.0: PCI bridge to [bus 06]
>Oct 25 01:15:46 pci 0000:05:00.0:   bridge window [mem 0x82900000-0x829fffff]
>Oct 25 01:15:46 pci 0000:05:01.0: PCI bridge to [bus 08-40]
>Oct 25 01:15:46 pci 0000:05:01.0:   bridge window [io  0x6000-0x7fff]
>Oct 25 01:15:46 pci 0000:05:01.0:   bridge window [mem 0x82a00000-0x899fffff]
>Oct 25 01:15:46 pci 0000:05:01.0:   bridge window [mem 0xc0200000-0xc71fffff 64bit pref]
>Oct 25 01:15:46 pci 0000:05:02.0: PCI bridge to [bus 07]
>Oct 25 01:15:46 pci 0000:05:02.0:   bridge window [mem 0x82800000-0x828fffff]
>Oct 25 01:15:46 pci 0000:05:04.0: PCI bridge to [bus 41-79]
>Oct 25 01:15:46 pci 0000:05:04.0:   bridge window [io  0x8000-0x9fff]
>Oct 25 01:15:46 pci 0000:05:04.0:   bridge window [mem 0x89a00000-0x909fffff]
>Oct 25 01:15:46 pci 0000:05:04.0:   bridge window [mem 0xc7200000-0xce1fffff 64bit pref]
>Oct 25 01:15:46 pci 0000:04:00.0: PCI bridge to [bus 05-79]
>Oct 25 01:15:46 pci 0000:04:00.0:   bridge window [io  0x6000-0x9fff]
>Oct 25 01:15:46 pci 0000:04:00.0:   bridge window [mem 0x82800000-0x909fffff]
>Oct 25 01:15:46 pci 0000:04:00.0:   bridge window [mem 0xc0200000-0xce1fffff 64bit pref]
>Oct 25 01:15:46 pci 0000:00:01.1: PCI bridge to [bus 04-79]
>Oct 25 01:15:46 pci 0000:00:01.1:   bridge window [io  0x6000-0x9fff]
>Oct 25 01:15:46 pci 0000:00:01.1:   bridge window [mem 0x82800000-0x909fffff]
>Oct 25 01:15:46 pci 0000:00:01.1:   bridge window [mem 0xc0200000-0xce1fffff 64bit pref]
>Oct 25 01:15:46 pci 0000:7b:02.0: BAR 15: no space for [mem size 0x00200000 64bit pref]
>Oct 25 01:15:46 pci 0000:7b:02.0: BAR 15: failed to assign [mem size 0x00200000 64bit pref]
>Oct 25 01:15:46 pci 0000:7b:02.0: BAR 13: no space for [io  size 0x1000]
>Oct 25 01:15:46 pci 0000:7b:02.0: BAR 13: failed to assign [io  size 0x1000]
>Oct 25 01:15:46 pci 0000:7b:02.0: BAR 15: no space for [mem size 0x00200000 64bit pref]
>Oct 25 01:15:46 pci 0000:7b:02.0: BAR 15: failed to assign [mem size 0x00200000 64bit pref]
>Oct 25 01:15:46 pci 0000:7b:02.0: BAR 13: no space for [io  size 0x1000]
>Oct 25 01:15:46 pci 0000:7b:02.0: BAR 13: failed to assign [io  size 0x1000]
>Oct 25 01:15:46 pci 0000:7b:00.0: PCI bridge to [bus 7c]
>Oct 25 01:15:46 pci 0000:7b:00.0:   bridge window [mem 0x90b00000-0x90bfffff]
>Oct 25 01:15:46 pci 0000:7b:01.0: PCI bridge to [bus 7e-b6]
>Oct 25 01:15:46 pci 0000:7b:01.0:   bridge window [io  0xa000-0xbfff]
>Oct 25 01:15:46 pci 0000:7b:01.0:   bridge window [mem 0x90c00000-0x97bfffff]
>Oct 25 01:15:46 pci 0000:7b:01.0:   bridge window [mem 0xce200000-0xd51fffff 64bit pref]
>Oct 25 01:15:46 pci 0000:7b:02.0: PCI bridge to [bus 7d]
>Oct 25 01:15:46 pci 0000:7b:02.0:   bridge window [mem 0x90a00000-0x90afffff]
>Oct 25 01:15:46 pci 0000:7b:04.0: PCI bridge to [bus b7-ef]
>Oct 25 01:15:46 pci 0000:7b:04.0:   bridge window [io  0xc000-0xdfff]
>Oct 25 01:15:46 pci 0000:7b:04.0:   bridge window [mem 0x97c00000-0x9ebfffff]
>Oct 25 01:15:46 pci 0000:7b:04.0:   bridge window [mem 0xd5200000-0xdc1fffff 64bit pref]
>Oct 25 01:15:46 pci 0000:7a:00.0: PCI bridge to [bus 7b-ef]
>Oct 25 01:15:46 pci 0000:7a:00.0:   bridge window [io  0xa000-0xdfff]
>Oct 25 01:15:46 pci 0000:7a:00.0:   bridge window [mem 0x90a00000-0x9ebfffff]
>Oct 25 01:15:46 pci 0000:7a:00.0:   bridge window [mem 0xce200000-0xdc1fffff 64bit pref]
>Oct 25 01:15:46 pci 0000:00:01.2: PCI bridge to [bus 7a-ef]
>Oct 25 01:15:46 pci 0000:00:01.2:   bridge window [io  0xa000-0xdfff]
>Oct 25 01:15:46 pci 0000:00:01.2:   bridge window [mem 0x90a00000-0x9ebfffff]
>Oct 25 01:15:46 pci 0000:00:01.2:   bridge window [mem 0xce200000-0xdc1fffff 64bit pref]
>Oct 25 01:15:46 pci 0000:00:1b.0: PCI bridge to [bus 02]
>Oct 25 01:15:46 pci 0000:00:1b.0:   bridge window [io  0x3000-0x3fff]
>Oct 25 01:15:46 pci 0000:00:1b.0:   bridge window [mem 0x82500000-0x825fffff]
>Oct 25 01:15:46 pci 0000:00:1c.0: PCI bridge to [bus 03]
>Oct 25 01:15:46 pci 0000:00:1c.0:   bridge window [mem 0x82000000-0x824fffff]
>Oct 25 01:15:46 pci_bus 0000:00: resource 4 [io  0x0000-0x0cf7 window]
>Oct 25 01:15:46 pci_bus 0000:00: resource 5 [io  0x0d00-0xffff window]
>Oct 25 01:15:46 pci_bus 0000:00: resource 6 [mem 0x000a0000-0x000bffff window]
>Oct 25 01:15:46 pci_bus 0000:00: resource 7 [mem 0x000c0000-0x000c3fff window]
>Oct 25 01:15:46 pci_bus 0000:00: resource 8 [mem 0x000c4000-0x000c7fff window]
>Oct 25 01:15:46 pci_bus 0000:00: resource 9 [mem 0x000c8000-0x000cbfff window]
>Oct 25 01:15:46 pci_bus 0000:00: resource 10 [mem 0x000cc000-0x000cffff window]
>Oct 25 01:15:46 pci_bus 0000:00: resource 11 [mem 0x000d0000-0x000d3fff window]
>Oct 25 01:15:46 pci_bus 0000:00: resource 12 [mem 0x000d4000-0x000d7fff window]
>Oct 25 01:15:46 pci_bus 0000:00: resource 13 [mem 0x000d8000-0x000dbfff window]
>Oct 25 01:15:46 pci_bus 0000:00: resource 14 [mem 0x000dc000-0x000dffff window]
>Oct 25 01:15:46 pci_bus 0000:00: resource 15 [mem 0x000e0000-0x000e3fff window]
>Oct 25 01:15:46 pci_bus 0000:00: resource 16 [mem 0x000e4000-0x000e7fff window]
>Oct 25 01:15:46 pci_bus 0000:00: resource 17 [mem 0x000e8000-0x000ebfff window]
>Oct 25 01:15:46 pci_bus 0000:00: resource 18 [mem 0x000ec000-0x000effff window]
>Oct 25 01:15:46 pci_bus 0000:00: resource 19 [mem 0x000f0000-0x000fffff window]
>Oct 25 01:15:46 pci_bus 0000:00: resource 20 [mem 0x80000000-0xfeafffff window]
>Oct 25 01:15:46 pci_bus 0000:01: resource 0 [io  0x4000-0x4fff]
>Oct 25 01:15:46 pci_bus 0000:01: resource 1 [mem 0x82600000-0x826fffff]
>Oct 25 01:15:46 pci_bus 0000:01: resource 2 [mem 0xb0000000-0xc01fffff 64bit pref]
>Oct 25 01:15:46 pci_bus 0000:04: resource 0 [io  0x6000-0x9fff]
>Oct 25 01:15:46 pci_bus 0000:04: resource 1 [mem 0x82800000-0x909fffff]
>Oct 25 01:15:46 pci_bus 0000:04: resource 2 [mem 0xc0200000-0xce1fffff 64bit pref]
>Oct 25 01:15:46 pci_bus 0000:05: resource 0 [io  0x6000-0x9fff]
>Oct 25 01:15:46 pci_bus 0000:05: resource 1 [mem 0x82800000-0x909fffff]
>Oct 25 01:15:46 pci_bus 0000:05: resource 2 [mem 0xc0200000-0xce1fffff 64bit pref]
>Oct 25 01:15:46 pci_bus 0000:06: resource 1 [mem 0x82900000-0x829fffff]
>Oct 25 01:15:46 pci_bus 0000:08: resource 0 [io  0x6000-0x7fff]
>Oct 25 01:15:46 pci_bus 0000:08: resource 1 [mem 0x82a00000-0x899fffff]
>Oct 25 01:15:46 pci_bus 0000:08: resource 2 [mem 0xc0200000-0xc71fffff 64bit pref]
>Oct 25 01:15:46 pci_bus 0000:07: resource 1 [mem 0x82800000-0x828fffff]
>Oct 25 01:15:46 pci_bus 0000:41: resource 0 [io  0x8000-0x9fff]
>Oct 25 01:15:46 pci_bus 0000:41: resource 1 [mem 0x89a00000-0x909fffff]
>Oct 25 01:15:46 pci_bus 0000:41: resource 2 [mem 0xc7200000-0xce1fffff 64bit pref]
>Oct 25 01:15:46 pci_bus 0000:7a: resource 0 [io  0xa000-0xdfff]
>Oct 25 01:15:46 pci_bus 0000:7a: resource 1 [mem 0x90a00000-0x9ebfffff]
>Oct 25 01:15:46 pci_bus 0000:7a: resource 2 [mem 0xce200000-0xdc1fffff 64bit pref]
>Oct 25 01:15:46 pci_bus 0000:7b: resource 0 [io  0xa000-0xdfff]
>Oct 25 01:15:46 pci_bus 0000:7b: resource 1 [mem 0x90a00000-0x9ebfffff]
>Oct 25 01:15:46 pci_bus 0000:7b: resource 2 [mem 0xce200000-0xdc1fffff 64bit pref]
>Oct 25 01:15:46 pci_bus 0000:7c: resource 1 [mem 0x90b00000-0x90bfffff]
>Oct 25 01:15:46 pci_bus 0000:7e: resource 0 [io  0xa000-0xbfff]
>Oct 25 01:15:46 pci_bus 0000:7e: resource 1 [mem 0x90c00000-0x97bfffff]
>Oct 25 01:15:46 pci_bus 0000:7e: resource 2 [mem 0xce200000-0xd51fffff 64bit pref]
>Oct 25 01:15:46 pci_bus 0000:7d: resource 1 [mem 0x90a00000-0x90afffff]
>Oct 25 01:15:46 pci_bus 0000:b7: resource 0 [io  0xc000-0xdfff]
>Oct 25 01:15:46 pci_bus 0000:b7: resource 1 [mem 0x97c00000-0x9ebfffff]
>Oct 25 01:15:46 pci_bus 0000:b7: resource 2 [mem 0xd5200000-0xdc1fffff 64bit pref]
>Oct 25 01:15:46 pci_bus 0000:02: resource 0 [io  0x3000-0x3fff]
>Oct 25 01:15:46 pci_bus 0000:02: resource 1 [mem 0x82500000-0x825fffff]
>Oct 25 01:15:46 pci_bus 0000:03: resource 1 [mem 0x82000000-0x824fffff]
>Oct 25 01:15:46 NET: Registered protocol family 2
>Oct 25 01:15:46 tcp_listen_portaddr_hash hash table entries: 8192 (order: 7, 720896 bytes)
>Oct 25 01:15:46 TCP established hash table entries: 131072 (order: 8, 1048576 bytes)
>Oct 25 01:15:46 TCP bind hash table entries: 65536 (order: 10, 5242880 bytes)
>Oct 25 01:15:46 TCP: Hash tables configured (established 131072 bind 65536)
>Oct 25 01:15:46 UDP hash table entries: 8192 (order: 8, 1572864 bytes)
>Oct 25 01:15:46 UDP-Lite hash table entries: 8192 (order: 8, 1572864 bytes)
>Oct 25 01:15:46 NET: Registered protocol family 1
>Oct 25 01:15:46 pci 0000:00:02.0: Video device with shadowed ROM at [mem 0x000c0000-0x000dffff]
>Oct 25 01:15:46 pci 0000:01:00.1: Linked as a consumer to 0000:01:00.0
>Oct 25 01:15:46 PCI: CLS 256 bytes, default 64
>Oct 25 01:15:46 Unpacking initramfs...
>Oct 25 01:15:46 Freeing initrd memory: 17380K
>Oct 25 01:15:46 DMAR: ACPI device "device:91" under DMAR at fed91000 as 00:15.0
>Oct 25 01:15:46 DMAR: ACPI device "device:92" under DMAR at fed91000 as 00:1e.2
>Oct 25 01:15:46 DMAR: ACPI device "device:93" under DMAR at fed91000 as 00:1e.3
>Oct 25 01:15:46 DMAR: Failed to find handle for ACPI object \_SB.PCI0.UA00
>Oct 25 01:15:46 DMAR: Failed to find handle for ACPI object \_SB.PCI0.UA01
>Oct 25 01:15:46 DMAR: Failed to find handle for ACPI object \_SB.PCI0.UA02
>Oct 25 01:15:46 DMAR: No ATSR found
>Oct 25 01:15:46 DMAR: dmar0: Using Queued invalidation
>Oct 25 01:15:46 DMAR: dmar1: Using Queued invalidation
>Oct 25 01:15:46 DMAR: Setting RMRR:
>Oct 25 01:15:46 DMAR: Setting identity map for device 0000:00:02.0 [0x7b800000 - 0x7fffffff]
>Oct 25 01:15:46 DMAR: Prepare 0-16MiB unity mapping for LPC
>Oct 25 01:15:46 DMAR: Setting identity map for device 0000:00:1f.0 [0x0 - 0xffffff]
>Oct 25 01:15:46 DMAR: Intel(R) Virtualization Technology for Directed I/O
>Oct 25 01:15:46 iommu: Adding device 0000:00:00.0 to group 0
>Oct 25 01:15:46 iommu: Adding device 0000:00:01.0 to group 1
>Oct 25 01:15:46 iommu: Adding device 0000:00:01.1 to group 1
>Oct 25 01:15:46 iommu: Adding device 0000:00:01.2 to group 1
>Oct 25 01:15:46 iommu: Adding device 0000:00:02.0 to group 2
>Oct 25 01:15:46 iommu: Adding device 0000:00:14.0 to group 3
>Oct 25 01:15:46 iommu: Adding device 0000:00:15.0 to group 4
>Oct 25 01:15:46 iommu: Adding device 0000:00:16.0 to group 5
>Oct 25 01:15:46 iommu: Adding device 0000:00:19.0 to group 6
>Oct 25 01:15:46 iommu: Adding device 0000:00:1b.0 to group 7
>Oct 25 01:15:46 iommu: Adding device 0000:00:1c.0 to group 8
>Oct 25 01:15:46 iommu: Adding device 0000:00:1e.0 to group 9
>Oct 25 01:15:46 iommu: Adding device 0000:00:1e.1 to group 9
>Oct 25 01:15:46 iommu: Adding device 0000:00:1e.2 to group 9
>Oct 25 01:15:46 iommu: Adding device 0000:00:1e.3 to group 9
>Oct 25 01:15:46 iommu: Adding device 0000:00:1f.0 to group 10
>Oct 25 01:15:46 iommu: Adding device 0000:00:1f.2 to group 10
>Oct 25 01:15:46 iommu: Adding device 0000:00:1f.3 to group 10
>Oct 25 01:15:46 iommu: Adding device 0000:00:1f.4 to group 10
>Oct 25 01:15:46 iommu: Adding device 0000:01:00.0 to group 1
>Oct 25 01:15:46 iommu: Adding device 0000:01:00.1 to group 1
>Oct 25 01:15:46 iommu: Adding device 0000:04:00.0 to group 1
>Oct 25 01:15:46 iommu: Adding device 0000:05:00.0 to group 1
>Oct 25 01:15:46 iommu: Adding device 0000:05:01.0 to group 1
>Oct 25 01:15:46 iommu: Adding device 0000:05:02.0 to group 1
>Oct 25 01:15:46 iommu: Adding device 0000:05:04.0 to group 1
>Oct 25 01:15:46 iommu: Adding device 0000:06:00.0 to group 1
>Oct 25 01:15:46 iommu: Adding device 0000:07:00.0 to group 1
>Oct 25 01:15:46 iommu: Adding device 0000:7a:00.0 to group 1
>Oct 25 01:15:46 iommu: Adding device 0000:7b:00.0 to group 1
>Oct 25 01:15:46 iommu: Adding device 0000:7b:01.0 to group 1
>Oct 25 01:15:46 iommu: Adding device 0000:7b:02.0 to group 1
>Oct 25 01:15:46 iommu: Adding device 0000:7b:04.0 to group 1
>Oct 25 01:15:46 iommu: Adding device 0000:7c:00.0 to group 1
>Oct 25 01:15:46 iommu: Adding device 0000:7d:00.0 to group 1
>Oct 25 01:15:46 iommu: Adding device 0000:02:00.0 to group 11
>Oct 25 01:15:46 iommu: Adding device 0000:03:00.0 to group 12
>Oct 25 01:15:46 clocksource: tsc: mask: 0xffffffffffffffff max_cycles: 0x29dc05e54fc, max_idle_ns: 440795291716 ns
>Oct 25 01:15:46 clocksource: Switched to clocksource tsc
>Oct 25 01:15:46 Initialise system trusted keyrings
>Oct 25 01:15:46 Key type blacklist registered
>Oct 25 01:15:46 workingset: timestamp_bits=36 max_order=22 bucket_order=0
>Oct 25 01:15:46 zbud: loaded
>Oct 25 01:15:46 pstore: using deflate compression
>Oct 25 01:15:46 alg: No test for 842 (842-generic)
>Oct 25 01:15:46 alg: No test for 842 (842-scomp)
>Oct 25 01:15:46 NET: Registered protocol family 38
>Oct 25 01:15:46 Key type asymmetric registered
>Oct 25 01:15:46 Asymmetric key parser 'x509' registered
>Oct 25 01:15:46 Block layer SCSI generic (bsg) driver version 0.4 loaded (major 243)
>Oct 25 01:15:46 io scheduler noop registered
>Oct 25 01:15:46 io scheduler deadline registered
>Oct 25 01:15:46 io scheduler cfq registered (default)
>Oct 25 01:15:46 io scheduler mq-deadline registered
>Oct 25 01:15:46 atomic64_test: passed for x86-64 platform with CX8 and with SSE
>Oct 25 01:15:46 pciehp 0000:05:01.0:pcie204: Slot #1 AttnBtn- PwrCtrl- MRL- AttnInd- PwrInd- HotPlug+ Surprise+ Interlock- NoCompl+ LLActRep+
>Oct 25 01:15:46 pciehp 0000:05:02.0:pcie204: Slot #0 AttnBtn- PwrCtrl- MRL- AttnInd- PwrInd- HotPlug+ Surprise+ Interlock- NoCompl+ LLActRep+
>Oct 25 01:15:46 pciehp 0000:05:04.0:pcie204: Slot #4 AttnBtn- PwrCtrl- MRL- AttnInd- PwrInd- HotPlug+ Surprise+ Interlock- NoCompl+ LLActRep+
>Oct 25 01:15:46 pciehp 0000:7b:01.0:pcie204: Slot #1 AttnBtn- PwrCtrl- MRL- AttnInd- PwrInd- HotPlug+ Surprise+ Interlock- NoCompl+ LLActRep+
>Oct 25 01:15:46 pciehp 0000:7b:02.0:pcie204: Slot #0 AttnBtn- PwrCtrl- MRL- AttnInd- PwrInd- HotPlug+ Surprise+ Interlock- NoCompl+ LLActRep+
>Oct 25 01:15:46 pciehp 0000:7b:04.0:pcie204: Slot #4 AttnBtn- PwrCtrl- MRL- AttnInd- PwrInd- HotPlug+ Surprise+ Interlock- NoCompl+ LLActRep+
>Oct 25 01:15:46 efifb: probing for efifb
>Oct 25 01:15:46 efifb: framebuffer at 0xa0000000, using 27564k, total 27562k
>Oct 25 01:15:46 efifb: mode is 3360x2100x32, linelength=13440, pages=1
>Oct 25 01:15:46 efifb: scrolling: redraw
>Oct 25 01:15:46 efifb: Truecolor: size=8:8:8:8, shift=24:16:8:0
>Oct 25 01:15:46 Console: switching to colour frame buffer device 420x131
>Oct 25 01:15:46 fb0: EFI VGA frame buffer device
>Oct 25 01:15:46 intel_idle: MWAIT substates: 0x11142120
>Oct 25 01:15:46 intel_idle: v0.4.1 model 0x5E
>Oct 25 01:15:46 intel_idle: state C8 is disabled
>Oct 25 01:15:46 intel_idle: state C9 is disabled
>Oct 25 01:15:46 intel_idle: lapic_timer_reliable_states 0xffffffff
>Oct 25 01:15:46 ACPI: AC Adapter [ADP1] (off-line)
>Oct 25 01:15:46 input: Lid Switch as /devices/LNXSYSTM:00/LNXSYBUS:00/PNP0C0D:00/input/input0
>Oct 25 01:15:46 ACPI: Lid Switch [LID0]
>Oct 25 01:15:46 input: Power Button as /devices/LNXSYSTM:00/LNXSYBUS:00/PNP0C0C:00/input/input1
>Oct 25 01:15:46 ACPI: Power Button [PWRB]
>Oct 25 01:15:46 input: Sleep Button as /devices/LNXSYSTM:00/LNXSYBUS:00/PNP0C0E:00/input/input2
>Oct 25 01:15:46 ACPI: Sleep Button [SLPB]
>Oct 25 01:15:46 input: Power Button as /devices/LNXSYSTM:00/LNXPWRBN:00/input/input3
>Oct 25 01:15:46 ACPI: Power Button [PWRF]
>Oct 25 01:15:46 Serial: 8250/16550 driver, 32 ports, IRQ sharing enabled
>Oct 25 01:15:46 Non-volatile memory driver v1.3
>Oct 25 01:15:46 Linux agpgart interface v0.103
>Oct 25 01:15:46 libphy: Fixed MDIO Bus: probed
>Oct 25 01:15:46 ehci_hcd: USB 2.0 'Enhanced' Host Controller (EHCI) Driver
>Oct 25 01:15:46 ehci-pci: EHCI PCI platform driver
>Oct 25 01:15:46 ohci_hcd: USB 1.1 'Open' Host Controller (OHCI) Driver
>Oct 25 01:15:46 ohci-pci: OHCI PCI platform driver
>Oct 25 01:15:46 uhci_hcd: USB Universal Host Controller Interface driver
>Oct 25 01:15:46 xhci_hcd 0000:00:14.0: xHCI Host Controller
>Oct 25 01:15:46 xhci_hcd 0000:00:14.0: new USB bus registered, assigned bus number 1
>Oct 25 01:15:46 xhci_hcd 0000:00:14.0: hcc params 0x200077c1 hci version 0x100 quirks 0x0000000001109810
>Oct 25 01:15:46 xhci_hcd 0000:00:14.0: cache line size of 256 is not supported
>Oct 25 01:15:46 usb usb1: New USB device found, idVendor=1d6b, idProduct=0002, bcdDevice= 4.19
>Oct 25 01:15:46 usb usb1: New USB device strings: Mfr=3, Product=2, SerialNumber=1
>Oct 25 01:15:46 usb usb1: Product: xHCI Host Controller
>Oct 25 01:15:46 usb usb1: Manufacturer: Linux 4.19.0-rc8-drm xhci-hcd
>Oct 25 01:15:46 usb usb1: SerialNumber: 0000:00:14.0
>Oct 25 01:15:46 hub 1-0:1.0: USB hub found
>Oct 25 01:15:46 hub 1-0:1.0: 16 ports detected
>Oct 25 01:15:46 xhci_hcd 0000:00:14.0: xHCI Host Controller
>Oct 25 01:15:46 xhci_hcd 0000:00:14.0: new USB bus registered, assigned bus number 2
>Oct 25 01:15:46 xhci_hcd 0000:00:14.0: Host supports USB 3.0  SuperSpeed
>Oct 25 01:15:46 usb usb2: New USB device found, idVendor=1d6b, idProduct=0003, bcdDevice= 4.19
>Oct 25 01:15:46 usb usb2: New USB device strings: Mfr=3, Product=2, SerialNumber=1
>Oct 25 01:15:46 usb usb2: Product: xHCI Host Controller
>Oct 25 01:15:46 usb usb2: Manufacturer: Linux 4.19.0-rc8-drm xhci-hcd
>Oct 25 01:15:46 usb usb2: SerialNumber: 0000:00:14.0
>Oct 25 01:15:46 hub 2-0:1.0: USB hub found
>Oct 25 01:15:46 hub 2-0:1.0: 8 ports detected
>Oct 25 01:15:46 xhci_hcd 0000:07:00.0: xHCI Host Controller
>Oct 25 01:15:46 xhci_hcd 0000:07:00.0: new USB bus registered, assigned bus number 3
>Oct 25 01:15:46 xhci_hcd 0000:07:00.0: hcc params 0x200077c1 hci version 0x110 quirks 0x0000000000009810
>Oct 25 01:15:46 usb usb3: New USB device found, idVendor=1d6b, idProduct=0002, bcdDevice= 4.19
>Oct 25 01:15:46 usb usb3: New USB device strings: Mfr=3, Product=2, SerialNumber=1
>Oct 25 01:15:46 usb usb3: Product: xHCI Host Controller
>Oct 25 01:15:46 usb usb3: Manufacturer: Linux 4.19.0-rc8-drm xhci-hcd
>Oct 25 01:15:46 usb usb3: SerialNumber: 0000:07:00.0
>Oct 25 01:15:46 hub 3-0:1.0: USB hub found
>Oct 25 01:15:46 hub 3-0:1.0: 2 ports detected
>Oct 25 01:15:46 xhci_hcd 0000:07:00.0: xHCI Host Controller
>Oct 25 01:15:46 xhci_hcd 0000:07:00.0: new USB bus registered, assigned bus number 4
>Oct 25 01:15:46 xhci_hcd 0000:07:00.0: Host supports USB 3.1 Enhanced SuperSpeed
>Oct 25 01:15:46 usb usb4: New USB device found, idVendor=1d6b, idProduct=0003, bcdDevice= 4.19
>Oct 25 01:15:46 usb usb4: New USB device strings: Mfr=3, Product=2, SerialNumber=1
>Oct 25 01:15:46 usb usb4: Product: xHCI Host Controller
>Oct 25 01:15:46 usb usb4: Manufacturer: Linux 4.19.0-rc8-drm xhci-hcd
>Oct 25 01:15:46 usb usb4: SerialNumber: 0000:07:00.0
>Oct 25 01:15:46 hub 4-0:1.0: USB hub found
>Oct 25 01:15:46 hub 4-0:1.0: 2 ports detected
>Oct 25 01:15:46 xhci_hcd 0000:7d:00.0: xHCI Host Controller
>Oct 25 01:15:46 xhci_hcd 0000:7d:00.0: new USB bus registered, assigned bus number 5
>Oct 25 01:15:46 xhci_hcd 0000:7d:00.0: hcc params 0x200077c1 hci version 0x110 quirks 0x0000000000009810
>Oct 25 01:15:46 usb usb5: New USB device found, idVendor=1d6b, idProduct=0002, bcdDevice= 4.19
>Oct 25 01:15:46 usb usb5: New USB device strings: Mfr=3, Product=2, SerialNumber=1
>Oct 25 01:15:46 usb usb5: Product: xHCI Host Controller
>Oct 25 01:15:46 usb usb5: Manufacturer: Linux 4.19.0-rc8-drm xhci-hcd
>Oct 25 01:15:46 usb usb5: SerialNumber: 0000:7d:00.0
>Oct 25 01:15:46 hub 5-0:1.0: USB hub found
>Oct 25 01:15:46 hub 5-0:1.0: 2 ports detected
>Oct 25 01:15:46 xhci_hcd 0000:7d:00.0: xHCI Host Controller
>Oct 25 01:15:46 xhci_hcd 0000:7d:00.0: new USB bus registered, assigned bus number 6
>Oct 25 01:15:46 xhci_hcd 0000:7d:00.0: Host supports USB 3.1 Enhanced SuperSpeed
>Oct 25 01:15:46 usb usb6: New USB device found, idVendor=1d6b, idProduct=0003, bcdDevice= 4.19
>Oct 25 01:15:46 usb usb6: New USB device strings: Mfr=3, Product=2, SerialNumber=1
>Oct 25 01:15:46 usb usb6: Product: xHCI Host Controller
>Oct 25 01:15:46 usb usb6: Manufacturer: Linux 4.19.0-rc8-drm xhci-hcd
>Oct 25 01:15:46 usb usb6: SerialNumber: 0000:7d:00.0
>Oct 25 01:15:46 hub 6-0:1.0: USB hub found
>Oct 25 01:15:46 hub 6-0:1.0: 2 ports detected
>Oct 25 01:15:46 usbcore: registered new interface driver usbserial_generic
>Oct 25 01:15:46 usbserial: USB Serial support registered for generic
>Oct 25 01:15:46 i8042: PNP: No PS/2 controller found.
>Oct 25 01:15:46 mousedev: PS/2 mouse device common for all mice
>Oct 25 01:15:46 rtc_cmos 00:01: RTC can wake from S4
>Oct 25 01:15:46 rtc_cmos 00:01: registered as rtc0
>Oct 25 01:15:46 rtc_cmos 00:01: alarms up to one month, y3k, 242 bytes nvram, hpet irqs
>Oct 25 01:15:46 device-mapper: uevent: version 1.0.3
>Oct 25 01:15:46 device-mapper: ioctl: 4.39.0-ioctl (2018-04-03) initialised: dm-devel@redhat.com
>Oct 25 01:15:46 intel_pstate: Intel P-state driver initializing
>Oct 25 01:15:46 intel_pstate: HWP enabled
>Oct 25 01:15:46 hidraw: raw HID events driver (C) Jiri Kosina
>Oct 25 01:15:46 usbcore: registered new interface driver usbhid
>Oct 25 01:15:46 usbhid: USB HID core driver
>Oct 25 01:15:46 intel_pmc_core:  initialized
>Oct 25 01:15:46 drop_monitor: Initializing network drop monitor service
>Oct 25 01:15:46 Initializing XFRM netlink socket
>Oct 25 01:15:46 NET: Registered protocol family 10
>Oct 25 01:15:46 Segment Routing with IPv6
>Oct 25 01:15:46 mip6: Mobile IPv6
>Oct 25 01:15:46 NET: Registered protocol family 17
>Oct 25 01:15:46 RAS: Correctable Errors collector initialized.
>Oct 25 01:15:46 microcode: sig=0x506e3, pf=0x20, revision=0xc6
>Oct 25 01:15:46 microcode: Microcode Update Driver: v2.2.
>Oct 25 01:15:46 AVX2 version of gcm_enc/dec engaged.
>Oct 25 01:15:46 AES CTR mode by8 optimization enabled
>Oct 25 01:15:46 sched_clock: Marking stable (2360212464, -375038)->(2369117349, -9279923)
>Oct 25 01:15:46 registered taskstats version 1
>Oct 25 01:15:46 Loading compiled-in X.509 certificates
>Oct 25 01:15:46 Loaded X.509 cert 'Build time autogenerated kernel key: 78b553e7189bfc0d00f92073c01cf4efb3fd886d'
>Oct 25 01:15:46 zswap: loaded using pool lzo/zbud
>Oct 25 01:15:46 Key type big_key registered
>Oct 25 01:15:46 Key type encrypted registered
>Oct 25 01:15:46 ima: No TPM chip found, activating TPM-bypass!
>Oct 25 01:15:46 ima: Allocated hash algorithm: sha1
>Oct 25 01:15:46   Magic number: 6:470:271
>Oct 25 01:15:46 rtc_cmos 00:01: setting system clock to 2018-10-25 08:15:45 UTC (1540455345)
>Oct 25 01:15:46 Freeing unused kernel image memory: 3936K
>Oct 25 01:15:46 Write protecting the kernel read-only data: 22528k
>Oct 25 01:15:46 Freeing unused kernel image memory: 2012K
>Oct 25 01:15:46 Freeing unused kernel image memory: 1988K
>Oct 25 01:15:46 x86/mm: Checked W+X mappings: passed, no W+X pages found.
>Oct 25 01:15:46 rodata_test: all tests were successful
>Oct 25 01:15:46 x86/mm: Checking user space page tables
>Oct 25 01:15:46 x86/mm: Checked W+X mappings: passed, no W+X pages found.
>Oct 25 01:15:46 Run /init as init process
>Oct 25 01:15:46 usb 1-5: new high-speed USB device number 2 using xhci_hcd
>Oct 25 01:15:46 usb 1-5: New USB device found, idVendor=13b1, idProduct=003f, bcdDevice= 0.00
>Oct 25 01:15:46 usb 1-5: New USB device strings: Mfr=1, Product=2, SerialNumber=3
>Oct 25 01:15:46 usb 1-5: Product: WUSB6300
>Oct 25 01:15:46 usb 1-5: Manufacturer: Linksys
>Oct 25 01:15:46 usb 1-5: SerialNumber: 34
>Oct 25 01:15:46 random: systemd: uninitialized urandom read (16 bytes read)
>Oct 25 01:15:46 random: systemd: uninitialized urandom read (16 bytes read)
>Oct 25 01:15:46 random: systemd: uninitialized urandom read (16 bytes read)
>Oct 25 01:15:46 audit: type=1130 audit(1540455346.243:2): pid=1 uid=0 auid=4294967295 ses=4294967295 subj=kernel msg='unit=systemd-tmpfiles-setup-dev comm="systemd" exe="/usr/lib/systemd/systemd" hostname=? addr=? terminal=? res=success'
>Oct 25 01:15:46 audit: type=1130 audit(1540455346.292:3): pid=1 uid=0 auid=4294967295 ses=4294967295 subj=kernel msg='unit=systemd-vconsole-setup comm="systemd" exe="/usr/lib/systemd/systemd" hostname=? addr=? terminal=? res=success'
>Oct 25 01:15:46 audit: type=1131 audit(1540455346.292:4): pid=1 uid=0 auid=4294967295 ses=4294967295 subj=kernel msg='unit=systemd-vconsole-setup comm="systemd" exe="/usr/lib/systemd/systemd" hostname=? addr=? terminal=? res=success'
>Oct 25 01:15:46 audit: type=1130 audit(1540455346.332:5): pid=1 uid=0 auid=4294967295 ses=4294967295 subj=kernel msg='unit=dracut-cmdline comm="systemd" exe="/usr/lib/systemd/systemd" hostname=? addr=? terminal=? res=success'
>Oct 25 01:15:46 audit: type=1130 audit(1540455346.346:6): pid=1 uid=0 auid=4294967295 ses=4294967295 subj=kernel msg='unit=systemd-udevd comm="systemd" exe="/usr/lib/systemd/systemd" hostname=? addr=? terminal=? res=success'
>Oct 25 01:15:46 audit: type=1130 audit(1540455346.356:7): pid=1 uid=0 auid=4294967295 ses=4294967295 subj=kernel msg='unit=systemd-journald comm="systemd" exe="/usr/lib/systemd/systemd" hostname=? addr=? terminal=? res=success'
>Oct 25 01:15:46 video: module verification failed: signature and/or required key missing - tainting kernel
>Oct 25 01:15:46 audit: type=1130 audit(1540455346.564:8): pid=1 uid=0 auid=4294967295 ses=4294967295 subj=kernel msg='unit=systemd-udev-trigger comm="systemd" exe="/usr/lib/systemd/systemd" hostname=? addr=? terminal=? res=success'
>Oct 25 01:15:46 apple_ibridge: loading out-of-tree module taints kernel.
>Oct 25 01:15:46 audit: type=1130 audit(1540455346.593:9): pid=1 uid=0 auid=4294967295 ses=4294967295 subj=kernel msg='unit=plymouth-start comm="systemd" exe="/usr/lib/systemd/systemd" hostname=? addr=? terminal=? res=success'
>Oct 25 01:15:46 intel-lpss 0000:00:15.0: enabling device (0000 -> 0002)
>Oct 25 01:15:46 nvme nvme0: pci function 0000:02:00.0
>Oct 25 01:15:46 intel-lpss 0000:00:19.0: enabling device (0000 -> 0002)
>Oct 25 01:15:46 dw-apb-uart.1: ttyS4 at MMIO 0x8272a000 (irq = 21, base_baud = 115200) is a 16550A
>Oct 25 01:15:46 serial serial0: tty port ttyS4 registered
>Oct 25 01:15:46 kvmgt: Unknown symbol gfn_to_memslot (err -2)
>Oct 25 01:15:46 kvmgt: Unknown symbol vfio_pin_pages (err -2)
>Oct 25 01:15:46 kvmgt: Unknown symbol vfio_info_cap_shift (err -2)
>Oct 25 01:15:46 kvmgt: Unknown symbol vfio_set_irqs_validate_and_prepare (err -2)
>Oct 25 01:15:46 kvmgt: Unknown symbol vfio_device_put (err -2)
>Oct 25 01:15:46 kvmgt: Unknown symbol gfn_to_pfn (err -2)
>Oct 25 01:15:46 kvmgt: Unknown symbol mdev_from_dev (err -2)
>Oct 25 01:15:46 kvmgt: Unknown symbol kvm_put_kvm (err -2)
>Oct 25 01:15:46 kvmgt: Unknown symbol kvm_write_guest (err -2)
>Oct 25 01:15:46 kvmgt: Unknown symbol kvm_slot_page_track_remove_page (err -2)
>Oct 25 01:15:46 kvmgt: Unknown symbol kvm_page_track_register_notifier (err -2)
>Oct 25 01:15:46 kvmgt: Unknown symbol mdev_parent_dev (err -2)
>Oct 25 01:15:46 kvmgt: Unknown symbol vfio_unpin_pages (err -2)
>Oct 25 01:15:46 kvmgt: Unknown symbol kvm_is_visible_gfn (err -2)
>Oct 25 01:15:46 kvmgt: Unknown symbol kvm_page_track_unregister_notifier (err -2)
>Oct 25 01:15:46 kvmgt: Unknown symbol vfio_device_get_from_dev (err -2)
>Oct 25 01:15:46 kvmgt: Unknown symbol kvm_slot_page_track_add_page (err -2)
>Oct 25 01:15:46 kvmgt: Unknown symbol vfio_register_notifier (err -2)
>Oct 25 01:15:46 kvmgt: Unknown symbol vfio_info_add_capability (err -2)
>Oct 25 01:15:46 kvmgt: Unknown symbol mdev_get_drvdata (err -2)
>Oct 25 01:15:46 kvmgt: Unknown symbol mdev_register_device (err -2)
>Oct 25 01:15:46 kvmgt: Unknown symbol mdev_dev (err -2)
>Oct 25 01:15:46 kvmgt: Unknown symbol mdev_unregister_device (err -2)
>Oct 25 01:15:46 kvmgt: Unknown symbol vfio_unregister_notifier (err -2)
>Oct 25 01:15:46 kvmgt: Unknown symbol kvm_read_guest (err -2)
>Oct 25 01:15:46 kvmgt: Unknown symbol mdev_set_drvdata (err -2)
>Oct 25 01:15:46 kvmgt: Unknown symbol kvm_get_kvm (err -2)
>Oct 25 01:15:46 intel-lpss 0000:00:1e.0: enabling device (0000 -> 0002)
>Oct 25 01:15:46 dw-apb-uart.2: ttyS5 at MMIO 0x8272b000 (irq = 20, base_baud = 3000000) is a 16550A
>Oct 25 01:15:46 serial serial1: tty port ttyS5 registered
>Oct 25 01:15:46 intel-lpss 0000:00:1e.1: enabling device (0000 -> 0002)
>Oct 25 01:15:46 dw-apb-uart.3: ttyS6 at MMIO 0x8272c000 (irq = 21, base_baud = 115200) is a 16550A
>Oct 25 01:15:46 serial serial2: tty port ttyS6 registered
>Oct 25 01:15:46 apple-ibridge: registered driver 'apple-ib-touchbar'
>Oct 25 01:15:46 intel-lpss 0000:00:1e.2: enabling device (0000 -> 0002)
>Oct 25 01:15:46 intel-lpss 0000:00:1e.3: enabling device (0000 -> 0002)
>Oct 25 01:15:46 input: Apple SPI Keyboard as /devices/pci0000:00/0000:00:1e.3/pxa2xx-spi.5/spi_master/spi2/spi-APP000D:00/input/input4
>Oct 25 01:15:46 applespi: spi-device probe done: spi-APP000D:00
>Oct 25 01:15:46 input: Apple SPI Touchpad as /devices/pci0000:00/0000:00:1e.3/pxa2xx-spi.5/spi_master/spi2/spi-APP000D:00/input/input5
>Oct 25 01:15:46 applespi: modeswitch done.
>Oct 25 01:15:46 [drm:intel_pch_type [i915]] Found SunrisePoint PCH
>Oct 25 01:15:46 [drm:i915_driver_load [i915]] WOPCM size: 1024KiB
>Oct 25 01:15:46 [drm:intel_uc_init_early [i915]] enable_guc=0 (submission:no huc:no)
>Oct 25 01:15:46 [drm:i915_driver_load [i915]] guc_log_level=0 (enabled:no, verbose:no, verbosity:0)
>Oct 25 01:15:46 [drm:intel_power_domains_init [i915]] Allowed DC state mask 03
>Oct 25 01:15:46 [drm:i915_ggtt_probe_hw [i915]] GGTT size = 4096M
>Oct 25 01:15:46 [drm:i915_ggtt_probe_hw [i915]] GMADR size = 256M
>Oct 25 01:15:46 [drm:i915_ggtt_probe_hw [i915]] DSM size = 64M
>Oct 25 01:15:46 [drm] VT-d active for gfx access
>Oct 25 01:15:46 checking generic (a0000000 1aeb000) vs hw (a0000000 10000000)
>Oct 25 01:15:46 fb0: switching to inteldrmfb from EFI VGA
>Oct 25 01:15:46 Console: switching to colour dummy device 80x25
>Oct 25 01:15:46 [drm] Replacing VGA console driver
>Oct 25 01:15:46 [drm:i915_gem_init_stolen [i915]] GEN6_STOLEN_RESERVED = 7ff00017
>Oct 25 01:15:46 [drm:i915_gem_init_stolen [i915]] Memory reserved for graphics device: 65536K, usable: 64512K
>Oct 25 01:15:46 [drm:intel_gvt_init [i915]] GVT-g is disabled by kernel params
>Oct 25 01:15:46 [drm:intel_opregion_setup [i915]] graphic opregion physical addr: 0x7af97018
>Oct 25 01:15:46 [drm:intel_opregion_setup [i915]] Public ACPI methods supported
>Oct 25 01:15:46 [drm:intel_opregion_setup [i915]] SWSCI supported
>Oct 25 01:15:46 [drm:intel_opregion_setup [i915]] SWSCI GBDA callbacks 00040001, SBCB callbacks 00200001
>Oct 25 01:15:46 [drm:intel_opregion_setup [i915]] ASLE supported
>Oct 25 01:15:46 [drm:intel_opregion_setup [i915]] ASLE extension supported
>Oct 25 01:15:46 [drm:intel_opregion_setup [i915]] Found valid VBT in ACPI OpRegion (Mailbox #4)
>Oct 25 01:15:46 [drm:skl_dram_get_channel_info [i915]] (size:width:rank) L(8GB:X16:dual) S(0GB:X8:single)
>Oct 25 01:15:46 [drm:skl_dram_get_channel_info [i915]] (size:width:rank) L(8GB:X16:dual) S(0GB:X8:single)
>Oct 25 01:15:46 [drm:skl_dram_get_channels_info [i915]] memory configuration is Symmetric memory
>Oct 25 01:15:46 [drm:i915_driver_load.cold.17 [i915]] DRAM bandwidth:34133344 KBps, total-channels: 2
>Oct 25 01:15:46 [drm:i915_driver_load.cold.17 [i915]] DRAM rank: dual rank 16GB-dimm:no
>Oct 25 01:15:46 [drm] Supports vblank timestamp caching Rev 2 (21.10.2013).
>Oct 25 01:15:46 [drm] Driver supports precise vblank timestamp query.
>Oct 25 01:15:46 [drm:intel_bios_init [i915]] Set default to SSC at 120000 kHz
>Oct 25 01:15:46 [drm:intel_bios_init [i915]] VBT signature "$VBT SKYLAKE        ", BDB version 196
>Oct 25 01:15:46 [drm:intel_bios_init [i915]] BDB_GENERAL_FEATURES int_tv_support 0 int_crt_support 0 lvds_use_ssc 0 lvds_ssc_freq 120000 display_clock_mode 1 fdi_rx_polarity_inverted 0
>Oct 25 01:15:46 [drm:intel_bios_init [i915]] crt_ddc_bus_pin: 2
>Oct 25 01:15:46 [drm:intel_opregion_get_panel_type [i915]] Failed to get panel details from OpRegion (-22)
>Oct 25 01:15:46 [drm:intel_bios_init [i915]] Panel type: 2 (VBT)
>Oct 25 01:15:46 [drm:intel_bios_init [i915]] DRRS supported mode is static
>Oct 25 01:15:46 [drm:intel_bios_init [i915]] Found panel mode in BIOS VBT tables:
>Oct 25 01:15:46 [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1024x768" 0 65000 1024 1048 1184 1344 768 771 777 806 0x8 0xa
>Oct 25 01:15:46 [drm:intel_bios_init [i915]] VBT initial LVDS value 300
>Oct 25 01:15:46 [drm:intel_bios_init [i915]] VBT backlight PWM modulation frequency 200 Hz, active high, min brightness 0, level 255, controller 0
>Oct 25 01:15:46 [drm:intel_bios_init [i915]] DRRS State Enabled:1
>Oct 25 01:15:46 [drm:intel_bios_init [i915]] Skipping SDVO device mapping
>Oct 25 01:15:46 [drm:intel_bios_init [i915]] Port A VBT info: DP:1 HDMI:0 DVI:0 EDP:1 CRT:0
>Oct 25 01:15:46 [drm:intel_bios_init [i915]] VBT HDMI level shift for port A: 0
>Oct 25 01:15:46 [drm:intel_bios_init [i915]] Port C VBT info: DP:1 HDMI:1 DVI:1 EDP:0 CRT:0
>Oct 25 01:15:46 [drm:intel_bios_init [i915]] VBT HDMI level shift for port C: 8
>Oct 25 01:15:46 [drm:intel_bios_init [i915]] Port D VBT info: DP:1 HDMI:1 DVI:1 EDP:0 CRT:0
>Oct 25 01:15:46 [drm:intel_bios_init [i915]] VBT HDMI level shift for port D: 8
>Oct 25 01:15:46 [drm:intel_dsm_detect [i915]] no _DSM method for intel device
>Oct 25 01:15:46 [drm:intel_dsm_detect [i915]] no _DSM method for intel device
>Oct 25 01:15:46 [drm:i915_driver_load [i915]] rawclk rate: 24000 kHz
>Oct 25 01:15:46 [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 00
>Oct 25 01:15:46 [drm:intel_power_well_enable [i915]] enabling power well 1
>Oct 25 01:15:46 [drm:intel_power_well_enable [i915]] enabling MISC IO power well
>Oct 25 01:15:46 [drm:intel_dump_cdclk_state [i915]] Current CDCLK 675000 kHz, VCO 8100000 kHz, ref 24000 kHz, bypass 24000 kHz, voltage level 3
>Oct 25 01:15:46 [drm:intel_update_max_cdclk [i915]] Max CD clock rate: 675000 kHz
>Oct 25 01:15:46 [drm:skl_init_cdclk [i915]] Max dotclock rate: 675000 kHz
>Oct 25 01:15:46 [drm:intel_power_well_enable [i915]] enabling always-on
>Oct 25 01:15:46 [drm:intel_power_well_enable [i915]] enabling DC off
>Oct 25 01:15:46 [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 00
>Oct 25 01:15:46 [drm:intel_power_well_enable [i915]] enabling power well 2
>Oct 25 01:15:46 i915 0000:00:02.0: vgaarb: changed VGA decodes: olddecodes=io+mem,decodes=none:owns=io+mem
>Oct 25 01:15:46 [drm:intel_power_well_enable [i915]] enabling DDI A/E IO power well
>Oct 25 01:15:46 [drm:intel_power_well_enable [i915]] enabling DDI B IO power well
>Oct 25 01:15:46 [drm:intel_power_well_enable [i915]] enabling DDI C IO power well
>Oct 25 01:15:46 [drm:intel_power_well_enable [i915]] enabling DDI D IO power well
>Oct 25 01:15:46 [drm:intel_csr_ucode_init [i915]] Loading i915/skl_dmc_ver1_27.bin
>Oct 25 01:15:46 [drm] Finished loading DMC firmware i915/skl_dmc_ver1_27.bin (v1.27)
>Oct 25 01:15:46 [drm] Disabling framebuffer compression (FBC) to prevent screen flicker with VT-d enabled
>Oct 25 01:15:46 [drm:intel_fbc_init [i915]] Sanitized enable_fbc value: 0
>Oct 25 01:15:46 [drm:intel_print_wm_latency [i915]] Gen9 Plane WM0 latency 2 (2.0 usec)
>Oct 25 01:15:46 [drm:intel_print_wm_latency [i915]] Gen9 Plane WM1 latency 19 (19.0 usec)
>Oct 25 01:15:46 [drm:intel_print_wm_latency [i915]] Gen9 Plane WM2 latency 28 (28.0 usec)
>Oct 25 01:15:46 [drm:intel_print_wm_latency [i915]] Gen9 Plane WM3 latency 32 (32.0 usec)
>Oct 25 01:15:46 [drm:intel_print_wm_latency [i915]] Gen9 Plane WM4 latency 63 (63.0 usec)
>Oct 25 01:15:46 [drm:intel_print_wm_latency [i915]] Gen9 Plane WM5 latency 77 (77.0 usec)
>Oct 25 01:15:46 [drm:intel_print_wm_latency [i915]] Gen9 Plane WM6 latency 83 (83.0 usec)
>Oct 25 01:15:46 [drm:intel_print_wm_latency [i915]] Gen9 Plane WM7 latency 99 (99.0 usec)
>Oct 25 01:15:46 [drm:intel_modeset_init [i915]] 3 display pipes available.
>Oct 25 01:15:46 [drm:intel_dump_cdclk_state [i915]] Current CDCLK 675000 kHz, VCO 8100000 kHz, ref 24000 kHz, bypass 24000 kHz, voltage level 3
>Oct 25 01:15:46 [drm:intel_dp_init_connector [i915]] Adding eDP connector on port A
>Oct 25 01:15:46 [drm:intel_dp_init_connector [i915]] using AUX A for port A (VBT)
>Oct 25 01:15:46 [drm:intel_pps_dump_state [i915]] cur t1_t3 125 t8 2100 t9 2500 t10 740 t11_t12 6000
>Oct 25 01:15:46 [drm:intel_pps_dump_state [i915]] vbt t1_t3 2000 t8 10 t9 2000 t10 500 t11_t12 6000
>Oct 25 01:15:46 [drm:intel_dp_init_panel_power_sequencer [i915]] panel power up delay 200, power down delay 74, power cycle delay 600
>Oct 25 01:15:46 [drm:intel_dp_init_panel_power_sequencer [i915]] backlight on delay 210, off delay 250
>Oct 25 01:15:46 [drm:intel_dp_init_panel_power_sequencer_registers [i915]] panel power sequencer register settings: PP_ON 0x7d00001, PP_OFF 0x2e40001, PP_DIV 0x4af06
>Oct 25 01:15:46 [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>Oct 25 01:15:46 [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000000f
>Oct 25 01:15:46 [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 41 00 00 01 80 02 00 00 00 0f 0b 00
>Oct 25 01:15:46 [drm:drm_dp_read_desc [drm_kms_helper]] DP sink: OUI 00-10-fa dev-ID eD\025eaa HW-rev 1.0 SW-rev 2.15 quirks 0x0000
>Oct 25 01:15:46 [drm:intel_dp_init_connector [i915]] eDP DPCD: 02 83 97
>Oct 25 01:15:46 [drm:intel_psr_init_dpcd [i915]] eDP panel supports PSR version 1
>Oct 25 01:15:46 [drm:drm_add_edid_modes [drm]] ELD: no CEA Extension found
>Oct 25 01:15:46 [drm:drm_add_display_info [drm]] non_desktop set to 0
>Oct 25 01:15:46 [drm:drm_add_display_info [drm]] non_desktop set to 0
>Oct 25 01:15:46 [drm:intel_dp_init_connector [i915]] VBT doesn't support DRRS
>Oct 25 01:15:46 [drm:intel_panel_setup_backlight [i915]] Connector eDP-1 backlight initialized, enabled, brightness 2082/2777
>Oct 25 01:15:46 [drm:intel_modeset_init [i915]] VBT says port B is not DVI/HDMI/DP compatible, respect it
>Oct 25 01:15:46 [drm:intel_dp_init_connector [i915]] Adding DP connector on port C
>Oct 25 01:15:46 [drm:intel_dp_init_connector [i915]] using AUX C for port C (VBT)
>Oct 25 01:15:46 [drm:intel_hdmi_init_connector [i915]] Adding HDMI connector on port C
>Oct 25 01:15:46 [drm:intel_hdmi_init_connector [i915]] Using DDC pin 0x4 for port C (VBT)
>Oct 25 01:15:46 [drm:intel_dp_init_connector [i915]] Adding DP connector on port D
>Oct 25 01:15:46 [drm:intel_dp_init_connector [i915]] using AUX D for port D (VBT)
>Oct 25 01:15:46 [drm:intel_hdmi_init_connector [i915]] Adding HDMI connector on port D
>Oct 25 01:15:46 [drm:intel_hdmi_init_connector [i915]] Using DDC pin 0x6 for port D (VBT)
>Oct 25 01:15:46 [drm:intel_modeset_setup_hw_state [i915]] [CRTC:45:pipe A] hw state readout: enabled
>Oct 25 01:15:46 [drm:intel_modeset_setup_hw_state [i915]] [CRTC:63:pipe B] hw state readout: disabled
>Oct 25 01:15:46 [drm:intel_modeset_setup_hw_state [i915]] [CRTC:81:pipe C] hw state readout: disabled
>Oct 25 01:15:46 [drm:intel_modeset_setup_hw_state [i915]] [PLANE:28:plane 1A] hw state readout: enabled, pipe A
>Oct 25 01:15:46 [drm:intel_modeset_setup_hw_state [i915]] [PLANE:35:plane 2A] hw state readout: disabled, pipe A
>Oct 25 01:15:46 [drm:intel_modeset_setup_hw_state [i915]] [PLANE:42:cursor A] hw state readout: disabled, pipe A
>Oct 25 01:15:46 [drm:intel_modeset_setup_hw_state [i915]] [PLANE:46:plane 1B] hw state readout: disabled, pipe B
>Oct 25 01:15:46 [drm:intel_modeset_setup_hw_state [i915]] [PLANE:53:plane 2B] hw state readout: disabled, pipe B
>Oct 25 01:15:46 [drm:intel_modeset_setup_hw_state [i915]] [PLANE:60:cursor B] hw state readout: disabled, pipe B
>Oct 25 01:15:46 [drm:intel_modeset_setup_hw_state [i915]] [PLANE:64:plane 1C] hw state readout: disabled, pipe C
>Oct 25 01:15:46 [drm:intel_modeset_setup_hw_state [i915]] [PLANE:71:plane 2C] hw state readout: disabled, pipe C
>Oct 25 01:15:46 [drm:intel_modeset_setup_hw_state [i915]] [PLANE:78:cursor C] hw state readout: disabled, pipe C
>Oct 25 01:15:46 [drm:intel_modeset_setup_hw_state [i915]] DPLL 0 hw state readout: crtc_mask 0x00000001, on 1
>Oct 25 01:15:46 [drm:intel_modeset_setup_hw_state [i915]] DPLL 1 hw state readout: crtc_mask 0x00000000, on 0
>Oct 25 01:15:46 [drm:intel_modeset_setup_hw_state [i915]] DPLL 2 hw state readout: crtc_mask 0x00000000, on 0
>Oct 25 01:15:46 [drm:intel_modeset_setup_hw_state [i915]] DPLL 3 hw state readout: crtc_mask 0x00000000, on 0
>Oct 25 01:15:46 [drm:intel_ddi_get_config [i915]] pipe has 30 bpp for eDP panel, overriding BIOS-provided max 18 bpp
>Oct 25 01:15:46 [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:82:DDI A] hw state readout: enabled, pipe A
>Oct 25 01:15:46 [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:89:DDI C] hw state readout: disabled, pipe A
>Oct 25 01:15:46 [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:91:DP-MST A] hw state readout: disabled, pipe A
>Oct 25 01:15:46 [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:92:DP-MST B] hw state readout: disabled, pipe B
>Oct 25 01:15:46 [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:93:DP-MST C] hw state readout: disabled, pipe C
>Oct 25 01:15:46 [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:100:DDI D] hw state readout: disabled, pipe A
>Oct 25 01:15:46 [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:102:DP-MST A] hw state readout: disabled, pipe A
>Oct 25 01:15:46 [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:103:DP-MST B] hw state readout: disabled, pipe B
>Oct 25 01:15:46 [drm:intel_modeset_setup_hw_state [i915]] [ENCODER:104:DP-MST C] hw state readout: disabled, pipe C
>Oct 25 01:15:46 [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:83:eDP-1] hw state readout: enabled
>Oct 25 01:15:46 [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:90:DP-1] hw state readout: disabled
>Oct 25 01:15:46 [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:96:HDMI-A-1] hw state readout: disabled
>Oct 25 01:15:46 [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:101:DP-2] hw state readout: disabled
>Oct 25 01:15:46 [drm:intel_modeset_setup_hw_state [i915]] [CONNECTOR:106:HDMI-A-2] hw state readout: disabled
>Oct 25 01:15:46 [drm:drm_atomic_set_mode_for_crtc [drm]] Set [MODE:2880x1800] for [CRTC:45:pipe A] state 00000000d7f9cfed
>Oct 25 01:15:46 [drm:intel_dump_pipe_config [i915]] [CRTC:45:pipe A][setup_hw_state]
>Oct 25 01:15:46 [drm:intel_dump_pipe_config [i915]] output_types: EDP (0x100)
>Oct 25 01:15:46 [drm:intel_dump_pipe_config [i915]] output format: RGB
>Oct 25 01:15:46 [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 30, dithering: 0
>Oct 25 01:15:46 [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 7983741, gmch_n: 8388608, link_m: 532249, link_n: 524288, tu: 64
>Oct 25 01:15:46 [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>Oct 25 01:15:46 [drm:intel_dump_pipe_config [i915]] requested mode:
>Oct 25 01:15:46 [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"2880x1800" 60 328919 3360 2888 2920 2960 2100 1838 1846 1852 0x40 0x9
>Oct 25 01:15:46 [drm:intel_dump_pipe_config [i915]] adjusted mode:
>Oct 25 01:15:46 [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"2880x1800" 60 328919 2880 2888 2920 2960 1800 1838 1846 1852 0x40 0x9
>Oct 25 01:15:46 [drm:intel_dump_pipe_config [i915]] crtc timings: 328919 2880 2888 2920 2960 1800 1838 1846 1852, type: 0x40 flags: 0x9
>Oct 25 01:15:46 [drm:intel_dump_pipe_config [i915]] port clock: 324000, pipe src size: 3360x2100, pixel rate 447695
>Oct 25 01:15:46 [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x80000000, scaler_id: 0
>Oct 25 01:15:46 [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x0b400708, enabled
>Oct 25 01:15:46 [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>Oct 25 01:15:46 [drm:intel_dump_pipe_config [i915]] dpll_hw_state: ctrl1: 0x7, cfgcr1: 0x0, cfgcr2: 0x0
>Oct 25 01:15:46 [drm:intel_dump_pipe_config [i915]] planes on this crtc
>Oct 25 01:15:46 [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 1A] disabled, scaler_id = -1
>Oct 25 01:15:46 [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 2A] disabled, scaler_id = -1
>Oct 25 01:15:46 [drm:intel_dump_pipe_config [i915]] [PLANE:42:cursor A] disabled, scaler_id = -1
>Oct 25 01:15:46 [drm:intel_dump_pipe_config [i915]] [CRTC:63:pipe B][setup_hw_state]
>Oct 25 01:15:46 [drm:intel_dump_pipe_config [i915]] output_types:  (0x0)
>Oct 25 01:15:46 [drm:intel_dump_pipe_config [i915]] output format: Invalid
>Oct 25 01:15:46 [drm:intel_dump_pipe_config [i915]] cpu_transcoder: B, pipe bpp: 0, dithering: 0
>Oct 25 01:15:46 [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>Oct 25 01:15:46 [drm:intel_dump_pipe_config [i915]] requested mode:
>Oct 25 01:15:46 [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>Oct 25 01:15:46 [drm:intel_dump_pipe_config [i915]] adjusted mode:
>Oct 25 01:15:46 [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>Oct 25 01:15:46 [drm:intel_dump_pipe_config [i915]] crtc timings: 0 0 0 0 0 0 0 0 0, type: 0x0 flags: 0x0
>Oct 25 01:15:46 [drm:intel_dump_pipe_config [i915]] port clock: 0, pipe src size: 0x0, pixel rate 0
>Oct 25 01:15:46 [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>Oct 25 01:15:46 [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>Oct 25 01:15:46 [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>Oct 25 01:15:46 [drm:intel_dump_pipe_config [i915]] dpll_hw_state: ctrl1: 0x0, cfgcr1: 0x0, cfgcr2: 0x0
>Oct 25 01:15:46 [drm:intel_dump_pipe_config [i915]] planes on this crtc
>Oct 25 01:15:46 [drm:intel_dump_pipe_config [i915]] [PLANE:46:plane 1B] disabled, scaler_id = -1
>Oct 25 01:15:46 [drm:intel_dump_pipe_config [i915]] [PLANE:53:plane 2B] disabled, scaler_id = -1
>Oct 25 01:15:46 [drm:intel_dump_pipe_config [i915]] [PLANE:60:cursor B] disabled, scaler_id = -1
>Oct 25 01:15:46 [drm:intel_dump_pipe_config [i915]] [CRTC:81:pipe C][setup_hw_state]
>Oct 25 01:15:46 [drm:intel_dump_pipe_config [i915]] output_types:  (0x0)
>Oct 25 01:15:46 [drm:intel_dump_pipe_config [i915]] output format: Invalid
>Oct 25 01:15:46 [drm:intel_dump_pipe_config [i915]] cpu_transcoder: C, pipe bpp: 0, dithering: 0
>Oct 25 01:15:46 [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>Oct 25 01:15:46 [drm:intel_dump_pipe_config [i915]] requested mode:
>Oct 25 01:15:46 [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>Oct 25 01:15:46 [drm:intel_dump_pipe_config [i915]] adjusted mode:
>Oct 25 01:15:46 [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>Oct 25 01:15:46 [drm:intel_dump_pipe_config [i915]] crtc timings: 0 0 0 0 0 0 0 0 0, type: 0x0 flags: 0x0
>Oct 25 01:15:46 [drm:intel_dump_pipe_config [i915]] port clock: 0, pipe src size: 0x0, pixel rate 0
>Oct 25 01:15:46 [drm:intel_dump_pipe_config [i915]] num_scalers: 1, scaler_users: 0x0, scaler_id: -1
>Oct 25 01:15:46 [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>Oct 25 01:15:46 [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>Oct 25 01:15:46 [drm:intel_dump_pipe_config [i915]] dpll_hw_state: ctrl1: 0x0, cfgcr1: 0x0, cfgcr2: 0x0
>Oct 25 01:15:46 [drm:intel_dump_pipe_config [i915]] planes on this crtc
>Oct 25 01:15:46 [drm:intel_dump_pipe_config [i915]] [PLANE:64:plane 1C] disabled, scaler_id = -1
>Oct 25 01:15:46 [drm:intel_dump_pipe_config [i915]] [PLANE:71:plane 2C] disabled, scaler_id = -1
>Oct 25 01:15:46 [drm:intel_dump_pipe_config [i915]] [PLANE:78:cursor C] disabled, scaler_id = -1
>Oct 25 01:15:46 [drm:skylake_get_initial_plane_config [i915]] pipe A/plane 1A with fb: size=3360x2100@32, offset=0, pitch 13440, size 0x1b12000
>Oct 25 01:15:46 [drm:i915_gem_object_create_stolen_for_preallocated [i915]] creating preallocated stolen object: stolen_offset=0x0000000000000000, gtt_offset=0x0000000000000000, size=0x0000000001b12000
>Oct 25 01:15:46 [drm:intel_alloc_initial_plane_obj.isra.148 [i915]] initial plane fb obj 00000000e4010146
>Oct 25 01:15:46 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000d8b189b6
>Oct 25 01:15:46 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000025c715f state to 00000000d8b189b6
>Oct 25 01:15:46 [drm:drm_atomic_add_affected_planes [drm]] Adding all current planes for [CRTC:45:pipe A] to 00000000d8b189b6
>Oct 25 01:15:46 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 000000006d00e21c state to 00000000d8b189b6
>Oct 25 01:15:46 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:63:pipe B] 0000000036ed9464 state to 00000000d8b189b6
>Oct 25 01:15:46 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000d8b189b6
>Oct 25 01:15:46 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 0000000036ed9464 state to 00000000d8b189b6
>Oct 25 01:15:46 [drm:drm_atomic_add_affected_planes [drm]] Adding all current planes for [CRTC:45:pipe A] to 00000000d8b189b6
>Oct 25 01:15:46 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 000000006d00e21c state to 00000000d8b189b6
>Oct 25 01:15:46 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:63:pipe B] 00000000025c715f state to 00000000d8b189b6
>Oct 25 01:15:46 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:81:pipe C] 00000000d0ba5f75 state to 00000000d8b189b6
>Oct 25 01:15:46 [drm:drm_atomic_check_only [drm]] checking 00000000d8b189b6
>Oct 25 01:15:46 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 109
>Oct 25 01:15:46 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:15:46 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45
>Oct 25 01:15:46 [drm:drm_atomic_check_only [drm]] atomic driver check for 00000000d8b189b6 failed: -35
>Oct 25 01:15:46 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000d8b189b6
>Oct 25 01:15:46 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000d0ba5f75 state to 00000000d8b189b6
>Oct 25 01:15:46 [drm:drm_atomic_add_affected_planes [drm]] Adding all current planes for [CRTC:45:pipe A] to 00000000d8b189b6
>Oct 25 01:15:46 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 000000006d00e21c state to 00000000d8b189b6
>Oct 25 01:15:46 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:63:pipe B] 00000000025c715f state to 00000000d8b189b6
>Oct 25 01:15:46 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:81:pipe C] 0000000036ed9464 state to 00000000d8b189b6
>Oct 25 01:15:46 [drm:drm_atomic_check_only [drm]] checking 00000000d8b189b6
>Oct 25 01:15:46 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 109
>Oct 25 01:15:46 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:15:46 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45
>Oct 25 01:15:46 [drm:skl_compute_wm [i915]] [PLANE:28:plane 1A] ddb (25 - 881) -> (0 - 860)
>Oct 25 01:15:46 [drm:skl_compute_wm [i915]] [PLANE:42:cursor A] ddb (0 - 0) -> (860 - 892)
>Oct 25 01:15:46 [drm:drm_atomic_commit [drm]] committing 00000000d8b189b6
>Oct 25 01:15:46 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:15:46 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:15:46 [drm:i915_gem_init_ggtt [i915]] clearing unused GTT space: [1b13000, 100000000]
>Oct 25 01:15:46 [drm:intel_ctx_workarounds_init [i915]] Number of context specific w/a: 9
>Oct 25 01:15:46 [drm:i915_gem_contexts_init [i915]] logical context support initialized
>Oct 25 01:15:46 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000d8b189b6
>Oct 25 01:15:46 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000d8b189b6
>Oct 25 01:15:46 [drm:intel_fbdev_init [i915]] found possible fb from plane A
>Oct 25 01:15:46 [drm:intel_fbdev_init [i915]] pipe B not active or no fb, skipping
>Oct 25 01:15:46 [drm:intel_fbdev_init [i915]] pipe C not active or no fb, skipping
>Oct 25 01:15:46 [drm:intel_fbdev_init [i915]] checking plane A for BIOS fb
>Oct 25 01:15:46 [drm:intel_fbdev_init [i915]] pipe A area: 2880x1800, bpp: 32, size: 24514560
>Oct 25 01:15:46 [drm:intel_fbdev_init [i915]] fb big enough for plane A (28385280 >= 24514560)
>Oct 25 01:15:46 [drm:intel_fbdev_init [i915]] pipe B not active, skipping
>Oct 25 01:15:46 [drm:intel_fbdev_init [i915]] pipe C not active, skipping
>Oct 25 01:15:46 [drm:intel_fbdev_init [i915]] using BIOS fb for initial console
>Oct 25 01:15:46 [drm:intel_backlight_device_register [i915]] Connector eDP-1 backlight sysfs interface registered
>Oct 25 01:15:46 [drm:intel_dp_connector_register [i915]] registering DPDDC-A bus for card0-eDP-1
>Oct 25 01:15:46 [drm:intel_dp_connector_register [i915]] registering DPDDC-C bus for card0-DP-1
>Oct 25 01:15:46 [drm:intel_dp_connector_register [i915]] registering DPDDC-D bus for card0-DP-2
>Oct 25 01:15:46 [drm] Initialized i915 1.6.0 20180921 for 0000:00:02.0 on minor 0
>Oct 25 01:15:46 [drm:intel_opregion_register [i915]] 5 outputs detected
>Oct 25 01:15:46 [Firmware Bug]: ACPI(GFX0) defines _DOD but not _DOS
>Oct 25 01:15:46 ACPI: Video Device [GFX0] (multi-head: yes  rom: no  post: no)
>Oct 25 01:15:46 acpi device:02: registered as cooling_device8
>Oct 25 01:15:46 input: Video Bus as /devices/LNXSYSTM:00/LNXSYBUS:00/PNP0A08:00/device:01/LNXVIDEO:00/input/input6
>Oct 25 01:15:46 ACPI: Video Device [IGPU] (multi-head: yes  rom: no  post: no)
>Oct 25 01:15:46 [drm:asle_work [i915]] bclp = 0x80000002
>Oct 25 01:15:46 [drm:asle_work [i915]] updating opregion backlight 2/255
>Oct 25 01:15:46 [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 22
>Oct 25 01:15:46 [drm:asle_work [i915]] No request on ASLC interrupt 0x00000000
>Oct 25 01:15:46 acpi device:7e: registered as cooling_device9
>Oct 25 01:15:46 input: Video Bus as /devices/LNXSYSTM:00/LNXSYBUS:00/PNP0A08:00/LNXVIDEO:01/input/input7
>Oct 25 01:15:46 [drm:intel_power_well_disable [i915]] disabling DDI D IO power well
>Oct 25 01:15:46 [drm:drm_setup_crtcs [drm_kms_helper]] 
>Oct 25 01:15:46 [drm:intel_power_well_disable [i915]] disabling DDI C IO power well
>Oct 25 01:15:46 [drm:intel_power_well_disable [i915]] disabling DDI B IO power well
>Oct 25 01:15:46 [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:83:eDP-1]
>Oct 25 01:15:46 [drm:intel_power_well_disable [i915]] disabling power well 2
>Oct 25 01:15:46 [drm:intel_dp_detect [i915]] [CONNECTOR:83:eDP-1]
>Oct 25 01:15:46 i915 device info: pciid=0x191b rev=0x06 platform=SKYLAKE gen=9
>Oct 25 01:15:46 i915 device info: is_mobile: no
>Oct 25 01:15:46 i915 device info: is_lp: no
>Oct 25 01:15:46 i915 device info: is_alpha_support: no
>Oct 25 01:15:46 i915 device info: has_64bit_reloc: yes
>Oct 25 01:15:46 i915 device info: has_csr: yes
>Oct 25 01:15:46 i915 device info: has_ddi: yes
>Oct 25 01:15:46 [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>Oct 25 01:15:46 i915 device info: has_dp_mst: yes
>Oct 25 01:15:46 i915 device info: has_reset_engine: yes
>Oct 25 01:15:46 i915 device info: has_fbc: no
>Oct 25 01:15:46 i915 device info: has_fpga_dbg: yes
>Oct 25 01:15:46 i915 device info: has_gmch_display: no
>Oct 25 01:15:46 [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>Oct 25 01:15:46 i915 device info: has_guc: yes
>Oct 25 01:15:46 [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>Oct 25 01:15:46 i915 device info: has_guc_ct: no
>Oct 25 01:15:46 i915 device info: has_hotplug: yes
>Oct 25 01:15:46 i915 device info: has_l3_dpf: no
>Oct 25 01:15:46 i915 device info: has_llc: yes
>Oct 25 01:15:46 i915 device info: has_logical_ring_contexts: yes
>Oct 25 01:15:46 i915 device info: has_logical_ring_elsq: no
>Oct 25 01:15:46 i915 device info: has_logical_ring_preemption: yes
>Oct 25 01:15:46 i915 device info: has_overlay: no
>Oct 25 01:15:46 i915 device info: has_pooled_eu: no
>Oct 25 01:15:46 i915 device info: has_psr: yes
>Oct 25 01:15:46 i915 device info: has_rc6: yes
>Oct 25 01:15:46 i915 device info: has_rc6p: no
>Oct 25 01:15:46 i915 device info: has_runtime_pm: yes
>Oct 25 01:15:46 i915 device info: has_snoop: no
>Oct 25 01:15:46 i915 device info: has_coherent_ggtt: yes
>Oct 25 01:15:46 i915 device info: unfenced_needs_alignment: no
>Oct 25 01:15:46 i915 device info: cursor_needs_physical: no
>Oct 25 01:15:46 i915 device info: hws_needs_physical: no
>Oct 25 01:15:46 i915 device info: overlay_needs_physical: no
>Oct 25 01:15:46 i915 device info: supports_tv: no
>Oct 25 01:15:46 i915 device info: has_ipc: no
>Oct 25 01:15:46 i915 device info: slice total: 1, mask=0001
>Oct 25 01:15:46 i915 device info: subslice total: 3
>Oct 25 01:15:46 i915 device info: slice0: 3 subslices, mask=0007
>Oct 25 01:15:46 i915 device info: slice1: 0 subslices, mask=0000
>Oct 25 01:15:46 i915 device info: slice2: 0 subslices, mask=0000
>Oct 25 01:15:46 i915 device info: EU total: 24
>Oct 25 01:15:46 i915 device info: EU per subslice: 8
>Oct 25 01:15:46 i915 device info: has slice power gating: no
>Oct 25 01:15:46 i915 device info: has subslice power gating: no
>Oct 25 01:15:46 i915 device info: has EU power gating: yes
>Oct 25 01:15:46 i915 device info: CS timestamp frequency: 12000 kHz
>Oct 25 01:15:46 [drm:drm_dp_read_desc [drm_kms_helper]] DP sink: OUI 00-10-fa dev-ID eD\025eaa HW-rev 1.0 SW-rev 2.15 quirks 0x0000
>Oct 25 01:15:46 [drm:intel_dp_detect [i915]] MST support? port A: no, sink: no, modparam: yes
>Oct 25 01:15:46 [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:83:eDP-1] status updated from unknown to connected
>Oct 25 01:15:46 [drm:drm_add_display_info [drm]] non_desktop set to 0
>Oct 25 01:15:46 [drm:drm_add_edid_modes [drm]] ELD: no CEA Extension found
>Oct 25 01:15:46 [drm:drm_add_display_info [drm]] non_desktop set to 0
>Oct 25 01:15:46 [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:83:eDP-1] probed modes :
>Oct 25 01:15:46 [drm:drm_mode_debug_printmodeline [drm]] Modeline 84:"2880x1800" 60 328920 2880 2888 2920 2960 1800 1838 1846 1852 0x48 0x9
>Oct 25 01:15:46 [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:90:DP-1]
>Oct 25 01:15:46 [drm:intel_dp_detect [i915]] [CONNECTOR:90:DP-1]
>Oct 25 01:15:46 [drm:intel_power_well_enable [i915]] enabling power well 2
>Oct 25 01:15:46 [drm:intel_power_well_disable [i915]] disabling power well 2
>Oct 25 01:15:46 [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:90:DP-1] status updated from unknown to disconnected
>Oct 25 01:15:46 [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:90:DP-1] disconnected
>Oct 25 01:15:46 [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:96:HDMI-A-1]
>Oct 25 01:15:46 [drm:intel_hdmi_detect [i915]] [CONNECTOR:96:HDMI-A-1]
>Oct 25 01:15:46 WARNING: CPU: 5 PID: 74 at drivers/pci/msi.c:1259 pci_irq_get_affinity+0x66/0x80
>Oct 25 01:15:46 Modules linked in: i915(E) spi_pxa2xx_platform(E) apple_ib_tb(OE) i2c_algo_bit(E) drm_kms_helper(E) crct10dif_pclmul(E) crc32_pclmul(E) crc32c_intel(E) drm(E) ghash_clmulni_intel(E) nvme(E) nvme_core(E) intel_lpss_pci(E) intel_lpss(E) applespi(OE) apple_ibridge(OE) video(E)
>Oct 25 01:15:46 CPU: 5 PID: 74 Comm: kworker/u16:1 Tainted: G           OE     4.19.0-rc8-drm #14
>Oct 25 01:15:46 Hardware name: Apple Inc. MacBookPro13,3/Mac-A5C67F76ED83108C, BIOS MBP133.88Z.0247.B00.1806261159 06/26/2018
>Oct 25 01:15:46 Workqueue: nvme-reset-wq nvme_reset_work [nvme]
>Oct 25 01:15:46 RIP: 0010:pci_irq_get_affinity+0x66/0x80
>Oct 25 01:15:46 Code: 0b 31 c0 c3 83 e2 02 48 c7 c0 30 76 7a b9 74 26 48 8b 87 48 04 00 00 48 85 c0 74 0e 48 8b 50 30 48 85 d2 74 05 39 70 14 77 05 <0f> 0b 31 c0 c3 48 63 f6 48 8d 04 f2 c3 48 8b 40 30 c3 0f 1f 84 00
>Oct 25 01:15:46 RSP: 0018:ffffabe0c1babce8 EFLAGS: 00010246
>Oct 25 01:15:46 RAX: ffff9df563270ea0 RBX: 0000000000000000 RCX: 0000000000000040
>Oct 25 01:15:46 RDX: 0000000000000000 RSI: 0000000000000000 RDI: ffff9df56b31a000
>Oct 25 01:15:46 RBP: ffff9df56bb64000 R08: ffff9df56e7e6160 R09: ffff9df56d807800
>Oct 25 01:15:46 R10: 0000000000000001 R11: 0000000000000000 R12: ffff9df56bb64008
>Oct 25 01:15:46 R13: 0000000000000000 R14: ffff9df56b31a000 R15: 00000000ffffffff
>Oct 25 01:15:46 FS:  0000000000000000(0000) GS:ffff9df56e600000(0000) knlGS:0000000000000000
>Oct 25 01:15:46 CS:  0010 DS: 0000 ES: 0000 CR0: 0000000080050033
>Oct 25 01:15:46 CR2: 00007f72adb52018 CR3: 00000003a3612006 CR4: 00000000003606e0
>Oct 25 01:15:46 DR0: 0000000000000000 DR1: 0000000000000000 DR2: 0000000000000000
>Oct 25 01:15:46 DR3: 0000000000000000 DR6: 00000000fffe0ff0 DR7: 0000000000000400
>Oct 25 01:15:46 Call Trace:
>Oct 25 01:15:46  blk_mq_pci_map_queues+0x37/0xc0
>Oct 25 01:15:46  blk_mq_alloc_tag_set+0xe3/0x220
>Oct 25 01:15:46  nvme_reset_work+0x113e/0x18e1 [nvme]
>Oct 25 01:15:46  process_one_work+0x24c/0x5a0
>Oct 25 01:15:46  worker_thread+0x3c/0x390
>Oct 25 01:15:46  ? rescuer_thread+0x360/0x360
>Oct 25 01:15:46  kthread+0x120/0x140
>Oct 25 01:15:46  ? kthread_create_worker_on_cpu+0x70/0x70
>Oct 25 01:15:46  ret_from_fork+0x3a/0x50
>Oct 25 01:15:46 irq event stamp: 1262
>Oct 25 01:15:46 hardirqs last  enabled at (1261): [<ffffffffb8a54b1b>] _raw_spin_unlock_irqrestore+0x4b/0x60
>Oct 25 01:15:46 hardirqs last disabled at (1262): [<ffffffffb8003828>] trace_hardirqs_off_thunk+0x1a/0x1c
>Oct 25 01:15:46 softirqs last  enabled at (984): [<ffffffffb88969b1>] peernet2id+0x51/0x80
>Oct 25 01:15:46 softirqs last disabled at (982): [<ffffffffb8896992>] peernet2id+0x32/0x80
>Oct 25 01:15:46 WARNING: CPU: 5 PID: 74 at drivers/pci/msi.c:1259 pci_irq_get_affinity+0x66/0x80
>Oct 25 01:15:46 ---[ end trace dbb7f0af966ae830 ]---
>Oct 25 01:15:46  nvme0n1: p1 p2 p3 p4 p5
>Oct 25 01:15:46 [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] timed out, falling back to bit banging on pin 4
>Oct 25 01:15:46 [drm:drm_do_probe_ddc_edid [drm]] drm: skipping non-existent adapter i915 gmbus dpc
>Oct 25 01:15:46 [drm:intel_hdmi_set_edid [i915]] HDMI GMBUS EDID read failed, retry using GPIO bit-banging
>Oct 25 01:15:46 [drm:intel_gmbus_force_bit [i915]] enabling bit-banging on i915 gmbus dpc. force bit now 1
>Oct 25 01:15:46 [drm:drm_do_probe_ddc_edid [drm]] drm: skipping non-existent adapter i915 gmbus dpc
>Oct 25 01:15:46 [drm:intel_gmbus_force_bit [i915]] disabling bit-banging on i915 gmbus dpc. force bit now 0
>Oct 25 01:15:46 [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] timed out, falling back to bit banging on pin 4
>Oct 25 01:15:46 [drm:drm_dp_dual_mode_detect [drm_kms_helper]] DP dual mode HDMI ID:  (err -6)
>Oct 25 01:15:46 [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:96:HDMI-A-1] status updated from unknown to disconnected
>Oct 25 01:15:46 [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:96:HDMI-A-1] disconnected
>Oct 25 01:15:46 [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:101:DP-2]
>Oct 25 01:15:46 [drm:intel_dp_detect [i915]] [CONNECTOR:101:DP-2]
>Oct 25 01:15:46 [drm:intel_power_well_enable [i915]] enabling power well 2
>Oct 25 01:15:46 [drm:intel_power_well_disable [i915]] disabling power well 2
>Oct 25 01:15:46 [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:101:DP-2] status updated from unknown to disconnected
>Oct 25 01:15:46 [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:101:DP-2] disconnected
>Oct 25 01:15:46 [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:106:HDMI-A-2]
>Oct 25 01:15:46 [drm:intel_hdmi_detect [i915]] [CONNECTOR:106:HDMI-A-2]
>Oct 25 01:15:46 [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] timed out, falling back to bit banging on pin 6
>Oct 25 01:15:46 [drm:drm_do_probe_ddc_edid [drm]] drm: skipping non-existent adapter i915 gmbus dpd
>Oct 25 01:15:46 [drm:intel_hdmi_set_edid [i915]] HDMI GMBUS EDID read failed, retry using GPIO bit-banging
>Oct 25 01:15:46 [drm:intel_gmbus_force_bit [i915]] enabling bit-banging on i915 gmbus dpd. force bit now 1
>Oct 25 01:15:46 [drm:drm_do_probe_ddc_edid [drm]] drm: skipping non-existent adapter i915 gmbus dpd
>Oct 25 01:15:46 [drm:intel_gmbus_force_bit [i915]] disabling bit-banging on i915 gmbus dpd. force bit now 0
>Oct 25 01:15:47 [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] timed out, falling back to bit banging on pin 6
>Oct 25 01:15:47 [drm:drm_dp_dual_mode_detect [drm_kms_helper]] DP dual mode HDMI ID:  (err -6)
>Oct 25 01:15:47 [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:106:HDMI-A-2] status updated from unknown to disconnected
>Oct 25 01:15:47 [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:106:HDMI-A-2] disconnected
>Oct 25 01:15:47 [drm:drm_setup_crtcs [drm_kms_helper]] connector 83 enabled? yes
>Oct 25 01:15:47 [drm:drm_setup_crtcs [drm_kms_helper]] connector 90 enabled? no
>Oct 25 01:15:47 [drm:drm_setup_crtcs [drm_kms_helper]] connector 96 enabled? no
>Oct 25 01:15:47 [drm:drm_setup_crtcs [drm_kms_helper]] connector 101 enabled? no
>Oct 25 01:15:47 [drm:drm_setup_crtcs [drm_kms_helper]] connector 106 enabled? no
>Oct 25 01:15:47 [drm:intel_fb_initial_config [i915]] Not using firmware configuration
>Oct 25 01:15:47 [drm:drm_setup_crtcs [drm_kms_helper]] looking for cmdline mode on connector 83
>Oct 25 01:15:47 [drm:drm_setup_crtcs [drm_kms_helper]] looking for preferred mode on connector 83 0
>Oct 25 01:15:47 [drm:drm_setup_crtcs [drm_kms_helper]] found mode 2880x1800
>Oct 25 01:15:47 [drm:drm_setup_crtcs [drm_kms_helper]] picking CRTCs for 8192x8192 config
>Oct 25 01:15:47 [drm:drm_setup_crtcs [drm_kms_helper]] desired mode 2880x1800 set on crtc 45 (0,0)
>Oct 25 01:15:47 [drm:intelfb_create [i915]] re-using BIOS fb
>Oct 25 01:15:47 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:15:47 [drm:intelfb_create [i915]] allocated 3360x2100 fb: 0x00000000
>Oct 25 01:15:47 fbcon: inteldrmfb (fb0) is primary device
>Oct 25 01:15:47 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000f93b029f
>Oct 25 01:15:47 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000ec257c5a state to 00000000f93b029f
>Oct 25 01:15:47 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 0000000009e50552 state to 00000000f93b029f
>Oct 25 01:15:47 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:35:plane 2A] 0000000092bcc227 state to 00000000f93b029f
>Oct 25 01:15:47 [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:35:plane 2A] state 0000000092bcc227
>Oct 25 01:15:47 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:42:cursor A] 000000009ac177a3 state to 00000000f93b029f
>Oct 25 01:15:47 [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:42:cursor A] state 000000009ac177a3
>Oct 25 01:15:47 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:46:plane 1B] 00000000e13d103c state to 00000000f93b029f
>Oct 25 01:15:47 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:53:plane 2B] 00000000418cfb59 state to 00000000f93b029f
>Oct 25 01:15:47 [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:53:plane 2B] state 00000000418cfb59
>Oct 25 01:15:47 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:60:cursor B] 00000000b3db0592 state to 00000000f93b029f
>Oct 25 01:15:47 [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:60:cursor B] state 00000000b3db0592
>Oct 25 01:15:47 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:64:plane 1C] 00000000f43575ba state to 00000000f93b029f
>Oct 25 01:15:47 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:71:plane 2C] 000000006a5e68f8 state to 00000000f93b029f
>Oct 25 01:15:47 [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:71:plane 2C] state 000000006a5e68f8
>Oct 25 01:15:47 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:78:cursor C] 00000000d12af5a6 state to 00000000f93b029f
>Oct 25 01:15:47 [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:78:cursor C] state 00000000d12af5a6
>Oct 25 01:15:47 [drm:drm_atomic_set_mode_for_crtc [drm]] Set [MODE:2880x1800] for [CRTC:45:pipe A] state 0000000009e50552
>Oct 25 01:15:47 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:109] for [PLANE:28:plane 1A] state 00000000ec257c5a
>Oct 25 01:15:47 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000f93b029f
>Oct 25 01:15:47 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000d12af5a6 state to 00000000f93b029f
>Oct 25 01:15:47 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 0000000009e50552 state to 00000000f93b029f
>Oct 25 01:15:47 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:35:plane 2A] 000000006a5e68f8 state to 00000000f93b029f
>Oct 25 01:15:47 [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:35:plane 2A] state 000000006a5e68f8
>Oct 25 01:15:47 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000f93b029f
>Oct 25 01:15:47 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 000000006a5e68f8 state to 00000000f93b029f
>Oct 25 01:15:47 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 0000000009e50552 state to 00000000f93b029f
>Oct 25 01:15:47 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:35:plane 2A] 00000000d12af5a6 state to 00000000f93b029f
>Oct 25 01:15:47 [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:35:plane 2A] state 00000000d12af5a6
>Oct 25 01:15:47 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:42:cursor A] 00000000f43575ba state to 00000000f93b029f
>Oct 25 01:15:47 [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:42:cursor A] state 00000000f43575ba
>Oct 25 01:15:47 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:46:plane 1B] 00000000b3db0592 state to 00000000f93b029f
>Oct 25 01:15:47 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:53:plane 2B] 00000000418cfb59 state to 00000000f93b029f
>Oct 25 01:15:47 [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:53:plane 2B] state 00000000418cfb59
>Oct 25 01:15:47 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:60:cursor B] 00000000e13d103c state to 00000000f93b029f
>Oct 25 01:15:47 [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:60:cursor B] state 00000000e13d103c
>Oct 25 01:15:47 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:64:plane 1C] 000000009ac177a3 state to 00000000f93b029f
>Oct 25 01:15:47 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:71:plane 2C] 0000000092bcc227 state to 00000000f93b029f
>Oct 25 01:15:47 [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:71:plane 2C] state 0000000092bcc227
>Oct 25 01:15:47 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:78:cursor C] 00000000ec257c5a state to 00000000f93b029f
>Oct 25 01:15:47 [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:78:cursor C] state 00000000ec257c5a
>Oct 25 01:15:47 [drm:drm_atomic_set_mode_for_crtc [drm]] Set [MODE:2880x1800] for [CRTC:45:pipe A] state 0000000009e50552
>Oct 25 01:15:47 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:109] for [PLANE:28:plane 1A] state 000000006a5e68f8
>Oct 25 01:15:47 [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:45:pipe A] to 00000000f93b029f
>Oct 25 01:15:47 [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:83:eDP-1] 0000000048378656 state to 00000000f93b029f
>Oct 25 01:15:47 [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:83:eDP-1] state 0000000048378656 to [NOCRTC]
>Oct 25 01:15:47 [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:83:eDP-1] state 0000000048378656 to [CRTC:45:pipe A]
>Oct 25 01:15:47 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000f93b029f
>Oct 25 01:15:47 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000ec257c5a state to 00000000f93b029f
>Oct 25 01:15:47 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 0000000009e50552 state to 00000000f93b029f
>Oct 25 01:15:47 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:35:plane 2A] 0000000092bcc227 state to 00000000f93b029f
>Oct 25 01:15:47 [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:35:plane 2A] state 0000000092bcc227
>Oct 25 01:15:47 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:42:cursor A] 000000009ac177a3 state to 00000000f93b029f
>Oct 25 01:15:47 [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:42:cursor A] state 000000009ac177a3
>Oct 25 01:15:47 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:46:plane 1B] 00000000e13d103c state to 00000000f93b029f
>Oct 25 01:15:47 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:53:plane 2B] 00000000418cfb59 state to 00000000f93b029f
>Oct 25 01:15:47 [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:53:plane 2B] state 00000000418cfb59
>Oct 25 01:15:47 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:60:cursor B] 00000000b3db0592 state to 00000000f93b029f
>Oct 25 01:15:47 [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:60:cursor B] state 00000000b3db0592
>Oct 25 01:15:47 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:64:plane 1C] 00000000f43575ba state to 00000000f93b029f
>Oct 25 01:15:47 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:71:plane 2C] 00000000d12af5a6 state to 00000000f93b029f
>Oct 25 01:15:47 [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:71:plane 2C] state 00000000d12af5a6
>Oct 25 01:15:47 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:78:cursor C] 000000006a5e68f8 state to 00000000f93b029f
>Oct 25 01:15:47 [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:78:cursor C] state 000000006a5e68f8
>Oct 25 01:15:47 [drm:drm_atomic_set_mode_for_crtc [drm]] Set [MODE:2880x1800] for [CRTC:45:pipe A] state 0000000009e50552
>Oct 25 01:15:47 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:109] for [PLANE:28:plane 1A] state 00000000ec257c5a
>Oct 25 01:15:47 [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:45:pipe A] to 00000000f93b029f
>Oct 25 01:15:47 [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:83:eDP-1] 0000000048378656 state to 00000000f93b029f
>Oct 25 01:15:47 [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:83:eDP-1] state 0000000048378656 to [NOCRTC]
>Oct 25 01:15:47 [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:83:eDP-1] state 0000000048378656 to [CRTC:45:pipe A]
>Oct 25 01:15:47 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:63:pipe B] 00000000f771058b state to 00000000f93b029f
>Oct 25 01:15:47 [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:63:pipe B] state 00000000f771058b
>Oct 25 01:15:47 [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:46:plane 1B] state 00000000e13d103c
>Oct 25 01:15:47 [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:63:pipe B] to 00000000f93b029f
>Oct 25 01:15:47 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:81:pipe C] 000000006d04277e state to 00000000f93b029f
>Oct 25 01:15:47 [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:81:pipe C] state 000000006d04277e
>Oct 25 01:15:47 [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:64:plane 1C] state 00000000f43575ba
>Oct 25 01:15:47 [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:81:pipe C] to 00000000f93b029f
>Oct 25 01:15:47 [drm:drm_atomic_check_only [drm]] checking 00000000f93b029f
>Oct 25 01:15:47 [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:45:pipe A] mode changed
>Oct 25 01:15:47 [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:83:eDP-1]
>Oct 25 01:15:47 [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:83:eDP-1] keeps [ENCODER:82:DDI A], now on [CRTC:45:pipe A]
>Oct 25 01:15:47 [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:45:pipe A] needs all connectors, enable: y, active: y
>Oct 25 01:15:47 [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:45:pipe A] to 00000000f93b029f
>Oct 25 01:15:47 [drm:drm_atomic_add_affected_planes [drm]] Adding all current planes for [CRTC:45:pipe A] to 00000000f93b029f
>Oct 25 01:15:47 [drm:intel_atomic_check [i915]] [CONNECTOR:83:eDP-1] checking for sink bpp constrains
>Oct 25 01:15:47 [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30
>Oct 25 01:15:47 [drm:skl_update_scaler [i915]] scaler_user index 0.31: Staged freeing scaler id 0 scaler_users = 0x0
>Oct 25 01:15:47 [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max rate 270000 max bpp 30 pixel clock 328920KHz
>Oct 25 01:15:47 [drm:intel_dp_compute_config [i915]] DP lane count 4 clock 270000 bpp 24
>Oct 25 01:15:47 [drm:intel_dp_compute_config [i915]] DP link rate required 986760 available 1080000
>Oct 25 01:15:47 [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>Oct 25 01:15:47 [drm:pipe_config_err [i915]] mismatch in dp_m_n (expected tu 64 gmch 7983741/8388608 link 532249/524288, or tu 0 gmch 0/0 link 0/0, found tu 64, gmch 7664391/8388608 link 638699/524288)
>Oct 25 01:15:47 [drm:pipe_config_err [i915]] mismatch in pipe_bpp (expected 30, found 24)
>Oct 25 01:15:47 [drm:pipe_config_err [i915]] mismatch in port_clock (expected 324000, found 270000)
>Oct 25 01:15:47 [drm:intel_dump_pipe_config [i915]] [CRTC:45:pipe A][modeset]
>Oct 25 01:15:47 [drm:intel_dump_pipe_config [i915]] output_types: EDP (0x100)
>Oct 25 01:15:47 [drm:intel_dump_pipe_config [i915]] output format: RGB
>Oct 25 01:15:47 [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0
>Oct 25 01:15:47 [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 7664391, gmch_n: 8388608, link_m: 638699, link_n: 524288, tu: 64
>Oct 25 01:15:47 [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>Oct 25 01:15:47 [drm:intel_dump_pipe_config [i915]] requested mode:
>Oct 25 01:15:47 [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"2880x1800" 60 328920 2880 2888 2920 2960 1800 1838 1846 1852 0x48 0x9
>Oct 25 01:15:47 [drm:intel_dump_pipe_config [i915]] adjusted mode:
>Oct 25 01:15:47 [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"2880x1800" 60 328920 2880 2888 2920 2960 1800 1838 1846 1852 0x48 0x9
>Oct 25 01:15:47 [drm:intel_dump_pipe_config [i915]] crtc timings: 328920 2880 2888 2920 2960 1800 1838 1846 1852, type: 0x48 flags: 0x9
>Oct 25 01:15:47 [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 2880x1800, pixel rate 328920
>Oct 25 01:15:47 [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x0, scaler_id: -1
>Oct 25 01:15:47 [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x00000000, disabled
>Oct 25 01:15:47 [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>Oct 25 01:15:47 [drm:intel_dump_pipe_config [i915]] dpll_hw_state: ctrl1: 0x7, cfgcr1: 0x0, cfgcr2: 0x0
>Oct 25 01:15:47 [drm:intel_dump_pipe_config [i915]] planes on this crtc
>Oct 25 01:15:47 [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 1A] FB:109, fb = 3360x2100 format = XR24 little-endian (0x34325258)
>Oct 25 01:15:47 [drm:intel_dump_pipe_config [i915]]         scaler:-1 src 0x0+3360+2100 dst 0x0+3360+2100
>Oct 25 01:15:47 [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 2A] disabled, scaler_id = -1
>Oct 25 01:15:47 [drm:intel_dump_pipe_config [i915]] [PLANE:42:cursor A] disabled, scaler_id = -1
>Oct 25 01:15:47 [drm:intel_atomic_check [i915]] New cdclk calculated to be logical 337500 kHz, actual 337500 kHz
>Oct 25 01:15:47 [drm:intel_atomic_check [i915]] New voltage level calculated to be logical 0, actual 0
>Oct 25 01:15:47 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 109
>Oct 25 01:15:47 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 1, on 1, ms 1
>Oct 25 01:15:47 [drm:intel_find_shared_dpll [i915]] [CRTC:45:pipe A] allocated DPLL 0
>Oct 25 01:15:47 [drm:intel_reference_shared_dpll [i915]] using DPLL 0 for pipe A
>Oct 25 01:15:47 [drm:drm_atomic_commit [drm]] committing 00000000f93b029f
>Oct 25 01:15:47 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:15:47 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:15:47 [drm:intel_edp_backlight_off [i915]] 
>Oct 25 01:15:47 usb 1-3: new high-speed USB device number 3 using xhci_hcd
>Oct 25 01:15:47 [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 0
>Oct 25 01:15:47 [drm:lpt_disable_backlight [i915]] cpu backlight was enabled, disabling
>Oct 25 01:15:47 [drm:intel_disable_pipe [i915]] disabling pipe A
>Oct 25 01:15:47 [drm:intel_edp_panel_off.part.42 [i915]] Turn eDP port A panel power off
>Oct 25 01:15:47 [drm:intel_edp_panel_off.part.42 [i915]] Wait for panel power off time
>Oct 25 01:15:47 [drm:wait_panel_status [i915]] mask b0000000 value 00000000 status a0000002 control 00000000
>Oct 25 01:15:47 [drm:wait_panel_status [i915]] Wait complete
>Oct 25 01:15:47 [drm:intel_power_well_disable [i915]] disabling DDI A/E IO power well
>Oct 25 01:15:47 [drm:intel_disable_shared_dpll [i915]] disable DPLL 0 (active 1, on? 1) for crtc 45
>Oct 25 01:15:47 [drm:gen8_de_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010, long 0x00000010
>Oct 25 01:15:47 [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>Oct 25 01:15:47 [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 0
>Oct 25 01:15:47 [drm:intel_disable_shared_dpll [i915]] disabling DPLL 0
>Oct 25 01:15:47 [drm:intel_dump_cdclk_state [i915]] Changing CDCLK to 337500 kHz, VCO 8100000 kHz, ref 24000 kHz, bypass 24000 kHz, voltage level 0
>Oct 25 01:15:47 [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>Oct 25 01:15:47 [drm:intel_atomic_commit_tail [i915]] [ENCODER:82:DDI A]
>Oct 25 01:15:47 [drm:intel_atomic_commit_tail [i915]] [ENCODER:89:DDI C]
>Oct 25 01:15:47 [drm:intel_atomic_commit_tail [i915]] [ENCODER:91:DP-MST A]
>Oct 25 01:15:47 [drm:intel_atomic_commit_tail [i915]] [ENCODER:92:DP-MST B]
>Oct 25 01:15:47 [drm:intel_atomic_commit_tail [i915]] [ENCODER:93:DP-MST C]
>Oct 25 01:15:47 [drm:intel_atomic_commit_tail [i915]] [ENCODER:100:DDI D]
>Oct 25 01:15:47 [drm:intel_atomic_commit_tail [i915]] [ENCODER:102:DP-MST A]
>Oct 25 01:15:47 [drm:intel_atomic_commit_tail [i915]] [ENCODER:103:DP-MST B]
>Oct 25 01:15:47 [drm:intel_atomic_commit_tail [i915]] [ENCODER:104:DP-MST C]
>Oct 25 01:15:47 [drm:verify_single_dpll_state.isra.85 [i915]] DPLL 0
>Oct 25 01:15:47 [drm:verify_single_dpll_state.isra.85 [i915]] DPLL 1
>Oct 25 01:15:47 [drm:verify_single_dpll_state.isra.85 [i915]] DPLL 2
>Oct 25 01:15:47 [drm:verify_single_dpll_state.isra.85 [i915]] DPLL 3
>Oct 25 01:15:47 [drm:intel_enable_shared_dpll [i915]] enable DPLL 0 (active 1, on? 0) for crtc 45
>Oct 25 01:15:47 [drm:intel_enable_shared_dpll [i915]] enabling DPLL 0
>Oct 25 01:15:47 [drm:edp_panel_on [i915]] Turn eDP port A panel power on
>Oct 25 01:15:47 [drm:wait_panel_power_cycle [i915]] Wait for panel power cycle
>Oct 25 01:15:47 usb 1-3: New USB device found, idVendor=05ac, idProduct=8600, bcdDevice= 1.01
>Oct 25 01:15:47 usb 1-3: New USB device strings: Mfr=1, Product=2, SerialNumber=0
>Oct 25 01:15:47 usb 1-3: Product: iBridge
>Oct 25 01:15:47 usb 1-3: Manufacturer: Apple Inc.
>Oct 25 01:15:47 apple-ibridge-hid 0003:05AC:8600.0001: tb: device probe done.
>Oct 25 01:15:47 input: Apple Inc. iBridge as /devices/pci0000:00/0000:00:14.0/usb1/1-3/1-3:1.2/0003:05AC:8600.0001/input/input8
>Oct 25 01:15:47 apple-ibridge-hid 0003:05AC:8600.0001: input,hidraw0: USB HID v1.01 Keyboard [Apple Inc. iBridge] on usb-0000:00:14.0-3/input2
>Oct 25 01:15:47 apple-ibridge-hid 0003:05AC:8600.0001: ib: device probe done.
>Oct 25 01:15:47 apple-ib-tb: Connected to keyboard input device
>Oct 25 01:15:47 apple-ib-tb: Connected to touchpad input device
>Oct 25 01:15:47 apple-ibridge-hid 0003:05AC:8600.0002: tb: device probe done.
>Oct 25 01:15:47 apple-ibridge-hid 0003:05AC:8600.0002: hiddev96,hidraw1: USB HID v1.01 Device [Apple Inc. iBridge] on usb-0000:00:14.0-3/input3
>Oct 25 01:15:47 apple-ibridge-hid 0003:05AC:8600.0002: ib: device probe done.
>Oct 25 01:15:48 [drm:wait_panel_status [i915]] mask b800000f value 00000000 status 00000000 control 00000000
>Oct 25 01:15:48 [drm:wait_panel_status [i915]] Wait complete
>Oct 25 01:15:48 [drm:edp_panel_on [i915]] Wait for panel power on
>Oct 25 01:15:48 [drm:wait_panel_status [i915]] mask b000000f value 80000008 status 9000000a control 00000003
>Oct 25 01:15:48 [drm:gen8_de_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x12101010, pins 0x00000010, long 0x00000010
>Oct 25 01:15:48 [drm:intel_hpd_irq_handler [i915]] digital hpd port A - long
>Oct 25 01:15:48 [drm:intel_hpd_irq_handler [i915]] Received HPD interrupt on PIN 4 - cnt: 1
>Oct 25 01:15:48 [drm:intel_dp_hpd_pulse [i915]] ignoring long hpd on eDP port A
>Oct 25 01:15:48 [drm:wait_panel_status [i915]] Wait complete
>Oct 25 01:15:48 [drm:intel_power_well_enable [i915]] enabling DDI A/E IO power well
>Oct 25 01:15:48 [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>Oct 25 01:15:48 [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000000b
>Oct 25 01:15:48 [drm:intel_dp_start_link_train [i915]] Using LINK_BW_SET value 0a
>Oct 25 01:15:48 [drm:intel_dp_set_signal_levels [i915]] Using signal levels 00000000
>Oct 25 01:15:48 [drm:intel_dp_set_signal_levels [i915]] Using vswing level 0
>Oct 25 01:15:48 [drm:intel_dp_set_signal_levels [i915]] Using pre-emphasis level 0
>Oct 25 01:15:48 [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS1
>Oct 25 01:15:48 [drm:intel_dp_start_link_train [i915]] clock recovery OK
>Oct 25 01:15:48 [drm:intel_dp_program_link_training_pattern [i915]] Using DP training pattern TPS2
>Oct 25 01:15:48 [drm:intel_dp_start_link_train [i915]] Channel EQ done. DP Training successful
>Oct 25 01:15:48 [drm:intel_dp_start_link_train [i915]] [CONNECTOR:83:eDP-1] Link Training Passed at Link Rate = 270000, Lane count = 4
>Oct 25 01:15:48 [drm:intel_enable_pipe [i915]] enabling pipe A
>Oct 25 01:15:48 [drm:intel_edp_backlight_on [i915]] 
>Oct 25 01:15:48 [drm:intel_panel_enable_backlight [i915]] pipe A
>Oct 25 01:15:48 [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 22
>Oct 25 01:15:48 [drm:intel_psr_enable_locked [i915]] Enabling PSR1
>Oct 25 01:15:48 [drm:intel_enable_ddi [i915]] Panel doesn't support DRRS
>Oct 25 01:15:48 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:15:48 [drm:verify_connector_state.isra.132 [i915]] [CONNECTOR:83:eDP-1]
>Oct 25 01:15:48 [drm:intel_atomic_commit_tail [i915]] [CRTC:45:pipe A]
>Oct 25 01:15:48 [drm:verify_single_dpll_state.isra.85 [i915]] DPLL 0
>Oct 25 01:15:48 [drm:intel_enable_sagv [i915]] Enabling the SAGV
>Oct 25 01:15:48 [drm:__intel_fb_obj_invalidate [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:15:48 Console: switching to colour frame buffer device 420x131
>Oct 25 01:15:48 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000f93b029f
>Oct 25 01:15:48 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000f93b029f
>Oct 25 01:15:48 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:15:48 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000f93b029f
>Oct 25 01:15:48 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 0000000068768f66 state to 00000000f93b029f
>Oct 25 01:15:48 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 000000002b2f160e state to 00000000f93b029f
>Oct 25 01:15:48 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:35:plane 2A] 000000009432cdc7 state to 00000000f93b029f
>Oct 25 01:15:48 [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:35:plane 2A] state 000000009432cdc7
>Oct 25 01:15:48 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:42:cursor A] 00000000e080a592 state to 00000000f93b029f
>Oct 25 01:15:48 [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:42:cursor A] state 00000000e080a592
>Oct 25 01:15:48 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:46:plane 1B] 0000000086d2d4f5 state to 00000000f93b029f
>Oct 25 01:15:48 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:53:plane 2B] 000000002745c681 state to 00000000f93b029f
>Oct 25 01:15:48 [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:53:plane 2B] state 000000002745c681
>Oct 25 01:15:48 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:60:cursor B] 0000000039ba8987 state to 00000000f93b029f
>Oct 25 01:15:48 [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:60:cursor B] state 0000000039ba8987
>Oct 25 01:15:48 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:64:plane 1C] 0000000075d93369 state to 00000000f93b029f
>Oct 25 01:15:48 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:71:plane 2C] 000000003409a515 state to 00000000f93b029f
>Oct 25 01:15:48 [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:71:plane 2C] state 000000003409a515
>Oct 25 01:15:48 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:78:cursor C] 000000001e021c4a state to 00000000f93b029f
>Oct 25 01:15:48 [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:78:cursor C] state 000000001e021c4a
>Oct 25 01:15:48 [drm:drm_atomic_set_mode_for_crtc [drm]] Set [MODE:2880x1800] for [CRTC:45:pipe A] state 000000002b2f160e
>Oct 25 01:15:48 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:109] for [PLANE:28:plane 1A] state 0000000068768f66
>Oct 25 01:15:48 [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:45:pipe A] to 00000000f93b029f
>Oct 25 01:15:48 [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:83:eDP-1] 000000005f591794 state to 00000000f93b029f
>Oct 25 01:15:48 [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:83:eDP-1] state 000000005f591794 to [NOCRTC]
>Oct 25 01:15:48 [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:83:eDP-1] state 000000005f591794 to [CRTC:45:pipe A]
>Oct 25 01:15:48 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000f93b029f
>Oct 25 01:15:48 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 000000001e021c4a state to 00000000f93b029f
>Oct 25 01:15:48 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 000000002b2f160e state to 00000000f93b029f
>Oct 25 01:15:48 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:35:plane 2A] 000000003409a515 state to 00000000f93b029f
>Oct 25 01:15:48 [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:35:plane 2A] state 000000003409a515
>Oct 25 01:15:48 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000f93b029f
>Oct 25 01:15:48 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 000000003409a515 state to 00000000f93b029f
>Oct 25 01:15:48 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 000000002b2f160e state to 00000000f93b029f
>Oct 25 01:15:48 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:35:plane 2A] 000000001e021c4a state to 00000000f93b029f
>Oct 25 01:15:48 [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:35:plane 2A] state 000000001e021c4a
>Oct 25 01:15:48 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:42:cursor A] 0000000075d93369 state to 00000000f93b029f
>Oct 25 01:15:48 [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:42:cursor A] state 0000000075d93369
>Oct 25 01:15:48 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:46:plane 1B] 0000000039ba8987 state to 00000000f93b029f
>Oct 25 01:15:48 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:53:plane 2B] 000000002745c681 state to 00000000f93b029f
>Oct 25 01:15:48 [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:53:plane 2B] state 000000002745c681
>Oct 25 01:15:48 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:60:cursor B] 0000000086d2d4f5 state to 00000000f93b029f
>Oct 25 01:15:48 [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:60:cursor B] state 0000000086d2d4f5
>Oct 25 01:15:48 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:64:plane 1C] 00000000e080a592 state to 00000000f93b029f
>Oct 25 01:15:48 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:71:plane 2C] 000000009432cdc7 state to 00000000f93b029f
>Oct 25 01:15:48 [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:71:plane 2C] state 000000009432cdc7
>Oct 25 01:15:48 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:78:cursor C] 0000000068768f66 state to 00000000f93b029f
>Oct 25 01:15:48 [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:78:cursor C] state 0000000068768f66
>Oct 25 01:15:48 [drm:drm_atomic_set_mode_for_crtc [drm]] Set [MODE:2880x1800] for [CRTC:45:pipe A] state 000000002b2f160e
>Oct 25 01:15:48 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:109] for [PLANE:28:plane 1A] state 000000003409a515
>Oct 25 01:15:48 [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:45:pipe A] to 00000000f93b029f
>Oct 25 01:15:48 [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:83:eDP-1] 000000005f591794 state to 00000000f93b029f
>Oct 25 01:15:48 [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:83:eDP-1] state 000000005f591794 to [NOCRTC]
>Oct 25 01:15:48 [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:83:eDP-1] state 000000005f591794 to [CRTC:45:pipe A]
>Oct 25 01:15:48 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000f93b029f
>Oct 25 01:15:48 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 0000000068768f66 state to 00000000f93b029f
>Oct 25 01:15:48 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 000000002b2f160e state to 00000000f93b029f
>Oct 25 01:15:48 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:35:plane 2A] 000000009432cdc7 state to 00000000f93b029f
>Oct 25 01:15:48 [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:35:plane 2A] state 000000009432cdc7
>Oct 25 01:15:48 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:42:cursor A] 00000000e080a592 state to 00000000f93b029f
>Oct 25 01:15:48 [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:42:cursor A] state 00000000e080a592
>Oct 25 01:15:48 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:46:plane 1B] 0000000086d2d4f5 state to 00000000f93b029f
>Oct 25 01:15:48 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:53:plane 2B] 000000002745c681 state to 00000000f93b029f
>Oct 25 01:15:48 [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:53:plane 2B] state 000000002745c681
>Oct 25 01:15:48 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:60:cursor B] 0000000039ba8987 state to 00000000f93b029f
>Oct 25 01:15:48 [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:60:cursor B] state 0000000039ba8987
>Oct 25 01:15:48 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:64:plane 1C] 0000000075d93369 state to 00000000f93b029f
>Oct 25 01:15:48 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:71:plane 2C] 000000001e021c4a state to 00000000f93b029f
>Oct 25 01:15:48 [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:71:plane 2C] state 000000001e021c4a
>Oct 25 01:15:48 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:78:cursor C] 000000003409a515 state to 00000000f93b029f
>Oct 25 01:15:48 [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:78:cursor C] state 000000003409a515
>Oct 25 01:15:48 [drm:drm_atomic_set_mode_for_crtc [drm]] Set [MODE:2880x1800] for [CRTC:45:pipe A] state 000000002b2f160e
>Oct 25 01:15:48 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:109] for [PLANE:28:plane 1A] state 0000000068768f66
>Oct 25 01:15:48 [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:45:pipe A] to 00000000f93b029f
>Oct 25 01:15:48 [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:83:eDP-1] 000000005f591794 state to 00000000f93b029f
>Oct 25 01:15:48 [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:83:eDP-1] state 000000005f591794 to [NOCRTC]
>Oct 25 01:15:48 [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:83:eDP-1] state 000000005f591794 to [CRTC:45:pipe A]
>Oct 25 01:15:48 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:63:pipe B] 0000000036ed9464 state to 00000000f93b029f
>Oct 25 01:15:48 [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:63:pipe B] state 0000000036ed9464
>Oct 25 01:15:48 [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:46:plane 1B] state 0000000086d2d4f5
>Oct 25 01:15:48 [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:63:pipe B] to 00000000f93b029f
>Oct 25 01:15:48 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:81:pipe C] 00000000025c715f state to 00000000f93b029f
>Oct 25 01:15:48 [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:81:pipe C] state 00000000025c715f
>Oct 25 01:15:48 [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:64:plane 1C] state 0000000075d93369
>Oct 25 01:15:48 [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:81:pipe C] to 00000000f93b029f
>Oct 25 01:15:48 [drm:drm_atomic_check_only [drm]] checking 00000000f93b029f
>Oct 25 01:15:48 [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:83:eDP-1]
>Oct 25 01:15:48 [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:83:eDP-1] keeps [ENCODER:82:DDI A], now on [CRTC:45:pipe A]
>Oct 25 01:15:48 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 109
>Oct 25 01:15:48 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:15:48 [drm:drm_atomic_commit [drm]] committing 00000000f93b029f
>Oct 25 01:15:48 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:15:48 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:15:48 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000f93b029f
>Oct 25 01:15:48 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000f93b029f
>Oct 25 01:15:48 [drm:__intel_fb_obj_invalidate [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:15:48 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:15:48 i915 0000:00:02.0: fb0: inteldrmfb frame buffer device
>Oct 25 01:15:48 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:15:48 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:15:48 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:15:48 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:15:48 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000579eae10
>Oct 25 01:15:48 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 0000000014df7a9e state to 00000000579eae10
>Oct 25 01:15:48 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 0000000035fa6645 state to 00000000579eae10
>Oct 25 01:15:48 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:35:plane 2A] 00000000bc95d85b state to 00000000579eae10
>Oct 25 01:15:48 [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:35:plane 2A] state 00000000bc95d85b
>Oct 25 01:15:48 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:42:cursor A] 0000000094ddf3d1 state to 00000000579eae10
>Oct 25 01:15:48 [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:42:cursor A] state 0000000094ddf3d1
>Oct 25 01:15:48 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:46:plane 1B] 00000000a03bcbe3 state to 00000000579eae10
>Oct 25 01:15:48 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:53:plane 2B] 00000000720ee04a state to 00000000579eae10
>Oct 25 01:15:48 [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:53:plane 2B] state 00000000720ee04a
>Oct 25 01:15:48 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:60:cursor B] 00000000871f9a4d state to 00000000579eae10
>Oct 25 01:15:48 [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:60:cursor B] state 00000000871f9a4d
>Oct 25 01:15:48 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:64:plane 1C] 0000000029b4b266 state to 00000000579eae10
>Oct 25 01:15:48 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:71:plane 2C] 00000000205cc665 state to 00000000579eae10
>Oct 25 01:15:48 [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:71:plane 2C] state 00000000205cc665
>Oct 25 01:15:48 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:78:cursor C] 000000009af0bc82 state to 00000000579eae10
>Oct 25 01:15:48 [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:78:cursor C] state 000000009af0bc82
>Oct 25 01:15:48 [drm:drm_atomic_set_mode_for_crtc [drm]] Set [MODE:2880x1800] for [CRTC:45:pipe A] state 0000000035fa6645
>Oct 25 01:15:48 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:109] for [PLANE:28:plane 1A] state 0000000014df7a9e
>Oct 25 01:15:48 [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:45:pipe A] to 00000000579eae10
>Oct 25 01:15:48 [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:83:eDP-1] 000000009cc66901 state to 00000000579eae10
>Oct 25 01:15:48 [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:83:eDP-1] state 000000009cc66901 to [NOCRTC]
>Oct 25 01:15:48 [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:83:eDP-1] state 000000009cc66901 to [CRTC:45:pipe A]
>Oct 25 01:15:48 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:63:pipe B] 0000000052f228d5 state to 00000000579eae10
>Oct 25 01:15:48 [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:63:pipe B] state 0000000052f228d5
>Oct 25 01:15:48 [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:46:plane 1B] state 00000000a03bcbe3
>Oct 25 01:15:48 [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:63:pipe B] to 00000000579eae10
>Oct 25 01:15:48 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000579eae10
>Oct 25 01:15:48 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 000000009af0bc82 state to 00000000579eae10
>Oct 25 01:15:48 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 0000000052f228d5 state to 00000000579eae10
>Oct 25 01:15:48 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:35:plane 2A] 00000000205cc665 state to 00000000579eae10
>Oct 25 01:15:48 [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:35:plane 2A] state 00000000205cc665
>Oct 25 01:15:48 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000579eae10
>Oct 25 01:15:48 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000205cc665 state to 00000000579eae10
>Oct 25 01:15:48 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 0000000052f228d5 state to 00000000579eae10
>Oct 25 01:15:48 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:35:plane 2A] 000000009af0bc82 state to 00000000579eae10
>Oct 25 01:15:48 [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:35:plane 2A] state 000000009af0bc82
>Oct 25 01:15:48 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:42:cursor A] 0000000029b4b266 state to 00000000579eae10
>Oct 25 01:15:48 [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:42:cursor A] state 0000000029b4b266
>Oct 25 01:15:48 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:46:plane 1B] 00000000871f9a4d state to 00000000579eae10
>Oct 25 01:15:48 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:53:plane 2B] 00000000720ee04a state to 00000000579eae10
>Oct 25 01:15:48 [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:53:plane 2B] state 00000000720ee04a
>Oct 25 01:15:48 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:60:cursor B] 00000000a03bcbe3 state to 00000000579eae10
>Oct 25 01:15:48 [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:60:cursor B] state 00000000a03bcbe3
>Oct 25 01:15:48 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:64:plane 1C] 0000000094ddf3d1 state to 00000000579eae10
>Oct 25 01:15:48 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:71:plane 2C] 00000000bc95d85b state to 00000000579eae10
>Oct 25 01:15:48 [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:71:plane 2C] state 00000000bc95d85b
>Oct 25 01:15:48 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:78:cursor C] 0000000014df7a9e state to 00000000579eae10
>Oct 25 01:15:48 [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:78:cursor C] state 0000000014df7a9e
>Oct 25 01:15:48 [drm:drm_atomic_set_mode_for_crtc [drm]] Set [MODE:2880x1800] for [CRTC:45:pipe A] state 0000000052f228d5
>Oct 25 01:15:48 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:109] for [PLANE:28:plane 1A] state 00000000205cc665
>Oct 25 01:15:48 [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:45:pipe A] to 00000000579eae10
>Oct 25 01:15:48 [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:83:eDP-1] 000000009cc66901 state to 00000000579eae10
>Oct 25 01:15:48 [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:83:eDP-1] state 000000009cc66901 to [NOCRTC]
>Oct 25 01:15:48 [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:83:eDP-1] state 000000009cc66901 to [CRTC:45:pipe A]
>Oct 25 01:15:48 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000579eae10
>Oct 25 01:15:48 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 0000000014df7a9e state to 00000000579eae10
>Oct 25 01:15:48 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 0000000052f228d5 state to 00000000579eae10
>Oct 25 01:15:48 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:35:plane 2A] 00000000bc95d85b state to 00000000579eae10
>Oct 25 01:15:48 [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:35:plane 2A] state 00000000bc95d85b
>Oct 25 01:15:48 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:42:cursor A] 0000000094ddf3d1 state to 00000000579eae10
>Oct 25 01:15:48 [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:42:cursor A] state 0000000094ddf3d1
>Oct 25 01:15:48 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:46:plane 1B] 00000000a03bcbe3 state to 00000000579eae10
>Oct 25 01:15:48 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:53:plane 2B] 00000000720ee04a state to 00000000579eae10
>Oct 25 01:15:48 [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:53:plane 2B] state 00000000720ee04a
>Oct 25 01:15:48 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:60:cursor B] 00000000871f9a4d state to 00000000579eae10
>Oct 25 01:15:48 [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:60:cursor B] state 00000000871f9a4d
>Oct 25 01:15:48 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:64:plane 1C] 0000000029b4b266 state to 00000000579eae10
>Oct 25 01:15:48 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:71:plane 2C] 000000009af0bc82 state to 00000000579eae10
>Oct 25 01:15:48 [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:71:plane 2C] state 000000009af0bc82
>Oct 25 01:15:48 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:78:cursor C] 00000000205cc665 state to 00000000579eae10
>Oct 25 01:15:48 [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:78:cursor C] state 00000000205cc665
>Oct 25 01:15:48 [drm:drm_atomic_set_mode_for_crtc [drm]] Set [MODE:2880x1800] for [CRTC:45:pipe A] state 0000000052f228d5
>Oct 25 01:15:48 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:109] for [PLANE:28:plane 1A] state 0000000014df7a9e
>Oct 25 01:15:48 [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:45:pipe A] to 00000000579eae10
>Oct 25 01:15:48 [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:83:eDP-1] 000000009cc66901 state to 00000000579eae10
>Oct 25 01:15:48 [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:83:eDP-1] state 000000009cc66901 to [NOCRTC]
>Oct 25 01:15:48 [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:83:eDP-1] state 000000009cc66901 to [CRTC:45:pipe A]
>Oct 25 01:15:48 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:63:pipe B] 0000000035fa6645 state to 00000000579eae10
>Oct 25 01:15:48 [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:63:pipe B] state 0000000035fa6645
>Oct 25 01:15:48 [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:46:plane 1B] state 00000000a03bcbe3
>Oct 25 01:15:48 [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:63:pipe B] to 00000000579eae10
>Oct 25 01:15:48 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:81:pipe C] 00000000fb97628a state to 00000000579eae10
>Oct 25 01:15:48 [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:81:pipe C] state 00000000fb97628a
>Oct 25 01:15:48 [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:64:plane 1C] state 0000000029b4b266
>Oct 25 01:15:48 [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:81:pipe C] to 00000000579eae10
>Oct 25 01:15:48 [drm:drm_atomic_check_only [drm]] checking 00000000579eae10
>Oct 25 01:15:48 [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:83:eDP-1]
>Oct 25 01:15:48 [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:83:eDP-1] keeps [ENCODER:82:DDI A], now on [CRTC:45:pipe A]
>Oct 25 01:15:48 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 109
>Oct 25 01:15:48 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:15:48 [drm:drm_atomic_commit [drm]] committing 00000000579eae10
>Oct 25 01:15:48 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:15:48 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:15:48 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000579eae10
>Oct 25 01:15:48 [drm:drm_fb_helper_hotplug_event.part.30 [drm_kms_helper]] 
>Oct 25 01:15:48 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000579eae10
>Oct 25 01:15:48 [drm:drm_setup_crtcs [drm_kms_helper]] 
>Oct 25 01:15:48 [drm:__intel_fb_obj_invalidate [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:15:48 [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:83:eDP-1]
>Oct 25 01:15:48 [drm:intel_dp_detect [i915]] [CONNECTOR:83:eDP-1]
>Oct 25 01:15:48 [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>Oct 25 01:15:48 [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>Oct 25 01:15:48 [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>Oct 25 01:15:48 [drm:drm_dp_read_desc [drm_kms_helper]] DP sink: OUI 00-10-fa dev-ID eD\025eaa HW-rev 1.0 SW-rev 2.15 quirks 0x0000
>Oct 25 01:15:48 [drm:intel_dp_detect [i915]] MST support? port A: no, sink: no, modparam: yes
>Oct 25 01:15:48 [drm:drm_add_display_info [drm]] non_desktop set to 0
>Oct 25 01:15:48 [drm:drm_add_edid_modes [drm]] ELD: no CEA Extension found
>Oct 25 01:15:48 [drm:drm_add_display_info [drm]] non_desktop set to 0
>Oct 25 01:15:48 [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:83:eDP-1] probed modes :
>Oct 25 01:15:48 [drm:drm_mode_debug_printmodeline [drm]] Modeline 84:"2880x1800" 60 328920 2880 2888 2920 2960 1800 1838 1846 1852 0x48 0x9
>Oct 25 01:15:48 [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:90:DP-1]
>Oct 25 01:15:48 [drm:intel_dp_detect [i915]] [CONNECTOR:90:DP-1]
>Oct 25 01:15:48 [drm:intel_power_well_enable [i915]] enabling power well 2
>Oct 25 01:15:48 [drm:intel_power_well_disable [i915]] disabling power well 2
>Oct 25 01:15:48 [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:90:DP-1] disconnected
>Oct 25 01:15:48 [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:96:HDMI-A-1]
>Oct 25 01:15:48 [drm:intel_hdmi_detect [i915]] [CONNECTOR:96:HDMI-A-1]
>Oct 25 01:15:48 random: fast init done
>Oct 25 01:15:48 [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] timed out, falling back to bit banging on pin 4
>Oct 25 01:15:48 audit: type=1130 audit(1540455348.584:10): pid=1 uid=0 auid=4294967295 ses=4294967295 subj=kernel msg='unit=systemd-ask-password-plymouth comm="systemd" exe="/usr/lib/systemd/systemd" hostname=? addr=? terminal=? res=success'
>Oct 25 01:15:48 [drm:drm_do_probe_ddc_edid [drm]] drm: skipping non-existent adapter i915 gmbus dpc
>Oct 25 01:15:48 [drm:intel_hdmi_set_edid [i915]] HDMI GMBUS EDID read failed, retry using GPIO bit-banging
>Oct 25 01:15:48 [drm:intel_gmbus_force_bit [i915]] enabling bit-banging on i915 gmbus dpc. force bit now 1
>Oct 25 01:15:48 [drm:drm_do_probe_ddc_edid [drm]] drm: skipping non-existent adapter i915 gmbus dpc
>Oct 25 01:15:48 [drm:intel_gmbus_force_bit [i915]] disabling bit-banging on i915 gmbus dpc. force bit now 0
>Oct 25 01:15:48 [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] timed out, falling back to bit banging on pin 4
>Oct 25 01:15:48 [drm:drm_dp_dual_mode_detect [drm_kms_helper]] DP dual mode HDMI ID:  (err -6)
>Oct 25 01:15:48 [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:96:HDMI-A-1] disconnected
>Oct 25 01:15:48 [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:101:DP-2]
>Oct 25 01:15:48 [drm:intel_dp_detect [i915]] [CONNECTOR:101:DP-2]
>Oct 25 01:15:48 [drm:intel_power_well_enable [i915]] enabling power well 2
>Oct 25 01:15:48 [drm:intel_power_well_disable [i915]] disabling power well 2
>Oct 25 01:15:48 [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:101:DP-2] disconnected
>Oct 25 01:15:48 [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:106:HDMI-A-2]
>Oct 25 01:15:48 [drm:intel_hdmi_detect [i915]] [CONNECTOR:106:HDMI-A-2]
>Oct 25 01:15:48 [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] timed out, falling back to bit banging on pin 6
>Oct 25 01:15:48 [drm:drm_do_probe_ddc_edid [drm]] drm: skipping non-existent adapter i915 gmbus dpd
>Oct 25 01:15:48 [drm:intel_hdmi_set_edid [i915]] HDMI GMBUS EDID read failed, retry using GPIO bit-banging
>Oct 25 01:15:48 [drm:intel_gmbus_force_bit [i915]] enabling bit-banging on i915 gmbus dpd. force bit now 1
>Oct 25 01:15:48 [drm:drm_do_probe_ddc_edid [drm]] drm: skipping non-existent adapter i915 gmbus dpd
>Oct 25 01:15:48 [drm:intel_gmbus_force_bit [i915]] disabling bit-banging on i915 gmbus dpd. force bit now 0
>Oct 25 01:15:48 [drm:gen8_de_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x11101010, pins 0x00000010, long 0x00000000
>Oct 25 01:15:48 [drm:intel_hpd_irq_handler [i915]] digital hpd port A - short
>Oct 25 01:15:48 [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port A - short
>Oct 25 01:15:48 [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 41 00 00 01 80 02 00 00 00 0f 0b 00
>Oct 25 01:15:48 [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] timed out, falling back to bit banging on pin 6
>Oct 25 01:15:48 [drm:drm_dp_dual_mode_detect [drm_kms_helper]] DP dual mode HDMI ID:  (err -6)
>Oct 25 01:15:48 [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:106:HDMI-A-2] disconnected
>Oct 25 01:15:48 [drm:drm_setup_crtcs [drm_kms_helper]] connector 83 enabled? yes
>Oct 25 01:15:48 [drm:drm_setup_crtcs [drm_kms_helper]] connector 90 enabled? no
>Oct 25 01:15:48 [drm:drm_setup_crtcs [drm_kms_helper]] connector 96 enabled? no
>Oct 25 01:15:48 [drm:drm_setup_crtcs [drm_kms_helper]] connector 101 enabled? no
>Oct 25 01:15:48 [drm:drm_setup_crtcs [drm_kms_helper]] connector 106 enabled? no
>Oct 25 01:15:48 [drm:intel_fb_initial_config [i915]] Not using firmware configuration
>Oct 25 01:15:48 [drm:drm_setup_crtcs [drm_kms_helper]] looking for cmdline mode on connector 83
>Oct 25 01:15:48 [drm:drm_setup_crtcs [drm_kms_helper]] looking for preferred mode on connector 83 0
>Oct 25 01:15:48 [drm:drm_setup_crtcs [drm_kms_helper]] found mode 2880x1800
>Oct 25 01:15:48 [drm:drm_setup_crtcs [drm_kms_helper]] picking CRTCs for 3360x2100 config
>Oct 25 01:15:48 [drm:drm_setup_crtcs [drm_kms_helper]] desired mode 2880x1800 set on crtc 45 (0,0)
>Oct 25 01:15:48 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000d7f9cfed
>Oct 25 01:15:48 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000f3034e6f state to 00000000d7f9cfed
>Oct 25 01:15:48 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000fe6521b2 state to 00000000d7f9cfed
>Oct 25 01:15:48 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:35:plane 2A] 000000000e7edf5c state to 00000000d7f9cfed
>Oct 25 01:15:48 [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:35:plane 2A] state 000000000e7edf5c
>Oct 25 01:15:48 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000d7f9cfed
>Oct 25 01:15:48 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 000000000e7edf5c state to 00000000d7f9cfed
>Oct 25 01:15:48 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000fe6521b2 state to 00000000d7f9cfed
>Oct 25 01:15:48 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:35:plane 2A] 00000000f3034e6f state to 00000000d7f9cfed
>Oct 25 01:15:48 [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:35:plane 2A] state 00000000f3034e6f
>Oct 25 01:15:48 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:42:cursor A] 0000000046b037f6 state to 00000000d7f9cfed
>Oct 25 01:15:48 [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:42:cursor A] state 0000000046b037f6
>Oct 25 01:15:48 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000d7f9cfed
>Oct 25 01:15:48 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 0000000046b037f6 state to 00000000d7f9cfed
>Oct 25 01:15:48 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000fe6521b2 state to 00000000d7f9cfed
>Oct 25 01:15:48 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:35:plane 2A] 00000000f3034e6f state to 00000000d7f9cfed
>Oct 25 01:15:48 [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:35:plane 2A] state 00000000f3034e6f
>Oct 25 01:15:48 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:42:cursor A] 000000000e7edf5c state to 00000000d7f9cfed
>Oct 25 01:15:48 [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:42:cursor A] state 000000000e7edf5c
>Oct 25 01:15:48 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:46:plane 1B] 000000000871dc67 state to 00000000d7f9cfed
>Oct 25 01:15:48 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:53:plane 2B] 0000000098ce6fa5 state to 00000000d7f9cfed
>Oct 25 01:15:48 [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:53:plane 2B] state 0000000098ce6fa5
>Oct 25 01:15:48 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:60:cursor B] 00000000b3c2f9db state to 00000000d7f9cfed
>Oct 25 01:15:48 [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:60:cursor B] state 00000000b3c2f9db
>Oct 25 01:15:48 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:64:plane 1C] 00000000c34618ba state to 00000000d7f9cfed
>Oct 25 01:15:48 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:71:plane 2C] 000000004255aff6 state to 00000000d7f9cfed
>Oct 25 01:15:48 [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:71:plane 2C] state 000000004255aff6
>Oct 25 01:15:48 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:78:cursor C] 000000007b8eec14 state to 00000000d7f9cfed
>Oct 25 01:15:48 [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:78:cursor C] state 000000007b8eec14
>Oct 25 01:15:48 [drm:drm_atomic_set_mode_for_crtc [drm]] Set [MODE:2880x1800] for [CRTC:45:pipe A] state 00000000fe6521b2
>Oct 25 01:15:48 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:109] for [PLANE:28:plane 1A] state 0000000046b037f6
>Oct 25 01:15:48 [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:45:pipe A] to 00000000d7f9cfed
>Oct 25 01:15:48 [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:83:eDP-1] 000000001fca08f1 state to 00000000d7f9cfed
>Oct 25 01:15:48 [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:83:eDP-1] state 000000001fca08f1 to [NOCRTC]
>Oct 25 01:15:48 [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:83:eDP-1] state 000000001fca08f1 to [CRTC:45:pipe A]
>Oct 25 01:15:48 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000d7f9cfed
>Oct 25 01:15:48 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 000000007b8eec14 state to 00000000d7f9cfed
>Oct 25 01:15:48 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000fe6521b2 state to 00000000d7f9cfed
>Oct 25 01:15:48 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:35:plane 2A] 000000004255aff6 state to 00000000d7f9cfed
>Oct 25 01:15:48 [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:35:plane 2A] state 000000004255aff6
>Oct 25 01:15:48 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:42:cursor A] 00000000c34618ba state to 00000000d7f9cfed
>Oct 25 01:15:48 [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:42:cursor A] state 00000000c34618ba
>Oct 25 01:15:48 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:46:plane 1B] 00000000b3c2f9db state to 00000000d7f9cfed
>Oct 25 01:15:48 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:53:plane 2B] 0000000098ce6fa5 state to 00000000d7f9cfed
>Oct 25 01:15:48 [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:53:plane 2B] state 0000000098ce6fa5
>Oct 25 01:15:48 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:60:cursor B] 000000000871dc67 state to 00000000d7f9cfed
>Oct 25 01:15:48 [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:60:cursor B] state 000000000871dc67
>Oct 25 01:15:48 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:64:plane 1C] 000000000e7edf5c state to 00000000d7f9cfed
>Oct 25 01:15:48 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:71:plane 2C] 00000000f3034e6f state to 00000000d7f9cfed
>Oct 25 01:15:48 [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:71:plane 2C] state 00000000f3034e6f
>Oct 25 01:15:48 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:78:cursor C] 0000000046b037f6 state to 00000000d7f9cfed
>Oct 25 01:15:48 [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:78:cursor C] state 0000000046b037f6
>Oct 25 01:15:48 [drm:drm_atomic_set_mode_for_crtc [drm]] Set [MODE:2880x1800] for [CRTC:45:pipe A] state 00000000fe6521b2
>Oct 25 01:15:48 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:109] for [PLANE:28:plane 1A] state 000000007b8eec14
>Oct 25 01:15:48 [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:45:pipe A] to 00000000d7f9cfed
>Oct 25 01:15:48 [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:83:eDP-1] 000000001fca08f1 state to 00000000d7f9cfed
>Oct 25 01:15:48 [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:83:eDP-1] state 000000001fca08f1 to [NOCRTC]
>Oct 25 01:15:48 [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:83:eDP-1] state 000000001fca08f1 to [CRTC:45:pipe A]
>Oct 25 01:15:48 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:63:pipe B] 00000000286b2c61 state to 00000000d7f9cfed
>Oct 25 01:15:48 [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:63:pipe B] state 00000000286b2c61
>Oct 25 01:15:48 [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:46:plane 1B] state 00000000b3c2f9db
>Oct 25 01:15:48 [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:63:pipe B] to 00000000d7f9cfed
>Oct 25 01:15:48 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:81:pipe C] 000000004235e5cf state to 00000000d7f9cfed
>Oct 25 01:15:48 [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:81:pipe C] state 000000004235e5cf
>Oct 25 01:15:48 [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:64:plane 1C] state 000000000e7edf5c
>Oct 25 01:15:48 [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:81:pipe C] to 00000000d7f9cfed
>Oct 25 01:15:48 [drm:drm_atomic_check_only [drm]] checking 00000000d7f9cfed
>Oct 25 01:15:48 [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:83:eDP-1]
>Oct 25 01:15:48 [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:83:eDP-1] keeps [ENCODER:82:DDI A], now on [CRTC:45:pipe A]
>Oct 25 01:15:48 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 109
>Oct 25 01:15:48 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:15:48 [drm:drm_atomic_commit [drm]] committing 00000000d7f9cfed
>Oct 25 01:15:48 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:15:48 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:15:48 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000d7f9cfed
>Oct 25 01:15:48 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:15:48 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000d7f9cfed
>Oct 25 01:15:48 [drm:drm_fb_helper_hotplug_event.part.30 [drm_kms_helper]] 
>Oct 25 01:15:48 [drm:drm_setup_crtcs [drm_kms_helper]] 
>Oct 25 01:15:48 [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:83:eDP-1]
>Oct 25 01:15:48 [drm:intel_dp_detect [i915]] [CONNECTOR:83:eDP-1]
>Oct 25 01:15:48 [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>Oct 25 01:15:48 [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>Oct 25 01:15:48 [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>Oct 25 01:15:48 [drm:drm_dp_read_desc [drm_kms_helper]] DP sink: OUI 00-10-fa dev-ID eD\025eaa HW-rev 1.0 SW-rev 2.15 quirks 0x0000
>Oct 25 01:15:48 [drm:intel_dp_detect [i915]] MST support? port A: no, sink: no, modparam: yes
>Oct 25 01:15:48 [drm:drm_add_display_info [drm]] non_desktop set to 0
>Oct 25 01:15:48 [drm:drm_add_edid_modes [drm]] ELD: no CEA Extension found
>Oct 25 01:15:48 [drm:drm_add_display_info [drm]] non_desktop set to 0
>Oct 25 01:15:48 [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:83:eDP-1] probed modes :
>Oct 25 01:15:48 [drm:drm_mode_debug_printmodeline [drm]] Modeline 84:"2880x1800" 60 328920 2880 2888 2920 2960 1800 1838 1846 1852 0x48 0x9
>Oct 25 01:15:48 [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:90:DP-1]
>Oct 25 01:15:48 [drm:intel_dp_detect [i915]] [CONNECTOR:90:DP-1]
>Oct 25 01:15:48 [drm:intel_power_well_enable [i915]] enabling power well 2
>Oct 25 01:15:48 [drm:intel_power_well_disable [i915]] disabling power well 2
>Oct 25 01:15:48 [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:90:DP-1] disconnected
>Oct 25 01:15:48 [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:96:HDMI-A-1]
>Oct 25 01:15:48 [drm:intel_hdmi_detect [i915]] [CONNECTOR:96:HDMI-A-1]
>Oct 25 01:15:48 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:15:48 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:15:48 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:15:48 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:15:48 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:15:48 [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] timed out, falling back to bit banging on pin 4
>Oct 25 01:15:48 [drm:drm_do_probe_ddc_edid [drm]] drm: skipping non-existent adapter i915 gmbus dpc
>Oct 25 01:15:48 [drm:intel_hdmi_set_edid [i915]] HDMI GMBUS EDID read failed, retry using GPIO bit-banging
>Oct 25 01:15:48 [drm:intel_gmbus_force_bit [i915]] enabling bit-banging on i915 gmbus dpc. force bit now 1
>Oct 25 01:15:48 [drm:drm_do_probe_ddc_edid [drm]] drm: skipping non-existent adapter i915 gmbus dpc
>Oct 25 01:15:48 [drm:intel_gmbus_force_bit [i915]] disabling bit-banging on i915 gmbus dpc. force bit now 0
>Oct 25 01:15:48 [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] timed out, falling back to bit banging on pin 4
>Oct 25 01:15:48 [drm:drm_dp_dual_mode_detect [drm_kms_helper]] DP dual mode HDMI ID:  (err -6)
>Oct 25 01:15:48 [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:96:HDMI-A-1] disconnected
>Oct 25 01:15:48 [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:101:DP-2]
>Oct 25 01:15:48 [drm:intel_dp_detect [i915]] [CONNECTOR:101:DP-2]
>Oct 25 01:15:48 [drm:intel_power_well_enable [i915]] enabling power well 2
>Oct 25 01:15:48 [drm:intel_power_well_disable [i915]] disabling power well 2
>Oct 25 01:15:48 [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:101:DP-2] disconnected
>Oct 25 01:15:48 [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:106:HDMI-A-2]
>Oct 25 01:15:48 [drm:intel_hdmi_detect [i915]] [CONNECTOR:106:HDMI-A-2]
>Oct 25 01:15:48 [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] timed out, falling back to bit banging on pin 6
>Oct 25 01:15:48 [drm:drm_do_probe_ddc_edid [drm]] drm: skipping non-existent adapter i915 gmbus dpd
>Oct 25 01:15:48 [drm:intel_hdmi_set_edid [i915]] HDMI GMBUS EDID read failed, retry using GPIO bit-banging
>Oct 25 01:15:48 [drm:intel_gmbus_force_bit [i915]] enabling bit-banging on i915 gmbus dpd. force bit now 1
>Oct 25 01:15:48 [drm:drm_do_probe_ddc_edid [drm]] drm: skipping non-existent adapter i915 gmbus dpd
>Oct 25 01:15:48 [drm:intel_gmbus_force_bit [i915]] disabling bit-banging on i915 gmbus dpd. force bit now 0
>Oct 25 01:15:48 [drm:gen8_de_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x11101010, pins 0x00000010, long 0x00000000
>Oct 25 01:15:48 [drm:intel_hpd_irq_handler [i915]] digital hpd port A - short
>Oct 25 01:15:48 [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port A - short
>Oct 25 01:15:48 [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 41 00 00 01 80 02 00 00 00 0f 0b 00
>Oct 25 01:15:49 [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] timed out, falling back to bit banging on pin 6
>Oct 25 01:15:49 [drm:drm_dp_dual_mode_detect [drm_kms_helper]] DP dual mode HDMI ID:  (err -6)
>Oct 25 01:15:49 [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:106:HDMI-A-2] disconnected
>Oct 25 01:15:49 [drm:drm_setup_crtcs [drm_kms_helper]] connector 83 enabled? yes
>Oct 25 01:15:49 [drm:drm_setup_crtcs [drm_kms_helper]] connector 90 enabled? no
>Oct 25 01:15:49 [drm:drm_setup_crtcs [drm_kms_helper]] connector 96 enabled? no
>Oct 25 01:15:49 [drm:drm_setup_crtcs [drm_kms_helper]] connector 101 enabled? no
>Oct 25 01:15:49 [drm:drm_setup_crtcs [drm_kms_helper]] connector 106 enabled? no
>Oct 25 01:15:49 [drm:intel_fb_initial_config [i915]] Not using firmware configuration
>Oct 25 01:15:49 [drm:drm_setup_crtcs [drm_kms_helper]] looking for cmdline mode on connector 83
>Oct 25 01:15:49 [drm:drm_setup_crtcs [drm_kms_helper]] looking for preferred mode on connector 83 0
>Oct 25 01:15:49 [drm:drm_setup_crtcs [drm_kms_helper]] found mode 2880x1800
>Oct 25 01:15:49 [drm:drm_setup_crtcs [drm_kms_helper]] picking CRTCs for 3360x2100 config
>Oct 25 01:15:49 [drm:drm_setup_crtcs [drm_kms_helper]] desired mode 2880x1800 set on crtc 45 (0,0)
>Oct 25 01:15:49 [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:83:eDP-1]
>Oct 25 01:15:49 [drm:intel_dp_detect [i915]] [CONNECTOR:83:eDP-1]
>Oct 25 01:15:49 [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>Oct 25 01:15:49 [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>Oct 25 01:15:49 [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>Oct 25 01:15:49 [drm:drm_dp_read_desc [drm_kms_helper]] DP sink: OUI 00-10-fa dev-ID eD\025eaa HW-rev 1.0 SW-rev 2.15 quirks 0x0000
>Oct 25 01:15:49 [drm:intel_dp_detect [i915]] MST support? port A: no, sink: no, modparam: yes
>Oct 25 01:15:49 [drm:drm_add_display_info [drm]] non_desktop set to 0
>Oct 25 01:15:49 [drm:drm_add_edid_modes [drm]] ELD: no CEA Extension found
>Oct 25 01:15:49 [drm:drm_add_display_info [drm]] non_desktop set to 0
>Oct 25 01:15:49 [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:83:eDP-1] probed modes :
>Oct 25 01:15:49 [drm:drm_mode_debug_printmodeline [drm]] Modeline 84:"2880x1800" 60 328920 2880 2888 2920 2960 1800 1838 1846 1852 0x48 0x9
>Oct 25 01:15:49 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000139c8ede
>Oct 25 01:15:49 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000265411cf state to 00000000139c8ede
>Oct 25 01:15:49 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000daabd739 state to 00000000139c8ede
>Oct 25 01:15:49 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:35:plane 2A] 00000000ee6ce82f state to 00000000139c8ede
>Oct 25 01:15:49 [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:35:plane 2A] state 00000000ee6ce82f
>Oct 25 01:15:49 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:42:cursor A] 00000000fed2ebe8 state to 00000000139c8ede
>Oct 25 01:15:49 [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:42:cursor A] state 00000000fed2ebe8
>Oct 25 01:15:49 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:46:plane 1B] 00000000469c63f9 state to 00000000139c8ede
>Oct 25 01:15:49 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:53:plane 2B] 00000000e8b47b60 state to 00000000139c8ede
>Oct 25 01:15:49 [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:53:plane 2B] state 00000000e8b47b60
>Oct 25 01:15:49 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:60:cursor B] 000000007d5db786 state to 00000000139c8ede
>Oct 25 01:15:49 [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:60:cursor B] state 000000007d5db786
>Oct 25 01:15:49 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:64:plane 1C] 00000000ff59fe61 state to 00000000139c8ede
>Oct 25 01:15:49 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:71:plane 2C] 00000000f9f8821d state to 00000000139c8ede
>Oct 25 01:15:49 [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:71:plane 2C] state 00000000f9f8821d
>Oct 25 01:15:49 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:78:cursor C] 00000000163f3dd3 state to 00000000139c8ede
>Oct 25 01:15:49 [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:78:cursor C] state 00000000163f3dd3
>Oct 25 01:15:49 [drm:drm_atomic_set_mode_for_crtc [drm]] Set [MODE:2880x1800] for [CRTC:45:pipe A] state 00000000daabd739
>Oct 25 01:15:49 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:109] for [PLANE:28:plane 1A] state 00000000265411cf
>Oct 25 01:15:49 [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:45:pipe A] to 00000000139c8ede
>Oct 25 01:15:49 [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:83:eDP-1] 00000000fbd2047f state to 00000000139c8ede
>Oct 25 01:15:49 [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:83:eDP-1] state 00000000fbd2047f to [NOCRTC]
>Oct 25 01:15:49 [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:83:eDP-1] state 00000000fbd2047f to [CRTC:45:pipe A]
>Oct 25 01:15:49 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000139c8ede
>Oct 25 01:15:49 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000163f3dd3 state to 00000000139c8ede
>Oct 25 01:15:49 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000daabd739 state to 00000000139c8ede
>Oct 25 01:15:49 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:35:plane 2A] 00000000f9f8821d state to 00000000139c8ede
>Oct 25 01:15:49 [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:35:plane 2A] state 00000000f9f8821d
>Oct 25 01:15:49 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000139c8ede
>Oct 25 01:15:49 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000f9f8821d state to 00000000139c8ede
>Oct 25 01:15:49 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000daabd739 state to 00000000139c8ede
>Oct 25 01:15:49 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:35:plane 2A] 00000000163f3dd3 state to 00000000139c8ede
>Oct 25 01:15:49 [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:35:plane 2A] state 00000000163f3dd3
>Oct 25 01:15:49 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:42:cursor A] 000000007a3161cd state to 00000000139c8ede
>Oct 25 01:15:49 [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:42:cursor A] state 000000007a3161cd
>Oct 25 01:15:49 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:46:plane 1B] 00000000194eb5c2 state to 00000000139c8ede
>Oct 25 01:15:49 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:53:plane 2B] 00000000087e7a1a state to 00000000139c8ede
>Oct 25 01:15:49 [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:53:plane 2B] state 00000000087e7a1a
>Oct 25 01:15:49 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:60:cursor B] 000000008dc8e7d9 state to 00000000139c8ede
>Oct 25 01:15:49 [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:60:cursor B] state 000000008dc8e7d9
>Oct 25 01:15:49 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:64:plane 1C] 000000009aa9f91e state to 00000000139c8ede
>Oct 25 01:15:49 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:71:plane 2C] 000000006e6834b1 state to 00000000139c8ede
>Oct 25 01:15:49 [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:71:plane 2C] state 000000006e6834b1
>Oct 25 01:15:49 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:78:cursor C] 0000000003a79cff state to 00000000139c8ede
>Oct 25 01:15:49 [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:78:cursor C] state 0000000003a79cff
>Oct 25 01:15:49 [drm:drm_atomic_set_mode_for_crtc [drm]] Set [MODE:2880x1800] for [CRTC:45:pipe A] state 00000000daabd739
>Oct 25 01:15:49 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:109] for [PLANE:28:plane 1A] state 00000000f9f8821d
>Oct 25 01:15:49 [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:45:pipe A] to 00000000139c8ede
>Oct 25 01:15:49 [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:83:eDP-1] 00000000fbd2047f state to 00000000139c8ede
>Oct 25 01:15:49 [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:83:eDP-1] state 00000000fbd2047f to [NOCRTC]
>Oct 25 01:15:49 [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:83:eDP-1] state 00000000fbd2047f to [CRTC:45:pipe A]
>Oct 25 01:15:49 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000139c8ede
>Oct 25 01:15:49 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 0000000003a79cff state to 00000000139c8ede
>Oct 25 01:15:49 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000daabd739 state to 00000000139c8ede
>Oct 25 01:15:49 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:35:plane 2A] 000000006e6834b1 state to 00000000139c8ede
>Oct 25 01:15:49 [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:35:plane 2A] state 000000006e6834b1
>Oct 25 01:15:49 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:42:cursor A] 000000009aa9f91e state to 00000000139c8ede
>Oct 25 01:15:49 [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:42:cursor A] state 000000009aa9f91e
>Oct 25 01:15:49 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:46:plane 1B] 000000008dc8e7d9 state to 00000000139c8ede
>Oct 25 01:15:49 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:53:plane 2B] 00000000087e7a1a state to 00000000139c8ede
>Oct 25 01:15:49 [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:53:plane 2B] state 00000000087e7a1a
>Oct 25 01:15:49 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:60:cursor B] 00000000194eb5c2 state to 00000000139c8ede
>Oct 25 01:15:49 [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:60:cursor B] state 00000000194eb5c2
>Oct 25 01:15:49 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:64:plane 1C] 000000007a3161cd state to 00000000139c8ede
>Oct 25 01:15:49 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:71:plane 2C] 00000000163f3dd3 state to 00000000139c8ede
>Oct 25 01:15:49 [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:71:plane 2C] state 00000000163f3dd3
>Oct 25 01:15:49 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:78:cursor C] 00000000f9f8821d state to 00000000139c8ede
>Oct 25 01:15:49 [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:78:cursor C] state 00000000f9f8821d
>Oct 25 01:15:49 [drm:drm_atomic_set_mode_for_crtc [drm]] Set [MODE:2880x1800] for [CRTC:45:pipe A] state 00000000daabd739
>Oct 25 01:15:49 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:109] for [PLANE:28:plane 1A] state 0000000003a79cff
>Oct 25 01:15:49 [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:45:pipe A] to 00000000139c8ede
>Oct 25 01:15:49 [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:83:eDP-1] 00000000fbd2047f state to 00000000139c8ede
>Oct 25 01:15:49 [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:83:eDP-1] state 00000000fbd2047f to [NOCRTC]
>Oct 25 01:15:49 [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:83:eDP-1] state 00000000fbd2047f to [CRTC:45:pipe A]
>Oct 25 01:15:49 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:63:pipe B] 00000000aef45ed5 state to 00000000139c8ede
>Oct 25 01:15:49 [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:63:pipe B] state 00000000aef45ed5
>Oct 25 01:15:49 [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:46:plane 1B] state 000000008dc8e7d9
>Oct 25 01:15:49 [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:63:pipe B] to 00000000139c8ede
>Oct 25 01:15:49 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:81:pipe C] 0000000075612452 state to 00000000139c8ede
>Oct 25 01:15:49 [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:81:pipe C] state 0000000075612452
>Oct 25 01:15:49 [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:64:plane 1C] state 000000007a3161cd
>Oct 25 01:15:49 [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:81:pipe C] to 00000000139c8ede
>Oct 25 01:15:49 [drm:drm_atomic_check_only [drm]] checking 00000000139c8ede
>Oct 25 01:15:49 [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:83:eDP-1]
>Oct 25 01:15:49 [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:83:eDP-1] keeps [ENCODER:82:DDI A], now on [CRTC:45:pipe A]
>Oct 25 01:15:49 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 109
>Oct 25 01:15:49 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:15:49 [drm:drm_atomic_commit [drm]] committing 00000000139c8ede
>Oct 25 01:15:49 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:15:49 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:15:49 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000139c8ede
>Oct 25 01:15:49 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000139c8ede
>Oct 25 01:15:49 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000d0ba5f75
>Oct 25 01:15:49 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 000000006a5e68f8 state to 00000000d0ba5f75
>Oct 25 01:15:49 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000025c715f state to 00000000d0ba5f75
>Oct 25 01:15:49 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:35:plane 2A] 00000000d733a28c state to 00000000d0ba5f75
>Oct 25 01:15:49 [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:35:plane 2A] state 00000000d733a28c
>Oct 25 01:15:49 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:42:cursor A] 00000000d12af5a6 state to 00000000d0ba5f75
>Oct 25 01:15:49 [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:42:cursor A] state 00000000d12af5a6
>Oct 25 01:15:49 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:46:plane 1B] 00000000f43575ba state to 00000000d0ba5f75
>Oct 25 01:15:49 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:53:plane 2B] 00000000b3db0592 state to 00000000d0ba5f75
>Oct 25 01:15:49 [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:53:plane 2B] state 00000000b3db0592
>Oct 25 01:15:49 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:60:cursor B] 00000000418cfb59 state to 00000000d0ba5f75
>Oct 25 01:15:49 [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:60:cursor B] state 00000000418cfb59
>Oct 25 01:15:49 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:64:plane 1C] 00000000e13d103c state to 00000000d0ba5f75
>Oct 25 01:15:49 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:71:plane 2C] 000000009ac177a3 state to 00000000d0ba5f75
>Oct 25 01:15:49 [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:71:plane 2C] state 000000009ac177a3
>Oct 25 01:15:49 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:78:cursor C] 0000000092bcc227 state to 00000000d0ba5f75
>Oct 25 01:15:49 [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:78:cursor C] state 0000000092bcc227
>Oct 25 01:15:49 [drm:drm_atomic_set_mode_for_crtc [drm]] Set [MODE:2880x1800] for [CRTC:45:pipe A] state 00000000025c715f
>Oct 25 01:15:49 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:109] for [PLANE:28:plane 1A] state 000000006a5e68f8
>Oct 25 01:15:49 [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:45:pipe A] to 00000000d0ba5f75
>Oct 25 01:15:49 [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:83:eDP-1] 00000000c3062f75 state to 00000000d0ba5f75
>Oct 25 01:15:49 [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:83:eDP-1] state 00000000c3062f75 to [NOCRTC]
>Oct 25 01:15:49 [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:83:eDP-1] state 00000000c3062f75 to [CRTC:45:pipe A]
>Oct 25 01:15:49 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:63:pipe B] 0000000036ed9464 state to 00000000d0ba5f75
>Oct 25 01:15:49 [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:63:pipe B] state 0000000036ed9464
>Oct 25 01:15:49 [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:46:plane 1B] state 00000000f43575ba
>Oct 25 01:15:49 [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:63:pipe B] to 00000000d0ba5f75
>Oct 25 01:15:49 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000d0ba5f75
>Oct 25 01:15:49 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 0000000092bcc227 state to 00000000d0ba5f75
>Oct 25 01:15:49 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 0000000036ed9464 state to 00000000d0ba5f75
>Oct 25 01:15:49 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:35:plane 2A] 000000009ac177a3 state to 00000000d0ba5f75
>Oct 25 01:15:49 [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:90:DP-1]
>Oct 25 01:15:49 [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:35:plane 2A] state 000000009ac177a3
>Oct 25 01:15:49 [drm:intel_dp_detect [i915]] [CONNECTOR:90:DP-1]
>Oct 25 01:15:49 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000d0ba5f75
>Oct 25 01:15:49 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 000000009ac177a3 state to 00000000d0ba5f75
>Oct 25 01:15:49 [drm:intel_power_well_enable [i915]] enabling power well 2
>Oct 25 01:15:49 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 0000000036ed9464 state to 00000000d0ba5f75
>Oct 25 01:15:49 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:35:plane 2A] 0000000092bcc227 state to 00000000d0ba5f75
>Oct 25 01:15:49 [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:35:plane 2A] state 0000000092bcc227
>Oct 25 01:15:49 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:42:cursor A] 00000000e13d103c state to 00000000d0ba5f75
>Oct 25 01:15:49 [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:42:cursor A] state 00000000e13d103c
>Oct 25 01:15:49 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:46:plane 1B] 00000000418cfb59 state to 00000000d0ba5f75
>Oct 25 01:15:49 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:53:plane 2B] 00000000b3db0592 state to 00000000d0ba5f75
>Oct 25 01:15:49 [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:53:plane 2B] state 00000000b3db0592
>Oct 25 01:15:49 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:60:cursor B] 00000000f43575ba state to 00000000d0ba5f75
>Oct 25 01:15:49 [drm:intel_power_well_disable [i915]] disabling power well 2
>Oct 25 01:15:49 [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:60:cursor B] state 00000000f43575ba
>Oct 25 01:15:49 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:64:plane 1C] 00000000d12af5a6 state to 00000000d0ba5f75
>Oct 25 01:15:49 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:71:plane 2C] 00000000d733a28c state to 00000000d0ba5f75
>Oct 25 01:15:49 [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:90:DP-1] disconnected
>Oct 25 01:15:49 [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:71:plane 2C] state 00000000d733a28c
>Oct 25 01:15:49 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:78:cursor C] 000000006a5e68f8 state to 00000000d0ba5f75
>Oct 25 01:15:49 [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:78:cursor C] state 000000006a5e68f8
>Oct 25 01:15:49 [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:96:HDMI-A-1]
>Oct 25 01:15:49 [drm:drm_atomic_set_mode_for_crtc [drm]] Set [MODE:2880x1800] for [CRTC:45:pipe A] state 0000000036ed9464
>Oct 25 01:15:49 [drm:intel_hdmi_detect [i915]] [CONNECTOR:96:HDMI-A-1]
>Oct 25 01:15:49 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:109] for [PLANE:28:plane 1A] state 000000009ac177a3
>Oct 25 01:15:49 [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] timed out, falling back to bit banging on pin 4
>Oct 25 01:15:49 [drm:drm_do_probe_ddc_edid [drm]] drm: skipping non-existent adapter i915 gmbus dpc
>Oct 25 01:15:49 [drm:intel_hdmi_set_edid [i915]] HDMI GMBUS EDID read failed, retry using GPIO bit-banging
>Oct 25 01:15:49 [drm:intel_gmbus_force_bit [i915]] enabling bit-banging on i915 gmbus dpc. force bit now 1
>Oct 25 01:15:49 [drm:drm_do_probe_ddc_edid [drm]] drm: skipping non-existent adapter i915 gmbus dpc
>Oct 25 01:15:49 [drm:intel_gmbus_force_bit [i915]] disabling bit-banging on i915 gmbus dpc. force bit now 0
>Oct 25 01:15:49 [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] timed out, falling back to bit banging on pin 4
>Oct 25 01:15:49 [drm:drm_dp_dual_mode_detect [drm_kms_helper]] DP dual mode HDMI ID:  (err -6)
>Oct 25 01:15:49 [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:96:HDMI-A-1] disconnected
>Oct 25 01:15:49 [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:45:pipe A] to 00000000d0ba5f75
>Oct 25 01:15:49 [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:101:DP-2]
>Oct 25 01:15:49 [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:83:eDP-1] 00000000c3062f75 state to 00000000d0ba5f75
>Oct 25 01:15:49 [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:83:eDP-1] state 00000000c3062f75 to [NOCRTC]
>Oct 25 01:15:49 [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:83:eDP-1] state 00000000c3062f75 to [CRTC:45:pipe A]
>Oct 25 01:15:49 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000d0ba5f75
>Oct 25 01:15:49 [drm:intel_dp_detect [i915]] [CONNECTOR:101:DP-2]
>Oct 25 01:15:49 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 000000006a5e68f8 state to 00000000d0ba5f75
>Oct 25 01:15:49 [drm:intel_power_well_enable [i915]] enabling power well 2
>Oct 25 01:15:49 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 0000000036ed9464 state to 00000000d0ba5f75
>Oct 25 01:15:49 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:35:plane 2A] 00000000d733a28c state to 00000000d0ba5f75
>Oct 25 01:15:49 [drm:intel_power_well_disable [i915]] disabling power well 2
>Oct 25 01:15:49 [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:35:plane 2A] state 00000000d733a28c
>Oct 25 01:15:49 [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:101:DP-2] disconnected
>Oct 25 01:15:49 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:42:cursor A] 00000000d12af5a6 state to 00000000d0ba5f75
>Oct 25 01:15:49 [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:42:cursor A] state 00000000d12af5a6
>Oct 25 01:15:49 [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:106:HDMI-A-2]
>Oct 25 01:15:49 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:46:plane 1B] 00000000f43575ba state to 00000000d0ba5f75
>Oct 25 01:15:49 [drm:intel_hdmi_detect [i915]] [CONNECTOR:106:HDMI-A-2]
>Oct 25 01:15:49 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:53:plane 2B] 00000000b3db0592 state to 00000000d0ba5f75
>Oct 25 01:15:49 [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:53:plane 2B] state 00000000b3db0592
>Oct 25 01:15:49 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:60:cursor B] 00000000418cfb59 state to 00000000d0ba5f75
>Oct 25 01:15:49 [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:60:cursor B] state 00000000418cfb59
>Oct 25 01:15:49 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:64:plane 1C] 00000000e13d103c state to 00000000d0ba5f75
>Oct 25 01:15:49 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:71:plane 2C] 0000000092bcc227 state to 00000000d0ba5f75
>Oct 25 01:15:49 [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:71:plane 2C] state 0000000092bcc227
>Oct 25 01:15:49 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:78:cursor C] 000000009ac177a3 state to 00000000d0ba5f75
>Oct 25 01:15:49 [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:78:cursor C] state 000000009ac177a3
>Oct 25 01:15:49 [drm:drm_atomic_set_mode_for_crtc [drm]] Set [MODE:2880x1800] for [CRTC:45:pipe A] state 0000000036ed9464
>Oct 25 01:15:49 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:109] for [PLANE:28:plane 1A] state 000000006a5e68f8
>Oct 25 01:15:49 [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] timed out, falling back to bit banging on pin 6
>Oct 25 01:15:49 [drm:drm_do_probe_ddc_edid [drm]] drm: skipping non-existent adapter i915 gmbus dpd
>Oct 25 01:15:49 [drm:intel_hdmi_set_edid [i915]] HDMI GMBUS EDID read failed, retry using GPIO bit-banging
>Oct 25 01:15:49 [drm:intel_gmbus_force_bit [i915]] enabling bit-banging on i915 gmbus dpd. force bit now 1
>Oct 25 01:15:49 [drm:drm_do_probe_ddc_edid [drm]] drm: skipping non-existent adapter i915 gmbus dpd
>Oct 25 01:15:49 [drm:intel_gmbus_force_bit [i915]] disabling bit-banging on i915 gmbus dpd. force bit now 0
>Oct 25 01:15:49 [drm:gen8_de_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x11101010, pins 0x00000010, long 0x00000000
>Oct 25 01:15:49 [drm:intel_hpd_irq_handler [i915]] digital hpd port A - short
>Oct 25 01:15:49 [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port A - short
>Oct 25 01:15:49 [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 41 00 00 01 80 02 00 00 00 0f 0b 00
>Oct 25 01:15:49 [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] timed out, falling back to bit banging on pin 6
>Oct 25 01:15:49 [drm:drm_dp_dual_mode_detect [drm_kms_helper]] DP dual mode HDMI ID:  (err -6)
>Oct 25 01:15:49 [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:106:HDMI-A-2] disconnected
>Oct 25 01:15:49 [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:45:pipe A] to 00000000d0ba5f75
>Oct 25 01:15:49 [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:83:eDP-1] 00000000c3062f75 state to 00000000d0ba5f75
>Oct 25 01:15:49 [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:83:eDP-1] state 00000000c3062f75 to [NOCRTC]
>Oct 25 01:15:49 [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:83:eDP-1] state 00000000c3062f75 to [CRTC:45:pipe A]
>Oct 25 01:15:49 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:63:pipe B] 00000000025c715f state to 00000000d0ba5f75
>Oct 25 01:15:49 [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:63:pipe B] state 00000000025c715f
>Oct 25 01:15:49 [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:46:plane 1B] state 00000000f43575ba
>Oct 25 01:15:49 [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:63:pipe B] to 00000000d0ba5f75
>Oct 25 01:15:49 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:81:pipe C] 000000002b2f160e state to 00000000d0ba5f75
>Oct 25 01:15:49 [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:81:pipe C] state 000000002b2f160e
>Oct 25 01:15:49 [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:64:plane 1C] state 00000000e13d103c
>Oct 25 01:15:49 [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:81:pipe C] to 00000000d0ba5f75
>Oct 25 01:15:49 [drm:drm_mode_addfb2 [drm]] [FB:112]
>Oct 25 01:15:49 [drm:drm_atomic_check_only [drm]] checking 00000000d0ba5f75
>Oct 25 01:15:49 [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:83:eDP-1]
>Oct 25 01:15:49 [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:83:eDP-1] keeps [ENCODER:82:DDI A], now on [CRTC:45:pipe A]
>Oct 25 01:15:49 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 109
>Oct 25 01:15:49 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:15:49 [drm:drm_atomic_commit [drm]] committing 00000000d0ba5f75
>Oct 25 01:15:49 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:15:49 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:15:49 [drm:__intel_fb_obj_invalidate [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:15:49 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000d0ba5f75
>Oct 25 01:15:49 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000d0ba5f75
>Oct 25 01:15:49 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:15:49 [drm:drm_mode_addfb2 [drm]] [FB:111]
>Oct 25 01:15:49 [drm:drm_mode_setcrtc [drm]] [CRTC:45:pipe A]
>Oct 25 01:15:49 [drm:drm_mode_setcrtc [drm]] [CONNECTOR:83:eDP-1]
>Oct 25 01:15:49 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000566fc8d0
>Oct 25 01:15:49 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 000000005a27ec3d state to 00000000566fc8d0
>Oct 25 01:15:49 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000cbd08854 state to 00000000566fc8d0
>Oct 25 01:15:49 [drm:drm_atomic_set_mode_for_crtc [drm]] Set [MODE:2880x1800] for [CRTC:45:pipe A] state 000000005a27ec3d
>Oct 25 01:15:49 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:111] for [PLANE:28:plane 1A] state 00000000cbd08854
>Oct 25 01:15:49 [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:45:pipe A] to 00000000566fc8d0
>Oct 25 01:15:49 [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:83:eDP-1] 00000000a579152a state to 00000000566fc8d0
>Oct 25 01:15:49 [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:83:eDP-1] state 00000000a579152a to [NOCRTC]
>Oct 25 01:15:49 [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:83:eDP-1] state 00000000a579152a to [CRTC:45:pipe A]
>Oct 25 01:15:49 [drm:drm_atomic_check_only [drm]] checking 00000000566fc8d0
>Oct 25 01:15:49 [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:83:eDP-1]
>Oct 25 01:15:49 [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:83:eDP-1] keeps [ENCODER:82:DDI A], now on [CRTC:45:pipe A]
>Oct 25 01:15:49 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 111
>Oct 25 01:15:49 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:15:49 [drm:drm_atomic_commit [drm]] committing 00000000566fc8d0
>Oct 25 01:15:49 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:15:49 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:15:49 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000566fc8d0
>Oct 25 01:15:49 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000566fc8d0
>Oct 25 01:15:49 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:15:49 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:15:49 [drm:drm_mode_setcrtc [drm]] [CRTC:45:pipe A]
>Oct 25 01:15:49 [drm:drm_mode_setcrtc [drm]] [CONNECTOR:83:eDP-1]
>Oct 25 01:15:49 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000566fc8d0
>Oct 25 01:15:49 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000dddead2e state to 00000000566fc8d0
>Oct 25 01:15:49 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000c67faed5 state to 00000000566fc8d0
>Oct 25 01:15:49 [drm:drm_atomic_set_mode_for_crtc [drm]] Set [MODE:2880x1800] for [CRTC:45:pipe A] state 00000000dddead2e
>Oct 25 01:15:49 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:111] for [PLANE:28:plane 1A] state 00000000c67faed5
>Oct 25 01:15:49 [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:45:pipe A] to 00000000566fc8d0
>Oct 25 01:15:49 [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:83:eDP-1] 000000001f424b9e state to 00000000566fc8d0
>Oct 25 01:15:49 [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:83:eDP-1] state 000000001f424b9e to [NOCRTC]
>Oct 25 01:15:49 [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:83:eDP-1] state 000000001f424b9e to [CRTC:45:pipe A]
>Oct 25 01:15:49 [drm:drm_atomic_check_only [drm]] checking 00000000566fc8d0
>Oct 25 01:15:49 [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:83:eDP-1]
>Oct 25 01:15:49 [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:83:eDP-1] keeps [ENCODER:82:DDI A], now on [CRTC:45:pipe A]
>Oct 25 01:15:49 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 111
>Oct 25 01:15:49 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:15:49 [drm:drm_atomic_commit [drm]] committing 00000000566fc8d0
>Oct 25 01:15:49 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:15:49 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:15:49 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000566fc8d0
>Oct 25 01:15:49 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000566fc8d0
>Oct 25 01:15:49 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:15:49 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:15:49 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:15:49 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:15:49 audit: type=1130 audit(1540455349.372:11): pid=1 uid=0 auid=4294967295 ses=4294967295 subj=kernel msg='unit=systemd-vconsole-setup comm="systemd" exe="/usr/lib/systemd/systemd" hostname=? addr=? terminal=? res=success'
>Oct 25 01:15:49 audit: type=1131 audit(1540455349.372:12): pid=1 uid=0 auid=4294967295 ses=4294967295 subj=kernel msg='unit=systemd-vconsole-setup comm="systemd" exe="/usr/lib/systemd/systemd" hostname=? addr=? terminal=? res=success'
>Oct 25 01:15:49 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:15:49 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:15:49 [drm:gen8_de_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x11101010, pins 0x00000010, long 0x00000000
>Oct 25 01:15:49 [drm:intel_hpd_irq_handler [i915]] digital hpd port A - short
>Oct 25 01:15:49 [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port A - short
>Oct 25 01:15:49 [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 41 00 00 01 80 02 00 00 00 0f 0b 00
>Oct 25 01:15:52 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:15:52 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:15:52 [drm:edp_panel_vdd_off_sync [i915]] Turning eDP port A VDD off
>Oct 25 01:15:52 [drm:edp_panel_vdd_off_sync [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x00000007
>Oct 25 01:15:52 [drm:intel_power_well_disable [i915]] disabling DC off
>Oct 25 01:15:52 [drm:gen9_dc_off_power_well_disable [i915]] Enabling DC6
>Oct 25 01:15:52 [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>Oct 25 01:15:52 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:15:53 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:15:53 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:15:53 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:15:53 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:15:53 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:15:58 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:15:58 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:15:58 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:15:58 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:15:58 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:15:58 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:15:58 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:15:58 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:15:58 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:15:58 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:15:58 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:15:58 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:15:58 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:15:58 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:15:58 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:15:58 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:15:58 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:15:58 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:15:58 audit: type=1130 audit(1540455358.836:13): pid=1 uid=0 auid=4294967295 ses=4294967295 subj=kernel msg='unit=systemd-cryptsetup@luks\x2d7d238e07\x2dc0ca\x2d40f5\x2db0b8\x2d5272c02bd87b comm="systemd" exe="/usr/lib/systemd/systemd" hostname=? addr=? terminal=? res=success'
>Oct 25 01:15:58 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:15:58 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:15:58 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:15:58 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:15:58 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:15:59 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:15:59 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:15:59 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:15:59 audit: type=1130 audit(1540455359.128:14): pid=1 uid=0 auid=4294967295 ses=4294967295 subj=kernel msg='unit=dracut-initqueue comm="systemd" exe="/usr/lib/systemd/systemd" hostname=? addr=? terminal=? res=success'
>Oct 25 01:15:59 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:15:59 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:15:59 audit: type=1130 audit(1540455359.181:15): pid=1 uid=0 auid=4294967295 ses=4294967295 subj=kernel msg='unit=systemd-fsck-root comm="systemd" exe="/usr/lib/systemd/systemd" hostname=? addr=? terminal=? res=success'
>Oct 25 01:15:59 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:15:59 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:15:59 EXT4-fs (dm-0): mounted filesystem with ordered data mode. Opts: (null)
>Oct 25 01:15:59 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:15:59 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:15:59 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:15:59 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:15:59 audit: type=1130 audit(1540455359.382:16): pid=1 uid=0 auid=4294967295 ses=4294967295 subj=kernel msg='unit=initrd-parse-etc comm="systemd" exe="/usr/lib/systemd/systemd" hostname=? addr=? terminal=? res=success'
>Oct 25 01:15:59 audit: type=1131 audit(1540455359.382:17): pid=1 uid=0 auid=4294967295 ses=4294967295 subj=kernel msg='unit=initrd-parse-etc comm="systemd" exe="/usr/lib/systemd/systemd" hostname=? addr=? terminal=? res=success'
>Oct 25 01:15:59 audit: type=1130 audit(1540455359.396:18): pid=1 uid=0 auid=4294967295 ses=4294967295 subj=kernel msg='unit=dracut-cmdline comm="systemd" exe="/usr/lib/systemd/systemd" hostname=? addr=? terminal=? res=success'
>Oct 25 01:15:59 audit: type=1131 audit(1540455359.396:19): pid=1 uid=0 auid=4294967295 ses=4294967295 subj=kernel msg='unit=dracut-cmdline comm="systemd" exe="/usr/lib/systemd/systemd" hostname=? addr=? terminal=? res=success'
>Oct 25 01:15:59 audit: type=1130 audit(1540455359.399:20): pid=1 uid=0 auid=4294967295 ses=4294967295 subj=kernel msg='unit=systemd-sysctl comm="systemd" exe="/usr/lib/systemd/systemd" hostname=? addr=? terminal=? res=success'
>Oct 25 01:15:59 audit: type=1131 audit(1540455359.399:21): pid=1 uid=0 auid=4294967295 ses=4294967295 subj=kernel msg='unit=systemd-sysctl comm="systemd" exe="/usr/lib/systemd/systemd" hostname=? addr=? terminal=? res=success'
>Oct 25 01:15:59 audit: type=1130 audit(1540455359.400:22): pid=1 uid=0 auid=4294967295 ses=4294967295 subj=kernel msg='unit=systemd-tmpfiles-setup comm="systemd" exe="/usr/lib/systemd/systemd" hostname=? addr=? terminal=? res=success'
>Oct 25 01:15:59 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:15:59 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:15:59 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:00 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:00 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:00 systemd: 22 output lines suppressed due to ratelimiting
>Oct 25 01:16:00 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:00 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:00 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:00 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:00 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:00 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:00 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:00 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:00 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:00 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:00 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:00 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:00 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:00 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:00 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:00 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:00 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:00 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:00 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:00 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:00 SELinux:  Class bpf not defined in policy.
>Oct 25 01:16:00 SELinux:  Class xdp_socket not defined in policy.
>Oct 25 01:16:00 SELinux: the above unknown classes and permissions will be allowed
>Oct 25 01:16:00 SELinux:  policy capability network_peer_controls=1
>Oct 25 01:16:00 SELinux:  policy capability open_perms=1
>Oct 25 01:16:00 SELinux:  policy capability extended_socket_class=1
>Oct 25 01:16:00 SELinux:  policy capability always_check_network=0
>Oct 25 01:16:00 SELinux:  policy capability cgroup_seclabel=1
>Oct 25 01:16:00 SELinux:  policy capability nnp_nosuid_transition=1
>Oct 25 01:16:00 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:00 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:00 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:00 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:00 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:00 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:00 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:00 random: crng init done
>Oct 25 01:16:00 random: 7 urandom warning(s) missed due to ratelimiting
>Oct 25 01:16:00 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:00 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:00 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:00 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:00 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:00 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:00 EXT4-fs (dm-0): re-mounted. Opts: (null)
>Oct 25 01:16:00 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:00 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:00 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:00 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:00 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:00 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:00 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:00 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:00 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:01 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:01 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:01 apple_gmux: Found gmux version 4.0.29 [indexed]
>Oct 25 01:16:01 smbus_hc ACPI0001:00: SBS HC: offset = 0x20, query_bit = 0x10
>Oct 25 01:16:01 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:01 ACPI: Smart Battery System [SBS0]: AC Adapter [AC0] (on-line)
>Oct 25 01:16:01 thunderbolt 0000:06:00.0: NHI initialized, starting thunderbolt
>Oct 25 01:16:01 thunderbolt 0000:06:00.0: allocating TX ring 0 of size 10
>Oct 25 01:16:01 thunderbolt 0000:06:00.0: allocating RX ring 0 of size 10
>Oct 25 01:16:01 thunderbolt 0000:06:00.0: control channel created
>Oct 25 01:16:01 thunderbolt 0000:06:00.0: control channel starting...
>Oct 25 01:16:01 thunderbolt 0000:06:00.0: starting TX ring 0
>Oct 25 01:16:01 thunderbolt 0000:06:00.0: enabling interrupt at register 0x38200 bit 0 (0x0 -> 0x1)
>Oct 25 01:16:01 thunderbolt 0000:06:00.0: starting RX ring 0
>Oct 25 01:16:01 thunderbolt 0000:06:00.0: enabling interrupt at register 0x38200 bit 12 (0x1 -> 0x1001)
>Oct 25 01:16:01 thunderbolt 0000:06:00.0: starting ICM firmware
>Oct 25 01:16:01 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:01 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:01 Bluetooth: Core ver 2.22
>Oct 25 01:16:01 NET: Registered protocol family 31
>Oct 25 01:16:01 Bluetooth: HCI device and connection manager initialized
>Oct 25 01:16:01 Bluetooth: HCI socket layer initialized
>Oct 25 01:16:01 Bluetooth: L2CAP socket layer initialized
>Oct 25 01:16:01 Bluetooth: SCO socket layer initialized
>Oct 25 01:16:01 Bluetooth: HCI UART driver ver 2.3
>Oct 25 01:16:01 Bluetooth: HCI UART protocol H4 registered
>Oct 25 01:16:01 Bluetooth: HCI UART protocol BCSP registered
>Oct 25 01:16:01 Bluetooth: HCI UART protocol LL registered
>Oct 25 01:16:01 Bluetooth: HCI UART protocol ATH3K registered
>Oct 25 01:16:01 Bluetooth: HCI UART protocol Three-wire (H5) registered
>Oct 25 01:16:01 Bluetooth: HCI UART protocol Intel registered
>Oct 25 01:16:01 Bluetooth: HCI UART protocol Broadcom registered
>Oct 25 01:16:01 Bluetooth: HCI UART protocol QCA registered
>Oct 25 01:16:01 Bluetooth: HCI UART protocol AG6XX registered
>Oct 25 01:16:01 Bluetooth: HCI UART protocol Marvell registered
>Oct 25 01:16:01 hci_uart_bcm serial1-0: Unexpected ACPI gpio_int_idx: -1
>Oct 25 01:16:01 hci_uart_bcm serial1-0: Unexpected number of ACPI GPIOs: 0
>Oct 25 01:16:01 hci_uart_bcm serial1-0: No reset resource, using default baud rate
>Oct 25 01:16:01 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:01 [drm:intel_backlight_device_update_status [i915]] updating intel_backlight, brightness=1388/2777
>Oct 25 01:16:01 [drm:intel_panel_actually_set_backlight [i915]] set backlight PWM = 1388
>Oct 25 01:16:01 [drm:intel_power_well_enable [i915]] enabling DC off
>Oct 25 01:16:01 [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>Oct 25 01:16:01 [drm:intel_power_well_disable [i915]] disabling DC off
>Oct 25 01:16:01 [drm:gen9_dc_off_power_well_disable [i915]] Enabling DC6
>Oct 25 01:16:01 [drm:gen9_set_dc_state [i915]] Setting DC state from 00 to 02
>Oct 25 01:16:01 ttyS5 - failed to request DMA
>Oct 25 01:16:01 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:01 ACPI: Smart Battery System [SBS0]: Battery Slot [BAT0] (battery present)
>Oct 25 01:16:01 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:01 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:01 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:01 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:01 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:01 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:01 Bluetooth: hci0: BCM: failed to write update baudrate (-16)
>Oct 25 01:16:01 Bluetooth: hci0: Failed to set baudrate
>Oct 25 01:16:01 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:01 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:01 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:01 input: Apple Inc. iBridge as /devices/pci0000:00/0000:00:14.0/usb1/1-3/1-3:1.2/0003:05AC:8600.0001/input/input9
>Oct 25 01:16:01 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:01 media: Linux media interface: v0.10
>Oct 25 01:16:01 Bluetooth: hci0: BCM: chip id 126
>Oct 25 01:16:01 Bluetooth: hci0: BCM: features 0x2f
>Oct 25 01:16:01 mei_me 0000:00:16.0: enabling device (0000 -> 0002)
>Oct 25 01:16:01 idma64 idma64.0: Found Intel integrated DMA 64-bit
>Oct 25 01:16:01 idma64 idma64.2: Found Intel integrated DMA 64-bit
>Oct 25 01:16:01 Bluetooth: hci0: BCM20703A2 Generic UART UHE Apple 40MHz wlcsp_x100
>Oct 25 01:16:01 Bluetooth: hci0: BCM (001.002.070) build 0176
>Oct 25 01:16:01 bluetooth hci0: Direct firmware load for brcm/BCM.hcd failed with error -2
>Oct 25 01:16:01 Bluetooth: hci0: BCM: Patch brcm/BCM.hcd not found
>Oct 25 01:16:01 idma64 idma64.3: Found Intel integrated DMA 64-bit
>Oct 25 01:16:01 i801_smbus 0000:00:1f.4: enabling device (0000 -> 0003)
>Oct 25 01:16:01 i801_smbus 0000:00:1f.4: SMBus using PCI interrupt
>Oct 25 01:16:01 cfg80211: Loading compiled-in X.509 certificates for regulatory database
>Oct 25 01:16:01 videodev: Linux video capture interface: v2.00
>Oct 25 01:16:01 cfg80211: Loaded X.509 cert 'sforshee: 00b28ddf47aef9cea7'
>Oct 25 01:16:01 idma64 idma64.4: Found Intel integrated DMA 64-bit
>Oct 25 01:16:01 idma64 idma64.5: Found Intel integrated DMA 64-bit
>Oct 25 01:16:01 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:01 input: PC Speaker as /devices/platform/pcspkr/input/input10
>Oct 25 01:16:01 uvcvideo: Found UVC 1.50 device iBridge (05ac:8600)
>Oct 25 01:16:01 uvcvideo 1-3:1.0: Entity type for entity Camera 1 was not initialized!
>Oct 25 01:16:01 usbcore: registered new interface driver uvcvideo
>Oct 25 01:16:01 USB Video Class driver (1.1.1)
>Oct 25 01:16:01 apple-ibridge-hid 0003:05AC:8600.0001: input,hidraw0: USB HID v1.01 Keyboard [Apple Inc. iBridge] on usb-0000:00:14.0-3/input2
>Oct 25 01:16:01 apple-ib-als: Found ambient light sensor
>Oct 25 01:16:01 apple-ibridge-hid 0003:05AC:8600.0002: device probe done.
>Oct 25 01:16:01 apple-ibridge-hid 0003:05AC:8600.0002: hiddev96,hidraw1: USB HID v1.01 Device [Apple Inc. iBridge] on usb-0000:00:14.0-3/input3
>Oct 25 01:16:01 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:01 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:01 apple-ibridge: registered driver 'apple-ib-als'
>Oct 25 01:16:01 RAPL PMU: API unit is 2^-32 Joules, 5 fixed counters, 655360 ms ovfl timer
>Oct 25 01:16:01 RAPL PMU: hw unit of domain pp0-core 2^-14 Joules
>Oct 25 01:16:01 RAPL PMU: hw unit of domain package 2^-14 Joules
>Oct 25 01:16:01 RAPL PMU: hw unit of domain dram 2^-14 Joules
>Oct 25 01:16:01 RAPL PMU: hw unit of domain pp1-gpu 2^-14 Joules
>Oct 25 01:16:01 RAPL PMU: hw unit of domain psys 2^-14 Joules
>Oct 25 01:16:01 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:01 usbcore: registered new interface driver brcmfmac
>Oct 25 01:16:01 brcmfmac 0000:03:00.0: enabling device (0000 -> 0002)
>Oct 25 01:16:01 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:01 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:01 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:01 applesmc: key=858 fan=2 temp=46 index=45 acc=0 lux=0 kbd=0
>Oct 25 01:16:01 applesmc applesmc.768: hwmon_device_register() is deprecated. Please convert the driver to use hwmon_device_register_with_info().
>Oct 25 01:16:01 brcmfmac: brcmf_fw_alloc_request: using brcm/brcmfmac43602-pcie for chip BCM43602/2
>Oct 25 01:16:01 brcmfmac 0000:03:00.0: Direct firmware load for brcm/brcmfmac43602-pcie.txt failed with error -2
>Oct 25 01:16:01 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:01 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:01 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:01 usbcore: registered new interface driver rtl8812au
>Oct 25 01:16:01 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:02 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:02 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:02 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:02 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:02 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:02 brcmfmac: brcmf_fw_alloc_request: using brcm/brcmfmac43602-pcie for chip BCM43602/2
>Oct 25 01:16:02 brcmfmac 0000:03:00.0: Direct firmware load for brcm/brcmfmac43602-pcie.clm_blob failed with error -2
>Oct 25 01:16:02 brcmfmac: brcmf_c_process_clm_blob: no clm_blob available (err=-2), device may have limited channels available
>Oct 25 01:16:02 brcmfmac: brcmf_c_preinit_dcmds: Firmware: BCM43602/2 wl0: Nov 10 2015 06:38:10 version 7.35.177.61 (r598657) FWID 01-ea662a8c
>Oct 25 01:16:02 intel_rapl: Found RAPL domain package
>Oct 25 01:16:02 intel_rapl: Found RAPL domain core
>Oct 25 01:16:02 intel_rapl: Found RAPL domain uncore
>Oct 25 01:16:02 intel_rapl: Found RAPL domain dram
>Oct 25 01:16:02 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:02 RTL871X: module init start
>Oct 25 01:16:02 RTL871X: rtl8812au v4.3.14_13455.20150212_BTCOEX20150128-51
>Oct 25 01:16:02 RTL871X: rtl8812au BT-Coex version = BTCOEX20150128-51
>Oct 25 01:16:02 ------------[ cut here ]------------
>Oct 25 01:16:02 proc_dir_entry 'net/rtl8812au' already registered
>Oct 25 01:16:02 WARNING: CPU: 4 PID: 732 at fs/proc/generic.c:360 proc_register+0x104/0x140
>Oct 25 01:16:02 Modules linked in: intel_rapl(E) rtl8812au(OE+) acpi_cpufreq(E-) x86_pkg_temp_thermal(E) intel_powerclamp(E) coretemp(E) kvm_intel(E) applesmc(E) input_polldev(E) kvm(E) brcmfmac(E) brcmutil(E) irqbypass(E) mmc_core(E) intel_cstate(E) intel_uncore(E) intel_rapl_perf(E) 8812au(OE) uvcvideo(E) pcspkr(E) videobuf2_vmalloc(E) videobuf2_memops(E) videobuf2_v4l2(E) videobuf2_common(E) videodev(E) i2c_i801(E) mei_me(E) joydev(E) cfg80211(E) media(E) mei(E) idma64(E) pcc_cpufreq(E) hci_uart(E) btqca(E) btrtl(E) btbcm(E) btintel(E) bluetooth(E) thunderbolt(E+) apple_ib_als(OE) industrialio_triggered_buffer(E) kfifo_buf(E) industrialio(E) ecdh_generic(E) sbs(E) rfkill(E) sbshc(E) apple_gmux(E) apple_bl(E) dm_crypt(E) i915(E) spi_pxa2xx_platform(E) apple_ib_tb(OE) i2c_algo_bit(E) drm_kms_helper(E)
>Oct 25 01:16:02  crct10dif_pclmul(E) crc32_pclmul(E) crc32c_intel(E) drm(E) ghash_clmulni_intel(E) nvme(E) nvme_core(E) intel_lpss_pci(E) intel_lpss(E) applespi(OE) apple_ibridge(OE) video(E)
>Oct 25 01:16:02 CPU: 4 PID: 732 Comm: systemd-udevd Tainted: G        W  OE     4.19.0-rc8-drm #14
>Oct 25 01:16:02 Hardware name: Apple Inc. MacBookPro13,3/Mac-A5C67F76ED83108C, BIOS MBP133.88Z.0247.B00.1806261159 06/26/2018
>Oct 25 01:16:02 RIP: 0010:proc_register+0x104/0x140
>Oct 25 01:16:02 Code: 6b b9 e8 5f 3c 6c 00 48 89 d8 5b 5d 41 5c 41 5d 41 5e c3 49 8b b4 24 d8 00 00 00 4c 89 f2 48 c7 c7 78 65 30 b9 e8 64 93 d2 ff <0f> 0b 48 c7 c7 40 0e 6b b9 e8 2e 3c 6c 00 8b 83 94 00 00 00 48 c7
>Oct 25 01:16:02 RSP: 0018:ffffabe0c27bbc40 EFLAGS: 00010286
>Oct 25 01:16:02 RAX: 0000000000000000 RBX: ffff9df559c31c00 RCX: 0000000000000006
>Oct 25 01:16:02 RDX: 0000000000000007 RSI: ffff9df559cbc8e8 RDI: ffff9df56e5d6c80
>Oct 25 01:16:02 RBP: ffff9df56adbf1c0 R08: 00000012dca9106c R09: 0000000000000000
>Oct 25 01:16:02 R10: 0000000000000000 R11: 0000000000000000 R12: ffff9df56b731900
>Oct 25 01:16:02 R13: ffff9df56b7319b8 R14: ffff9df559c31ce3 R15: ffffffffc104b140
>Oct 25 01:16:02 FS:  00007f8a81c97180(0000) GS:ffff9df56e400000(0000) knlGS:0000000000000000
>Oct 25 01:16:02 CS:  0010 DS: 0000 ES: 0000 CR0: 0000000080050033
>Oct 25 01:16:02 CR2: 0000559357479730 CR3: 0000000459cba002 CR4: 00000000003606e0
>Oct 25 01:16:02 DR0: 0000000000000000 DR1: 0000000000000000 DR2: 0000000000000000
>Oct 25 01:16:02 DR3: 0000000000000000 DR6: 00000000fffe0ff0 DR7: 0000000000000400
>Oct 25 01:16:02 Call Trace:
>Oct 25 01:16:02  ? 0xffffffffc0e20000
>Oct 25 01:16:02  proc_mkdir_data+0x63/0x80
>Oct 25 01:16:02  rtw_drv_proc_init+0x34/0xa5 [rtl8812au]
>Oct 25 01:16:02  rtw_drv_entry+0x63/0x1000 [rtl8812au]
>Oct 25 01:16:02  do_one_initcall+0x5d/0x2be
>Oct 25 01:16:02  ? do_init_module+0x22/0x210
>Oct 25 01:16:02  ? rcu_read_lock_sched_held+0x6b/0x80
>Oct 25 01:16:02  ? kmem_cache_alloc_trace+0x24e/0x280
>Oct 25 01:16:02  do_init_module+0x5a/0x210
>Oct 25 01:16:02  load_module+0x2094/0x2330
>Oct 25 01:16:02  ? lockdep_hardirqs_on+0xed/0x180
>Oct 25 01:16:02  ? __do_sys_init_module+0x147/0x190
>Oct 25 01:16:02  __do_sys_init_module+0x147/0x190
>Oct 25 01:16:02  do_syscall_64+0x60/0x1f0
>Oct 25 01:16:02  entry_SYSCALL_64_after_hwframe+0x49/0xbe
>Oct 25 01:16:02 RIP: 0033:0x7f8a808c386a
>Oct 25 01:16:02 Code: 48 8b 0d 39 e6 2b 00 f7 d8 64 89 01 48 83 c8 ff c3 66 2e 0f 1f 84 00 00 00 00 00 0f 1f 44 00 00 49 89 ca b8 af 00 00 00 0f 05 <48> 3d 01 f0 ff ff 73 01 c3 48 8b 0d 06 e6 2b 00 f7 d8 64 89 01 48
>Oct 25 01:16:02 RSP: 002b:00007ffcc02aa338 EFLAGS: 00000246 ORIG_RAX: 00000000000000af
>Oct 25 01:16:02 RAX: ffffffffffffffda RBX: 0000562b859766f0 RCX: 00007f8a808c386a
>Oct 25 01:16:02 RDX: 00007f8a8142a4cd RSI: 00000000002f87a8 RDI: 0000562b865c7ae0
>Oct 25 01:16:02 RBP: 00007f8a8142a4cd R08: 0000000000000002 R09: 0000000000000001
>Oct 25 01:16:02 R10: 0000562b85900010 R11: 0000000000000246 R12: 0000562b865c7ae0
>Oct 25 01:16:02 R13: 0000562b859662c0 R14: 0000000000020000 R15: 0000000000000000
>Oct 25 01:16:02 irq event stamp: 171666
>Oct 25 01:16:02 hardirqs last  enabled at (171665): [<ffffffffb8134ead>] console_unlock+0x45d/0x600
>Oct 25 01:16:02 hardirqs last disabled at (171666): [<ffffffffb8003828>] trace_hardirqs_off_thunk+0x1a/0x1c
>Oct 25 01:16:02 softirqs last  enabled at (170674): [<ffffffffb8e00342>] __do_softirq+0x342/0x437
>Oct 25 01:16:02 softirqs last disabled at (170667): [<ffffffffb80c232d>] irq_exit+0x10d/0x120
>Oct 25 01:16:02 WARNING: CPU: 4 PID: 732 at fs/proc/generic.c:360 proc_register+0x104/0x140
>Oct 25 01:16:02 ---[ end trace dbb7f0af966ae831 ]---
>Oct 25 01:16:02 WARNING: CPU: 4 PID: 732 at /var/lib/dkms/rtl8812au/4.3.14/build/os_dep/linux/rtw_proc.c:193 rtw_drv_proc_init+0x99/0xa5 [rtl8812au]
>Oct 25 01:16:02 Modules linked in: intel_rapl(E) rtl8812au(OE+) acpi_cpufreq(E-) x86_pkg_temp_thermal(E) intel_powerclamp(E) coretemp(E) kvm_intel(E) applesmc(E) input_polldev(E) kvm(E) brcmfmac(E) brcmutil(E) irqbypass(E) mmc_core(E) intel_cstate(E) intel_uncore(E) intel_rapl_perf(E) 8812au(OE) uvcvideo(E) pcspkr(E) videobuf2_vmalloc(E) videobuf2_memops(E) videobuf2_v4l2(E) videobuf2_common(E) videodev(E) i2c_i801(E) mei_me(E) joydev(E) cfg80211(E) media(E) mei(E) idma64(E) pcc_cpufreq(E) hci_uart(E) btqca(E) btrtl(E) btbcm(E) btintel(E) bluetooth(E) thunderbolt(E+) apple_ib_als(OE) industrialio_triggered_buffer(E) kfifo_buf(E) industrialio(E) ecdh_generic(E) sbs(E) rfkill(E) sbshc(E) apple_gmux(E) apple_bl(E) dm_crypt(E) i915(E) spi_pxa2xx_platform(E) apple_ib_tb(OE) i2c_algo_bit(E) drm_kms_helper(E)
>Oct 25 01:16:02  crct10dif_pclmul(E) crc32_pclmul(E) crc32c_intel(E) drm(E) ghash_clmulni_intel(E) nvme(E) nvme_core(E) intel_lpss_pci(E) intel_lpss(E) applespi(OE) apple_ibridge(OE) video(E)
>Oct 25 01:16:02 CPU: 4 PID: 732 Comm: systemd-udevd Tainted: G        W  OE     4.19.0-rc8-drm #14
>Oct 25 01:16:02 Hardware name: Apple Inc. MacBookPro13,3/Mac-A5C67F76ED83108C, BIOS MBP133.88Z.0247.B00.1806261159 06/26/2018
>Oct 25 01:16:02 RIP: 0010:rtw_drv_proc_init+0x99/0xa5 [rtl8812au]
>Oct 25 01:16:02 Code: 00 03 fa c0 48 8b 15 13 ac 0e 00 be b6 81 00 00 48 c7 c7 03 c9 fa c0 e8 22 c3 42 f7 48 89 c2 b8 01 00 00 00 48 85 d2 74 04 c3 <0f> 0b c3 0f 0b b8 00 00 00 00 eb f3 0f 1f 44 00 00 48 8b 35 dc ab
>Oct 25 01:16:02 RSP: 0018:ffffabe0c27bbc88 EFLAGS: 00010246
>Oct 25 01:16:02 RAX: 0000000000000000 RBX: 00000000ffffffff RCX: 00000000000000ff
>Oct 25 01:16:02 RDX: ffff9df56b731900 RSI: 00000000ffffffff RDI: 0000000000000246
>Oct 25 01:16:02 RBP: ffffffffc0e20000 R08: 0000000000000001 R09: 0000000000000000
>Oct 25 01:16:02 R10: 0000000000000000 R11: 0000000000000000 R12: ffffffffc104b340
>Oct 25 01:16:02 R13: ffffffffc104b158 R14: ffffabe0c27bbe88 R15: ffffffffc104b140
>Oct 25 01:16:02 FS:  00007f8a81c97180(0000) GS:ffff9df56e400000(0000) knlGS:0000000000000000
>Oct 25 01:16:02 CS:  0010 DS: 0000 ES: 0000 CR0: 0000000080050033
>Oct 25 01:16:02 CR2: 0000559357479730 CR3: 0000000459cba002 CR4: 00000000003606e0
>Oct 25 01:16:02 DR0: 0000000000000000 DR1: 0000000000000000 DR2: 0000000000000000
>Oct 25 01:16:02 DR3: 0000000000000000 DR6: 00000000fffe0ff0 DR7: 0000000000000400
>Oct 25 01:16:02 Call Trace:
>Oct 25 01:16:02  rtw_drv_entry+0x63/0x1000 [rtl8812au]
>Oct 25 01:16:02  do_one_initcall+0x5d/0x2be
>Oct 25 01:16:02  ? do_init_module+0x22/0x210
>Oct 25 01:16:02  ? rcu_read_lock_sched_held+0x6b/0x80
>Oct 25 01:16:02  ? kmem_cache_alloc_trace+0x24e/0x280
>Oct 25 01:16:02  do_init_module+0x5a/0x210
>Oct 25 01:16:02  load_module+0x2094/0x2330
>Oct 25 01:16:02  ? lockdep_hardirqs_on+0xed/0x180
>Oct 25 01:16:02  ? __do_sys_init_module+0x147/0x190
>Oct 25 01:16:02  __do_sys_init_module+0x147/0x190
>Oct 25 01:16:02  do_syscall_64+0x60/0x1f0
>Oct 25 01:16:02  entry_SYSCALL_64_after_hwframe+0x49/0xbe
>Oct 25 01:16:02 RIP: 0033:0x7f8a808c386a
>Oct 25 01:16:02 Code: 48 8b 0d 39 e6 2b 00 f7 d8 64 89 01 48 83 c8 ff c3 66 2e 0f 1f 84 00 00 00 00 00 0f 1f 44 00 00 49 89 ca b8 af 00 00 00 0f 05 <48> 3d 01 f0 ff ff 73 01 c3 48 8b 0d 06 e6 2b 00 f7 d8 64 89 01 48
>Oct 25 01:16:02 RSP: 002b:00007ffcc02aa338 EFLAGS: 00000246 ORIG_RAX: 00000000000000af
>Oct 25 01:16:02 RAX: ffffffffffffffda RBX: 0000562b859766f0 RCX: 00007f8a808c386a
>Oct 25 01:16:02 RDX: 00007f8a8142a4cd RSI: 00000000002f87a8 RDI: 0000562b865c7ae0
>Oct 25 01:16:02 RBP: 00007f8a8142a4cd R08: 0000000000000002 R09: 0000000000000001
>Oct 25 01:16:02 R10: 0000562b85900010 R11: 0000000000000246 R12: 0000562b865c7ae0
>Oct 25 01:16:02 R13: 0000562b859662c0 R14: 0000000000020000 R15: 0000000000000000
>Oct 25 01:16:02 irq event stamp: 171674
>Oct 25 01:16:02 hardirqs last  enabled at (171673): [<ffffffffb82c26f1>] kmem_cache_free+0xa1/0x2e0
>Oct 25 01:16:02 hardirqs last disabled at (171674): [<ffffffffb8003828>] trace_hardirqs_off_thunk+0x1a/0x1c
>Oct 25 01:16:02 softirqs last  enabled at (170674): [<ffffffffb8e00342>] __do_softirq+0x342/0x437
>Oct 25 01:16:02 softirqs last disabled at (170667): [<ffffffffb80c232d>] irq_exit+0x10d/0x120
>Oct 25 01:16:02 WARNING: CPU: 4 PID: 732 at /var/lib/dkms/rtl8812au/4.3.14/build/os_dep/linux/rtw_proc.c:193 rtw_drv_proc_init+0x99/0xa5 [rtl8812au]
>Oct 25 01:16:02 ---[ end trace dbb7f0af966ae832 ]---
>Oct 25 01:16:02 Error: Driver 'rtl8812au' is already registered, aborting...
>Oct 25 01:16:02 RTL871X: module init ret=-16
>Oct 25 01:16:02 brcmfmac 0000:03:00.0 wlp3s0: renamed from wlan1
>Oct 25 01:16:02 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:02 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:02 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:02 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:02 Adding 16352652k swap on /var/cache/swapfile.  Priority:-2 extents:14 across:17646988k SSDsFS
>Oct 25 01:16:02 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:02 rtl8812au 1-5:1.0 wlp0s20f0u5: renamed from wlan0
>Oct 25 01:16:02 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:02 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:02 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:02 thunderbolt 0000:06:00.0: current switch config:
>Oct 25 01:16:02 thunderbolt 0000:06:00.0:  Switch: 8086:15d3 (Revision: 6, TB Version: 2)
>Oct 25 01:16:02 thunderbolt 0000:06:00.0:   Max Port Number: 11
>Oct 25 01:16:02 thunderbolt 0000:06:00.0:   Config:
>Oct 25 01:16:02 thunderbolt 0000:06:00.0:    Upstream Port Number: 5 Depth: 0 Route String: 0x0 Enabled: 1, PlugEventsDelay: 254ms
>Oct 25 01:16:02 thunderbolt 0000:06:00.0:    unknown1: 0x0 unknown4: 0x0
>Oct 25 01:16:02 thunderbolt 0000:06:00.0: 0: uid: 0x15a4820626a00
>Oct 25 01:16:02 thunderbolt 0000:06:00.0:  Port 0: 8086:15d3 (Revision: 6, TB Version: 1, Type: Port (0x1))
>Oct 25 01:16:02 thunderbolt 0000:06:00.0:   Max hop id (in/out): 7/7
>Oct 25 01:16:02 thunderbolt 0000:06:00.0:   Max counters: 8
>Oct 25 01:16:02 thunderbolt 0000:06:00.0:   NFC Credits: 0x800000
>Oct 25 01:16:02 thunderbolt 0000:06:00.0:  Port 1: 8086:15d3 (Revision: 6, TB Version: 1, Type: Port (0x1))
>Oct 25 01:16:02 thunderbolt 0000:06:00.0:   Max hop id (in/out): 15/15
>Oct 25 01:16:02 thunderbolt 0000:06:00.0:   Max counters: 16
>Oct 25 01:16:02 thunderbolt 0000:06:00.0:   NFC Credits: 0x3c00000
>Oct 25 01:16:02 thunderbolt 0000:06:00.0:  Port 2: 8086:15d3 (Revision: 6, TB Version: 1, Type: Port (0x1))
>Oct 25 01:16:02 thunderbolt 0000:06:00.0:   Max hop id (in/out): 15/15
>Oct 25 01:16:02 thunderbolt 0000:06:00.0:   Max counters: 16
>Oct 25 01:16:02 thunderbolt 0000:06:00.0:   NFC Credits: 0x3c00000
>Oct 25 01:16:02 thunderbolt 0000:06:00.0:  Port 3: 8086:15d3 (Revision: 6, TB Version: 1, Type: Port (0x1))
>Oct 25 01:16:02 thunderbolt 0000:06:00.0:   Max hop id (in/out): 15/15
>Oct 25 01:16:02 thunderbolt 0000:06:00.0:   Max counters: 16
>Oct 25 01:16:02 thunderbolt 0000:06:00.0:   NFC Credits: 0x3c00000
>Oct 25 01:16:02 thunderbolt 0000:06:00.0:  Port 4: 8086:15d3 (Revision: 6, TB Version: 1, Type: Port (0x1))
>Oct 25 01:16:02 thunderbolt 0000:06:00.0:   Max hop id (in/out): 15/15
>Oct 25 01:16:02 thunderbolt 0000:06:00.0:   Max counters: 16
>Oct 25 01:16:02 thunderbolt 0000:06:00.0:   NFC Credits: 0x3c00000
>Oct 25 01:16:02 thunderbolt 0000:06:00.0:  Port 5: 8086:15d3 (Revision: 6, TB Version: 1, Type: NHI (0x2))
>Oct 25 01:16:02 thunderbolt 0000:06:00.0:   Max hop id (in/out): 11/11
>Oct 25 01:16:02 thunderbolt 0000:06:00.0:   Max counters: 16
>Oct 25 01:16:02 thunderbolt 0000:06:00.0:   NFC Credits: 0x1000000
>Oct 25 01:16:02 thunderbolt 0000:06:00.0:  Port 6: 8086:15d3 (Revision: 6, TB Version: 1, Type: PCIe (0x100101))
>Oct 25 01:16:02 thunderbolt 0000:06:00.0:   Max hop id (in/out): 8/8
>Oct 25 01:16:02 thunderbolt 0000:06:00.0:   Max counters: 2
>Oct 25 01:16:02 thunderbolt 0000:06:00.0:   NFC Credits: 0x800000
>Oct 25 01:16:02 thunderbolt 0000:06:00.0:  Port 7: 8086:15d3 (Revision: 6, TB Version: 1, Type: PCIe (0x100101))
>Oct 25 01:16:02 thunderbolt 0000:06:00.0:   Max hop id (in/out): 8/8
>Oct 25 01:16:02 thunderbolt 0000:06:00.0:   Max counters: 2
>Oct 25 01:16:02 thunderbolt 0000:06:00.0:   NFC Credits: 0x800000
>Oct 25 01:16:02 thunderbolt 0000:06:00.0: 0:8: disabled by eeprom
>Oct 25 01:16:02 thunderbolt 0000:06:00.0:  Port 9: 8086:15d3 (Revision: 6, TB Version: 1, Type: DP/HDMI (0xe0101))
>Oct 25 01:16:02 thunderbolt 0000:06:00.0:   Max hop id (in/out): 9/9
>Oct 25 01:16:02 thunderbolt 0000:06:00.0:   Max counters: 2
>Oct 25 01:16:02 thunderbolt 0000:06:00.0:   NFC Credits: 0x1000000
>Oct 25 01:16:02 thunderbolt 0000:06:00.0:  Port 10: 8086:15d3 (Revision: 6, TB Version: 1, Type: DP/HDMI (0xe0101))
>Oct 25 01:16:02 thunderbolt 0000:06:00.0:   Max hop id (in/out): 9/9
>Oct 25 01:16:02 thunderbolt 0000:06:00.0:   Max counters: 2
>Oct 25 01:16:02 thunderbolt 0000:06:00.0:   NFC Credits: 0x1000000
>Oct 25 01:16:02 thunderbolt 0000:06:00.0: 0:b: disabled by eeprom
>Oct 25 01:16:02 thunderbolt 0000:7c:00.0: NHI initialized, starting thunderbolt
>Oct 25 01:16:02 thunderbolt 0000:7c:00.0: allocating TX ring 0 of size 10
>Oct 25 01:16:02 thunderbolt 0000:7c:00.0: allocating RX ring 0 of size 10
>Oct 25 01:16:02 thunderbolt 0000:7c:00.0: control channel created
>Oct 25 01:16:02 thunderbolt 0000:7c:00.0: control channel starting...
>Oct 25 01:16:02 thunderbolt 0000:7c:00.0: starting TX ring 0
>Oct 25 01:16:02 thunderbolt 0000:7c:00.0: enabling interrupt at register 0x38200 bit 0 (0x0 -> 0x1)
>Oct 25 01:16:02 thunderbolt 0000:7c:00.0: starting RX ring 0
>Oct 25 01:16:02 thunderbolt 0000:7c:00.0: enabling interrupt at register 0x38200 bit 12 (0x1 -> 0x1001)
>Oct 25 01:16:02 thunderbolt 0000:7c:00.0: starting ICM firmware
>Oct 25 01:16:02 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:02 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:02 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:02 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:02 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:02 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:02 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:02 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:02 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:02 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:02 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:02 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:02 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:02 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:02 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:03 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:03 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:03 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:03 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:03 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:03 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:03 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:03 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:03 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:03 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:03 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:03 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:03 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:03 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:03 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:03 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:03 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:03 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:03 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:03 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:03 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:03 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:03 thunderbolt 0000:7c:00.0: current switch config:
>Oct 25 01:16:03 thunderbolt 0000:7c:00.0:  Switch: 8086:15d3 (Revision: 6, TB Version: 2)
>Oct 25 01:16:03 thunderbolt 0000:7c:00.0:   Max Port Number: 11
>Oct 25 01:16:03 thunderbolt 0000:7c:00.0:   Config:
>Oct 25 01:16:03 thunderbolt 0000:7c:00.0:    Upstream Port Number: 5 Depth: 0 Route String: 0x0 Enabled: 1, PlugEventsDelay: 254ms
>Oct 25 01:16:03 thunderbolt 0000:7c:00.0:    unknown1: 0x0 unknown4: 0x0
>Oct 25 01:16:03 thunderbolt 0000:7c:00.0: 0: uid: 0x15a4820626a01
>Oct 25 01:16:03 thunderbolt 0000:7c:00.0:  Port 0: 8086:15d3 (Revision: 6, TB Version: 1, Type: Port (0x1))
>Oct 25 01:16:03 thunderbolt 0000:7c:00.0:   Max hop id (in/out): 7/7
>Oct 25 01:16:03 thunderbolt 0000:7c:00.0:   Max counters: 8
>Oct 25 01:16:03 thunderbolt 0000:7c:00.0:   NFC Credits: 0x800000
>Oct 25 01:16:03 thunderbolt 0000:7c:00.0:  Port 1: 8086:15d3 (Revision: 6, TB Version: 1, Type: Port (0x1))
>Oct 25 01:16:03 thunderbolt 0000:7c:00.0:   Max hop id (in/out): 15/15
>Oct 25 01:16:03 thunderbolt 0000:7c:00.0:   Max counters: 16
>Oct 25 01:16:03 thunderbolt 0000:7c:00.0:   NFC Credits: 0x3c00000
>Oct 25 01:16:03 thunderbolt 0000:7c:00.0:  Port 2: 8086:15d3 (Revision: 6, TB Version: 1, Type: Port (0x1))
>Oct 25 01:16:03 thunderbolt 0000:7c:00.0:   Max hop id (in/out): 15/15
>Oct 25 01:16:03 thunderbolt 0000:7c:00.0:   Max counters: 16
>Oct 25 01:16:03 thunderbolt 0000:7c:00.0:   NFC Credits: 0x3c00000
>Oct 25 01:16:03 thunderbolt 0000:7c:00.0:  Port 3: 8086:15d3 (Revision: 6, TB Version: 1, Type: Port (0x1))
>Oct 25 01:16:03 thunderbolt 0000:7c:00.0:   Max hop id (in/out): 15/15
>Oct 25 01:16:03 thunderbolt 0000:7c:00.0:   Max counters: 16
>Oct 25 01:16:03 thunderbolt 0000:7c:00.0:   NFC Credits: 0x3c00000
>Oct 25 01:16:03 thunderbolt 0000:7c:00.0:  Port 4: 8086:15d3 (Revision: 6, TB Version: 1, Type: Port (0x1))
>Oct 25 01:16:03 thunderbolt 0000:7c:00.0:   Max hop id (in/out): 15/15
>Oct 25 01:16:03 thunderbolt 0000:7c:00.0:   Max counters: 16
>Oct 25 01:16:03 thunderbolt 0000:7c:00.0:   NFC Credits: 0x3c00000
>Oct 25 01:16:03 thunderbolt 0000:7c:00.0:  Port 5: 8086:15d3 (Revision: 6, TB Version: 1, Type: NHI (0x2))
>Oct 25 01:16:03 thunderbolt 0000:7c:00.0:   Max hop id (in/out): 11/11
>Oct 25 01:16:03 thunderbolt 0000:7c:00.0:   Max counters: 16
>Oct 25 01:16:03 thunderbolt 0000:7c:00.0:   NFC Credits: 0x1000000
>Oct 25 01:16:03 thunderbolt 0000:7c:00.0:  Port 6: 8086:15d3 (Revision: 6, TB Version: 1, Type: PCIe (0x100101))
>Oct 25 01:16:03 thunderbolt 0000:7c:00.0:   Max hop id (in/out): 8/8
>Oct 25 01:16:03 thunderbolt 0000:7c:00.0:   Max counters: 2
>Oct 25 01:16:03 thunderbolt 0000:7c:00.0:   NFC Credits: 0x800000
>Oct 25 01:16:03 thunderbolt 0000:7c:00.0:  Port 7: 8086:15d3 (Revision: 6, TB Version: 1, Type: PCIe (0x100101))
>Oct 25 01:16:03 thunderbolt 0000:7c:00.0:   Max hop id (in/out): 8/8
>Oct 25 01:16:03 thunderbolt 0000:7c:00.0:   Max counters: 2
>Oct 25 01:16:03 thunderbolt 0000:7c:00.0:   NFC Credits: 0x800000
>Oct 25 01:16:03 thunderbolt 0000:7c:00.0: 0:8: disabled by eeprom
>Oct 25 01:16:03 thunderbolt 0000:7c:00.0:  Port 9: 8086:15d3 (Revision: 6, TB Version: 1, Type: DP/HDMI (0xe0101))
>Oct 25 01:16:03 thunderbolt 0000:7c:00.0:   Max hop id (in/out): 9/9
>Oct 25 01:16:03 thunderbolt 0000:7c:00.0:   Max counters: 2
>Oct 25 01:16:03 thunderbolt 0000:7c:00.0:   NFC Credits: 0x1000000
>Oct 25 01:16:03 thunderbolt 0000:7c:00.0:  Port 10: 8086:15d3 (Revision: 6, TB Version: 1, Type: DP/HDMI (0xe0101))
>Oct 25 01:16:03 thunderbolt 0000:7c:00.0:   Max hop id (in/out): 9/9
>Oct 25 01:16:03 thunderbolt 0000:7c:00.0:   Max counters: 2
>Oct 25 01:16:03 thunderbolt 0000:7c:00.0:   NFC Credits: 0x1000000
>Oct 25 01:16:03 thunderbolt 0000:7c:00.0: 0:b: disabled by eeprom
>Oct 25 01:16:03 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:03 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:03 kauditd_printk_skb: 49 callbacks suppressed
>Oct 25 01:16:03 audit: type=1130 audit(1540455363.857:72): pid=1 uid=0 auid=4294967295 ses=4294967295 subj=system_u:system_r:init_t:s0 msg='unit=dmraid-activation comm="systemd" exe="/usr/lib/systemd/systemd" hostname=? addr=? terminal=? res=success'
>Oct 25 01:16:03 audit: type=1131 audit(1540455363.857:73): pid=1 uid=0 auid=4294967295 ses=4294967295 subj=system_u:system_r:init_t:s0 msg='unit=dmraid-activation comm="systemd" exe="/usr/lib/systemd/systemd" hostname=? addr=? terminal=? res=success'
>Oct 25 01:16:03 audit: type=1130 audit(1540455363.866:74): pid=1 uid=0 auid=4294967295 ses=4294967295 subj=system_u:system_r:init_t:s0 msg='unit=lvm2-monitor comm="systemd" exe="/usr/lib/systemd/systemd" hostname=? addr=? terminal=? res=success'
>Oct 25 01:16:03 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:03 audit: type=1130 audit(1540455363.900:75): pid=1 uid=0 auid=4294967295 ses=4294967295 subj=system_u:system_r:init_t:s0 msg='unit=systemd-fsck@dev-disk-by\x2duuid-c6f4265d\x2dc566\x2d3c5b\x2d9a93\x2dde411b952fac comm="systemd" exe="/usr/lib/systemd/systemd" hostname=? addr=? terminal=? res=success'
>Oct 25 01:16:03 audit: type=1130 audit(1540455363.902:76): pid=1 uid=0 auid=4294967295 ses=4294967295 subj=system_u:system_r:init_t:s0 msg='unit=systemd-fsck@dev-disk-by\x2duuid-3823c2c8\x2dd2d3\x2d4174\x2dab59\x2d6bf2019bf2d1 comm="systemd" exe="/usr/lib/systemd/systemd" hostname=? addr=? terminal=? res=success'
>Oct 25 01:16:03 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:03 EXT4-fs (nvme0n1p4): mounted filesystem with ordered data mode. Opts: (null)
>Oct 25 01:16:03 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:03 audit: type=1130 audit(1540455363.987:77): pid=1 uid=0 auid=4294967295 ses=4294967295 subj=system_u:system_r:init_t:s0 msg='unit=dracut-shutdown comm="systemd" exe="/usr/lib/systemd/systemd" hostname=? addr=? terminal=? res=success'
>Oct 25 01:16:03 audit: type=1130 audit(1540455363.992:78): pid=1 uid=0 auid=4294967295 ses=4294967295 subj=system_u:system_r:init_t:s0 msg='unit=nfs-config comm="systemd" exe="/usr/lib/systemd/systemd" hostname=? addr=? terminal=? res=success'
>Oct 25 01:16:03 audit: type=1131 audit(1540455363.992:79): pid=1 uid=0 auid=4294967295 ses=4294967295 subj=system_u:system_r:init_t:s0 msg='unit=nfs-config comm="systemd" exe="/usr/lib/systemd/systemd" hostname=? addr=? terminal=? res=success'
>Oct 25 01:16:03 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:03 audit: type=1130 audit(1540455363.996:80): pid=1 uid=0 auid=4294967295 ses=4294967295 subj=system_u:system_r:init_t:s0 msg='unit=plymouth-read-write comm="systemd" exe="/usr/lib/systemd/systemd" hostname=? addr=? terminal=? res=success'
>Oct 25 01:16:03 audit: type=1131 audit(1540455363.996:81): pid=1 uid=0 auid=4294967295 ses=4294967295 subj=system_u:system_r:init_t:s0 msg='unit=plymouth-read-write comm="systemd" exe="/usr/lib/systemd/systemd" hostname=? addr=? terminal=? res=success'
>Oct 25 01:16:04 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:04 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:04 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:04 RPC: Registered named UNIX socket transport module.
>Oct 25 01:16:04 RPC: Registered udp transport module.
>Oct 25 01:16:04 RPC: Registered tcp transport module.
>Oct 25 01:16:04 RPC: Registered tcp NFSv4.1 backchannel transport module.
>Oct 25 01:16:04 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:04 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:04 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:04 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:04 Bluetooth: BNEP (Ethernet Emulation) ver 1.3
>Oct 25 01:16:04 Bluetooth: BNEP filters: protocol multicast
>Oct 25 01:16:04 Bluetooth: BNEP socket layer initialized
>Oct 25 01:16:04 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:04 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:04 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:04 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:04 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:04 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:04 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:04 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:04 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:04 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:04 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:04 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:04 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:04 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:04 IPv6: ADDRCONF(NETDEV_UP): wlp0s20f0u5: link is not ready
>Oct 25 01:16:04 
>Oct 25 01:16:04 ============================================
>Oct 25 01:16:04 WARNING: possible recursive locking detected
>Oct 25 01:16:04 4.19.0-rc8-drm #14 Tainted: G        W  OE    
>Oct 25 01:16:04 --------------------------------------------
>Oct 25 01:16:04 NetworkManager/1011 is trying to acquire lock:
>Oct 25 01:16:04 0000000001f88b72 (pmutex){+.+.}, at: usbctrl_vendorreq+0x9b/0x296 [8812au]
>Oct 25 01:16:04 
>                but task is already holding lock:
>Oct 25 01:16:04 00000000d3fd8ba9 (pmutex){+.+.}, at: netdev_open+0x34/0x53 [8812au]
>Oct 25 01:16:04 
>                other info that might help us debug this:
>Oct 25 01:16:04  Possible unsafe locking scenario:
>Oct 25 01:16:04        CPU0
>Oct 25 01:16:04        ----
>Oct 25 01:16:04   lock(pmutex);
>Oct 25 01:16:04   lock(pmutex);
>Oct 25 01:16:04 
>                 *** DEADLOCK ***
>Oct 25 01:16:04  May be due to missing lock nesting notation
>Oct 25 01:16:04 2 locks held by NetworkManager/1011:
>Oct 25 01:16:04  #0: 00000000ea83cca8 (rtnl_mutex){+.+.}, at: rtnetlink_rcv_msg+0x158/0x4b0
>Oct 25 01:16:04  #1: 00000000d3fd8ba9 (pmutex){+.+.}, at: netdev_open+0x34/0x53 [8812au]
>Oct 25 01:16:04 
>                stack backtrace:
>Oct 25 01:16:04 CPU: 4 PID: 1011 Comm: NetworkManager Tainted: G        W  OE     4.19.0-rc8-drm #14
>Oct 25 01:16:04 Hardware name: Apple Inc. MacBookPro13,3/Mac-A5C67F76ED83108C, BIOS MBP133.88Z.0247.B00.1806261159 06/26/2018
>Oct 25 01:16:04 Call Trace:
>Oct 25 01:16:04  dump_stack+0x85/0xc0
>Oct 25 01:16:04  __lock_acquire.cold.62+0x158/0x227
>Oct 25 01:16:04  ? is_bpf_text_address+0x86/0xf0
>Oct 25 01:16:04  ? kernel_text_address+0xe5/0xf0
>Oct 25 01:16:04  ? __kernel_text_address+0xe/0x30
>Oct 25 01:16:04  ? unwind_get_return_address+0x1b/0x30
>Oct 25 01:16:04  ? __save_stack_trace+0x92/0x100
>Oct 25 01:16:04  lock_acquire+0x9e/0x180
>Oct 25 01:16:04  ? usbctrl_vendorreq+0x9b/0x296 [8812au]
>Oct 25 01:16:04  ? usbctrl_vendorreq+0x9b/0x296 [8812au]
>Oct 25 01:16:04  __mutex_lock+0x88/0x9c0
>Oct 25 01:16:04  ? usbctrl_vendorreq+0x9b/0x296 [8812au]
>Oct 25 01:16:04  ? usbctrl_vendorreq+0x9b/0x296 [8812au]
>Oct 25 01:16:04  ? netdev_open+0x34/0x53 [8812au]
>Oct 25 01:16:04  usbctrl_vendorreq+0x9b/0x296 [8812au]
>Oct 25 01:16:04  usb_read8+0x3e/0x5d [8812au]
>Oct 25 01:16:04  _rtw_read8+0x1b/0x1c [8812au]
>Oct 25 01:16:04  rtl8812au_hal_init+0x78/0x10eb [8812au]
>Oct 25 01:16:04  rtw_hal_init+0x25/0x96 [8812au]
>Oct 25 01:16:04  _netdev_open+0x54/0x200 [8812au]
>Oct 25 01:16:04  netdev_open+0x3c/0x53 [8812au]
>Oct 25 01:16:04  __dev_open+0xce/0x160
>Oct 25 01:16:04  __dev_change_flags+0x1a3/0x210
>Oct 25 01:16:04  ? rcu_read_unlock+0x12/0x60
>Oct 25 01:16:04  dev_change_flags+0x21/0x60
>Oct 25 01:16:04  do_setlink+0x30b/0xf00
>Oct 25 01:16:04  ? nla_parse+0xb5/0xe0
>Oct 25 01:16:04  ? native_sched_clock+0x3e/0xa0
>Oct 25 01:16:04  ? validate_linkmsg+0x19d/0x350
>Oct 25 01:16:04  ? native_sched_clock+0x3e/0xa0
>Oct 25 01:16:04  rtnl_newlink+0x504/0x810
>Oct 25 01:16:04  ? __lock_acquire+0x29a/0x16c0
>Oct 25 01:16:04  ? mark_held_locks+0x57/0x80
>Oct 25 01:16:04  ? __lock_acquire+0x29a/0x16c0
>Oct 25 01:16:04  ? __snmp6_fill_stats64.isra.58+0x6b/0x110
>Oct 25 01:16:04  ? native_sched_clock+0x3e/0xa0
>Oct 25 01:16:04  ? native_sched_clock+0x3e/0xa0
>Oct 25 01:16:04  ? native_sched_clock+0x3e/0xa0
>Oct 25 01:16:04  ? native_sched_clock+0x3e/0xa0
>Oct 25 01:16:04  ? __lock_acquire+0x29a/0x16c0
>Oct 25 01:16:04  ? native_sched_clock+0x3e/0xa0
>Oct 25 01:16:04  ? __lock_acquire+0x29a/0x16c0
>Oct 25 01:16:04  ? __lock_acquire+0x29a/0x16c0
>Oct 25 01:16:04  ? native_sched_clock+0x3e/0xa0
>Oct 25 01:16:04  ? native_sched_clock+0x3e/0xa0
>Oct 25 01:16:04  ? __lock_acquire+0x29a/0x16c0
>Oct 25 01:16:04  ? __lock_acquire+0x29a/0x16c0
>Oct 25 01:16:04  ? native_sched_clock+0x3e/0xa0
>Oct 25 01:16:04  ? __lock_acquire+0x29a/0x16c0
>Oct 25 01:16:04  ? find_held_lock+0x60/0xa0
>Oct 25 01:16:04  rtnetlink_rcv_msg+0x184/0x4b0
>Oct 25 01:16:04  ? netlink_deliver_tap+0x99/0x410
>Oct 25 01:16:04  ? native_sched_clock+0x3e/0xa0
>Oct 25 01:16:04  ? rtnetlink_put_metrics+0x1b0/0x1b0
>Oct 25 01:16:04  netlink_rcv_skb+0x4c/0x120
>Oct 25 01:16:04  netlink_unicast+0x196/0x230
>Oct 25 01:16:04  netlink_sendmsg+0x218/0x3e0
>Oct 25 01:16:04  sock_sendmsg+0x36/0x40
>Oct 25 01:16:04  ___sys_sendmsg+0x298/0x2f0
>Oct 25 01:16:04  ? __lock_acquire+0x29a/0x16c0
>Oct 25 01:16:04  ? native_sched_clock+0x3e/0xa0
>Oct 25 01:16:04  ? __fget+0xee/0x1f0
>Oct 25 01:16:04  ? __fget+0x10d/0x1f0
>Oct 25 01:16:04  __sys_sendmsg+0x57/0xa0
>Oct 25 01:16:04  do_syscall_64+0x60/0x1f0
>Oct 25 01:16:04  entry_SYSCALL_64_after_hwframe+0x49/0xbe
>Oct 25 01:16:04 RIP: 0033:0x7ff23b04cce7
>Oct 25 01:16:04 Code: 44 00 00 41 54 41 89 d4 55 48 89 f5 53 89 fb 48 83 ec 10 e8 0b ea ff ff 44 89 e2 48 89 ee 89 df 41 89 c0 b8 2e 00 00 00 0f 05 <48> 3d 00 f0 ff ff 77 35 44 89 c7 48 89 44 24 08 e8 44 ea ff ff 48
>Oct 25 01:16:04 RSP: 002b:00007ffddf5225c0 EFLAGS: 00000293 ORIG_RAX: 000000000000002e
>Oct 25 01:16:04 RAX: ffffffffffffffda RBX: 0000000000000007 RCX: 00007ff23b04cce7
>Oct 25 01:16:04 RDX: 0000000000000000 RSI: 00007ffddf522620 RDI: 0000000000000007
>Oct 25 01:16:04 RBP: 00007ffddf522620 R08: 0000000000000000 R09: 0000000000000008
>Oct 25 01:16:04 R10: 000055d8f10b7010 R11: 0000000000000293 R12: 0000000000000000
>Oct 25 01:16:04 R13: 00007ffddf522620 R14: 00007ffddf5227b4 R15: 0000000000000000
>Oct 25 01:16:04 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:04 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:04 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:04 vboxdrv: Found 8 processor cores
>Oct 25 01:16:04 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:04 vboxdrv: TSC mode is Invariant, tentative frequency 2904009903 Hz
>Oct 25 01:16:04 vboxdrv: Successfully loaded version 5.2.18 (interface 0x00290001)
>Oct 25 01:16:04 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:04 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:04 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:04 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:04 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:04 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:05 VBoxNetFlt: Successfully started.
>Oct 25 01:16:05 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:05 VBoxNetAdp: Successfully started.
>Oct 25 01:16:05 VBoxPciLinuxInit
>Oct 25 01:16:05 vboxpci: IOMMU found
>Oct 25 01:16:05 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:05 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:05 IPv6: ADDRCONF(NETDEV_UP): wlp0s20f0u5: link is not ready
>Oct 25 01:16:05 IPv6: ADDRCONF(NETDEV_UP): wlp0s20f0u5: link is not ready
>Oct 25 01:16:05 IPv6: ADDRCONF(NETDEV_UP): wlp3s0: link is not ready
>Oct 25 01:16:05 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:05 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:05 IPv6: ADDRCONF(NETDEV_UP): wlp3s0: link is not ready
>Oct 25 01:16:05 IPv6: ADDRCONF(NETDEV_UP): wlp3s0: link is not ready
>Oct 25 01:16:05 bridge: filtering via arp/ip/ip6tables is no longer available by default. Update your scripts to load br_netfilter if you need this.
>Oct 25 01:16:05 tun: Universal TUN/TAP device driver, 1.6
>Oct 25 01:16:05 virbr0: port 1(virbr0-nic) entered blocking state
>Oct 25 01:16:05 virbr0: port 1(virbr0-nic) entered disabled state
>Oct 25 01:16:05 device virbr0-nic entered promiscuous mode
>Oct 25 01:16:05 IPv6: ADDRCONF(NETDEV_UP): wlp3s0: link is not ready
>Oct 25 01:16:05 IPv6: ADDRCONF(NETDEV_UP): wlp0s20f0u5: link is not ready
>Oct 25 01:16:05 virbr0: port 1(virbr0-nic) entered blocking state
>Oct 25 01:16:05 virbr0: port 1(virbr0-nic) entered listening state
>Oct 25 01:16:05 [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:83:eDP-1]
>Oct 25 01:16:05 [drm:intel_dp_detect [i915]] [CONNECTOR:83:eDP-1]
>Oct 25 01:16:05 [drm:intel_power_well_enable [i915]] enabling DC off
>Oct 25 01:16:05 [drm:gen9_set_dc_state [i915]] Setting DC state from 02 to 00
>Oct 25 01:16:05 [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>Oct 25 01:16:05 [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>Oct 25 01:16:05 [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>Oct 25 01:16:05 [drm:edp_panel_vdd_on [i915]] Turning eDP port A VDD on
>Oct 25 01:16:05 [drm:edp_panel_vdd_on [i915]] PP_STATUS: 0x80000008 PP_CONTROL: 0x0000000f
>Oct 25 01:16:05 [drm:drm_dp_read_desc [drm_kms_helper]] DP sink: OUI 00-10-fa dev-ID eD\025eaa HW-rev 1.0 SW-rev 2.15 quirks 0x0000
>Oct 25 01:16:05 [drm:intel_dp_detect [i915]] MST support? port A: no, sink: no, modparam: yes
>Oct 25 01:16:05 [drm:drm_add_display_info [drm]] non_desktop set to 0
>Oct 25 01:16:05 [drm:drm_add_edid_modes [drm]] ELD: no CEA Extension found
>Oct 25 01:16:05 [drm:drm_add_display_info [drm]] non_desktop set to 0
>Oct 25 01:16:05 [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:83:eDP-1] probed modes :
>Oct 25 01:16:05 [drm:drm_mode_debug_printmodeline [drm]] Modeline 84:"2880x1800" 60 328920 2880 2888 2920 2960 1800 1838 1846 1852 0x48 0x9
>Oct 25 01:16:05 [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:90:DP-1]
>Oct 25 01:16:05 [drm:intel_dp_detect [i915]] [CONNECTOR:90:DP-1]
>Oct 25 01:16:05 [drm:intel_power_well_enable [i915]] enabling power well 2
>Oct 25 01:16:05 [drm:intel_power_well_disable [i915]] disabling power well 2
>Oct 25 01:16:05 [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:90:DP-1] disconnected
>Oct 25 01:16:05 [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:96:HDMI-A-1]
>Oct 25 01:16:05 [drm:intel_hdmi_detect [i915]] [CONNECTOR:96:HDMI-A-1]
>Oct 25 01:16:05 virbr0: port 1(virbr0-nic) entered disabled state
>Oct 25 01:16:06 [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] timed out, falling back to bit banging on pin 4
>Oct 25 01:16:06 [drm:drm_do_probe_ddc_edid [drm]] drm: skipping non-existent adapter i915 gmbus dpc
>Oct 25 01:16:06 [drm:intel_hdmi_set_edid [i915]] HDMI GMBUS EDID read failed, retry using GPIO bit-banging
>Oct 25 01:16:06 [drm:intel_gmbus_force_bit [i915]] enabling bit-banging on i915 gmbus dpc. force bit now 1
>Oct 25 01:16:06 [drm:drm_do_probe_ddc_edid [drm]] drm: skipping non-existent adapter i915 gmbus dpc
>Oct 25 01:16:06 [drm:intel_gmbus_force_bit [i915]] disabling bit-banging on i915 gmbus dpc. force bit now 0
>Oct 25 01:16:06 [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] timed out, falling back to bit banging on pin 4
>Oct 25 01:16:06 [drm:drm_dp_dual_mode_detect [drm_kms_helper]] DP dual mode HDMI ID:  (err -6)
>Oct 25 01:16:06 [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:96:HDMI-A-1] disconnected
>Oct 25 01:16:06 [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:101:DP-2]
>Oct 25 01:16:06 [drm:intel_dp_detect [i915]] [CONNECTOR:101:DP-2]
>Oct 25 01:16:06 [drm:intel_power_well_enable [i915]] enabling power well 2
>Oct 25 01:16:06 [drm:intel_power_well_disable [i915]] disabling power well 2
>Oct 25 01:16:06 [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:101:DP-2] disconnected
>Oct 25 01:16:06 [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:106:HDMI-A-2]
>Oct 25 01:16:06 [drm:intel_hdmi_detect [i915]] [CONNECTOR:106:HDMI-A-2]
>Oct 25 01:16:06 [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] timed out, falling back to bit banging on pin 6
>Oct 25 01:16:06 [drm:drm_do_probe_ddc_edid [drm]] drm: skipping non-existent adapter i915 gmbus dpd
>Oct 25 01:16:06 [drm:intel_hdmi_set_edid [i915]] HDMI GMBUS EDID read failed, retry using GPIO bit-banging
>Oct 25 01:16:06 [drm:intel_gmbus_force_bit [i915]] enabling bit-banging on i915 gmbus dpd. force bit now 1
>Oct 25 01:16:06 [drm:drm_do_probe_ddc_edid [drm]] drm: skipping non-existent adapter i915 gmbus dpd
>Oct 25 01:16:06 [drm:intel_gmbus_force_bit [i915]] disabling bit-banging on i915 gmbus dpd. force bit now 0
>Oct 25 01:16:06 [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] timed out, falling back to bit banging on pin 6
>Oct 25 01:16:06 [drm:drm_dp_dual_mode_detect [drm_kms_helper]] DP dual mode HDMI ID:  (err -6)
>Oct 25 01:16:06 [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:106:HDMI-A-2] disconnected
>Oct 25 01:16:06 [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:83:eDP-1]
>Oct 25 01:16:06 [drm:intel_dp_detect [i915]] [CONNECTOR:83:eDP-1]
>Oct 25 01:16:06 [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>Oct 25 01:16:06 [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>Oct 25 01:16:06 [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>Oct 25 01:16:06 [drm:drm_dp_read_desc [drm_kms_helper]] DP sink: OUI 00-10-fa dev-ID eD\025eaa HW-rev 1.0 SW-rev 2.15 quirks 0x0000
>Oct 25 01:16:06 [drm:intel_dp_detect [i915]] MST support? port A: no, sink: no, modparam: yes
>Oct 25 01:16:06 [drm:drm_add_display_info [drm]] non_desktop set to 0
>Oct 25 01:16:06 [drm:drm_add_edid_modes [drm]] ELD: no CEA Extension found
>Oct 25 01:16:06 [drm:drm_add_display_info [drm]] non_desktop set to 0
>Oct 25 01:16:06 [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:83:eDP-1] probed modes :
>Oct 25 01:16:06 [drm:drm_mode_debug_printmodeline [drm]] Modeline 84:"2880x1800" 60 328920 2880 2888 2920 2960 1800 1838 1846 1852 0x48 0x9
>Oct 25 01:16:06 [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:90:DP-1]
>Oct 25 01:16:06 [drm:intel_dp_detect [i915]] [CONNECTOR:90:DP-1]
>Oct 25 01:16:06 [drm:intel_power_well_enable [i915]] enabling power well 2
>Oct 25 01:16:06 [drm:intel_power_well_disable [i915]] disabling power well 2
>Oct 25 01:16:06 [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:90:DP-1] disconnected
>Oct 25 01:16:06 [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:96:HDMI-A-1]
>Oct 25 01:16:06 [drm:intel_hdmi_detect [i915]] [CONNECTOR:96:HDMI-A-1]
>Oct 25 01:16:06 [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] timed out, falling back to bit banging on pin 4
>Oct 25 01:16:06 [drm:drm_do_probe_ddc_edid [drm]] drm: skipping non-existent adapter i915 gmbus dpc
>Oct 25 01:16:06 [drm:intel_hdmi_set_edid [i915]] HDMI GMBUS EDID read failed, retry using GPIO bit-banging
>Oct 25 01:16:06 [drm:intel_gmbus_force_bit [i915]] enabling bit-banging on i915 gmbus dpc. force bit now 1
>Oct 25 01:16:06 [drm:drm_do_probe_ddc_edid [drm]] drm: skipping non-existent adapter i915 gmbus dpc
>Oct 25 01:16:06 [drm:intel_gmbus_force_bit [i915]] disabling bit-banging on i915 gmbus dpc. force bit now 0
>Oct 25 01:16:06 [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] timed out, falling back to bit banging on pin 4
>Oct 25 01:16:06 [drm:drm_dp_dual_mode_detect [drm_kms_helper]] DP dual mode HDMI ID:  (err -6)
>Oct 25 01:16:06 [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:96:HDMI-A-1] disconnected
>Oct 25 01:16:06 [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:101:DP-2]
>Oct 25 01:16:06 [drm:intel_dp_detect [i915]] [CONNECTOR:101:DP-2]
>Oct 25 01:16:06 [drm:intel_power_well_enable [i915]] enabling power well 2
>Oct 25 01:16:06 [drm:intel_power_well_disable [i915]] disabling power well 2
>Oct 25 01:16:06 [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:101:DP-2] disconnected
>Oct 25 01:16:06 [drm:intel_backlight_device_get_brightness [i915]] get backlight PWM = 1388
>Oct 25 01:16:06 [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:106:HDMI-A-2]
>Oct 25 01:16:06 [drm:intel_hdmi_detect [i915]] [CONNECTOR:106:HDMI-A-2]
>Oct 25 01:16:06 [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] timed out, falling back to bit banging on pin 6
>Oct 25 01:16:06 [drm:drm_do_probe_ddc_edid [drm]] drm: skipping non-existent adapter i915 gmbus dpd
>Oct 25 01:16:06 [drm:intel_hdmi_set_edid [i915]] HDMI GMBUS EDID read failed, retry using GPIO bit-banging
>Oct 25 01:16:06 [drm:intel_gmbus_force_bit [i915]] enabling bit-banging on i915 gmbus dpd. force bit now 1
>Oct 25 01:16:06 [drm:drm_do_probe_ddc_edid [drm]] drm: skipping non-existent adapter i915 gmbus dpd
>Oct 25 01:16:06 [drm:intel_gmbus_force_bit [i915]] disabling bit-banging on i915 gmbus dpd. force bit now 0
>Oct 25 01:16:06 [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] timed out, falling back to bit banging on pin 6
>Oct 25 01:16:06 [drm:drm_dp_dual_mode_detect [drm_kms_helper]] DP dual mode HDMI ID:  (err -6)
>Oct 25 01:16:06 [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:106:HDMI-A-2] disconnected
>Oct 25 01:16:06 [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000001e2967c2
>Oct 25 01:16:06 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 000000002ae74130 state to 000000001e2967c2
>Oct 25 01:16:06 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000001e2967c2
>Oct 25 01:16:06 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 000000002ae74130 state to 000000001e2967c2
>Oct 25 01:16:06 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000314d4a5f state to 000000001e2967c2
>Oct 25 01:16:06 [drm:drm_atomic_check_only [drm]] checking 000000001e2967c2
>Oct 25 01:16:06 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 111
>Oct 25 01:16:06 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:06 [drm:drm_atomic_commit [drm]] committing 000000001e2967c2
>Oct 25 01:16:06 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:06 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:06 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000001e2967c2
>Oct 25 01:16:06 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000001e2967c2
>Oct 25 01:16:06 [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000001e2967c2
>Oct 25 01:16:06 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:42:cursor A] 00000000cf54532a state to 000000001e2967c2
>Oct 25 01:16:06 [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:42:cursor A] state 00000000cf54532a
>Oct 25 01:16:06 [drm:drm_atomic_check_only [drm]] checking 000000001e2967c2
>Oct 25 01:16:06 [drm:drm_atomic_commit [drm]] committing 000000001e2967c2
>Oct 25 01:16:06 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000001e2967c2
>Oct 25 01:16:06 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000001e2967c2
>Oct 25 01:16:06 [drm:gen8_de_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x11101010, pins 0x00000010, long 0x00000000
>Oct 25 01:16:06 [drm:intel_hpd_irq_handler [i915]] digital hpd port A - short
>Oct 25 01:16:06 [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port A - short
>Oct 25 01:16:06 [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 41 00 00 01 80 02 00 00 00 0f 0b 00
>Oct 25 01:16:07 [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000088004fa5
>Oct 25 01:16:07 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:42:cursor A] 0000000066b1c3dd state to 0000000088004fa5
>Oct 25 01:16:07 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000a4ae3b4d state to 0000000088004fa5
>Oct 25 01:16:07 [drm:drm_atomic_set_crtc_for_plane [drm]] Link [PLANE:42:cursor A] state 0000000066b1c3dd to [CRTC:45:pipe A]
>Oct 25 01:16:07 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:42:cursor A] state 0000000066b1c3dd
>Oct 25 01:16:07 [drm:drm_atomic_check_only [drm]] checking 0000000088004fa5
>Oct 25 01:16:07 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 110
>Oct 25 01:16:07 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 0 -> 1, off 0, on 1, ms 0
>Oct 25 01:16:07 [drm:drm_atomic_commit [drm]] committing 0000000088004fa5
>Oct 25 01:16:07 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:07 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000088004fa5
>Oct 25 01:16:07 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000088004fa5
>Oct 25 01:16:07 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:42:cursor A] state 000000009a037ad9
>Oct 25 01:16:07 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 110
>Oct 25 01:16:07 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:07 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:07 [drm:gen8_de_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x11101010, pins 0x00000010, long 0x00000000
>Oct 25 01:16:07 [drm:intel_hpd_irq_handler [i915]] digital hpd port A - short
>Oct 25 01:16:07 [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port A - short
>Oct 25 01:16:07 [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 41 00 00 01 80 02 00 00 00 0f 0b 00
>Oct 25 01:16:07 [drm:intel_backlight_device_get_brightness [i915]] get backlight PWM = 1388
>Oct 25 01:16:08 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:42:cursor A] state 000000000794640b
>Oct 25 01:16:08 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 110
>Oct 25 01:16:08 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:08 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:08 [drm:drm_mode_addfb2 [drm]] [FB:113]
>Oct 25 01:16:08 [drm:drm_mode_setcrtc [drm]] [CRTC:45:pipe A]
>Oct 25 01:16:08 [drm:drm_mode_setcrtc [drm]] [CONNECTOR:83:eDP-1]
>Oct 25 01:16:08 [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000003b3393c9
>Oct 25 01:16:08 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 000000001f0d0149 state to 000000003b3393c9
>Oct 25 01:16:08 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000aa094b5a state to 000000003b3393c9
>Oct 25 01:16:08 [drm:drm_atomic_set_mode_for_crtc [drm]] Set [MODE:2880x1800] for [CRTC:45:pipe A] state 000000001f0d0149
>Oct 25 01:16:08 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:113] for [PLANE:28:plane 1A] state 00000000aa094b5a
>Oct 25 01:16:08 [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:45:pipe A] to 000000003b3393c9
>Oct 25 01:16:08 [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:83:eDP-1] 000000003ef6d7c0 state to 000000003b3393c9
>Oct 25 01:16:08 [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:83:eDP-1] state 000000003ef6d7c0 to [NOCRTC]
>Oct 25 01:16:08 [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:83:eDP-1] state 000000003ef6d7c0 to [CRTC:45:pipe A]
>Oct 25 01:16:08 [drm:drm_atomic_check_only [drm]] checking 000000003b3393c9
>Oct 25 01:16:08 [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:83:eDP-1]
>Oct 25 01:16:08 [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:83:eDP-1] keeps [ENCODER:82:DDI A], now on [CRTC:45:pipe A]
>Oct 25 01:16:08 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 113
>Oct 25 01:16:08 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:08 [drm:drm_atomic_commit [drm]] committing 000000003b3393c9
>Oct 25 01:16:08 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:08 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000003b3393c9
>Oct 25 01:16:08 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000003b3393c9
>Oct 25 01:16:08 [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000003b3393c9
>Oct 25 01:16:08 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 000000001ab56d54 state to 000000003b3393c9
>Oct 25 01:16:08 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 0000000029fac543 state to 000000003b3393c9
>Oct 25 01:16:08 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:113] for [PLANE:28:plane 1A] state 0000000029fac543
>Oct 25 01:16:08 [drm:drm_atomic_check_only [drm]] checking 000000003b3393c9
>Oct 25 01:16:08 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 113
>Oct 25 01:16:08 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:08 [drm:drm_atomic_nonblocking_commit [drm]] committing 000000003b3393c9 nonblocking
>Oct 25 01:16:08 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:08 [drm:drm_mode_setcrtc [drm]] [CRTC:63:pipe B]
>Oct 25 01:16:08 [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000002fe59080
>Oct 25 01:16:08 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:63:pipe B] 00000000624e831c state to 000000002fe59080
>Oct 25 01:16:08 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:46:plane 1B] 000000007dac08fd state to 000000002fe59080
>Oct 25 01:16:08 [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:63:pipe B] state 00000000624e831c
>Oct 25 01:16:08 [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:46:plane 1B] state 000000007dac08fd
>Oct 25 01:16:08 [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:63:pipe B] to 000000002fe59080
>Oct 25 01:16:08 [drm:drm_atomic_check_only [drm]] checking 000000002fe59080
>Oct 25 01:16:08 [drm:drm_atomic_commit [drm]] committing 000000002fe59080
>Oct 25 01:16:08 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000002fe59080
>Oct 25 01:16:08 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000002fe59080
>Oct 25 01:16:08 [drm:drm_mode_setcrtc [drm]] [CRTC:81:pipe C]
>Oct 25 01:16:08 [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000002fe59080
>Oct 25 01:16:08 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:81:pipe C] 00000000ff8ba4cf state to 000000002fe59080
>Oct 25 01:16:08 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:64:plane 1C] 00000000ba3689da state to 000000002fe59080
>Oct 25 01:16:08 [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:81:pipe C] state 00000000ff8ba4cf
>Oct 25 01:16:08 [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:64:plane 1C] state 00000000ba3689da
>Oct 25 01:16:08 [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:81:pipe C] to 000000002fe59080
>Oct 25 01:16:08 [drm:drm_atomic_check_only [drm]] checking 000000002fe59080
>Oct 25 01:16:08 [drm:drm_atomic_commit [drm]] committing 000000002fe59080
>Oct 25 01:16:08 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000002fe59080
>Oct 25 01:16:08 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000002fe59080
>Oct 25 01:16:08 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:08 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000003b3393c9
>Oct 25 01:16:08 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000003b3393c9
>Oct 25 01:16:08 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:42:cursor A] state 0000000011e9cff2
>Oct 25 01:16:08 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 110
>Oct 25 01:16:08 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:08 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:08 [drm:drm_mode_addfb2 [drm]] [FB:112]
>Oct 25 01:16:08 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000e1ec5aa4
>Oct 25 01:16:08 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 0000000048d26ec9 state to 00000000e1ec5aa4
>Oct 25 01:16:08 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000d2c9109c state to 00000000e1ec5aa4
>Oct 25 01:16:08 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:112] for [PLANE:28:plane 1A] state 00000000d2c9109c
>Oct 25 01:16:08 [drm:drm_atomic_check_only [drm]] checking 00000000e1ec5aa4
>Oct 25 01:16:08 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 112
>Oct 25 01:16:08 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:08 [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000e1ec5aa4 nonblocking
>Oct 25 01:16:08 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:08 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000e1ec5aa4
>Oct 25 01:16:08 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000e1ec5aa4
>Oct 25 01:16:08 [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000002fe59080
>Oct 25 01:16:08 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 000000003b3393c9 state to 000000002fe59080
>Oct 25 01:16:08 [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:45:pipe A] to 000000002fe59080
>Oct 25 01:16:08 [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:83:eDP-1] 0000000099fbc9d3 state to 000000002fe59080
>Oct 25 01:16:08 [drm:drm_atomic_check_only [drm]] checking 000000002fe59080
>Oct 25 01:16:08 [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:83:eDP-1]
>Oct 25 01:16:08 [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:83:eDP-1] keeps [ENCODER:82:DDI A], now on [CRTC:45:pipe A]
>Oct 25 01:16:08 [drm:drm_atomic_commit [drm]] committing 000000002fe59080
>Oct 25 01:16:08 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000002fe59080
>Oct 25 01:16:08 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000002fe59080
>Oct 25 01:16:08 [drm:drm_mode_addfb2 [drm]] [FB:113]
>Oct 25 01:16:08 [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000002fe59080
>Oct 25 01:16:08 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 000000001f0d0149 state to 000000002fe59080
>Oct 25 01:16:08 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000aa094b5a state to 000000002fe59080
>Oct 25 01:16:08 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:113] for [PLANE:28:plane 1A] state 00000000aa094b5a
>Oct 25 01:16:08 [drm:drm_atomic_check_only [drm]] checking 000000002fe59080
>Oct 25 01:16:08 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 113
>Oct 25 01:16:08 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:08 [drm:drm_atomic_nonblocking_commit [drm]] committing 000000002fe59080 nonblocking
>Oct 25 01:16:08 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:08 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000002fe59080
>Oct 25 01:16:08 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000002fe59080
>Oct 25 01:16:08 [drm:drm_mode_addfb2 [drm]] [FB:112]
>Oct 25 01:16:08 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000a23f8f5f
>Oct 25 01:16:08 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 000000001eccf585 state to 00000000a23f8f5f
>Oct 25 01:16:08 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 000000004c4f76a6 state to 00000000a23f8f5f
>Oct 25 01:16:08 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:112] for [PLANE:28:plane 1A] state 000000004c4f76a6
>Oct 25 01:16:08 [drm:drm_atomic_check_only [drm]] checking 00000000a23f8f5f
>Oct 25 01:16:08 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 112
>Oct 25 01:16:08 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:08 [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000a23f8f5f nonblocking
>Oct 25 01:16:08 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:08 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000a23f8f5f
>Oct 25 01:16:08 [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000007b2f9efe
>Oct 25 01:16:08 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000a23f8f5f
>Oct 25 01:16:08 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000007b2f9efe
>Oct 25 01:16:08 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000007b2f9efe
>Oct 25 01:16:08 [drm:drm_mode_addfb2 [drm]] [FB:113]
>Oct 25 01:16:08 [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000007b2f9efe
>Oct 25 01:16:08 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000ffe41dfe state to 000000007b2f9efe
>Oct 25 01:16:08 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000c3bb7f05 state to 000000007b2f9efe
>Oct 25 01:16:08 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:113] for [PLANE:28:plane 1A] state 00000000c3bb7f05
>Oct 25 01:16:08 [drm:drm_atomic_check_only [drm]] checking 000000007b2f9efe
>Oct 25 01:16:08 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 113
>Oct 25 01:16:08 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:08 [drm:drm_atomic_nonblocking_commit [drm]] committing 000000007b2f9efe nonblocking
>Oct 25 01:16:08 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:08 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000007b2f9efe
>Oct 25 01:16:08 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000007b2f9efe
>Oct 25 01:16:08 [drm:drm_mode_addfb2 [drm]] [FB:112]
>Oct 25 01:16:08 [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000004994a620
>Oct 25 01:16:08 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000fac8a01c state to 000000004994a620
>Oct 25 01:16:08 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 0000000035605ff7 state to 000000004994a620
>Oct 25 01:16:08 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:112] for [PLANE:28:plane 1A] state 0000000035605ff7
>Oct 25 01:16:08 [drm:drm_atomic_check_only [drm]] checking 000000004994a620
>Oct 25 01:16:08 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 112
>Oct 25 01:16:08 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:08 [drm:drm_atomic_nonblocking_commit [drm]] committing 000000004994a620 nonblocking
>Oct 25 01:16:08 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:08 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000004994a620
>Oct 25 01:16:08 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000004994a620
>Oct 25 01:16:08 [drm:drm_mode_addfb2 [drm]] [FB:113]
>Oct 25 01:16:08 [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000004994a620
>Oct 25 01:16:08 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000e1ec5aa4 state to 000000004994a620
>Oct 25 01:16:08 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000d19fa08b state to 000000004994a620
>Oct 25 01:16:08 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:113] for [PLANE:28:plane 1A] state 00000000d19fa08b
>Oct 25 01:16:08 [drm:drm_atomic_check_only [drm]] checking 000000004994a620
>Oct 25 01:16:08 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 113
>Oct 25 01:16:08 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:08 [drm:drm_atomic_nonblocking_commit [drm]] committing 000000004994a620 nonblocking
>Oct 25 01:16:08 [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000035417744
>Oct 25 01:16:08 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000f8616964 state to 0000000035417744
>Oct 25 01:16:08 [drm:drm_atomic_check_only [drm]] checking 0000000035417744
>Oct 25 01:16:08 [drm:drm_atomic_commit [drm]] committing 0000000035417744
>Oct 25 01:16:08 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:08 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000004994a620
>Oct 25 01:16:08 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000004994a620
>Oct 25 01:16:08 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000035417744
>Oct 25 01:16:08 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000035417744
>Oct 25 01:16:08 [drm:drm_mode_addfb2 [drm]] [FB:112]
>Oct 25 01:16:08 [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000048d26ec9
>Oct 25 01:16:08 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000473c4803 state to 0000000048d26ec9
>Oct 25 01:16:08 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 000000003180b920 state to 0000000048d26ec9
>Oct 25 01:16:08 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:112] for [PLANE:28:plane 1A] state 000000003180b920
>Oct 25 01:16:08 [drm:drm_atomic_check_only [drm]] checking 0000000048d26ec9
>Oct 25 01:16:08 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 112
>Oct 25 01:16:08 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:08 [drm:drm_atomic_nonblocking_commit [drm]] committing 0000000048d26ec9 nonblocking
>Oct 25 01:16:08 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:08 [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000001b7a88b0
>Oct 25 01:16:08 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000048d26ec9
>Oct 25 01:16:08 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000048d26ec9
>Oct 25 01:16:08 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000001b7a88b0
>Oct 25 01:16:08 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000001b7a88b0
>Oct 25 01:16:08 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000001b7a88b0
>Oct 25 01:16:08 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000001b7a88b0
>Oct 25 01:16:08 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000001b7a88b0
>Oct 25 01:16:08 [drm:drm_mode_addfb2 [drm]] [FB:113]
>Oct 25 01:16:08 [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000001b7a88b0
>Oct 25 01:16:08 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000434a56f6 state to 000000001b7a88b0
>Oct 25 01:16:08 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 000000001d7eec09 state to 000000001b7a88b0
>Oct 25 01:16:08 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:113] for [PLANE:28:plane 1A] state 000000001d7eec09
>Oct 25 01:16:08 [drm:drm_atomic_check_only [drm]] checking 000000001b7a88b0
>Oct 25 01:16:08 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 113
>Oct 25 01:16:08 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:08 [drm:drm_atomic_nonblocking_commit [drm]] committing 000000001b7a88b0 nonblocking
>Oct 25 01:16:08 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:08 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000001b7a88b0
>Oct 25 01:16:08 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000772e8fbc
>Oct 25 01:16:08 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000772e8fbc
>Oct 25 01:16:08 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000001b7a88b0
>Oct 25 01:16:08 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000772e8fbc
>Oct 25 01:16:08 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000772e8fbc
>Oct 25 01:16:08 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000772e8fbc
>Oct 25 01:16:08 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000772e8fbc
>Oct 25 01:16:08 [drm:drm_mode_addfb2 [drm]] [FB:112]
>Oct 25 01:16:08 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000772e8fbc
>Oct 25 01:16:08 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000a3a6daf9 state to 00000000772e8fbc
>Oct 25 01:16:08 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 000000004e18d68a state to 00000000772e8fbc
>Oct 25 01:16:08 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:112] for [PLANE:28:plane 1A] state 000000004e18d68a
>Oct 25 01:16:08 [drm:drm_atomic_check_only [drm]] checking 00000000772e8fbc
>Oct 25 01:16:08 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 112
>Oct 25 01:16:08 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:08 [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000772e8fbc nonblocking
>Oct 25 01:16:08 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:08 [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000001b7a88b0
>Oct 25 01:16:08 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000772e8fbc
>Oct 25 01:16:08 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000772e8fbc
>Oct 25 01:16:08 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000001b7a88b0
>Oct 25 01:16:08 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000001b7a88b0
>Oct 25 01:16:08 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000001b7a88b0
>Oct 25 01:16:08 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000001b7a88b0
>Oct 25 01:16:08 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000001b7a88b0
>Oct 25 01:16:08 [drm:drm_mode_addfb2 [drm]] [FB:113]
>Oct 25 01:16:08 [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000001b7a88b0
>Oct 25 01:16:08 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000473c4803 state to 000000001b7a88b0
>Oct 25 01:16:08 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 000000003180b920 state to 000000001b7a88b0
>Oct 25 01:16:08 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:113] for [PLANE:28:plane 1A] state 000000003180b920
>Oct 25 01:16:08 [drm:drm_atomic_check_only [drm]] checking 000000001b7a88b0
>Oct 25 01:16:08 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 113
>Oct 25 01:16:08 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:08 [drm:drm_atomic_nonblocking_commit [drm]] committing 000000001b7a88b0 nonblocking
>Oct 25 01:16:08 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:08 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000001b7a88b0
>Oct 25 01:16:08 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000001b7a88b0
>Oct 25 01:16:08 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000772e8fbc
>Oct 25 01:16:08 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000772e8fbc
>Oct 25 01:16:08 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000772e8fbc
>Oct 25 01:16:08 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000772e8fbc
>Oct 25 01:16:08 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000772e8fbc
>Oct 25 01:16:08 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000772e8fbc
>Oct 25 01:16:08 [drm:drm_mode_addfb2 [drm]] [FB:112]
>Oct 25 01:16:08 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000772e8fbc
>Oct 25 01:16:08 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000434a56f6 state to 00000000772e8fbc
>Oct 25 01:16:08 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 000000001d7eec09 state to 00000000772e8fbc
>Oct 25 01:16:08 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:112] for [PLANE:28:plane 1A] state 000000001d7eec09
>Oct 25 01:16:08 [drm:drm_atomic_check_only [drm]] checking 00000000772e8fbc
>Oct 25 01:16:08 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 112
>Oct 25 01:16:08 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:08 [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000772e8fbc nonblocking
>Oct 25 01:16:08 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:08 [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000001b7a88b0
>Oct 25 01:16:08 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000772e8fbc
>Oct 25 01:16:08 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000772e8fbc
>Oct 25 01:16:08 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000001b7a88b0
>Oct 25 01:16:08 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000001b7a88b0
>Oct 25 01:16:08 [drm:drm_mode_addfb2 [drm]] [FB:113]
>Oct 25 01:16:08 [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000001b7a88b0
>Oct 25 01:16:08 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000a3a6daf9 state to 000000001b7a88b0
>Oct 25 01:16:08 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 000000004e18d68a state to 000000001b7a88b0
>Oct 25 01:16:08 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:113] for [PLANE:28:plane 1A] state 000000004e18d68a
>Oct 25 01:16:08 [drm:drm_atomic_check_only [drm]] checking 000000001b7a88b0
>Oct 25 01:16:08 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 113
>Oct 25 01:16:08 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:08 [drm:drm_atomic_nonblocking_commit [drm]] committing 000000001b7a88b0 nonblocking
>Oct 25 01:16:08 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:08 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000001b7a88b0
>Oct 25 01:16:08 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000001b7a88b0
>Oct 25 01:16:08 [drm:drm_mode_addfb2 [drm]] [FB:112]
>Oct 25 01:16:08 [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000001b7a88b0
>Oct 25 01:16:08 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000434a56f6 state to 000000001b7a88b0
>Oct 25 01:16:08 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 000000001d7eec09 state to 000000001b7a88b0
>Oct 25 01:16:08 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:112] for [PLANE:28:plane 1A] state 000000001d7eec09
>Oct 25 01:16:08 [drm:drm_atomic_check_only [drm]] checking 000000001b7a88b0
>Oct 25 01:16:08 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 112
>Oct 25 01:16:08 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:08 [drm:drm_atomic_nonblocking_commit [drm]] committing 000000001b7a88b0 nonblocking
>Oct 25 01:16:08 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:08 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000001b7a88b0
>Oct 25 01:16:08 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000001b7a88b0
>Oct 25 01:16:08 [drm:drm_mode_addfb2 [drm]] [FB:113]
>Oct 25 01:16:08 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000772e8fbc
>Oct 25 01:16:08 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000473c4803 state to 00000000772e8fbc
>Oct 25 01:16:08 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 000000003180b920 state to 00000000772e8fbc
>Oct 25 01:16:08 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:113] for [PLANE:28:plane 1A] state 000000003180b920
>Oct 25 01:16:08 [drm:drm_atomic_check_only [drm]] checking 00000000772e8fbc
>Oct 25 01:16:08 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 113
>Oct 25 01:16:08 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:08 [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000772e8fbc nonblocking
>Oct 25 01:16:08 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:08 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000772e8fbc
>Oct 25 01:16:08 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000772e8fbc
>Oct 25 01:16:08 [drm:drm_mode_addfb2 [drm]] [FB:112]
>Oct 25 01:16:08 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000772e8fbc
>Oct 25 01:16:08 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000434a56f6 state to 00000000772e8fbc
>Oct 25 01:16:08 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 000000001d7eec09 state to 00000000772e8fbc
>Oct 25 01:16:08 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:112] for [PLANE:28:plane 1A] state 000000001d7eec09
>Oct 25 01:16:08 [drm:drm_atomic_check_only [drm]] checking 00000000772e8fbc
>Oct 25 01:16:08 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 112
>Oct 25 01:16:08 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:08 [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000772e8fbc nonblocking
>Oct 25 01:16:08 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:08 [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000001b7a88b0
>Oct 25 01:16:08 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000772e8fbc
>Oct 25 01:16:08 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000772e8fbc
>Oct 25 01:16:08 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000001b7a88b0
>Oct 25 01:16:08 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000001b7a88b0
>Oct 25 01:16:08 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000001b7a88b0
>Oct 25 01:16:08 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000001b7a88b0
>Oct 25 01:16:08 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000001b7a88b0
>Oct 25 01:16:08 [drm:drm_mode_addfb2 [drm]] [FB:113]
>Oct 25 01:16:08 [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000001b7a88b0
>Oct 25 01:16:08 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000a3a6daf9 state to 000000001b7a88b0
>Oct 25 01:16:08 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 000000004e18d68a state to 000000001b7a88b0
>Oct 25 01:16:08 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:113] for [PLANE:28:plane 1A] state 000000004e18d68a
>Oct 25 01:16:08 [drm:drm_atomic_check_only [drm]] checking 000000001b7a88b0
>Oct 25 01:16:08 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 113
>Oct 25 01:16:08 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:08 [drm:drm_atomic_nonblocking_commit [drm]] committing 000000001b7a88b0 nonblocking
>Oct 25 01:16:09 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:09 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000772e8fbc
>Oct 25 01:16:09 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000001b7a88b0
>Oct 25 01:16:09 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000001b7a88b0
>Oct 25 01:16:09 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000772e8fbc
>Oct 25 01:16:09 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000772e8fbc
>Oct 25 01:16:09 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000772e8fbc
>Oct 25 01:16:09 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000772e8fbc
>Oct 25 01:16:09 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000772e8fbc
>Oct 25 01:16:09 [drm:drm_mode_addfb2 [drm]] [FB:112]
>Oct 25 01:16:09 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000772e8fbc
>Oct 25 01:16:09 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000473c4803 state to 00000000772e8fbc
>Oct 25 01:16:09 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 000000003180b920 state to 00000000772e8fbc
>Oct 25 01:16:09 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:112] for [PLANE:28:plane 1A] state 000000003180b920
>Oct 25 01:16:09 [drm:drm_atomic_check_only [drm]] checking 00000000772e8fbc
>Oct 25 01:16:09 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 112
>Oct 25 01:16:09 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:09 [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000772e8fbc nonblocking
>Oct 25 01:16:09 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:09 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000772e8fbc
>Oct 25 01:16:09 [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000001b7a88b0
>Oct 25 01:16:09 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000001b7a88b0
>Oct 25 01:16:09 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000772e8fbc
>Oct 25 01:16:09 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000001b7a88b0
>Oct 25 01:16:09 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000001b7a88b0
>Oct 25 01:16:09 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000001b7a88b0
>Oct 25 01:16:09 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000001b7a88b0
>Oct 25 01:16:09 [drm:drm_mode_addfb2 [drm]] [FB:113]
>Oct 25 01:16:09 [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000001b7a88b0
>Oct 25 01:16:09 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000434a56f6 state to 000000001b7a88b0
>Oct 25 01:16:09 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 000000001d7eec09 state to 000000001b7a88b0
>Oct 25 01:16:09 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:113] for [PLANE:28:plane 1A] state 000000001d7eec09
>Oct 25 01:16:09 [drm:drm_atomic_check_only [drm]] checking 000000001b7a88b0
>Oct 25 01:16:09 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 113
>Oct 25 01:16:09 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:09 [drm:drm_atomic_nonblocking_commit [drm]] committing 000000001b7a88b0 nonblocking
>Oct 25 01:16:09 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:09 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000001b7a88b0
>Oct 25 01:16:09 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000772e8fbc
>Oct 25 01:16:09 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000772e8fbc
>Oct 25 01:16:09 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000001b7a88b0
>Oct 25 01:16:09 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000772e8fbc
>Oct 25 01:16:09 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000772e8fbc
>Oct 25 01:16:09 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000772e8fbc
>Oct 25 01:16:09 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000772e8fbc
>Oct 25 01:16:09 [drm:drm_mode_addfb2 [drm]] [FB:112]
>Oct 25 01:16:09 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000772e8fbc
>Oct 25 01:16:09 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000a3a6daf9 state to 00000000772e8fbc
>Oct 25 01:16:09 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 000000004e18d68a state to 00000000772e8fbc
>Oct 25 01:16:09 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:112] for [PLANE:28:plane 1A] state 000000004e18d68a
>Oct 25 01:16:09 [drm:drm_atomic_check_only [drm]] checking 00000000772e8fbc
>Oct 25 01:16:09 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 112
>Oct 25 01:16:09 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:09 [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000772e8fbc nonblocking
>Oct 25 01:16:09 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:09 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000772e8fbc
>Oct 25 01:16:09 [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000001b7a88b0
>Oct 25 01:16:09 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000001b7a88b0
>Oct 25 01:16:09 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000772e8fbc
>Oct 25 01:16:09 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000001b7a88b0
>Oct 25 01:16:09 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000001b7a88b0
>Oct 25 01:16:09 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000001b7a88b0
>Oct 25 01:16:09 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000001b7a88b0
>Oct 25 01:16:09 [drm:drm_mode_addfb2 [drm]] [FB:113]
>Oct 25 01:16:09 [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000001b7a88b0
>Oct 25 01:16:09 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000473c4803 state to 000000001b7a88b0
>Oct 25 01:16:09 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 000000003180b920 state to 000000001b7a88b0
>Oct 25 01:16:09 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:113] for [PLANE:28:plane 1A] state 000000003180b920
>Oct 25 01:16:09 [drm:drm_atomic_check_only [drm]] checking 000000001b7a88b0
>Oct 25 01:16:09 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 113
>Oct 25 01:16:09 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:09 [drm:drm_atomic_nonblocking_commit [drm]] committing 000000001b7a88b0 nonblocking
>Oct 25 01:16:09 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:09 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000001b7a88b0
>Oct 25 01:16:09 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000772e8fbc
>Oct 25 01:16:09 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000772e8fbc
>Oct 25 01:16:09 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000001b7a88b0
>Oct 25 01:16:09 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000772e8fbc
>Oct 25 01:16:09 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000772e8fbc
>Oct 25 01:16:09 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000772e8fbc
>Oct 25 01:16:09 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000772e8fbc
>Oct 25 01:16:09 [drm:drm_mode_addfb2 [drm]] [FB:112]
>Oct 25 01:16:09 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000772e8fbc
>Oct 25 01:16:09 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000434a56f6 state to 00000000772e8fbc
>Oct 25 01:16:09 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 000000001d7eec09 state to 00000000772e8fbc
>Oct 25 01:16:09 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:112] for [PLANE:28:plane 1A] state 000000001d7eec09
>Oct 25 01:16:09 [drm:drm_atomic_check_only [drm]] checking 00000000772e8fbc
>Oct 25 01:16:09 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 112
>Oct 25 01:16:09 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:09 [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000772e8fbc nonblocking
>Oct 25 01:16:09 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:09 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000772e8fbc
>Oct 25 01:16:09 [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000001b7a88b0
>Oct 25 01:16:09 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000772e8fbc
>Oct 25 01:16:09 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000001b7a88b0
>Oct 25 01:16:09 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000001b7a88b0
>Oct 25 01:16:09 [drm:drm_mode_addfb2 [drm]] [FB:113]
>Oct 25 01:16:09 [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000001b7a88b0
>Oct 25 01:16:09 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000a3a6daf9 state to 000000001b7a88b0
>Oct 25 01:16:09 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 000000004e18d68a state to 000000001b7a88b0
>Oct 25 01:16:09 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:113] for [PLANE:28:plane 1A] state 000000004e18d68a
>Oct 25 01:16:09 [drm:drm_atomic_check_only [drm]] checking 000000001b7a88b0
>Oct 25 01:16:09 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 113
>Oct 25 01:16:09 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:09 [drm:drm_atomic_nonblocking_commit [drm]] committing 000000001b7a88b0 nonblocking
>Oct 25 01:16:09 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:09 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000772e8fbc
>Oct 25 01:16:09 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000772e8fbc
>Oct 25 01:16:09 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000001b7a88b0
>Oct 25 01:16:09 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000001b7a88b0
>Oct 25 01:16:09 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000772e8fbc
>Oct 25 01:16:09 [drm:drm_mode_addfb2 [drm]] [FB:112]
>Oct 25 01:16:09 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000772e8fbc
>Oct 25 01:16:09 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000473c4803 state to 00000000772e8fbc
>Oct 25 01:16:09 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 000000003180b920 state to 00000000772e8fbc
>Oct 25 01:16:09 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:112] for [PLANE:28:plane 1A] state 000000003180b920
>Oct 25 01:16:09 [drm:drm_atomic_check_only [drm]] checking 00000000772e8fbc
>Oct 25 01:16:09 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 112
>Oct 25 01:16:09 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:09 [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000772e8fbc nonblocking
>Oct 25 01:16:09 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:09 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000772e8fbc
>Oct 25 01:16:09 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000772e8fbc
>Oct 25 01:16:09 [drm:drm_mode_addfb2 [drm]] [FB:113]
>Oct 25 01:16:09 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000772e8fbc
>Oct 25 01:16:09 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000a3a6daf9 state to 00000000772e8fbc
>Oct 25 01:16:09 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 000000004e18d68a state to 00000000772e8fbc
>Oct 25 01:16:09 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:113] for [PLANE:28:plane 1A] state 000000004e18d68a
>Oct 25 01:16:09 [drm:drm_atomic_check_only [drm]] checking 00000000772e8fbc
>Oct 25 01:16:09 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 113
>Oct 25 01:16:09 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:09 [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000772e8fbc nonblocking
>Oct 25 01:16:09 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:09 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000772e8fbc
>Oct 25 01:16:09 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000772e8fbc
>Oct 25 01:16:09 [drm:drm_mode_addfb2 [drm]] [FB:112]
>Oct 25 01:16:09 [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000001b7a88b0
>Oct 25 01:16:09 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000434a56f6 state to 000000001b7a88b0
>Oct 25 01:16:09 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 000000001d7eec09 state to 000000001b7a88b0
>Oct 25 01:16:09 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:112] for [PLANE:28:plane 1A] state 000000001d7eec09
>Oct 25 01:16:09 [drm:drm_atomic_check_only [drm]] checking 000000001b7a88b0
>Oct 25 01:16:09 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 112
>Oct 25 01:16:09 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:09 [drm:drm_atomic_nonblocking_commit [drm]] committing 000000001b7a88b0 nonblocking
>Oct 25 01:16:09 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:09 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000001b7a88b0
>Oct 25 01:16:09 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000001b7a88b0
>Oct 25 01:16:09 [drm:drm_mode_addfb2 [drm]] [FB:113]
>Oct 25 01:16:09 [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000001b7a88b0
>Oct 25 01:16:09 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000a3a6daf9 state to 000000001b7a88b0
>Oct 25 01:16:09 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 000000004e18d68a state to 000000001b7a88b0
>Oct 25 01:16:09 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:113] for [PLANE:28:plane 1A] state 000000004e18d68a
>Oct 25 01:16:09 [drm:drm_atomic_check_only [drm]] checking 000000001b7a88b0
>Oct 25 01:16:09 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 113
>Oct 25 01:16:09 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:09 [drm:drm_atomic_nonblocking_commit [drm]] committing 000000001b7a88b0 nonblocking
>Oct 25 01:16:09 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:09 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000772e8fbc
>Oct 25 01:16:09 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000772e8fbc
>Oct 25 01:16:09 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000772e8fbc
>Oct 25 01:16:09 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000001b7a88b0
>Oct 25 01:16:09 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000001b7a88b0
>Oct 25 01:16:09 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000772e8fbc
>Oct 25 01:16:09 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000772e8fbc
>Oct 25 01:16:09 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000772e8fbc
>Oct 25 01:16:09 [drm:drm_mode_addfb2 [drm]] [FB:111]
>Oct 25 01:16:09 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000772e8fbc
>Oct 25 01:16:09 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000473c4803 state to 00000000772e8fbc
>Oct 25 01:16:09 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 000000003180b920 state to 00000000772e8fbc
>Oct 25 01:16:09 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:111] for [PLANE:28:plane 1A] state 000000003180b920
>Oct 25 01:16:09 [drm:drm_atomic_check_only [drm]] checking 00000000772e8fbc
>Oct 25 01:16:09 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 111
>Oct 25 01:16:09 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:09 [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000772e8fbc nonblocking
>Oct 25 01:16:09 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:09 [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000001b7a88b0
>Oct 25 01:16:09 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000772e8fbc
>Oct 25 01:16:09 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000772e8fbc
>Oct 25 01:16:09 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000001b7a88b0
>Oct 25 01:16:09 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000001b7a88b0
>Oct 25 01:16:09 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000001b7a88b0
>Oct 25 01:16:09 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000001b7a88b0
>Oct 25 01:16:09 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000001b7a88b0
>Oct 25 01:16:09 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:42:cursor A] state 0000000022297d51
>Oct 25 01:16:09 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 110
>Oct 25 01:16:09 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:09 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:09 [drm:drm_mode_addfb2 [drm]] [FB:112]
>Oct 25 01:16:09 [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000001b7a88b0
>Oct 25 01:16:09 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000434a56f6 state to 000000001b7a88b0
>Oct 25 01:16:09 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 000000001d7eec09 state to 000000001b7a88b0
>Oct 25 01:16:09 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:112] for [PLANE:28:plane 1A] state 000000001d7eec09
>Oct 25 01:16:09 [drm:drm_atomic_check_only [drm]] checking 000000001b7a88b0
>Oct 25 01:16:09 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 112
>Oct 25 01:16:09 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:09 [drm:drm_atomic_nonblocking_commit [drm]] committing 000000001b7a88b0 nonblocking
>Oct 25 01:16:09 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:09 [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000001eccf585
>Oct 25 01:16:09 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000001eccf585
>Oct 25 01:16:09 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000001b7a88b0
>Oct 25 01:16:09 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000001b7a88b0
>Oct 25 01:16:09 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000001eccf585
>Oct 25 01:16:09 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000001eccf585
>Oct 25 01:16:09 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000001eccf585
>Oct 25 01:16:09 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000001eccf585
>Oct 25 01:16:09 [drm:drm_mode_addfb2 [drm]] [FB:111]
>Oct 25 01:16:09 [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000001eccf585
>Oct 25 01:16:09 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000a23f8f5f state to 000000001eccf585
>Oct 25 01:16:09 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 0000000029fac543 state to 000000001eccf585
>Oct 25 01:16:09 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:111] for [PLANE:28:plane 1A] state 0000000029fac543
>Oct 25 01:16:09 [drm:drm_atomic_check_only [drm]] checking 000000001eccf585
>Oct 25 01:16:09 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 111
>Oct 25 01:16:09 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:09 [drm:drm_atomic_nonblocking_commit [drm]] committing 000000001eccf585 nonblocking
>Oct 25 01:16:09 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:09 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000001eccf585
>Oct 25 01:16:09 [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000001f0d0149
>Oct 25 01:16:09 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000001f0d0149
>Oct 25 01:16:09 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000001eccf585
>Oct 25 01:16:09 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000001f0d0149
>Oct 25 01:16:09 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000001f0d0149
>Oct 25 01:16:09 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000001f0d0149
>Oct 25 01:16:09 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000001f0d0149
>Oct 25 01:16:09 [drm:drm_mode_addfb2 [drm]] [FB:112]
>Oct 25 01:16:09 [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000001f0d0149
>Oct 25 01:16:09 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 000000002fe59080 state to 000000001f0d0149
>Oct 25 01:16:09 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 000000004c4f76a6 state to 000000001f0d0149
>Oct 25 01:16:09 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:112] for [PLANE:28:plane 1A] state 000000004c4f76a6
>Oct 25 01:16:09 [drm:drm_atomic_check_only [drm]] checking 000000001f0d0149
>Oct 25 01:16:09 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 112
>Oct 25 01:16:09 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:09 [drm:drm_atomic_nonblocking_commit [drm]] committing 000000001f0d0149 nonblocking
>Oct 25 01:16:09 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:09 [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000003b3393c9
>Oct 25 01:16:09 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000003b3393c9
>Oct 25 01:16:09 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000001f0d0149
>Oct 25 01:16:09 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000001f0d0149
>Oct 25 01:16:09 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000003b3393c9
>Oct 25 01:16:09 [drm:drm_mode_addfb2 [drm]] [FB:111]
>Oct 25 01:16:09 [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000003b3393c9
>Oct 25 01:16:09 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 000000001ab56d54 state to 000000003b3393c9
>Oct 25 01:16:09 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 0000000005afd297 state to 000000003b3393c9
>Oct 25 01:16:09 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:111] for [PLANE:28:plane 1A] state 0000000005afd297
>Oct 25 01:16:09 [drm:drm_atomic_check_only [drm]] checking 000000003b3393c9
>Oct 25 01:16:09 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 111
>Oct 25 01:16:09 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:09 [drm:drm_atomic_nonblocking_commit [drm]] committing 000000003b3393c9 nonblocking
>Oct 25 01:16:09 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:09 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000003b3393c9
>Oct 25 01:16:09 [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000001aaab301
>Oct 25 01:16:09 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000003b3393c9
>Oct 25 01:16:09 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000001aaab301
>Oct 25 01:16:09 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000001aaab301
>Oct 25 01:16:09 [drm:drm_mode_addfb2 [drm]] [FB:112]
>Oct 25 01:16:09 [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000001aaab301
>Oct 25 01:16:09 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 000000008bde6312 state to 000000001aaab301
>Oct 25 01:16:09 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 000000005077c257 state to 000000001aaab301
>Oct 25 01:16:09 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:112] for [PLANE:28:plane 1A] state 000000005077c257
>Oct 25 01:16:09 [drm:drm_atomic_check_only [drm]] checking 000000001aaab301
>Oct 25 01:16:09 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 112
>Oct 25 01:16:09 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:09 [drm:drm_atomic_nonblocking_commit [drm]] committing 000000001aaab301 nonblocking
>Oct 25 01:16:09 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:09 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000001aaab301
>Oct 25 01:16:09 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000001aaab301
>Oct 25 01:16:09 [drm:drm_mode_addfb2 [drm]] [FB:111]
>Oct 25 01:16:09 [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000001aaab301
>Oct 25 01:16:09 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 000000002480bd06 state to 000000001aaab301
>Oct 25 01:16:09 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 000000005dcb047e state to 000000001aaab301
>Oct 25 01:16:09 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:111] for [PLANE:28:plane 1A] state 000000005dcb047e
>Oct 25 01:16:09 [drm:drm_atomic_check_only [drm]] checking 000000001aaab301
>Oct 25 01:16:09 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 111
>Oct 25 01:16:09 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:09 [drm:drm_atomic_nonblocking_commit [drm]] committing 000000001aaab301 nonblocking
>Oct 25 01:16:09 [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000001ab56d54
>Oct 25 01:16:09 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000001ab56d54
>Oct 25 01:16:09 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000001ab56d54
>Oct 25 01:16:09 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000001ab56d54
>Oct 25 01:16:09 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000001ab56d54
>Oct 25 01:16:09 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000001ab56d54
>Oct 25 01:16:09 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:09 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000001aaab301
>Oct 25 01:16:09 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000001aaab301
>Oct 25 01:16:09 [drm:drm_mode_addfb2 [drm]] [FB:112]
>Oct 25 01:16:09 [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000001ab56d54
>Oct 25 01:16:09 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 000000003b3393c9 state to 000000001ab56d54
>Oct 25 01:16:09 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 0000000005afd297 state to 000000001ab56d54
>Oct 25 01:16:09 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:112] for [PLANE:28:plane 1A] state 0000000005afd297
>Oct 25 01:16:09 [drm:drm_atomic_check_only [drm]] checking 000000001ab56d54
>Oct 25 01:16:09 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 112
>Oct 25 01:16:09 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:09 [drm:drm_atomic_nonblocking_commit [drm]] committing 000000001ab56d54 nonblocking
>Oct 25 01:16:09 [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000006087c748
>Oct 25 01:16:09 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000006087c748
>Oct 25 01:16:09 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000006087c748
>Oct 25 01:16:09 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000006087c748
>Oct 25 01:16:09 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:09 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000006087c748
>Oct 25 01:16:09 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000006087c748
>Oct 25 01:16:09 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000001ab56d54
>Oct 25 01:16:09 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000001ab56d54
>Oct 25 01:16:09 [drm:drm_mode_addfb2 [drm]] [FB:111]
>Oct 25 01:16:09 [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000006087c748
>Oct 25 01:16:09 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 0000000078f5ca8b state to 000000006087c748
>Oct 25 01:16:09 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000d096858d state to 000000006087c748
>Oct 25 01:16:09 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:111] for [PLANE:28:plane 1A] state 00000000d096858d
>Oct 25 01:16:09 [drm:drm_atomic_check_only [drm]] checking 000000006087c748
>Oct 25 01:16:09 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 111
>Oct 25 01:16:09 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:09 [drm:drm_atomic_nonblocking_commit [drm]] committing 000000006087c748 nonblocking
>Oct 25 01:16:09 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:09 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000006087c748
>Oct 25 01:16:09 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000006087c748
>Oct 25 01:16:09 [drm:drm_mode_addfb2 [drm]] [FB:112]
>Oct 25 01:16:09 [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000006087c748
>Oct 25 01:16:09 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 000000001fc0d337 state to 000000006087c748
>Oct 25 01:16:09 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 0000000071a397dd state to 000000006087c748
>Oct 25 01:16:09 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:112] for [PLANE:28:plane 1A] state 0000000071a397dd
>Oct 25 01:16:09 [drm:drm_atomic_check_only [drm]] checking 000000006087c748
>Oct 25 01:16:09 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 112
>Oct 25 01:16:09 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:09 [drm:drm_atomic_nonblocking_commit [drm]] committing 000000006087c748 nonblocking
>Oct 25 01:16:09 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:09 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000ba416ab1
>Oct 25 01:16:09 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000ba416ab1
>Oct 25 01:16:09 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000006087c748
>Oct 25 01:16:09 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000006087c748
>Oct 25 01:16:09 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000ba416ab1
>Oct 25 01:16:09 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000ba416ab1
>Oct 25 01:16:09 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000ba416ab1
>Oct 25 01:16:09 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000ba416ab1
>Oct 25 01:16:09 [drm:drm_mode_addfb2 [drm]] [FB:111]
>Oct 25 01:16:09 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000ba416ab1
>Oct 25 01:16:09 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 0000000052044b10 state to 00000000ba416ab1
>Oct 25 01:16:09 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000e60a6dc4 state to 00000000ba416ab1
>Oct 25 01:16:09 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:111] for [PLANE:28:plane 1A] state 00000000e60a6dc4
>Oct 25 01:16:09 [drm:drm_atomic_check_only [drm]] checking 00000000ba416ab1
>Oct 25 01:16:09 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 111
>Oct 25 01:16:09 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:09 [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000ba416ab1 nonblocking
>Oct 25 01:16:09 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:09 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000ba416ab1
>Oct 25 01:16:09 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000ba416ab1
>Oct 25 01:16:09 [drm:drm_mode_addfb2 [drm]] [FB:112]
>Oct 25 01:16:09 [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000009e1f3756
>Oct 25 01:16:09 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 0000000074ccde13 state to 000000009e1f3756
>Oct 25 01:16:09 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 000000002403bb64 state to 000000009e1f3756
>Oct 25 01:16:09 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:112] for [PLANE:28:plane 1A] state 000000002403bb64
>Oct 25 01:16:09 [drm:drm_atomic_check_only [drm]] checking 000000009e1f3756
>Oct 25 01:16:09 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 112
>Oct 25 01:16:09 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:09 [drm:drm_atomic_nonblocking_commit [drm]] committing 000000009e1f3756 nonblocking
>Oct 25 01:16:09 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:09 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000009e1f3756
>Oct 25 01:16:09 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000009e1f3756
>Oct 25 01:16:09 [drm:drm_mode_addfb2 [drm]] [FB:111]
>Oct 25 01:16:09 [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000009e1f3756
>Oct 25 01:16:09 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 0000000052044b10 state to 000000009e1f3756
>Oct 25 01:16:09 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 000000005e80c054 state to 000000009e1f3756
>Oct 25 01:16:09 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:111] for [PLANE:28:plane 1A] state 000000005e80c054
>Oct 25 01:16:09 [drm:drm_atomic_check_only [drm]] checking 000000009e1f3756
>Oct 25 01:16:09 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 111
>Oct 25 01:16:09 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:09 [drm:drm_atomic_nonblocking_commit [drm]] committing 000000009e1f3756 nonblocking
>Oct 25 01:16:09 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:09 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000009e1f3756
>Oct 25 01:16:09 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000ba416ab1
>Oct 25 01:16:09 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000009e1f3756
>Oct 25 01:16:09 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000ba416ab1
>Oct 25 01:16:09 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000ba416ab1
>Oct 25 01:16:09 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000ba416ab1
>Oct 25 01:16:09 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000ba416ab1
>Oct 25 01:16:09 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000ba416ab1
>Oct 25 01:16:09 [drm:drm_mode_addfb2 [drm]] [FB:112]
>Oct 25 01:16:09 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000ba416ab1
>Oct 25 01:16:09 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 000000009e1f3756 state to 00000000ba416ab1
>Oct 25 01:16:09 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 0000000062c89365 state to 00000000ba416ab1
>Oct 25 01:16:09 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:112] for [PLANE:28:plane 1A] state 0000000062c89365
>Oct 25 01:16:09 [drm:drm_atomic_check_only [drm]] checking 00000000ba416ab1
>Oct 25 01:16:09 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 112
>Oct 25 01:16:09 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:09 [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000ba416ab1 nonblocking
>Oct 25 01:16:09 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:09 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000ba416ab1
>Oct 25 01:16:09 [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000074ccde13
>Oct 25 01:16:09 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000ba416ab1
>Oct 25 01:16:09 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000074ccde13
>Oct 25 01:16:09 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000074ccde13
>Oct 25 01:16:09 [drm:drm_mode_addfb2 [drm]] [FB:111]
>Oct 25 01:16:09 [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000074ccde13
>Oct 25 01:16:09 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000ba416ab1 state to 0000000074ccde13
>Oct 25 01:16:09 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 000000005dcb047e state to 0000000074ccde13
>Oct 25 01:16:09 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:111] for [PLANE:28:plane 1A] state 000000005dcb047e
>Oct 25 01:16:09 [drm:drm_atomic_check_only [drm]] checking 0000000074ccde13
>Oct 25 01:16:09 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 111
>Oct 25 01:16:09 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:09 [drm:drm_atomic_nonblocking_commit [drm]] committing 0000000074ccde13 nonblocking
>Oct 25 01:16:09 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:09 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000074ccde13
>Oct 25 01:16:09 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000074ccde13
>Oct 25 01:16:09 [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000052044b10
>Oct 25 01:16:09 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000052044b10
>Oct 25 01:16:09 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000052044b10
>Oct 25 01:16:09 [drm:drm_mode_addfb2 [drm]] [FB:112]
>Oct 25 01:16:09 [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000052044b10
>Oct 25 01:16:09 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 0000000074ccde13 state to 0000000052044b10
>Oct 25 01:16:09 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000925ca3c6 state to 0000000052044b10
>Oct 25 01:16:09 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:112] for [PLANE:28:plane 1A] state 00000000925ca3c6
>Oct 25 01:16:09 [drm:drm_atomic_check_only [drm]] checking 0000000052044b10
>Oct 25 01:16:09 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 112
>Oct 25 01:16:09 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:09 [drm:drm_atomic_nonblocking_commit [drm]] committing 0000000052044b10 nonblocking
>Oct 25 01:16:09 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:09 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000052044b10
>Oct 25 01:16:09 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000052044b10
>Oct 25 01:16:09 [drm:drm_mode_addfb2 [drm]] [FB:111]
>Oct 25 01:16:09 [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000009e1f3756
>Oct 25 01:16:09 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 0000000052044b10 state to 000000009e1f3756
>Oct 25 01:16:09 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 000000005077c257 state to 000000009e1f3756
>Oct 25 01:16:09 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:111] for [PLANE:28:plane 1A] state 000000005077c257
>Oct 25 01:16:09 [drm:drm_atomic_check_only [drm]] checking 000000009e1f3756
>Oct 25 01:16:09 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 111
>Oct 25 01:16:09 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:09 [drm:drm_atomic_nonblocking_commit [drm]] committing 000000009e1f3756 nonblocking
>Oct 25 01:16:09 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:09 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000009e1f3756
>Oct 25 01:16:09 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000009e1f3756
>Oct 25 01:16:09 [drm:drm_mode_addfb2 [drm]] [FB:112]
>Oct 25 01:16:09 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000ba416ab1
>Oct 25 01:16:09 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 000000009e1f3756 state to 00000000ba416ab1
>Oct 25 01:16:09 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000add5d5e9 state to 00000000ba416ab1
>Oct 25 01:16:09 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:112] for [PLANE:28:plane 1A] state 00000000add5d5e9
>Oct 25 01:16:09 [drm:drm_atomic_check_only [drm]] checking 00000000ba416ab1
>Oct 25 01:16:09 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 112
>Oct 25 01:16:09 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:09 [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000ba416ab1 nonblocking
>Oct 25 01:16:09 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:09 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000ba416ab1
>Oct 25 01:16:09 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000ba416ab1
>Oct 25 01:16:09 [drm:drm_mode_addfb2 [drm]] [FB:111]
>Oct 25 01:16:09 [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000074ccde13
>Oct 25 01:16:09 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000ba416ab1 state to 0000000074ccde13
>Oct 25 01:16:09 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000064a1649 state to 0000000074ccde13
>Oct 25 01:16:09 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:111] for [PLANE:28:plane 1A] state 00000000064a1649
>Oct 25 01:16:09 [drm:drm_atomic_check_only [drm]] checking 0000000074ccde13
>Oct 25 01:16:09 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 111
>Oct 25 01:16:09 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:09 [drm:drm_atomic_nonblocking_commit [drm]] committing 0000000074ccde13 nonblocking
>Oct 25 01:16:09 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:09 [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000052044b10
>Oct 25 01:16:09 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000052044b10
>Oct 25 01:16:09 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000052044b10
>Oct 25 01:16:09 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000074ccde13
>Oct 25 01:16:09 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000074ccde13
>Oct 25 01:16:09 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000052044b10
>Oct 25 01:16:09 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000052044b10
>Oct 25 01:16:09 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000052044b10
>Oct 25 01:16:09 [drm:drm_mode_addfb2 [drm]] [FB:112]
>Oct 25 01:16:09 [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000052044b10
>Oct 25 01:16:09 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 0000000074ccde13 state to 0000000052044b10
>Oct 25 01:16:09 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000413cb84f state to 0000000052044b10
>Oct 25 01:16:09 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:112] for [PLANE:28:plane 1A] state 00000000413cb84f
>Oct 25 01:16:09 [drm:drm_atomic_check_only [drm]] checking 0000000052044b10
>Oct 25 01:16:09 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 112
>Oct 25 01:16:09 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:09 [drm:drm_atomic_nonblocking_commit [drm]] committing 0000000052044b10 nonblocking
>Oct 25 01:16:09 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:09 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000052044b10
>Oct 25 01:16:09 [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000093deb6b7
>Oct 25 01:16:09 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000093deb6b7
>Oct 25 01:16:09 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000052044b10
>Oct 25 01:16:09 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000093deb6b7
>Oct 25 01:16:09 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000093deb6b7
>Oct 25 01:16:09 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000093deb6b7
>Oct 25 01:16:09 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000093deb6b7
>Oct 25 01:16:09 [drm:drm_mode_addfb2 [drm]] [FB:111]
>Oct 25 01:16:09 [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000093deb6b7
>Oct 25 01:16:09 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 0000000080edc7c0 state to 0000000093deb6b7
>Oct 25 01:16:09 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000087410c8 state to 0000000093deb6b7
>Oct 25 01:16:09 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:111] for [PLANE:28:plane 1A] state 00000000087410c8
>Oct 25 01:16:09 [drm:drm_atomic_check_only [drm]] checking 0000000093deb6b7
>Oct 25 01:16:09 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 111
>Oct 25 01:16:09 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:09 [drm:drm_atomic_nonblocking_commit [drm]] committing 0000000093deb6b7 nonblocking
>Oct 25 01:16:09 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:09 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000093deb6b7
>Oct 25 01:16:09 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000093deb6b7
>Oct 25 01:16:09 [drm:drm_mode_addfb2 [drm]] [FB:112]
>Oct 25 01:16:09 [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000022f13fb8
>Oct 25 01:16:09 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 000000004017ba0f state to 0000000022f13fb8
>Oct 25 01:16:09 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 0000000040b21ff5 state to 0000000022f13fb8
>Oct 25 01:16:09 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:112] for [PLANE:28:plane 1A] state 0000000040b21ff5
>Oct 25 01:16:09 [drm:drm_atomic_check_only [drm]] checking 0000000022f13fb8
>Oct 25 01:16:09 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 112
>Oct 25 01:16:09 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:09 [drm:drm_atomic_nonblocking_commit [drm]] committing 0000000022f13fb8 nonblocking
>Oct 25 01:16:09 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:09 [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000009e1f3756
>Oct 25 01:16:09 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000022f13fb8
>Oct 25 01:16:09 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000022f13fb8
>Oct 25 01:16:09 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000009e1f3756
>Oct 25 01:16:09 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000009e1f3756
>Oct 25 01:16:09 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000009e1f3756
>Oct 25 01:16:09 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000009e1f3756
>Oct 25 01:16:09 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000009e1f3756
>Oct 25 01:16:09 [drm:drm_mode_addfb2 [drm]] [FB:111]
>Oct 25 01:16:09 [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000009e1f3756
>Oct 25 01:16:09 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 0000000074ccde13 state to 000000009e1f3756
>Oct 25 01:16:09 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 000000005e80c054 state to 000000009e1f3756
>Oct 25 01:16:09 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:111] for [PLANE:28:plane 1A] state 000000005e80c054
>Oct 25 01:16:09 [drm:drm_atomic_check_only [drm]] checking 000000009e1f3756
>Oct 25 01:16:09 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 111
>Oct 25 01:16:09 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:09 [drm:drm_atomic_nonblocking_commit [drm]] committing 000000009e1f3756 nonblocking
>Oct 25 01:16:09 IPv6: ADDRCONF(NETDEV_UP): wlp0s20f0u5: link is not ready
>Oct 25 01:16:09 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:09 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000009e1f3756
>Oct 25 01:16:09 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000009e1f3756
>Oct 25 01:16:09 [drm:drm_mode_addfb2 [drm]] [FB:112]
>Oct 25 01:16:09 [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000001f0d0149
>Oct 25 01:16:09 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000a23f8f5f state to 000000001f0d0149
>Oct 25 01:16:09 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 000000004c4f76a6 state to 000000001f0d0149
>Oct 25 01:16:09 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:112] for [PLANE:28:plane 1A] state 000000004c4f76a6
>Oct 25 01:16:09 [drm:drm_atomic_check_only [drm]] checking 000000001f0d0149
>Oct 25 01:16:09 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 112
>Oct 25 01:16:09 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:09 [drm:drm_atomic_nonblocking_commit [drm]] committing 000000001f0d0149 nonblocking
>Oct 25 01:16:09 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:09 [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000001eccf585
>Oct 25 01:16:09 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000001eccf585
>Oct 25 01:16:09 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000001f0d0149
>Oct 25 01:16:09 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000001f0d0149
>Oct 25 01:16:09 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000001eccf585
>Oct 25 01:16:09 [drm:drm_mode_addfb2 [drm]] [FB:111]
>Oct 25 01:16:09 [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000001eccf585
>Oct 25 01:16:09 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 000000001f0d0149 state to 000000001eccf585
>Oct 25 01:16:09 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000bf5ed01f state to 000000001eccf585
>Oct 25 01:16:09 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:111] for [PLANE:28:plane 1A] state 00000000bf5ed01f
>Oct 25 01:16:09 [drm:drm_atomic_check_only [drm]] checking 000000001eccf585
>Oct 25 01:16:09 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 111
>Oct 25 01:16:09 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:09 [drm:drm_atomic_nonblocking_commit [drm]] committing 000000001eccf585 nonblocking
>Oct 25 01:16:09 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:09 [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000003b3393c9
>Oct 25 01:16:09 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000003b3393c9
>Oct 25 01:16:09 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000001eccf585
>Oct 25 01:16:09 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000001eccf585
>Oct 25 01:16:09 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000003b3393c9
>Oct 25 01:16:09 [drm:drm_mode_addfb2 [drm]] [FB:112]
>Oct 25 01:16:09 [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000003b3393c9
>Oct 25 01:16:09 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 000000002fe59080 state to 000000003b3393c9
>Oct 25 01:16:09 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000aa094b5a state to 000000003b3393c9
>Oct 25 01:16:09 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:112] for [PLANE:28:plane 1A] state 00000000aa094b5a
>Oct 25 01:16:09 [drm:drm_atomic_check_only [drm]] checking 000000003b3393c9
>Oct 25 01:16:09 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 112
>Oct 25 01:16:09 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:09 [drm:drm_atomic_nonblocking_commit [drm]] committing 000000003b3393c9 nonblocking
>Oct 25 01:16:09 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:09 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000003b3393c9
>Oct 25 01:16:09 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000003b3393c9
>Oct 25 01:16:09 [drm:drm_mode_addfb2 [drm]] [FB:111]
>Oct 25 01:16:09 [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000052044b10
>Oct 25 01:16:09 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000ba416ab1 state to 0000000052044b10
>Oct 25 01:16:09 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 0000000071a397dd state to 0000000052044b10
>Oct 25 01:16:09 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:111] for [PLANE:28:plane 1A] state 0000000071a397dd
>Oct 25 01:16:09 [drm:drm_atomic_check_only [drm]] checking 0000000052044b10
>Oct 25 01:16:09 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 111
>Oct 25 01:16:09 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:09 [drm:drm_atomic_nonblocking_commit [drm]] committing 0000000052044b10 nonblocking
>Oct 25 01:16:09 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:09 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000052044b10
>Oct 25 01:16:09 [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000074ccde13
>Oct 25 01:16:09 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000074ccde13
>Oct 25 01:16:09 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000074ccde13
>Oct 25 01:16:09 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000052044b10
>Oct 25 01:16:09 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000074ccde13
>Oct 25 01:16:09 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000074ccde13
>Oct 25 01:16:09 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000074ccde13
>Oct 25 01:16:09 [drm:drm_mode_addfb2 [drm]] [FB:112]
>Oct 25 01:16:09 [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000074ccde13
>Oct 25 01:16:09 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 000000009e1f3756 state to 0000000074ccde13
>Oct 25 01:16:09 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 000000002403bb64 state to 0000000074ccde13
>Oct 25 01:16:09 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:112] for [PLANE:28:plane 1A] state 000000002403bb64
>Oct 25 01:16:09 [drm:drm_atomic_check_only [drm]] checking 0000000074ccde13
>Oct 25 01:16:09 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 112
>Oct 25 01:16:09 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:09 [drm:drm_atomic_nonblocking_commit [drm]] committing 0000000074ccde13 nonblocking
>Oct 25 01:16:09 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:09 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000074ccde13
>Oct 25 01:16:09 [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000052044b10
>Oct 25 01:16:09 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000052044b10
>Oct 25 01:16:09 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000052044b10
>Oct 25 01:16:09 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000074ccde13
>Oct 25 01:16:09 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000052044b10
>Oct 25 01:16:09 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000052044b10
>Oct 25 01:16:09 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000052044b10
>Oct 25 01:16:09 [drm:drm_mode_addfb2 [drm]] [FB:111]
>Oct 25 01:16:09 [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000052044b10
>Oct 25 01:16:09 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 0000000074ccde13 state to 0000000052044b10
>Oct 25 01:16:09 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000d096858d state to 0000000052044b10
>Oct 25 01:16:09 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:111] for [PLANE:28:plane 1A] state 00000000d096858d
>Oct 25 01:16:09 [drm:drm_atomic_check_only [drm]] checking 0000000052044b10
>Oct 25 01:16:09 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 111
>Oct 25 01:16:09 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:09 [drm:drm_atomic_nonblocking_commit [drm]] committing 0000000052044b10 nonblocking
>Oct 25 01:16:09 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:09 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000052044b10
>Oct 25 01:16:09 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000052044b10
>Oct 25 01:16:09 [drm:drm_mode_addfb2 [drm]] [FB:112]
>Oct 25 01:16:09 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000ba416ab1
>Oct 25 01:16:09 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 0000000052044b10 state to 00000000ba416ab1
>Oct 25 01:16:09 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000413cb84f state to 00000000ba416ab1
>Oct 25 01:16:09 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:112] for [PLANE:28:plane 1A] state 00000000413cb84f
>Oct 25 01:16:09 [drm:drm_atomic_check_only [drm]] checking 00000000ba416ab1
>Oct 25 01:16:09 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 112
>Oct 25 01:16:09 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:09 [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000ba416ab1 nonblocking
>Oct 25 01:16:09 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:09 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000ba416ab1
>Oct 25 01:16:09 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000ba416ab1
>Oct 25 01:16:09 [drm:drm_mode_addfb2 [drm]] [FB:111]
>Oct 25 01:16:09 [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000009e1f3756
>Oct 25 01:16:09 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000ba416ab1 state to 000000009e1f3756
>Oct 25 01:16:09 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 000000008fc3b409 state to 000000009e1f3756
>Oct 25 01:16:09 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:111] for [PLANE:28:plane 1A] state 000000008fc3b409
>Oct 25 01:16:09 [drm:drm_atomic_check_only [drm]] checking 000000009e1f3756
>Oct 25 01:16:09 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 111
>Oct 25 01:16:09 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:09 [drm:drm_atomic_nonblocking_commit [drm]] committing 000000009e1f3756 nonblocking
>Oct 25 01:16:09 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:09 [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000074ccde13
>Oct 25 01:16:09 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000074ccde13
>Oct 25 01:16:09 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000009e1f3756
>Oct 25 01:16:09 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000009e1f3756
>Oct 25 01:16:09 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000074ccde13
>Oct 25 01:16:09 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000074ccde13
>Oct 25 01:16:09 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000074ccde13
>Oct 25 01:16:09 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000074ccde13
>Oct 25 01:16:09 [drm:drm_mode_addfb2 [drm]] [FB:112]
>Oct 25 01:16:09 [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000074ccde13
>Oct 25 01:16:09 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 000000009e1f3756 state to 0000000074ccde13
>Oct 25 01:16:09 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000925ca3c6 state to 0000000074ccde13
>Oct 25 01:16:09 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:112] for [PLANE:28:plane 1A] state 00000000925ca3c6
>Oct 25 01:16:09 [drm:drm_atomic_check_only [drm]] checking 0000000074ccde13
>Oct 25 01:16:09 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 112
>Oct 25 01:16:09 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:09 [drm:drm_atomic_nonblocking_commit [drm]] committing 0000000074ccde13 nonblocking
>Oct 25 01:16:09 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:09 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000074ccde13
>Oct 25 01:16:09 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000074ccde13
>Oct 25 01:16:09 [drm:drm_mode_addfb2 [drm]] [FB:111]
>Oct 25 01:16:09 [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000052044b10
>Oct 25 01:16:09 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 0000000074ccde13 state to 0000000052044b10
>Oct 25 01:16:09 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 000000007308b7a0 state to 0000000052044b10
>Oct 25 01:16:09 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:111] for [PLANE:28:plane 1A] state 000000007308b7a0
>Oct 25 01:16:09 [drm:drm_atomic_check_only [drm]] checking 0000000052044b10
>Oct 25 01:16:09 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 111
>Oct 25 01:16:09 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:09 [drm:drm_atomic_nonblocking_commit [drm]] committing 0000000052044b10 nonblocking
>Oct 25 01:16:09 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:09 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000052044b10
>Oct 25 01:16:09 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000052044b10
>Oct 25 01:16:09 [drm:drm_mode_addfb2 [drm]] [FB:112]
>Oct 25 01:16:09 [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000043b006de
>Oct 25 01:16:09 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000052b2c0d state to 0000000043b006de
>Oct 25 01:16:09 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000ca33d97c state to 0000000043b006de
>Oct 25 01:16:09 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:112] for [PLANE:28:plane 1A] state 00000000ca33d97c
>Oct 25 01:16:09 [drm:drm_atomic_check_only [drm]] checking 0000000043b006de
>Oct 25 01:16:09 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 112
>Oct 25 01:16:09 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:09 [drm:drm_atomic_nonblocking_commit [drm]] committing 0000000043b006de nonblocking
>Oct 25 01:16:09 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:09 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000043b006de
>Oct 25 01:16:09 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000043b006de
>Oct 25 01:16:09 [drm:drm_mode_addfb2 [drm]] [FB:111]
>Oct 25 01:16:09 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000d3dfc947
>Oct 25 01:16:09 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 000000009b9aab00 state to 00000000d3dfc947
>Oct 25 01:16:09 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000371a467f state to 00000000d3dfc947
>Oct 25 01:16:09 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:111] for [PLANE:28:plane 1A] state 00000000371a467f
>Oct 25 01:16:09 [drm:drm_atomic_check_only [drm]] checking 00000000d3dfc947
>Oct 25 01:16:09 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 111
>Oct 25 01:16:09 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:09 [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000d3dfc947 nonblocking
>Oct 25 01:16:09 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:09 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000d3dfc947
>Oct 25 01:16:09 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000d3dfc947
>Oct 25 01:16:09 [drm:drm_mode_addfb2 [drm]] [FB:112]
>Oct 25 01:16:09 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000d3dfc947
>Oct 25 01:16:09 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000052b2c0d state to 00000000d3dfc947
>Oct 25 01:16:09 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000ca882a93 state to 00000000d3dfc947
>Oct 25 01:16:09 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:112] for [PLANE:28:plane 1A] state 00000000ca882a93
>Oct 25 01:16:09 [drm:drm_atomic_check_only [drm]] checking 00000000d3dfc947
>Oct 25 01:16:09 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 112
>Oct 25 01:16:09 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:09 [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000d3dfc947 nonblocking
>Oct 25 01:16:09 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:09 [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000001ab56d54
>Oct 25 01:16:09 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000001ab56d54
>Oct 25 01:16:09 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000d3dfc947
>Oct 25 01:16:09 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000d3dfc947
>Oct 25 01:16:09 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000001ab56d54
>Oct 25 01:16:09 [drm:drm_mode_addfb2 [drm]] [FB:111]
>Oct 25 01:16:09 [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000001ab56d54
>Oct 25 01:16:09 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000602b335e state to 000000001ab56d54
>Oct 25 01:16:09 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 0000000005afd297 state to 000000001ab56d54
>Oct 25 01:16:09 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:111] for [PLANE:28:plane 1A] state 0000000005afd297
>Oct 25 01:16:09 [drm:drm_atomic_check_only [drm]] checking 000000001ab56d54
>Oct 25 01:16:09 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 111
>Oct 25 01:16:09 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:09 [drm:drm_atomic_nonblocking_commit [drm]] committing 000000001ab56d54 nonblocking
>Oct 25 01:16:09 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:09 [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000002fe59080
>Oct 25 01:16:09 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000002fe59080
>Oct 25 01:16:09 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000001ab56d54
>Oct 25 01:16:09 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000001ab56d54
>Oct 25 01:16:09 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000002fe59080
>Oct 25 01:16:09 [drm:drm_mode_addfb2 [drm]] [FB:112]
>Oct 25 01:16:09 [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000002fe59080
>Oct 25 01:16:09 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 000000003b3393c9 state to 000000002fe59080
>Oct 25 01:16:09 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 000000005fbad319 state to 000000002fe59080
>Oct 25 01:16:09 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:112] for [PLANE:28:plane 1A] state 000000005fbad319
>Oct 25 01:16:09 [drm:drm_atomic_check_only [drm]] checking 000000002fe59080
>Oct 25 01:16:09 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 112
>Oct 25 01:16:09 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:09 [drm:drm_atomic_nonblocking_commit [drm]] committing 000000002fe59080 nonblocking
>Oct 25 01:16:10 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:10 [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000001f0d0149
>Oct 25 01:16:10 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000001f0d0149
>Oct 25 01:16:10 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000001f0d0149
>Oct 25 01:16:10 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000001f0d0149
>Oct 25 01:16:10 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000002fe59080
>Oct 25 01:16:10 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000002fe59080
>Oct 25 01:16:10 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000001f0d0149
>Oct 25 01:16:10 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000001f0d0149
>Oct 25 01:16:10 [drm:drm_mode_addfb2 [drm]] [FB:111]
>Oct 25 01:16:10 [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000001f0d0149
>Oct 25 01:16:10 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 000000001eccf585 state to 000000001f0d0149
>Oct 25 01:16:10 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000bf5ed01f state to 000000001f0d0149
>Oct 25 01:16:10 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:111] for [PLANE:28:plane 1A] state 00000000bf5ed01f
>Oct 25 01:16:10 [drm:drm_atomic_check_only [drm]] checking 000000001f0d0149
>Oct 25 01:16:10 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 111
>Oct 25 01:16:10 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:10 [drm:drm_atomic_nonblocking_commit [drm]] committing 000000001f0d0149 nonblocking
>Oct 25 01:16:10 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000a23f8f5f
>Oct 25 01:16:10 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:10 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000a23f8f5f
>Oct 25 01:16:10 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000001f0d0149
>Oct 25 01:16:10 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000001f0d0149
>Oct 25 01:16:10 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000a23f8f5f
>Oct 25 01:16:10 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000a23f8f5f
>Oct 25 01:16:10 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000a23f8f5f
>Oct 25 01:16:10 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000a23f8f5f
>Oct 25 01:16:10 [drm:drm_mode_addfb2 [drm]] [FB:112]
>Oct 25 01:16:10 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000a23f8f5f
>Oct 25 01:16:10 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 000000001f0d0149 state to 00000000a23f8f5f
>Oct 25 01:16:10 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 000000004c4f76a6 state to 00000000a23f8f5f
>Oct 25 01:16:10 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:112] for [PLANE:28:plane 1A] state 000000004c4f76a6
>Oct 25 01:16:10 [drm:drm_atomic_check_only [drm]] checking 00000000a23f8f5f
>Oct 25 01:16:10 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 112
>Oct 25 01:16:10 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:10 [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000a23f8f5f nonblocking
>Oct 25 01:16:10 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:10 [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000003b3393c9
>Oct 25 01:16:10 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000003b3393c9
>Oct 25 01:16:10 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000003b3393c9
>Oct 25 01:16:10 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000a23f8f5f
>Oct 25 01:16:10 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000a23f8f5f
>Oct 25 01:16:10 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000003b3393c9
>Oct 25 01:16:10 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000003b3393c9
>Oct 25 01:16:10 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000003b3393c9
>Oct 25 01:16:10 [drm:drm_mode_addfb2 [drm]] [FB:111]
>Oct 25 01:16:10 [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000003b3393c9
>Oct 25 01:16:10 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 000000002fe59080 state to 000000003b3393c9
>Oct 25 01:16:10 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 000000005fbad319 state to 000000003b3393c9
>Oct 25 01:16:10 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:111] for [PLANE:28:plane 1A] state 000000005fbad319
>Oct 25 01:16:10 [drm:drm_atomic_check_only [drm]] checking 000000003b3393c9
>Oct 25 01:16:10 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 111
>Oct 25 01:16:10 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:10 [drm:drm_atomic_nonblocking_commit [drm]] committing 000000003b3393c9 nonblocking
>Oct 25 01:16:10 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:10 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000602b335e
>Oct 25 01:16:10 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000602b335e
>Oct 25 01:16:10 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000602b335e
>Oct 25 01:16:10 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000003b3393c9
>Oct 25 01:16:10 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000003b3393c9
>Oct 25 01:16:10 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000602b335e
>Oct 25 01:16:10 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000602b335e
>Oct 25 01:16:10 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000602b335e
>Oct 25 01:16:10 [drm:drm_mode_addfb2 [drm]] [FB:112]
>Oct 25 01:16:10 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000602b335e
>Oct 25 01:16:10 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 000000001ab56d54 state to 00000000602b335e
>Oct 25 01:16:10 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 0000000005afd297 state to 00000000602b335e
>Oct 25 01:16:10 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:112] for [PLANE:28:plane 1A] state 0000000005afd297
>Oct 25 01:16:10 [drm:drm_atomic_check_only [drm]] checking 00000000602b335e
>Oct 25 01:16:10 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 112
>Oct 25 01:16:10 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:10 [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000602b335e nonblocking
>Oct 25 01:16:10 [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000003b3393c9
>Oct 25 01:16:10 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:10 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000003b3393c9
>Oct 25 01:16:10 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000602b335e
>Oct 25 01:16:10 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000602b335e
>Oct 25 01:16:10 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000003b3393c9
>Oct 25 01:16:10 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000003b3393c9
>Oct 25 01:16:10 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000003b3393c9
>Oct 25 01:16:10 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000003b3393c9
>Oct 25 01:16:10 [drm:drm_mode_addfb2 [drm]] [FB:111]
>Oct 25 01:16:10 [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000003b3393c9
>Oct 25 01:16:10 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 000000001f0d0149 state to 000000003b3393c9
>Oct 25 01:16:10 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000aa094b5a state to 000000003b3393c9
>Oct 25 01:16:10 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:111] for [PLANE:28:plane 1A] state 00000000aa094b5a
>Oct 25 01:16:10 [drm:drm_atomic_check_only [drm]] checking 000000003b3393c9
>Oct 25 01:16:10 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 111
>Oct 25 01:16:10 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:10 [drm:drm_atomic_nonblocking_commit [drm]] committing 000000003b3393c9 nonblocking
>Oct 25 01:16:10 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:10 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000a23f8f5f
>Oct 25 01:16:10 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000a23f8f5f
>Oct 25 01:16:10 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000003b3393c9
>Oct 25 01:16:10 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000003b3393c9
>Oct 25 01:16:10 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000a23f8f5f
>Oct 25 01:16:10 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000a23f8f5f
>Oct 25 01:16:10 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000a23f8f5f
>Oct 25 01:16:10 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000a23f8f5f
>Oct 25 01:16:10 [drm:drm_mode_addfb2 [drm]] [FB:112]
>Oct 25 01:16:10 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000a23f8f5f
>Oct 25 01:16:10 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 000000001eccf585 state to 00000000a23f8f5f
>Oct 25 01:16:10 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000a9ea3eae state to 00000000a23f8f5f
>Oct 25 01:16:10 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:112] for [PLANE:28:plane 1A] state 00000000a9ea3eae
>Oct 25 01:16:10 [drm:drm_atomic_check_only [drm]] checking 00000000a23f8f5f
>Oct 25 01:16:10 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 112
>Oct 25 01:16:10 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:10 [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000a23f8f5f nonblocking
>Oct 25 01:16:10 [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000003b3393c9
>Oct 25 01:16:10 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:10 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000003b3393c9
>Oct 25 01:16:10 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000a23f8f5f
>Oct 25 01:16:10 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000a23f8f5f
>Oct 25 01:16:10 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000003b3393c9
>Oct 25 01:16:10 [drm:drm_mode_addfb2 [drm]] [FB:111]
>Oct 25 01:16:10 [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000003b3393c9
>Oct 25 01:16:10 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 000000001ab56d54 state to 000000003b3393c9
>Oct 25 01:16:10 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 0000000029fac543 state to 000000003b3393c9
>Oct 25 01:16:10 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:111] for [PLANE:28:plane 1A] state 0000000029fac543
>Oct 25 01:16:10 [drm:drm_atomic_check_only [drm]] checking 000000003b3393c9
>Oct 25 01:16:10 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 111
>Oct 25 01:16:10 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:10 [drm:drm_atomic_nonblocking_commit [drm]] committing 000000003b3393c9 nonblocking
>Oct 25 01:16:10 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:10 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000602b335e
>Oct 25 01:16:10 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000602b335e
>Oct 25 01:16:10 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000003b3393c9
>Oct 25 01:16:10 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000003b3393c9
>Oct 25 01:16:10 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000602b335e
>Oct 25 01:16:10 [drm:drm_mode_addfb2 [drm]] [FB:112]
>Oct 25 01:16:10 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000602b335e
>Oct 25 01:16:10 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 000000002fe59080 state to 00000000602b335e
>Oct 25 01:16:10 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000a6afb494 state to 00000000602b335e
>Oct 25 01:16:10 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:112] for [PLANE:28:plane 1A] state 00000000a6afb494
>Oct 25 01:16:10 [drm:drm_atomic_check_only [drm]] checking 00000000602b335e
>Oct 25 01:16:10 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 112
>Oct 25 01:16:10 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:10 [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000602b335e nonblocking
>Oct 25 01:16:10 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:10 [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000003b3393c9
>Oct 25 01:16:10 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000003b3393c9
>Oct 25 01:16:10 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000003b3393c9
>Oct 25 01:16:10 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000003b3393c9
>Oct 25 01:16:10 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000602b335e
>Oct 25 01:16:10 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000602b335e
>Oct 25 01:16:10 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000003b3393c9
>Oct 25 01:16:10 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000003b3393c9
>Oct 25 01:16:10 [drm:drm_mode_addfb2 [drm]] [FB:111]
>Oct 25 01:16:10 [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000003b3393c9
>Oct 25 01:16:10 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 000000001eccf585 state to 000000003b3393c9
>Oct 25 01:16:10 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 000000000794640b state to 000000003b3393c9
>Oct 25 01:16:10 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:111] for [PLANE:28:plane 1A] state 000000000794640b
>Oct 25 01:16:10 [drm:drm_atomic_check_only [drm]] checking 000000003b3393c9
>Oct 25 01:16:10 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 111
>Oct 25 01:16:10 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:10 [drm:drm_atomic_nonblocking_commit [drm]] committing 000000003b3393c9 nonblocking
>Oct 25 01:16:10 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:10 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000003b3393c9
>Oct 25 01:16:10 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000003b3393c9
>Oct 25 01:16:10 [drm:gen8_de_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x11101010, pins 0x00000010, long 0x00000000
>Oct 25 01:16:10 [drm:intel_hpd_irq_handler [i915]] digital hpd port A - short
>Oct 25 01:16:10 [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port A - short
>Oct 25 01:16:10 [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 41 00 00 01 80 02 00 00 00 0f 0b 00
>Oct 25 01:16:10 [drm:drm_mode_addfb2 [drm]] [FB:112]
>Oct 25 01:16:10 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000d3dfc947
>Oct 25 01:16:10 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 000000009b9aab00 state to 00000000d3dfc947
>Oct 25 01:16:10 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 0000000023ecf331 state to 00000000d3dfc947
>Oct 25 01:16:10 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:112] for [PLANE:28:plane 1A] state 0000000023ecf331
>Oct 25 01:16:10 [drm:drm_atomic_check_only [drm]] checking 00000000d3dfc947
>Oct 25 01:16:10 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 112
>Oct 25 01:16:10 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:10 [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000d3dfc947 nonblocking
>Oct 25 01:16:10 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:10 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000d3dfc947
>Oct 25 01:16:10 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000a23f8f5f
>Oct 25 01:16:10 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000a23f8f5f
>Oct 25 01:16:10 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000d3dfc947
>Oct 25 01:16:10 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000a23f8f5f
>Oct 25 01:16:10 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000a23f8f5f
>Oct 25 01:16:10 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000a23f8f5f
>Oct 25 01:16:10 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000a23f8f5f
>Oct 25 01:16:11 [drm:gen8_de_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x11101010, pins 0x00000010, long 0x00000000
>Oct 25 01:16:11 [drm:intel_hpd_irq_handler [i915]] digital hpd port A - short
>Oct 25 01:16:11 [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port A - short
>Oct 25 01:16:11 [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 41 00 00 01 80 02 00 00 00 0f 0b 00
>Oct 25 01:16:11 [drm:drm_mode_addfb2 [drm]] [FB:111]
>Oct 25 01:16:11 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000d3dfc947
>Oct 25 01:16:11 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 0000000043b006de state to 00000000d3dfc947
>Oct 25 01:16:11 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 000000006f66a135 state to 00000000d3dfc947
>Oct 25 01:16:11 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:111] for [PLANE:28:plane 1A] state 000000006f66a135
>Oct 25 01:16:11 [drm:drm_atomic_check_only [drm]] checking 00000000d3dfc947
>Oct 25 01:16:11 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 111
>Oct 25 01:16:11 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:11 [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000d3dfc947 nonblocking
>Oct 25 01:16:11 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:11 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000d3dfc947
>Oct 25 01:16:11 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000d3dfc947
>Oct 25 01:16:11 [drm:drm_mode_addfb2 [drm]] [FB:112]
>Oct 25 01:16:11 [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000080edc7c0
>Oct 25 01:16:11 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 0000000093deb6b7 state to 0000000080edc7c0
>Oct 25 01:16:11 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000ea7039a6 state to 0000000080edc7c0
>Oct 25 01:16:11 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:112] for [PLANE:28:plane 1A] state 00000000ea7039a6
>Oct 25 01:16:11 [drm:drm_atomic_check_only [drm]] checking 0000000080edc7c0
>Oct 25 01:16:11 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 112
>Oct 25 01:16:11 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:11 [drm:drm_atomic_nonblocking_commit [drm]] committing 0000000080edc7c0 nonblocking
>Oct 25 01:16:11 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:11 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000080edc7c0
>Oct 25 01:16:11 [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000009041c25c
>Oct 25 01:16:11 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000080edc7c0
>Oct 25 01:16:11 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000009041c25c
>Oct 25 01:16:11 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000009041c25c
>Oct 25 01:16:11 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000009041c25c
>Oct 25 01:16:11 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000009041c25c
>Oct 25 01:16:11 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000009041c25c
>Oct 25 01:16:11 [drm:gen8_de_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x11101010, pins 0x00000010, long 0x00000000
>Oct 25 01:16:11 [drm:intel_hpd_irq_handler [i915]] digital hpd port A - short
>Oct 25 01:16:11 [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port A - short
>Oct 25 01:16:11 [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 41 00 00 01 80 02 00 00 00 0f 0b 00
>Oct 25 01:16:11 [drm:drm_mode_addfb2 [drm]] [FB:111]
>Oct 25 01:16:11 [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000009041c25c
>Oct 25 01:16:11 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000b5a21653 state to 000000009041c25c
>Oct 25 01:16:11 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000087410c8 state to 000000009041c25c
>Oct 25 01:16:11 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:111] for [PLANE:28:plane 1A] state 00000000087410c8
>Oct 25 01:16:11 [drm:drm_atomic_check_only [drm]] checking 000000009041c25c
>Oct 25 01:16:11 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 111
>Oct 25 01:16:11 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:11 [drm:drm_atomic_nonblocking_commit [drm]] committing 000000009041c25c nonblocking
>Oct 25 01:16:11 [drm:intel_dp_aux_xfer [i915]] Forbidden recv_bytes = 0 on aux transaction
>Oct 25 01:16:11 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:11 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000009041c25c
>Oct 25 01:16:11 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000009041c25c
>Oct 25 01:16:11 [drm:drm_mode_addfb2 [drm]] [FB:112]
>Oct 25 01:16:11 [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000080edc7c0
>Oct 25 01:16:11 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 0000000043b006de state to 0000000080edc7c0
>Oct 25 01:16:11 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000fde2e3b0 state to 0000000080edc7c0
>Oct 25 01:16:11 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:112] for [PLANE:28:plane 1A] state 00000000fde2e3b0
>Oct 25 01:16:11 [drm:drm_atomic_check_only [drm]] checking 0000000080edc7c0
>Oct 25 01:16:11 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 112
>Oct 25 01:16:11 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:11 [drm:drm_atomic_nonblocking_commit [drm]] committing 0000000080edc7c0 nonblocking
>Oct 25 01:16:11 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:11 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000080edc7c0
>Oct 25 01:16:11 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000d3dfc947
>Oct 25 01:16:11 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000080edc7c0
>Oct 25 01:16:11 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000d3dfc947
>Oct 25 01:16:11 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000d3dfc947
>Oct 25 01:16:11 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000d3dfc947
>Oct 25 01:16:11 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000d3dfc947
>Oct 25 01:16:11 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000d3dfc947
>Oct 25 01:16:11 [drm:drm_mode_addfb2 [drm]] [FB:111]
>Oct 25 01:16:11 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000d3dfc947
>Oct 25 01:16:11 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 000000009b9aab00 state to 00000000d3dfc947
>Oct 25 01:16:11 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000811ed0bd state to 00000000d3dfc947
>Oct 25 01:16:11 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:111] for [PLANE:28:plane 1A] state 00000000811ed0bd
>Oct 25 01:16:11 [drm:drm_atomic_check_only [drm]] checking 00000000d3dfc947
>Oct 25 01:16:11 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 111
>Oct 25 01:16:11 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:11 [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000d3dfc947 nonblocking
>Oct 25 01:16:11 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:11 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000052b2c0d
>Oct 25 01:16:11 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000d3dfc947
>Oct 25 01:16:11 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000d3dfc947
>Oct 25 01:16:11 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000052b2c0d
>Oct 25 01:16:11 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000052b2c0d
>Oct 25 01:16:11 [drm:drm_mode_addfb2 [drm]] [FB:112]
>Oct 25 01:16:11 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000052b2c0d
>Oct 25 01:16:11 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000d3dfc947 state to 00000000052b2c0d
>Oct 25 01:16:11 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000ca33d97c state to 00000000052b2c0d
>Oct 25 01:16:11 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:112] for [PLANE:28:plane 1A] state 00000000ca33d97c
>Oct 25 01:16:11 [drm:drm_atomic_check_only [drm]] checking 00000000052b2c0d
>Oct 25 01:16:11 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 112
>Oct 25 01:16:11 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:11 [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000052b2c0d nonblocking
>Oct 25 01:16:11 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:11 [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000043b006de
>Oct 25 01:16:11 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000052b2c0d
>Oct 25 01:16:11 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000052b2c0d
>Oct 25 01:16:11 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000043b006de
>Oct 25 01:16:11 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000043b006de
>Oct 25 01:16:11 [drm:drm_mode_addfb2 [drm]] [FB:111]
>Oct 25 01:16:11 [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000074ccde13
>Oct 25 01:16:11 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 0000000052044b10 state to 0000000074ccde13
>Oct 25 01:16:11 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 000000008fc3b409 state to 0000000074ccde13
>Oct 25 01:16:11 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:111] for [PLANE:28:plane 1A] state 000000008fc3b409
>Oct 25 01:16:11 [drm:drm_atomic_check_only [drm]] checking 0000000074ccde13
>Oct 25 01:16:11 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 111
>Oct 25 01:16:11 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:11 [drm:drm_atomic_nonblocking_commit [drm]] committing 0000000074ccde13 nonblocking
>Oct 25 01:16:11 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:11 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000074ccde13
>Oct 25 01:16:11 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000074ccde13
>Oct 25 01:16:12 [drm:drm_mode_addfb2 [drm]] [FB:112]
>Oct 25 01:16:12 [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000002b2f160e
>Oct 25 01:16:12 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 000000003ad357d3 state to 000000002b2f160e
>Oct 25 01:16:12 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000a68ebe01 state to 000000002b2f160e
>Oct 25 01:16:12 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:112] for [PLANE:28:plane 1A] state 00000000a68ebe01
>Oct 25 01:16:12 [drm:drm_atomic_check_only [drm]] checking 000000002b2f160e
>Oct 25 01:16:12 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 112
>Oct 25 01:16:12 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:12 [drm:drm_atomic_nonblocking_commit [drm]] committing 000000002b2f160e nonblocking
>Oct 25 01:16:12 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:12 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000002b2f160e
>Oct 25 01:16:12 [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000001fc0d337
>Oct 25 01:16:12 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000001fc0d337
>Oct 25 01:16:12 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000001fc0d337
>Oct 25 01:16:12 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000002b2f160e
>Oct 25 01:16:12 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000001fc0d337
>Oct 25 01:16:12 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000001fc0d337
>Oct 25 01:16:12 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000001fc0d337
>Oct 25 01:16:12 [drm:gen8_de_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x11101010, pins 0x00000010, long 0x00000000
>Oct 25 01:16:12 [drm:intel_hpd_irq_handler [i915]] digital hpd port A - short
>Oct 25 01:16:12 [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port A - short
>Oct 25 01:16:12 [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 41 00 00 01 80 02 00 00 00 0f 0b 00
>Oct 25 01:16:13 IPv6: ADDRCONF(NETDEV_CHANGE): wlp0s20f0u5: link becomes ready
>Oct 25 01:16:14 [drm:drm_mode_addfb2 [drm]] [FB:111]
>Oct 25 01:16:14 [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000052044b10
>Oct 25 01:16:14 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 0000000074ccde13 state to 0000000052044b10
>Oct 25 01:16:14 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 0000000062c89365 state to 0000000052044b10
>Oct 25 01:16:14 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:111] for [PLANE:28:plane 1A] state 0000000062c89365
>Oct 25 01:16:14 [drm:drm_atomic_check_only [drm]] checking 0000000052044b10
>Oct 25 01:16:14 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 111
>Oct 25 01:16:14 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:14 [drm:drm_atomic_nonblocking_commit [drm]] committing 0000000052044b10 nonblocking
>Oct 25 01:16:14 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:14 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000e1ec5aa4
>Oct 25 01:16:14 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000e1ec5aa4
>Oct 25 01:16:14 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000e1ec5aa4
>Oct 25 01:16:14 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000052044b10
>Oct 25 01:16:14 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000052044b10
>Oct 25 01:16:14 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000e1ec5aa4
>Oct 25 01:16:14 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000e1ec5aa4
>Oct 25 01:16:14 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000e1ec5aa4
>Oct 25 01:16:14 [drm:drm_mode_addfb2 [drm]] [FB:112]
>Oct 25 01:16:14 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000e1ec5aa4
>Oct 25 01:16:14 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 000000007245a5bd state to 00000000e1ec5aa4
>Oct 25 01:16:14 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000d096858d state to 00000000e1ec5aa4
>Oct 25 01:16:14 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:112] for [PLANE:28:plane 1A] state 00000000d096858d
>Oct 25 01:16:14 [drm:drm_atomic_check_only [drm]] checking 00000000e1ec5aa4
>Oct 25 01:16:14 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 112
>Oct 25 01:16:14 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:14 [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000e1ec5aa4 nonblocking
>Oct 25 01:16:14 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:14 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000e1ec5aa4
>Oct 25 01:16:14 [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000009d4a3bf4
>Oct 25 01:16:14 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000e1ec5aa4
>Oct 25 01:16:14 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000009d4a3bf4
>Oct 25 01:16:14 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000009d4a3bf4
>Oct 25 01:16:14 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000009d4a3bf4
>Oct 25 01:16:14 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000009d4a3bf4
>Oct 25 01:16:14 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000009d4a3bf4
>Oct 25 01:16:14 [drm:drm_mode_addfb2 [drm]] [FB:111]
>Oct 25 01:16:14 [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000009041c25c
>Oct 25 01:16:14 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000b5a21653 state to 000000009041c25c
>Oct 25 01:16:14 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000c8aee5c6 state to 000000009041c25c
>Oct 25 01:16:14 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:111] for [PLANE:28:plane 1A] state 00000000c8aee5c6
>Oct 25 01:16:14 [drm:drm_atomic_check_only [drm]] checking 000000009041c25c
>Oct 25 01:16:14 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 111
>Oct 25 01:16:14 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:14 [drm:drm_atomic_nonblocking_commit [drm]] committing 000000009041c25c nonblocking
>Oct 25 01:16:14 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:14 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000009041c25c
>Oct 25 01:16:14 [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000043b006de
>Oct 25 01:16:14 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000043b006de
>Oct 25 01:16:14 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000009041c25c
>Oct 25 01:16:14 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000043b006de
>Oct 25 01:16:14 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000043b006de
>Oct 25 01:16:14 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000043b006de
>Oct 25 01:16:14 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000043b006de
>Oct 25 01:16:14 [drm:drm_mode_addfb2 [drm]] [FB:112]
>Oct 25 01:16:14 [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000043b006de
>Oct 25 01:16:14 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000cafbdc02 state to 0000000043b006de
>Oct 25 01:16:14 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000f50a22c9 state to 0000000043b006de
>Oct 25 01:16:14 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:112] for [PLANE:28:plane 1A] state 00000000f50a22c9
>Oct 25 01:16:14 [drm:drm_atomic_check_only [drm]] checking 0000000043b006de
>Oct 25 01:16:14 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 112
>Oct 25 01:16:14 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:14 [drm:drm_atomic_nonblocking_commit [drm]] committing 0000000043b006de nonblocking
>Oct 25 01:16:14 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:14 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000043b006de
>Oct 25 01:16:14 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000043b006de
>Oct 25 01:16:14 [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000004bb00d2c
>Oct 25 01:16:14 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000004bb00d2c
>Oct 25 01:16:14 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000004bb00d2c
>Oct 25 01:16:14 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000004bb00d2c
>Oct 25 01:16:14 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000004bb00d2c
>Oct 25 01:16:14 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000004bb00d2c
>Oct 25 01:16:14 [drm:drm_mode_addfb2 [drm]] [FB:111]
>Oct 25 01:16:14 [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000004bb00d2c
>Oct 25 01:16:14 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000e0a66b26 state to 000000004bb00d2c
>Oct 25 01:16:14 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000fca9ccda state to 000000004bb00d2c
>Oct 25 01:16:14 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:111] for [PLANE:28:plane 1A] state 00000000fca9ccda
>Oct 25 01:16:14 [drm:drm_atomic_check_only [drm]] checking 000000004bb00d2c
>Oct 25 01:16:14 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 111
>Oct 25 01:16:14 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:14 [drm:drm_atomic_nonblocking_commit [drm]] committing 000000004bb00d2c nonblocking
>Oct 25 01:16:14 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:14 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000004bb00d2c
>Oct 25 01:16:14 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000004bb00d2c
>Oct 25 01:16:14 [drm:drm_mode_addfb2 [drm]] [FB:112]
>Oct 25 01:16:14 [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000007d6e1cbe
>Oct 25 01:16:14 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 000000005618b448 state to 000000007d6e1cbe
>Oct 25 01:16:14 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000e430db89 state to 000000007d6e1cbe
>Oct 25 01:16:14 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:112] for [PLANE:28:plane 1A] state 00000000e430db89
>Oct 25 01:16:14 [drm:drm_atomic_check_only [drm]] checking 000000007d6e1cbe
>Oct 25 01:16:14 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 112
>Oct 25 01:16:14 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:14 [drm:drm_atomic_nonblocking_commit [drm]] committing 000000007d6e1cbe nonblocking
>Oct 25 01:16:14 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:14 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000007d6e1cbe
>Oct 25 01:16:14 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000d3dfc947
>Oct 25 01:16:14 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000007d6e1cbe
>Oct 25 01:16:14 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000d3dfc947
>Oct 25 01:16:14 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000d3dfc947
>Oct 25 01:16:14 [drm:drm_mode_addfb2 [drm]] [FB:111]
>Oct 25 01:16:14 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000d3dfc947
>Oct 25 01:16:14 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000052b2c0d state to 00000000d3dfc947
>Oct 25 01:16:14 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000835ed397 state to 00000000d3dfc947
>Oct 25 01:16:14 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:111] for [PLANE:28:plane 1A] state 00000000835ed397
>Oct 25 01:16:14 [drm:drm_atomic_check_only [drm]] checking 00000000d3dfc947
>Oct 25 01:16:14 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 111
>Oct 25 01:16:14 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:14 [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000d3dfc947 nonblocking
>Oct 25 01:16:14 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:14 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000d3dfc947
>Oct 25 01:16:14 [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000009b9aab00
>Oct 25 01:16:14 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000009b9aab00
>Oct 25 01:16:14 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000d3dfc947
>Oct 25 01:16:14 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000009b9aab00
>Oct 25 01:16:14 [drm:drm_mode_addfb2 [drm]] [FB:112]
>Oct 25 01:16:14 [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000009b9aab00
>Oct 25 01:16:14 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000d3dfc947 state to 000000009b9aab00
>Oct 25 01:16:14 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000beb39792 state to 000000009b9aab00
>Oct 25 01:16:14 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:112] for [PLANE:28:plane 1A] state 00000000beb39792
>Oct 25 01:16:14 [drm:drm_atomic_check_only [drm]] checking 000000009b9aab00
>Oct 25 01:16:14 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 112
>Oct 25 01:16:14 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:14 [drm:drm_atomic_nonblocking_commit [drm]] committing 000000009b9aab00 nonblocking
>Oct 25 01:16:14 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:14 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000009b9aab00
>Oct 25 01:16:14 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000009b9aab00
>Oct 25 01:16:14 [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000005618b448
>Oct 25 01:16:14 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000005618b448
>Oct 25 01:16:14 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000005618b448
>Oct 25 01:16:14 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000005618b448
>Oct 25 01:16:14 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000005618b448
>Oct 25 01:16:14 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000005618b448
>Oct 25 01:16:14 [drm:drm_mode_addfb2 [drm]] [FB:111]
>Oct 25 01:16:14 [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000005618b448
>Oct 25 01:16:14 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 000000007d6e1cbe state to 000000005618b448
>Oct 25 01:16:14 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 000000004443d82c state to 000000005618b448
>Oct 25 01:16:14 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:111] for [PLANE:28:plane 1A] state 000000004443d82c
>Oct 25 01:16:14 [drm:drm_atomic_check_only [drm]] checking 000000005618b448
>Oct 25 01:16:14 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 111
>Oct 25 01:16:14 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:14 [drm:drm_atomic_nonblocking_commit [drm]] committing 000000005618b448 nonblocking
>Oct 25 01:16:14 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:14 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000005618b448
>Oct 25 01:16:14 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000005618b448
>Oct 25 01:16:14 [drm:drm_mode_addfb2 [drm]] [FB:112]
>Oct 25 01:16:14 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000e0a66b26
>Oct 25 01:16:14 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 000000004bb00d2c state to 00000000e0a66b26
>Oct 25 01:16:14 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 000000008b4848ae state to 00000000e0a66b26
>Oct 25 01:16:14 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:112] for [PLANE:28:plane 1A] state 000000008b4848ae
>Oct 25 01:16:14 [drm:drm_atomic_check_only [drm]] checking 00000000e0a66b26
>Oct 25 01:16:14 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 112
>Oct 25 01:16:14 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:14 [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000e0a66b26 nonblocking
>Oct 25 01:16:14 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:14 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000e0a66b26
>Oct 25 01:16:14 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000e0a66b26
>Oct 25 01:16:14 [drm:drm_mode_addfb2 [drm]] [FB:111]
>Oct 25 01:16:14 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000cafbdc02
>Oct 25 01:16:14 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 0000000043b006de state to 00000000cafbdc02
>Oct 25 01:16:14 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000ee8ff057 state to 00000000cafbdc02
>Oct 25 01:16:14 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:111] for [PLANE:28:plane 1A] state 00000000ee8ff057
>Oct 25 01:16:14 [drm:drm_atomic_check_only [drm]] checking 00000000cafbdc02
>Oct 25 01:16:14 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 111
>Oct 25 01:16:14 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:14 [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000cafbdc02 nonblocking
>Oct 25 01:16:14 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:14 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000cafbdc02
>Oct 25 01:16:14 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000b5a21653
>Oct 25 01:16:14 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000b5a21653
>Oct 25 01:16:14 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000b5a21653
>Oct 25 01:16:14 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000cafbdc02
>Oct 25 01:16:14 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000b5a21653
>Oct 25 01:16:14 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000b5a21653
>Oct 25 01:16:14 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000b5a21653
>Oct 25 01:16:14 [drm:drm_mode_addfb2 [drm]] [FB:112]
>Oct 25 01:16:14 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000b5a21653
>Oct 25 01:16:14 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 000000009041c25c state to 00000000b5a21653
>Oct 25 01:16:14 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000110861ee state to 00000000b5a21653
>Oct 25 01:16:14 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:112] for [PLANE:28:plane 1A] state 00000000110861ee
>Oct 25 01:16:14 [drm:drm_atomic_check_only [drm]] checking 00000000b5a21653
>Oct 25 01:16:14 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 112
>Oct 25 01:16:14 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:14 [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000b5a21653 nonblocking
>Oct 25 01:16:14 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:14 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000b5a21653
>Oct 25 01:16:14 [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000080edc7c0
>Oct 25 01:16:14 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000b5a21653
>Oct 25 01:16:14 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000080edc7c0
>Oct 25 01:16:14 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000080edc7c0
>Oct 25 01:16:14 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000080edc7c0
>Oct 25 01:16:14 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000080edc7c0
>Oct 25 01:16:14 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000080edc7c0
>Oct 25 01:16:14 [drm:drm_mode_addfb2 [drm]] [FB:111]
>Oct 25 01:16:14 [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000080edc7c0
>Oct 25 01:16:14 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000b5a21653 state to 0000000080edc7c0
>Oct 25 01:16:14 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000d10a60f6 state to 0000000080edc7c0
>Oct 25 01:16:14 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:111] for [PLANE:28:plane 1A] state 00000000d10a60f6
>Oct 25 01:16:14 [drm:drm_atomic_check_only [drm]] checking 0000000080edc7c0
>Oct 25 01:16:14 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 111
>Oct 25 01:16:14 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:14 [drm:drm_atomic_nonblocking_commit [drm]] committing 0000000080edc7c0 nonblocking
>Oct 25 01:16:14 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:14 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000080edc7c0
>Oct 25 01:16:14 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000080edc7c0
>Oct 25 01:16:14 [drm:drm_mode_addfb2 [drm]] [FB:112]
>Oct 25 01:16:14 [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000043b006de
>Oct 25 01:16:14 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000cafbdc02 state to 0000000043b006de
>Oct 25 01:16:14 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000832c83f4 state to 0000000043b006de
>Oct 25 01:16:14 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:112] for [PLANE:28:plane 1A] state 00000000832c83f4
>Oct 25 01:16:14 [drm:drm_atomic_check_only [drm]] checking 0000000043b006de
>Oct 25 01:16:14 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 112
>Oct 25 01:16:14 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:14 [drm:drm_atomic_nonblocking_commit [drm]] committing 0000000043b006de nonblocking
>Oct 25 01:16:14 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:14 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000043b006de
>Oct 25 01:16:14 [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000004bb00d2c
>Oct 25 01:16:14 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000004bb00d2c
>Oct 25 01:16:14 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000043b006de
>Oct 25 01:16:14 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000004bb00d2c
>Oct 25 01:16:14 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000004bb00d2c
>Oct 25 01:16:14 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000004bb00d2c
>Oct 25 01:16:14 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000004bb00d2c
>Oct 25 01:16:14 [drm:drm_mode_addfb2 [drm]] [FB:111]
>Oct 25 01:16:14 [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000004bb00d2c
>Oct 25 01:16:14 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000e0a66b26 state to 000000004bb00d2c
>Oct 25 01:16:14 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 000000001b7bc524 state to 000000004bb00d2c
>Oct 25 01:16:14 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:111] for [PLANE:28:plane 1A] state 000000001b7bc524
>Oct 25 01:16:14 [drm:drm_atomic_check_only [drm]] checking 000000004bb00d2c
>Oct 25 01:16:14 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 111
>Oct 25 01:16:14 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:14 [drm:drm_atomic_nonblocking_commit [drm]] committing 000000004bb00d2c nonblocking
>Oct 25 01:16:14 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:14 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000004bb00d2c
>Oct 25 01:16:14 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000004bb00d2c
>Oct 25 01:16:14 [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000007d6e1cbe
>Oct 25 01:16:14 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000007d6e1cbe
>Oct 25 01:16:14 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000007d6e1cbe
>Oct 25 01:16:14 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000007d6e1cbe
>Oct 25 01:16:14 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000007d6e1cbe
>Oct 25 01:16:14 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000007d6e1cbe
>Oct 25 01:16:14 [drm:drm_mode_addfb2 [drm]] [FB:112]
>Oct 25 01:16:14 [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000007d6e1cbe
>Oct 25 01:16:14 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 000000005618b448 state to 000000007d6e1cbe
>Oct 25 01:16:14 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 0000000031c2ac15 state to 000000007d6e1cbe
>Oct 25 01:16:14 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:112] for [PLANE:28:plane 1A] state 0000000031c2ac15
>Oct 25 01:16:14 [drm:drm_atomic_check_only [drm]] checking 000000007d6e1cbe
>Oct 25 01:16:14 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 112
>Oct 25 01:16:14 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:14 [drm:drm_atomic_nonblocking_commit [drm]] committing 000000007d6e1cbe nonblocking
>Oct 25 01:16:14 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:14 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000007d6e1cbe
>Oct 25 01:16:14 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000d3dfc947
>Oct 25 01:16:14 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000d3dfc947
>Oct 25 01:16:14 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000007d6e1cbe
>Oct 25 01:16:14 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000d3dfc947
>Oct 25 01:16:14 [drm:gen8_de_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x11101010, pins 0x00000010, long 0x00000000
>Oct 25 01:16:14 [drm:intel_hpd_irq_handler [i915]] digital hpd port A - short
>Oct 25 01:16:14 [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port A - short
>Oct 25 01:16:14 [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 41 00 00 01 80 02 00 00 00 0f 0b 00
>Oct 25 01:16:14 [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:83:eDP-1]
>Oct 25 01:16:14 [drm:intel_dp_detect [i915]] [CONNECTOR:83:eDP-1]
>Oct 25 01:16:14 [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>Oct 25 01:16:14 [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>Oct 25 01:16:14 [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>Oct 25 01:16:14 [drm:drm_dp_read_desc [drm_kms_helper]] DP sink: OUI 00-10-fa dev-ID eD\025eaa HW-rev 1.0 SW-rev 2.15 quirks 0x0000
>Oct 25 01:16:14 [drm:intel_dp_detect [i915]] MST support? port A: no, sink: no, modparam: yes
>Oct 25 01:16:14 [drm:drm_add_display_info [drm]] non_desktop set to 0
>Oct 25 01:16:14 [drm:drm_add_edid_modes [drm]] ELD: no CEA Extension found
>Oct 25 01:16:14 [drm:drm_add_display_info [drm]] non_desktop set to 0
>Oct 25 01:16:14 [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:83:eDP-1] probed modes :
>Oct 25 01:16:14 [drm:drm_mode_debug_printmodeline [drm]] Modeline 84:"2880x1800" 60 328920 2880 2888 2920 2960 1800 1838 1846 1852 0x48 0x9
>Oct 25 01:16:14 [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:90:DP-1]
>Oct 25 01:16:14 [drm:intel_dp_detect [i915]] [CONNECTOR:90:DP-1]
>Oct 25 01:16:14 [drm:intel_power_well_enable [i915]] enabling power well 2
>Oct 25 01:16:14 [drm:intel_power_well_disable [i915]] disabling power well 2
>Oct 25 01:16:14 [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:90:DP-1] disconnected
>Oct 25 01:16:14 [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:96:HDMI-A-1]
>Oct 25 01:16:14 [drm:intel_hdmi_detect [i915]] [CONNECTOR:96:HDMI-A-1]
>Oct 25 01:16:14 [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] timed out, falling back to bit banging on pin 4
>Oct 25 01:16:14 [drm:drm_do_probe_ddc_edid [drm]] drm: skipping non-existent adapter i915 gmbus dpc
>Oct 25 01:16:14 [drm:intel_hdmi_set_edid [i915]] HDMI GMBUS EDID read failed, retry using GPIO bit-banging
>Oct 25 01:16:14 [drm:intel_gmbus_force_bit [i915]] enabling bit-banging on i915 gmbus dpc. force bit now 1
>Oct 25 01:16:14 [drm:drm_do_probe_ddc_edid [drm]] drm: skipping non-existent adapter i915 gmbus dpc
>Oct 25 01:16:14 [drm:intel_gmbus_force_bit [i915]] disabling bit-banging on i915 gmbus dpc. force bit now 0
>Oct 25 01:16:14 [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] timed out, falling back to bit banging on pin 4
>Oct 25 01:16:14 [drm:drm_dp_dual_mode_detect [drm_kms_helper]] DP dual mode HDMI ID:  (err -6)
>Oct 25 01:16:14 [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:96:HDMI-A-1] disconnected
>Oct 25 01:16:14 [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:101:DP-2]
>Oct 25 01:16:14 [drm:intel_dp_detect [i915]] [CONNECTOR:101:DP-2]
>Oct 25 01:16:14 [drm:intel_power_well_enable [i915]] enabling power well 2
>Oct 25 01:16:14 [drm:intel_power_well_disable [i915]] disabling power well 2
>Oct 25 01:16:14 [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:101:DP-2] disconnected
>Oct 25 01:16:14 [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:106:HDMI-A-2]
>Oct 25 01:16:14 [drm:intel_hdmi_detect [i915]] [CONNECTOR:106:HDMI-A-2]
>Oct 25 01:16:14 [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] timed out, falling back to bit banging on pin 6
>Oct 25 01:16:14 [drm:drm_do_probe_ddc_edid [drm]] drm: skipping non-existent adapter i915 gmbus dpd
>Oct 25 01:16:14 [drm:intel_hdmi_set_edid [i915]] HDMI GMBUS EDID read failed, retry using GPIO bit-banging
>Oct 25 01:16:14 [drm:intel_gmbus_force_bit [i915]] enabling bit-banging on i915 gmbus dpd. force bit now 1
>Oct 25 01:16:14 [drm:drm_do_probe_ddc_edid [drm]] drm: skipping non-existent adapter i915 gmbus dpd
>Oct 25 01:16:14 [drm:intel_gmbus_force_bit [i915]] disabling bit-banging on i915 gmbus dpd. force bit now 0
>Oct 25 01:16:14 [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] timed out, falling back to bit banging on pin 6
>Oct 25 01:16:14 [drm:drm_dp_dual_mode_detect [drm_kms_helper]] DP dual mode HDMI ID:  (err -6)
>Oct 25 01:16:14 [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:106:HDMI-A-2] disconnected
>Oct 25 01:16:15 [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:83:eDP-1]
>Oct 25 01:16:15 [drm:intel_dp_detect [i915]] [CONNECTOR:83:eDP-1]
>Oct 25 01:16:15 [drm:intel_dp_print_rates [i915]] source rates: 162000, 216000, 270000, 324000, 432000, 540000
>Oct 25 01:16:15 [drm:intel_dp_print_rates [i915]] sink rates: 162000, 270000
>Oct 25 01:16:15 [drm:intel_dp_print_rates [i915]] common rates: 162000, 270000
>Oct 25 01:16:15 [drm:drm_dp_read_desc [drm_kms_helper]] DP sink: OUI 00-10-fa dev-ID eD\025eaa HW-rev 1.0 SW-rev 2.15 quirks 0x0000
>Oct 25 01:16:15 [drm:intel_dp_detect [i915]] MST support? port A: no, sink: no, modparam: yes
>Oct 25 01:16:15 [drm:drm_add_display_info [drm]] non_desktop set to 0
>Oct 25 01:16:15 [drm:drm_add_edid_modes [drm]] ELD: no CEA Extension found
>Oct 25 01:16:15 [drm:drm_add_display_info [drm]] non_desktop set to 0
>Oct 25 01:16:15 [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:83:eDP-1] probed modes :
>Oct 25 01:16:15 [drm:drm_mode_debug_printmodeline [drm]] Modeline 84:"2880x1800" 60 328920 2880 2888 2920 2960 1800 1838 1846 1852 0x48 0x9
>Oct 25 01:16:15 [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:90:DP-1]
>Oct 25 01:16:15 [drm:intel_dp_detect [i915]] [CONNECTOR:90:DP-1]
>Oct 25 01:16:15 [drm:intel_power_well_enable [i915]] enabling power well 2
>Oct 25 01:16:15 [drm:intel_power_well_disable [i915]] disabling power well 2
>Oct 25 01:16:15 [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:90:DP-1] disconnected
>Oct 25 01:16:15 [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:96:HDMI-A-1]
>Oct 25 01:16:15 [drm:intel_hdmi_detect [i915]] [CONNECTOR:96:HDMI-A-1]
>Oct 25 01:16:15 fuse init (API version 7.27)
>Oct 25 01:16:15 [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] timed out, falling back to bit banging on pin 4
>Oct 25 01:16:15 [drm:drm_do_probe_ddc_edid [drm]] drm: skipping non-existent adapter i915 gmbus dpc
>Oct 25 01:16:15 [drm:intel_hdmi_set_edid [i915]] HDMI GMBUS EDID read failed, retry using GPIO bit-banging
>Oct 25 01:16:15 [drm:intel_gmbus_force_bit [i915]] enabling bit-banging on i915 gmbus dpc. force bit now 1
>Oct 25 01:16:15 [drm:drm_do_probe_ddc_edid [drm]] drm: skipping non-existent adapter i915 gmbus dpc
>Oct 25 01:16:15 [drm:intel_gmbus_force_bit [i915]] disabling bit-banging on i915 gmbus dpc. force bit now 0
>Oct 25 01:16:15 [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpc] timed out, falling back to bit banging on pin 4
>Oct 25 01:16:15 [drm:drm_dp_dual_mode_detect [drm_kms_helper]] DP dual mode HDMI ID:  (err -6)
>Oct 25 01:16:15 [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:96:HDMI-A-1] disconnected
>Oct 25 01:16:15 [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:101:DP-2]
>Oct 25 01:16:15 [drm:intel_dp_detect [i915]] [CONNECTOR:101:DP-2]
>Oct 25 01:16:15 [drm:intel_power_well_enable [i915]] enabling power well 2
>Oct 25 01:16:15 [drm:intel_power_well_disable [i915]] disabling power well 2
>Oct 25 01:16:15 [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:101:DP-2] disconnected
>Oct 25 01:16:15 [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:106:HDMI-A-2]
>Oct 25 01:16:15 [drm:intel_hdmi_detect [i915]] [CONNECTOR:106:HDMI-A-2]
>Oct 25 01:16:15 [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] timed out, falling back to bit banging on pin 6
>Oct 25 01:16:15 [drm:drm_do_probe_ddc_edid [drm]] drm: skipping non-existent adapter i915 gmbus dpd
>Oct 25 01:16:15 [drm:intel_hdmi_set_edid [i915]] HDMI GMBUS EDID read failed, retry using GPIO bit-banging
>Oct 25 01:16:15 [drm:intel_gmbus_force_bit [i915]] enabling bit-banging on i915 gmbus dpd. force bit now 1
>Oct 25 01:16:15 [drm:drm_do_probe_ddc_edid [drm]] drm: skipping non-existent adapter i915 gmbus dpd
>Oct 25 01:16:15 [drm:intel_gmbus_force_bit [i915]] disabling bit-banging on i915 gmbus dpd. force bit now 0
>Oct 25 01:16:15 [drm:do_gmbus_xfer [i915]] GMBUS [i915 gmbus dpd] timed out, falling back to bit banging on pin 6
>Oct 25 01:16:15 [drm:drm_dp_dual_mode_detect [drm_kms_helper]] DP dual mode HDMI ID:  (err -6)
>Oct 25 01:16:15 [drm:drm_helper_probe_single_connector_modes [drm_kms_helper]] [CONNECTOR:106:HDMI-A-2] disconnected
>Oct 25 01:16:15 [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000009b9aab00
>Oct 25 01:16:15 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000835ed397 state to 000000009b9aab00
>Oct 25 01:16:15 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000052b2c0d state to 000000009b9aab00
>Oct 25 01:16:15 [drm:drm_atomic_check_only [drm]] checking 000000009b9aab00
>Oct 25 01:16:15 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 112
>Oct 25 01:16:15 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:15 [drm:drm_atomic_commit [drm]] committing 000000009b9aab00
>Oct 25 01:16:15 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:15 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:15 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000009b9aab00
>Oct 25 01:16:15 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000009b9aab00
>Oct 25 01:16:15 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000b3ba1f02
>Oct 25 01:16:15 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:42:cursor A] 000000005cf9f815 state to 00000000b3ba1f02
>Oct 25 01:16:15 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 000000005216250d state to 00000000b3ba1f02
>Oct 25 01:16:15 [drm:drm_atomic_set_crtc_for_plane [drm]] Link [PLANE:42:cursor A] state 000000005cf9f815 to [NOCRTC]
>Oct 25 01:16:15 [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:42:cursor A] state 000000005cf9f815
>Oct 25 01:16:15 [drm:drm_atomic_check_only [drm]] checking 00000000b3ba1f02
>Oct 25 01:16:15 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb -1
>Oct 25 01:16:15 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 0, off 1, on 0, ms 0
>Oct 25 01:16:15 [drm:drm_atomic_commit [drm]] committing 00000000b3ba1f02
>Oct 25 01:16:15 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:15 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000b3ba1f02
>Oct 25 01:16:15 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000b3ba1f02
>Oct 25 01:16:15 [drm:gen8_de_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x11101010, pins 0x00000010, long 0x00000000
>Oct 25 01:16:15 [drm:intel_hpd_irq_handler [i915]] digital hpd port A - short
>Oct 25 01:16:15 [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port A - short
>Oct 25 01:16:15 [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 41 00 00 01 80 02 00 00 00 0f 0b 00
>Oct 25 01:16:15 Bluetooth: RFCOMM TTY layer initialized
>Oct 25 01:16:15 Bluetooth: RFCOMM socket layer initialized
>Oct 25 01:16:15 Bluetooth: RFCOMM ver 1.11
>Oct 25 01:16:15 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000b3ba1f02
>Oct 25 01:16:15 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:42:cursor A] 00000000bea42600 state to 00000000b3ba1f02
>Oct 25 01:16:15 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 0000000036015cdc state to 00000000b3ba1f02
>Oct 25 01:16:15 [drm:drm_atomic_set_crtc_for_plane [drm]] Link [PLANE:42:cursor A] state 00000000bea42600 to [CRTC:45:pipe A]
>Oct 25 01:16:15 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:42:cursor A] state 00000000bea42600
>Oct 25 01:16:15 [drm:drm_atomic_check_only [drm]] checking 00000000b3ba1f02
>Oct 25 01:16:15 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 110
>Oct 25 01:16:15 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 0 -> 1, off 0, on 1, ms 0
>Oct 25 01:16:15 [drm:drm_atomic_commit [drm]] committing 00000000b3ba1f02
>Oct 25 01:16:15 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:15 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000b3ba1f02
>Oct 25 01:16:15 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000b3ba1f02
>Oct 25 01:16:15 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:42:cursor A] state 00000000424f4d84
>Oct 25 01:16:15 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 110
>Oct 25 01:16:15 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:15 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:15 [drm:gen8_de_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x11101010, pins 0x00000010, long 0x00000000
>Oct 25 01:16:15 [drm:intel_hpd_irq_handler [i915]] digital hpd port A - short
>Oct 25 01:16:15 [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port A - short
>Oct 25 01:16:15 [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 41 00 00 01 80 02 00 00 00 0f 0b 00
>Oct 25 01:16:16 rfkill: input handler disabled
>Oct 25 01:16:16 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:42:cursor A] state 00000000167f5c94
>Oct 25 01:16:16 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 110
>Oct 25 01:16:16 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:16 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:16 [drm:drm_mode_addfb2 [drm]] [FB:111]
>Oct 25 01:16:16 [drm:drm_mode_setcrtc [drm]] [CRTC:45:pipe A]
>Oct 25 01:16:16 [drm:drm_mode_setcrtc [drm]] [CONNECTOR:83:eDP-1]
>Oct 25 01:16:16 [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000004691ab98
>Oct 25 01:16:16 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000fc7c8f0d state to 000000004691ab98
>Oct 25 01:16:16 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 000000006ae0f1d5 state to 000000004691ab98
>Oct 25 01:16:16 [drm:drm_atomic_set_mode_for_crtc [drm]] Set [MODE:1920x1200_60.00] for [CRTC:45:pipe A] state 00000000fc7c8f0d
>Oct 25 01:16:16 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:111] for [PLANE:28:plane 1A] state 000000006ae0f1d5
>Oct 25 01:16:16 [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:45:pipe A] to 000000004691ab98
>Oct 25 01:16:16 [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:83:eDP-1] 00000000b550f8b8 state to 000000004691ab98
>Oct 25 01:16:16 [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:83:eDP-1] state 00000000b550f8b8 to [NOCRTC]
>Oct 25 01:16:16 [drm:drm_atomic_set_crtc_for_connector [drm]] Link [CONNECTOR:83:eDP-1] state 00000000b550f8b8 to [CRTC:45:pipe A]
>Oct 25 01:16:16 [drm:drm_atomic_check_only [drm]] checking 000000004691ab98
>Oct 25 01:16:16 [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:45:pipe A] mode changed
>Oct 25 01:16:16 [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:83:eDP-1]
>Oct 25 01:16:16 [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:83:eDP-1] keeps [ENCODER:82:DDI A], now on [CRTC:45:pipe A]
>Oct 25 01:16:16 [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CRTC:45:pipe A] needs all connectors, enable: y, active: y
>Oct 25 01:16:16 [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:45:pipe A] to 000000004691ab98
>Oct 25 01:16:16 [drm:drm_atomic_add_affected_planes [drm]] Adding all current planes for [CRTC:45:pipe A] to 000000004691ab98
>Oct 25 01:16:16 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:42:cursor A] 00000000d026dd96 state to 000000004691ab98
>Oct 25 01:16:16 [drm:intel_atomic_check [i915]] [CONNECTOR:83:eDP-1] checking for sink bpp constrains
>Oct 25 01:16:16 [drm:intel_atomic_check [i915]] clamping display bpp (was 36) to EDID reported max of 30
>Oct 25 01:16:16 [drm:skl_update_scaler [i915]] scaler_user index 0.31: staged scaling request for 1920x1200->2880x1800 scaler_users = 0x80000000
>Oct 25 01:16:16 [drm:intel_dp_compute_config [i915]] DP link computation with max lane count 4 max rate 270000 max bpp 30 pixel clock 328920KHz
>Oct 25 01:16:16 [drm:intel_dp_compute_config [i915]] DP lane count 4 clock 270000 bpp 24
>Oct 25 01:16:16 [drm:intel_dp_compute_config [i915]] DP link rate required 986760 available 1080000
>Oct 25 01:16:16 [drm:intel_atomic_check [i915]] hw max bpp: 36, pipe bpp: 24, dithering: 0
>Oct 25 01:16:16 [drm:intel_dump_pipe_config [i915]] [CRTC:45:pipe A][fastset]
>Oct 25 01:16:16 [drm:intel_dump_pipe_config [i915]] output_types: EDP (0x100)
>Oct 25 01:16:16 [drm:intel_dump_pipe_config [i915]] output format: RGB
>Oct 25 01:16:16 [drm:intel_dump_pipe_config [i915]] cpu_transcoder: EDP, pipe bpp: 24, dithering: 0
>Oct 25 01:16:16 [drm:intel_dump_pipe_config [i915]] dp m_n: lanes: 4; gmch_m: 7664391, gmch_n: 8388608, link_m: 638699, link_n: 524288, tu: 64
>Oct 25 01:16:16 [drm:intel_dump_pipe_config [i915]] audio: 0, infoframes: 0
>Oct 25 01:16:16 [drm:intel_dump_pipe_config [i915]] requested mode:
>Oct 25 01:16:16 [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"1920x1200_60.00" 0 193250 1920 2056 2256 2592 1200 1203 1209 1245 0x0 0x6
>Oct 25 01:16:16 [drm:intel_dump_pipe_config [i915]] adjusted mode:
>Oct 25 01:16:16 [drm:drm_mode_debug_printmodeline [drm]] Modeline 0:"2880x1800" 60 328920 2880 2888 2920 2960 1800 1838 1846 1852 0x48 0x9
>Oct 25 01:16:16 [drm:intel_dump_pipe_config [i915]] crtc timings: 328920 2880 2888 2920 2960 1800 1838 1846 1852, type: 0x48 flags: 0x9
>Oct 25 01:16:16 [drm:intel_dump_pipe_config [i915]] port clock: 270000, pipe src size: 1920x1200, pixel rate 328920
>Oct 25 01:16:16 [drm:intel_dump_pipe_config [i915]] num_scalers: 2, scaler_users: 0x80000000, scaler_id: -1
>Oct 25 01:16:16 [drm:intel_dump_pipe_config [i915]] pch pfit: pos: 0x00000000, size: 0x0b400708, enabled
>Oct 25 01:16:16 [drm:intel_dump_pipe_config [i915]] ips: 0, double wide: 0
>Oct 25 01:16:16 [drm:intel_dump_pipe_config [i915]] dpll_hw_state: ctrl1: 0x3, cfgcr1: 0x0, cfgcr2: 0x0
>Oct 25 01:16:16 [drm:intel_dump_pipe_config [i915]] planes on this crtc
>Oct 25 01:16:16 [drm:intel_dump_pipe_config [i915]] [PLANE:28:plane 1A] FB:112, fb = 2880x1800 format = XR24 little-endian (0x34325258)
>Oct 25 01:16:16 [drm:intel_dump_pipe_config [i915]]         scaler:-1 src 0x0+2880+1800 dst 0x0+2880+1800
>Oct 25 01:16:16 [drm:intel_dump_pipe_config [i915]] [PLANE:35:plane 2A] disabled, scaler_id = -1
>Oct 25 01:16:16 [drm:intel_dump_pipe_config [i915]] [PLANE:42:cursor A] FB:110, fb = 256x256 format = AR24 little-endian (0x34325241)
>Oct 25 01:16:16 [drm:intel_dump_pipe_config [i915]]         scaler:-1 src 0x0+256+256 dst 1724x1076+256+256
>Oct 25 01:16:16 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 111
>Oct 25 01:16:16 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:16 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 110
>Oct 25 01:16:16 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:16 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45
>Oct 25 01:16:16 [drm:drm_atomic_commit [drm]] committing 000000004691ab98
>Oct 25 01:16:16 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:16 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:16 [drm:verify_connector_state.isra.132 [i915]] [CONNECTOR:83:eDP-1]
>Oct 25 01:16:16 [drm:intel_atomic_commit_tail [i915]] [CRTC:45:pipe A]
>Oct 25 01:16:16 [drm:verify_single_dpll_state.isra.85 [i915]] DPLL 0
>Oct 25 01:16:16 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000004691ab98
>Oct 25 01:16:16 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000004691ab98
>Oct 25 01:16:16 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000935c3744
>Oct 25 01:16:16 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000217e0795 state to 00000000935c3744
>Oct 25 01:16:16 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000c0372087 state to 00000000935c3744
>Oct 25 01:16:16 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:111] for [PLANE:28:plane 1A] state 00000000c0372087
>Oct 25 01:16:16 [drm:drm_atomic_check_only [drm]] checking 00000000935c3744
>Oct 25 01:16:16 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 111
>Oct 25 01:16:16 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:16 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45
>Oct 25 01:16:16 [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000935c3744 nonblocking
>Oct 25 01:16:16 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:16 [drm:drm_mode_setcrtc [drm]] [CRTC:63:pipe B]
>Oct 25 01:16:16 [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000007245a5bd
>Oct 25 01:16:16 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:63:pipe B] 00000000a371189e state to 000000007245a5bd
>Oct 25 01:16:16 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:46:plane 1B] 000000001317c747 state to 000000007245a5bd
>Oct 25 01:16:16 [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:63:pipe B] state 00000000a371189e
>Oct 25 01:16:16 [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:46:plane 1B] state 000000001317c747
>Oct 25 01:16:16 [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:63:pipe B] to 000000007245a5bd
>Oct 25 01:16:16 [drm:drm_atomic_check_only [drm]] checking 000000007245a5bd
>Oct 25 01:16:16 [drm:drm_atomic_commit [drm]] committing 000000007245a5bd
>Oct 25 01:16:16 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000007245a5bd
>Oct 25 01:16:16 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000007245a5bd
>Oct 25 01:16:16 [drm:drm_mode_setcrtc [drm]] [CRTC:81:pipe C]
>Oct 25 01:16:16 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000b3457264
>Oct 25 01:16:16 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:81:pipe C] 00000000d981a2e7 state to 00000000b3457264
>Oct 25 01:16:16 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:64:plane 1C] 000000007dac08fd state to 00000000b3457264
>Oct 25 01:16:16 [drm:drm_atomic_set_mode_for_crtc [drm]] Set [NOMODE] for [CRTC:81:pipe C] state 00000000d981a2e7
>Oct 25 01:16:16 [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:64:plane 1C] state 000000007dac08fd
>Oct 25 01:16:16 [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:81:pipe C] to 00000000b3457264
>Oct 25 01:16:16 [drm:drm_atomic_check_only [drm]] checking 00000000b3457264
>Oct 25 01:16:16 [drm:drm_atomic_commit [drm]] committing 00000000b3457264
>Oct 25 01:16:16 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000b3457264
>Oct 25 01:16:16 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000b3457264
>Oct 25 01:16:16 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:16 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000935c3744
>Oct 25 01:16:16 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000935c3744
>Oct 25 01:16:16 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:42:cursor A] state 0000000097c7c37c
>Oct 25 01:16:16 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 110
>Oct 25 01:16:16 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:16 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:16 [drm:drm_mode_addfb2 [drm]] [FB:113]
>Oct 25 01:16:16 [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000054d243d6
>Oct 25 01:16:16 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000d3c6ed8a state to 0000000054d243d6
>Oct 25 01:16:16 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 000000008b044653 state to 0000000054d243d6
>Oct 25 01:16:16 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:113] for [PLANE:28:plane 1A] state 000000008b044653
>Oct 25 01:16:16 [drm:drm_atomic_check_only [drm]] checking 0000000054d243d6
>Oct 25 01:16:16 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 113
>Oct 25 01:16:16 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:16 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45
>Oct 25 01:16:16 [drm:drm_atomic_nonblocking_commit [drm]] committing 0000000054d243d6 nonblocking
>Oct 25 01:16:16 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:16 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000054d243d6
>Oct 25 01:16:16 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000054d243d6
>Oct 25 01:16:16 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:42:cursor A] state 00000000c310f03d
>Oct 25 01:16:16 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 110
>Oct 25 01:16:16 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:16 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:17 [drm:drm_mode_addfb2 [drm]] [FB:111]
>Oct 25 01:16:17 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000fac8a01c
>Oct 25 01:16:17 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 0000000054d243d6 state to 00000000fac8a01c
>Oct 25 01:16:17 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 000000009896654e state to 00000000fac8a01c
>Oct 25 01:16:17 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:111] for [PLANE:28:plane 1A] state 000000009896654e
>Oct 25 01:16:17 [drm:drm_atomic_check_only [drm]] checking 00000000fac8a01c
>Oct 25 01:16:17 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 111
>Oct 25 01:16:17 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:17 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45
>Oct 25 01:16:17 [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000fac8a01c nonblocking
>Oct 25 01:16:17 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:17 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000fac8a01c
>Oct 25 01:16:17 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000c5b1d89a
>Oct 25 01:16:17 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000c5b1d89a
>Oct 25 01:16:17 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000c5b1d89a
>Oct 25 01:16:17 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000c5b1d89a
>Oct 25 01:16:17 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000c5b1d89a
>Oct 25 01:16:17 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000c5b1d89a
>Oct 25 01:16:17 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000fac8a01c
>Oct 25 01:16:17 [drm:drm_mode_addfb2 [drm]] [FB:113]
>Oct 25 01:16:17 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000c5b1d89a
>Oct 25 01:16:17 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 0000000067a23d31 state to 00000000c5b1d89a
>Oct 25 01:16:17 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000a0c1150c state to 00000000c5b1d89a
>Oct 25 01:16:17 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:113] for [PLANE:28:plane 1A] state 00000000a0c1150c
>Oct 25 01:16:17 [drm:drm_atomic_check_only [drm]] checking 00000000c5b1d89a
>Oct 25 01:16:17 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 113
>Oct 25 01:16:17 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:17 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45
>Oct 25 01:16:17 [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000c5b1d89a nonblocking
>Oct 25 01:16:17 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:17 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000c5b1d89a
>Oct 25 01:16:17 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000c5b1d89a
>Oct 25 01:16:17 [drm:drm_mode_addfb2 [drm]] [FB:111]
>Oct 25 01:16:17 [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000008c9b5d2a
>Oct 25 01:16:17 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000fd2711b4 state to 000000008c9b5d2a
>Oct 25 01:16:17 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 0000000084d45d3a state to 000000008c9b5d2a
>Oct 25 01:16:17 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:111] for [PLANE:28:plane 1A] state 0000000084d45d3a
>Oct 25 01:16:17 [drm:drm_atomic_check_only [drm]] checking 000000008c9b5d2a
>Oct 25 01:16:17 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 111
>Oct 25 01:16:17 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:17 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45
>Oct 25 01:16:17 [drm:drm_atomic_nonblocking_commit [drm]] committing 000000008c9b5d2a nonblocking
>Oct 25 01:16:17 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:17 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000008c9b5d2a
>Oct 25 01:16:17 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000008c9b5d2a
>Oct 25 01:16:17 [drm:drm_mode_addfb2 [drm]] [FB:113]
>Oct 25 01:16:17 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000b22e48ab
>Oct 25 01:16:17 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000217e0795 state to 00000000b22e48ab
>Oct 25 01:16:17 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000eef4ea9c state to 00000000b22e48ab
>Oct 25 01:16:17 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:113] for [PLANE:28:plane 1A] state 00000000eef4ea9c
>Oct 25 01:16:17 [drm:drm_atomic_check_only [drm]] checking 00000000b22e48ab
>Oct 25 01:16:17 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 113
>Oct 25 01:16:17 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:17 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45
>Oct 25 01:16:17 [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000b22e48ab nonblocking
>Oct 25 01:16:17 [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000009d092e74
>Oct 25 01:16:17 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000009d092e74
>Oct 25 01:16:17 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000009d092e74
>Oct 25 01:16:17 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000009d092e74
>Oct 25 01:16:17 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000009d092e74
>Oct 25 01:16:17 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000009d092e74
>Oct 25 01:16:17 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:17 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000b22e48ab
>Oct 25 01:16:17 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000b22e48ab
>Oct 25 01:16:17 [drm:drm_mode_addfb2 [drm]] [FB:111]
>Oct 25 01:16:17 [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000009d092e74
>Oct 25 01:16:17 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000a4955e94 state to 000000009d092e74
>Oct 25 01:16:17 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000708ec110 state to 000000009d092e74
>Oct 25 01:16:17 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:111] for [PLANE:28:plane 1A] state 00000000708ec110
>Oct 25 01:16:17 [drm:drm_atomic_check_only [drm]] checking 000000009d092e74
>Oct 25 01:16:17 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 111
>Oct 25 01:16:17 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:17 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45
>Oct 25 01:16:17 [drm:drm_atomic_nonblocking_commit [drm]] committing 000000009d092e74 nonblocking
>Oct 25 01:16:17 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:17 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000009d092e74
>Oct 25 01:16:17 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000009d092e74
>Oct 25 01:16:17 [drm:drm_mode_addfb2 [drm]] [FB:113]
>Oct 25 01:16:17 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000d2d5cfa0
>Oct 25 01:16:17 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 000000006087c748 state to 00000000d2d5cfa0
>Oct 25 01:16:17 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 0000000065c96970 state to 00000000d2d5cfa0
>Oct 25 01:16:17 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:113] for [PLANE:28:plane 1A] state 0000000065c96970
>Oct 25 01:16:17 [drm:drm_atomic_check_only [drm]] checking 00000000d2d5cfa0
>Oct 25 01:16:17 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 113
>Oct 25 01:16:17 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:17 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45
>Oct 25 01:16:17 [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000d2d5cfa0 nonblocking
>Oct 25 01:16:17 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:17 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000d2d5cfa0
>Oct 25 01:16:17 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000d2d5cfa0
>Oct 25 01:16:17 [drm:drm_mode_addfb2 [drm]] [FB:111]
>Oct 25 01:16:17 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000ca185597
>Oct 25 01:16:17 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000dd03cc21 state to 00000000ca185597
>Oct 25 01:16:17 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000b63a4291 state to 00000000ca185597
>Oct 25 01:16:17 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:111] for [PLANE:28:plane 1A] state 00000000b63a4291
>Oct 25 01:16:17 [drm:drm_atomic_check_only [drm]] checking 00000000ca185597
>Oct 25 01:16:17 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 111
>Oct 25 01:16:17 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:17 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45
>Oct 25 01:16:17 [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000ca185597 nonblocking
>Oct 25 01:16:17 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:17 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000ca185597
>Oct 25 01:16:17 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000ca185597
>Oct 25 01:16:17 [drm:drm_mode_addfb2 [drm]] [FB:113]
>Oct 25 01:16:17 [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000087eef9f8
>Oct 25 01:16:17 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 000000009c862dc2 state to 0000000087eef9f8
>Oct 25 01:16:17 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000c05759d9 state to 0000000087eef9f8
>Oct 25 01:16:17 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:113] for [PLANE:28:plane 1A] state 00000000c05759d9
>Oct 25 01:16:17 [drm:drm_atomic_check_only [drm]] checking 0000000087eef9f8
>Oct 25 01:16:17 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 113
>Oct 25 01:16:17 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:17 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45
>Oct 25 01:16:17 [drm:drm_atomic_nonblocking_commit [drm]] committing 0000000087eef9f8 nonblocking
>Oct 25 01:16:17 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000223447a7
>Oct 25 01:16:17 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000223447a7
>Oct 25 01:16:17 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000223447a7
>Oct 25 01:16:17 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:17 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000087eef9f8
>Oct 25 01:16:17 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000087eef9f8
>Oct 25 01:16:17 [drm:drm_mode_addfb2 [drm]] [FB:111]
>Oct 25 01:16:17 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000223447a7
>Oct 25 01:16:17 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 0000000087eef9f8 state to 00000000223447a7
>Oct 25 01:16:17 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 0000000027b59cc5 state to 00000000223447a7
>Oct 25 01:16:17 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:111] for [PLANE:28:plane 1A] state 0000000027b59cc5
>Oct 25 01:16:17 [drm:drm_atomic_check_only [drm]] checking 00000000223447a7
>Oct 25 01:16:17 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 111
>Oct 25 01:16:17 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:17 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45
>Oct 25 01:16:17 [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000223447a7 nonblocking
>Oct 25 01:16:17 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:17 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000d3c6ed8a
>Oct 25 01:16:17 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000d3c6ed8a
>Oct 25 01:16:17 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000d3c6ed8a
>Oct 25 01:16:17 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000d3c6ed8a
>Oct 25 01:16:17 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000223447a7
>Oct 25 01:16:17 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000223447a7
>Oct 25 01:16:17 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000d3c6ed8a
>Oct 25 01:16:17 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000d3c6ed8a
>Oct 25 01:16:17 [drm:drm_mode_addfb2 [drm]] [FB:113]
>Oct 25 01:16:17 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000dd03cc21
>Oct 25 01:16:17 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000ca185597 state to 00000000dd03cc21
>Oct 25 01:16:17 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000536d82ed state to 00000000dd03cc21
>Oct 25 01:16:17 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:113] for [PLANE:28:plane 1A] state 00000000536d82ed
>Oct 25 01:16:17 [drm:drm_atomic_check_only [drm]] checking 00000000dd03cc21
>Oct 25 01:16:17 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 113
>Oct 25 01:16:17 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:17 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45
>Oct 25 01:16:17 [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000dd03cc21 nonblocking
>Oct 25 01:16:17 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:17 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000dd03cc21
>Oct 25 01:16:17 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000c6229f40
>Oct 25 01:16:17 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000c6229f40
>Oct 25 01:16:17 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000c6229f40
>Oct 25 01:16:17 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000dd03cc21
>Oct 25 01:16:17 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000c6229f40
>Oct 25 01:16:17 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000c6229f40
>Oct 25 01:16:17 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000c6229f40
>Oct 25 01:16:17 [drm:drm_mode_addfb2 [drm]] [FB:111]
>Oct 25 01:16:17 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000c6229f40
>Oct 25 01:16:17 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000dddead2e state to 00000000c6229f40
>Oct 25 01:16:17 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 0000000081e301df state to 00000000c6229f40
>Oct 25 01:16:17 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:111] for [PLANE:28:plane 1A] state 0000000081e301df
>Oct 25 01:16:17 [drm:drm_atomic_check_only [drm]] checking 00000000c6229f40
>Oct 25 01:16:17 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 111
>Oct 25 01:16:17 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:17 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45
>Oct 25 01:16:17 [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000c6229f40 nonblocking
>Oct 25 01:16:17 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:17 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000c6229f40
>Oct 25 01:16:17 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000c6229f40
>Oct 25 01:16:17 [drm:gen8_de_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x11101010, pins 0x00000010, long 0x00000000
>Oct 25 01:16:17 [drm:intel_hpd_irq_handler [i915]] digital hpd port A - short
>Oct 25 01:16:17 [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port A - short
>Oct 25 01:16:17 [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 41 00 00 01 80 02 00 00 00 0f 0b 00
>Oct 25 01:16:17 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000f22ad9a6
>Oct 25 01:16:17 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000263d4c2c state to 00000000f22ad9a6
>Oct 25 01:16:17 [drm:drm_atomic_check_only [drm]] checking 00000000f22ad9a6
>Oct 25 01:16:17 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45
>Oct 25 01:16:17 [drm:drm_atomic_commit [drm]] committing 00000000f22ad9a6
>Oct 25 01:16:17 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000f22ad9a6
>Oct 25 01:16:17 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000f22ad9a6
>Oct 25 01:16:17 [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000006bebd53d
>Oct 25 01:16:17 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 000000006e109ca8 state to 000000006bebd53d
>Oct 25 01:16:17 [drm:drm_atomic_add_affected_connectors [drm]] Adding all current connectors for [CRTC:45:pipe A] to 000000006bebd53d
>Oct 25 01:16:17 [drm:drm_atomic_get_connector_state [drm]] Added [CONNECTOR:83:eDP-1] 00000000a37bd2e2 state to 000000006bebd53d
>Oct 25 01:16:17 [drm:drm_atomic_check_only [drm]] checking 000000006bebd53d
>Oct 25 01:16:17 [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] Updating routing for [CONNECTOR:83:eDP-1]
>Oct 25 01:16:17 [drm:drm_atomic_helper_check_modeset [drm_kms_helper]] [CONNECTOR:83:eDP-1] keeps [ENCODER:82:DDI A], now on [CRTC:45:pipe A]
>Oct 25 01:16:17 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45
>Oct 25 01:16:17 [drm:drm_atomic_commit [drm]] committing 000000006bebd53d
>Oct 25 01:16:17 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000006bebd53d
>Oct 25 01:16:17 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000006bebd53d
>Oct 25 01:16:17 [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000006bebd53d
>Oct 25 01:16:17 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000f4cee46f state to 000000006bebd53d
>Oct 25 01:16:17 [drm:drm_atomic_check_only [drm]] checking 000000006bebd53d
>Oct 25 01:16:17 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45
>Oct 25 01:16:17 [drm:drm_atomic_commit [drm]] committing 000000006bebd53d
>Oct 25 01:16:17 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000006bebd53d
>Oct 25 01:16:17 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000006bebd53d
>Oct 25 01:16:17 [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000008c2cb725
>Oct 25 01:16:17 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 000000001dd69e2b state to 000000008c2cb725
>Oct 25 01:16:17 [drm:drm_atomic_check_only [drm]] checking 000000008c2cb725
>Oct 25 01:16:17 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45
>Oct 25 01:16:17 [drm:drm_atomic_commit [drm]] committing 000000008c2cb725
>Oct 25 01:16:17 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000008c2cb725
>Oct 25 01:16:17 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000008c2cb725
>Oct 25 01:16:17 [drm:drm_mode_addfb2 [drm]] [FB:114]
>Oct 25 01:16:17 [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000001aa47d8a
>Oct 25 01:16:17 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 000000004dee64ed state to 000000001aa47d8a
>Oct 25 01:16:17 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000a64ad5eb state to 000000001aa47d8a
>Oct 25 01:16:17 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:114] for [PLANE:28:plane 1A] state 00000000a64ad5eb
>Oct 25 01:16:17 [drm:drm_atomic_check_only [drm]] checking 000000001aa47d8a
>Oct 25 01:16:17 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 114
>Oct 25 01:16:17 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:17 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45
>Oct 25 01:16:17 [drm:drm_atomic_nonblocking_commit [drm]] committing 000000001aa47d8a nonblocking
>Oct 25 01:16:17 [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000006fe095b0
>Oct 25 01:16:17 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000fd2711b4 state to 000000006fe095b0
>Oct 25 01:16:17 [drm:drm_atomic_check_only [drm]] checking 000000006fe095b0
>Oct 25 01:16:17 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45
>Oct 25 01:16:17 [drm:drm_atomic_commit [drm]] committing 000000006fe095b0
>Oct 25 01:16:17 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:17 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000001aa47d8a
>Oct 25 01:16:17 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000001aa47d8a
>Oct 25 01:16:17 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000006fe095b0
>Oct 25 01:16:17 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000006fe095b0
>Oct 25 01:16:17 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:42:cursor A] state 0000000017411d14
>Oct 25 01:16:17 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 110
>Oct 25 01:16:17 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:17 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:17 [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000006fe095b0
>Oct 25 01:16:17 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 000000004dee64ed state to 000000006fe095b0
>Oct 25 01:16:17 [drm:drm_atomic_check_only [drm]] checking 000000006fe095b0
>Oct 25 01:16:17 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45
>Oct 25 01:16:17 [drm:drm_atomic_commit [drm]] committing 000000006fe095b0
>Oct 25 01:16:17 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000006fe095b0
>Oct 25 01:16:17 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000006fe095b0
>Oct 25 01:16:17 [drm:drm_mode_addfb2 [drm]] [FB:113]
>Oct 25 01:16:17 [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000006fe095b0
>Oct 25 01:16:17 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000fd2711b4 state to 000000006fe095b0
>Oct 25 01:16:17 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 000000001244ab3c state to 000000006fe095b0
>Oct 25 01:16:17 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:113] for [PLANE:28:plane 1A] state 000000001244ab3c
>Oct 25 01:16:17 [drm:drm_atomic_check_only [drm]] checking 000000006fe095b0
>Oct 25 01:16:17 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 113
>Oct 25 01:16:17 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:17 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45
>Oct 25 01:16:17 [drm:drm_atomic_nonblocking_commit [drm]] committing 000000006fe095b0 nonblocking
>Oct 25 01:16:17 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:17 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000006fe095b0
>Oct 25 01:16:17 [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000006bebd53d
>Oct 25 01:16:17 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000006fe095b0
>Oct 25 01:16:17 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000006bebd53d
>Oct 25 01:16:17 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000006bebd53d
>Oct 25 01:16:17 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000a4955e94
>Oct 25 01:16:17 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 000000009d092e74 state to 00000000a4955e94
>Oct 25 01:16:17 [drm:drm_atomic_check_only [drm]] checking 00000000a4955e94
>Oct 25 01:16:17 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45
>Oct 25 01:16:17 [drm:drm_atomic_commit [drm]] committing 00000000a4955e94
>Oct 25 01:16:17 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000a4955e94
>Oct 25 01:16:17 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000a4955e94
>Oct 25 01:16:17 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000653af0b9
>Oct 25 01:16:17 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000c4f722fb state to 00000000653af0b9
>Oct 25 01:16:17 [drm:drm_atomic_check_only [drm]] checking 00000000653af0b9
>Oct 25 01:16:17 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45
>Oct 25 01:16:17 [drm:drm_atomic_commit [drm]] committing 00000000653af0b9
>Oct 25 01:16:17 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000653af0b9
>Oct 25 01:16:17 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000653af0b9
>Oct 25 01:16:17 [drm:drm_mode_addfb2 [drm]] [FB:114]
>Oct 25 01:16:17 [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000087eef9f8
>Oct 25 01:16:17 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000d3c6ed8a state to 0000000087eef9f8
>Oct 25 01:16:17 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 000000001665e807 state to 0000000087eef9f8
>Oct 25 01:16:17 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:114] for [PLANE:28:plane 1A] state 000000001665e807
>Oct 25 01:16:17 [drm:drm_atomic_check_only [drm]] checking 0000000087eef9f8
>Oct 25 01:16:17 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 114
>Oct 25 01:16:17 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:17 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45
>Oct 25 01:16:17 [drm:drm_atomic_nonblocking_commit [drm]] committing 0000000087eef9f8 nonblocking
>Oct 25 01:16:17 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000223447a7
>Oct 25 01:16:17 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 000000009c862dc2 state to 00000000223447a7
>Oct 25 01:16:17 [drm:drm_atomic_check_only [drm]] checking 00000000223447a7
>Oct 25 01:16:17 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45
>Oct 25 01:16:17 [drm:drm_atomic_commit [drm]] committing 00000000223447a7
>Oct 25 01:16:17 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:17 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000087eef9f8
>Oct 25 01:16:17 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000087eef9f8
>Oct 25 01:16:17 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000223447a7
>Oct 25 01:16:17 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000223447a7
>Oct 25 01:16:17 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:42:cursor A] state 000000001791cb47
>Oct 25 01:16:17 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 110
>Oct 25 01:16:17 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:17 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:17 [drm:drm_mode_addfb2 [drm]] [FB:111]
>Oct 25 01:16:17 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000e99068a3
>Oct 25 01:16:17 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 000000000ab4b2fc state to 00000000e99068a3
>Oct 25 01:16:17 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000c3022ad1 state to 00000000e99068a3
>Oct 25 01:16:17 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:111] for [PLANE:28:plane 1A] state 00000000c3022ad1
>Oct 25 01:16:17 [drm:drm_atomic_check_only [drm]] checking 00000000e99068a3
>Oct 25 01:16:17 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 111
>Oct 25 01:16:17 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:17 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45
>Oct 25 01:16:17 [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000e99068a3 nonblocking
>Oct 25 01:16:17 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:17 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000e99068a3
>Oct 25 01:16:17 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000e99068a3
>Oct 25 01:16:17 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000992f48e6
>Oct 25 01:16:17 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000f87fc6b0 state to 00000000992f48e6
>Oct 25 01:16:17 [drm:drm_atomic_check_only [drm]] checking 00000000992f48e6
>Oct 25 01:16:17 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45
>Oct 25 01:16:17 [drm:drm_atomic_commit [drm]] committing 00000000992f48e6
>Oct 25 01:16:17 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000992f48e6
>Oct 25 01:16:17 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000992f48e6
>Oct 25 01:16:17 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:42:cursor A] state 000000007a781f4d
>Oct 25 01:16:17 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 110
>Oct 25 01:16:17 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:17 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:17 [drm:drm_mode_addfb2 [drm]] [FB:114]
>Oct 25 01:16:17 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000992f48e6
>Oct 25 01:16:17 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 000000000ab4b2fc state to 00000000992f48e6
>Oct 25 01:16:17 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 000000006217ea8a state to 00000000992f48e6
>Oct 25 01:16:17 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:114] for [PLANE:28:plane 1A] state 000000006217ea8a
>Oct 25 01:16:17 [drm:drm_atomic_check_only [drm]] checking 00000000992f48e6
>Oct 25 01:16:17 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 114
>Oct 25 01:16:17 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:17 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45
>Oct 25 01:16:17 [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000992f48e6 nonblocking
>Oct 25 01:16:17 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000ff023107
>Oct 25 01:16:17 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 0000000055e5b1c7 state to 00000000ff023107
>Oct 25 01:16:17 [drm:drm_atomic_check_only [drm]] checking 00000000ff023107
>Oct 25 01:16:17 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45
>Oct 25 01:16:17 [drm:drm_atomic_commit [drm]] committing 00000000ff023107
>Oct 25 01:16:17 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:17 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000992f48e6
>Oct 25 01:16:17 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000992f48e6
>Oct 25 01:16:17 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000ff023107
>Oct 25 01:16:17 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000ff023107
>Oct 25 01:16:17 [drm:drm_mode_addfb2 [drm]] [FB:111]
>Oct 25 01:16:17 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000ff023107
>Oct 25 01:16:17 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 000000000ab4b2fc state to 00000000ff023107
>Oct 25 01:16:17 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 000000004bc529ab state to 00000000ff023107
>Oct 25 01:16:17 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:111] for [PLANE:28:plane 1A] state 000000004bc529ab
>Oct 25 01:16:17 [drm:drm_atomic_check_only [drm]] checking 00000000ff023107
>Oct 25 01:16:17 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 111
>Oct 25 01:16:17 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:17 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45
>Oct 25 01:16:17 [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000ff023107 nonblocking
>Oct 25 01:16:17 [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000001cc9f018
>Oct 25 01:16:17 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000c92b4d9a state to 000000001cc9f018
>Oct 25 01:16:17 [drm:drm_atomic_check_only [drm]] checking 000000001cc9f018
>Oct 25 01:16:17 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45
>Oct 25 01:16:17 [drm:drm_atomic_commit [drm]] committing 000000001cc9f018
>Oct 25 01:16:17 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:17 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000ff023107
>Oct 25 01:16:17 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000ff023107
>Oct 25 01:16:18 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000001cc9f018
>Oct 25 01:16:18 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000001cc9f018
>Oct 25 01:16:18 [drm:drm_mode_addfb2 [drm]] [FB:114]
>Oct 25 01:16:18 [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000001cc9f018
>Oct 25 01:16:18 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 000000000ab4b2fc state to 000000001cc9f018
>Oct 25 01:16:18 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000acfe34be state to 000000001cc9f018
>Oct 25 01:16:18 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:114] for [PLANE:28:plane 1A] state 00000000acfe34be
>Oct 25 01:16:18 [drm:drm_atomic_check_only [drm]] checking 000000001cc9f018
>Oct 25 01:16:18 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 114
>Oct 25 01:16:18 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:18 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45
>Oct 25 01:16:18 [drm:drm_atomic_nonblocking_commit [drm]] committing 000000001cc9f018 nonblocking
>Oct 25 01:16:18 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:18 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000ff023107
>Oct 25 01:16:18 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000001cc9f018
>Oct 25 01:16:18 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000001cc9f018
>Oct 25 01:16:18 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000ff023107
>Oct 25 01:16:18 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000ff023107
>Oct 25 01:16:18 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000ff023107
>Oct 25 01:16:18 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000ff023107
>Oct 25 01:16:18 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000ff023107
>Oct 25 01:16:18 [drm:drm_mode_addfb2 [drm]] [FB:111]
>Oct 25 01:16:18 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000ff023107
>Oct 25 01:16:18 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 0000000055e5b1c7 state to 00000000ff023107
>Oct 25 01:16:18 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 0000000045211b27 state to 00000000ff023107
>Oct 25 01:16:18 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:111] for [PLANE:28:plane 1A] state 0000000045211b27
>Oct 25 01:16:18 [drm:drm_atomic_check_only [drm]] checking 00000000ff023107
>Oct 25 01:16:18 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 111
>Oct 25 01:16:18 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:18 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45
>Oct 25 01:16:18 [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000ff023107 nonblocking
>Oct 25 01:16:18 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000032eedea
>Oct 25 01:16:18 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000001b1a16 state to 00000000032eedea
>Oct 25 01:16:18 [drm:drm_atomic_check_only [drm]] checking 00000000032eedea
>Oct 25 01:16:18 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45
>Oct 25 01:16:18 [drm:drm_atomic_commit [drm]] committing 00000000032eedea
>Oct 25 01:16:18 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:18 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000ff023107
>Oct 25 01:16:18 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000ff023107
>Oct 25 01:16:18 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000032eedea
>Oct 25 01:16:18 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000032eedea
>Oct 25 01:16:18 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000c73ebe3d
>Oct 25 01:16:18 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000914e8c39 state to 00000000c73ebe3d
>Oct 25 01:16:18 [drm:drm_atomic_check_only [drm]] checking 00000000c73ebe3d
>Oct 25 01:16:18 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45
>Oct 25 01:16:18 [drm:drm_atomic_commit [drm]] committing 00000000c73ebe3d
>Oct 25 01:16:18 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000c73ebe3d
>Oct 25 01:16:18 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000c73ebe3d
>Oct 25 01:16:18 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000b7798c85
>Oct 25 01:16:18 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 000000002480bd06 state to 00000000b7798c85
>Oct 25 01:16:18 [drm:drm_atomic_check_only [drm]] checking 00000000b7798c85
>Oct 25 01:16:18 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45
>Oct 25 01:16:18 [drm:drm_atomic_commit [drm]] committing 00000000b7798c85
>Oct 25 01:16:18 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000b7798c85
>Oct 25 01:16:18 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000b7798c85
>Oct 25 01:16:18 [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000006a1c1622
>Oct 25 01:16:18 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000217e0795 state to 000000006a1c1622
>Oct 25 01:16:18 [drm:drm_atomic_check_only [drm]] checking 000000006a1c1622
>Oct 25 01:16:18 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45
>Oct 25 01:16:18 [drm:drm_atomic_commit [drm]] committing 000000006a1c1622
>Oct 25 01:16:18 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000006a1c1622
>Oct 25 01:16:18 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000006a1c1622
>Oct 25 01:16:18 [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000006a1c1622
>Oct 25 01:16:18 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000e53e1ae0 state to 000000006a1c1622
>Oct 25 01:16:18 [drm:drm_atomic_check_only [drm]] checking 000000006a1c1622
>Oct 25 01:16:18 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45
>Oct 25 01:16:18 [drm:drm_atomic_commit [drm]] committing 000000006a1c1622
>Oct 25 01:16:18 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000006a1c1622
>Oct 25 01:16:18 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000006a1c1622
>Oct 25 01:16:18 [drm:drm_mode_addfb2 [drm]] [FB:113]
>Oct 25 01:16:18 [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000001000e46e
>Oct 25 01:16:18 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 0000000051afabcb state to 000000001000e46e
>Oct 25 01:16:18 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 000000009d810c73 state to 000000001000e46e
>Oct 25 01:16:18 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:113] for [PLANE:28:plane 1A] state 000000009d810c73
>Oct 25 01:16:18 [drm:drm_atomic_check_only [drm]] checking 000000001000e46e
>Oct 25 01:16:18 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 113
>Oct 25 01:16:18 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:18 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45
>Oct 25 01:16:18 [drm:drm_atomic_nonblocking_commit [drm]] committing 000000001000e46e nonblocking
>Oct 25 01:16:18 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:18 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000001000e46e
>Oct 25 01:16:18 [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000001a5b8c96
>Oct 25 01:16:18 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000001a5b8c96
>Oct 25 01:16:18 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000001000e46e
>Oct 25 01:16:18 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000001a5b8c96
>Oct 25 01:16:18 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000001a5b8c96
>Oct 25 01:16:18 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000001a5b8c96
>Oct 25 01:16:18 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000001a5b8c96
>Oct 25 01:16:18 [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000001a5b8c96
>Oct 25 01:16:18 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000032eedea state to 000000001a5b8c96
>Oct 25 01:16:18 [drm:drm_atomic_check_only [drm]] checking 000000001a5b8c96
>Oct 25 01:16:18 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45
>Oct 25 01:16:18 [drm:drm_atomic_commit [drm]] committing 000000001a5b8c96
>Oct 25 01:16:18 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000001a5b8c96
>Oct 25 01:16:18 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000001a5b8c96
>Oct 25 01:16:18 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000001b1a16
>Oct 25 01:16:18 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 000000006e109ca8 state to 00000000001b1a16
>Oct 25 01:16:18 [drm:drm_atomic_check_only [drm]] checking 00000000001b1a16
>Oct 25 01:16:18 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45
>Oct 25 01:16:18 [drm:drm_atomic_commit [drm]] committing 00000000001b1a16
>Oct 25 01:16:18 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000001b1a16
>Oct 25 01:16:18 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000001b1a16
>Oct 25 01:16:18 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000001b1a16
>Oct 25 01:16:18 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000032eedea state to 00000000001b1a16
>Oct 25 01:16:18 [drm:drm_atomic_check_only [drm]] checking 00000000001b1a16
>Oct 25 01:16:18 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45
>Oct 25 01:16:18 [drm:drm_atomic_commit [drm]] committing 00000000001b1a16
>Oct 25 01:16:18 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000001b1a16
>Oct 25 01:16:18 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000001b1a16
>Oct 25 01:16:18 [drm:drm_mode_addfb2 [drm]] [FB:114]
>Oct 25 01:16:18 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000c4f722fb
>Oct 25 01:16:18 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000f4cee46f state to 00000000c4f722fb
>Oct 25 01:16:18 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000d026dd96 state to 00000000c4f722fb
>Oct 25 01:16:18 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:114] for [PLANE:28:plane 1A] state 00000000d026dd96
>Oct 25 01:16:18 [drm:drm_atomic_check_only [drm]] checking 00000000c4f722fb
>Oct 25 01:16:18 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 114
>Oct 25 01:16:18 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:18 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45
>Oct 25 01:16:18 [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000c4f722fb nonblocking
>Oct 25 01:16:18 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:18 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000c4f722fb
>Oct 25 01:16:18 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000e53e1ae0
>Oct 25 01:16:18 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000c4f722fb
>Oct 25 01:16:18 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000e53e1ae0
>Oct 25 01:16:18 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000e53e1ae0
>Oct 25 01:16:18 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000e53e1ae0
>Oct 25 01:16:18 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000e53e1ae0
>Oct 25 01:16:18 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000e53e1ae0
>Oct 25 01:16:18 [drm:gen8_de_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x11101010, pins 0x00000010, long 0x00000000
>Oct 25 01:16:18 [drm:intel_hpd_irq_handler [i915]] digital hpd port A - short
>Oct 25 01:16:18 [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port A - short
>Oct 25 01:16:18 [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 41 00 00 01 80 02 00 00 00 0f 0b 00
>Oct 25 01:16:18 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:42:cursor A] state 000000002451fb49
>Oct 25 01:16:18 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 110
>Oct 25 01:16:18 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:18 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:18 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:42:cursor A] state 00000000bc95d85b
>Oct 25 01:16:18 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 110
>Oct 25 01:16:18 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:18 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:18 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:42:cursor A] state 0000000042b58459
>Oct 25 01:16:18 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 110
>Oct 25 01:16:18 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:18 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:18 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:42:cursor A] state 0000000071120d97
>Oct 25 01:16:18 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 110
>Oct 25 01:16:18 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:18 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:18 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:42:cursor A] state 0000000042b58459
>Oct 25 01:16:18 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 110
>Oct 25 01:16:18 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:18 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:18 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:42:cursor A] state 0000000071120d97
>Oct 25 01:16:18 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 110
>Oct 25 01:16:18 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:18 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:18 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:42:cursor A] state 0000000042b58459
>Oct 25 01:16:18 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 110
>Oct 25 01:16:18 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:18 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:18 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:42:cursor A] state 0000000071120d97
>Oct 25 01:16:18 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 110
>Oct 25 01:16:18 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:18 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:18 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:42:cursor A] state 0000000042b58459
>Oct 25 01:16:18 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 110
>Oct 25 01:16:18 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:18 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:18 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:42:cursor A] state 0000000071120d97
>Oct 25 01:16:18 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 110
>Oct 25 01:16:18 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:18 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:18 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:42:cursor A] state 0000000042b58459
>Oct 25 01:16:18 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 110
>Oct 25 01:16:18 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:18 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:18 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:42:cursor A] state 0000000033dd3c46
>Oct 25 01:16:18 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 110
>Oct 25 01:16:18 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:18 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:18 [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000000ab4b2fc
>Oct 25 01:16:18 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:42:cursor A] 00000000585a4343 state to 000000000ab4b2fc
>Oct 25 01:16:18 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 000000001cc9f018 state to 000000000ab4b2fc
>Oct 25 01:16:18 [drm:drm_atomic_set_crtc_for_plane [drm]] Link [PLANE:42:cursor A] state 00000000585a4343 to [NOCRTC]
>Oct 25 01:16:18 [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:42:cursor A] state 00000000585a4343
>Oct 25 01:16:18 [drm:drm_atomic_check_only [drm]] checking 000000000ab4b2fc
>Oct 25 01:16:18 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb -1
>Oct 25 01:16:18 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 0, off 1, on 0, ms 0
>Oct 25 01:16:18 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45
>Oct 25 01:16:18 [drm:drm_atomic_commit [drm]] committing 000000000ab4b2fc
>Oct 25 01:16:18 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:18 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000000ab4b2fc
>Oct 25 01:16:18 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000000ab4b2fc
>Oct 25 01:16:18 [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000000ab4b2fc
>Oct 25 01:16:18 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:42:cursor A] 00000000915c31d4 state to 000000000ab4b2fc
>Oct 25 01:16:18 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000c92b4d9a state to 000000000ab4b2fc
>Oct 25 01:16:18 [drm:drm_atomic_set_crtc_for_plane [drm]] Link [PLANE:42:cursor A] state 00000000915c31d4 to [CRTC:45:pipe A]
>Oct 25 01:16:18 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:42:cursor A] state 00000000915c31d4
>Oct 25 01:16:18 [drm:drm_atomic_check_only [drm]] checking 000000000ab4b2fc
>Oct 25 01:16:18 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 110
>Oct 25 01:16:18 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 0 -> 1, off 0, on 1, ms 0
>Oct 25 01:16:18 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45
>Oct 25 01:16:18 [drm:drm_atomic_commit [drm]] committing 000000000ab4b2fc
>Oct 25 01:16:18 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:18 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:18 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000000ab4b2fc
>Oct 25 01:16:18 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000000ab4b2fc
>Oct 25 01:16:18 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:42:cursor A] state 00000000db3b1574
>Oct 25 01:16:18 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 110
>Oct 25 01:16:18 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:18 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:18 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:42:cursor A] state 00000000aa66c66b
>Oct 25 01:16:18 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 110
>Oct 25 01:16:18 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:18 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:18 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:42:cursor A] state 0000000067fc7b92
>Oct 25 01:16:18 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 110
>Oct 25 01:16:18 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:18 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:18 [drm:drm_mode_addfb2 [drm]] [FB:113]
>Oct 25 01:16:18 [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000000ab4b2fc
>Oct 25 01:16:18 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 000000001cc9f018 state to 000000000ab4b2fc
>Oct 25 01:16:18 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 000000008e8b0461 state to 000000000ab4b2fc
>Oct 25 01:16:18 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:113] for [PLANE:28:plane 1A] state 000000008e8b0461
>Oct 25 01:16:18 [drm:drm_atomic_check_only [drm]] checking 000000000ab4b2fc
>Oct 25 01:16:18 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 113
>Oct 25 01:16:18 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:18 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45
>Oct 25 01:16:18 [drm:drm_atomic_nonblocking_commit [drm]] committing 000000000ab4b2fc nonblocking
>Oct 25 01:16:18 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:18 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000ff023107
>Oct 25 01:16:18 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000000ab4b2fc
>Oct 25 01:16:18 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000000ab4b2fc
>Oct 25 01:16:18 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000ff023107
>Oct 25 01:16:18 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000ff023107
>Oct 25 01:16:18 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000ff023107
>Oct 25 01:16:18 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000ff023107
>Oct 25 01:16:18 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000ff023107
>Oct 25 01:16:19 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:42:cursor A] state 000000002451fb49
>Oct 25 01:16:19 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 110
>Oct 25 01:16:19 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:19 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:19 [drm:drm_mode_addfb2 [drm]] [FB:114]
>Oct 25 01:16:19 [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000019a0f0fa
>Oct 25 01:16:19 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 000000005fc31b65 state to 0000000019a0f0fa
>Oct 25 01:16:19 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 000000008b7d9274 state to 0000000019a0f0fa
>Oct 25 01:16:19 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:114] for [PLANE:28:plane 1A] state 000000008b7d9274
>Oct 25 01:16:19 [drm:drm_atomic_check_only [drm]] checking 0000000019a0f0fa
>Oct 25 01:16:19 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 114
>Oct 25 01:16:19 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:19 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45
>Oct 25 01:16:19 [drm:drm_atomic_nonblocking_commit [drm]] committing 0000000019a0f0fa nonblocking
>Oct 25 01:16:19 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:19 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000019a0f0fa
>Oct 25 01:16:19 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000ca185597
>Oct 25 01:16:19 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000019a0f0fa
>Oct 25 01:16:19 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000ca185597
>Oct 25 01:16:19 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000ca185597
>Oct 25 01:16:19 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:42:cursor A] state 00000000f6ccbc36
>Oct 25 01:16:19 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 110
>Oct 25 01:16:19 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:19 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:19 [drm:drm_mode_addfb2 [drm]] [FB:113]
>Oct 25 01:16:19 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000834703a2
>Oct 25 01:16:19 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000969b0f48 state to 00000000834703a2
>Oct 25 01:16:19 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000835ed397 state to 00000000834703a2
>Oct 25 01:16:19 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:113] for [PLANE:28:plane 1A] state 00000000835ed397
>Oct 25 01:16:19 [drm:drm_atomic_check_only [drm]] checking 00000000834703a2
>Oct 25 01:16:19 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 113
>Oct 25 01:16:19 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:19 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45
>Oct 25 01:16:19 [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000834703a2 nonblocking
>Oct 25 01:16:19 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:19 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000834703a2
>Oct 25 01:16:19 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000e53e1ae0
>Oct 25 01:16:19 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000e53e1ae0
>Oct 25 01:16:19 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000e53e1ae0
>Oct 25 01:16:19 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000834703a2
>Oct 25 01:16:19 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000e53e1ae0
>Oct 25 01:16:19 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000e53e1ae0
>Oct 25 01:16:19 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000e53e1ae0
>Oct 25 01:16:19 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:42:cursor A] state 000000006d00e21c
>Oct 25 01:16:19 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 110
>Oct 25 01:16:19 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:19 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:19 [drm:drm_mode_addfb2 [drm]] [FB:114]
>Oct 25 01:16:19 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000834703a2
>Oct 25 01:16:19 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000263d4c2c state to 00000000834703a2
>Oct 25 01:16:19 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 000000006c6e661b state to 00000000834703a2
>Oct 25 01:16:19 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:114] for [PLANE:28:plane 1A] state 000000006c6e661b
>Oct 25 01:16:19 [drm:drm_atomic_check_only [drm]] checking 00000000834703a2
>Oct 25 01:16:19 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 114
>Oct 25 01:16:19 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:19 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45
>Oct 25 01:16:19 [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000834703a2 nonblocking
>Oct 25 01:16:19 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:19 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000653af0b9
>Oct 25 01:16:19 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000653af0b9
>Oct 25 01:16:19 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000653af0b9
>Oct 25 01:16:19 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000834703a2
>Oct 25 01:16:19 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000653af0b9
>Oct 25 01:16:19 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000834703a2
>Oct 25 01:16:19 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000653af0b9
>Oct 25 01:16:19 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000653af0b9
>Oct 25 01:16:19 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:42:cursor A] state 000000003d940b65
>Oct 25 01:16:19 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 110
>Oct 25 01:16:19 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:19 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:19 [drm:drm_mode_addfb2 [drm]] [FB:113]
>Oct 25 01:16:19 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000e53e1ae0
>Oct 25 01:16:19 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 000000006a1c1622 state to 00000000e53e1ae0
>Oct 25 01:16:19 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000af6a9896 state to 00000000e53e1ae0
>Oct 25 01:16:19 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:113] for [PLANE:28:plane 1A] state 00000000af6a9896
>Oct 25 01:16:19 [drm:drm_atomic_check_only [drm]] checking 00000000e53e1ae0
>Oct 25 01:16:19 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 113
>Oct 25 01:16:19 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:19 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45
>Oct 25 01:16:19 [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000e53e1ae0 nonblocking
>Oct 25 01:16:19 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:19 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000e53e1ae0
>Oct 25 01:16:19 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000ff023107
>Oct 25 01:16:19 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000ff023107
>Oct 25 01:16:19 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000e53e1ae0
>Oct 25 01:16:19 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000ff023107
>Oct 25 01:16:19 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000ff023107
>Oct 25 01:16:19 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000ff023107
>Oct 25 01:16:19 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000ff023107
>Oct 25 01:16:19 [drm:drm_mode_addfb2 [drm]] [FB:114]
>Oct 25 01:16:19 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000217e0795
>Oct 25 01:16:19 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000f1ecca12 state to 00000000217e0795
>Oct 25 01:16:19 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 000000008937e5ae state to 00000000217e0795
>Oct 25 01:16:19 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:114] for [PLANE:28:plane 1A] state 000000008937e5ae
>Oct 25 01:16:19 [drm:drm_atomic_check_only [drm]] checking 00000000217e0795
>Oct 25 01:16:19 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 114
>Oct 25 01:16:19 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:19 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45
>Oct 25 01:16:19 [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000217e0795 nonblocking
>Oct 25 01:16:19 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:19 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000217e0795
>Oct 25 01:16:19 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000e53e1ae0
>Oct 25 01:16:19 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000217e0795
>Oct 25 01:16:19 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000e53e1ae0
>Oct 25 01:16:19 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000e53e1ae0
>Oct 25 01:16:19 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000e53e1ae0
>Oct 25 01:16:19 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000e53e1ae0
>Oct 25 01:16:19 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000e53e1ae0
>Oct 25 01:16:19 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000e53e1ae0
>Oct 25 01:16:19 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000217e0795 state to 00000000e53e1ae0
>Oct 25 01:16:19 [drm:drm_atomic_check_only [drm]] checking 00000000e53e1ae0
>Oct 25 01:16:19 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45
>Oct 25 01:16:19 [drm:drm_atomic_commit [drm]] committing 00000000e53e1ae0
>Oct 25 01:16:19 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000e53e1ae0
>Oct 25 01:16:19 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000e53e1ae0
>Oct 25 01:16:19 [drm:drm_mode_addfb2 [drm]] [FB:111]
>Oct 25 01:16:19 [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000008bde6312
>Oct 25 01:16:19 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 000000002480bd06 state to 000000008bde6312
>Oct 25 01:16:19 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 000000007b0042d5 state to 000000008bde6312
>Oct 25 01:16:19 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:111] for [PLANE:28:plane 1A] state 000000007b0042d5
>Oct 25 01:16:19 [drm:drm_atomic_check_only [drm]] checking 000000008bde6312
>Oct 25 01:16:19 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 111
>Oct 25 01:16:19 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:19 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45
>Oct 25 01:16:19 [drm:drm_atomic_nonblocking_commit [drm]] committing 000000008bde6312 nonblocking
>Oct 25 01:16:19 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:19 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000008bde6312
>Oct 25 01:16:19 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000b7798c85
>Oct 25 01:16:19 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000008bde6312
>Oct 25 01:16:19 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000b7798c85
>Oct 25 01:16:19 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000b7798c85
>Oct 25 01:16:19 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:42:cursor A] state 0000000011a47b16
>Oct 25 01:16:19 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 110
>Oct 25 01:16:19 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:19 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:19 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:42:cursor A] state 00000000d12af5a6
>Oct 25 01:16:19 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 110
>Oct 25 01:16:19 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:19 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:19 [drm:drm_mode_addfb2 [drm]] [FB:114]
>Oct 25 01:16:19 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000f22ad9a6
>Oct 25 01:16:19 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000263d4c2c state to 00000000f22ad9a6
>Oct 25 01:16:19 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 000000006c6e661b state to 00000000f22ad9a6
>Oct 25 01:16:19 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:114] for [PLANE:28:plane 1A] state 000000006c6e661b
>Oct 25 01:16:19 [drm:drm_atomic_check_only [drm]] checking 00000000f22ad9a6
>Oct 25 01:16:19 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 114
>Oct 25 01:16:19 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:19 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45
>Oct 25 01:16:19 [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000f22ad9a6 nonblocking
>Oct 25 01:16:19 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:19 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000f22ad9a6
>Oct 25 01:16:19 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000f22ad9a6
>Oct 25 01:16:19 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:42:cursor A] state 00000000e13d103c
>Oct 25 01:16:19 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 110
>Oct 25 01:16:19 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:19 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:19 [drm:drm_mode_addfb2 [drm]] [FB:111]
>Oct 25 01:16:19 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000834703a2
>Oct 25 01:16:19 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000969b0f48 state to 00000000834703a2
>Oct 25 01:16:19 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 000000003ceedc5b state to 00000000834703a2
>Oct 25 01:16:19 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:111] for [PLANE:28:plane 1A] state 000000003ceedc5b
>Oct 25 01:16:19 [drm:drm_atomic_check_only [drm]] checking 00000000834703a2
>Oct 25 01:16:19 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 111
>Oct 25 01:16:19 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:19 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45
>Oct 25 01:16:19 [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000834703a2 nonblocking
>Oct 25 01:16:19 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:19 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000834703a2
>Oct 25 01:16:19 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000834703a2
>Oct 25 01:16:19 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:42:cursor A] state 0000000046c4678b
>Oct 25 01:16:19 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 110
>Oct 25 01:16:19 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:19 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:19 [drm:drm_mode_addfb2 [drm]] [FB:114]
>Oct 25 01:16:19 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000834703a2
>Oct 25 01:16:19 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000263d4c2c state to 00000000834703a2
>Oct 25 01:16:19 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 000000006706d0c1 state to 00000000834703a2
>Oct 25 01:16:19 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:114] for [PLANE:28:plane 1A] state 000000006706d0c1
>Oct 25 01:16:19 [drm:drm_atomic_check_only [drm]] checking 00000000834703a2
>Oct 25 01:16:19 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 114
>Oct 25 01:16:19 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:19 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45
>Oct 25 01:16:19 [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000834703a2 nonblocking
>Oct 25 01:16:19 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:19 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000834703a2
>Oct 25 01:16:19 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000834703a2
>Oct 25 01:16:19 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:42:cursor A] state 000000007741023c
>Oct 25 01:16:19 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 110
>Oct 25 01:16:19 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:19 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:19 [drm:drm_mode_addfb2 [drm]] [FB:111]
>Oct 25 01:16:19 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000f22ad9a6
>Oct 25 01:16:19 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000834703a2 state to 00000000f22ad9a6
>Oct 25 01:16:19 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 000000009420548f state to 00000000f22ad9a6
>Oct 25 01:16:19 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:111] for [PLANE:28:plane 1A] state 000000009420548f
>Oct 25 01:16:19 [drm:drm_atomic_check_only [drm]] checking 00000000f22ad9a6
>Oct 25 01:16:19 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 111
>Oct 25 01:16:19 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:19 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45
>Oct 25 01:16:19 [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000f22ad9a6 nonblocking
>Oct 25 01:16:19 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:19 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000969b0f48
>Oct 25 01:16:19 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000f22ad9a6
>Oct 25 01:16:19 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000f22ad9a6
>Oct 25 01:16:19 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000969b0f48
>Oct 25 01:16:19 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000969b0f48
>Oct 25 01:16:19 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000969b0f48
>Oct 25 01:16:19 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000969b0f48
>Oct 25 01:16:19 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000969b0f48
>Oct 25 01:16:19 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:42:cursor A] state 00000000a45cb617
>Oct 25 01:16:19 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 110
>Oct 25 01:16:19 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:19 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:19 [drm:drm_mode_addfb2 [drm]] [FB:114]
>Oct 25 01:16:19 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000969b0f48
>Oct 25 01:16:19 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000f22ad9a6 state to 00000000969b0f48
>Oct 25 01:16:19 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000f3729a32 state to 00000000969b0f48
>Oct 25 01:16:19 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:114] for [PLANE:28:plane 1A] state 00000000f3729a32
>Oct 25 01:16:19 [drm:drm_atomic_check_only [drm]] checking 00000000969b0f48
>Oct 25 01:16:19 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 114
>Oct 25 01:16:19 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:19 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45
>Oct 25 01:16:19 [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000969b0f48 nonblocking
>Oct 25 01:16:19 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:115] for [PLANE:42:cursor A] state 00000000b84ddf72
>Oct 25 01:16:19 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 115
>Oct 25 01:16:19 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:19 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:19 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:115] for [PLANE:42:cursor A] state 00000000a45cb617
>Oct 25 01:16:19 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 115
>Oct 25 01:16:19 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:19 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:19 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:42:cursor A] state 000000001d030b27
>Oct 25 01:16:19 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 110
>Oct 25 01:16:19 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:19 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:19 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:42:cursor A] state 00000000a45cb617
>Oct 25 01:16:19 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 110
>Oct 25 01:16:19 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:19 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:19 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:19 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000263d4c2c
>Oct 25 01:16:19 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000263d4c2c
>Oct 25 01:16:19 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000969b0f48
>Oct 25 01:16:19 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000969b0f48
>Oct 25 01:16:19 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000263d4c2c
>Oct 25 01:16:19 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:42:cursor A] state 000000001d030b27
>Oct 25 01:16:19 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 110
>Oct 25 01:16:19 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:19 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:19 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:42:cursor A] state 00000000a45cb617
>Oct 25 01:16:19 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 110
>Oct 25 01:16:19 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:19 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:19 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:42:cursor A] state 000000001d030b27
>Oct 25 01:16:19 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 110
>Oct 25 01:16:19 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:19 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:19 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:42:cursor A] state 00000000a45cb617
>Oct 25 01:16:19 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 110
>Oct 25 01:16:19 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:19 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:19 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:42:cursor A] state 000000001d030b27
>Oct 25 01:16:19 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 110
>Oct 25 01:16:19 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:19 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:19 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:42:cursor A] state 00000000a45cb617
>Oct 25 01:16:19 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 110
>Oct 25 01:16:19 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:19 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:19 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:42:cursor A] state 0000000032f3802f
>Oct 25 01:16:19 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 110
>Oct 25 01:16:19 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:19 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:19 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:42:cursor A] state 000000008b7d9274
>Oct 25 01:16:19 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 110
>Oct 25 01:16:19 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:19 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:19 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:42:cursor A] state 0000000032f3802f
>Oct 25 01:16:19 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 110
>Oct 25 01:16:19 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:19 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:19 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:42:cursor A] state 000000008b7d9274
>Oct 25 01:16:19 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 110
>Oct 25 01:16:19 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:19 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:19 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:42:cursor A] state 0000000032f3802f
>Oct 25 01:16:19 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 110
>Oct 25 01:16:19 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:19 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:19 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:42:cursor A] state 000000008b7d9274
>Oct 25 01:16:19 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 110
>Oct 25 01:16:19 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:19 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:19 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:42:cursor A] state 0000000032f3802f
>Oct 25 01:16:19 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 110
>Oct 25 01:16:19 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:19 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:19 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:42:cursor A] state 000000008b7d9274
>Oct 25 01:16:19 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 110
>Oct 25 01:16:19 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:19 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:19 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:42:cursor A] state 0000000032f3802f
>Oct 25 01:16:19 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 110
>Oct 25 01:16:19 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:19 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:19 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:42:cursor A] state 000000008b7d9274
>Oct 25 01:16:19 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 110
>Oct 25 01:16:19 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:19 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:19 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:42:cursor A] state 0000000032f3802f
>Oct 25 01:16:19 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 110
>Oct 25 01:16:19 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:19 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:19 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:42:cursor A] state 000000008b7d9274
>Oct 25 01:16:19 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 110
>Oct 25 01:16:19 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:19 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:19 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:42:cursor A] state 0000000027b59cc5
>Oct 25 01:16:19 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 110
>Oct 25 01:16:19 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:19 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:19 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:42:cursor A] state 00000000f487a8b3
>Oct 25 01:16:19 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 110
>Oct 25 01:16:19 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:19 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:19 [drm:drm_mode_addfb2 [drm]] [FB:111]
>Oct 25 01:16:19 [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000008b4c294f
>Oct 25 01:16:19 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000ffe41dfe state to 000000008b4c294f
>Oct 25 01:16:19 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000e2388a2b state to 000000008b4c294f
>Oct 25 01:16:19 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:111] for [PLANE:28:plane 1A] state 00000000e2388a2b
>Oct 25 01:16:19 [drm:drm_atomic_check_only [drm]] checking 000000008b4c294f
>Oct 25 01:16:19 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 111
>Oct 25 01:16:19 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:19 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45
>Oct 25 01:16:19 [drm:drm_atomic_nonblocking_commit [drm]] committing 000000008b4c294f nonblocking
>Oct 25 01:16:19 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:19 [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000067a23d31
>Oct 25 01:16:19 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000008b4c294f
>Oct 25 01:16:19 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000008b4c294f
>Oct 25 01:16:19 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000067a23d31
>Oct 25 01:16:19 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000067a23d31
>Oct 25 01:16:19 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000067a23d31
>Oct 25 01:16:19 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000067a23d31
>Oct 25 01:16:19 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000067a23d31
>Oct 25 01:16:19 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:42:cursor A] state 0000000097c7c37c
>Oct 25 01:16:19 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 110
>Oct 25 01:16:19 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:19 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:19 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:42:cursor A] state 00000000f487a8b3
>Oct 25 01:16:19 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 110
>Oct 25 01:16:19 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:19 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:19 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:42:cursor A] state 0000000097c7c37c
>Oct 25 01:16:19 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 110
>Oct 25 01:16:19 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:19 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:19 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:42:cursor A] state 00000000f487a8b3
>Oct 25 01:16:19 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 110
>Oct 25 01:16:19 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:19 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:19 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:42:cursor A] state 0000000097c7c37c
>Oct 25 01:16:19 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 110
>Oct 25 01:16:19 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:19 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:19 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:42:cursor A] state 0000000071120d97
>Oct 25 01:16:19 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 110
>Oct 25 01:16:19 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:19 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:19 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:42:cursor A] state 000000008b497eb0
>Oct 25 01:16:19 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 110
>Oct 25 01:16:19 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:19 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:19 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:42:cursor A] state 00000000acfe34be
>Oct 25 01:16:19 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 110
>Oct 25 01:16:19 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:19 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:19 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:42:cursor A] state 00000000ab49742b
>Oct 25 01:16:19 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 110
>Oct 25 01:16:19 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:19 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:19 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:42:cursor A] state 00000000b2c1c1a0
>Oct 25 01:16:19 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 110
>Oct 25 01:16:19 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:19 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:19 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:42:cursor A] state 000000003555737b
>Oct 25 01:16:19 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 110
>Oct 25 01:16:19 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:19 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:19 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:42:cursor A] state 00000000b2c1c1a0
>Oct 25 01:16:19 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 110
>Oct 25 01:16:19 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:19 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:19 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:42:cursor A] state 000000003555737b
>Oct 25 01:16:19 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 110
>Oct 25 01:16:19 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:19 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:19 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:42:cursor A] state 00000000b2c1c1a0
>Oct 25 01:16:19 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 110
>Oct 25 01:16:19 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:19 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:19 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:42:cursor A] state 000000003555737b
>Oct 25 01:16:19 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 110
>Oct 25 01:16:19 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:19 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:20 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:42:cursor A] state 00000000b2c1c1a0
>Oct 25 01:16:20 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 110
>Oct 25 01:16:20 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:20 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:20 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:42:cursor A] state 000000003555737b
>Oct 25 01:16:20 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 110
>Oct 25 01:16:20 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:20 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:20 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:42:cursor A] state 00000000b2c1c1a0
>Oct 25 01:16:20 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 110
>Oct 25 01:16:20 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:20 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:20 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:42:cursor A] state 000000003555737b
>Oct 25 01:16:20 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 110
>Oct 25 01:16:20 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:20 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:20 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:42:cursor A] state 00000000b2c1c1a0
>Oct 25 01:16:20 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 110
>Oct 25 01:16:20 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:20 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:20 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:42:cursor A] state 000000003555737b
>Oct 25 01:16:20 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 110
>Oct 25 01:16:20 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:20 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:20 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:42:cursor A] state 00000000b2c1c1a0
>Oct 25 01:16:20 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 110
>Oct 25 01:16:20 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:20 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:20 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:42:cursor A] state 000000003555737b
>Oct 25 01:16:20 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 110
>Oct 25 01:16:20 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:20 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:20 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:42:cursor A] state 00000000b2c1c1a0
>Oct 25 01:16:20 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 110
>Oct 25 01:16:20 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:20 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:20 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:42:cursor A] state 000000003555737b
>Oct 25 01:16:20 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 110
>Oct 25 01:16:20 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:20 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:20 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:42:cursor A] state 00000000b2c1c1a0
>Oct 25 01:16:20 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 110
>Oct 25 01:16:20 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:20 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:20 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:42:cursor A] state 00000000fae218d6
>Oct 25 01:16:20 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 110
>Oct 25 01:16:20 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:20 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:20 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:42:cursor A] state 00000000ab69dab2
>Oct 25 01:16:20 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 110
>Oct 25 01:16:20 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:20 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:20 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:42:cursor A] state 00000000fae218d6
>Oct 25 01:16:20 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 110
>Oct 25 01:16:20 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:20 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:20 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:42:cursor A] state 00000000ab69dab2
>Oct 25 01:16:20 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 110
>Oct 25 01:16:20 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:20 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:20 [drm:drm_mode_addfb2 [drm]] [FB:114]
>Oct 25 01:16:20 [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000001dd69e2b
>Oct 25 01:16:20 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000c986cc08 state to 000000001dd69e2b
>Oct 25 01:16:20 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000727717c7 state to 000000001dd69e2b
>Oct 25 01:16:20 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:114] for [PLANE:28:plane 1A] state 00000000727717c7
>Oct 25 01:16:20 [drm:drm_atomic_check_only [drm]] checking 000000001dd69e2b
>Oct 25 01:16:20 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 114
>Oct 25 01:16:20 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:20 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45
>Oct 25 01:16:20 [drm:drm_atomic_nonblocking_commit [drm]] committing 000000001dd69e2b nonblocking
>Oct 25 01:16:20 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:20 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000a4955e94
>Oct 25 01:16:20 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000001dd69e2b
>Oct 25 01:16:20 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000001dd69e2b
>Oct 25 01:16:20 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000a4955e94
>Oct 25 01:16:20 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000a4955e94
>Oct 25 01:16:20 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000a4955e94
>Oct 25 01:16:20 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000a4955e94
>Oct 25 01:16:20 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000a4955e94
>Oct 25 01:16:20 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:42:cursor A] state 00000000bb09c912
>Oct 25 01:16:20 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 110
>Oct 25 01:16:20 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:20 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:20 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:42:cursor A] state 00000000ab69dab2
>Oct 25 01:16:20 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 110
>Oct 25 01:16:20 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:20 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:20 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:42:cursor A] state 00000000bb09c912
>Oct 25 01:16:20 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 110
>Oct 25 01:16:20 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:20 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:20 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:42:cursor A] state 00000000ab69dab2
>Oct 25 01:16:20 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 110
>Oct 25 01:16:20 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:20 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:20 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:42:cursor A] state 000000001d030b27
>Oct 25 01:16:20 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 110
>Oct 25 01:16:20 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:20 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:20 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:42:cursor A] state 00000000a0e38ad2
>Oct 25 01:16:20 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 110
>Oct 25 01:16:20 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:20 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:20 [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000004dee64ed
>Oct 25 01:16:20 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000fd2711b4 state to 000000004dee64ed
>Oct 25 01:16:20 [drm:drm_atomic_check_only [drm]] checking 000000004dee64ed
>Oct 25 01:16:20 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45
>Oct 25 01:16:20 [drm:drm_atomic_commit [drm]] committing 000000004dee64ed
>Oct 25 01:16:20 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000004dee64ed
>Oct 25 01:16:20 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000004dee64ed
>Oct 25 01:16:20 [drm:gen8_de_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x11101010, pins 0x00000010, long 0x00000000
>Oct 25 01:16:20 [drm:intel_hpd_irq_handler [i915]] digital hpd port A - short
>Oct 25 01:16:20 [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port A - short
>Oct 25 01:16:20 [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 41 00 00 01 80 02 00 00 00 0f 0b 00
>Oct 25 01:16:20 [drm:drm_mode_addfb2 [drm]] [FB:113]
>Oct 25 01:16:20 [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000067a23d31
>Oct 25 01:16:20 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000c0902f8c state to 0000000067a23d31
>Oct 25 01:16:20 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000db3b1574 state to 0000000067a23d31
>Oct 25 01:16:20 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:113] for [PLANE:28:plane 1A] state 00000000db3b1574
>Oct 25 01:16:20 [drm:drm_atomic_check_only [drm]] checking 0000000067a23d31
>Oct 25 01:16:20 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 113
>Oct 25 01:16:20 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:20 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45
>Oct 25 01:16:20 [drm:drm_atomic_nonblocking_commit [drm]] committing 0000000067a23d31 nonblocking
>Oct 25 01:16:20 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:20 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000ca185597
>Oct 25 01:16:20 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000067a23d31
>Oct 25 01:16:20 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000067a23d31
>Oct 25 01:16:20 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000ca185597
>Oct 25 01:16:20 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000ca185597
>Oct 25 01:16:21 [drm:gen8_de_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x11101010, pins 0x00000010, long 0x00000000
>Oct 25 01:16:21 [drm:intel_hpd_irq_handler [i915]] digital hpd port A - short
>Oct 25 01:16:21 [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port A - short
>Oct 25 01:16:21 [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 41 00 00 01 80 02 00 00 00 0f 0b 00
>Oct 25 01:16:21 [drm:drm_mode_addfb2 [drm]] [FB:114]
>Oct 25 01:16:21 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000a7a225a5
>Oct 25 01:16:21 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000f8616964 state to 00000000a7a225a5
>Oct 25 01:16:21 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000b1fe57dd state to 00000000a7a225a5
>Oct 25 01:16:21 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:114] for [PLANE:28:plane 1A] state 00000000b1fe57dd
>Oct 25 01:16:21 [drm:drm_atomic_check_only [drm]] checking 00000000a7a225a5
>Oct 25 01:16:21 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 114
>Oct 25 01:16:21 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:21 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45
>Oct 25 01:16:21 [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000a7a225a5 nonblocking
>Oct 25 01:16:21 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:21 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000a7a225a5
>Oct 25 01:16:21 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000a7a225a5
>Oct 25 01:16:21 [drm:gen8_de_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x11101010, pins 0x00000010, long 0x00000000
>Oct 25 01:16:21 [drm:intel_hpd_irq_handler [i915]] digital hpd port A - short
>Oct 25 01:16:21 [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port A - short
>Oct 25 01:16:21 [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 41 00 00 01 80 02 00 00 00 0f 0b 00
>Oct 25 01:16:21 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:42:cursor A] state 00000000c1050601
>Oct 25 01:16:21 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 110
>Oct 25 01:16:21 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:21 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:22 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:42:cursor A] state 0000000009c70f94
>Oct 25 01:16:22 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 110
>Oct 25 01:16:22 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:22 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:22 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:113] for [PLANE:42:cursor A] state 00000000e396bf6c
>Oct 25 01:16:22 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 113
>Oct 25 01:16:22 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:22 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:22 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:113] for [PLANE:42:cursor A] state 0000000009c70f94
>Oct 25 01:16:22 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 113
>Oct 25 01:16:22 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:22 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:22 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:113] for [PLANE:42:cursor A] state 00000000e396bf6c
>Oct 25 01:16:22 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 113
>Oct 25 01:16:22 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:22 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:22 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:113] for [PLANE:42:cursor A] state 0000000009c70f94
>Oct 25 01:16:22 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 113
>Oct 25 01:16:22 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:22 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:22 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:113] for [PLANE:42:cursor A] state 00000000e396bf6c
>Oct 25 01:16:22 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 113
>Oct 25 01:16:22 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:22 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:22 [drm:drm_mode_addfb2 [drm]] [FB:110]
>Oct 25 01:16:22 [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000035417744
>Oct 25 01:16:22 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000a7a225a5 state to 0000000035417744
>Oct 25 01:16:22 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 000000006166d1c9 state to 0000000035417744
>Oct 25 01:16:22 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:28:plane 1A] state 000000006166d1c9
>Oct 25 01:16:22 [drm:drm_atomic_check_only [drm]] checking 0000000035417744
>Oct 25 01:16:22 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 110
>Oct 25 01:16:22 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:22 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45
>Oct 25 01:16:22 [drm:drm_atomic_nonblocking_commit [drm]] committing 0000000035417744 nonblocking
>Oct 25 01:16:22 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:22 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000035417744
>Oct 25 01:16:22 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000035417744
>Oct 25 01:16:22 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:113] for [PLANE:42:cursor A] state 0000000020e68c00
>Oct 25 01:16:22 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 113
>Oct 25 01:16:22 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:22 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:22 [drm:drm_mode_addfb2 [drm]] [FB:114]
>Oct 25 01:16:22 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000b7798c85
>Oct 25 01:16:22 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 000000002480bd06 state to 00000000b7798c85
>Oct 25 01:16:22 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 0000000037e40ab3 state to 00000000b7798c85
>Oct 25 01:16:22 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:114] for [PLANE:28:plane 1A] state 0000000037e40ab3
>Oct 25 01:16:22 [drm:drm_atomic_check_only [drm]] checking 00000000b7798c85
>Oct 25 01:16:22 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 114
>Oct 25 01:16:22 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:22 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45
>Oct 25 01:16:22 [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000b7798c85 nonblocking
>Oct 25 01:16:22 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:22 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000b7798c85
>Oct 25 01:16:22 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000b7798c85
>Oct 25 01:16:22 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:113] for [PLANE:42:cursor A] state 0000000009c70f94
>Oct 25 01:16:22 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 113
>Oct 25 01:16:22 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:22 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:22 [drm:drm_mode_addfb2 [drm]] [FB:110]
>Oct 25 01:16:22 [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000008bde6312
>Oct 25 01:16:22 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000b7798c85 state to 000000008bde6312
>Oct 25 01:16:22 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000fb2fe074 state to 000000008bde6312
>Oct 25 01:16:22 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:28:plane 1A] state 00000000fb2fe074
>Oct 25 01:16:22 [drm:drm_atomic_check_only [drm]] checking 000000008bde6312
>Oct 25 01:16:22 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 110
>Oct 25 01:16:22 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:22 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45
>Oct 25 01:16:22 [drm:drm_atomic_nonblocking_commit [drm]] committing 000000008bde6312 nonblocking
>Oct 25 01:16:22 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:22 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000008bde6312
>Oct 25 01:16:22 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000a7a225a5
>Oct 25 01:16:22 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000a7a225a5
>Oct 25 01:16:22 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000008bde6312
>Oct 25 01:16:22 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000a7a225a5
>Oct 25 01:16:22 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000a7a225a5
>Oct 25 01:16:22 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000a7a225a5
>Oct 25 01:16:22 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000a7a225a5
>Oct 25 01:16:22 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:113] for [PLANE:42:cursor A] state 00000000e396bf6c
>Oct 25 01:16:22 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 113
>Oct 25 01:16:22 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:22 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:22 [drm:drm_mode_addfb2 [drm]] [FB:114]
>Oct 25 01:16:22 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000a7a225a5
>Oct 25 01:16:22 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 0000000035417744 state to 00000000a7a225a5
>Oct 25 01:16:22 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 000000006166d1c9 state to 00000000a7a225a5
>Oct 25 01:16:22 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:114] for [PLANE:28:plane 1A] state 000000006166d1c9
>Oct 25 01:16:22 [drm:drm_atomic_check_only [drm]] checking 00000000a7a225a5
>Oct 25 01:16:22 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 114
>Oct 25 01:16:22 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:22 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45
>Oct 25 01:16:22 [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000a7a225a5 nonblocking
>Oct 25 01:16:22 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:22 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000a7a225a5
>Oct 25 01:16:22 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000a7a225a5
>Oct 25 01:16:22 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:113] for [PLANE:42:cursor A] state 0000000020e68c00
>Oct 25 01:16:22 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 113
>Oct 25 01:16:22 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:22 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:22 [drm:drm_mode_addfb2 [drm]] [FB:110]
>Oct 25 01:16:22 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000f8616964
>Oct 25 01:16:22 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000a7a225a5 state to 00000000f8616964
>Oct 25 01:16:22 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000b1fe57dd state to 00000000f8616964
>Oct 25 01:16:22 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:28:plane 1A] state 00000000b1fe57dd
>Oct 25 01:16:22 [drm:drm_atomic_check_only [drm]] checking 00000000f8616964
>Oct 25 01:16:22 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 110
>Oct 25 01:16:22 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:22 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45
>Oct 25 01:16:22 [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000f8616964 nonblocking
>Oct 25 01:16:22 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:22 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000f8616964
>Oct 25 01:16:22 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000f8616964
>Oct 25 01:16:22 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:113] for [PLANE:42:cursor A] state 0000000009c70f94
>Oct 25 01:16:22 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 113
>Oct 25 01:16:22 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:22 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:22 [drm:drm_mode_addfb2 [drm]] [FB:114]
>Oct 25 01:16:22 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000b7798c85
>Oct 25 01:16:22 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 000000008bde6312 state to 00000000b7798c85
>Oct 25 01:16:22 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 000000006166d1c9 state to 00000000b7798c85
>Oct 25 01:16:22 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:114] for [PLANE:28:plane 1A] state 000000006166d1c9
>Oct 25 01:16:22 [drm:drm_atomic_check_only [drm]] checking 00000000b7798c85
>Oct 25 01:16:22 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 114
>Oct 25 01:16:22 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:22 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45
>Oct 25 01:16:22 [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000b7798c85 nonblocking
>Oct 25 01:16:22 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:22 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000b7798c85
>Oct 25 01:16:22 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000b7798c85
>Oct 25 01:16:22 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:113] for [PLANE:42:cursor A] state 00000000e396bf6c
>Oct 25 01:16:22 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 113
>Oct 25 01:16:22 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:22 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:22 [drm:drm_mode_addfb2 [drm]] [FB:110]
>Oct 25 01:16:22 [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000002480bd06
>Oct 25 01:16:22 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000b7798c85 state to 000000002480bd06
>Oct 25 01:16:22 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000fb2fe074 state to 000000002480bd06
>Oct 25 01:16:22 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:28:plane 1A] state 00000000fb2fe074
>Oct 25 01:16:22 [drm:drm_atomic_check_only [drm]] checking 000000002480bd06
>Oct 25 01:16:22 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 110
>Oct 25 01:16:22 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:22 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45
>Oct 25 01:16:22 [drm:drm_atomic_nonblocking_commit [drm]] committing 000000002480bd06 nonblocking
>Oct 25 01:16:22 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:22 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000002480bd06
>Oct 25 01:16:22 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000002480bd06
>Oct 25 01:16:22 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:113] for [PLANE:42:cursor A] state 0000000020e68c00
>Oct 25 01:16:22 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 113
>Oct 25 01:16:22 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:22 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:22 [drm:drm_mode_addfb2 [drm]] [FB:114]
>Oct 25 01:16:22 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000a7a225a5
>Oct 25 01:16:22 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000f8616964 state to 00000000a7a225a5
>Oct 25 01:16:22 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 0000000037e40ab3 state to 00000000a7a225a5
>Oct 25 01:16:22 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:114] for [PLANE:28:plane 1A] state 0000000037e40ab3
>Oct 25 01:16:22 [drm:drm_atomic_check_only [drm]] checking 00000000a7a225a5
>Oct 25 01:16:22 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 114
>Oct 25 01:16:22 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:22 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45
>Oct 25 01:16:22 [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000a7a225a5 nonblocking
>Oct 25 01:16:22 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:22 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000a7a225a5
>Oct 25 01:16:22 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000a7a225a5
>Oct 25 01:16:22 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:113] for [PLANE:42:cursor A] state 0000000009c70f94
>Oct 25 01:16:22 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 113
>Oct 25 01:16:22 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:22 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:22 [drm:drm_mode_addfb2 [drm]] [FB:110]
>Oct 25 01:16:22 [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000035417744
>Oct 25 01:16:22 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000a7a225a5 state to 0000000035417744
>Oct 25 01:16:22 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000fb2fe074 state to 0000000035417744
>Oct 25 01:16:22 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:28:plane 1A] state 00000000fb2fe074
>Oct 25 01:16:22 [drm:drm_atomic_check_only [drm]] checking 0000000035417744
>Oct 25 01:16:22 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 110
>Oct 25 01:16:22 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:22 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45
>Oct 25 01:16:22 [drm:drm_atomic_nonblocking_commit [drm]] committing 0000000035417744 nonblocking
>Oct 25 01:16:22 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:22 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000035417744
>Oct 25 01:16:22 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000035417744
>Oct 25 01:16:22 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:113] for [PLANE:42:cursor A] state 00000000e396bf6c
>Oct 25 01:16:22 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 113
>Oct 25 01:16:22 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:22 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:22 [drm:drm_mode_addfb2 [drm]] [FB:114]
>Oct 25 01:16:22 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000b7798c85
>Oct 25 01:16:22 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 000000002480bd06 state to 00000000b7798c85
>Oct 25 01:16:22 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 000000006166d1c9 state to 00000000b7798c85
>Oct 25 01:16:22 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:114] for [PLANE:28:plane 1A] state 000000006166d1c9
>Oct 25 01:16:22 [drm:drm_atomic_check_only [drm]] checking 00000000b7798c85
>Oct 25 01:16:22 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 114
>Oct 25 01:16:22 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:22 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45
>Oct 25 01:16:22 [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000b7798c85 nonblocking
>Oct 25 01:16:22 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:22 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000b7798c85
>Oct 25 01:16:22 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000b7798c85
>Oct 25 01:16:22 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:113] for [PLANE:42:cursor A] state 0000000020e68c00
>Oct 25 01:16:22 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 113
>Oct 25 01:16:22 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:22 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:22 [drm:drm_mode_addfb2 [drm]] [FB:110]
>Oct 25 01:16:22 [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000008bde6312
>Oct 25 01:16:22 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000b7798c85 state to 000000008bde6312
>Oct 25 01:16:22 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000b1fe57dd state to 000000008bde6312
>Oct 25 01:16:22 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:28:plane 1A] state 00000000b1fe57dd
>Oct 25 01:16:22 [drm:drm_atomic_check_only [drm]] checking 000000008bde6312
>Oct 25 01:16:22 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 110
>Oct 25 01:16:22 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:22 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45
>Oct 25 01:16:22 [drm:drm_atomic_nonblocking_commit [drm]] committing 000000008bde6312 nonblocking
>Oct 25 01:16:22 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:22 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000008bde6312
>Oct 25 01:16:22 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000008bde6312
>Oct 25 01:16:22 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:113] for [PLANE:42:cursor A] state 0000000009c70f94
>Oct 25 01:16:22 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 113
>Oct 25 01:16:22 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:22 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:22 [drm:drm_mode_addfb2 [drm]] [FB:114]
>Oct 25 01:16:22 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000a7a225a5
>Oct 25 01:16:22 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 0000000035417744 state to 00000000a7a225a5
>Oct 25 01:16:22 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 000000006166d1c9 state to 00000000a7a225a5
>Oct 25 01:16:22 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:114] for [PLANE:28:plane 1A] state 000000006166d1c9
>Oct 25 01:16:22 [drm:drm_atomic_check_only [drm]] checking 00000000a7a225a5
>Oct 25 01:16:22 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 114
>Oct 25 01:16:22 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:22 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45
>Oct 25 01:16:22 [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000a7a225a5 nonblocking
>Oct 25 01:16:22 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:22 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000a7a225a5
>Oct 25 01:16:22 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000a7a225a5
>Oct 25 01:16:22 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:113] for [PLANE:42:cursor A] state 00000000e396bf6c
>Oct 25 01:16:22 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 113
>Oct 25 01:16:22 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:22 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:22 [drm:drm_mode_addfb2 [drm]] [FB:110]
>Oct 25 01:16:22 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000f8616964
>Oct 25 01:16:22 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000a7a225a5 state to 00000000f8616964
>Oct 25 01:16:22 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000fb2fe074 state to 00000000f8616964
>Oct 25 01:16:22 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:28:plane 1A] state 00000000fb2fe074
>Oct 25 01:16:22 [drm:drm_atomic_check_only [drm]] checking 00000000f8616964
>Oct 25 01:16:22 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 110
>Oct 25 01:16:22 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:22 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45
>Oct 25 01:16:22 [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000f8616964 nonblocking
>Oct 25 01:16:22 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:22 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000f8616964
>Oct 25 01:16:22 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000f8616964
>Oct 25 01:16:22 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:113] for [PLANE:42:cursor A] state 0000000020e68c00
>Oct 25 01:16:22 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 113
>Oct 25 01:16:22 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:22 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:22 [drm:drm_mode_addfb2 [drm]] [FB:114]
>Oct 25 01:16:22 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000b7798c85
>Oct 25 01:16:22 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 000000008bde6312 state to 00000000b7798c85
>Oct 25 01:16:22 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 0000000037e40ab3 state to 00000000b7798c85
>Oct 25 01:16:22 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:114] for [PLANE:28:plane 1A] state 0000000037e40ab3
>Oct 25 01:16:22 [drm:drm_atomic_check_only [drm]] checking 00000000b7798c85
>Oct 25 01:16:22 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 114
>Oct 25 01:16:22 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:22 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45
>Oct 25 01:16:22 [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000b7798c85 nonblocking
>Oct 25 01:16:22 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:22 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000b7798c85
>Oct 25 01:16:22 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000b7798c85
>Oct 25 01:16:22 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:113] for [PLANE:42:cursor A] state 0000000009c70f94
>Oct 25 01:16:22 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 113
>Oct 25 01:16:22 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:22 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:22 [drm:drm_mode_addfb2 [drm]] [FB:110]
>Oct 25 01:16:22 [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000002480bd06
>Oct 25 01:16:22 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000b7798c85 state to 000000002480bd06
>Oct 25 01:16:22 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000fb2fe074 state to 000000002480bd06
>Oct 25 01:16:22 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:28:plane 1A] state 00000000fb2fe074
>Oct 25 01:16:22 [drm:drm_atomic_check_only [drm]] checking 000000002480bd06
>Oct 25 01:16:22 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 110
>Oct 25 01:16:22 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:22 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45
>Oct 25 01:16:22 [drm:drm_atomic_nonblocking_commit [drm]] committing 000000002480bd06 nonblocking
>Oct 25 01:16:22 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:22 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000a7a225a5
>Oct 25 01:16:22 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000002480bd06
>Oct 25 01:16:22 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000002480bd06
>Oct 25 01:16:22 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000a7a225a5
>Oct 25 01:16:22 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000a7a225a5
>Oct 25 01:16:22 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000a7a225a5
>Oct 25 01:16:22 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000a7a225a5
>Oct 25 01:16:22 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000a7a225a5
>Oct 25 01:16:22 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:113] for [PLANE:42:cursor A] state 00000000e396bf6c
>Oct 25 01:16:22 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 113
>Oct 25 01:16:22 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:22 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:22 [drm:drm_mode_addfb2 [drm]] [FB:114]
>Oct 25 01:16:22 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000a7a225a5
>Oct 25 01:16:22 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000f8616964 state to 00000000a7a225a5
>Oct 25 01:16:22 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 000000006166d1c9 state to 00000000a7a225a5
>Oct 25 01:16:22 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:114] for [PLANE:28:plane 1A] state 000000006166d1c9
>Oct 25 01:16:22 [drm:drm_atomic_check_only [drm]] checking 00000000a7a225a5
>Oct 25 01:16:22 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 114
>Oct 25 01:16:22 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:22 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45
>Oct 25 01:16:22 [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000a7a225a5 nonblocking
>Oct 25 01:16:22 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:22 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000a7a225a5
>Oct 25 01:16:22 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000a7a225a5
>Oct 25 01:16:22 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:113] for [PLANE:42:cursor A] state 0000000020e68c00
>Oct 25 01:16:22 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 113
>Oct 25 01:16:22 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:22 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:22 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:113] for [PLANE:42:cursor A] state 00000000e396bf6c
>Oct 25 01:16:22 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 113
>Oct 25 01:16:22 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:22 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:22 [drm:drm_mode_addfb2 [drm]] [FB:110]
>Oct 25 01:16:22 [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000035417744
>Oct 25 01:16:22 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000a7a225a5 state to 0000000035417744
>Oct 25 01:16:22 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000b1fe57dd state to 0000000035417744
>Oct 25 01:16:22 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:28:plane 1A] state 00000000b1fe57dd
>Oct 25 01:16:22 [drm:drm_atomic_check_only [drm]] checking 0000000035417744
>Oct 25 01:16:22 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 110
>Oct 25 01:16:22 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:22 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45
>Oct 25 01:16:22 [drm:drm_atomic_nonblocking_commit [drm]] committing 0000000035417744 nonblocking
>Oct 25 01:16:22 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:22 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000035417744
>Oct 25 01:16:22 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000035417744
>Oct 25 01:16:22 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:113] for [PLANE:42:cursor A] state 0000000009c70f94
>Oct 25 01:16:22 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 113
>Oct 25 01:16:22 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:22 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:22 [drm:drm_mode_addfb2 [drm]] [FB:114]
>Oct 25 01:16:22 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000b7798c85
>Oct 25 01:16:22 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 000000002480bd06 state to 00000000b7798c85
>Oct 25 01:16:22 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 000000006166d1c9 state to 00000000b7798c85
>Oct 25 01:16:22 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:114] for [PLANE:28:plane 1A] state 000000006166d1c9
>Oct 25 01:16:22 [drm:drm_atomic_check_only [drm]] checking 00000000b7798c85
>Oct 25 01:16:22 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 114
>Oct 25 01:16:22 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:22 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45
>Oct 25 01:16:22 [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000b7798c85 nonblocking
>Oct 25 01:16:22 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:22 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000b7798c85
>Oct 25 01:16:22 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000b7798c85
>Oct 25 01:16:22 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:113] for [PLANE:42:cursor A] state 0000000020e68c00
>Oct 25 01:16:22 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 113
>Oct 25 01:16:22 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:22 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:22 [drm:drm_mode_addfb2 [drm]] [FB:110]
>Oct 25 01:16:22 [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000008bde6312
>Oct 25 01:16:22 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000b7798c85 state to 000000008bde6312
>Oct 25 01:16:22 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000fb2fe074 state to 000000008bde6312
>Oct 25 01:16:22 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:28:plane 1A] state 00000000fb2fe074
>Oct 25 01:16:22 [drm:drm_atomic_check_only [drm]] checking 000000008bde6312
>Oct 25 01:16:22 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 110
>Oct 25 01:16:22 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:22 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45
>Oct 25 01:16:22 [drm:drm_atomic_nonblocking_commit [drm]] committing 000000008bde6312 nonblocking
>Oct 25 01:16:22 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:22 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000008bde6312
>Oct 25 01:16:22 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000a7a225a5
>Oct 25 01:16:22 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000008bde6312
>Oct 25 01:16:22 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000a7a225a5
>Oct 25 01:16:22 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000a7a225a5
>Oct 25 01:16:22 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:113] for [PLANE:42:cursor A] state 00000000e396bf6c
>Oct 25 01:16:22 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 113
>Oct 25 01:16:22 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:22 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:22 [drm:drm_mode_addfb2 [drm]] [FB:114]
>Oct 25 01:16:22 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000a7a225a5
>Oct 25 01:16:22 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 0000000035417744 state to 00000000a7a225a5
>Oct 25 01:16:22 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 0000000037e40ab3 state to 00000000a7a225a5
>Oct 25 01:16:22 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:114] for [PLANE:28:plane 1A] state 0000000037e40ab3
>Oct 25 01:16:22 [drm:drm_atomic_check_only [drm]] checking 00000000a7a225a5
>Oct 25 01:16:22 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 114
>Oct 25 01:16:22 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:22 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45
>Oct 25 01:16:22 [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000a7a225a5 nonblocking
>Oct 25 01:16:22 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:22 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000a7a225a5
>Oct 25 01:16:22 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000a7a225a5
>Oct 25 01:16:22 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:113] for [PLANE:42:cursor A] state 0000000009c70f94
>Oct 25 01:16:22 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 113
>Oct 25 01:16:22 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:22 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:22 [drm:drm_mode_addfb2 [drm]] [FB:110]
>Oct 25 01:16:22 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000f8616964
>Oct 25 01:16:22 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000a7a225a5 state to 00000000f8616964
>Oct 25 01:16:22 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000fb2fe074 state to 00000000f8616964
>Oct 25 01:16:22 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:28:plane 1A] state 00000000fb2fe074
>Oct 25 01:16:22 [drm:drm_atomic_check_only [drm]] checking 00000000f8616964
>Oct 25 01:16:22 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 110
>Oct 25 01:16:22 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:22 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45
>Oct 25 01:16:22 [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000f8616964 nonblocking
>Oct 25 01:16:22 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:22 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000f8616964
>Oct 25 01:16:22 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000f8616964
>Oct 25 01:16:22 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:113] for [PLANE:42:cursor A] state 0000000020e68c00
>Oct 25 01:16:22 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 113
>Oct 25 01:16:22 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:22 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:22 [drm:drm_mode_addfb2 [drm]] [FB:114]
>Oct 25 01:16:22 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000b7798c85
>Oct 25 01:16:22 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 000000008bde6312 state to 00000000b7798c85
>Oct 25 01:16:22 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 000000006166d1c9 state to 00000000b7798c85
>Oct 25 01:16:22 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:114] for [PLANE:28:plane 1A] state 000000006166d1c9
>Oct 25 01:16:22 [drm:drm_atomic_check_only [drm]] checking 00000000b7798c85
>Oct 25 01:16:22 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 114
>Oct 25 01:16:22 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:22 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45
>Oct 25 01:16:22 [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000b7798c85 nonblocking
>Oct 25 01:16:22 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:22 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000b7798c85
>Oct 25 01:16:22 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000b7798c85
>Oct 25 01:16:22 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:113] for [PLANE:42:cursor A] state 00000000e396bf6c
>Oct 25 01:16:22 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 113
>Oct 25 01:16:22 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:22 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:22 [drm:drm_mode_addfb2 [drm]] [FB:110]
>Oct 25 01:16:22 [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000002480bd06
>Oct 25 01:16:22 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000b7798c85 state to 000000002480bd06
>Oct 25 01:16:22 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000b1fe57dd state to 000000002480bd06
>Oct 25 01:16:22 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:28:plane 1A] state 00000000b1fe57dd
>Oct 25 01:16:22 [drm:drm_atomic_check_only [drm]] checking 000000002480bd06
>Oct 25 01:16:22 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 110
>Oct 25 01:16:22 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:22 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45
>Oct 25 01:16:22 [drm:drm_atomic_nonblocking_commit [drm]] committing 000000002480bd06 nonblocking
>Oct 25 01:16:22 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:22 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000002480bd06
>Oct 25 01:16:22 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000002480bd06
>Oct 25 01:16:22 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:113] for [PLANE:42:cursor A] state 0000000009c70f94
>Oct 25 01:16:22 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 113
>Oct 25 01:16:22 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:22 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:22 [drm:drm_mode_addfb2 [drm]] [FB:114]
>Oct 25 01:16:22 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000a7a225a5
>Oct 25 01:16:22 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000f8616964 state to 00000000a7a225a5
>Oct 25 01:16:22 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 000000006166d1c9 state to 00000000a7a225a5
>Oct 25 01:16:22 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:114] for [PLANE:28:plane 1A] state 000000006166d1c9
>Oct 25 01:16:22 [drm:drm_atomic_check_only [drm]] checking 00000000a7a225a5
>Oct 25 01:16:22 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 114
>Oct 25 01:16:22 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:22 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45
>Oct 25 01:16:22 [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000a7a225a5 nonblocking
>Oct 25 01:16:22 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:22 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000a7a225a5
>Oct 25 01:16:22 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000a7a225a5
>Oct 25 01:16:22 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:113] for [PLANE:42:cursor A] state 0000000020e68c00
>Oct 25 01:16:22 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 113
>Oct 25 01:16:22 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:22 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:22 [drm:drm_mode_addfb2 [drm]] [FB:110]
>Oct 25 01:16:22 [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000035417744
>Oct 25 01:16:22 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000a7a225a5 state to 0000000035417744
>Oct 25 01:16:22 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000fb2fe074 state to 0000000035417744
>Oct 25 01:16:22 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:28:plane 1A] state 00000000fb2fe074
>Oct 25 01:16:22 [drm:drm_atomic_check_only [drm]] checking 0000000035417744
>Oct 25 01:16:22 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 110
>Oct 25 01:16:22 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:22 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45
>Oct 25 01:16:22 [drm:drm_atomic_nonblocking_commit [drm]] committing 0000000035417744 nonblocking
>Oct 25 01:16:22 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:22 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000035417744
>Oct 25 01:16:22 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000035417744
>Oct 25 01:16:22 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:113] for [PLANE:42:cursor A] state 00000000e396bf6c
>Oct 25 01:16:22 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 113
>Oct 25 01:16:22 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:22 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:22 [drm:drm_mode_addfb2 [drm]] [FB:114]
>Oct 25 01:16:22 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000b7798c85
>Oct 25 01:16:22 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 000000002480bd06 state to 00000000b7798c85
>Oct 25 01:16:22 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 0000000037e40ab3 state to 00000000b7798c85
>Oct 25 01:16:22 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:114] for [PLANE:28:plane 1A] state 0000000037e40ab3
>Oct 25 01:16:22 [drm:drm_atomic_check_only [drm]] checking 00000000b7798c85
>Oct 25 01:16:22 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 114
>Oct 25 01:16:22 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:22 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45
>Oct 25 01:16:22 [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000b7798c85 nonblocking
>Oct 25 01:16:22 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:22 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000b7798c85
>Oct 25 01:16:22 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000b7798c85
>Oct 25 01:16:22 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:113] for [PLANE:42:cursor A] state 0000000009c70f94
>Oct 25 01:16:22 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 113
>Oct 25 01:16:22 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:22 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:22 [drm:drm_mode_addfb2 [drm]] [FB:110]
>Oct 25 01:16:22 [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000008bde6312
>Oct 25 01:16:22 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000b7798c85 state to 000000008bde6312
>Oct 25 01:16:22 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000fb2fe074 state to 000000008bde6312
>Oct 25 01:16:22 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:28:plane 1A] state 00000000fb2fe074
>Oct 25 01:16:22 [drm:drm_atomic_check_only [drm]] checking 000000008bde6312
>Oct 25 01:16:22 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 110
>Oct 25 01:16:22 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:22 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45
>Oct 25 01:16:22 [drm:drm_atomic_nonblocking_commit [drm]] committing 000000008bde6312 nonblocking
>Oct 25 01:16:22 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:22 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000008bde6312
>Oct 25 01:16:22 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000008bde6312
>Oct 25 01:16:22 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:113] for [PLANE:42:cursor A] state 0000000020e68c00
>Oct 25 01:16:22 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 113
>Oct 25 01:16:22 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:22 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:22 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:113] for [PLANE:42:cursor A] state 0000000009c70f94
>Oct 25 01:16:22 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 113
>Oct 25 01:16:22 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:22 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:22 [drm:drm_mode_addfb2 [drm]] [FB:114]
>Oct 25 01:16:22 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000a7a225a5
>Oct 25 01:16:22 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 0000000035417744 state to 00000000a7a225a5
>Oct 25 01:16:22 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 000000006166d1c9 state to 00000000a7a225a5
>Oct 25 01:16:22 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:114] for [PLANE:28:plane 1A] state 000000006166d1c9
>Oct 25 01:16:22 [drm:drm_atomic_check_only [drm]] checking 00000000a7a225a5
>Oct 25 01:16:22 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 114
>Oct 25 01:16:22 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:22 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45
>Oct 25 01:16:22 [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000a7a225a5 nonblocking
>Oct 25 01:16:22 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:22 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000a7a225a5
>Oct 25 01:16:22 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000a7a225a5
>Oct 25 01:16:22 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:113] for [PLANE:42:cursor A] state 00000000e396bf6c
>Oct 25 01:16:22 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 113
>Oct 25 01:16:22 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:22 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:22 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:113] for [PLANE:42:cursor A] state 0000000009c70f94
>Oct 25 01:16:22 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 113
>Oct 25 01:16:22 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:22 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:22 [drm:drm_mode_addfb2 [drm]] [FB:110]
>Oct 25 01:16:22 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000f8616964
>Oct 25 01:16:22 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000a7a225a5 state to 00000000f8616964
>Oct 25 01:16:22 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000b1fe57dd state to 00000000f8616964
>Oct 25 01:16:22 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:28:plane 1A] state 00000000b1fe57dd
>Oct 25 01:16:22 [drm:drm_atomic_check_only [drm]] checking 00000000f8616964
>Oct 25 01:16:22 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 110
>Oct 25 01:16:22 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:22 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45
>Oct 25 01:16:22 [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000f8616964 nonblocking
>Oct 25 01:16:22 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:22 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000f8616964
>Oct 25 01:16:22 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000f8616964
>Oct 25 01:16:22 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:113] for [PLANE:42:cursor A] state 0000000020e68c00
>Oct 25 01:16:22 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 113
>Oct 25 01:16:22 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:22 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:22 [drm:drm_mode_addfb2 [drm]] [FB:114]
>Oct 25 01:16:22 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000b7798c85
>Oct 25 01:16:22 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 000000008bde6312 state to 00000000b7798c85
>Oct 25 01:16:22 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 000000006166d1c9 state to 00000000b7798c85
>Oct 25 01:16:22 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:114] for [PLANE:28:plane 1A] state 000000006166d1c9
>Oct 25 01:16:22 [drm:drm_atomic_check_only [drm]] checking 00000000b7798c85
>Oct 25 01:16:22 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 114
>Oct 25 01:16:22 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:22 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45
>Oct 25 01:16:22 [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000b7798c85 nonblocking
>Oct 25 01:16:22 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:22 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000b7798c85
>Oct 25 01:16:22 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000b7798c85
>Oct 25 01:16:22 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:113] for [PLANE:42:cursor A] state 00000000e396bf6c
>Oct 25 01:16:22 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 113
>Oct 25 01:16:22 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:22 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:22 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:113] for [PLANE:42:cursor A] state 0000000020e68c00
>Oct 25 01:16:22 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 113
>Oct 25 01:16:22 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:22 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:22 [drm:drm_mode_addfb2 [drm]] [FB:110]
>Oct 25 01:16:22 [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000002480bd06
>Oct 25 01:16:22 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000b7798c85 state to 000000002480bd06
>Oct 25 01:16:22 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000fb2fe074 state to 000000002480bd06
>Oct 25 01:16:22 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:28:plane 1A] state 00000000fb2fe074
>Oct 25 01:16:22 [drm:drm_atomic_check_only [drm]] checking 000000002480bd06
>Oct 25 01:16:22 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 110
>Oct 25 01:16:22 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:22 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45
>Oct 25 01:16:22 [drm:drm_atomic_nonblocking_commit [drm]] committing 000000002480bd06 nonblocking
>Oct 25 01:16:22 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:22 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000002480bd06
>Oct 25 01:16:22 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000002480bd06
>Oct 25 01:16:22 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:113] for [PLANE:42:cursor A] state 0000000009c70f94
>Oct 25 01:16:22 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 113
>Oct 25 01:16:22 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:22 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:22 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:113] for [PLANE:42:cursor A] state 0000000020e68c00
>Oct 25 01:16:22 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 113
>Oct 25 01:16:22 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:22 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:22 [drm:drm_mode_addfb2 [drm]] [FB:114]
>Oct 25 01:16:22 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000a7a225a5
>Oct 25 01:16:22 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000f8616964 state to 00000000a7a225a5
>Oct 25 01:16:22 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 0000000037e40ab3 state to 00000000a7a225a5
>Oct 25 01:16:22 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:114] for [PLANE:28:plane 1A] state 0000000037e40ab3
>Oct 25 01:16:22 [drm:drm_atomic_check_only [drm]] checking 00000000a7a225a5
>Oct 25 01:16:22 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 114
>Oct 25 01:16:22 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:22 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45
>Oct 25 01:16:22 [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000a7a225a5 nonblocking
>Oct 25 01:16:22 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:22 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000a7a225a5
>Oct 25 01:16:22 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000a7a225a5
>Oct 25 01:16:22 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:113] for [PLANE:42:cursor A] state 00000000e396bf6c
>Oct 25 01:16:22 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 113
>Oct 25 01:16:22 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:22 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:22 [drm:drm_mode_addfb2 [drm]] [FB:110]
>Oct 25 01:16:22 [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000035417744
>Oct 25 01:16:22 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000a7a225a5 state to 0000000035417744
>Oct 25 01:16:22 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000fb2fe074 state to 0000000035417744
>Oct 25 01:16:22 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:28:plane 1A] state 00000000fb2fe074
>Oct 25 01:16:22 [drm:drm_atomic_check_only [drm]] checking 0000000035417744
>Oct 25 01:16:22 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 110
>Oct 25 01:16:22 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:22 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45
>Oct 25 01:16:22 [drm:drm_atomic_nonblocking_commit [drm]] committing 0000000035417744 nonblocking
>Oct 25 01:16:22 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:22 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000035417744
>Oct 25 01:16:22 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000035417744
>Oct 25 01:16:22 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:113] for [PLANE:42:cursor A] state 0000000009c70f94
>Oct 25 01:16:22 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 113
>Oct 25 01:16:22 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:22 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:22 [drm:drm_mode_addfb2 [drm]] [FB:114]
>Oct 25 01:16:22 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000b7798c85
>Oct 25 01:16:22 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 000000002480bd06 state to 00000000b7798c85
>Oct 25 01:16:22 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 000000006166d1c9 state to 00000000b7798c85
>Oct 25 01:16:22 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:114] for [PLANE:28:plane 1A] state 000000006166d1c9
>Oct 25 01:16:22 [drm:drm_atomic_check_only [drm]] checking 00000000b7798c85
>Oct 25 01:16:22 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 114
>Oct 25 01:16:22 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:22 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45
>Oct 25 01:16:22 [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000b7798c85 nonblocking
>Oct 25 01:16:22 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:22 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000b7798c85
>Oct 25 01:16:22 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000b7798c85
>Oct 25 01:16:22 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:113] for [PLANE:42:cursor A] state 0000000020e68c00
>Oct 25 01:16:22 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 113
>Oct 25 01:16:22 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:22 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:22 [drm:drm_mode_addfb2 [drm]] [FB:110]
>Oct 25 01:16:22 [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000008bde6312
>Oct 25 01:16:22 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000b7798c85 state to 000000008bde6312
>Oct 25 01:16:22 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000b1fe57dd state to 000000008bde6312
>Oct 25 01:16:22 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:28:plane 1A] state 00000000b1fe57dd
>Oct 25 01:16:22 [drm:drm_atomic_check_only [drm]] checking 000000008bde6312
>Oct 25 01:16:22 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 110
>Oct 25 01:16:22 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:22 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45
>Oct 25 01:16:22 [drm:drm_atomic_nonblocking_commit [drm]] committing 000000008bde6312 nonblocking
>Oct 25 01:16:22 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:22 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000008bde6312
>Oct 25 01:16:22 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000e53e1ae0
>Oct 25 01:16:22 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000e53e1ae0
>Oct 25 01:16:22 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000008bde6312
>Oct 25 01:16:22 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000e53e1ae0
>Oct 25 01:16:22 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000e53e1ae0
>Oct 25 01:16:22 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000e53e1ae0
>Oct 25 01:16:22 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000e53e1ae0
>Oct 25 01:16:22 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:113] for [PLANE:42:cursor A] state 00000000d882e53e
>Oct 25 01:16:22 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 113
>Oct 25 01:16:22 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:22 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:22 [drm:drm_mode_addfb2 [drm]] [FB:114]
>Oct 25 01:16:22 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000e53e1ae0
>Oct 25 01:16:22 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000f1ecca12 state to 00000000e53e1ae0
>Oct 25 01:16:22 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 000000008c84e646 state to 00000000e53e1ae0
>Oct 25 01:16:22 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:114] for [PLANE:28:plane 1A] state 000000008c84e646
>Oct 25 01:16:22 [drm:drm_atomic_check_only [drm]] checking 00000000e53e1ae0
>Oct 25 01:16:22 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 114
>Oct 25 01:16:22 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:22 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45
>Oct 25 01:16:22 [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000e53e1ae0 nonblocking
>Oct 25 01:16:22 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:22 [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000006a1c1622
>Oct 25 01:16:22 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000006a1c1622
>Oct 25 01:16:22 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000e53e1ae0
>Oct 25 01:16:22 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000e53e1ae0
>Oct 25 01:16:22 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000006a1c1622
>Oct 25 01:16:22 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000006a1c1622
>Oct 25 01:16:22 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000006a1c1622
>Oct 25 01:16:22 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000006a1c1622
>Oct 25 01:16:22 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:113] for [PLANE:42:cursor A] state 00000000fb161e43
>Oct 25 01:16:22 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 113
>Oct 25 01:16:22 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:22 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:22 [drm:drm_mode_addfb2 [drm]] [FB:110]
>Oct 25 01:16:22 [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000006a1c1622
>Oct 25 01:16:22 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000e53e1ae0 state to 000000006a1c1622
>Oct 25 01:16:22 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000cd328e60 state to 000000006a1c1622
>Oct 25 01:16:22 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:28:plane 1A] state 00000000cd328e60
>Oct 25 01:16:22 [drm:drm_atomic_check_only [drm]] checking 000000006a1c1622
>Oct 25 01:16:22 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 110
>Oct 25 01:16:22 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:22 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45
>Oct 25 01:16:22 [drm:drm_atomic_nonblocking_commit [drm]] committing 000000006a1c1622 nonblocking
>Oct 25 01:16:22 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:22 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000006a1c1622
>Oct 25 01:16:22 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000006a1c1622
>Oct 25 01:16:22 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:113] for [PLANE:42:cursor A] state 00000000e2388a2b
>Oct 25 01:16:22 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 113
>Oct 25 01:16:22 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:22 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:22 [drm:drm_mode_addfb2 [drm]] [FB:114]
>Oct 25 01:16:22 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000a7a225a5
>Oct 25 01:16:22 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 0000000035417744 state to 00000000a7a225a5
>Oct 25 01:16:22 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000e74eab73 state to 00000000a7a225a5
>Oct 25 01:16:22 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:114] for [PLANE:28:plane 1A] state 00000000e74eab73
>Oct 25 01:16:22 [drm:drm_atomic_check_only [drm]] checking 00000000a7a225a5
>Oct 25 01:16:22 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 114
>Oct 25 01:16:22 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:22 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45
>Oct 25 01:16:22 [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000a7a225a5 nonblocking
>Oct 25 01:16:22 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:22 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000f8616964
>Oct 25 01:16:22 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000a7a225a5
>Oct 25 01:16:22 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000a7a225a5
>Oct 25 01:16:22 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000f8616964
>Oct 25 01:16:22 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000f8616964
>Oct 25 01:16:22 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000f8616964
>Oct 25 01:16:22 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000f8616964
>Oct 25 01:16:22 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000f8616964
>Oct 25 01:16:22 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:113] for [PLANE:42:cursor A] state 00000000e396bf6c
>Oct 25 01:16:22 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 113
>Oct 25 01:16:22 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:22 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:22 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:113] for [PLANE:42:cursor A] state 000000004b50eded
>Oct 25 01:16:22 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 113
>Oct 25 01:16:22 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:22 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:22 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:113] for [PLANE:42:cursor A] state 00000000e396bf6c
>Oct 25 01:16:22 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 113
>Oct 25 01:16:22 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:22 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:22 [drm:drm_mode_addfb2 [drm]] [FB:110]
>Oct 25 01:16:22 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000f8616964
>Oct 25 01:16:22 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000a7a225a5 state to 00000000f8616964
>Oct 25 01:16:22 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 000000002a08f491 state to 00000000f8616964
>Oct 25 01:16:22 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:28:plane 1A] state 000000002a08f491
>Oct 25 01:16:22 [drm:drm_atomic_check_only [drm]] checking 00000000f8616964
>Oct 25 01:16:22 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 110
>Oct 25 01:16:22 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:22 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45
>Oct 25 01:16:22 [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000f8616964 nonblocking
>Oct 25 01:16:22 [drm:gen8_de_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x11101010, pins 0x00000010, long 0x00000000
>Oct 25 01:16:22 [drm:intel_hpd_irq_handler [i915]] digital hpd port A - short
>Oct 25 01:16:22 [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port A - short
>Oct 25 01:16:22 [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 41 00 00 01 80 02 00 00 00 0f 0b 00
>Oct 25 01:16:22 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:22 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000f8616964
>Oct 25 01:16:22 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000b7798c85
>Oct 25 01:16:22 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000f8616964
>Oct 25 01:16:22 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000b7798c85
>Oct 25 01:16:22 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000b7798c85
>Oct 25 01:16:22 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:113] for [PLANE:42:cursor A] state 0000000009c70f94
>Oct 25 01:16:22 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 113
>Oct 25 01:16:22 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:22 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:23 [drm:gen8_de_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x11101010, pins 0x00000010, long 0x00000000
>Oct 25 01:16:23 [drm:intel_hpd_irq_handler [i915]] digital hpd port A - short
>Oct 25 01:16:23 [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port A - short
>Oct 25 01:16:23 [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 41 00 00 01 80 02 00 00 00 0f 0b 00
>Oct 25 01:16:23 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:114] for [PLANE:42:cursor A] state 00000000fb2fe074
>Oct 25 01:16:23 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 114
>Oct 25 01:16:23 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:23 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:114] for [PLANE:42:cursor A] state 0000000009c70f94
>Oct 25 01:16:23 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 114
>Oct 25 01:16:23 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:23 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:23 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:114] for [PLANE:42:cursor A] state 00000000fb2fe074
>Oct 25 01:16:23 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 114
>Oct 25 01:16:23 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:23 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:23 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:114] for [PLANE:42:cursor A] state 0000000009c70f94
>Oct 25 01:16:23 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 114
>Oct 25 01:16:23 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:23 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:23 [drm:drm_mode_addfb2 [drm]] [FB:113]
>Oct 25 01:16:23 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000b7798c85
>Oct 25 01:16:23 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 000000008bde6312 state to 00000000b7798c85
>Oct 25 01:16:23 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000aa66c66b state to 00000000b7798c85
>Oct 25 01:16:23 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:113] for [PLANE:28:plane 1A] state 00000000aa66c66b
>Oct 25 01:16:23 [drm:drm_atomic_check_only [drm]] checking 00000000b7798c85
>Oct 25 01:16:23 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 113
>Oct 25 01:16:23 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:23 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45
>Oct 25 01:16:23 [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000b7798c85 nonblocking
>Oct 25 01:16:23 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:23 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000b7798c85
>Oct 25 01:16:23 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000b7798c85
>Oct 25 01:16:23 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:114] for [PLANE:42:cursor A] state 000000004b50eded
>Oct 25 01:16:23 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 114
>Oct 25 01:16:23 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:23 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:23 [drm:gen8_de_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x11101010, pins 0x00000010, long 0x00000000
>Oct 25 01:16:23 [drm:intel_hpd_irq_handler [i915]] digital hpd port A - short
>Oct 25 01:16:23 [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port A - short
>Oct 25 01:16:23 [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 41 00 00 01 80 02 00 00 00 0f 0b 00
>Oct 25 01:16:23 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:114] for [PLANE:42:cursor A] state 0000000009c70f94
>Oct 25 01:16:23 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 114
>Oct 25 01:16:23 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:23 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:23 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:114] for [PLANE:42:cursor A] state 000000004b50eded
>Oct 25 01:16:23 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 114
>Oct 25 01:16:23 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:23 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:23 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:42:cursor A] state 000000007b0042d5
>Oct 25 01:16:23 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 110
>Oct 25 01:16:23 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:23 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:23 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:42:cursor A] state 000000004b50eded
>Oct 25 01:16:23 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 110
>Oct 25 01:16:23 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:23 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:23 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:114] for [PLANE:42:cursor A] state 00000000e396bf6c
>Oct 25 01:16:23 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 114
>Oct 25 01:16:23 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:23 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:23 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:114] for [PLANE:42:cursor A] state 000000004b50eded
>Oct 25 01:16:23 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 114
>Oct 25 01:16:23 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:23 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:23 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:114] for [PLANE:42:cursor A] state 00000000e396bf6c
>Oct 25 01:16:23 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 114
>Oct 25 01:16:23 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:23 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:23 [drm:drm_mode_addfb2 [drm]] [FB:110]
>Oct 25 01:16:23 [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000002480bd06
>Oct 25 01:16:23 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000b7798c85 state to 000000002480bd06
>Oct 25 01:16:23 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 000000008b497eb0 state to 000000002480bd06
>Oct 25 01:16:23 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:28:plane 1A] state 000000008b497eb0
>Oct 25 01:16:23 [drm:drm_atomic_check_only [drm]] checking 000000002480bd06
>Oct 25 01:16:23 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 110
>Oct 25 01:16:23 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:23 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45
>Oct 25 01:16:23 [drm:drm_atomic_nonblocking_commit [drm]] committing 000000002480bd06 nonblocking
>Oct 25 01:16:23 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:23 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000002480bd06
>Oct 25 01:16:23 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000002480bd06
>Oct 25 01:16:23 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:114] for [PLANE:42:cursor A] state 00000000fb2fe074
>Oct 25 01:16:23 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 114
>Oct 25 01:16:23 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:23 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:23 [drm:drm_mode_addfb2 [drm]] [FB:113]
>Oct 25 01:16:23 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000a7a225a5
>Oct 25 01:16:23 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000f8616964 state to 00000000a7a225a5
>Oct 25 01:16:23 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000e74eab73 state to 00000000a7a225a5
>Oct 25 01:16:23 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:113] for [PLANE:28:plane 1A] state 00000000e74eab73
>Oct 25 01:16:23 [drm:drm_atomic_check_only [drm]] checking 00000000a7a225a5
>Oct 25 01:16:23 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 113
>Oct 25 01:16:23 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:23 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45
>Oct 25 01:16:23 [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000a7a225a5 nonblocking
>Oct 25 01:16:23 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:23 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000a7a225a5
>Oct 25 01:16:23 [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000035417744
>Oct 25 01:16:23 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000035417744
>Oct 25 01:16:23 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000035417744
>Oct 25 01:16:23 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000a7a225a5
>Oct 25 01:16:23 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000035417744
>Oct 25 01:16:23 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000035417744
>Oct 25 01:16:23 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000035417744
>Oct 25 01:16:23 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:114] for [PLANE:42:cursor A] state 000000004b50eded
>Oct 25 01:16:23 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 114
>Oct 25 01:16:23 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:23 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:23 [drm:drm_mode_addfb2 [drm]] [FB:110]
>Oct 25 01:16:23 [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000035417744
>Oct 25 01:16:23 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000a7a225a5 state to 0000000035417744
>Oct 25 01:16:23 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 000000006166d1c9 state to 0000000035417744
>Oct 25 01:16:23 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:28:plane 1A] state 000000006166d1c9
>Oct 25 01:16:23 [drm:drm_atomic_check_only [drm]] checking 0000000035417744
>Oct 25 01:16:23 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 110
>Oct 25 01:16:23 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:23 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45
>Oct 25 01:16:23 [drm:drm_atomic_nonblocking_commit [drm]] committing 0000000035417744 nonblocking
>Oct 25 01:16:23 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:23 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000b7798c85
>Oct 25 01:16:23 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000035417744
>Oct 25 01:16:23 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000035417744
>Oct 25 01:16:23 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000b7798c85
>Oct 25 01:16:23 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000b7798c85
>Oct 25 01:16:23 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000b7798c85
>Oct 25 01:16:23 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000b7798c85
>Oct 25 01:16:23 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000b7798c85
>Oct 25 01:16:23 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:114] for [PLANE:42:cursor A] state 00000000e396bf6c
>Oct 25 01:16:23 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 114
>Oct 25 01:16:23 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:23 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:23 [drm:drm_mode_addfb2 [drm]] [FB:113]
>Oct 25 01:16:23 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000b7798c85
>Oct 25 01:16:23 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 000000002480bd06 state to 00000000b7798c85
>Oct 25 01:16:23 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 0000000037e40ab3 state to 00000000b7798c85
>Oct 25 01:16:23 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:113] for [PLANE:28:plane 1A] state 0000000037e40ab3
>Oct 25 01:16:23 [drm:drm_atomic_check_only [drm]] checking 00000000b7798c85
>Oct 25 01:16:23 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 113
>Oct 25 01:16:23 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:23 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45
>Oct 25 01:16:23 [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000b7798c85 nonblocking
>Oct 25 01:16:23 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:23 [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000008bde6312
>Oct 25 01:16:23 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000b7798c85
>Oct 25 01:16:23 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000b7798c85
>Oct 25 01:16:23 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000008bde6312
>Oct 25 01:16:23 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000008bde6312
>Oct 25 01:16:23 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000008bde6312
>Oct 25 01:16:23 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000008bde6312
>Oct 25 01:16:23 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000008bde6312
>Oct 25 01:16:23 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:114] for [PLANE:42:cursor A] state 00000000fb2fe074
>Oct 25 01:16:23 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 114
>Oct 25 01:16:23 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:23 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:23 [drm:drm_mode_addfb2 [drm]] [FB:110]
>Oct 25 01:16:23 [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000008bde6312
>Oct 25 01:16:23 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000b7798c85 state to 000000008bde6312
>Oct 25 01:16:23 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 0000000083150a5b state to 000000008bde6312
>Oct 25 01:16:23 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:28:plane 1A] state 0000000083150a5b
>Oct 25 01:16:23 [drm:drm_atomic_check_only [drm]] checking 000000008bde6312
>Oct 25 01:16:23 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 110
>Oct 25 01:16:23 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:23 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45
>Oct 25 01:16:23 [drm:drm_atomic_nonblocking_commit [drm]] committing 000000008bde6312 nonblocking
>Oct 25 01:16:23 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:23 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000a7a225a5
>Oct 25 01:16:23 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000008bde6312
>Oct 25 01:16:23 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000008bde6312
>Oct 25 01:16:23 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000a7a225a5
>Oct 25 01:16:23 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000a7a225a5
>Oct 25 01:16:23 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000a7a225a5
>Oct 25 01:16:23 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000a7a225a5
>Oct 25 01:16:23 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000a7a225a5
>Oct 25 01:16:23 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:114] for [PLANE:42:cursor A] state 000000004b50eded
>Oct 25 01:16:23 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 114
>Oct 25 01:16:23 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:23 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:23 [drm:drm_mode_addfb2 [drm]] [FB:113]
>Oct 25 01:16:23 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000a7a225a5
>Oct 25 01:16:23 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 0000000035417744 state to 00000000a7a225a5
>Oct 25 01:16:23 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000b1fe57dd state to 00000000a7a225a5
>Oct 25 01:16:23 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:113] for [PLANE:28:plane 1A] state 00000000b1fe57dd
>Oct 25 01:16:23 [drm:drm_atomic_check_only [drm]] checking 00000000a7a225a5
>Oct 25 01:16:23 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 113
>Oct 25 01:16:23 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:23 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45
>Oct 25 01:16:23 [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000a7a225a5 nonblocking
>Oct 25 01:16:23 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:23 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000a7a225a5
>Oct 25 01:16:23 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000a7a225a5
>Oct 25 01:16:23 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:114] for [PLANE:42:cursor A] state 00000000e396bf6c
>Oct 25 01:16:23 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 114
>Oct 25 01:16:23 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:23 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:23 [drm:drm_mode_addfb2 [drm]] [FB:110]
>Oct 25 01:16:23 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000f8616964
>Oct 25 01:16:23 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000a7a225a5 state to 00000000f8616964
>Oct 25 01:16:23 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 000000008b497eb0 state to 00000000f8616964
>Oct 25 01:16:23 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:28:plane 1A] state 000000008b497eb0
>Oct 25 01:16:23 [drm:drm_atomic_check_only [drm]] checking 00000000f8616964
>Oct 25 01:16:23 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 110
>Oct 25 01:16:23 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:23 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45
>Oct 25 01:16:23 [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000f8616964 nonblocking
>Oct 25 01:16:23 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:23 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000f8616964
>Oct 25 01:16:23 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000b7798c85
>Oct 25 01:16:23 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000f8616964
>Oct 25 01:16:23 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000b7798c85
>Oct 25 01:16:23 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000b7798c85
>Oct 25 01:16:23 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:114] for [PLANE:42:cursor A] state 00000000fb2fe074
>Oct 25 01:16:23 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 114
>Oct 25 01:16:23 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:23 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:23 [drm:drm_mode_addfb2 [drm]] [FB:113]
>Oct 25 01:16:23 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000b7798c85
>Oct 25 01:16:23 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 000000008bde6312 state to 00000000b7798c85
>Oct 25 01:16:23 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000f87b65b5 state to 00000000b7798c85
>Oct 25 01:16:23 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:113] for [PLANE:28:plane 1A] state 00000000f87b65b5
>Oct 25 01:16:23 [drm:drm_atomic_check_only [drm]] checking 00000000b7798c85
>Oct 25 01:16:23 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 113
>Oct 25 01:16:23 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:23 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45
>Oct 25 01:16:23 [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000b7798c85 nonblocking
>Oct 25 01:16:23 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:23 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000b7798c85
>Oct 25 01:16:23 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000b7798c85
>Oct 25 01:16:23 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:42:cursor A] state 000000006166d1c9
>Oct 25 01:16:23 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 110
>Oct 25 01:16:23 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:23 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:23 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:42:cursor A] state 00000000fb2fe074
>Oct 25 01:16:23 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 110
>Oct 25 01:16:23 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:23 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:23 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:42:cursor A] state 000000006166d1c9
>Oct 25 01:16:23 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 110
>Oct 25 01:16:23 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:23 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:23 [drm:drm_mode_addfb2 [drm]] [FB:114]
>Oct 25 01:16:23 [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000002480bd06
>Oct 25 01:16:23 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000b7798c85 state to 000000002480bd06
>Oct 25 01:16:23 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 0000000083150a5b state to 000000002480bd06
>Oct 25 01:16:23 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:114] for [PLANE:28:plane 1A] state 0000000083150a5b
>Oct 25 01:16:23 [drm:drm_atomic_check_only [drm]] checking 000000002480bd06
>Oct 25 01:16:23 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 114
>Oct 25 01:16:23 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:23 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45
>Oct 25 01:16:23 [drm:drm_atomic_nonblocking_commit [drm]] committing 000000002480bd06 nonblocking
>Oct 25 01:16:23 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:42:cursor A] state 00000000b1fe57dd
>Oct 25 01:16:23 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 110
>Oct 25 01:16:23 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:23 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:23 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:23 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000002480bd06
>Oct 25 01:16:23 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000002480bd06
>Oct 25 01:16:23 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:42:cursor A] state 00000000e396bf6c
>Oct 25 01:16:23 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 110
>Oct 25 01:16:23 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:23 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:23 [drm:drm_mode_addfb2 [drm]] [FB:113]
>Oct 25 01:16:23 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000a7a225a5
>Oct 25 01:16:23 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000f8616964 state to 00000000a7a225a5
>Oct 25 01:16:23 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000e74eab73 state to 00000000a7a225a5
>Oct 25 01:16:23 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:113] for [PLANE:28:plane 1A] state 00000000e74eab73
>Oct 25 01:16:23 [drm:drm_atomic_check_only [drm]] checking 00000000a7a225a5
>Oct 25 01:16:23 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 113
>Oct 25 01:16:23 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:23 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45
>Oct 25 01:16:23 [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000a7a225a5 nonblocking
>Oct 25 01:16:23 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:23 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000a7a225a5
>Oct 25 01:16:23 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000a7a225a5
>Oct 25 01:16:24 [drm:gen8_de_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x11101010, pins 0x00000010, long 0x00000000
>Oct 25 01:16:24 [drm:intel_hpd_irq_handler [i915]] digital hpd port A - short
>Oct 25 01:16:24 [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port A - short
>Oct 25 01:16:24 [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 41 00 00 01 80 02 00 00 00 0f 0b 00
>Oct 25 01:16:24 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:42:cursor A] state 00000000fb2fe074
>Oct 25 01:16:24 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 110
>Oct 25 01:16:24 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:24 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:24 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:42:cursor A] state 00000000e396bf6c
>Oct 25 01:16:24 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 110
>Oct 25 01:16:24 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:24 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:24 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:42:cursor A] state 00000000fb2fe074
>Oct 25 01:16:24 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 110
>Oct 25 01:16:24 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:24 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:24 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:42:cursor A] state 00000000e396bf6c
>Oct 25 01:16:24 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 110
>Oct 25 01:16:24 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:24 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:24 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:42:cursor A] state 00000000fb2fe074
>Oct 25 01:16:24 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 110
>Oct 25 01:16:24 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:24 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:24 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:42:cursor A] state 00000000e396bf6c
>Oct 25 01:16:24 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 110
>Oct 25 01:16:24 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:24 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:24 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:42:cursor A] state 00000000fb2fe074
>Oct 25 01:16:24 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 110
>Oct 25 01:16:24 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:24 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:24 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:42:cursor A] state 00000000e396bf6c
>Oct 25 01:16:24 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 110
>Oct 25 01:16:24 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:24 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:24 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:42:cursor A] state 00000000fb2fe074
>Oct 25 01:16:24 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 110
>Oct 25 01:16:24 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:24 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:24 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:42:cursor A] state 00000000e396bf6c
>Oct 25 01:16:24 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 110
>Oct 25 01:16:24 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:24 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:24 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:42:cursor A] state 00000000fb2fe074
>Oct 25 01:16:24 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 110
>Oct 25 01:16:24 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:24 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:24 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:42:cursor A] state 00000000e396bf6c
>Oct 25 01:16:24 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 110
>Oct 25 01:16:24 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:24 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:24 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:42:cursor A] state 00000000fb2fe074
>Oct 25 01:16:24 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 110
>Oct 25 01:16:24 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:24 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:24 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:42:cursor A] state 00000000e396bf6c
>Oct 25 01:16:24 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 110
>Oct 25 01:16:24 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:24 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:24 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:42:cursor A] state 00000000fb2fe074
>Oct 25 01:16:24 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 110
>Oct 25 01:16:24 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:24 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:24 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:42:cursor A] state 00000000e396bf6c
>Oct 25 01:16:24 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 110
>Oct 25 01:16:24 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:24 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:24 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:114] for [PLANE:42:cursor A] state 00000000f87b65b5
>Oct 25 01:16:24 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 114
>Oct 25 01:16:24 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:24 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:114] for [PLANE:42:cursor A] state 00000000e396bf6c
>Oct 25 01:16:24 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 114
>Oct 25 01:16:24 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:24 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:24 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:114] for [PLANE:42:cursor A] state 00000000f87b65b5
>Oct 25 01:16:24 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 114
>Oct 25 01:16:24 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:24 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:24 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:114] for [PLANE:42:cursor A] state 00000000e396bf6c
>Oct 25 01:16:24 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 114
>Oct 25 01:16:24 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:24 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:24 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:42:cursor A] state 00000000aa66c66b
>Oct 25 01:16:24 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 110
>Oct 25 01:16:24 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:24 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:24 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:42:cursor A] state 00000000e396bf6c
>Oct 25 01:16:24 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 110
>Oct 25 01:16:24 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:24 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:24 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:114] for [PLANE:42:cursor A] state 00000000fb2fe074
>Oct 25 01:16:24 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 114
>Oct 25 01:16:24 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:24 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:24 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:114] for [PLANE:42:cursor A] state 00000000e396bf6c
>Oct 25 01:16:24 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 114
>Oct 25 01:16:24 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:24 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:24 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:114] for [PLANE:42:cursor A] state 00000000fb2fe074
>Oct 25 01:16:24 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 114
>Oct 25 01:16:24 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:24 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:24 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:114] for [PLANE:42:cursor A] state 00000000e396bf6c
>Oct 25 01:16:24 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 114
>Oct 25 01:16:24 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:24 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:24 [drm:drm_mode_addfb2 [drm]] [FB:110]
>Oct 25 01:16:24 [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000035417744
>Oct 25 01:16:24 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000a7a225a5 state to 0000000035417744
>Oct 25 01:16:24 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 0000000083150a5b state to 0000000035417744
>Oct 25 01:16:24 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:28:plane 1A] state 0000000083150a5b
>Oct 25 01:16:24 [drm:drm_atomic_check_only [drm]] checking 0000000035417744
>Oct 25 01:16:24 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 110
>Oct 25 01:16:24 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:24 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45
>Oct 25 01:16:24 [drm:drm_atomic_nonblocking_commit [drm]] committing 0000000035417744 nonblocking
>Oct 25 01:16:24 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:24 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000035417744
>Oct 25 01:16:24 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000035417744
>Oct 25 01:16:24 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:114] for [PLANE:42:cursor A] state 00000000b1fe57dd
>Oct 25 01:16:24 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 114
>Oct 25 01:16:24 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:24 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:24 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:114] for [PLANE:42:cursor A] state 00000000e396bf6c
>Oct 25 01:16:24 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 114
>Oct 25 01:16:24 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:24 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:24 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:114] for [PLANE:42:cursor A] state 00000000b1fe57dd
>Oct 25 01:16:24 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 114
>Oct 25 01:16:24 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:24 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:24 [drm:gen8_de_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x11101010, pins 0x00000010, long 0x00000000
>Oct 25 01:16:24 [drm:intel_hpd_irq_handler [i915]] digital hpd port A - short
>Oct 25 01:16:24 [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port A - short
>Oct 25 01:16:24 [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 41 00 00 01 80 02 00 00 00 0f 0b 00
>Oct 25 01:16:24 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:114] for [PLANE:42:cursor A] state 00000000e396bf6c
>Oct 25 01:16:24 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 114
>Oct 25 01:16:24 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:24 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:24 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:113] for [PLANE:42:cursor A] state 00000000f87b65b5
>Oct 25 01:16:24 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 113
>Oct 25 01:16:24 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:24 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:24 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:113] for [PLANE:42:cursor A] state 00000000e396bf6c
>Oct 25 01:16:24 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 113
>Oct 25 01:16:24 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:24 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:24 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:113] for [PLANE:42:cursor A] state 00000000f87b65b5
>Oct 25 01:16:24 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 113
>Oct 25 01:16:24 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:24 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:24 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:113] for [PLANE:42:cursor A] state 00000000e396bf6c
>Oct 25 01:16:24 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 113
>Oct 25 01:16:24 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:24 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:24 [drm:drm_mode_addfb2 [drm]] [FB:114]
>Oct 25 01:16:24 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000b7798c85
>Oct 25 01:16:24 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 000000002480bd06 state to 00000000b7798c85
>Oct 25 01:16:24 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 000000007b0042d5 state to 00000000b7798c85
>Oct 25 01:16:24 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:114] for [PLANE:28:plane 1A] state 000000007b0042d5
>Oct 25 01:16:24 [drm:drm_atomic_check_only [drm]] checking 00000000b7798c85
>Oct 25 01:16:24 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 114
>Oct 25 01:16:24 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:24 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45
>Oct 25 01:16:24 [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000b7798c85 nonblocking
>Oct 25 01:16:24 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:24 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000b7798c85
>Oct 25 01:16:24 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000b7798c85
>Oct 25 01:16:24 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:113] for [PLANE:42:cursor A] state 00000000fb2fe074
>Oct 25 01:16:24 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 113
>Oct 25 01:16:24 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:24 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:24 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:113] for [PLANE:42:cursor A] state 00000000e396bf6c
>Oct 25 01:16:24 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 113
>Oct 25 01:16:24 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:24 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:25 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:113] for [PLANE:42:cursor A] state 00000000fb2fe074
>Oct 25 01:16:25 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 113
>Oct 25 01:16:25 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:25 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:25 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:113] for [PLANE:42:cursor A] state 00000000e396bf6c
>Oct 25 01:16:25 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 113
>Oct 25 01:16:25 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:25 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:25 [drm:drm_mode_addfb2 [drm]] [FB:110]
>Oct 25 01:16:25 [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000008bde6312
>Oct 25 01:16:25 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000b7798c85 state to 000000008bde6312
>Oct 25 01:16:25 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000aa66c66b state to 000000008bde6312
>Oct 25 01:16:25 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:28:plane 1A] state 00000000aa66c66b
>Oct 25 01:16:25 [drm:drm_atomic_check_only [drm]] checking 000000008bde6312
>Oct 25 01:16:25 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 110
>Oct 25 01:16:25 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:25 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45
>Oct 25 01:16:25 [drm:drm_atomic_nonblocking_commit [drm]] committing 000000008bde6312 nonblocking
>Oct 25 01:16:25 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:25 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000a7a225a5
>Oct 25 01:16:25 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000008bde6312
>Oct 25 01:16:25 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000008bde6312
>Oct 25 01:16:25 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000a7a225a5
>Oct 25 01:16:25 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000a7a225a5
>Oct 25 01:16:25 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000a7a225a5
>Oct 25 01:16:25 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000a7a225a5
>Oct 25 01:16:25 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000a7a225a5
>Oct 25 01:16:25 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:113] for [PLANE:42:cursor A] state 00000000f87b65b5
>Oct 25 01:16:25 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 113
>Oct 25 01:16:25 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:25 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:25 [drm:drm_mode_addfb2 [drm]] [FB:114]
>Oct 25 01:16:25 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000a7a225a5
>Oct 25 01:16:25 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 0000000035417744 state to 00000000a7a225a5
>Oct 25 01:16:25 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 000000008b497eb0 state to 00000000a7a225a5
>Oct 25 01:16:25 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:114] for [PLANE:28:plane 1A] state 000000008b497eb0
>Oct 25 01:16:25 [drm:drm_atomic_check_only [drm]] checking 00000000a7a225a5
>Oct 25 01:16:25 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 114
>Oct 25 01:16:25 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:25 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45
>Oct 25 01:16:25 [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000a7a225a5 nonblocking
>Oct 25 01:16:25 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:25 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000f8616964
>Oct 25 01:16:25 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000f8616964
>Oct 25 01:16:25 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000a7a225a5
>Oct 25 01:16:25 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000a7a225a5
>Oct 25 01:16:25 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000f8616964
>Oct 25 01:16:25 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000f8616964
>Oct 25 01:16:25 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000f8616964
>Oct 25 01:16:25 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000f8616964
>Oct 25 01:16:25 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:113] for [PLANE:42:cursor A] state 00000000fb2fe074
>Oct 25 01:16:25 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 113
>Oct 25 01:16:25 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:25 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:25 [drm:drm_mode_addfb2 [drm]] [FB:110]
>Oct 25 01:16:25 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000f8616964
>Oct 25 01:16:25 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000a7a225a5 state to 00000000f8616964
>Oct 25 01:16:25 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000c1050601 state to 00000000f8616964
>Oct 25 01:16:25 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:28:plane 1A] state 00000000c1050601
>Oct 25 01:16:25 [drm:drm_atomic_check_only [drm]] checking 00000000f8616964
>Oct 25 01:16:25 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 110
>Oct 25 01:16:25 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:25 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45
>Oct 25 01:16:25 [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000f8616964 nonblocking
>Oct 25 01:16:25 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:25 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000b7798c85
>Oct 25 01:16:25 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000f8616964
>Oct 25 01:16:25 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000f8616964
>Oct 25 01:16:25 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000b7798c85
>Oct 25 01:16:25 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000b7798c85
>Oct 25 01:16:25 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000b7798c85
>Oct 25 01:16:25 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000b7798c85
>Oct 25 01:16:25 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000b7798c85
>Oct 25 01:16:25 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:113] for [PLANE:42:cursor A] state 00000000e396bf6c
>Oct 25 01:16:25 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 113
>Oct 25 01:16:25 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:25 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:25 [drm:drm_mode_addfb2 [drm]] [FB:114]
>Oct 25 01:16:25 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000b7798c85
>Oct 25 01:16:25 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 000000008bde6312 state to 00000000b7798c85
>Oct 25 01:16:25 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 0000000083150a5b state to 00000000b7798c85
>Oct 25 01:16:25 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:114] for [PLANE:28:plane 1A] state 0000000083150a5b
>Oct 25 01:16:25 [drm:drm_atomic_check_only [drm]] checking 00000000b7798c85
>Oct 25 01:16:25 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 114
>Oct 25 01:16:25 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:25 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45
>Oct 25 01:16:25 [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000b7798c85 nonblocking
>Oct 25 01:16:25 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:25 [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000002480bd06
>Oct 25 01:16:25 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000b7798c85
>Oct 25 01:16:25 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000b7798c85
>Oct 25 01:16:25 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000002480bd06
>Oct 25 01:16:25 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000002480bd06
>Oct 25 01:16:25 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000002480bd06
>Oct 25 01:16:25 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000002480bd06
>Oct 25 01:16:25 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000002480bd06
>Oct 25 01:16:25 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:113] for [PLANE:42:cursor A] state 00000000f87b65b5
>Oct 25 01:16:25 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 113
>Oct 25 01:16:25 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:25 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:25 [drm:drm_mode_addfb2 [drm]] [FB:110]
>Oct 25 01:16:25 [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000002480bd06
>Oct 25 01:16:25 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000b7798c85 state to 000000002480bd06
>Oct 25 01:16:25 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 000000004b50eded state to 000000002480bd06
>Oct 25 01:16:25 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:28:plane 1A] state 000000004b50eded
>Oct 25 01:16:25 [drm:drm_atomic_check_only [drm]] checking 000000002480bd06
>Oct 25 01:16:25 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 110
>Oct 25 01:16:25 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:25 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45
>Oct 25 01:16:25 [drm:drm_atomic_nonblocking_commit [drm]] committing 000000002480bd06 nonblocking
>Oct 25 01:16:25 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:25 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000a7a225a5
>Oct 25 01:16:25 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000002480bd06
>Oct 25 01:16:25 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000002480bd06
>Oct 25 01:16:25 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000a7a225a5
>Oct 25 01:16:25 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000a7a225a5
>Oct 25 01:16:25 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:113] for [PLANE:42:cursor A] state 00000000fb2fe074
>Oct 25 01:16:25 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 113
>Oct 25 01:16:25 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:25 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:25 [drm:drm_mode_addfb2 [drm]] [FB:114]
>Oct 25 01:16:25 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000a7a225a5
>Oct 25 01:16:25 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000f8616964 state to 00000000a7a225a5
>Oct 25 01:16:25 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 0000000020e68c00 state to 00000000a7a225a5
>Oct 25 01:16:25 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:114] for [PLANE:28:plane 1A] state 0000000020e68c00
>Oct 25 01:16:25 [drm:drm_atomic_check_only [drm]] checking 00000000a7a225a5
>Oct 25 01:16:25 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 114
>Oct 25 01:16:25 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:25 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45
>Oct 25 01:16:25 [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000a7a225a5 nonblocking
>Oct 25 01:16:25 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:25 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000a7a225a5
>Oct 25 01:16:25 [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000035417744
>Oct 25 01:16:25 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000035417744
>Oct 25 01:16:25 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000035417744
>Oct 25 01:16:25 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000a7a225a5
>Oct 25 01:16:25 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000035417744
>Oct 25 01:16:25 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000035417744
>Oct 25 01:16:25 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000035417744
>Oct 25 01:16:25 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:113] for [PLANE:42:cursor A] state 00000000e396bf6c
>Oct 25 01:16:25 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 113
>Oct 25 01:16:25 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:25 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:25 [drm:drm_mode_addfb2 [drm]] [FB:110]
>Oct 25 01:16:25 [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000035417744
>Oct 25 01:16:25 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000a7a225a5 state to 0000000035417744
>Oct 25 01:16:25 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000c1050601 state to 0000000035417744
>Oct 25 01:16:25 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:28:plane 1A] state 00000000c1050601
>Oct 25 01:16:25 [drm:drm_atomic_check_only [drm]] checking 0000000035417744
>Oct 25 01:16:25 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 110
>Oct 25 01:16:25 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:25 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45
>Oct 25 01:16:25 [drm:drm_atomic_nonblocking_commit [drm]] committing 0000000035417744 nonblocking
>Oct 25 01:16:25 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:25 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000035417744
>Oct 25 01:16:25 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000b7798c85
>Oct 25 01:16:25 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000b7798c85
>Oct 25 01:16:25 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000035417744
>Oct 25 01:16:25 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000b7798c85
>Oct 25 01:16:25 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000b7798c85
>Oct 25 01:16:25 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000b7798c85
>Oct 25 01:16:25 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000b7798c85
>Oct 25 01:16:25 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:113] for [PLANE:42:cursor A] state 00000000f87b65b5
>Oct 25 01:16:25 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 113
>Oct 25 01:16:25 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:25 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:25 [drm:drm_mode_addfb2 [drm]] [FB:114]
>Oct 25 01:16:25 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000b7798c85
>Oct 25 01:16:25 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 000000002480bd06 state to 00000000b7798c85
>Oct 25 01:16:25 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 000000007b0042d5 state to 00000000b7798c85
>Oct 25 01:16:25 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:114] for [PLANE:28:plane 1A] state 000000007b0042d5
>Oct 25 01:16:25 [drm:drm_atomic_check_only [drm]] checking 00000000b7798c85
>Oct 25 01:16:25 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 114
>Oct 25 01:16:25 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:25 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45
>Oct 25 01:16:25 [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000b7798c85 nonblocking
>Oct 25 01:16:25 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:25 [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000008bde6312
>Oct 25 01:16:25 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000b7798c85
>Oct 25 01:16:25 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000b7798c85
>Oct 25 01:16:25 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000008bde6312
>Oct 25 01:16:25 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000008bde6312
>Oct 25 01:16:25 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000008bde6312
>Oct 25 01:16:25 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000008bde6312
>Oct 25 01:16:25 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000008bde6312
>Oct 25 01:16:25 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:113] for [PLANE:42:cursor A] state 00000000fb2fe074
>Oct 25 01:16:25 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 113
>Oct 25 01:16:25 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:25 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:25 [drm:drm_mode_addfb2 [drm]] [FB:110]
>Oct 25 01:16:25 [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000008bde6312
>Oct 25 01:16:25 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000b7798c85 state to 000000008bde6312
>Oct 25 01:16:25 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000aa66c66b state to 000000008bde6312
>Oct 25 01:16:25 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:28:plane 1A] state 00000000aa66c66b
>Oct 25 01:16:25 [drm:drm_atomic_check_only [drm]] checking 000000008bde6312
>Oct 25 01:16:25 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 110
>Oct 25 01:16:25 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:25 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45
>Oct 25 01:16:25 [drm:drm_atomic_nonblocking_commit [drm]] committing 000000008bde6312 nonblocking
>Oct 25 01:16:25 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:25 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000008bde6312
>Oct 25 01:16:25 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000a7a225a5
>Oct 25 01:16:25 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000a7a225a5
>Oct 25 01:16:25 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000008bde6312
>Oct 25 01:16:25 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000a7a225a5
>Oct 25 01:16:25 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000a7a225a5
>Oct 25 01:16:25 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000a7a225a5
>Oct 25 01:16:25 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000a7a225a5
>Oct 25 01:16:25 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:113] for [PLANE:42:cursor A] state 00000000e396bf6c
>Oct 25 01:16:25 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 113
>Oct 25 01:16:25 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:25 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:25 [drm:drm_mode_addfb2 [drm]] [FB:114]
>Oct 25 01:16:25 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000a7a225a5
>Oct 25 01:16:25 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 0000000035417744 state to 00000000a7a225a5
>Oct 25 01:16:25 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 000000008b497eb0 state to 00000000a7a225a5
>Oct 25 01:16:25 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:114] for [PLANE:28:plane 1A] state 000000008b497eb0
>Oct 25 01:16:25 [drm:drm_atomic_check_only [drm]] checking 00000000a7a225a5
>Oct 25 01:16:25 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 114
>Oct 25 01:16:25 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:25 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45
>Oct 25 01:16:25 [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000a7a225a5 nonblocking
>Oct 25 01:16:25 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:25 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000a7a225a5
>Oct 25 01:16:25 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000f8616964
>Oct 25 01:16:25 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000a7a225a5
>Oct 25 01:16:25 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000f8616964
>Oct 25 01:16:25 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000f8616964
>Oct 25 01:16:25 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:113] for [PLANE:42:cursor A] state 00000000f87b65b5
>Oct 25 01:16:25 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 113
>Oct 25 01:16:25 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:25 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:25 [drm:drm_mode_addfb2 [drm]] [FB:110]
>Oct 25 01:16:25 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000f8616964
>Oct 25 01:16:25 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000a7a225a5 state to 00000000f8616964
>Oct 25 01:16:25 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 000000004b50eded state to 00000000f8616964
>Oct 25 01:16:25 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:28:plane 1A] state 000000004b50eded
>Oct 25 01:16:25 [drm:drm_atomic_check_only [drm]] checking 00000000f8616964
>Oct 25 01:16:25 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 110
>Oct 25 01:16:25 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:25 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45
>Oct 25 01:16:25 [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000f8616964 nonblocking
>Oct 25 01:16:25 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:25 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000b7798c85
>Oct 25 01:16:25 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000f8616964
>Oct 25 01:16:25 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000b7798c85
>Oct 25 01:16:25 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000b7798c85
>Oct 25 01:16:25 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000f8616964
>Oct 25 01:16:25 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000b7798c85
>Oct 25 01:16:25 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000b7798c85
>Oct 25 01:16:25 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000b7798c85
>Oct 25 01:16:25 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:113] for [PLANE:42:cursor A] state 00000000fb2fe074
>Oct 25 01:16:25 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 113
>Oct 25 01:16:25 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:25 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:25 [drm:drm_mode_addfb2 [drm]] [FB:114]
>Oct 25 01:16:25 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000b7798c85
>Oct 25 01:16:25 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 000000008bde6312 state to 00000000b7798c85
>Oct 25 01:16:25 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 0000000020e68c00 state to 00000000b7798c85
>Oct 25 01:16:25 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:114] for [PLANE:28:plane 1A] state 0000000020e68c00
>Oct 25 01:16:25 [drm:drm_atomic_check_only [drm]] checking 00000000b7798c85
>Oct 25 01:16:25 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 114
>Oct 25 01:16:25 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:25 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45
>Oct 25 01:16:25 [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000b7798c85 nonblocking
>Oct 25 01:16:25 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:25 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000b7798c85
>Oct 25 01:16:25 [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000002480bd06
>Oct 25 01:16:25 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000002480bd06
>Oct 25 01:16:25 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000b7798c85
>Oct 25 01:16:25 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000002480bd06
>Oct 25 01:16:25 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000002480bd06
>Oct 25 01:16:25 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000002480bd06
>Oct 25 01:16:25 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000002480bd06
>Oct 25 01:16:25 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:113] for [PLANE:42:cursor A] state 00000000e396bf6c
>Oct 25 01:16:25 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 113
>Oct 25 01:16:25 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:25 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:25 [drm:drm_mode_addfb2 [drm]] [FB:110]
>Oct 25 01:16:25 [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000002480bd06
>Oct 25 01:16:25 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000b7798c85 state to 000000002480bd06
>Oct 25 01:16:25 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000c1050601 state to 000000002480bd06
>Oct 25 01:16:25 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:28:plane 1A] state 00000000c1050601
>Oct 25 01:16:25 [drm:drm_atomic_check_only [drm]] checking 000000002480bd06
>Oct 25 01:16:25 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 110
>Oct 25 01:16:25 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:25 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45
>Oct 25 01:16:25 [drm:drm_atomic_nonblocking_commit [drm]] committing 000000002480bd06 nonblocking
>Oct 25 01:16:25 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:25 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000002480bd06
>Oct 25 01:16:25 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000a7a225a5
>Oct 25 01:16:25 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000a7a225a5
>Oct 25 01:16:25 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000002480bd06
>Oct 25 01:16:25 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000a7a225a5
>Oct 25 01:16:25 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000a7a225a5
>Oct 25 01:16:25 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000a7a225a5
>Oct 25 01:16:25 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000a7a225a5
>Oct 25 01:16:25 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:113] for [PLANE:42:cursor A] state 00000000f87b65b5
>Oct 25 01:16:25 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 113
>Oct 25 01:16:25 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:25 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:25 [drm:drm_mode_addfb2 [drm]] [FB:114]
>Oct 25 01:16:25 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000a7a225a5
>Oct 25 01:16:25 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000f8616964 state to 00000000a7a225a5
>Oct 25 01:16:25 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 000000007b0042d5 state to 00000000a7a225a5
>Oct 25 01:16:25 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:114] for [PLANE:28:plane 1A] state 000000007b0042d5
>Oct 25 01:16:25 [drm:drm_atomic_check_only [drm]] checking 00000000a7a225a5
>Oct 25 01:16:25 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 114
>Oct 25 01:16:25 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:25 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45
>Oct 25 01:16:25 [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000a7a225a5 nonblocking
>Oct 25 01:16:25 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:25 [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000035417744
>Oct 25 01:16:25 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000035417744
>Oct 25 01:16:25 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000a7a225a5
>Oct 25 01:16:25 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000a7a225a5
>Oct 25 01:16:25 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000035417744
>Oct 25 01:16:25 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000035417744
>Oct 25 01:16:25 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000035417744
>Oct 25 01:16:25 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000035417744
>Oct 25 01:16:25 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:113] for [PLANE:42:cursor A] state 00000000fb2fe074
>Oct 25 01:16:25 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 113
>Oct 25 01:16:25 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:25 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:25 [drm:drm_mode_addfb2 [drm]] [FB:110]
>Oct 25 01:16:25 [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000035417744
>Oct 25 01:16:25 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000a7a225a5 state to 0000000035417744
>Oct 25 01:16:25 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000aa66c66b state to 0000000035417744
>Oct 25 01:16:25 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:28:plane 1A] state 00000000aa66c66b
>Oct 25 01:16:25 [drm:drm_atomic_check_only [drm]] checking 0000000035417744
>Oct 25 01:16:25 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 110
>Oct 25 01:16:25 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:25 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45
>Oct 25 01:16:25 [drm:drm_atomic_nonblocking_commit [drm]] committing 0000000035417744 nonblocking
>Oct 25 01:16:25 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:25 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000035417744
>Oct 25 01:16:25 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000b7798c85
>Oct 25 01:16:25 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000035417744
>Oct 25 01:16:25 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000b7798c85
>Oct 25 01:16:25 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000b7798c85
>Oct 25 01:16:25 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:113] for [PLANE:42:cursor A] state 00000000e396bf6c
>Oct 25 01:16:25 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 113
>Oct 25 01:16:25 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:25 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:25 [drm:drm_mode_addfb2 [drm]] [FB:114]
>Oct 25 01:16:25 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000b7798c85
>Oct 25 01:16:25 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 000000002480bd06 state to 00000000b7798c85
>Oct 25 01:16:25 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 000000008b497eb0 state to 00000000b7798c85
>Oct 25 01:16:25 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:114] for [PLANE:28:plane 1A] state 000000008b497eb0
>Oct 25 01:16:25 [drm:drm_atomic_check_only [drm]] checking 00000000b7798c85
>Oct 25 01:16:25 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 114
>Oct 25 01:16:25 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:25 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45
>Oct 25 01:16:25 [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000b7798c85 nonblocking
>Oct 25 01:16:25 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:25 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000b7798c85
>Oct 25 01:16:25 [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000008bde6312
>Oct 25 01:16:25 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000b7798c85
>Oct 25 01:16:25 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000008bde6312
>Oct 25 01:16:25 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000008bde6312
>Oct 25 01:16:25 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:113] for [PLANE:42:cursor A] state 00000000f87b65b5
>Oct 25 01:16:25 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 113
>Oct 25 01:16:25 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:25 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:25 [drm:drm_mode_addfb2 [drm]] [FB:110]
>Oct 25 01:16:25 [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000008bde6312
>Oct 25 01:16:25 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000b7798c85 state to 000000008bde6312
>Oct 25 01:16:25 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 000000004b50eded state to 000000008bde6312
>Oct 25 01:16:25 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:28:plane 1A] state 000000004b50eded
>Oct 25 01:16:25 [drm:drm_atomic_check_only [drm]] checking 000000008bde6312
>Oct 25 01:16:25 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 110
>Oct 25 01:16:25 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:25 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45
>Oct 25 01:16:25 [drm:drm_atomic_nonblocking_commit [drm]] committing 000000008bde6312 nonblocking
>Oct 25 01:16:25 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:25 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000008bde6312
>Oct 25 01:16:25 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000008bde6312
>Oct 25 01:16:25 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:113] for [PLANE:42:cursor A] state 00000000fb2fe074
>Oct 25 01:16:25 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 113
>Oct 25 01:16:25 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:25 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:25 [drm:drm_mode_addfb2 [drm]] [FB:114]
>Oct 25 01:16:25 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000a7a225a5
>Oct 25 01:16:25 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 0000000035417744 state to 00000000a7a225a5
>Oct 25 01:16:25 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 0000000020e68c00 state to 00000000a7a225a5
>Oct 25 01:16:25 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:114] for [PLANE:28:plane 1A] state 0000000020e68c00
>Oct 25 01:16:25 [drm:drm_atomic_check_only [drm]] checking 00000000a7a225a5
>Oct 25 01:16:25 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 114
>Oct 25 01:16:25 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:25 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45
>Oct 25 01:16:25 [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000a7a225a5 nonblocking
>Oct 25 01:16:25 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:25 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000f8616964
>Oct 25 01:16:25 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000f8616964
>Oct 25 01:16:25 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000f8616964
>Oct 25 01:16:25 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000a7a225a5
>Oct 25 01:16:25 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000f8616964
>Oct 25 01:16:25 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000f8616964
>Oct 25 01:16:25 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000a7a225a5
>Oct 25 01:16:25 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000f8616964
>Oct 25 01:16:25 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:113] for [PLANE:42:cursor A] state 00000000e396bf6c
>Oct 25 01:16:25 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 113
>Oct 25 01:16:25 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:25 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:25 [drm:drm_mode_addfb2 [drm]] [FB:110]
>Oct 25 01:16:25 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000f8616964
>Oct 25 01:16:25 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000a7a225a5 state to 00000000f8616964
>Oct 25 01:16:25 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000c1050601 state to 00000000f8616964
>Oct 25 01:16:25 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:28:plane 1A] state 00000000c1050601
>Oct 25 01:16:25 [drm:drm_atomic_check_only [drm]] checking 00000000f8616964
>Oct 25 01:16:25 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 110
>Oct 25 01:16:25 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:25 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45
>Oct 25 01:16:25 [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000f8616964 nonblocking
>Oct 25 01:16:25 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:25 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000b7798c85
>Oct 25 01:16:25 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000f8616964
>Oct 25 01:16:25 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000f8616964
>Oct 25 01:16:25 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000b7798c85
>Oct 25 01:16:25 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000b7798c85
>Oct 25 01:16:25 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000b7798c85
>Oct 25 01:16:25 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000b7798c85
>Oct 25 01:16:25 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000b7798c85
>Oct 25 01:16:25 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:113] for [PLANE:42:cursor A] state 00000000f87b65b5
>Oct 25 01:16:25 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 113
>Oct 25 01:16:25 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:25 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:25 [drm:drm_mode_addfb2 [drm]] [FB:114]
>Oct 25 01:16:25 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000b7798c85
>Oct 25 01:16:25 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 000000008bde6312 state to 00000000b7798c85
>Oct 25 01:16:25 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 000000007b0042d5 state to 00000000b7798c85
>Oct 25 01:16:25 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:114] for [PLANE:28:plane 1A] state 000000007b0042d5
>Oct 25 01:16:25 [drm:drm_atomic_check_only [drm]] checking 00000000b7798c85
>Oct 25 01:16:25 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 114
>Oct 25 01:16:25 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:25 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45
>Oct 25 01:16:25 [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000b7798c85 nonblocking
>Oct 25 01:16:25 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:25 [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000002480bd06
>Oct 25 01:16:25 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000b7798c85
>Oct 25 01:16:25 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000b7798c85
>Oct 25 01:16:25 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000002480bd06
>Oct 25 01:16:25 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000002480bd06
>Oct 25 01:16:25 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000002480bd06
>Oct 25 01:16:25 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000002480bd06
>Oct 25 01:16:25 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000002480bd06
>Oct 25 01:16:25 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:113] for [PLANE:42:cursor A] state 00000000fb2fe074
>Oct 25 01:16:25 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 113
>Oct 25 01:16:25 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:25 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:25 [drm:drm_mode_addfb2 [drm]] [FB:110]
>Oct 25 01:16:25 [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000002480bd06
>Oct 25 01:16:25 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000b7798c85 state to 000000002480bd06
>Oct 25 01:16:25 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000aa66c66b state to 000000002480bd06
>Oct 25 01:16:25 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:28:plane 1A] state 00000000aa66c66b
>Oct 25 01:16:25 [drm:drm_atomic_check_only [drm]] checking 000000002480bd06
>Oct 25 01:16:25 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 110
>Oct 25 01:16:25 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:25 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45
>Oct 25 01:16:25 [drm:drm_atomic_nonblocking_commit [drm]] committing 000000002480bd06 nonblocking
>Oct 25 01:16:25 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:25 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000002480bd06
>Oct 25 01:16:25 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000a7a225a5
>Oct 25 01:16:25 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000002480bd06
>Oct 25 01:16:25 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000a7a225a5
>Oct 25 01:16:25 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000a7a225a5
>Oct 25 01:16:25 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:113] for [PLANE:42:cursor A] state 00000000e396bf6c
>Oct 25 01:16:25 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 113
>Oct 25 01:16:25 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:25 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:25 [drm:drm_mode_addfb2 [drm]] [FB:114]
>Oct 25 01:16:25 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000a7a225a5
>Oct 25 01:16:25 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000f8616964 state to 00000000a7a225a5
>Oct 25 01:16:25 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 000000008b497eb0 state to 00000000a7a225a5
>Oct 25 01:16:25 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:114] for [PLANE:28:plane 1A] state 000000008b497eb0
>Oct 25 01:16:25 [drm:drm_atomic_check_only [drm]] checking 00000000a7a225a5
>Oct 25 01:16:25 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 114
>Oct 25 01:16:25 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:25 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45
>Oct 25 01:16:25 [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000a7a225a5 nonblocking
>Oct 25 01:16:25 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:25 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000a7a225a5
>Oct 25 01:16:25 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000a7a225a5
>Oct 25 01:16:25 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:113] for [PLANE:42:cursor A] state 00000000f87b65b5
>Oct 25 01:16:25 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 113
>Oct 25 01:16:25 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:25 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:25 [drm:drm_mode_addfb2 [drm]] [FB:110]
>Oct 25 01:16:25 [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000035417744
>Oct 25 01:16:25 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000a7a225a5 state to 0000000035417744
>Oct 25 01:16:25 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 000000004b50eded state to 0000000035417744
>Oct 25 01:16:25 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:28:plane 1A] state 000000004b50eded
>Oct 25 01:16:25 [drm:drm_atomic_check_only [drm]] checking 0000000035417744
>Oct 25 01:16:25 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 110
>Oct 25 01:16:25 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:25 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45
>Oct 25 01:16:25 [drm:drm_atomic_nonblocking_commit [drm]] committing 0000000035417744 nonblocking
>Oct 25 01:16:25 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:25 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000035417744
>Oct 25 01:16:25 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000b7798c85
>Oct 25 01:16:25 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000b7798c85
>Oct 25 01:16:25 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000b7798c85
>Oct 25 01:16:25 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000035417744
>Oct 25 01:16:25 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000b7798c85
>Oct 25 01:16:25 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000b7798c85
>Oct 25 01:16:25 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000b7798c85
>Oct 25 01:16:25 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:113] for [PLANE:42:cursor A] state 00000000fb2fe074
>Oct 25 01:16:25 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 113
>Oct 25 01:16:25 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:25 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:25 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:113] for [PLANE:42:cursor A] state 00000000f87b65b5
>Oct 25 01:16:25 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 113
>Oct 25 01:16:25 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:25 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:25 [drm:drm_mode_addfb2 [drm]] [FB:114]
>Oct 25 01:16:25 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000b7798c85
>Oct 25 01:16:25 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 000000002480bd06 state to 00000000b7798c85
>Oct 25 01:16:25 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 0000000020e68c00 state to 00000000b7798c85
>Oct 25 01:16:25 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:114] for [PLANE:28:plane 1A] state 0000000020e68c00
>Oct 25 01:16:25 [drm:drm_atomic_check_only [drm]] checking 00000000b7798c85
>Oct 25 01:16:25 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 114
>Oct 25 01:16:25 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:25 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45
>Oct 25 01:16:25 [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000b7798c85 nonblocking
>Oct 25 01:16:25 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:25 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000b7798c85
>Oct 25 01:16:25 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000b7798c85
>Oct 25 01:16:25 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:113] for [PLANE:42:cursor A] state 00000000e396bf6c
>Oct 25 01:16:25 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 113
>Oct 25 01:16:25 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:25 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:25 [drm:drm_mode_addfb2 [drm]] [FB:110]
>Oct 25 01:16:25 [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000008bde6312
>Oct 25 01:16:25 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000b7798c85 state to 000000008bde6312
>Oct 25 01:16:25 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000c1050601 state to 000000008bde6312
>Oct 25 01:16:25 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:28:plane 1A] state 00000000c1050601
>Oct 25 01:16:25 [drm:drm_atomic_check_only [drm]] checking 000000008bde6312
>Oct 25 01:16:25 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 110
>Oct 25 01:16:25 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:25 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45
>Oct 25 01:16:25 [drm:drm_atomic_nonblocking_commit [drm]] committing 000000008bde6312 nonblocking
>Oct 25 01:16:25 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:25 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000008bde6312
>Oct 25 01:16:25 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000008bde6312
>Oct 25 01:16:25 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:113] for [PLANE:42:cursor A] state 00000000fb2fe074
>Oct 25 01:16:25 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 113
>Oct 25 01:16:25 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:25 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:25 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:113] for [PLANE:42:cursor A] state 00000000e396bf6c
>Oct 25 01:16:25 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 113
>Oct 25 01:16:25 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:25 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:25 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:113] for [PLANE:42:cursor A] state 00000000fb2fe074
>Oct 25 01:16:25 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 113
>Oct 25 01:16:25 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:25 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:25 [drm:gen8_de_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x11101010, pins 0x00000010, long 0x00000000
>Oct 25 01:16:25 [drm:intel_hpd_irq_handler [i915]] digital hpd port A - short
>Oct 25 01:16:25 [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port A - short
>Oct 25 01:16:25 [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 41 00 00 01 80 02 00 00 00 0f 0b 00
>Oct 25 01:16:25 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:113] for [PLANE:42:cursor A] state 00000000e396bf6c
>Oct 25 01:16:25 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 113
>Oct 25 01:16:25 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:25 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:25 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:113] for [PLANE:42:cursor A] state 00000000fb2fe074
>Oct 25 01:16:25 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 113
>Oct 25 01:16:25 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:25 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:25 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:113] for [PLANE:42:cursor A] state 00000000e396bf6c
>Oct 25 01:16:25 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 113
>Oct 25 01:16:25 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:25 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:25 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:113] for [PLANE:42:cursor A] state 00000000fb2fe074
>Oct 25 01:16:25 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 113
>Oct 25 01:16:25 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:25 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:25 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:113] for [PLANE:42:cursor A] state 00000000e396bf6c
>Oct 25 01:16:25 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 113
>Oct 25 01:16:25 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:25 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:25 [drm:drm_mode_addfb2 [drm]] [FB:114]
>Oct 25 01:16:25 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000a7a225a5
>Oct 25 01:16:25 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 0000000035417744 state to 00000000a7a225a5
>Oct 25 01:16:25 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 000000007b0042d5 state to 00000000a7a225a5
>Oct 25 01:16:25 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:114] for [PLANE:28:plane 1A] state 000000007b0042d5
>Oct 25 01:16:25 [drm:drm_atomic_check_only [drm]] checking 00000000a7a225a5
>Oct 25 01:16:25 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 114
>Oct 25 01:16:25 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:25 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45
>Oct 25 01:16:25 [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000a7a225a5 nonblocking
>Oct 25 01:16:25 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:25 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000a7a225a5
>Oct 25 01:16:25 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000a7a225a5
>Oct 25 01:16:25 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:113] for [PLANE:42:cursor A] state 000000001d030b27
>Oct 25 01:16:25 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 113
>Oct 25 01:16:25 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:25 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:25 [drm:drm_mode_addfb2 [drm]] [FB:110]
>Oct 25 01:16:25 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000ff023107
>Oct 25 01:16:25 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 0000000055e5b1c7 state to 00000000ff023107
>Oct 25 01:16:25 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000535363ea state to 00000000ff023107
>Oct 25 01:16:25 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:28:plane 1A] state 00000000535363ea
>Oct 25 01:16:25 [drm:drm_atomic_check_only [drm]] checking 00000000ff023107
>Oct 25 01:16:25 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 110
>Oct 25 01:16:25 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:25 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45
>Oct 25 01:16:25 [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000ff023107 nonblocking
>Oct 25 01:16:25 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:25 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000ff023107
>Oct 25 01:16:25 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000ff023107
>Oct 25 01:16:25 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:113] for [PLANE:42:cursor A] state 0000000020e71326
>Oct 25 01:16:25 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 113
>Oct 25 01:16:25 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:25 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:25 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:113] for [PLANE:42:cursor A] state 0000000032f3802f
>Oct 25 01:16:25 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 113
>Oct 25 01:16:25 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:25 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:25 [drm:drm_mode_addfb2 [drm]] [FB:114]
>Oct 25 01:16:25 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000ca185597
>Oct 25 01:16:25 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000cdd506c4 state to 00000000ca185597
>Oct 25 01:16:25 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 000000005063004e state to 00000000ca185597
>Oct 25 01:16:25 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:114] for [PLANE:28:plane 1A] state 000000005063004e
>Oct 25 01:16:25 [drm:drm_atomic_check_only [drm]] checking 00000000ca185597
>Oct 25 01:16:25 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 114
>Oct 25 01:16:25 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:25 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45
>Oct 25 01:16:25 [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000ca185597 nonblocking
>Oct 25 01:16:25 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:25 [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000006a1c1622
>Oct 25 01:16:25 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000006a1c1622
>Oct 25 01:16:25 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000ca185597
>Oct 25 01:16:25 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000ca185597
>Oct 25 01:16:25 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000006a1c1622
>Oct 25 01:16:25 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000006a1c1622
>Oct 25 01:16:25 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000006a1c1622
>Oct 25 01:16:25 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000006a1c1622
>Oct 25 01:16:25 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:113] for [PLANE:42:cursor A] state 00000000e42aa11d
>Oct 25 01:16:25 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 113
>Oct 25 01:16:25 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:25 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:25 [drm:drm_mode_addfb2 [drm]] [FB:110]
>Oct 25 01:16:25 [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000000fde14e3
>Oct 25 01:16:25 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000a907ef8e state to 000000000fde14e3
>Oct 25 01:16:25 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 000000007bcb4dd1 state to 000000000fde14e3
>Oct 25 01:16:25 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:28:plane 1A] state 000000007bcb4dd1
>Oct 25 01:16:25 [drm:drm_atomic_check_only [drm]] checking 000000000fde14e3
>Oct 25 01:16:25 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 110
>Oct 25 01:16:25 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:25 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45
>Oct 25 01:16:25 [drm:drm_atomic_nonblocking_commit [drm]] committing 000000000fde14e3 nonblocking
>Oct 25 01:16:25 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:25 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000000fde14e3
>Oct 25 01:16:25 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000000fde14e3
>Oct 25 01:16:25 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:113] for [PLANE:42:cursor A] state 0000000020e71326
>Oct 25 01:16:25 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 113
>Oct 25 01:16:25 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:25 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:25 [drm:drm_mode_addfb2 [drm]] [FB:114]
>Oct 25 01:16:25 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000f9a09d92
>Oct 25 01:16:25 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000e0975642 state to 00000000f9a09d92
>Oct 25 01:16:25 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 0000000010e63a31 state to 00000000f9a09d92
>Oct 25 01:16:25 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:114] for [PLANE:28:plane 1A] state 0000000010e63a31
>Oct 25 01:16:25 [drm:drm_atomic_check_only [drm]] checking 00000000f9a09d92
>Oct 25 01:16:25 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 114
>Oct 25 01:16:25 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:25 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45
>Oct 25 01:16:25 [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000f9a09d92 nonblocking
>Oct 25 01:16:25 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:25 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000f9a09d92
>Oct 25 01:16:25 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000f9a09d92
>Oct 25 01:16:25 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:113] for [PLANE:42:cursor A] state 0000000032f3802f
>Oct 25 01:16:25 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 113
>Oct 25 01:16:25 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:25 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:26 [drm:gen8_de_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x11101010, pins 0x00000010, long 0x00000000
>Oct 25 01:16:26 [drm:intel_hpd_irq_handler [i915]] digital hpd port A - short
>Oct 25 01:16:26 [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port A - short
>Oct 25 01:16:26 [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 41 00 00 01 80 02 00 00 00 0f 0b 00
>Oct 25 01:16:26 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:113] for [PLANE:42:cursor A] state 00000000bb09c912
>Oct 25 01:16:26 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 113
>Oct 25 01:16:26 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:26 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:26 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:113] for [PLANE:42:cursor A] state 00000000a01adddc
>Oct 25 01:16:26 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 113
>Oct 25 01:16:26 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:26 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:26 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:113] for [PLANE:42:cursor A] state 00000000bb09c912
>Oct 25 01:16:26 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 113
>Oct 25 01:16:26 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:26 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:26 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:113] for [PLANE:42:cursor A] state 00000000a01adddc
>Oct 25 01:16:26 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 113
>Oct 25 01:16:26 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:26 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:26 [drm:drm_mode_addfb2 [drm]] [FB:110]
>Oct 25 01:16:26 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000a4955e94
>Oct 25 01:16:26 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 000000001e2967c2 state to 00000000a4955e94
>Oct 25 01:16:26 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000fa374140 state to 00000000a4955e94
>Oct 25 01:16:26 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:28:plane 1A] state 00000000fa374140
>Oct 25 01:16:26 [drm:drm_atomic_check_only [drm]] checking 00000000a4955e94
>Oct 25 01:16:26 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 110
>Oct 25 01:16:26 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:26 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45
>Oct 25 01:16:26 [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000a4955e94 nonblocking
>Oct 25 01:16:26 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:26 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000a4955e94
>Oct 25 01:16:26 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000c986cc08
>Oct 25 01:16:26 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000c986cc08
>Oct 25 01:16:26 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000c986cc08
>Oct 25 01:16:26 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000a4955e94
>Oct 25 01:16:26 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000c986cc08
>Oct 25 01:16:26 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000c986cc08
>Oct 25 01:16:26 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000c986cc08
>Oct 25 01:16:26 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:113] for [PLANE:42:cursor A] state 00000000cad9a501
>Oct 25 01:16:26 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 113
>Oct 25 01:16:26 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:26 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:26 [drm:drm_mode_addfb2 [drm]] [FB:114]
>Oct 25 01:16:26 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000c986cc08
>Oct 25 01:16:26 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000a4955e94 state to 00000000c986cc08
>Oct 25 01:16:26 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000163b82bd state to 00000000c986cc08
>Oct 25 01:16:26 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:114] for [PLANE:28:plane 1A] state 00000000163b82bd
>Oct 25 01:16:26 [drm:drm_atomic_check_only [drm]] checking 00000000c986cc08
>Oct 25 01:16:26 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 114
>Oct 25 01:16:26 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:26 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45
>Oct 25 01:16:26 [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000c986cc08 nonblocking
>Oct 25 01:16:26 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:26 [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000002199d420
>Oct 25 01:16:26 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000002199d420
>Oct 25 01:16:26 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000002199d420
>Oct 25 01:16:26 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000c986cc08
>Oct 25 01:16:26 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000c986cc08
>Oct 25 01:16:26 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000002199d420
>Oct 25 01:16:26 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000002199d420
>Oct 25 01:16:26 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000002199d420
>Oct 25 01:16:26 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:113] for [PLANE:42:cursor A] state 00000000bb09c912
>Oct 25 01:16:26 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 113
>Oct 25 01:16:26 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:26 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:26 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:113] for [PLANE:42:cursor A] state 00000000cad9a501
>Oct 25 01:16:26 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 113
>Oct 25 01:16:26 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:26 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:26 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:113] for [PLANE:42:cursor A] state 000000008b497eb0
>Oct 25 01:16:26 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 113
>Oct 25 01:16:26 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:26 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:26 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:113] for [PLANE:42:cursor A] state 00000000fb2fe074
>Oct 25 01:16:26 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 113
>Oct 25 01:16:26 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:26 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:26 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:113] for [PLANE:42:cursor A] state 000000008b497eb0
>Oct 25 01:16:26 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 113
>Oct 25 01:16:26 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:26 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:26 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:113] for [PLANE:42:cursor A] state 00000000fb2fe074
>Oct 25 01:16:26 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 113
>Oct 25 01:16:26 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:26 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:26 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:113] for [PLANE:42:cursor A] state 000000008b497eb0
>Oct 25 01:16:26 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 113
>Oct 25 01:16:26 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:26 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:26 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:113] for [PLANE:42:cursor A] state 00000000fb2fe074
>Oct 25 01:16:26 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 113
>Oct 25 01:16:26 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:26 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:26 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:113] for [PLANE:42:cursor A] state 000000008b497eb0
>Oct 25 01:16:26 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 113
>Oct 25 01:16:26 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:26 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:26 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:113] for [PLANE:42:cursor A] state 00000000fb2fe074
>Oct 25 01:16:26 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 113
>Oct 25 01:16:26 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:26 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:26 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:113] for [PLANE:42:cursor A] state 000000008b497eb0
>Oct 25 01:16:26 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 113
>Oct 25 01:16:26 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:26 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:26 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:113] for [PLANE:42:cursor A] state 00000000fb2fe074
>Oct 25 01:16:26 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 113
>Oct 25 01:16:26 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:26 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:26 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:113] for [PLANE:42:cursor A] state 000000008b497eb0
>Oct 25 01:16:26 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 113
>Oct 25 01:16:26 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:26 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:26 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:113] for [PLANE:42:cursor A] state 00000000fb2fe074
>Oct 25 01:16:26 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 113
>Oct 25 01:16:26 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:26 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:26 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:113] for [PLANE:42:cursor A] state 000000008b497eb0
>Oct 25 01:16:26 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 113
>Oct 25 01:16:26 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:26 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:26 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:113] for [PLANE:42:cursor A] state 00000000fb2fe074
>Oct 25 01:16:26 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 113
>Oct 25 01:16:26 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:26 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:26 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:113] for [PLANE:42:cursor A] state 000000008b497eb0
>Oct 25 01:16:26 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 113
>Oct 25 01:16:26 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:26 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:26 [drm:gen8_de_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x11101010, pins 0x00000010, long 0x00000000
>Oct 25 01:16:26 [drm:intel_hpd_irq_handler [i915]] digital hpd port A - short
>Oct 25 01:16:26 [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port A - short
>Oct 25 01:16:26 [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 41 00 00 01 80 02 00 00 00 0f 0b 00
>Oct 25 01:16:27 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:113] for [PLANE:42:cursor A] state 00000000fb2fe074
>Oct 25 01:16:27 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 113
>Oct 25 01:16:27 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:27 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:27 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:113] for [PLANE:42:cursor A] state 000000008b497eb0
>Oct 25 01:16:27 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 113
>Oct 25 01:16:27 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:27 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:27 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:113] for [PLANE:42:cursor A] state 00000000fb2fe074
>Oct 25 01:16:27 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 113
>Oct 25 01:16:27 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:27 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:27 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:113] for [PLANE:42:cursor A] state 000000008b497eb0
>Oct 25 01:16:27 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 113
>Oct 25 01:16:27 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:27 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:27 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:113] for [PLANE:42:cursor A] state 00000000fb2fe074
>Oct 25 01:16:27 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 113
>Oct 25 01:16:27 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:27 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:27 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:42:cursor A] state 000000007b0042d5
>Oct 25 01:16:27 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 110
>Oct 25 01:16:27 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:27 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:27 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:42:cursor A] state 00000000fb2fe074
>Oct 25 01:16:27 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 110
>Oct 25 01:16:27 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:27 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:27 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:42:cursor A] state 000000007b0042d5
>Oct 25 01:16:27 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 110
>Oct 25 01:16:27 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:27 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:27 [drm:drm_mode_addfb2 [drm]] [FB:113]
>Oct 25 01:16:27 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000f8616964
>Oct 25 01:16:27 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000a7a225a5 state to 00000000f8616964
>Oct 25 01:16:27 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000e396bf6c state to 00000000f8616964
>Oct 25 01:16:27 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:113] for [PLANE:28:plane 1A] state 00000000e396bf6c
>Oct 25 01:16:27 [drm:drm_atomic_check_only [drm]] checking 00000000f8616964
>Oct 25 01:16:27 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 113
>Oct 25 01:16:27 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:27 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45
>Oct 25 01:16:27 [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000f8616964 nonblocking
>Oct 25 01:16:27 [drm:gen8_de_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x11101010, pins 0x00000010, long 0x00000000
>Oct 25 01:16:27 [drm:intel_hpd_irq_handler [i915]] digital hpd port A - short
>Oct 25 01:16:27 [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port A - short
>Oct 25 01:16:27 [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 41 00 00 01 80 02 00 00 00 0f 0b 00
>Oct 25 01:16:27 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:27 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000f8616964
>Oct 25 01:16:27 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000f8616964
>Oct 25 01:16:27 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:42:cursor A] state 00000000aa66c66b
>Oct 25 01:16:27 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 110
>Oct 25 01:16:27 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:27 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:27 [drm:gen8_de_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x11101010, pins 0x00000010, long 0x00000000
>Oct 25 01:16:27 [drm:intel_hpd_irq_handler [i915]] digital hpd port A - short
>Oct 25 01:16:27 [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port A - short
>Oct 25 01:16:27 [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 41 00 00 01 80 02 00 00 00 0f 0b 00
>Oct 25 01:16:27 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:42:cursor A] state 000000007b0042d5
>Oct 25 01:16:27 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 110
>Oct 25 01:16:27 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:27 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:27 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:114] for [PLANE:42:cursor A] state 00000000c1050601
>Oct 25 01:16:27 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 114
>Oct 25 01:16:27 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:27 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:114] for [PLANE:42:cursor A] state 000000007b0042d5
>Oct 25 01:16:27 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 114
>Oct 25 01:16:27 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:27 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:27 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:114] for [PLANE:42:cursor A] state 00000000c1050601
>Oct 25 01:16:27 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 114
>Oct 25 01:16:27 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:27 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:27 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:114] for [PLANE:42:cursor A] state 000000007b0042d5
>Oct 25 01:16:27 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 114
>Oct 25 01:16:27 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:27 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:27 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:42:cursor A] state 000000008b497eb0
>Oct 25 01:16:27 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 110
>Oct 25 01:16:27 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:27 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:27 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:42:cursor A] state 000000007b0042d5
>Oct 25 01:16:27 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 110
>Oct 25 01:16:27 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:27 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:27 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:114] for [PLANE:42:cursor A] state 00000000aa66c66b
>Oct 25 01:16:27 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 114
>Oct 25 01:16:27 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:27 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:27 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:114] for [PLANE:42:cursor A] state 000000007b0042d5
>Oct 25 01:16:27 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 114
>Oct 25 01:16:27 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:27 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:27 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:114] for [PLANE:42:cursor A] state 00000000aa66c66b
>Oct 25 01:16:27 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 114
>Oct 25 01:16:27 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:27 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:27 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:114] for [PLANE:42:cursor A] state 000000007b0042d5
>Oct 25 01:16:27 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 114
>Oct 25 01:16:27 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:27 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:27 [drm:drm_mode_addfb2 [drm]] [FB:110]
>Oct 25 01:16:27 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000b7798c85
>Oct 25 01:16:27 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 000000002480bd06 state to 00000000b7798c85
>Oct 25 01:16:27 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000e74eab73 state to 00000000b7798c85
>Oct 25 01:16:27 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:28:plane 1A] state 00000000e74eab73
>Oct 25 01:16:27 [drm:drm_atomic_check_only [drm]] checking 00000000b7798c85
>Oct 25 01:16:27 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 110
>Oct 25 01:16:27 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:27 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45
>Oct 25 01:16:27 [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000b7798c85 nonblocking
>Oct 25 01:16:27 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:27 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000f8616964
>Oct 25 01:16:27 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000b7798c85
>Oct 25 01:16:27 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000b7798c85
>Oct 25 01:16:27 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000f8616964
>Oct 25 01:16:27 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000f8616964
>Oct 25 01:16:27 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:114] for [PLANE:42:cursor A] state 00000000fb2fe074
>Oct 25 01:16:27 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 114
>Oct 25 01:16:27 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:27 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:27 [drm:drm_mode_addfb2 [drm]] [FB:113]
>Oct 25 01:16:27 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000f8616964
>Oct 25 01:16:27 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000b7798c85 state to 00000000f8616964
>Oct 25 01:16:27 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000c1050601 state to 00000000f8616964
>Oct 25 01:16:27 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:113] for [PLANE:28:plane 1A] state 00000000c1050601
>Oct 25 01:16:27 [drm:drm_atomic_check_only [drm]] checking 00000000f8616964
>Oct 25 01:16:27 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 113
>Oct 25 01:16:27 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:27 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45
>Oct 25 01:16:27 [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000f8616964 nonblocking
>Oct 25 01:16:27 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:27 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000f8616964
>Oct 25 01:16:27 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000f8616964
>Oct 25 01:16:27 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:114] for [PLANE:42:cursor A] state 00000000aa66c66b
>Oct 25 01:16:27 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 114
>Oct 25 01:16:27 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:27 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:27 [drm:drm_mode_addfb2 [drm]] [FB:110]
>Oct 25 01:16:27 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000a7a225a5
>Oct 25 01:16:27 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000f8616964 state to 00000000a7a225a5
>Oct 25 01:16:27 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 000000002a08f491 state to 00000000a7a225a5
>Oct 25 01:16:27 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:28:plane 1A] state 000000002a08f491
>Oct 25 01:16:27 [drm:drm_atomic_check_only [drm]] checking 00000000a7a225a5
>Oct 25 01:16:27 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 110
>Oct 25 01:16:27 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:27 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45
>Oct 25 01:16:27 [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000a7a225a5 nonblocking
>Oct 25 01:16:27 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:27 [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000002480bd06
>Oct 25 01:16:27 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000a7a225a5
>Oct 25 01:16:27 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000a7a225a5
>Oct 25 01:16:27 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000002480bd06
>Oct 25 01:16:27 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000002480bd06
>Oct 25 01:16:27 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000002480bd06
>Oct 25 01:16:27 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000002480bd06
>Oct 25 01:16:27 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000002480bd06
>Oct 25 01:16:27 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:114] for [PLANE:42:cursor A] state 000000007b0042d5
>Oct 25 01:16:27 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 114
>Oct 25 01:16:27 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:27 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:27 [drm:drm_mode_addfb2 [drm]] [FB:113]
>Oct 25 01:16:27 [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000002480bd06
>Oct 25 01:16:27 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000a7a225a5 state to 000000002480bd06
>Oct 25 01:16:27 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000e74eab73 state to 000000002480bd06
>Oct 25 01:16:27 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:113] for [PLANE:28:plane 1A] state 00000000e74eab73
>Oct 25 01:16:27 [drm:drm_atomic_check_only [drm]] checking 000000002480bd06
>Oct 25 01:16:27 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 113
>Oct 25 01:16:27 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:27 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45
>Oct 25 01:16:27 [drm:drm_atomic_nonblocking_commit [drm]] committing 000000002480bd06 nonblocking
>Oct 25 01:16:27 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:27 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000b7798c85
>Oct 25 01:16:27 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000002480bd06
>Oct 25 01:16:27 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000002480bd06
>Oct 25 01:16:27 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000b7798c85
>Oct 25 01:16:27 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000b7798c85
>Oct 25 01:16:27 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000b7798c85
>Oct 25 01:16:27 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000b7798c85
>Oct 25 01:16:27 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000b7798c85
>Oct 25 01:16:27 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:114] for [PLANE:42:cursor A] state 00000000fb2fe074
>Oct 25 01:16:27 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 114
>Oct 25 01:16:27 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:27 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:27 [drm:drm_mode_addfb2 [drm]] [FB:110]
>Oct 25 01:16:27 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000b7798c85
>Oct 25 01:16:27 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 000000002480bd06 state to 00000000b7798c85
>Oct 25 01:16:27 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000c1050601 state to 00000000b7798c85
>Oct 25 01:16:27 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:28:plane 1A] state 00000000c1050601
>Oct 25 01:16:27 [drm:drm_atomic_check_only [drm]] checking 00000000b7798c85
>Oct 25 01:16:27 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 110
>Oct 25 01:16:27 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:27 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45
>Oct 25 01:16:27 [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000b7798c85 nonblocking
>Oct 25 01:16:27 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:27 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000b7798c85
>Oct 25 01:16:27 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000f8616964
>Oct 25 01:16:27 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000b7798c85
>Oct 25 01:16:27 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000f8616964
>Oct 25 01:16:27 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000f8616964
>Oct 25 01:16:27 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000f8616964
>Oct 25 01:16:27 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000f8616964
>Oct 25 01:16:27 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000f8616964
>Oct 25 01:16:27 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:114] for [PLANE:42:cursor A] state 00000000aa66c66b
>Oct 25 01:16:27 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 114
>Oct 25 01:16:27 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:27 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:27 [drm:drm_mode_addfb2 [drm]] [FB:113]
>Oct 25 01:16:27 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000f8616964
>Oct 25 01:16:27 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000b7798c85 state to 00000000f8616964
>Oct 25 01:16:27 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 000000002a08f491 state to 00000000f8616964
>Oct 25 01:16:27 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:113] for [PLANE:28:plane 1A] state 000000002a08f491
>Oct 25 01:16:27 [drm:drm_atomic_check_only [drm]] checking 00000000f8616964
>Oct 25 01:16:27 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 113
>Oct 25 01:16:27 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:27 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45
>Oct 25 01:16:27 [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000f8616964 nonblocking
>Oct 25 01:16:27 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:27 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000f8616964
>Oct 25 01:16:27 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000f8616964
>Oct 25 01:16:27 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:114] for [PLANE:42:cursor A] state 000000007b0042d5
>Oct 25 01:16:27 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 114
>Oct 25 01:16:27 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:27 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:27 [drm:drm_mode_addfb2 [drm]] [FB:110]
>Oct 25 01:16:27 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000a7a225a5
>Oct 25 01:16:27 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000f8616964 state to 00000000a7a225a5
>Oct 25 01:16:27 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000c1050601 state to 00000000a7a225a5
>Oct 25 01:16:27 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:28:plane 1A] state 00000000c1050601
>Oct 25 01:16:27 [drm:drm_atomic_check_only [drm]] checking 00000000a7a225a5
>Oct 25 01:16:27 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 110
>Oct 25 01:16:27 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:27 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45
>Oct 25 01:16:27 [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000a7a225a5 nonblocking
>Oct 25 01:16:27 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:27 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000a7a225a5
>Oct 25 01:16:27 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000a7a225a5
>Oct 25 01:16:27 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:114] for [PLANE:42:cursor A] state 00000000fb2fe074
>Oct 25 01:16:27 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 114
>Oct 25 01:16:27 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:27 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:27 [drm:drm_mode_addfb2 [drm]] [FB:113]
>Oct 25 01:16:27 [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000002480bd06
>Oct 25 01:16:27 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000a7a225a5 state to 000000002480bd06
>Oct 25 01:16:27 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000e74eab73 state to 000000002480bd06
>Oct 25 01:16:27 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:113] for [PLANE:28:plane 1A] state 00000000e74eab73
>Oct 25 01:16:27 [drm:drm_atomic_check_only [drm]] checking 000000002480bd06
>Oct 25 01:16:27 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 113
>Oct 25 01:16:27 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:27 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45
>Oct 25 01:16:27 [drm:drm_atomic_nonblocking_commit [drm]] committing 000000002480bd06 nonblocking
>Oct 25 01:16:27 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:27 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000002480bd06
>Oct 25 01:16:27 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000b7798c85
>Oct 25 01:16:27 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000002480bd06
>Oct 25 01:16:27 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000b7798c85
>Oct 25 01:16:27 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000b7798c85
>Oct 25 01:16:27 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:114] for [PLANE:42:cursor A] state 00000000aa66c66b
>Oct 25 01:16:27 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 114
>Oct 25 01:16:27 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:27 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:27 [drm:drm_mode_addfb2 [drm]] [FB:110]
>Oct 25 01:16:27 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000b7798c85
>Oct 25 01:16:27 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 000000002480bd06 state to 00000000b7798c85
>Oct 25 01:16:27 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 000000002a08f491 state to 00000000b7798c85
>Oct 25 01:16:27 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:28:plane 1A] state 000000002a08f491
>Oct 25 01:16:27 [drm:drm_atomic_check_only [drm]] checking 00000000b7798c85
>Oct 25 01:16:27 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 110
>Oct 25 01:16:27 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:27 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45
>Oct 25 01:16:27 [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000b7798c85 nonblocking
>Oct 25 01:16:27 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:27 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000b7798c85
>Oct 25 01:16:27 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000b7798c85
>Oct 25 01:16:27 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:114] for [PLANE:42:cursor A] state 000000007b0042d5
>Oct 25 01:16:27 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 114
>Oct 25 01:16:27 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:27 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:27 [drm:drm_mode_addfb2 [drm]] [FB:113]
>Oct 25 01:16:27 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000f8616964
>Oct 25 01:16:27 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000b7798c85 state to 00000000f8616964
>Oct 25 01:16:27 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000e74eab73 state to 00000000f8616964
>Oct 25 01:16:27 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:113] for [PLANE:28:plane 1A] state 00000000e74eab73
>Oct 25 01:16:27 [drm:drm_atomic_check_only [drm]] checking 00000000f8616964
>Oct 25 01:16:27 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 113
>Oct 25 01:16:27 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:27 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45
>Oct 25 01:16:27 [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000f8616964 nonblocking
>Oct 25 01:16:27 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:27 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000f8616964
>Oct 25 01:16:27 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000f8616964
>Oct 25 01:16:27 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:114] for [PLANE:42:cursor A] state 00000000fb2fe074
>Oct 25 01:16:27 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb 114
>Oct 25 01:16:27 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:27 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:27 [drm:drm_mode_addfb2 [drm]] [FB:110]
>Oct 25 01:16:27 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000a7a225a5
>Oct 25 01:16:27 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000f8616964 state to 00000000a7a225a5
>Oct 25 01:16:27 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000c1050601 state to 00000000a7a225a5
>Oct 25 01:16:27 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:28:plane 1A] state 00000000c1050601
>Oct 25 01:16:27 [drm:drm_atomic_check_only [drm]] checking 00000000a7a225a5
>Oct 25 01:16:27 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 110
>Oct 25 01:16:27 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:27 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45
>Oct 25 01:16:27 [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000a7a225a5 nonblocking
>Oct 25 01:16:27 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:27 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000a7a225a5
>Oct 25 01:16:27 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000a7a225a5
>Oct 25 01:16:27 [drm:drm_mode_addfb2 [drm]] [FB:113]
>Oct 25 01:16:27 [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000002480bd06
>Oct 25 01:16:27 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000a7a225a5 state to 000000002480bd06
>Oct 25 01:16:27 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000e74eab73 state to 000000002480bd06
>Oct 25 01:16:27 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:113] for [PLANE:28:plane 1A] state 00000000e74eab73
>Oct 25 01:16:27 [drm:drm_atomic_check_only [drm]] checking 000000002480bd06
>Oct 25 01:16:27 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 113
>Oct 25 01:16:27 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:27 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45
>Oct 25 01:16:27 [drm:drm_atomic_nonblocking_commit [drm]] committing 000000002480bd06 nonblocking
>Oct 25 01:16:27 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:27 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000002480bd06
>Oct 25 01:16:27 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000002480bd06
>Oct 25 01:16:27 [drm:drm_mode_addfb2 [drm]] [FB:110]
>Oct 25 01:16:27 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000b7798c85
>Oct 25 01:16:27 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 000000002480bd06 state to 00000000b7798c85
>Oct 25 01:16:27 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 000000002a08f491 state to 00000000b7798c85
>Oct 25 01:16:27 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:28:plane 1A] state 000000002a08f491
>Oct 25 01:16:27 [drm:drm_atomic_check_only [drm]] checking 00000000b7798c85
>Oct 25 01:16:27 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 110
>Oct 25 01:16:27 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:27 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45
>Oct 25 01:16:27 [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000b7798c85 nonblocking
>Oct 25 01:16:27 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:27 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000b7798c85
>Oct 25 01:16:27 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000b7798c85
>Oct 25 01:16:28 [drm:drm_mode_addfb2 [drm]] [FB:113]
>Oct 25 01:16:28 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000f8616964
>Oct 25 01:16:28 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000b7798c85 state to 00000000f8616964
>Oct 25 01:16:28 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000e74eab73 state to 00000000f8616964
>Oct 25 01:16:28 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:113] for [PLANE:28:plane 1A] state 00000000e74eab73
>Oct 25 01:16:28 [drm:drm_atomic_check_only [drm]] checking 00000000f8616964
>Oct 25 01:16:28 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 113
>Oct 25 01:16:28 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:28 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45
>Oct 25 01:16:28 [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000f8616964 nonblocking
>Oct 25 01:16:28 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:28 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000f8616964
>Oct 25 01:16:28 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000f8616964
>Oct 25 01:16:28 [drm:drm_mode_addfb2 [drm]] [FB:110]
>Oct 25 01:16:28 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000a7a225a5
>Oct 25 01:16:28 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000f8616964 state to 00000000a7a225a5
>Oct 25 01:16:28 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000c1050601 state to 00000000a7a225a5
>Oct 25 01:16:28 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:28:plane 1A] state 00000000c1050601
>Oct 25 01:16:28 [drm:drm_atomic_check_only [drm]] checking 00000000a7a225a5
>Oct 25 01:16:28 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 110
>Oct 25 01:16:28 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:28 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45
>Oct 25 01:16:28 [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000a7a225a5 nonblocking
>Oct 25 01:16:28 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:28 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000a7a225a5
>Oct 25 01:16:28 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000a7a225a5
>Oct 25 01:16:28 [drm:gen8_de_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x11101010, pins 0x00000010, long 0x00000000
>Oct 25 01:16:28 [drm:intel_hpd_irq_handler [i915]] digital hpd port A - short
>Oct 25 01:16:28 [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port A - short
>Oct 25 01:16:28 [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 41 00 00 01 80 02 00 00 00 0f 0b 00
>Oct 25 01:16:28 [drm:drm_mode_addfb2 [drm]] [FB:113]
>Oct 25 01:16:28 [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000055e5b1c7
>Oct 25 01:16:28 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000ff023107 state to 0000000055e5b1c7
>Oct 25 01:16:28 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 0000000035e2d4ef state to 0000000055e5b1c7
>Oct 25 01:16:28 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:113] for [PLANE:28:plane 1A] state 0000000035e2d4ef
>Oct 25 01:16:28 [drm:drm_atomic_check_only [drm]] checking 0000000055e5b1c7
>Oct 25 01:16:28 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 113
>Oct 25 01:16:28 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:28 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45
>Oct 25 01:16:28 [drm:drm_atomic_nonblocking_commit [drm]] committing 0000000055e5b1c7 nonblocking
>Oct 25 01:16:28 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:28 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000055e5b1c7
>Oct 25 01:16:28 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000055e5b1c7
>Oct 25 01:16:28 [drm:gen8_de_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x11101010, pins 0x00000010, long 0x00000000
>Oct 25 01:16:28 [drm:intel_hpd_irq_handler [i915]] digital hpd port A - short
>Oct 25 01:16:28 [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port A - short
>Oct 25 01:16:28 [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 41 00 00 01 80 02 00 00 00 0f 0b 00
>Oct 25 01:16:29 [drm:drm_mode_addfb2 [drm]] [FB:110]
>Oct 25 01:16:29 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000260d955a
>Oct 25 01:16:29 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000bd83b9dd state to 00000000260d955a
>Oct 25 01:16:29 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 0000000004431c76 state to 00000000260d955a
>Oct 25 01:16:29 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:28:plane 1A] state 0000000004431c76
>Oct 25 01:16:29 [drm:drm_atomic_check_only [drm]] checking 00000000260d955a
>Oct 25 01:16:29 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 110
>Oct 25 01:16:29 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:29 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45
>Oct 25 01:16:29 [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000260d955a nonblocking
>Oct 25 01:16:29 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:29 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000260d955a
>Oct 25 01:16:29 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000260d955a
>Oct 25 01:16:29 [drm:gen8_de_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x11101010, pins 0x00000010, long 0x00000000
>Oct 25 01:16:29 [drm:intel_hpd_irq_handler [i915]] digital hpd port A - short
>Oct 25 01:16:29 [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port A - short
>Oct 25 01:16:29 [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 41 00 00 01 80 02 00 00 00 0f 0b 00
>Oct 25 01:16:29 [drm:drm_mode_addfb2 [drm]] [FB:113]
>Oct 25 01:16:29 [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000002480bd06
>Oct 25 01:16:29 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000f8616964 state to 000000002480bd06
>Oct 25 01:16:29 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000c1050601 state to 000000002480bd06
>Oct 25 01:16:29 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:113] for [PLANE:28:plane 1A] state 00000000c1050601
>Oct 25 01:16:29 [drm:drm_atomic_check_only [drm]] checking 000000002480bd06
>Oct 25 01:16:29 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 113
>Oct 25 01:16:29 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:29 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45
>Oct 25 01:16:29 [drm:drm_atomic_nonblocking_commit [drm]] committing 000000002480bd06 nonblocking
>Oct 25 01:16:29 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:29 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000002480bd06
>Oct 25 01:16:29 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000002480bd06
>Oct 25 01:16:30 [drm:gen8_de_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x11101010, pins 0x00000010, long 0x00000000
>Oct 25 01:16:30 [drm:intel_hpd_irq_handler [i915]] digital hpd port A - short
>Oct 25 01:16:30 [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port A - short
>Oct 25 01:16:30 [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 41 00 00 01 80 02 00 00 00 0f 0b 00
>Oct 25 01:16:30 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000a7a225a5
>Oct 25 01:16:30 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:42:cursor A] 00000000e74eab73 state to 00000000a7a225a5
>Oct 25 01:16:30 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000b7798c85 state to 00000000a7a225a5
>Oct 25 01:16:30 [drm:drm_atomic_set_crtc_for_plane [drm]] Link [PLANE:42:cursor A] state 00000000e74eab73 to [NOCRTC]
>Oct 25 01:16:30 [drm:drm_atomic_set_fb_for_plane [drm]] Set [NOFB] for [PLANE:42:cursor A] state 00000000e74eab73
>Oct 25 01:16:30 [drm:drm_atomic_check_only [drm]] checking 00000000a7a225a5
>Oct 25 01:16:30 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:42:cursor A] with fb -1
>Oct 25 01:16:30 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:42:cursor A] visible 1 -> 0, off 1, on 0, ms 0
>Oct 25 01:16:30 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45
>Oct 25 01:16:30 [drm:drm_atomic_commit [drm]] committing 00000000a7a225a5
>Oct 25 01:16:30 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:30 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000a7a225a5
>Oct 25 01:16:30 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000a7a225a5
>Oct 25 01:16:30 [drm:drm_mode_addfb2 [drm]] [FB:110]
>Oct 25 01:16:30 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000a7a225a5
>Oct 25 01:16:30 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000f8616964 state to 00000000a7a225a5
>Oct 25 01:16:30 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 000000008b497eb0 state to 00000000a7a225a5
>Oct 25 01:16:30 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:28:plane 1A] state 000000008b497eb0
>Oct 25 01:16:30 [drm:drm_atomic_check_only [drm]] checking 00000000a7a225a5
>Oct 25 01:16:30 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 110
>Oct 25 01:16:30 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:30 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45
>Oct 25 01:16:30 [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000a7a225a5 nonblocking
>Oct 25 01:16:30 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:30 [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000002480bd06
>Oct 25 01:16:30 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000a7a225a5
>Oct 25 01:16:30 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000a7a225a5
>Oct 25 01:16:30 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000002480bd06
>Oct 25 01:16:30 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000002480bd06
>Oct 25 01:16:30 [drm:gen8_de_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x11101010, pins 0x00000010, long 0x00000000
>Oct 25 01:16:30 [drm:intel_hpd_irq_handler [i915]] digital hpd port A - short
>Oct 25 01:16:30 [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port A - short
>Oct 25 01:16:30 [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 41 00 00 01 80 02 00 00 00 0f 0b 00
>Oct 25 01:16:30 [drm:drm_mode_addfb2 [drm]] [FB:113]
>Oct 25 01:16:30 [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000002480bd06
>Oct 25 01:16:30 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000a7a225a5 state to 000000002480bd06
>Oct 25 01:16:30 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 0000000037e40ab3 state to 000000002480bd06
>Oct 25 01:16:30 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:113] for [PLANE:28:plane 1A] state 0000000037e40ab3
>Oct 25 01:16:30 [drm:drm_atomic_check_only [drm]] checking 000000002480bd06
>Oct 25 01:16:30 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 113
>Oct 25 01:16:30 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:30 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45
>Oct 25 01:16:30 [drm:drm_atomic_nonblocking_commit [drm]] committing 000000002480bd06 nonblocking
>Oct 25 01:16:30 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:30 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000002480bd06
>Oct 25 01:16:30 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000002480bd06
>Oct 25 01:16:30 [drm:drm_mode_addfb2 [drm]] [FB:110]
>Oct 25 01:16:30 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000b7798c85
>Oct 25 01:16:30 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 000000002480bd06 state to 00000000b7798c85
>Oct 25 01:16:30 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000e396bf6c state to 00000000b7798c85
>Oct 25 01:16:30 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:28:plane 1A] state 00000000e396bf6c
>Oct 25 01:16:30 [drm:drm_atomic_check_only [drm]] checking 00000000b7798c85
>Oct 25 01:16:30 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 110
>Oct 25 01:16:30 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:30 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45
>Oct 25 01:16:30 [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000b7798c85 nonblocking
>Oct 25 01:16:30 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:30 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000b7798c85
>Oct 25 01:16:30 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000b7798c85
>Oct 25 01:16:30 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000f8616964
>Oct 25 01:16:30 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000f8616964
>Oct 25 01:16:30 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000f8616964
>Oct 25 01:16:30 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000f8616964
>Oct 25 01:16:30 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000f8616964
>Oct 25 01:16:30 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000f8616964
>Oct 25 01:16:30 [drm:gen8_de_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x11101010, pins 0x00000010, long 0x00000000
>Oct 25 01:16:30 [drm:intel_hpd_irq_handler [i915]] digital hpd port A - short
>Oct 25 01:16:30 [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port A - short
>Oct 25 01:16:30 [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 41 00 00 01 80 02 00 00 00 0f 0b 00
>Oct 25 01:16:30 [drm:drm_mode_addfb2 [drm]] [FB:113]
>Oct 25 01:16:30 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000f8616964
>Oct 25 01:16:30 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000b7798c85 state to 00000000f8616964
>Oct 25 01:16:30 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000c1050601 state to 00000000f8616964
>Oct 25 01:16:30 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:113] for [PLANE:28:plane 1A] state 00000000c1050601
>Oct 25 01:16:30 [drm:drm_atomic_check_only [drm]] checking 00000000f8616964
>Oct 25 01:16:30 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 113
>Oct 25 01:16:30 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:30 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45
>Oct 25 01:16:30 [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000f8616964 nonblocking
>Oct 25 01:16:30 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:30 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000f8616964
>Oct 25 01:16:30 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000f8616964
>Oct 25 01:16:30 [drm:gen8_de_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x11101010, pins 0x00000010, long 0x00000000
>Oct 25 01:16:30 [drm:intel_hpd_irq_handler [i915]] digital hpd port A - short
>Oct 25 01:16:30 [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port A - short
>Oct 25 01:16:30 [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 41 00 00 01 80 02 00 00 00 0f 0b 00
>Oct 25 01:16:31 [drm:drm_mode_addfb2 [drm]] [FB:110]
>Oct 25 01:16:31 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000a7a225a5
>Oct 25 01:16:31 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000f8616964 state to 00000000a7a225a5
>Oct 25 01:16:31 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 000000002a08f491 state to 00000000a7a225a5
>Oct 25 01:16:31 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:28:plane 1A] state 000000002a08f491
>Oct 25 01:16:31 [drm:drm_atomic_check_only [drm]] checking 00000000a7a225a5
>Oct 25 01:16:31 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 110
>Oct 25 01:16:31 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:31 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45
>Oct 25 01:16:31 [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000a7a225a5 nonblocking
>Oct 25 01:16:31 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:31 [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000002480bd06
>Oct 25 01:16:31 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000002480bd06
>Oct 25 01:16:31 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000002480bd06
>Oct 25 01:16:31 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000a7a225a5
>Oct 25 01:16:31 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000a7a225a5
>Oct 25 01:16:31 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000002480bd06
>Oct 25 01:16:31 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000002480bd06
>Oct 25 01:16:31 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000002480bd06
>Oct 25 01:16:31 [drm:gen8_de_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x11101010, pins 0x00000010, long 0x00000000
>Oct 25 01:16:31 [drm:intel_hpd_irq_handler [i915]] digital hpd port A - short
>Oct 25 01:16:31 [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port A - short
>Oct 25 01:16:31 [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 41 00 00 01 80 02 00 00 00 0f 0b 00
>Oct 25 01:16:31 [drm:drm_mode_addfb2 [drm]] [FB:113]
>Oct 25 01:16:31 [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000002480bd06
>Oct 25 01:16:31 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000a7a225a5 state to 000000002480bd06
>Oct 25 01:16:31 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000fb2fe074 state to 000000002480bd06
>Oct 25 01:16:31 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:113] for [PLANE:28:plane 1A] state 00000000fb2fe074
>Oct 25 01:16:31 [drm:drm_atomic_check_only [drm]] checking 000000002480bd06
>Oct 25 01:16:31 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 113
>Oct 25 01:16:31 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:31 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45
>Oct 25 01:16:31 [drm:drm_atomic_nonblocking_commit [drm]] committing 000000002480bd06 nonblocking
>Oct 25 01:16:31 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:31 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000002480bd06
>Oct 25 01:16:31 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000002480bd06
>Oct 25 01:16:32 [drm:gen8_de_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x11101010, pins 0x00000010, long 0x00000000
>Oct 25 01:16:32 [drm:intel_hpd_irq_handler [i915]] digital hpd port A - short
>Oct 25 01:16:32 [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port A - short
>Oct 25 01:16:32 [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 41 00 00 01 80 02 00 00 00 0f 0b 00
>Oct 25 01:16:32 [drm:drm_mode_addfb2 [drm]] [FB:110]
>Oct 25 01:16:32 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000b7798c85
>Oct 25 01:16:32 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 000000002480bd06 state to 00000000b7798c85
>Oct 25 01:16:32 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 000000006166d1c9 state to 00000000b7798c85
>Oct 25 01:16:32 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:28:plane 1A] state 000000006166d1c9
>Oct 25 01:16:32 [drm:drm_atomic_check_only [drm]] checking 00000000b7798c85
>Oct 25 01:16:32 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 110
>Oct 25 01:16:32 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:32 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45
>Oct 25 01:16:32 [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000b7798c85 nonblocking
>Oct 25 01:16:32 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:32 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000b7798c85
>Oct 25 01:16:32 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000f8616964
>Oct 25 01:16:32 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000b7798c85
>Oct 25 01:16:32 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000f8616964
>Oct 25 01:16:32 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000f8616964
>Oct 25 01:16:32 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000f8616964
>Oct 25 01:16:32 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000f8616964
>Oct 25 01:16:32 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000f8616964
>Oct 25 01:16:32 [drm:gen8_de_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x11101010, pins 0x00000010, long 0x00000000
>Oct 25 01:16:32 [drm:intel_hpd_irq_handler [i915]] digital hpd port A - short
>Oct 25 01:16:32 [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port A - short
>Oct 25 01:16:32 [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 41 00 00 01 80 02 00 00 00 0f 0b 00
>Oct 25 01:16:32 [drm:drm_mode_addfb2 [drm]] [FB:113]
>Oct 25 01:16:32 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000f22ad9a6
>Oct 25 01:16:32 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000969b0f48 state to 00000000f22ad9a6
>Oct 25 01:16:32 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000df007935 state to 00000000f22ad9a6
>Oct 25 01:16:32 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:113] for [PLANE:28:plane 1A] state 00000000df007935
>Oct 25 01:16:32 [drm:drm_atomic_check_only [drm]] checking 00000000f22ad9a6
>Oct 25 01:16:32 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 113
>Oct 25 01:16:32 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:32 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45
>Oct 25 01:16:32 [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000f22ad9a6 nonblocking
>Oct 25 01:16:32 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:32 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000f22ad9a6
>Oct 25 01:16:32 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000f22ad9a6
>Oct 25 01:16:32 [drm:drm_mode_addfb2 [drm]] [FB:110]
>Oct 25 01:16:32 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000834703a2
>Oct 25 01:16:32 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000f22ad9a6 state to 00000000834703a2
>Oct 25 01:16:32 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 0000000057bd8380 state to 00000000834703a2
>Oct 25 01:16:32 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:28:plane 1A] state 0000000057bd8380
>Oct 25 01:16:32 [drm:drm_atomic_check_only [drm]] checking 00000000834703a2
>Oct 25 01:16:32 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 110
>Oct 25 01:16:32 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:32 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45
>Oct 25 01:16:32 [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000834703a2 nonblocking
>Oct 25 01:16:32 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:32 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000834703a2
>Oct 25 01:16:32 [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000078f5ca8b
>Oct 25 01:16:32 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000078f5ca8b
>Oct 25 01:16:32 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000834703a2
>Oct 25 01:16:32 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000078f5ca8b
>Oct 25 01:16:32 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000078f5ca8b
>Oct 25 01:16:32 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000078f5ca8b
>Oct 25 01:16:32 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000078f5ca8b
>Oct 25 01:16:32 [drm:drm_mode_addfb2 [drm]] [FB:113]
>Oct 25 01:16:32 [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000078f5ca8b
>Oct 25 01:16:32 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 000000009e1f3756 state to 0000000078f5ca8b
>Oct 25 01:16:32 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000a3a7092e state to 0000000078f5ca8b
>Oct 25 01:16:32 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:113] for [PLANE:28:plane 1A] state 00000000a3a7092e
>Oct 25 01:16:32 [drm:drm_atomic_check_only [drm]] checking 0000000078f5ca8b
>Oct 25 01:16:32 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 113
>Oct 25 01:16:32 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:32 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45
>Oct 25 01:16:32 [drm:drm_atomic_nonblocking_commit [drm]] committing 0000000078f5ca8b nonblocking
>Oct 25 01:16:33 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:33 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000078f5ca8b
>Oct 25 01:16:33 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000078f5ca8b
>Oct 25 01:16:33 [drm:gen8_de_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x11101010, pins 0x00000010, long 0x00000000
>Oct 25 01:16:33 [drm:intel_hpd_irq_handler [i915]] digital hpd port A - short
>Oct 25 01:16:33 [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port A - short
>Oct 25 01:16:33 [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 41 00 00 01 80 02 00 00 00 0f 0b 00
>Oct 25 01:16:33 [drm:drm_mode_addfb2 [drm]] [FB:110]
>Oct 25 01:16:33 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000f8616964
>Oct 25 01:16:33 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 000000002480bd06 state to 00000000f8616964
>Oct 25 01:16:33 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 000000007b0042d5 state to 00000000f8616964
>Oct 25 01:16:33 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:28:plane 1A] state 000000007b0042d5
>Oct 25 01:16:33 [drm:drm_atomic_check_only [drm]] checking 00000000f8616964
>Oct 25 01:16:33 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 110
>Oct 25 01:16:33 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:33 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45
>Oct 25 01:16:33 [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000f8616964 nonblocking
>Oct 25 01:16:33 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:33 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000f1ecca12
>Oct 25 01:16:33 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000f1ecca12
>Oct 25 01:16:33 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000f8616964
>Oct 25 01:16:33 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000f8616964
>Oct 25 01:16:33 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000f1ecca12
>Oct 25 01:16:33 [drm:gen8_de_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x11101010, pins 0x00000010, long 0x00000000
>Oct 25 01:16:33 [drm:intel_hpd_irq_handler [i915]] digital hpd port A - short
>Oct 25 01:16:33 [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port A - short
>Oct 25 01:16:33 [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 41 00 00 01 80 02 00 00 00 0f 0b 00
>Oct 25 01:16:34 [drm:drm_mode_addfb2 [drm]] [FB:113]
>Oct 25 01:16:34 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000f1ecca12
>Oct 25 01:16:34 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000217e0795 state to 00000000f1ecca12
>Oct 25 01:16:34 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 000000005e7e9301 state to 00000000f1ecca12
>Oct 25 01:16:34 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:113] for [PLANE:28:plane 1A] state 000000005e7e9301
>Oct 25 01:16:34 [drm:drm_atomic_check_only [drm]] checking 00000000f1ecca12
>Oct 25 01:16:34 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 113
>Oct 25 01:16:34 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:34 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45
>Oct 25 01:16:34 [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000f1ecca12 nonblocking
>Oct 25 01:16:34 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:34 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000f1ecca12
>Oct 25 01:16:34 [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000001cc9f018
>Oct 25 01:16:34 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000f1ecca12
>Oct 25 01:16:34 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000001cc9f018
>Oct 25 01:16:34 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000001cc9f018
>Oct 25 01:16:34 [drm:drm_mode_addfb2 [drm]] [FB:110]
>Oct 25 01:16:34 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000f1ecca12
>Oct 25 01:16:34 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000888ce6dc state to 00000000f1ecca12
>Oct 25 01:16:34 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000baae07e3 state to 00000000f1ecca12
>Oct 25 01:16:34 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:28:plane 1A] state 00000000baae07e3
>Oct 25 01:16:34 [drm:drm_atomic_check_only [drm]] checking 00000000f1ecca12
>Oct 25 01:16:34 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 110
>Oct 25 01:16:34 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:34 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45
>Oct 25 01:16:34 [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000f1ecca12 nonblocking
>Oct 25 01:16:34 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:34 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000f1ecca12
>Oct 25 01:16:34 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000e53e1ae0
>Oct 25 01:16:34 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000e53e1ae0
>Oct 25 01:16:34 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000e53e1ae0
>Oct 25 01:16:34 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000f1ecca12
>Oct 25 01:16:34 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000e53e1ae0
>Oct 25 01:16:34 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000e53e1ae0
>Oct 25 01:16:34 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000e53e1ae0
>Oct 25 01:16:34 [drm:gen8_de_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x11101010, pins 0x00000010, long 0x00000000
>Oct 25 01:16:34 [drm:intel_hpd_irq_handler [i915]] digital hpd port A - short
>Oct 25 01:16:34 [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port A - short
>Oct 25 01:16:34 [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 41 00 00 01 80 02 00 00 00 0f 0b 00
>Oct 25 01:16:34 [drm:drm_mode_addfb2 [drm]] [FB:113]
>Oct 25 01:16:34 [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000002199d420
>Oct 25 01:16:34 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000f58b00ef state to 000000002199d420
>Oct 25 01:16:34 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 0000000015ac6fed state to 000000002199d420
>Oct 25 01:16:34 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:113] for [PLANE:28:plane 1A] state 0000000015ac6fed
>Oct 25 01:16:34 [drm:drm_atomic_check_only [drm]] checking 000000002199d420
>Oct 25 01:16:34 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 113
>Oct 25 01:16:34 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:34 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45
>Oct 25 01:16:34 [drm:drm_atomic_nonblocking_commit [drm]] committing 000000002199d420 nonblocking
>Oct 25 01:16:34 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:34 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000002199d420
>Oct 25 01:16:34 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000e53e1ae0
>Oct 25 01:16:34 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000e53e1ae0
>Oct 25 01:16:34 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000002199d420
>Oct 25 01:16:34 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000e53e1ae0
>Oct 25 01:16:34 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000e53e1ae0
>Oct 25 01:16:34 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000e53e1ae0
>Oct 25 01:16:34 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000e53e1ae0
>Oct 25 01:16:34 [drm:gen8_de_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x11101010, pins 0x00000010, long 0x00000000
>Oct 25 01:16:34 [drm:intel_hpd_irq_handler [i915]] digital hpd port A - short
>Oct 25 01:16:34 [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port A - short
>Oct 25 01:16:34 [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 41 00 00 01 80 02 00 00 00 0f 0b 00
>Oct 25 01:16:34 [drm:drm_mode_addfb2 [drm]] [FB:110]
>Oct 25 01:16:34 [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000002199d420
>Oct 25 01:16:34 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 000000001c5aa71e state to 000000002199d420
>Oct 25 01:16:34 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 0000000025735428 state to 000000002199d420
>Oct 25 01:16:34 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:28:plane 1A] state 0000000025735428
>Oct 25 01:16:34 [drm:drm_atomic_check_only [drm]] checking 000000002199d420
>Oct 25 01:16:34 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 110
>Oct 25 01:16:34 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:34 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45
>Oct 25 01:16:34 [drm:drm_atomic_nonblocking_commit [drm]] committing 000000002199d420 nonblocking
>Oct 25 01:16:34 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:34 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000002199d420
>Oct 25 01:16:34 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000a036df3f
>Oct 25 01:16:34 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000002199d420
>Oct 25 01:16:34 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000a036df3f
>Oct 25 01:16:34 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000a036df3f
>Oct 25 01:16:34 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000a036df3f
>Oct 25 01:16:34 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000a036df3f
>Oct 25 01:16:34 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000a036df3f
>Oct 25 01:16:34 [drm:gen8_de_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x11101010, pins 0x00000010, long 0x00000000
>Oct 25 01:16:34 [drm:intel_hpd_irq_handler [i915]] digital hpd port A - short
>Oct 25 01:16:34 [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port A - short
>Oct 25 01:16:34 [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 41 00 00 01 80 02 00 00 00 0f 0b 00
>Oct 25 01:16:35 [drm:drm_mode_addfb2 [drm]] [FB:113]
>Oct 25 01:16:35 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000a036df3f
>Oct 25 01:16:35 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 0000000062f8df16 state to 00000000a036df3f
>Oct 25 01:16:35 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000fa374140 state to 00000000a036df3f
>Oct 25 01:16:35 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:113] for [PLANE:28:plane 1A] state 00000000fa374140
>Oct 25 01:16:35 [drm:drm_atomic_check_only [drm]] checking 00000000a036df3f
>Oct 25 01:16:35 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 113
>Oct 25 01:16:35 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:35 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45
>Oct 25 01:16:35 [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000a036df3f nonblocking
>Oct 25 01:16:35 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:35 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000a036df3f
>Oct 25 01:16:35 [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000005e33b12
>Oct 25 01:16:35 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000a036df3f
>Oct 25 01:16:35 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000005e33b12
>Oct 25 01:16:35 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000005e33b12
>Oct 25 01:16:35 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000005e33b12
>Oct 25 01:16:35 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000005e33b12
>Oct 25 01:16:35 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000005e33b12
>Oct 25 01:16:35 [drm:drm_mode_addfb2 [drm]] [FB:110]
>Oct 25 01:16:35 [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000005e33b12
>Oct 25 01:16:35 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000a930749a state to 0000000005e33b12
>Oct 25 01:16:35 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000fae218d6 state to 0000000005e33b12
>Oct 25 01:16:35 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:28:plane 1A] state 00000000fae218d6
>Oct 25 01:16:35 [drm:drm_atomic_check_only [drm]] checking 0000000005e33b12
>Oct 25 01:16:35 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 110
>Oct 25 01:16:35 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:35 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45
>Oct 25 01:16:35 [drm:drm_atomic_nonblocking_commit [drm]] committing 0000000005e33b12 nonblocking
>Oct 25 01:16:35 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:35 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000005e33b12
>Oct 25 01:16:35 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000005e33b12
>Oct 25 01:16:35 [drm:gen8_de_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x11101010, pins 0x00000010, long 0x00000000
>Oct 25 01:16:35 [drm:intel_hpd_irq_handler [i915]] digital hpd port A - short
>Oct 25 01:16:35 [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port A - short
>Oct 25 01:16:35 [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 41 00 00 01 80 02 00 00 00 0f 0b 00
>Oct 25 01:16:35 [drm:drm_mode_addfb2 [drm]] [FB:113]
>Oct 25 01:16:35 [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000026e30fbc
>Oct 25 01:16:35 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 0000000053594abf state to 0000000026e30fbc
>Oct 25 01:16:35 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000ab69dab2 state to 0000000026e30fbc
>Oct 25 01:16:35 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:113] for [PLANE:28:plane 1A] state 00000000ab69dab2
>Oct 25 01:16:35 [drm:drm_atomic_check_only [drm]] checking 0000000026e30fbc
>Oct 25 01:16:35 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 113
>Oct 25 01:16:35 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:35 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45
>Oct 25 01:16:35 [drm:drm_atomic_nonblocking_commit [drm]] committing 0000000026e30fbc nonblocking
>Oct 25 01:16:35 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:35 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000026e30fbc
>Oct 25 01:16:35 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000026e30fbc
>Oct 25 01:16:35 [drm:gen8_de_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x11101010, pins 0x00000010, long 0x00000000
>Oct 25 01:16:35 [drm:intel_hpd_irq_handler [i915]] digital hpd port A - short
>Oct 25 01:16:35 [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port A - short
>Oct 25 01:16:35 [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 41 00 00 01 80 02 00 00 00 0f 0b 00
>Oct 25 01:16:36 [drm:drm_mode_addfb2 [drm]] [FB:110]
>Oct 25 01:16:36 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000981adb63
>Oct 25 01:16:36 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000c4423c76 state to 00000000981adb63
>Oct 25 01:16:36 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 0000000095425241 state to 00000000981adb63
>Oct 25 01:16:36 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:28:plane 1A] state 0000000095425241
>Oct 25 01:16:36 [drm:drm_atomic_check_only [drm]] checking 00000000981adb63
>Oct 25 01:16:36 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 110
>Oct 25 01:16:36 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:36 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45
>Oct 25 01:16:36 [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000981adb63 nonblocking
>Oct 25 01:16:36 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:36 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000981adb63
>Oct 25 01:16:36 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000981adb63
>Oct 25 01:16:36 [drm:gen8_de_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x11101010, pins 0x00000010, long 0x00000000
>Oct 25 01:16:36 [drm:intel_hpd_irq_handler [i915]] digital hpd port A - short
>Oct 25 01:16:36 [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port A - short
>Oct 25 01:16:36 [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 41 00 00 01 80 02 00 00 00 0f 0b 00
>Oct 25 01:16:36 [drm:drm_mode_addfb2 [drm]] [FB:113]
>Oct 25 01:16:36 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000aa1400b5
>Oct 25 01:16:36 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 0000000031de9364 state to 00000000aa1400b5
>Oct 25 01:16:36 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 0000000006c6ab14 state to 00000000aa1400b5
>Oct 25 01:16:36 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:113] for [PLANE:28:plane 1A] state 0000000006c6ab14
>Oct 25 01:16:36 [drm:drm_atomic_check_only [drm]] checking 00000000aa1400b5
>Oct 25 01:16:36 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 113
>Oct 25 01:16:36 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:36 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45
>Oct 25 01:16:36 [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000aa1400b5 nonblocking
>Oct 25 01:16:36 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:36 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000aa1400b5
>Oct 25 01:16:36 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000f8616964
>Oct 25 01:16:36 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000aa1400b5
>Oct 25 01:16:36 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000f8616964
>Oct 25 01:16:36 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000f8616964
>Oct 25 01:16:36 [drm:drm_mode_addfb2 [drm]] [FB:110]
>Oct 25 01:16:36 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000f8616964
>Oct 25 01:16:36 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000b7798c85 state to 00000000f8616964
>Oct 25 01:16:36 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 0000000037e40ab3 state to 00000000f8616964
>Oct 25 01:16:36 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:28:plane 1A] state 0000000037e40ab3
>Oct 25 01:16:36 [drm:drm_atomic_check_only [drm]] checking 00000000f8616964
>Oct 25 01:16:36 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 110
>Oct 25 01:16:36 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:36 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45
>Oct 25 01:16:36 [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000f8616964 nonblocking
>Oct 25 01:16:36 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:36 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000f8616964
>Oct 25 01:16:36 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000a7a225a5
>Oct 25 01:16:36 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000f8616964
>Oct 25 01:16:36 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000a7a225a5
>Oct 25 01:16:36 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000a7a225a5
>Oct 25 01:16:36 [drm:gen8_de_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x11101010, pins 0x00000010, long 0x00000000
>Oct 25 01:16:36 [drm:intel_hpd_irq_handler [i915]] digital hpd port A - short
>Oct 25 01:16:36 [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port A - short
>Oct 25 01:16:36 [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 41 00 00 01 80 02 00 00 00 0f 0b 00
>Oct 25 01:16:37 [drm:drm_mode_addfb2 [drm]] [FB:113]
>Oct 25 01:16:37 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000a7a225a5
>Oct 25 01:16:37 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000f8616964 state to 00000000a7a225a5
>Oct 25 01:16:37 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000f87b65b5 state to 00000000a7a225a5
>Oct 25 01:16:37 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:113] for [PLANE:28:plane 1A] state 00000000f87b65b5
>Oct 25 01:16:37 [drm:drm_atomic_check_only [drm]] checking 00000000a7a225a5
>Oct 25 01:16:37 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 113
>Oct 25 01:16:37 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:37 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45
>Oct 25 01:16:37 [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000a7a225a5 nonblocking
>Oct 25 01:16:37 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:37 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000a7a225a5
>Oct 25 01:16:37 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000a7a225a5
>Oct 25 01:16:37 [drm:gen8_de_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x11101010, pins 0x00000010, long 0x00000000
>Oct 25 01:16:37 [drm:intel_hpd_irq_handler [i915]] digital hpd port A - short
>Oct 25 01:16:37 [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port A - short
>Oct 25 01:16:37 [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 41 00 00 01 80 02 00 00 00 0f 0b 00
>Oct 25 01:16:37 [drm:drm_mode_addfb2 [drm]] [FB:110]
>Oct 25 01:16:37 [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000009e1f3756
>Oct 25 01:16:37 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000f93b029f state to 000000009e1f3756
>Oct 25 01:16:37 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000f8c1b653 state to 000000009e1f3756
>Oct 25 01:16:37 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:28:plane 1A] state 00000000f8c1b653
>Oct 25 01:16:37 [drm:drm_atomic_check_only [drm]] checking 000000009e1f3756
>Oct 25 01:16:37 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 110
>Oct 25 01:16:37 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:37 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45
>Oct 25 01:16:37 [drm:drm_atomic_nonblocking_commit [drm]] committing 000000009e1f3756 nonblocking
>Oct 25 01:16:37 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:37 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000009e1f3756
>Oct 25 01:16:37 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000009e1f3756
>Oct 25 01:16:37 [drm:gen8_de_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x11101010, pins 0x00000010, long 0x00000000
>Oct 25 01:16:37 [drm:intel_hpd_irq_handler [i915]] digital hpd port A - short
>Oct 25 01:16:37 [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port A - short
>Oct 25 01:16:37 [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 41 00 00 01 80 02 00 00 00 0f 0b 00
>Oct 25 01:16:37 [drm:drm_mode_addfb2 [drm]] [FB:113]
>Oct 25 01:16:37 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000226abb0c
>Oct 25 01:16:37 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000606364d3 state to 00000000226abb0c
>Oct 25 01:16:37 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000d6657de7 state to 00000000226abb0c
>Oct 25 01:16:37 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:113] for [PLANE:28:plane 1A] state 00000000d6657de7
>Oct 25 01:16:37 [drm:drm_atomic_check_only [drm]] checking 00000000226abb0c
>Oct 25 01:16:37 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 113
>Oct 25 01:16:37 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:37 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45
>Oct 25 01:16:37 [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000226abb0c nonblocking
>Oct 25 01:16:37 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:37 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000935c3744
>Oct 25 01:16:37 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000226abb0c
>Oct 25 01:16:37 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000226abb0c
>Oct 25 01:16:37 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000935c3744
>Oct 25 01:16:37 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000935c3744
>Oct 25 01:16:37 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000935c3744
>Oct 25 01:16:37 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000935c3744
>Oct 25 01:16:37 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000935c3744
>Oct 25 01:16:37 [drm:drm_mode_addfb2 [drm]] [FB:110]
>Oct 25 01:16:37 [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000002aa35c4f
>Oct 25 01:16:37 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000f22ad9a6 state to 000000002aa35c4f
>Oct 25 01:16:37 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000e2388a2b state to 000000002aa35c4f
>Oct 25 01:16:37 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:28:plane 1A] state 00000000e2388a2b
>Oct 25 01:16:37 [drm:drm_atomic_check_only [drm]] checking 000000002aa35c4f
>Oct 25 01:16:37 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 110
>Oct 25 01:16:37 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:37 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45
>Oct 25 01:16:37 [drm:drm_atomic_nonblocking_commit [drm]] committing 000000002aa35c4f nonblocking
>Oct 25 01:16:37 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:37 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000002aa35c4f
>Oct 25 01:16:37 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000002aa35c4f
>Oct 25 01:16:37 [drm:drm_mode_addfb2 [drm]] [FB:113]
>Oct 25 01:16:37 [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000002480bd06
>Oct 25 01:16:37 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000f8616964 state to 000000002480bd06
>Oct 25 01:16:37 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000fb2fe074 state to 000000002480bd06
>Oct 25 01:16:37 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:113] for [PLANE:28:plane 1A] state 00000000fb2fe074
>Oct 25 01:16:37 [drm:drm_atomic_check_only [drm]] checking 000000002480bd06
>Oct 25 01:16:37 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 113
>Oct 25 01:16:37 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:37 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45
>Oct 25 01:16:37 [drm:drm_atomic_nonblocking_commit [drm]] committing 000000002480bd06 nonblocking
>Oct 25 01:16:37 [drm:gen8_de_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x11101010, pins 0x00000010, long 0x00000000
>Oct 25 01:16:37 [drm:intel_hpd_irq_handler [i915]] digital hpd port A - short
>Oct 25 01:16:37 [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port A - short
>Oct 25 01:16:37 [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 41 00 00 01 80 02 00 00 00 0f 0b 00
>Oct 25 01:16:37 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:37 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000002480bd06
>Oct 25 01:16:37 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000002480bd06
>Oct 25 01:16:38 [drm:drm_mode_addfb2 [drm]] [FB:110]
>Oct 25 01:16:38 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000a7a225a5
>Oct 25 01:16:38 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000b7798c85 state to 00000000a7a225a5
>Oct 25 01:16:38 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000c1050601 state to 00000000a7a225a5
>Oct 25 01:16:38 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:28:plane 1A] state 00000000c1050601
>Oct 25 01:16:38 [drm:drm_atomic_check_only [drm]] checking 00000000a7a225a5
>Oct 25 01:16:38 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 110
>Oct 25 01:16:38 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:38 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45
>Oct 25 01:16:38 [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000a7a225a5 nonblocking
>Oct 25 01:16:38 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:38 [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000002480bd06
>Oct 25 01:16:38 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000002480bd06
>Oct 25 01:16:38 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000a7a225a5
>Oct 25 01:16:38 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000a7a225a5
>Oct 25 01:16:38 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000002480bd06
>Oct 25 01:16:38 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000002480bd06
>Oct 25 01:16:38 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000002480bd06
>Oct 25 01:16:38 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000002480bd06
>Oct 25 01:16:38 [drm:drm_mode_addfb2 [drm]] [FB:113]
>Oct 25 01:16:38 [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000002480bd06
>Oct 25 01:16:38 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 000000009ee0b018 state to 000000002480bd06
>Oct 25 01:16:38 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 000000008b497eb0 state to 000000002480bd06
>Oct 25 01:16:38 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:113] for [PLANE:28:plane 1A] state 000000008b497eb0
>Oct 25 01:16:38 [drm:drm_atomic_check_only [drm]] checking 000000002480bd06
>Oct 25 01:16:38 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 113
>Oct 25 01:16:38 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:38 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45
>Oct 25 01:16:38 [drm:drm_atomic_nonblocking_commit [drm]] committing 000000002480bd06 nonblocking
>Oct 25 01:16:38 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:38 [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000008a7d870b
>Oct 25 01:16:38 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000002480bd06
>Oct 25 01:16:38 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000002480bd06
>Oct 25 01:16:38 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000008a7d870b
>Oct 25 01:16:38 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000008a7d870b
>Oct 25 01:16:38 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000008a7d870b
>Oct 25 01:16:38 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000008a7d870b
>Oct 25 01:16:38 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000008a7d870b
>Oct 25 01:16:38 [drm:drm_mode_addfb2 [drm]] [FB:110]
>Oct 25 01:16:38 [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000008a7d870b
>Oct 25 01:16:38 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000a7a225a5 state to 000000008a7d870b
>Oct 25 01:16:38 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 000000006166d1c9 state to 000000008a7d870b
>Oct 25 01:16:38 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:28:plane 1A] state 000000006166d1c9
>Oct 25 01:16:38 [drm:drm_atomic_check_only [drm]] checking 000000008a7d870b
>Oct 25 01:16:38 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 110
>Oct 25 01:16:38 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:38 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45
>Oct 25 01:16:38 [drm:drm_atomic_nonblocking_commit [drm]] committing 000000008a7d870b nonblocking
>Oct 25 01:16:38 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:38 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000f8616964
>Oct 25 01:16:38 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000f8616964
>Oct 25 01:16:38 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000008a7d870b
>Oct 25 01:16:38 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000008a7d870b
>Oct 25 01:16:38 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000f8616964
>Oct 25 01:16:38 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000f8616964
>Oct 25 01:16:38 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000f8616964
>Oct 25 01:16:38 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000f8616964
>Oct 25 01:16:38 [drm:gen8_de_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x11101010, pins 0x00000010, long 0x00000000
>Oct 25 01:16:38 [drm:intel_hpd_irq_handler [i915]] digital hpd port A - short
>Oct 25 01:16:38 [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port A - short
>Oct 25 01:16:38 [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 41 00 00 01 80 02 00 00 00 0f 0b 00
>Oct 25 01:16:39 [drm:drm_mode_addfb2 [drm]] [FB:113]
>Oct 25 01:16:39 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000f8616964
>Oct 25 01:16:39 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 000000008a7d870b state to 00000000f8616964
>Oct 25 01:16:39 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 0000000037e40ab3 state to 00000000f8616964
>Oct 25 01:16:39 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:113] for [PLANE:28:plane 1A] state 0000000037e40ab3
>Oct 25 01:16:39 [drm:drm_atomic_check_only [drm]] checking 00000000f8616964
>Oct 25 01:16:39 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 113
>Oct 25 01:16:39 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:39 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45
>Oct 25 01:16:39 [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000f8616964 nonblocking
>Oct 25 01:16:39 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:39 [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000009ee0b018
>Oct 25 01:16:39 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000f8616964
>Oct 25 01:16:39 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000f8616964
>Oct 25 01:16:39 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000009ee0b018
>Oct 25 01:16:39 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000009ee0b018
>Oct 25 01:16:40 [drm:gen8_de_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x11101010, pins 0x00000010, long 0x00000000
>Oct 25 01:16:40 [drm:intel_hpd_irq_handler [i915]] digital hpd port A - short
>Oct 25 01:16:40 [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port A - short
>Oct 25 01:16:40 [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 41 00 00 01 80 02 00 00 00 0f 0b 00
>Oct 25 01:16:40 [drm:drm_mode_addfb2 [drm]] [FB:110]
>Oct 25 01:16:40 [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000009ee0b018
>Oct 25 01:16:40 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 000000002480bd06 state to 000000009ee0b018
>Oct 25 01:16:40 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000fb2fe074 state to 000000009ee0b018
>Oct 25 01:16:40 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:28:plane 1A] state 00000000fb2fe074
>Oct 25 01:16:40 [drm:drm_atomic_check_only [drm]] checking 000000009ee0b018
>Oct 25 01:16:40 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 110
>Oct 25 01:16:40 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:40 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45
>Oct 25 01:16:40 [drm:drm_atomic_nonblocking_commit [drm]] committing 000000009ee0b018 nonblocking
>Oct 25 01:16:40 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:40 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000009ee0b018
>Oct 25 01:16:40 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000b7798c85
>Oct 25 01:16:40 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000009ee0b018
>Oct 25 01:16:40 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000b7798c85
>Oct 25 01:16:40 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000b7798c85
>Oct 25 01:16:40 [drm:gen8_de_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x11101010, pins 0x00000010, long 0x00000000
>Oct 25 01:16:40 [drm:intel_hpd_irq_handler [i915]] digital hpd port A - short
>Oct 25 01:16:40 [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port A - short
>Oct 25 01:16:40 [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 41 00 00 01 80 02 00 00 00 0f 0b 00
>Oct 25 01:16:40 [drm:drm_mode_addfb2 [drm]] [FB:113]
>Oct 25 01:16:40 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000b7798c85
>Oct 25 01:16:40 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 000000009ee0b018 state to 00000000b7798c85
>Oct 25 01:16:40 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000e396bf6c state to 00000000b7798c85
>Oct 25 01:16:40 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:113] for [PLANE:28:plane 1A] state 00000000e396bf6c
>Oct 25 01:16:40 [drm:drm_atomic_check_only [drm]] checking 00000000b7798c85
>Oct 25 01:16:40 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 113
>Oct 25 01:16:40 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:40 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45
>Oct 25 01:16:40 [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000b7798c85 nonblocking
>Oct 25 01:16:40 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:40 [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000008a7d870b
>Oct 25 01:16:40 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000b7798c85
>Oct 25 01:16:40 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000b7798c85
>Oct 25 01:16:40 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000008a7d870b
>Oct 25 01:16:40 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000008a7d870b
>Oct 25 01:16:40 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000008a7d870b
>Oct 25 01:16:40 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000008a7d870b
>Oct 25 01:16:40 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000008a7d870b
>Oct 25 01:16:40 [drm:drm_mode_addfb2 [drm]] [FB:110]
>Oct 25 01:16:40 [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000001cc9f018
>Oct 25 01:16:40 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 000000000ab4b2fc state to 000000001cc9f018
>Oct 25 01:16:40 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000c3022ad1 state to 000000001cc9f018
>Oct 25 01:16:40 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:28:plane 1A] state 00000000c3022ad1
>Oct 25 01:16:40 [drm:drm_atomic_check_only [drm]] checking 000000001cc9f018
>Oct 25 01:16:40 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 110
>Oct 25 01:16:40 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:40 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45
>Oct 25 01:16:40 [drm:drm_atomic_nonblocking_commit [drm]] committing 000000001cc9f018 nonblocking
>Oct 25 01:16:41 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:41 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000c92b4d9a
>Oct 25 01:16:41 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000c92b4d9a
>Oct 25 01:16:41 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000001cc9f018
>Oct 25 01:16:41 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000001cc9f018
>Oct 25 01:16:41 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000c92b4d9a
>Oct 25 01:16:41 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000c92b4d9a
>Oct 25 01:16:41 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000c92b4d9a
>Oct 25 01:16:41 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000c92b4d9a
>Oct 25 01:16:41 [drm:drm_mode_addfb2 [drm]] [FB:113]
>Oct 25 01:16:41 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000c92b4d9a
>Oct 25 01:16:41 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 000000001cc9f018 state to 00000000c92b4d9a
>Oct 25 01:16:41 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 000000008e8b0461 state to 00000000c92b4d9a
>Oct 25 01:16:41 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:113] for [PLANE:28:plane 1A] state 000000008e8b0461
>Oct 25 01:16:41 [drm:drm_atomic_check_only [drm]] checking 00000000c92b4d9a
>Oct 25 01:16:41 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 113
>Oct 25 01:16:41 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:41 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45
>Oct 25 01:16:41 [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000c92b4d9a nonblocking
>Oct 25 01:16:41 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:41 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000ff023107
>Oct 25 01:16:41 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000ff023107
>Oct 25 01:16:41 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000c92b4d9a
>Oct 25 01:16:41 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000c92b4d9a
>Oct 25 01:16:41 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000ff023107
>Oct 25 01:16:41 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000ff023107
>Oct 25 01:16:41 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000ff023107
>Oct 25 01:16:41 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000ff023107
>Oct 25 01:16:41 [drm:gen8_de_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x11101010, pins 0x00000010, long 0x00000000
>Oct 25 01:16:41 [drm:intel_hpd_irq_handler [i915]] digital hpd port A - short
>Oct 25 01:16:41 [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port A - short
>Oct 25 01:16:41 [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 41 00 00 01 80 02 00 00 00 0f 0b 00
>Oct 25 01:16:41 [drm:drm_mode_addfb2 [drm]] [FB:110]
>Oct 25 01:16:41 [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000008a7d870b
>Oct 25 01:16:41 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000f8616964 state to 000000008a7d870b
>Oct 25 01:16:41 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000f87b65b5 state to 000000008a7d870b
>Oct 25 01:16:41 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:28:plane 1A] state 00000000f87b65b5
>Oct 25 01:16:41 [drm:drm_atomic_check_only [drm]] checking 000000008a7d870b
>Oct 25 01:16:41 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 110
>Oct 25 01:16:41 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:41 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45
>Oct 25 01:16:41 [drm:drm_atomic_nonblocking_commit [drm]] committing 000000008a7d870b nonblocking
>Oct 25 01:16:41 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:41 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000a7a225a5
>Oct 25 01:16:41 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000a7a225a5
>Oct 25 01:16:41 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000008a7d870b
>Oct 25 01:16:41 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000008a7d870b
>Oct 25 01:16:41 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000a7a225a5
>Oct 25 01:16:41 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000a7a225a5
>Oct 25 01:16:41 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000a7a225a5
>Oct 25 01:16:41 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000a7a225a5
>Oct 25 01:16:41 [drm:gen8_de_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x11101010, pins 0x00000010, long 0x00000000
>Oct 25 01:16:41 [drm:intel_hpd_irq_handler [i915]] digital hpd port A - short
>Oct 25 01:16:41 [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port A - short
>Oct 25 01:16:41 [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 41 00 00 01 80 02 00 00 00 0f 0b 00
>Oct 25 01:16:41 [drm:drm_mode_addfb2 [drm]] [FB:113]
>Oct 25 01:16:41 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000a7a225a5
>Oct 25 01:16:41 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 000000008a7d870b state to 00000000a7a225a5
>Oct 25 01:16:41 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 000000006166d1c9 state to 00000000a7a225a5
>Oct 25 01:16:41 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:113] for [PLANE:28:plane 1A] state 000000006166d1c9
>Oct 25 01:16:41 [drm:drm_atomic_check_only [drm]] checking 00000000a7a225a5
>Oct 25 01:16:41 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 113
>Oct 25 01:16:41 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:41 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45
>Oct 25 01:16:41 [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000a7a225a5 nonblocking
>Oct 25 01:16:41 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:41 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000a7a225a5
>Oct 25 01:16:41 [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000009ee0b018
>Oct 25 01:16:41 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000009ee0b018
>Oct 25 01:16:41 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000a7a225a5
>Oct 25 01:16:41 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000009ee0b018
>Oct 25 01:16:41 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000009ee0b018
>Oct 25 01:16:41 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000009ee0b018
>Oct 25 01:16:41 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000009ee0b018
>Oct 25 01:16:41 [drm:drm_mode_addfb2 [drm]] [FB:110]
>Oct 25 01:16:41 [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000009ee0b018
>Oct 25 01:16:41 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000b7798c85 state to 000000009ee0b018
>Oct 25 01:16:41 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 000000008b497eb0 state to 000000009ee0b018
>Oct 25 01:16:41 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:28:plane 1A] state 000000008b497eb0
>Oct 25 01:16:41 [drm:drm_atomic_check_only [drm]] checking 000000009ee0b018
>Oct 25 01:16:41 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 110
>Oct 25 01:16:41 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:41 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45
>Oct 25 01:16:41 [drm:drm_atomic_nonblocking_commit [drm]] committing 000000009ee0b018 nonblocking
>Oct 25 01:16:41 [drm:gen8_de_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x11101010, pins 0x00000010, long 0x00000000
>Oct 25 01:16:41 [drm:intel_hpd_irq_handler [i915]] digital hpd port A - short
>Oct 25 01:16:41 [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port A - short
>Oct 25 01:16:41 [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 41 00 00 01 80 02 00 00 00 0f 0b 00
>Oct 25 01:16:41 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:41 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000009ee0b018
>Oct 25 01:16:41 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000009ee0b018
>Oct 25 01:16:41 [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000002480bd06
>Oct 25 01:16:41 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000002480bd06
>Oct 25 01:16:41 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000002480bd06
>Oct 25 01:16:41 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000002480bd06
>Oct 25 01:16:41 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000002480bd06
>Oct 25 01:16:41 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000002480bd06
>Oct 25 01:16:42 [drm:drm_mode_addfb2 [drm]] [FB:113]
>Oct 25 01:16:42 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000e53e1ae0
>Oct 25 01:16:42 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000888ce6dc state to 00000000e53e1ae0
>Oct 25 01:16:42 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000682e5d75 state to 00000000e53e1ae0
>Oct 25 01:16:42 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:113] for [PLANE:28:plane 1A] state 00000000682e5d75
>Oct 25 01:16:42 [drm:drm_atomic_check_only [drm]] checking 00000000e53e1ae0
>Oct 25 01:16:42 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 113
>Oct 25 01:16:42 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:42 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45
>Oct 25 01:16:42 [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000e53e1ae0 nonblocking
>Oct 25 01:16:42 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000f1ecca12
>Oct 25 01:16:42 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:42 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000f1ecca12
>Oct 25 01:16:42 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000e53e1ae0
>Oct 25 01:16:42 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000e53e1ae0
>Oct 25 01:16:42 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000f1ecca12
>Oct 25 01:16:42 [drm:gen8_de_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x11101010, pins 0x00000010, long 0x00000000
>Oct 25 01:16:42 [drm:intel_hpd_irq_handler [i915]] digital hpd port A - short
>Oct 25 01:16:42 [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port A - short
>Oct 25 01:16:42 [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 41 00 00 01 80 02 00 00 00 0f 0b 00
>Oct 25 01:16:42 [drm:drm_mode_addfb2 [drm]] [FB:110]
>Oct 25 01:16:42 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000f1ecca12
>Oct 25 01:16:42 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000217e0795 state to 00000000f1ecca12
>Oct 25 01:16:42 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000e318f39f state to 00000000f1ecca12
>Oct 25 01:16:42 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:28:plane 1A] state 00000000e318f39f
>Oct 25 01:16:42 [drm:drm_atomic_check_only [drm]] checking 00000000f1ecca12
>Oct 25 01:16:42 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 110
>Oct 25 01:16:42 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:42 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45
>Oct 25 01:16:42 [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000f1ecca12 nonblocking
>Oct 25 01:16:42 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:42 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000f1ecca12
>Oct 25 01:16:42 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000e53e1ae0
>Oct 25 01:16:42 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000f1ecca12
>Oct 25 01:16:42 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000e53e1ae0
>Oct 25 01:16:42 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000e53e1ae0
>Oct 25 01:16:42 [drm:drm_mode_addfb2 [drm]] [FB:113]
>Oct 25 01:16:42 [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000000417025f
>Oct 25 01:16:42 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000df4df6eb state to 000000000417025f
>Oct 25 01:16:42 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000abd75e56 state to 000000000417025f
>Oct 25 01:16:42 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:113] for [PLANE:28:plane 1A] state 00000000abd75e56
>Oct 25 01:16:42 [drm:drm_atomic_check_only [drm]] checking 000000000417025f
>Oct 25 01:16:42 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 113
>Oct 25 01:16:42 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:42 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45
>Oct 25 01:16:42 [drm:drm_atomic_nonblocking_commit [drm]] committing 000000000417025f nonblocking
>Oct 25 01:16:42 [drm:gen8_de_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x11101010, pins 0x00000010, long 0x00000000
>Oct 25 01:16:42 [drm:intel_hpd_irq_handler [i915]] digital hpd port A - short
>Oct 25 01:16:42 [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port A - short
>Oct 25 01:16:42 [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 41 00 00 01 80 02 00 00 00 0f 0b 00
>Oct 25 01:16:42 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:42 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000000417025f
>Oct 25 01:16:42 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000884bfc9b
>Oct 25 01:16:42 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000884bfc9b
>Oct 25 01:16:42 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000884bfc9b
>Oct 25 01:16:42 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000000417025f
>Oct 25 01:16:42 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000884bfc9b
>Oct 25 01:16:42 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000884bfc9b
>Oct 25 01:16:42 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000884bfc9b
>Oct 25 01:16:42 [drm:gen8_de_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x11101010, pins 0x00000010, long 0x00000000
>Oct 25 01:16:42 [drm:intel_hpd_irq_handler [i915]] digital hpd port A - short
>Oct 25 01:16:42 [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port A - short
>Oct 25 01:16:42 [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 41 00 00 01 80 02 00 00 00 0f 0b 00
>Oct 25 01:16:43 [drm:drm_mode_addfb2 [drm]] [FB:110]
>Oct 25 01:16:43 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000de8150b9
>Oct 25 01:16:43 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 000000008682ac03 state to 00000000de8150b9
>Oct 25 01:16:43 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 000000002d6ddac4 state to 00000000de8150b9
>Oct 25 01:16:43 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:28:plane 1A] state 000000002d6ddac4
>Oct 25 01:16:43 [drm:drm_atomic_check_only [drm]] checking 00000000de8150b9
>Oct 25 01:16:43 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 110
>Oct 25 01:16:43 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:43 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45
>Oct 25 01:16:43 [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000de8150b9 nonblocking
>Oct 25 01:16:43 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:43 [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000063149474
>Oct 25 01:16:43 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000063149474
>Oct 25 01:16:43 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000de8150b9
>Oct 25 01:16:43 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000de8150b9
>Oct 25 01:16:43 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000063149474
>Oct 25 01:16:43 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000063149474
>Oct 25 01:16:43 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000063149474
>Oct 25 01:16:43 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000063149474
>Oct 25 01:16:43 [drm:drm_mode_addfb2 [drm]] [FB:113]
>Oct 25 01:16:43 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000935c3744
>Oct 25 01:16:43 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000229b8bc1 state to 00000000935c3744
>Oct 25 01:16:43 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 000000009784664f state to 00000000935c3744
>Oct 25 01:16:43 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:113] for [PLANE:28:plane 1A] state 000000009784664f
>Oct 25 01:16:43 [drm:drm_atomic_check_only [drm]] checking 00000000935c3744
>Oct 25 01:16:43 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 113
>Oct 25 01:16:43 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:43 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45
>Oct 25 01:16:43 [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000935c3744 nonblocking
>Oct 25 01:16:43 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:43 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000935c3744
>Oct 25 01:16:43 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000935c3744
>Oct 25 01:16:43 [drm:drm_mode_addfb2 [drm]] [FB:110]
>Oct 25 01:16:43 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000cfbb2c46
>Oct 25 01:16:43 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000dd20a85b state to 00000000cfbb2c46
>Oct 25 01:16:43 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000df007935 state to 00000000cfbb2c46
>Oct 25 01:16:43 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:28:plane 1A] state 00000000df007935
>Oct 25 01:16:43 [drm:drm_atomic_check_only [drm]] checking 00000000cfbb2c46
>Oct 25 01:16:43 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 110
>Oct 25 01:16:43 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:43 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45
>Oct 25 01:16:43 [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000cfbb2c46 nonblocking
>Oct 25 01:16:43 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:43 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000cfbb2c46
>Oct 25 01:16:43 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000cfbb2c46
>Oct 25 01:16:43 [drm:gen8_de_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x11101010, pins 0x00000010, long 0x00000000
>Oct 25 01:16:43 [drm:intel_hpd_irq_handler [i915]] digital hpd port A - short
>Oct 25 01:16:43 [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port A - short
>Oct 25 01:16:43 [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 41 00 00 01 80 02 00 00 00 0f 0b 00
>Oct 25 01:16:43 [drm:drm_mode_addfb2 [drm]] [FB:113]
>Oct 25 01:16:43 [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000002480bd06
>Oct 25 01:16:43 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000b7798c85 state to 000000002480bd06
>Oct 25 01:16:43 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 0000000037e40ab3 state to 000000002480bd06
>Oct 25 01:16:43 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:113] for [PLANE:28:plane 1A] state 0000000037e40ab3
>Oct 25 01:16:43 [drm:drm_atomic_check_only [drm]] checking 000000002480bd06
>Oct 25 01:16:43 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 113
>Oct 25 01:16:43 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:43 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45
>Oct 25 01:16:43 [drm:drm_atomic_nonblocking_commit [drm]] committing 000000002480bd06 nonblocking
>Oct 25 01:16:43 [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000009ee0b018
>Oct 25 01:16:43 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000009ee0b018
>Oct 25 01:16:43 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000009ee0b018
>Oct 25 01:16:43 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000009ee0b018
>Oct 25 01:16:43 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000009ee0b018
>Oct 25 01:16:43 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000009ee0b018
>Oct 25 01:16:43 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:43 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000002480bd06
>Oct 25 01:16:43 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000002480bd06
>Oct 25 01:16:44 [drm:gen8_de_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x11101010, pins 0x00000010, long 0x00000000
>Oct 25 01:16:44 [drm:intel_hpd_irq_handler [i915]] digital hpd port A - short
>Oct 25 01:16:44 [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port A - short
>Oct 25 01:16:44 [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 41 00 00 01 80 02 00 00 00 0f 0b 00
>Oct 25 01:16:44 [drm:drm_mode_addfb2 [drm]] [FB:110]
>Oct 25 01:16:44 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000ff023107
>Oct 25 01:16:44 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 0000000055e5b1c7 state to 00000000ff023107
>Oct 25 01:16:44 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 000000004bc529ab state to 00000000ff023107
>Oct 25 01:16:44 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:28:plane 1A] state 000000004bc529ab
>Oct 25 01:16:44 [drm:drm_atomic_check_only [drm]] checking 00000000ff023107
>Oct 25 01:16:44 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 110
>Oct 25 01:16:44 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:44 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45
>Oct 25 01:16:44 [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000ff023107 nonblocking
>Oct 25 01:16:44 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:44 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000ff023107
>Oct 25 01:16:44 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000ff023107
>Oct 25 01:16:44 [drm:gen8_de_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x11101010, pins 0x00000010, long 0x00000000
>Oct 25 01:16:44 [drm:intel_hpd_irq_handler [i915]] digital hpd port A - short
>Oct 25 01:16:44 [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port A - short
>Oct 25 01:16:44 [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 41 00 00 01 80 02 00 00 00 0f 0b 00
>Oct 25 01:16:44 [drm:drm_mode_addfb2 [drm]] [FB:113]
>Oct 25 01:16:44 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000ff023107
>Oct 25 01:16:44 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 000000001cc9f018 state to 00000000ff023107
>Oct 25 01:16:44 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000585a4343 state to 00000000ff023107
>Oct 25 01:16:44 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:113] for [PLANE:28:plane 1A] state 00000000585a4343
>Oct 25 01:16:44 [drm:drm_atomic_check_only [drm]] checking 00000000ff023107
>Oct 25 01:16:44 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 113
>Oct 25 01:16:44 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:44 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45
>Oct 25 01:16:44 [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000ff023107 nonblocking
>Oct 25 01:16:44 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:44 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000ff023107
>Oct 25 01:16:44 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000ff023107
>Oct 25 01:16:45 [drm:drm_mode_addfb2 [drm]] [FB:110]
>Oct 25 01:16:45 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000c92b4d9a
>Oct 25 01:16:45 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 000000000ab4b2fc state to 00000000c92b4d9a
>Oct 25 01:16:45 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 000000004bc529ab state to 00000000c92b4d9a
>Oct 25 01:16:45 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:28:plane 1A] state 000000004bc529ab
>Oct 25 01:16:45 [drm:drm_atomic_check_only [drm]] checking 00000000c92b4d9a
>Oct 25 01:16:45 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 110
>Oct 25 01:16:45 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:45 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45
>Oct 25 01:16:45 [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000c92b4d9a nonblocking
>Oct 25 01:16:45 [drm:gen8_de_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x11101010, pins 0x00000010, long 0x00000000
>Oct 25 01:16:45 [drm:intel_hpd_irq_handler [i915]] digital hpd port A - short
>Oct 25 01:16:45 [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port A - short
>Oct 25 01:16:45 [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 41 00 00 01 80 02 00 00 00 0f 0b 00
>Oct 25 01:16:45 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:45 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000c92b4d9a
>Oct 25 01:16:45 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000c92b4d9a
>Oct 25 01:16:45 [drm:gen8_de_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x11101010, pins 0x00000010, long 0x00000000
>Oct 25 01:16:45 [drm:intel_hpd_irq_handler [i915]] digital hpd port A - short
>Oct 25 01:16:45 [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port A - short
>Oct 25 01:16:45 [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 41 00 00 01 80 02 00 00 00 0f 0b 00
>Oct 25 01:16:45 [drm:drm_mode_addfb2 [drm]] [FB:113]
>Oct 25 01:16:45 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000e53e1ae0
>Oct 25 01:16:45 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000217e0795 state to 00000000e53e1ae0
>Oct 25 01:16:45 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000c843f5b3 state to 00000000e53e1ae0
>Oct 25 01:16:45 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:113] for [PLANE:28:plane 1A] state 00000000c843f5b3
>Oct 25 01:16:45 [drm:drm_atomic_check_only [drm]] checking 00000000e53e1ae0
>Oct 25 01:16:45 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 113
>Oct 25 01:16:45 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:45 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45
>Oct 25 01:16:45 [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000e53e1ae0 nonblocking
>Oct 25 01:16:45 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:45 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000e53e1ae0
>Oct 25 01:16:45 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000f1ecca12
>Oct 25 01:16:45 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000e53e1ae0
>Oct 25 01:16:45 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000f1ecca12
>Oct 25 01:16:45 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000f1ecca12
>Oct 25 01:16:45 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000f1ecca12
>Oct 25 01:16:45 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000f1ecca12
>Oct 25 01:16:45 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000f1ecca12
>Oct 25 01:16:45 [drm:gen8_de_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x11101010, pins 0x00000010, long 0x00000000
>Oct 25 01:16:45 [drm:intel_hpd_irq_handler [i915]] digital hpd port A - short
>Oct 25 01:16:45 [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port A - short
>Oct 25 01:16:45 [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 41 00 00 01 80 02 00 00 00 0f 0b 00
>Oct 25 01:16:46 [drm:drm_mode_addfb2 [drm]] [FB:110]
>Oct 25 01:16:46 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000f1ecca12
>Oct 25 01:16:46 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000888ce6dc state to 00000000f1ecca12
>Oct 25 01:16:46 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000df1d36b4 state to 00000000f1ecca12
>Oct 25 01:16:46 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:28:plane 1A] state 00000000df1d36b4
>Oct 25 01:16:46 [drm:drm_atomic_check_only [drm]] checking 00000000f1ecca12
>Oct 25 01:16:46 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 110
>Oct 25 01:16:46 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:46 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45
>Oct 25 01:16:46 [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000f1ecca12 nonblocking
>Oct 25 01:16:46 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000e53e1ae0
>Oct 25 01:16:46 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000e53e1ae0
>Oct 25 01:16:46 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000e53e1ae0
>Oct 25 01:16:46 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:46 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000f1ecca12
>Oct 25 01:16:46 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000f1ecca12
>Oct 25 01:16:46 [drm:gen8_de_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x11101010, pins 0x00000010, long 0x00000000
>Oct 25 01:16:46 [drm:intel_hpd_irq_handler [i915]] digital hpd port A - short
>Oct 25 01:16:46 [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port A - short
>Oct 25 01:16:46 [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 41 00 00 01 80 02 00 00 00 0f 0b 00
>Oct 25 01:16:46 [drm:drm_mode_addfb2 [drm]] [FB:113]
>Oct 25 01:16:46 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000884bfc9b
>Oct 25 01:16:46 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 0000000032e4e74b state to 00000000884bfc9b
>Oct 25 01:16:46 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000c559571b state to 00000000884bfc9b
>Oct 25 01:16:46 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:113] for [PLANE:28:plane 1A] state 00000000c559571b
>Oct 25 01:16:46 [drm:drm_atomic_check_only [drm]] checking 00000000884bfc9b
>Oct 25 01:16:46 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 113
>Oct 25 01:16:46 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:46 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45
>Oct 25 01:16:46 [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000884bfc9b nonblocking
>Oct 25 01:16:46 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:46 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000884bfc9b
>Oct 25 01:16:46 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000884bfc9b
>Oct 25 01:16:46 [drm:gen8_de_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x11101010, pins 0x00000010, long 0x00000000
>Oct 25 01:16:46 [drm:intel_hpd_irq_handler [i915]] digital hpd port A - short
>Oct 25 01:16:46 [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port A - short
>Oct 25 01:16:46 [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 41 00 00 01 80 02 00 00 00 0f 0b 00
>Oct 25 01:16:47 [drm:drm_mode_addfb2 [drm]] [FB:110]
>Oct 25 01:16:47 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000888ce6dc
>Oct 25 01:16:47 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000e53e1ae0 state to 00000000888ce6dc
>Oct 25 01:16:47 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000682e5d75 state to 00000000888ce6dc
>Oct 25 01:16:47 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:28:plane 1A] state 00000000682e5d75
>Oct 25 01:16:47 [drm:drm_atomic_check_only [drm]] checking 00000000888ce6dc
>Oct 25 01:16:47 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 110
>Oct 25 01:16:47 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:47 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45
>Oct 25 01:16:47 [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000888ce6dc nonblocking
>Oct 25 01:16:47 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:47 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000f1ecca12
>Oct 25 01:16:47 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000f1ecca12
>Oct 25 01:16:47 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000f1ecca12
>Oct 25 01:16:47 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000f1ecca12
>Oct 25 01:16:47 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000888ce6dc
>Oct 25 01:16:47 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000888ce6dc
>Oct 25 01:16:47 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000f1ecca12
>Oct 25 01:16:47 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000f1ecca12
>Oct 25 01:16:47 [drm:gen8_de_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x11101010, pins 0x00000010, long 0x00000000
>Oct 25 01:16:47 [drm:intel_hpd_irq_handler [i915]] digital hpd port A - short
>Oct 25 01:16:47 [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port A - short
>Oct 25 01:16:47 [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 41 00 00 01 80 02 00 00 00 0f 0b 00
>Oct 25 01:16:47 [drm:drm_mode_addfb2 [drm]] [FB:113]
>Oct 25 01:16:47 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000c7512c5c
>Oct 25 01:16:47 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000ce706e06 state to 00000000c7512c5c
>Oct 25 01:16:47 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000e437da1f state to 00000000c7512c5c
>Oct 25 01:16:47 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:113] for [PLANE:28:plane 1A] state 00000000e437da1f
>Oct 25 01:16:47 [drm:drm_atomic_check_only [drm]] checking 00000000c7512c5c
>Oct 25 01:16:47 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 113
>Oct 25 01:16:47 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:47 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45
>Oct 25 01:16:47 [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000c7512c5c nonblocking
>Oct 25 01:16:48 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:48 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000c7512c5c
>Oct 25 01:16:48 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000c7512c5c
>Oct 25 01:16:48 [drm:gen8_de_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x11101010, pins 0x00000010, long 0x00000000
>Oct 25 01:16:48 [drm:intel_hpd_irq_handler [i915]] digital hpd port A - short
>Oct 25 01:16:48 [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port A - short
>Oct 25 01:16:48 [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 41 00 00 01 80 02 00 00 00 0f 0b 00
>Oct 25 01:16:48 [drm:drm_mode_addfb2 [drm]] [FB:110]
>Oct 25 01:16:48 [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000000ab4b2fc
>Oct 25 01:16:48 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000c92b4d9a state to 000000000ab4b2fc
>Oct 25 01:16:48 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 0000000067fc7b92 state to 000000000ab4b2fc
>Oct 25 01:16:48 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:28:plane 1A] state 0000000067fc7b92
>Oct 25 01:16:48 [drm:drm_atomic_check_only [drm]] checking 000000000ab4b2fc
>Oct 25 01:16:48 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 110
>Oct 25 01:16:48 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:48 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45
>Oct 25 01:16:48 [drm:drm_atomic_nonblocking_commit [drm]] committing 000000000ab4b2fc nonblocking
>Oct 25 01:16:48 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:48 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000000ab4b2fc
>Oct 25 01:16:48 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000000ab4b2fc
>Oct 25 01:16:48 [drm:gen8_de_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x11101010, pins 0x00000010, long 0x00000000
>Oct 25 01:16:48 [drm:intel_hpd_irq_handler [i915]] digital hpd port A - short
>Oct 25 01:16:48 [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port A - short
>Oct 25 01:16:48 [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 41 00 00 01 80 02 00 00 00 0f 0b 00
>Oct 25 01:16:49 [drm:drm_mode_addfb2 [drm]] [FB:113]
>Oct 25 01:16:49 [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000001cc9f018
>Oct 25 01:16:49 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000ff023107 state to 000000001cc9f018
>Oct 25 01:16:49 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 000000006debb45b state to 000000001cc9f018
>Oct 25 01:16:49 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:113] for [PLANE:28:plane 1A] state 000000006debb45b
>Oct 25 01:16:49 [drm:drm_atomic_check_only [drm]] checking 000000001cc9f018
>Oct 25 01:16:49 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 113
>Oct 25 01:16:49 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:49 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45
>Oct 25 01:16:49 [drm:drm_atomic_nonblocking_commit [drm]] committing 000000001cc9f018 nonblocking
>Oct 25 01:16:49 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:49 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000001cc9f018
>Oct 25 01:16:49 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000001cc9f018
>Oct 25 01:16:49 [drm:gen8_de_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x11101010, pins 0x00000010, long 0x00000000
>Oct 25 01:16:49 [drm:intel_hpd_irq_handler [i915]] digital hpd port A - short
>Oct 25 01:16:49 [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port A - short
>Oct 25 01:16:49 [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 41 00 00 01 80 02 00 00 00 0f 0b 00
>Oct 25 01:16:49 [drm:drm_mode_addfb2 [drm]] [FB:110]
>Oct 25 01:16:49 [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000055e5b1c7
>Oct 25 01:16:49 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 000000001cc9f018 state to 0000000055e5b1c7
>Oct 25 01:16:49 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000ab49742b state to 0000000055e5b1c7
>Oct 25 01:16:49 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:28:plane 1A] state 00000000ab49742b
>Oct 25 01:16:49 [drm:drm_atomic_check_only [drm]] checking 0000000055e5b1c7
>Oct 25 01:16:49 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 110
>Oct 25 01:16:49 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:49 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45
>Oct 25 01:16:49 [drm:drm_atomic_nonblocking_commit [drm]] committing 0000000055e5b1c7 nonblocking
>Oct 25 01:16:49 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:49 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000055e5b1c7
>Oct 25 01:16:49 [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000053594abf
>Oct 25 01:16:49 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000055e5b1c7
>Oct 25 01:16:49 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000053594abf
>Oct 25 01:16:49 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000053594abf
>Oct 25 01:16:49 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000053594abf
>Oct 25 01:16:49 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000053594abf
>Oct 25 01:16:49 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000053594abf
>Oct 25 01:16:49 [drm:gen8_de_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x11101010, pins 0x00000010, long 0x00000000
>Oct 25 01:16:49 [drm:intel_hpd_irq_handler [i915]] digital hpd port A - short
>Oct 25 01:16:49 [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port A - short
>Oct 25 01:16:49 [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 41 00 00 01 80 02 00 00 00 0f 0b 00
>Oct 25 01:16:49 [drm:drm_mode_addfb2 [drm]] [FB:113]
>Oct 25 01:16:49 [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000053594abf
>Oct 25 01:16:49 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 0000000026e30fbc state to 0000000053594abf
>Oct 25 01:16:49 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 000000005a7abf26 state to 0000000053594abf
>Oct 25 01:16:49 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:113] for [PLANE:28:plane 1A] state 000000005a7abf26
>Oct 25 01:16:49 [drm:drm_atomic_check_only [drm]] checking 0000000053594abf
>Oct 25 01:16:49 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 113
>Oct 25 01:16:49 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:49 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45
>Oct 25 01:16:49 [drm:drm_atomic_nonblocking_commit [drm]] committing 0000000053594abf nonblocking
>Oct 25 01:16:49 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:49 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000053594abf
>Oct 25 01:16:49 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000053594abf
>Oct 25 01:16:50 [drm:gen8_de_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x11101010, pins 0x00000010, long 0x00000000
>Oct 25 01:16:50 [drm:intel_hpd_irq_handler [i915]] digital hpd port A - short
>Oct 25 01:16:50 [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port A - short
>Oct 25 01:16:50 [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 41 00 00 01 80 02 00 00 00 0f 0b 00
>Oct 25 01:16:50 [drm:drm_mode_addfb2 [drm]] [FB:110]
>Oct 25 01:16:50 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000a930749a
>Oct 25 01:16:50 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 0000000005e33b12 state to 00000000a930749a
>Oct 25 01:16:50 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000fec068a9 state to 00000000a930749a
>Oct 25 01:16:50 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:28:plane 1A] state 00000000fec068a9
>Oct 25 01:16:50 [drm:drm_atomic_check_only [drm]] checking 00000000a930749a
>Oct 25 01:16:50 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 110
>Oct 25 01:16:50 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:50 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45
>Oct 25 01:16:50 [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000a930749a nonblocking
>Oct 25 01:16:50 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:50 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000a930749a
>Oct 25 01:16:50 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000a930749a
>Oct 25 01:16:50 [drm:drm_mode_addfb2 [drm]] [FB:113]
>Oct 25 01:16:50 [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000062f8df16
>Oct 25 01:16:50 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000a036df3f state to 0000000062f8df16
>Oct 25 01:16:50 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000238a9ec7 state to 0000000062f8df16
>Oct 25 01:16:50 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:113] for [PLANE:28:plane 1A] state 00000000238a9ec7
>Oct 25 01:16:50 [drm:drm_atomic_check_only [drm]] checking 0000000062f8df16
>Oct 25 01:16:50 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 113
>Oct 25 01:16:50 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:50 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45
>Oct 25 01:16:50 [drm:drm_atomic_nonblocking_commit [drm]] committing 0000000062f8df16 nonblocking
>Oct 25 01:16:50 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:50 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000062f8df16
>Oct 25 01:16:50 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000062f8df16
>Oct 25 01:16:50 [drm:gen8_de_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x11101010, pins 0x00000010, long 0x00000000
>Oct 25 01:16:50 [drm:intel_hpd_irq_handler [i915]] digital hpd port A - short
>Oct 25 01:16:50 [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port A - short
>Oct 25 01:16:50 [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 41 00 00 01 80 02 00 00 00 0f 0b 00
>Oct 25 01:16:51 [drm:drm_mode_addfb2 [drm]] [FB:110]
>Oct 25 01:16:51 [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000001c5aa71e
>Oct 25 01:16:51 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 000000002199d420 state to 000000001c5aa71e
>Oct 25 01:16:51 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000c32487fe state to 000000001c5aa71e
>Oct 25 01:16:51 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:28:plane 1A] state 00000000c32487fe
>Oct 25 01:16:51 [drm:drm_atomic_check_only [drm]] checking 000000001c5aa71e
>Oct 25 01:16:51 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 110
>Oct 25 01:16:51 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:51 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45
>Oct 25 01:16:51 [drm:drm_atomic_nonblocking_commit [drm]] committing 000000001c5aa71e nonblocking
>Oct 25 01:16:51 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:51 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000f58b00ef
>Oct 25 01:16:51 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000001c5aa71e
>Oct 25 01:16:51 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000001c5aa71e
>Oct 25 01:16:51 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000f58b00ef
>Oct 25 01:16:51 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000f58b00ef
>Oct 25 01:16:51 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000f58b00ef
>Oct 25 01:16:51 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000f58b00ef
>Oct 25 01:16:51 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000f58b00ef
>Oct 25 01:16:51 [drm:drm_mode_addfb2 [drm]] [FB:113]
>Oct 25 01:16:51 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000f58b00ef
>Oct 25 01:16:51 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 000000001c5aa71e state to 00000000f58b00ef
>Oct 25 01:16:51 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000163b82bd state to 00000000f58b00ef
>Oct 25 01:16:51 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:113] for [PLANE:28:plane 1A] state 00000000163b82bd
>Oct 25 01:16:51 [drm:drm_atomic_check_only [drm]] checking 00000000f58b00ef
>Oct 25 01:16:51 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 113
>Oct 25 01:16:51 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:51 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45
>Oct 25 01:16:51 [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000f58b00ef nonblocking
>Oct 25 01:16:51 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:51 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000f58b00ef
>Oct 25 01:16:51 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000f58b00ef
>Oct 25 01:16:51 [drm:drm_mode_addfb2 [drm]] [FB:110]
>Oct 25 01:16:51 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000a036df3f
>Oct 25 01:16:51 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 0000000062f8df16 state to 00000000a036df3f
>Oct 25 01:16:51 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000cad9a501 state to 00000000a036df3f
>Oct 25 01:16:51 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:28:plane 1A] state 00000000cad9a501
>Oct 25 01:16:51 [drm:drm_atomic_check_only [drm]] checking 00000000a036df3f
>Oct 25 01:16:51 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 110
>Oct 25 01:16:51 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:51 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45
>Oct 25 01:16:51 [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000a036df3f nonblocking
>Oct 25 01:16:51 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:51 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000a036df3f
>Oct 25 01:16:51 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000a036df3f
>Oct 25 01:16:51 [drm:gen8_de_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x11101010, pins 0x00000010, long 0x00000000
>Oct 25 01:16:51 [drm:intel_hpd_irq_handler [i915]] digital hpd port A - short
>Oct 25 01:16:51 [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port A - short
>Oct 25 01:16:51 [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 41 00 00 01 80 02 00 00 00 0f 0b 00
>Oct 25 01:16:51 [drm:drm_mode_addfb2 [drm]] [FB:113]
>Oct 25 01:16:51 [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000005e33b12
>Oct 25 01:16:51 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000a930749a state to 0000000005e33b12
>Oct 25 01:16:51 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 0000000070e374a7 state to 0000000005e33b12
>Oct 25 01:16:51 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:113] for [PLANE:28:plane 1A] state 0000000070e374a7
>Oct 25 01:16:51 [drm:drm_atomic_check_only [drm]] checking 0000000005e33b12
>Oct 25 01:16:51 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 113
>Oct 25 01:16:51 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:51 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45
>Oct 25 01:16:51 [drm:drm_atomic_nonblocking_commit [drm]] committing 0000000005e33b12 nonblocking
>Oct 25 01:16:51 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:51 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000005e33b12
>Oct 25 01:16:51 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000005e33b12
>Oct 25 01:16:51 [drm:gen8_de_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x11101010, pins 0x00000010, long 0x00000000
>Oct 25 01:16:51 [drm:intel_hpd_irq_handler [i915]] digital hpd port A - short
>Oct 25 01:16:51 [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port A - short
>Oct 25 01:16:51 [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 41 00 00 01 80 02 00 00 00 0f 0b 00
>Oct 25 01:16:51 [drm:drm_mode_addfb2 [drm]] [FB:110]
>Oct 25 01:16:51 [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000009ee0b018
>Oct 25 01:16:51 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 000000008a7d870b state to 000000009ee0b018
>Oct 25 01:16:51 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000c1050601 state to 000000009ee0b018
>Oct 25 01:16:51 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:28:plane 1A] state 00000000c1050601
>Oct 25 01:16:51 [drm:drm_atomic_check_only [drm]] checking 000000009ee0b018
>Oct 25 01:16:51 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 110
>Oct 25 01:16:51 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:51 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45
>Oct 25 01:16:51 [drm:drm_atomic_nonblocking_commit [drm]] committing 000000009ee0b018 nonblocking
>Oct 25 01:16:51 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:51 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000009ee0b018
>Oct 25 01:16:51 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000009ee0b018
>Oct 25 01:16:52 [drm:drm_mode_addfb2 [drm]] [FB:113]
>Oct 25 01:16:52 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000ce706e06
>Oct 25 01:16:52 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 000000006ef87567 state to 00000000ce706e06
>Oct 25 01:16:52 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 000000000737cf9a state to 00000000ce706e06
>Oct 25 01:16:52 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:113] for [PLANE:28:plane 1A] state 000000000737cf9a
>Oct 25 01:16:52 [drm:drm_atomic_check_only [drm]] checking 00000000ce706e06
>Oct 25 01:16:52 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 113
>Oct 25 01:16:52 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:52 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45
>Oct 25 01:16:52 [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000ce706e06 nonblocking
>Oct 25 01:16:52 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:52 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000ce706e06
>Oct 25 01:16:52 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000ce706e06
>Oct 25 01:16:52 [drm:gen8_de_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x11101010, pins 0x00000010, long 0x00000000
>Oct 25 01:16:52 [drm:intel_hpd_irq_handler [i915]] digital hpd port A - short
>Oct 25 01:16:52 [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port A - short
>Oct 25 01:16:52 [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 41 00 00 01 80 02 00 00 00 0f 0b 00
>Oct 25 01:16:52 [drm:drm_mode_addfb2 [drm]] [FB:110]
>Oct 25 01:16:52 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000834703a2
>Oct 25 01:16:52 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000b019f1b8 state to 00000000834703a2
>Oct 25 01:16:52 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 000000008b044653 state to 00000000834703a2
>Oct 25 01:16:52 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:28:plane 1A] state 000000008b044653
>Oct 25 01:16:52 [drm:drm_atomic_check_only [drm]] checking 00000000834703a2
>Oct 25 01:16:52 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 110
>Oct 25 01:16:52 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:52 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45
>Oct 25 01:16:52 [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000834703a2 nonblocking
>Oct 25 01:16:52 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:52 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000de382fed
>Oct 25 01:16:52 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000de382fed
>Oct 25 01:16:52 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000de382fed
>Oct 25 01:16:52 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000de382fed
>Oct 25 01:16:52 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000834703a2
>Oct 25 01:16:52 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000834703a2
>Oct 25 01:16:52 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000de382fed
>Oct 25 01:16:52 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000de382fed
>Oct 25 01:16:52 [drm:drm_mode_addfb2 [drm]] [FB:113]
>Oct 25 01:16:52 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000028f3b9f
>Oct 25 01:16:52 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000fc7c8f0d state to 00000000028f3b9f
>Oct 25 01:16:52 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 0000000071f797e0 state to 00000000028f3b9f
>Oct 25 01:16:52 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:113] for [PLANE:28:plane 1A] state 0000000071f797e0
>Oct 25 01:16:52 [drm:drm_atomic_check_only [drm]] checking 00000000028f3b9f
>Oct 25 01:16:52 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 113
>Oct 25 01:16:52 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:52 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45
>Oct 25 01:16:52 [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000028f3b9f nonblocking
>Oct 25 01:16:52 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:52 [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000046d61892
>Oct 25 01:16:52 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000046d61892
>Oct 25 01:16:52 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000046d61892
>Oct 25 01:16:52 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000028f3b9f
>Oct 25 01:16:52 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000028f3b9f
>Oct 25 01:16:52 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000046d61892
>Oct 25 01:16:52 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000046d61892
>Oct 25 01:16:52 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000046d61892
>Oct 25 01:16:52 [drm:drm_mode_addfb2 [drm]] [FB:110]
>Oct 25 01:16:52 [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000046d61892
>Oct 25 01:16:52 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 0000000071a48533 state to 0000000046d61892
>Oct 25 01:16:52 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 0000000071120d97 state to 0000000046d61892
>Oct 25 01:16:52 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:28:plane 1A] state 0000000071120d97
>Oct 25 01:16:52 [drm:drm_atomic_check_only [drm]] checking 0000000046d61892
>Oct 25 01:16:52 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 110
>Oct 25 01:16:52 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:52 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45
>Oct 25 01:16:52 [drm:drm_atomic_nonblocking_commit [drm]] committing 0000000046d61892 nonblocking
>Oct 25 01:16:52 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:52 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000fedc4d48
>Oct 25 01:16:52 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000fedc4d48
>Oct 25 01:16:52 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000fedc4d48
>Oct 25 01:16:52 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000046d61892
>Oct 25 01:16:52 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000046d61892
>Oct 25 01:16:52 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000fedc4d48
>Oct 25 01:16:52 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000fedc4d48
>Oct 25 01:16:52 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000fedc4d48
>Oct 25 01:16:52 [drm:gen8_de_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x11101010, pins 0x00000010, long 0x00000000
>Oct 25 01:16:52 [drm:intel_hpd_irq_handler [i915]] digital hpd port A - short
>Oct 25 01:16:52 [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port A - short
>Oct 25 01:16:52 [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 41 00 00 01 80 02 00 00 00 0f 0b 00
>Oct 25 01:16:53 [drm:drm_mode_addfb2 [drm]] [FB:113]
>Oct 25 01:16:53 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000fedc4d48
>Oct 25 01:16:53 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 0000000019a0f0fa state to 00000000fedc4d48
>Oct 25 01:16:53 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000d5584283 state to 00000000fedc4d48
>Oct 25 01:16:53 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:113] for [PLANE:28:plane 1A] state 00000000d5584283
>Oct 25 01:16:53 [drm:drm_atomic_check_only [drm]] checking 00000000fedc4d48
>Oct 25 01:16:53 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 113
>Oct 25 01:16:53 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:53 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45
>Oct 25 01:16:53 [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000fedc4d48 nonblocking
>Oct 25 01:16:53 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:53 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000f6431e01
>Oct 25 01:16:53 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000fedc4d48
>Oct 25 01:16:53 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000fedc4d48
>Oct 25 01:16:53 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000f6431e01
>Oct 25 01:16:53 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000f6431e01
>Oct 25 01:16:53 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000f6431e01
>Oct 25 01:16:53 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000f6431e01
>Oct 25 01:16:53 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000f6431e01
>Oct 25 01:16:53 [drm:drm_mode_addfb2 [drm]] [FB:110]
>Oct 25 01:16:53 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000f6431e01
>Oct 25 01:16:53 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 000000001dd69e2b state to 00000000f6431e01
>Oct 25 01:16:53 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 000000002e59751f state to 00000000f6431e01
>Oct 25 01:16:53 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:28:plane 1A] state 000000002e59751f
>Oct 25 01:16:53 [drm:drm_atomic_check_only [drm]] checking 00000000f6431e01
>Oct 25 01:16:53 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 110
>Oct 25 01:16:53 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:53 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45
>Oct 25 01:16:53 [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000f6431e01 nonblocking
>Oct 25 01:16:53 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:53 [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000024d78c82
>Oct 25 01:16:53 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000024d78c82
>Oct 25 01:16:53 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000f6431e01
>Oct 25 01:16:53 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000f6431e01
>Oct 25 01:16:53 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000024d78c82
>Oct 25 01:16:53 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000024d78c82
>Oct 25 01:16:53 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000024d78c82
>Oct 25 01:16:53 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000024d78c82
>Oct 25 01:16:53 [drm:gen8_de_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x11101010, pins 0x00000010, long 0x00000000
>Oct 25 01:16:53 [drm:intel_hpd_irq_handler [i915]] digital hpd port A - short
>Oct 25 01:16:53 [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port A - short
>Oct 25 01:16:53 [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 41 00 00 01 80 02 00 00 00 0f 0b 00
>Oct 25 01:16:53 [drm:drm_mode_addfb2 [drm]] [FB:113]
>Oct 25 01:16:53 [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000024d78c82
>Oct 25 01:16:53 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 000000000f733a4b state to 0000000024d78c82
>Oct 25 01:16:53 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000167f5c94 state to 0000000024d78c82
>Oct 25 01:16:53 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:113] for [PLANE:28:plane 1A] state 00000000167f5c94
>Oct 25 01:16:53 [drm:drm_atomic_check_only [drm]] checking 0000000024d78c82
>Oct 25 01:16:53 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 113
>Oct 25 01:16:53 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:53 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45
>Oct 25 01:16:53 [drm:drm_atomic_nonblocking_commit [drm]] committing 0000000024d78c82 nonblocking
>Oct 25 01:16:53 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:53 [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000007932c056
>Oct 25 01:16:53 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000007932c056
>Oct 25 01:16:53 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000024d78c82
>Oct 25 01:16:53 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000024d78c82
>Oct 25 01:16:53 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000007932c056
>Oct 25 01:16:53 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000007932c056
>Oct 25 01:16:53 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000007932c056
>Oct 25 01:16:53 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000007932c056
>Oct 25 01:16:53 [drm:drm_mode_addfb2 [drm]] [FB:110]
>Oct 25 01:16:53 [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000007932c056
>Oct 25 01:16:53 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000f5d086ba state to 000000007932c056
>Oct 25 01:16:53 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 000000009d810c73 state to 000000007932c056
>Oct 25 01:16:53 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:28:plane 1A] state 000000009d810c73
>Oct 25 01:16:53 [drm:drm_atomic_check_only [drm]] checking 000000007932c056
>Oct 25 01:16:53 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 110
>Oct 25 01:16:53 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:53 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45
>Oct 25 01:16:53 [drm:drm_atomic_nonblocking_commit [drm]] committing 000000007932c056 nonblocking
>Oct 25 01:16:53 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:53 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000dddead2e
>Oct 25 01:16:53 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000dddead2e
>Oct 25 01:16:53 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000007932c056
>Oct 25 01:16:53 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000007932c056
>Oct 25 01:16:53 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000dddead2e
>Oct 25 01:16:53 [drm:gen8_de_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x11101010, pins 0x00000010, long 0x00000000
>Oct 25 01:16:53 [drm:intel_hpd_irq_handler [i915]] digital hpd port A - short
>Oct 25 01:16:53 [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port A - short
>Oct 25 01:16:53 [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 41 00 00 01 80 02 00 00 00 0f 0b 00
>Oct 25 01:16:53 [drm:drm_mode_addfb2 [drm]] [FB:113]
>Oct 25 01:16:53 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000dddead2e
>Oct 25 01:16:53 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000ba416ab1 state to 00000000dddead2e
>Oct 25 01:16:53 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 000000009dfceb0c state to 00000000dddead2e
>Oct 25 01:16:53 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:113] for [PLANE:28:plane 1A] state 000000009dfceb0c
>Oct 25 01:16:53 [drm:drm_atomic_check_only [drm]] checking 00000000dddead2e
>Oct 25 01:16:53 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 113
>Oct 25 01:16:53 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:53 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45
>Oct 25 01:16:53 [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000dddead2e nonblocking
>Oct 25 01:16:53 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:53 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000dddead2e
>Oct 25 01:16:53 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000dddead2e
>Oct 25 01:16:54 [drm:drm_mode_addfb2 [drm]] [FB:110]
>Oct 25 01:16:54 [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000009e1f3756
>Oct 25 01:16:54 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000f93b029f state to 000000009e1f3756
>Oct 25 01:16:54 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000d026dd96 state to 000000009e1f3756
>Oct 25 01:16:54 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:28:plane 1A] state 00000000d026dd96
>Oct 25 01:16:54 [drm:drm_atomic_check_only [drm]] checking 000000009e1f3756
>Oct 25 01:16:54 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 110
>Oct 25 01:16:54 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:54 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45
>Oct 25 01:16:54 [drm:drm_atomic_nonblocking_commit [drm]] committing 000000009e1f3756 nonblocking
>Oct 25 01:16:54 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:54 [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000059386f6f
>Oct 25 01:16:54 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000059386f6f
>Oct 25 01:16:54 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000059386f6f
>Oct 25 01:16:54 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000059386f6f
>Oct 25 01:16:54 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000009e1f3756
>Oct 25 01:16:54 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000009e1f3756
>Oct 25 01:16:54 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000059386f6f
>Oct 25 01:16:54 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000059386f6f
>Oct 25 01:16:54 [drm:gen8_de_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x11101010, pins 0x00000010, long 0x00000000
>Oct 25 01:16:54 [drm:intel_hpd_irq_handler [i915]] digital hpd port A - short
>Oct 25 01:16:54 [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port A - short
>Oct 25 01:16:54 [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 41 00 00 01 80 02 00 00 00 0f 0b 00
>Oct 25 01:16:54 [drm:drm_mode_addfb2 [drm]] [FB:113]
>Oct 25 01:16:54 [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000026e30fbc
>Oct 25 01:16:54 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 0000000053594abf state to 0000000026e30fbc
>Oct 25 01:16:54 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000727717c7 state to 0000000026e30fbc
>Oct 25 01:16:54 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:113] for [PLANE:28:plane 1A] state 00000000727717c7
>Oct 25 01:16:54 [drm:drm_atomic_check_only [drm]] checking 0000000026e30fbc
>Oct 25 01:16:54 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 113
>Oct 25 01:16:54 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:54 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45
>Oct 25 01:16:54 [drm:drm_atomic_nonblocking_commit [drm]] committing 0000000026e30fbc nonblocking
>Oct 25 01:16:54 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:54 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000981adb63
>Oct 25 01:16:54 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000026e30fbc
>Oct 25 01:16:54 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000026e30fbc
>Oct 25 01:16:54 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000981adb63
>Oct 25 01:16:54 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000981adb63
>Oct 25 01:16:54 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000981adb63
>Oct 25 01:16:54 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000981adb63
>Oct 25 01:16:54 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000981adb63
>Oct 25 01:16:54 [drm:gen8_de_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x11101010, pins 0x00000010, long 0x00000000
>Oct 25 01:16:54 [drm:intel_hpd_irq_handler [i915]] digital hpd port A - short
>Oct 25 01:16:54 [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port A - short
>Oct 25 01:16:54 [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 41 00 00 01 80 02 00 00 00 0f 0b 00
>Oct 25 01:16:55 [drm:drm_mode_addfb2 [drm]] [FB:110]
>Oct 25 01:16:55 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000a7a225a5
>Oct 25 01:16:55 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000f8616964 state to 00000000a7a225a5
>Oct 25 01:16:55 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000c1050601 state to 00000000a7a225a5
>Oct 25 01:16:55 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:28:plane 1A] state 00000000c1050601
>Oct 25 01:16:55 [drm:drm_atomic_check_only [drm]] checking 00000000a7a225a5
>Oct 25 01:16:55 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 110
>Oct 25 01:16:55 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:55 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45
>Oct 25 01:16:55 [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000a7a225a5 nonblocking
>Oct 25 01:16:55 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:55 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000f1ecca12
>Oct 25 01:16:55 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000a7a225a5
>Oct 25 01:16:55 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000a7a225a5
>Oct 25 01:16:55 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000f1ecca12
>Oct 25 01:16:55 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000f1ecca12
>Oct 25 01:16:55 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000f1ecca12
>Oct 25 01:16:55 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000f1ecca12
>Oct 25 01:16:55 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000f1ecca12
>Oct 25 01:16:55 [drm:drm_mode_addfb2 [drm]] [FB:113]
>Oct 25 01:16:55 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000eb32d938
>Oct 25 01:16:55 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000dd20a85b state to 00000000eb32d938
>Oct 25 01:16:55 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 0000000068cc55bf state to 00000000eb32d938
>Oct 25 01:16:55 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:113] for [PLANE:28:plane 1A] state 0000000068cc55bf
>Oct 25 01:16:55 [drm:drm_atomic_check_only [drm]] checking 00000000eb32d938
>Oct 25 01:16:55 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 113
>Oct 25 01:16:55 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:55 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45
>Oct 25 01:16:55 [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000eb32d938 nonblocking
>Oct 25 01:16:55 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:55 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000cfbb2c46
>Oct 25 01:16:55 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000cfbb2c46
>Oct 25 01:16:55 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000cfbb2c46
>Oct 25 01:16:55 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000eb32d938
>Oct 25 01:16:55 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000eb32d938
>Oct 25 01:16:55 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000cfbb2c46
>Oct 25 01:16:55 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000cfbb2c46
>Oct 25 01:16:55 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000cfbb2c46
>Oct 25 01:16:55 [drm:gen8_de_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x11101010, pins 0x00000010, long 0x00000000
>Oct 25 01:16:55 [drm:intel_hpd_irq_handler [i915]] digital hpd port A - short
>Oct 25 01:16:55 [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port A - short
>Oct 25 01:16:55 [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 41 00 00 01 80 02 00 00 00 0f 0b 00
>Oct 25 01:16:55 [drm:drm_mode_addfb2 [drm]] [FB:110]
>Oct 25 01:16:55 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000cfbb2c46
>Oct 25 01:16:55 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000229b8bc1 state to 00000000cfbb2c46
>Oct 25 01:16:55 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000389eb8c9 state to 00000000cfbb2c46
>Oct 25 01:16:55 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:28:plane 1A] state 00000000389eb8c9
>Oct 25 01:16:55 [drm:drm_atomic_check_only [drm]] checking 00000000cfbb2c46
>Oct 25 01:16:55 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 110
>Oct 25 01:16:55 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:55 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45
>Oct 25 01:16:55 [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000cfbb2c46 nonblocking
>Oct 25 01:16:55 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:55 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000cfbb2c46
>Oct 25 01:16:55 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000cfbb2c46
>Oct 25 01:16:55 [drm:drm_mode_addfb2 [drm]] [FB:113]
>Oct 25 01:16:55 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000f8616964
>Oct 25 01:16:55 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000a7a225a5 state to 00000000f8616964
>Oct 25 01:16:55 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000f87b65b5 state to 00000000f8616964
>Oct 25 01:16:55 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:113] for [PLANE:28:plane 1A] state 00000000f87b65b5
>Oct 25 01:16:55 [drm:drm_atomic_check_only [drm]] checking 00000000f8616964
>Oct 25 01:16:55 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 113
>Oct 25 01:16:55 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:55 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45
>Oct 25 01:16:55 [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000f8616964 nonblocking
>Oct 25 01:16:55 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:55 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000f8616964
>Oct 25 01:16:55 [drm:drm_atomic_state_init [drm]] Allocated atomic state 000000008a7d870b
>Oct 25 01:16:55 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000f8616964
>Oct 25 01:16:55 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000008a7d870b
>Oct 25 01:16:55 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000008a7d870b
>Oct 25 01:16:55 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000008a7d870b
>Oct 25 01:16:55 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 000000008a7d870b
>Oct 25 01:16:55 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 000000008a7d870b
>Oct 25 01:16:55 [drm:drm_mode_addfb2 [drm]] [FB:110]
>Oct 25 01:16:55 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000935c3744
>Oct 25 01:16:55 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000229b8bc1 state to 00000000935c3744
>Oct 25 01:16:55 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000345477f7 state to 00000000935c3744
>Oct 25 01:16:55 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:28:plane 1A] state 00000000345477f7
>Oct 25 01:16:55 [drm:drm_atomic_check_only [drm]] checking 00000000935c3744
>Oct 25 01:16:55 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 110
>Oct 25 01:16:55 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:55 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45
>Oct 25 01:16:55 [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000935c3744 nonblocking
>Oct 25 01:16:55 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:55 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000cfbb2c46
>Oct 25 01:16:55 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000cfbb2c46
>Oct 25 01:16:55 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000935c3744
>Oct 25 01:16:55 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000935c3744
>Oct 25 01:16:55 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000cfbb2c46
>Oct 25 01:16:55 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000cfbb2c46
>Oct 25 01:16:55 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000cfbb2c46
>Oct 25 01:16:55 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000cfbb2c46
>Oct 25 01:16:55 [drm:drm_mode_addfb2 [drm]] [FB:113]
>Oct 25 01:16:55 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000cfbb2c46
>Oct 25 01:16:55 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000dd20a85b state to 00000000cfbb2c46
>Oct 25 01:16:55 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000f3729a32 state to 00000000cfbb2c46
>Oct 25 01:16:55 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:113] for [PLANE:28:plane 1A] state 00000000f3729a32
>Oct 25 01:16:55 [drm:drm_atomic_check_only [drm]] checking 00000000cfbb2c46
>Oct 25 01:16:55 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 113
>Oct 25 01:16:55 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:55 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45
>Oct 25 01:16:55 [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000cfbb2c46 nonblocking
>Oct 25 01:16:55 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:55 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000eb32d938
>Oct 25 01:16:55 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000eb32d938
>Oct 25 01:16:55 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000cfbb2c46
>Oct 25 01:16:55 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000cfbb2c46
>Oct 25 01:16:55 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000eb32d938
>Oct 25 01:16:55 [drm:gen8_de_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x11101010, pins 0x00000010, long 0x00000000
>Oct 25 01:16:55 [drm:intel_hpd_irq_handler [i915]] digital hpd port A - short
>Oct 25 01:16:55 [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port A - short
>Oct 25 01:16:55 [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 41 00 00 01 80 02 00 00 00 0f 0b 00
>Oct 25 01:16:55 [drm:drm_mode_addfb2 [drm]] [FB:110]
>Oct 25 01:16:55 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000eb32d938
>Oct 25 01:16:55 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 0000000073b43f1a state to 00000000eb32d938
>Oct 25 01:16:55 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000f848c836 state to 00000000eb32d938
>Oct 25 01:16:55 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:28:plane 1A] state 00000000f848c836
>Oct 25 01:16:55 [drm:drm_atomic_check_only [drm]] checking 00000000eb32d938
>Oct 25 01:16:55 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 110
>Oct 25 01:16:55 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:55 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45
>Oct 25 01:16:55 [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000eb32d938 nonblocking
>Oct 25 01:16:56 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:56 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000eb32d938
>Oct 25 01:16:56 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000eb32d938
>Oct 25 01:16:56 [drm:drm_mode_addfb2 [drm]] [FB:113]
>Oct 25 01:16:56 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000eb32d938
>Oct 25 01:16:56 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000dd20a85b state to 00000000eb32d938
>Oct 25 01:16:56 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000f3729a32 state to 00000000eb32d938
>Oct 25 01:16:56 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:113] for [PLANE:28:plane 1A] state 00000000f3729a32
>Oct 25 01:16:56 [drm:drm_atomic_check_only [drm]] checking 00000000eb32d938
>Oct 25 01:16:56 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 113
>Oct 25 01:16:56 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:56 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45
>Oct 25 01:16:56 [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000eb32d938 nonblocking
>Oct 25 01:16:56 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:56 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000eb32d938
>Oct 25 01:16:56 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000eb32d938
>Oct 25 01:16:56 [drm:drm_mode_addfb2 [drm]] [FB:110]
>Oct 25 01:16:56 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000cfbb2c46
>Oct 25 01:16:56 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000229b8bc1 state to 00000000cfbb2c46
>Oct 25 01:16:56 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000345477f7 state to 00000000cfbb2c46
>Oct 25 01:16:56 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:28:plane 1A] state 00000000345477f7
>Oct 25 01:16:56 [drm:drm_atomic_check_only [drm]] checking 00000000cfbb2c46
>Oct 25 01:16:56 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 110
>Oct 25 01:16:56 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:56 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45
>Oct 25 01:16:56 [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000cfbb2c46 nonblocking
>Oct 25 01:16:56 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000935c3744
>Oct 25 01:16:56 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000935c3744
>Oct 25 01:16:56 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000935c3744
>Oct 25 01:16:56 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000935c3744
>Oct 25 01:16:56 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000935c3744
>Oct 25 01:16:56 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000935c3744
>Oct 25 01:16:56 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:56 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000cfbb2c46
>Oct 25 01:16:56 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000cfbb2c46
>Oct 25 01:16:56 [drm:drm_mode_addfb2 [drm]] [FB:113]
>Oct 25 01:16:56 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000935c3744
>Oct 25 01:16:56 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000cfbb2c46 state to 00000000935c3744
>Oct 25 01:16:56 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000389eb8c9 state to 00000000935c3744
>Oct 25 01:16:56 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:113] for [PLANE:28:plane 1A] state 00000000389eb8c9
>Oct 25 01:16:56 [drm:drm_atomic_check_only [drm]] checking 00000000935c3744
>Oct 25 01:16:56 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 113
>Oct 25 01:16:56 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:56 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45
>Oct 25 01:16:56 [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000935c3744 nonblocking
>Oct 25 01:16:56 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:56 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000935c3744
>Oct 25 01:16:56 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000dd20a85b
>Oct 25 01:16:56 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000935c3744
>Oct 25 01:16:56 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000dd20a85b
>Oct 25 01:16:56 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000dd20a85b
>Oct 25 01:16:56 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000dd20a85b
>Oct 25 01:16:56 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000dd20a85b
>Oct 25 01:16:56 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000dd20a85b
>Oct 25 01:16:56 [drm:drm_mode_addfb2 [drm]] [FB:110]
>Oct 25 01:16:56 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000dd20a85b
>Oct 25 01:16:56 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000eb32d938 state to 00000000dd20a85b
>Oct 25 01:16:56 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 0000000068cc55bf state to 00000000dd20a85b
>Oct 25 01:16:56 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:28:plane 1A] state 0000000068cc55bf
>Oct 25 01:16:56 [drm:drm_atomic_check_only [drm]] checking 00000000dd20a85b
>Oct 25 01:16:56 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 110
>Oct 25 01:16:56 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:56 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45
>Oct 25 01:16:56 [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000dd20a85b nonblocking
>Oct 25 01:16:56 [drm:gen8_de_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x11101010, pins 0x00000010, long 0x00000000
>Oct 25 01:16:56 [drm:intel_hpd_irq_handler [i915]] digital hpd port A - short
>Oct 25 01:16:56 [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port A - short
>Oct 25 01:16:56 [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 41 00 00 01 80 02 00 00 00 0f 0b 00
>Oct 25 01:16:56 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:56 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000dd20a85b
>Oct 25 01:16:56 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000dd20a85b
>Oct 25 01:16:56 [drm:gen8_de_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x11101010, pins 0x00000010, long 0x00000000
>Oct 25 01:16:56 [drm:intel_hpd_irq_handler [i915]] digital hpd port A - short
>Oct 25 01:16:56 [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port A - short
>Oct 25 01:16:56 [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 41 00 00 01 80 02 00 00 00 0f 0b 00
>Oct 25 01:16:57 [drm:drm_mode_addfb2 [drm]] [FB:113]
>Oct 25 01:16:57 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000935c3744
>Oct 25 01:16:57 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000229b8bc1 state to 00000000935c3744
>Oct 25 01:16:57 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 000000009d89b46f state to 00000000935c3744
>Oct 25 01:16:57 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:113] for [PLANE:28:plane 1A] state 000000009d89b46f
>Oct 25 01:16:57 [drm:drm_atomic_check_only [drm]] checking 00000000935c3744
>Oct 25 01:16:57 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 113
>Oct 25 01:16:57 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:57 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45
>Oct 25 01:16:57 [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000935c3744 nonblocking
>Oct 25 01:16:57 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:57 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000dd20a85b
>Oct 25 01:16:57 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000935c3744
>Oct 25 01:16:57 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000935c3744
>Oct 25 01:16:57 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000dd20a85b
>Oct 25 01:16:57 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000dd20a85b
>Oct 25 01:16:57 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000dd20a85b
>Oct 25 01:16:57 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000dd20a85b
>Oct 25 01:16:57 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000dd20a85b
>Oct 25 01:16:57 [drm:drm_mode_addfb2 [drm]] [FB:110]
>Oct 25 01:16:57 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000dd20a85b
>Oct 25 01:16:57 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000cfbb2c46 state to 00000000dd20a85b
>Oct 25 01:16:57 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 0000000041b02316 state to 00000000dd20a85b
>Oct 25 01:16:57 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:28:plane 1A] state 0000000041b02316
>Oct 25 01:16:57 [drm:drm_atomic_check_only [drm]] checking 00000000dd20a85b
>Oct 25 01:16:57 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 110
>Oct 25 01:16:57 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:57 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45
>Oct 25 01:16:57 [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000dd20a85b nonblocking
>Oct 25 01:16:57 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:57 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000dd20a85b
>Oct 25 01:16:57 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000dd20a85b
>Oct 25 01:16:57 [drm:drm_mode_addfb2 [drm]] [FB:113]
>Oct 25 01:16:57 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000dd20a85b
>Oct 25 01:16:57 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000229b8bc1 state to 00000000dd20a85b
>Oct 25 01:16:57 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000a3a7092e state to 00000000dd20a85b
>Oct 25 01:16:57 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:113] for [PLANE:28:plane 1A] state 00000000a3a7092e
>Oct 25 01:16:57 [drm:drm_atomic_check_only [drm]] checking 00000000dd20a85b
>Oct 25 01:16:57 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 113
>Oct 25 01:16:57 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:57 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45
>Oct 25 01:16:57 [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000dd20a85b nonblocking
>Oct 25 01:16:57 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:57 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000dd20a85b
>Oct 25 01:16:57 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000935c3744
>Oct 25 01:16:57 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000dd20a85b
>Oct 25 01:16:57 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000935c3744
>Oct 25 01:16:57 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000935c3744
>Oct 25 01:16:57 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000935c3744
>Oct 25 01:16:57 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000935c3744
>Oct 25 01:16:57 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000935c3744
>Oct 25 01:16:57 [drm:gen8_de_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x11101010, pins 0x00000010, long 0x00000000
>Oct 25 01:16:57 [drm:intel_hpd_irq_handler [i915]] digital hpd port A - short
>Oct 25 01:16:57 [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port A - short
>Oct 25 01:16:57 [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 41 00 00 01 80 02 00 00 00 0f 0b 00
>Oct 25 01:16:57 [drm:drm_mode_addfb2 [drm]] [FB:110]
>Oct 25 01:16:57 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000e14b3206
>Oct 25 01:16:57 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 000000006ef87567 state to 00000000e14b3206
>Oct 25 01:16:57 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000009d91cd state to 00000000e14b3206
>Oct 25 01:16:57 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:28:plane 1A] state 00000000009d91cd
>Oct 25 01:16:57 [drm:drm_atomic_check_only [drm]] checking 00000000e14b3206
>Oct 25 01:16:57 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 110
>Oct 25 01:16:57 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:57 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45
>Oct 25 01:16:57 [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000e14b3206 nonblocking
>Oct 25 01:16:57 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:57 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000e14b3206
>Oct 25 01:16:57 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000ce706e06
>Oct 25 01:16:57 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000ce706e06
>Oct 25 01:16:57 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000e14b3206
>Oct 25 01:16:57 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000ce706e06
>Oct 25 01:16:57 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000ce706e06
>Oct 25 01:16:57 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000ce706e06
>Oct 25 01:16:57 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000ce706e06
>Oct 25 01:16:57 [drm:gen8_de_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x11101010, pins 0x00000010, long 0x00000000
>Oct 25 01:16:57 [drm:intel_hpd_irq_handler [i915]] digital hpd port A - short
>Oct 25 01:16:57 [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port A - short
>Oct 25 01:16:57 [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 41 00 00 01 80 02 00 00 00 0f 0b 00
>Oct 25 01:16:58 [drm:drm_mode_addfb2 [drm]] [FB:113]
>Oct 25 01:16:58 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000f1ecca12
>Oct 25 01:16:58 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000217e0795 state to 00000000f1ecca12
>Oct 25 01:16:58 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 0000000014135680 state to 00000000f1ecca12
>Oct 25 01:16:58 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:113] for [PLANE:28:plane 1A] state 0000000014135680
>Oct 25 01:16:58 [drm:drm_atomic_check_only [drm]] checking 00000000f1ecca12
>Oct 25 01:16:58 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 113
>Oct 25 01:16:58 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:58 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45
>Oct 25 01:16:58 [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000f1ecca12 nonblocking
>Oct 25 01:16:58 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:58 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000e53e1ae0
>Oct 25 01:16:58 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000f1ecca12
>Oct 25 01:16:58 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000f1ecca12
>Oct 25 01:16:58 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000e53e1ae0
>Oct 25 01:16:58 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000e53e1ae0
>Oct 25 01:16:58 [drm:gen8_de_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x11101010, pins 0x00000010, long 0x00000000
>Oct 25 01:16:58 [drm:intel_hpd_irq_handler [i915]] digital hpd port A - short
>Oct 25 01:16:58 [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port A - short
>Oct 25 01:16:58 [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 41 00 00 01 80 02 00 00 00 0f 0b 00
>Oct 25 01:16:58 [drm:drm_mode_addfb2 [drm]] [FB:110]
>Oct 25 01:16:58 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000e53e1ae0
>Oct 25 01:16:58 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000888ce6dc state to 00000000e53e1ae0
>Oct 25 01:16:58 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000d882e53e state to 00000000e53e1ae0
>Oct 25 01:16:58 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:28:plane 1A] state 00000000d882e53e
>Oct 25 01:16:58 [drm:drm_atomic_check_only [drm]] checking 00000000e53e1ae0
>Oct 25 01:16:58 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 110
>Oct 25 01:16:58 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:58 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45
>Oct 25 01:16:58 [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000e53e1ae0 nonblocking
>Oct 25 01:16:58 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:58 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000f1ecca12
>Oct 25 01:16:58 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000e53e1ae0
>Oct 25 01:16:58 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000e53e1ae0
>Oct 25 01:16:58 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000f1ecca12
>Oct 25 01:16:58 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000f1ecca12
>Oct 25 01:16:59 [drm:drm_mode_addfb2 [drm]] [FB:113]
>Oct 25 01:16:59 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000f1ecca12
>Oct 25 01:16:59 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000e53e1ae0 state to 00000000f1ecca12
>Oct 25 01:16:59 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000fb161e43 state to 00000000f1ecca12
>Oct 25 01:16:59 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:113] for [PLANE:28:plane 1A] state 00000000fb161e43
>Oct 25 01:16:59 [drm:drm_atomic_check_only [drm]] checking 00000000f1ecca12
>Oct 25 01:16:59 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 113
>Oct 25 01:16:59 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:59 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45
>Oct 25 01:16:59 [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000f1ecca12 nonblocking
>Oct 25 01:16:59 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:59 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000217e0795
>Oct 25 01:16:59 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000217e0795
>Oct 25 01:16:59 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000217e0795
>Oct 25 01:16:59 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000217e0795
>Oct 25 01:16:59 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000f1ecca12
>Oct 25 01:16:59 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000f1ecca12
>Oct 25 01:16:59 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000217e0795
>Oct 25 01:16:59 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000217e0795
>Oct 25 01:16:59 [drm:drm_mode_addfb2 [drm]] [FB:110]
>Oct 25 01:16:59 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000217e0795
>Oct 25 01:16:59 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000f1ecca12 state to 00000000217e0795
>Oct 25 01:16:59 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 000000003d940b65 state to 00000000217e0795
>Oct 25 01:16:59 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:28:plane 1A] state 000000003d940b65
>Oct 25 01:16:59 [drm:drm_atomic_check_only [drm]] checking 00000000217e0795
>Oct 25 01:16:59 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 110
>Oct 25 01:16:59 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:59 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45
>Oct 25 01:16:59 [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000217e0795 nonblocking
>Oct 25 01:16:59 [drm:gen8_de_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x11101010, pins 0x00000010, long 0x00000000
>Oct 25 01:16:59 [drm:intel_hpd_irq_handler [i915]] digital hpd port A - short
>Oct 25 01:16:59 [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port A - short
>Oct 25 01:16:59 [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 41 00 00 01 80 02 00 00 00 0f 0b 00
>Oct 25 01:16:59 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:59 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000888ce6dc
>Oct 25 01:16:59 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000217e0795
>Oct 25 01:16:59 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000217e0795
>Oct 25 01:16:59 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000888ce6dc
>Oct 25 01:16:59 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000888ce6dc
>Oct 25 01:16:59 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000888ce6dc
>Oct 25 01:16:59 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000888ce6dc
>Oct 25 01:16:59 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000888ce6dc
>Oct 25 01:16:59 [drm:drm_mode_addfb2 [drm]] [FB:113]
>Oct 25 01:16:59 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000888ce6dc
>Oct 25 01:16:59 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000217e0795 state to 00000000888ce6dc
>Oct 25 01:16:59 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000af6a9896 state to 00000000888ce6dc
>Oct 25 01:16:59 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:113] for [PLANE:28:plane 1A] state 00000000af6a9896
>Oct 25 01:16:59 [drm:drm_atomic_check_only [drm]] checking 00000000888ce6dc
>Oct 25 01:16:59 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 113
>Oct 25 01:16:59 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:59 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45
>Oct 25 01:16:59 [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000888ce6dc nonblocking
>Oct 25 01:16:59 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:59 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000e53e1ae0
>Oct 25 01:16:59 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000e53e1ae0
>Oct 25 01:16:59 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000e53e1ae0
>Oct 25 01:16:59 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000888ce6dc
>Oct 25 01:16:59 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000888ce6dc
>Oct 25 01:16:59 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000e53e1ae0
>Oct 25 01:16:59 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000e53e1ae0
>Oct 25 01:16:59 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000e53e1ae0
>Oct 25 01:16:59 [drm:drm_mode_addfb2 [drm]] [FB:110]
>Oct 25 01:16:59 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000e53e1ae0
>Oct 25 01:16:59 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000888ce6dc state to 00000000e53e1ae0
>Oct 25 01:16:59 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 000000001791cb47 state to 00000000e53e1ae0
>Oct 25 01:16:59 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:28:plane 1A] state 000000001791cb47
>Oct 25 01:16:59 [drm:drm_atomic_check_only [drm]] checking 00000000e53e1ae0
>Oct 25 01:16:59 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 110
>Oct 25 01:16:59 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:59 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45
>Oct 25 01:16:59 [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000e53e1ae0 nonblocking
>Oct 25 01:16:59 [drm:gen8_de_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x11101010, pins 0x00000010, long 0x00000000
>Oct 25 01:16:59 [drm:intel_hpd_irq_handler [i915]] digital hpd port A - short
>Oct 25 01:16:59 [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port A - short
>Oct 25 01:16:59 [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 41 00 00 01 80 02 00 00 00 0f 0b 00
>Oct 25 01:16:59 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:59 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000f1ecca12
>Oct 25 01:16:59 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000e53e1ae0
>Oct 25 01:16:59 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000e53e1ae0
>Oct 25 01:16:59 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000f1ecca12
>Oct 25 01:16:59 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000f1ecca12
>Oct 25 01:16:59 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000f1ecca12
>Oct 25 01:16:59 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000f1ecca12
>Oct 25 01:16:59 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000f1ecca12
>Oct 25 01:16:59 [drm:drm_mode_addfb2 [drm]] [FB:113]
>Oct 25 01:16:59 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000f1ecca12
>Oct 25 01:16:59 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000e53e1ae0 state to 00000000f1ecca12
>Oct 25 01:16:59 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 000000009b37fdb2 state to 00000000f1ecca12
>Oct 25 01:16:59 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:113] for [PLANE:28:plane 1A] state 000000009b37fdb2
>Oct 25 01:16:59 [drm:drm_atomic_check_only [drm]] checking 00000000f1ecca12
>Oct 25 01:16:59 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 113
>Oct 25 01:16:59 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:16:59 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45
>Oct 25 01:16:59 [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000f1ecca12 nonblocking
>Oct 25 01:16:59 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:16:59 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000217e0795
>Oct 25 01:16:59 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000f1ecca12
>Oct 25 01:16:59 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000f1ecca12
>Oct 25 01:16:59 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000217e0795
>Oct 25 01:16:59 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000217e0795
>Oct 25 01:16:59 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000217e0795
>Oct 25 01:16:59 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000217e0795
>Oct 25 01:16:59 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000217e0795
>Oct 25 01:16:59 [drm:gen8_de_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x11101010, pins 0x00000010, long 0x00000000
>Oct 25 01:16:59 [drm:intel_hpd_irq_handler [i915]] digital hpd port A - short
>Oct 25 01:16:59 [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port A - short
>Oct 25 01:16:59 [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 41 00 00 01 80 02 00 00 00 0f 0b 00
>Oct 25 01:17:00 [drm:drm_mode_addfb2 [drm]] [FB:110]
>Oct 25 01:17:00 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000217e0795
>Oct 25 01:17:00 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000f1ecca12 state to 00000000217e0795
>Oct 25 01:17:00 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 000000008873b7b8 state to 00000000217e0795
>Oct 25 01:17:00 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:28:plane 1A] state 000000008873b7b8
>Oct 25 01:17:00 [drm:drm_atomic_check_only [drm]] checking 00000000217e0795
>Oct 25 01:17:00 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 110
>Oct 25 01:17:00 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:17:00 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45
>Oct 25 01:17:00 [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000217e0795 nonblocking
>Oct 25 01:17:00 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:17:00 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000888ce6dc
>Oct 25 01:17:00 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000888ce6dc
>Oct 25 01:17:00 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000217e0795
>Oct 25 01:17:00 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000217e0795
>Oct 25 01:17:00 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000888ce6dc
>Oct 25 01:17:00 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000888ce6dc
>Oct 25 01:17:00 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000888ce6dc
>Oct 25 01:17:00 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000888ce6dc
>Oct 25 01:17:00 [drm:drm_mode_addfb2 [drm]] [FB:113]
>Oct 25 01:17:00 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000888ce6dc
>Oct 25 01:17:00 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000217e0795 state to 00000000888ce6dc
>Oct 25 01:17:00 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000baae07e3 state to 00000000888ce6dc
>Oct 25 01:17:00 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:113] for [PLANE:28:plane 1A] state 00000000baae07e3
>Oct 25 01:17:00 [drm:drm_atomic_check_only [drm]] checking 00000000888ce6dc
>Oct 25 01:17:00 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 113
>Oct 25 01:17:00 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:17:00 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45
>Oct 25 01:17:00 [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000888ce6dc nonblocking
>Oct 25 01:17:00 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:17:00 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000e53e1ae0
>Oct 25 01:17:00 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000e53e1ae0
>Oct 25 01:17:00 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000888ce6dc
>Oct 25 01:17:00 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000888ce6dc
>Oct 25 01:17:00 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000e53e1ae0
>Oct 25 01:17:00 [drm:gen8_de_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x11101010, pins 0x00000010, long 0x00000000
>Oct 25 01:17:00 [drm:intel_hpd_irq_handler [i915]] digital hpd port A - short
>Oct 25 01:17:00 [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port A - short
>Oct 25 01:17:00 [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 41 00 00 01 80 02 00 00 00 0f 0b 00
>Oct 25 01:17:00 [drm:drm_mode_addfb2 [drm]] [FB:110]
>Oct 25 01:17:00 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000e53e1ae0
>Oct 25 01:17:00 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000888ce6dc state to 00000000e53e1ae0
>Oct 25 01:17:00 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 000000005c65d29c state to 00000000e53e1ae0
>Oct 25 01:17:00 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:28:plane 1A] state 000000005c65d29c
>Oct 25 01:17:00 [drm:drm_atomic_check_only [drm]] checking 00000000e53e1ae0
>Oct 25 01:17:00 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 110
>Oct 25 01:17:00 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:17:00 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45
>Oct 25 01:17:00 [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000e53e1ae0 nonblocking
>Oct 25 01:17:00 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:17:00 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000f1ecca12
>Oct 25 01:17:00 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000f1ecca12
>Oct 25 01:17:00 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000e53e1ae0
>Oct 25 01:17:00 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000e53e1ae0
>Oct 25 01:17:00 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000f1ecca12
>Oct 25 01:17:00 [drm:drm_mode_addfb2 [drm]] [FB:113]
>Oct 25 01:17:00 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000f1ecca12
>Oct 25 01:17:00 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000e53e1ae0 state to 00000000f1ecca12
>Oct 25 01:17:00 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000e318f39f state to 00000000f1ecca12
>Oct 25 01:17:00 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:113] for [PLANE:28:plane 1A] state 00000000e318f39f
>Oct 25 01:17:00 [drm:drm_atomic_check_only [drm]] checking 00000000f1ecca12
>Oct 25 01:17:00 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 113
>Oct 25 01:17:00 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:17:00 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45
>Oct 25 01:17:00 [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000f1ecca12 nonblocking
>Oct 25 01:17:00 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000217e0795
>Oct 25 01:17:00 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:17:00 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000217e0795
>Oct 25 01:17:00 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000f1ecca12
>Oct 25 01:17:00 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000f1ecca12
>Oct 25 01:17:00 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000217e0795
>Oct 25 01:17:00 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000217e0795
>Oct 25 01:17:00 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000217e0795
>Oct 25 01:17:00 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000217e0795
>Oct 25 01:17:00 [drm:gen8_de_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x11101010, pins 0x00000010, long 0x00000000
>Oct 25 01:17:00 [drm:intel_hpd_irq_handler [i915]] digital hpd port A - short
>Oct 25 01:17:00 [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port A - short
>Oct 25 01:17:00 [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 41 00 00 01 80 02 00 00 00 0f 0b 00
>Oct 25 01:17:01 [drm:drm_mode_addfb2 [drm]] [FB:110]
>Oct 25 01:17:01 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000217e0795
>Oct 25 01:17:01 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000f1ecca12 state to 00000000217e0795
>Oct 25 01:17:01 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 000000008c84e646 state to 00000000217e0795
>Oct 25 01:17:01 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:28:plane 1A] state 000000008c84e646
>Oct 25 01:17:01 [drm:drm_atomic_check_only [drm]] checking 00000000217e0795
>Oct 25 01:17:01 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 110
>Oct 25 01:17:01 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:17:01 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45
>Oct 25 01:17:01 [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000217e0795 nonblocking
>Oct 25 01:17:01 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:17:01 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000217e0795
>Oct 25 01:17:01 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000888ce6dc
>Oct 25 01:17:01 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000888ce6dc
>Oct 25 01:17:01 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000217e0795
>Oct 25 01:17:01 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000888ce6dc
>Oct 25 01:17:01 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000888ce6dc
>Oct 25 01:17:01 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000888ce6dc
>Oct 25 01:17:01 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000888ce6dc
>Oct 25 01:17:01 [drm:gen8_de_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x11101010, pins 0x00000010, long 0x00000000
>Oct 25 01:17:01 [drm:intel_hpd_irq_handler [i915]] digital hpd port A - short
>Oct 25 01:17:01 [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port A - short
>Oct 25 01:17:01 [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 41 00 00 01 80 02 00 00 00 0f 0b 00
>Oct 25 01:17:01 [drm:drm_mode_addfb2 [drm]] [FB:113]
>Oct 25 01:17:01 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000888ce6dc
>Oct 25 01:17:01 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000217e0795 state to 00000000888ce6dc
>Oct 25 01:17:01 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 000000005c65d29c state to 00000000888ce6dc
>Oct 25 01:17:01 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:113] for [PLANE:28:plane 1A] state 000000005c65d29c
>Oct 25 01:17:01 [drm:drm_atomic_check_only [drm]] checking 00000000888ce6dc
>Oct 25 01:17:01 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 113
>Oct 25 01:17:01 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:17:01 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45
>Oct 25 01:17:01 [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000888ce6dc nonblocking
>Oct 25 01:17:01 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:17:01 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000e53e1ae0
>Oct 25 01:17:01 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000e53e1ae0
>Oct 25 01:17:01 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000e53e1ae0
>Oct 25 01:17:01 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000888ce6dc
>Oct 25 01:17:01 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000888ce6dc
>Oct 25 01:17:01 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000e53e1ae0
>Oct 25 01:17:01 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000e53e1ae0
>Oct 25 01:17:01 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000e53e1ae0
>Oct 25 01:17:02 [drm:gen8_de_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x11101010, pins 0x00000010, long 0x00000000
>Oct 25 01:17:02 [drm:intel_hpd_irq_handler [i915]] digital hpd port A - short
>Oct 25 01:17:02 [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port A - short
>Oct 25 01:17:02 [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 41 00 00 01 80 02 00 00 00 0f 0b 00
>Oct 25 01:17:02 [drm:drm_mode_addfb2 [drm]] [FB:110]
>Oct 25 01:17:02 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000e53e1ae0
>Oct 25 01:17:02 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000888ce6dc state to 00000000e53e1ae0
>Oct 25 01:17:02 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000baae07e3 state to 00000000e53e1ae0
>Oct 25 01:17:02 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:28:plane 1A] state 00000000baae07e3
>Oct 25 01:17:02 [drm:drm_atomic_check_only [drm]] checking 00000000e53e1ae0
>Oct 25 01:17:02 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 110
>Oct 25 01:17:02 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:17:02 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45
>Oct 25 01:17:02 [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000e53e1ae0 nonblocking
>Oct 25 01:17:02 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:17:02 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000f1ecca12
>Oct 25 01:17:02 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000f1ecca12
>Oct 25 01:17:02 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000f1ecca12
>Oct 25 01:17:02 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000e53e1ae0
>Oct 25 01:17:02 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000e53e1ae0
>Oct 25 01:17:02 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000f1ecca12
>Oct 25 01:17:02 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000f1ecca12
>Oct 25 01:17:02 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000f1ecca12
>Oct 25 01:17:02 [drm:gen8_de_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x11101010, pins 0x00000010, long 0x00000000
>Oct 25 01:17:02 [drm:intel_hpd_irq_handler [i915]] digital hpd port A - short
>Oct 25 01:17:02 [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port A - short
>Oct 25 01:17:02 [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 41 00 00 01 80 02 00 00 00 0f 0b 00
>Oct 25 01:17:02 [drm:drm_mode_addfb2 [drm]] [FB:113]
>Oct 25 01:17:02 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000f1ecca12
>Oct 25 01:17:02 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000e53e1ae0 state to 00000000f1ecca12
>Oct 25 01:17:02 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 000000008873b7b8 state to 00000000f1ecca12
>Oct 25 01:17:02 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:113] for [PLANE:28:plane 1A] state 000000008873b7b8
>Oct 25 01:17:02 [drm:drm_atomic_check_only [drm]] checking 00000000f1ecca12
>Oct 25 01:17:02 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 113
>Oct 25 01:17:02 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:17:02 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45
>Oct 25 01:17:02 [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000f1ecca12 nonblocking
>Oct 25 01:17:03 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:17:03 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000f1ecca12
>Oct 25 01:17:03 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000217e0795
>Oct 25 01:17:03 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000f1ecca12
>Oct 25 01:17:03 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000217e0795
>Oct 25 01:17:03 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000217e0795
>Oct 25 01:17:03 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000217e0795
>Oct 25 01:17:03 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000217e0795
>Oct 25 01:17:03 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000217e0795
>Oct 25 01:17:03 [drm:gen8_de_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x11101010, pins 0x00000010, long 0x00000000
>Oct 25 01:17:03 [drm:intel_hpd_irq_handler [i915]] digital hpd port A - short
>Oct 25 01:17:03 [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port A - short
>Oct 25 01:17:03 [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 41 00 00 01 80 02 00 00 00 0f 0b 00
>Oct 25 01:17:03 [drm:drm_mode_addfb2 [drm]] [FB:110]
>Oct 25 01:17:03 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000217e0795
>Oct 25 01:17:03 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000f1ecca12 state to 00000000217e0795
>Oct 25 01:17:03 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 000000009b37fdb2 state to 00000000217e0795
>Oct 25 01:17:03 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:28:plane 1A] state 000000009b37fdb2
>Oct 25 01:17:03 [drm:drm_atomic_check_only [drm]] checking 00000000217e0795
>Oct 25 01:17:03 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 110
>Oct 25 01:17:03 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:17:03 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45
>Oct 25 01:17:03 [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000217e0795 nonblocking
>Oct 25 01:17:03 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:17:03 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000888ce6dc
>Oct 25 01:17:03 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000888ce6dc
>Oct 25 01:17:03 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000217e0795
>Oct 25 01:17:03 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000217e0795
>Oct 25 01:17:03 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000888ce6dc
>Oct 25 01:17:03 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000888ce6dc
>Oct 25 01:17:03 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000888ce6dc
>Oct 25 01:17:03 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000888ce6dc
>Oct 25 01:17:03 [drm:gen8_de_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x11101010, pins 0x00000010, long 0x00000000
>Oct 25 01:17:03 [drm:intel_hpd_irq_handler [i915]] digital hpd port A - short
>Oct 25 01:17:03 [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port A - short
>Oct 25 01:17:03 [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 41 00 00 01 80 02 00 00 00 0f 0b 00
>Oct 25 01:17:04 [drm:drm_mode_addfb2 [drm]] [FB:113]
>Oct 25 01:17:04 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000888ce6dc
>Oct 25 01:17:04 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000217e0795 state to 00000000888ce6dc
>Oct 25 01:17:04 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 000000001791cb47 state to 00000000888ce6dc
>Oct 25 01:17:04 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:113] for [PLANE:28:plane 1A] state 000000001791cb47
>Oct 25 01:17:04 [drm:drm_atomic_check_only [drm]] checking 00000000888ce6dc
>Oct 25 01:17:04 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 113
>Oct 25 01:17:04 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:17:04 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45
>Oct 25 01:17:04 [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000888ce6dc nonblocking
>Oct 25 01:17:04 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:17:04 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000e53e1ae0
>Oct 25 01:17:04 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000e53e1ae0
>Oct 25 01:17:04 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000888ce6dc
>Oct 25 01:17:04 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000e53e1ae0
>Oct 25 01:17:04 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000888ce6dc
>Oct 25 01:17:04 [drm:drm_mode_addfb2 [drm]] [FB:110]
>Oct 25 01:17:04 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000e53e1ae0
>Oct 25 01:17:04 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000888ce6dc state to 00000000e53e1ae0
>Oct 25 01:17:04 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000af6a9896 state to 00000000e53e1ae0
>Oct 25 01:17:04 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:28:plane 1A] state 00000000af6a9896
>Oct 25 01:17:04 [drm:drm_atomic_check_only [drm]] checking 00000000e53e1ae0
>Oct 25 01:17:04 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 110
>Oct 25 01:17:04 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:17:04 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45
>Oct 25 01:17:04 [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000e53e1ae0 nonblocking
>Oct 25 01:17:04 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:17:04 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000f1ecca12
>Oct 25 01:17:04 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000f1ecca12
>Oct 25 01:17:04 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000e53e1ae0
>Oct 25 01:17:04 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000e53e1ae0
>Oct 25 01:17:04 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000f1ecca12
>Oct 25 01:17:04 [drm:drm_mode_addfb2 [drm]] [FB:113]
>Oct 25 01:17:04 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000f1ecca12
>Oct 25 01:17:04 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000e53e1ae0 state to 00000000f1ecca12
>Oct 25 01:17:04 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 000000009b37fdb2 state to 00000000f1ecca12
>Oct 25 01:17:04 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:113] for [PLANE:28:plane 1A] state 000000009b37fdb2
>Oct 25 01:17:04 [drm:drm_atomic_check_only [drm]] checking 00000000f1ecca12
>Oct 25 01:17:04 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 113
>Oct 25 01:17:04 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:17:04 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45
>Oct 25 01:17:04 [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000f1ecca12 nonblocking
>Oct 25 01:17:04 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:17:04 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000217e0795
>Oct 25 01:17:04 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000217e0795
>Oct 25 01:17:04 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000217e0795
>Oct 25 01:17:04 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000217e0795
>Oct 25 01:17:04 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000f1ecca12
>Oct 25 01:17:04 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000f1ecca12
>Oct 25 01:17:04 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000217e0795
>Oct 25 01:17:04 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000217e0795
>Oct 25 01:17:04 [drm:drm_mode_addfb2 [drm]] [FB:110]
>Oct 25 01:17:04 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000217e0795
>Oct 25 01:17:04 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000f1ecca12 state to 00000000217e0795
>Oct 25 01:17:04 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 000000008873b7b8 state to 00000000217e0795
>Oct 25 01:17:04 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:28:plane 1A] state 000000008873b7b8
>Oct 25 01:17:04 [drm:drm_atomic_check_only [drm]] checking 00000000217e0795
>Oct 25 01:17:04 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 110
>Oct 25 01:17:04 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:17:04 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45
>Oct 25 01:17:04 [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000217e0795 nonblocking
>Oct 25 01:17:04 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000888ce6dc
>Oct 25 01:17:04 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:17:04 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000888ce6dc
>Oct 25 01:17:04 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000217e0795
>Oct 25 01:17:04 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000217e0795
>Oct 25 01:17:04 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000888ce6dc
>Oct 25 01:17:04 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000888ce6dc
>Oct 25 01:17:04 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000888ce6dc
>Oct 25 01:17:04 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000888ce6dc
>Oct 25 01:17:04 [drm:drm_mode_addfb2 [drm]] [FB:113]
>Oct 25 01:17:04 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000888ce6dc
>Oct 25 01:17:04 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000217e0795 state to 00000000888ce6dc
>Oct 25 01:17:04 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000baae07e3 state to 00000000888ce6dc
>Oct 25 01:17:04 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:113] for [PLANE:28:plane 1A] state 00000000baae07e3
>Oct 25 01:17:04 [drm:drm_atomic_check_only [drm]] checking 00000000888ce6dc
>Oct 25 01:17:04 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 113
>Oct 25 01:17:04 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:17:04 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45
>Oct 25 01:17:04 [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000888ce6dc nonblocking
>Oct 25 01:17:04 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000e53e1ae0
>Oct 25 01:17:04 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:17:04 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000e53e1ae0
>Oct 25 01:17:04 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000888ce6dc
>Oct 25 01:17:04 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000888ce6dc
>Oct 25 01:17:04 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000e53e1ae0
>Oct 25 01:17:04 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000e53e1ae0
>Oct 25 01:17:04 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000e53e1ae0
>Oct 25 01:17:04 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000e53e1ae0
>Oct 25 01:17:04 [drm:gen8_de_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x11101010, pins 0x00000010, long 0x00000000
>Oct 25 01:17:04 [drm:intel_hpd_irq_handler [i915]] digital hpd port A - short
>Oct 25 01:17:04 [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port A - short
>Oct 25 01:17:04 [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 41 00 00 01 80 02 00 00 00 0f 0b 00
>Oct 25 01:17:04 [drm:drm_mode_addfb2 [drm]] [FB:110]
>Oct 25 01:17:04 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000e53e1ae0
>Oct 25 01:17:04 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000888ce6dc state to 00000000e53e1ae0
>Oct 25 01:17:04 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 000000005c65d29c state to 00000000e53e1ae0
>Oct 25 01:17:04 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:28:plane 1A] state 000000005c65d29c
>Oct 25 01:17:04 [drm:drm_atomic_check_only [drm]] checking 00000000e53e1ae0
>Oct 25 01:17:04 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 110
>Oct 25 01:17:04 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:17:04 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45
>Oct 25 01:17:04 [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000e53e1ae0 nonblocking
>Oct 25 01:17:04 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:17:04 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000e53e1ae0
>Oct 25 01:17:04 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000e53e1ae0
>Oct 25 01:17:05 [drm:gen8_de_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x11101010, pins 0x00000010, long 0x00000000
>Oct 25 01:17:05 [drm:intel_hpd_irq_handler [i915]] digital hpd port A - short
>Oct 25 01:17:05 [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port A - short
>Oct 25 01:17:05 [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 41 00 00 01 80 02 00 00 00 0f 0b 00
>Oct 25 01:17:05 [drm:drm_mode_addfb2 [drm]] [FB:113]
>Oct 25 01:17:05 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000f1ecca12
>Oct 25 01:17:05 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000e53e1ae0 state to 00000000f1ecca12
>Oct 25 01:17:05 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 000000008d0a38c2 state to 00000000f1ecca12
>Oct 25 01:17:05 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:113] for [PLANE:28:plane 1A] state 000000008d0a38c2
>Oct 25 01:17:05 [drm:drm_atomic_check_only [drm]] checking 00000000f1ecca12
>Oct 25 01:17:05 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 113
>Oct 25 01:17:05 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:17:05 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45
>Oct 25 01:17:05 [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000f1ecca12 nonblocking
>Oct 25 01:17:05 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:17:05 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000f1ecca12
>Oct 25 01:17:05 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000217e0795
>Oct 25 01:17:05 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000f1ecca12
>Oct 25 01:17:05 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000217e0795
>Oct 25 01:17:05 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000217e0795
>Oct 25 01:17:05 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000217e0795
>Oct 25 01:17:05 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000217e0795
>Oct 25 01:17:05 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000217e0795
>Oct 25 01:17:05 [drm:drm_mode_addfb2 [drm]] [FB:110]
>Oct 25 01:17:05 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000217e0795
>Oct 25 01:17:05 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000f1ecca12 state to 00000000217e0795
>Oct 25 01:17:05 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000c843f5b3 state to 00000000217e0795
>Oct 25 01:17:05 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:28:plane 1A] state 00000000c843f5b3
>Oct 25 01:17:05 [drm:drm_atomic_check_only [drm]] checking 00000000217e0795
>Oct 25 01:17:05 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 110
>Oct 25 01:17:05 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:17:05 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45
>Oct 25 01:17:05 [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000217e0795 nonblocking
>Oct 25 01:17:05 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000888ce6dc
>Oct 25 01:17:05 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:17:05 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000888ce6dc
>Oct 25 01:17:05 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000217e0795
>Oct 25 01:17:05 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000217e0795
>Oct 25 01:17:05 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000888ce6dc
>Oct 25 01:17:05 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000888ce6dc
>Oct 25 01:17:05 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000888ce6dc
>Oct 25 01:17:05 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000888ce6dc
>Oct 25 01:17:05 [drm:drm_mode_addfb2 [drm]] [FB:113]
>Oct 25 01:17:05 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000888ce6dc
>Oct 25 01:17:05 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000217e0795 state to 00000000888ce6dc
>Oct 25 01:17:05 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000df1d36b4 state to 00000000888ce6dc
>Oct 25 01:17:05 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:113] for [PLANE:28:plane 1A] state 00000000df1d36b4
>Oct 25 01:17:05 [drm:drm_atomic_check_only [drm]] checking 00000000888ce6dc
>Oct 25 01:17:05 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 113
>Oct 25 01:17:05 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:17:05 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45
>Oct 25 01:17:05 [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000888ce6dc nonblocking
>Oct 25 01:17:05 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:17:05 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000e53e1ae0
>Oct 25 01:17:05 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000e53e1ae0
>Oct 25 01:17:05 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000888ce6dc
>Oct 25 01:17:05 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000e53e1ae0
>Oct 25 01:17:05 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000888ce6dc
>Oct 25 01:17:05 [drm:gen8_de_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x11101010, pins 0x00000010, long 0x00000000
>Oct 25 01:17:05 [drm:intel_hpd_irq_handler [i915]] digital hpd port A - short
>Oct 25 01:17:05 [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port A - short
>Oct 25 01:17:05 [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 41 00 00 01 80 02 00 00 00 0f 0b 00
>Oct 25 01:17:05 [drm:drm_mode_addfb2 [drm]] [FB:110]
>Oct 25 01:17:05 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000dd20a85b
>Oct 25 01:17:05 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000cfbb2c46 state to 00000000dd20a85b
>Oct 25 01:17:05 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 0000000080c08f9a state to 00000000dd20a85b
>Oct 25 01:17:05 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:28:plane 1A] state 0000000080c08f9a
>Oct 25 01:17:05 [drm:drm_atomic_check_only [drm]] checking 00000000dd20a85b
>Oct 25 01:17:05 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 110
>Oct 25 01:17:05 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:17:05 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45
>Oct 25 01:17:05 [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000dd20a85b nonblocking
>Oct 25 01:17:05 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:17:05 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000dd20a85b
>Oct 25 01:17:05 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000dd20a85b
>Oct 25 01:17:05 [drm:drm_mode_addfb2 [drm]] [FB:113]
>Oct 25 01:17:05 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000e53e1ae0
>Oct 25 01:17:05 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000217e0795 state to 00000000e53e1ae0
>Oct 25 01:17:05 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000668c6894 state to 00000000e53e1ae0
>Oct 25 01:17:05 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:113] for [PLANE:28:plane 1A] state 00000000668c6894
>Oct 25 01:17:05 [drm:drm_atomic_check_only [drm]] checking 00000000e53e1ae0
>Oct 25 01:17:05 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 113
>Oct 25 01:17:05 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:17:05 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45
>Oct 25 01:17:05 [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000e53e1ae0 nonblocking
>Oct 25 01:17:05 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:17:05 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000888ce6dc
>Oct 25 01:17:05 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000888ce6dc
>Oct 25 01:17:05 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000e53e1ae0
>Oct 25 01:17:05 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000e53e1ae0
>Oct 25 01:17:05 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000888ce6dc
>Oct 25 01:17:05 [drm:drm_mode_addfb2 [drm]] [FB:110]
>Oct 25 01:17:05 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000ce706e06
>Oct 25 01:17:05 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000c7512c5c state to 00000000ce706e06
>Oct 25 01:17:05 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 000000002e29199c state to 00000000ce706e06
>Oct 25 01:17:05 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:28:plane 1A] state 000000002e29199c
>Oct 25 01:17:05 [drm:drm_atomic_check_only [drm]] checking 00000000ce706e06
>Oct 25 01:17:05 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 110
>Oct 25 01:17:05 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:17:05 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45
>Oct 25 01:17:05 [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000ce706e06 nonblocking
>Oct 25 01:17:05 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:17:05 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000ce706e06
>Oct 25 01:17:05 [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000032e4e74b
>Oct 25 01:17:05 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000032e4e74b
>Oct 25 01:17:05 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000032e4e74b
>Oct 25 01:17:05 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000ce706e06
>Oct 25 01:17:05 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000032e4e74b
>Oct 25 01:17:05 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000032e4e74b
>Oct 25 01:17:05 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000032e4e74b
>Oct 25 01:17:06 [drm:drm_mode_addfb2 [drm]] [FB:113]
>Oct 25 01:17:06 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000c92b4d9a
>Oct 25 01:17:06 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 000000000ab4b2fc state to 00000000c92b4d9a
>Oct 25 01:17:06 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 0000000045211b27 state to 00000000c92b4d9a
>Oct 25 01:17:06 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:113] for [PLANE:28:plane 1A] state 0000000045211b27
>Oct 25 01:17:06 [drm:drm_atomic_check_only [drm]] checking 00000000c92b4d9a
>Oct 25 01:17:06 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 113
>Oct 25 01:17:06 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:17:06 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45
>Oct 25 01:17:06 [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000c92b4d9a nonblocking
>Oct 25 01:17:06 [drm:gen8_de_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x11101010, pins 0x00000010, long 0x00000000
>Oct 25 01:17:06 [drm:intel_hpd_irq_handler [i915]] digital hpd port A - short
>Oct 25 01:17:06 [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port A - short
>Oct 25 01:17:06 [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 41 00 00 01 80 02 00 00 00 0f 0b 00
>Oct 25 01:17:06 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:17:06 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000c92b4d9a
>Oct 25 01:17:06 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000c92b4d9a
>Oct 25 01:17:06 [drm:gen8_de_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x11101010, pins 0x00000010, long 0x00000000
>Oct 25 01:17:06 [drm:intel_hpd_irq_handler [i915]] digital hpd port A - short
>Oct 25 01:17:06 [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port A - short
>Oct 25 01:17:06 [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 41 00 00 01 80 02 00 00 00 0f 0b 00
>Oct 25 01:17:06 [drm:drm_mode_addfb2 [drm]] [FB:110]
>Oct 25 01:17:06 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000c92b4d9a
>Oct 25 01:17:06 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 000000001cc9f018 state to 00000000c92b4d9a
>Oct 25 01:17:06 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 000000008e8b0461 state to 00000000c92b4d9a
>Oct 25 01:17:06 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:28:plane 1A] state 000000008e8b0461
>Oct 25 01:17:06 [drm:drm_atomic_check_only [drm]] checking 00000000c92b4d9a
>Oct 25 01:17:06 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 110
>Oct 25 01:17:06 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:17:06 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45
>Oct 25 01:17:06 [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000c92b4d9a nonblocking
>Oct 25 01:17:06 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:17:06 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000c92b4d9a
>Oct 25 01:17:06 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000c92b4d9a
>Oct 25 01:17:06 [drm:gen8_de_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x11101010, pins 0x00000010, long 0x00000000
>Oct 25 01:17:06 [drm:intel_hpd_irq_handler [i915]] digital hpd port A - short
>Oct 25 01:17:06 [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port A - short
>Oct 25 01:17:06 [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 41 00 00 01 80 02 00 00 00 0f 0b 00
>Oct 25 01:17:07 [drm:drm_mode_addfb2 [drm]] [FB:113]
>Oct 25 01:17:07 [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000055e5b1c7
>Oct 25 01:17:07 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000ff023107 state to 0000000055e5b1c7
>Oct 25 01:17:07 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000c3022ad1 state to 0000000055e5b1c7
>Oct 25 01:17:07 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:113] for [PLANE:28:plane 1A] state 00000000c3022ad1
>Oct 25 01:17:07 [drm:drm_atomic_check_only [drm]] checking 0000000055e5b1c7
>Oct 25 01:17:07 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 113
>Oct 25 01:17:07 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:17:07 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45
>Oct 25 01:17:07 [drm:drm_atomic_nonblocking_commit [drm]] committing 0000000055e5b1c7 nonblocking
>Oct 25 01:17:07 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:17:07 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000055e5b1c7
>Oct 25 01:17:07 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000055e5b1c7
>Oct 25 01:17:07 [drm:gen8_de_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x11101010, pins 0x00000010, long 0x00000000
>Oct 25 01:17:07 [drm:intel_hpd_irq_handler [i915]] digital hpd port A - short
>Oct 25 01:17:07 [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port A - short
>Oct 25 01:17:07 [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 41 00 00 01 80 02 00 00 00 0f 0b 00
>Oct 25 01:17:07 [drm:drm_mode_addfb2 [drm]] [FB:110]
>Oct 25 01:17:07 [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000055e5b1c7
>Oct 25 01:17:07 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 000000001cc9f018 state to 0000000055e5b1c7
>Oct 25 01:17:07 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 0000000076c0581d state to 0000000055e5b1c7
>Oct 25 01:17:07 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:28:plane 1A] state 0000000076c0581d
>Oct 25 01:17:07 [drm:drm_atomic_check_only [drm]] checking 0000000055e5b1c7
>Oct 25 01:17:07 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 110
>Oct 25 01:17:07 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:17:07 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45
>Oct 25 01:17:07 [drm:drm_atomic_nonblocking_commit [drm]] committing 0000000055e5b1c7 nonblocking
>Oct 25 01:17:07 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:17:07 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000055e5b1c7
>Oct 25 01:17:07 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000055e5b1c7
>Oct 25 01:17:08 [drm:gen8_de_irq_handler [i915]] hotplug event received, stat 0x01000000, dig 0x11101010, pins 0x00000010, long 0x00000000
>Oct 25 01:17:08 [drm:intel_hpd_irq_handler [i915]] digital hpd port A - short
>Oct 25 01:17:08 [drm:intel_dp_hpd_pulse [i915]] got hpd irq on port A - short
>Oct 25 01:17:08 [drm:intel_dp_read_dpcd [i915]] DPCD: 11 0a 84 41 00 00 01 80 02 00 00 00 0f 0b 00
>Oct 25 01:17:08 [drm:drm_mode_addfb2 [drm]] [FB:113]
>Oct 25 01:17:08 [drm:drm_atomic_state_init [drm]] Allocated atomic state 00000000c92b4d9a
>Oct 25 01:17:08 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 000000000ab4b2fc state to 00000000c92b4d9a
>Oct 25 01:17:08 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 00000000915c31d4 state to 00000000c92b4d9a
>Oct 25 01:17:08 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:113] for [PLANE:28:plane 1A] state 00000000915c31d4
>Oct 25 01:17:08 [drm:drm_atomic_check_only [drm]] checking 00000000c92b4d9a
>Oct 25 01:17:08 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 113
>Oct 25 01:17:08 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:17:08 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45
>Oct 25 01:17:08 [drm:drm_atomic_nonblocking_commit [drm]] committing 00000000c92b4d9a nonblocking
>Oct 25 01:17:08 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:17:08 [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000055e5b1c7
>Oct 25 01:17:08 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000055e5b1c7
>Oct 25 01:17:08 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000055e5b1c7
>Oct 25 01:17:08 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 00000000c92b4d9a
>Oct 25 01:17:08 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 00000000c92b4d9a
>Oct 25 01:17:08 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000055e5b1c7
>Oct 25 01:17:08 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000055e5b1c7
>Oct 25 01:17:08 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000055e5b1c7
>Oct 25 01:17:08 [drm:drm_mode_addfb2 [drm]] [FB:110]
>Oct 25 01:17:08 [drm:drm_atomic_state_init [drm]] Allocated atomic state 0000000055e5b1c7
>Oct 25 01:17:08 [drm:drm_atomic_get_crtc_state [drm]] Added [CRTC:45:pipe A] 00000000ff023107 state to 0000000055e5b1c7
>Oct 25 01:17:08 [drm:drm_atomic_get_plane_state [drm]] Added [PLANE:28:plane 1A] 000000007a781f4d state to 0000000055e5b1c7
>Oct 25 01:17:08 [drm:drm_atomic_set_fb_for_plane [drm]] Set [FB:110] for [PLANE:28:plane 1A] state 000000007a781f4d
>Oct 25 01:17:08 [drm:drm_atomic_check_only [drm]] checking 0000000055e5b1c7
>Oct 25 01:17:08 [drm:intel_plane_atomic_calc_changes [i915]] [CRTC:45:pipe A] has [PLANE:28:plane 1A] with fb 110
>Oct 25 01:17:08 [drm:intel_plane_atomic_calc_changes [i915]] [PLANE:28:plane 1A] visible 1 -> 1, off 0, on 0, ms 0
>Oct 25 01:17:08 [drm:intel_atomic_setup_scalers [i915]] Attached scaler id 0.0 to CRTC:45
>Oct 25 01:17:08 [drm:drm_atomic_nonblocking_commit [drm]] committing 0000000055e5b1c7 nonblocking
>Oct 25 01:17:08 [drm:intel_frontbuffer_flush [i915]] Avoid PSR SW frontbuffer tracking
>Oct 25 01:17:08 [drm:drm_atomic_state_default_clear [drm]] Clearing atomic state 0000000055e5b1c7
>Oct 25 01:17:08 [drm:__drm_atomic_state_free [drm]] Freeing atomic state 0000000055e5b1c7

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Attachments on bug 108503: 142108 | 142109 | 142110 | 142111 | 142146 | 142181 | 142191 | 142192 | 142193 | 142194 | 142403 | 142415 | 142417

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