Attachment 142536 Details for Bug 108814 – gallium dump t1

gallium dump t1

roles_1043_00000001 (text/plain), 248.00 KB, created by Domen on 2018-11-21 11:13:07 UTC

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Filename:

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Creator: Domen

Created: 2018-11-21 11:13:07 UTC

Size: 248.00 KB

patch

obsolete

>Command: ./roles -1 1 
>Driver vendor: X.Org
>Device vendor: AMD
>Device name: AMD Radeon (TM) RX 460 Graphics (POLARIS11, DRM 3.27.0, 4.19.2, LLVM 7.0.0)
>
>[1;33mpipe[0m = 0x12d2b40
>[1;33mtime before (API call)[0m = 332.014456s
>[1;33mtime after (driver done)[0m = 332.014673s
>
>[1;33mdraw_info: [0m{index_size = 0, has_user_indices = 0, mode = triangle_strip, start = 0, count = 0, start_instance = 0, instance_count = 1, drawid = 0, vertices_per_patch = 3, index_bias = 0, min_index = 0, max_index = 4294967295, primitive_restart = 0, count_from_stream_output = NULL, indirect->offset = 259152, indirect->stride = 16, indirect->draw_count = 1, indirect->indirect_draw_count_offset = 0, indirect->buffer = 0x7efba011a240, indirect->indirect_draw_count = NULL, }
>  indirect->buffer: {target = buffer, format = PIPE_FORMAT_R8_UNORM, width0 = 388608, height0 = 1, depth0 = 1, array_size = 1, last_level = 0, nr_samples = 0, nr_storage_samples = 0, usage = 0, bind = 0, flags = 3, }
>
>[1;33mvertex_buffer 0: [0m{stride = 32, is_user_buffer = 0, buffer_offset = 0, buffer.resource = 0x7efba0019770, }
>  buffer.resource: {target = buffer, format = PIPE_FORMAT_R8_UNORM, width0 = 777216, height0 = 1, depth0 = 1, array_size = 1, last_level = 0, nr_samples = 0, nr_storage_samples = 0, usage = 0, bind = 0, flags = 3, }
>[1;33mnum vertex elements[0m = 5
>  [1;33mvertex_element 0: [0m{src_offset = 0, instance_divisor = 1, vertex_buffer_index = 0, src_format = PIPE_FORMAT_R32G32_FLOAT, }
>  [1;33mvertex_element 1: [0m{src_offset = 8, instance_divisor = 1, vertex_buffer_index = 0, src_format = PIPE_FORMAT_R32G32_FLOAT, }
>  [1;33mvertex_element 2: [0m{src_offset = 16, instance_divisor = 1, vertex_buffer_index = 0, src_format = PIPE_FORMAT_R32G32_FLOAT, }
>  [1;33mvertex_element 3: [0m{src_offset = 24, instance_divisor = 1, vertex_buffer_index = 0, src_format = PIPE_FORMAT_R32_UINT, }
>  [1;33mvertex_element 4: [0m{src_offset = 28, instance_divisor = 1, vertex_buffer_index = 0, src_format = PIPE_FORMAT_R32_UINT, }
>[1;33mnum stream output targets[0m = 0
>
>[1;32mbegin shader: VERTEX[0m
>[1;33mshader_state: [0m{tokens = "
>VERT
>PROPERTY NEXT_SHADER FRAG
>DCL IN[0]
>DCL IN[1]
>DCL IN[2]
>DCL IN[3]
>DCL IN[4]
>DCL SV[0], VERTEXID
>DCL OUT[0], POSITION
>DCL OUT[1].xy, GENERIC[0]
>DCL OUT[2].x, GENERIC[1]
>DCL OUT[3].x, GENERIC[2]
>DCL BUFFER[8]
>DCL CONST[0][0]
>DCL CONST[1][0..260]
>DCL TEMP[0..46], LOCAL
>IMM[0] INT32 {1, 0, 0, 0}
>IMM[1] FLT32 {    0.0000,     1.0000,     0.0000,     0.0000}
>IMM[2] UINT32 {0, 192, 4, 64}
>IMM[3] UINT32 {80, 96, 112, 128}
>IMM[4] UINT32 {16, 32, 48, 0}
>  0: UADD OUT[3].x, CONST[0][0].xxxx, IN[4].xxxx
>  1: ISHR TEMP[0].x, SV[0].xxxx, IMM[0].xxxx
>  2: I2F TEMP[1].x, TEMP[0].xxxx
>  3: AND TEMP[2].x, SV[0].xxxx, IMM[0].xxxx
>  4: I2F TEMP[3].x, TEMP[2].xxxx
>  5: MOV TEMP[1].y, TEMP[3].xxxx
>  6: ADD TEMP[4].xy, TEMP[1].xyyy, IN[2].xyyy
>  7: MUL OUT[1].xy, IN[1].xyyy, TEMP[4].xyyy
>  8: MOV OUT[2].x, IN[3].xxxx
>  9: MUL TEMP[5].xy, TEMP[1].xyyy, IN[0].xyyy
> 10: LOAD TEMP[6].x, CONSTBUF[1], IMM[2].xxxx
> 11: LOAD TEMP[7].x, CONSTBUF[1], IMM[2].zzzz
> 12: UMUL TEMP[8].x, TEMP[7].xxxx, IMM[2].wwww
> 13: UMAD TEMP[9].x, TEMP[6].xxxx, IMM[2].yyyy, TEMP[8].xxxx
> 14: UADD TEMP[10].x, TEMP[9].xxxx, IMM[3].xxxx
> 15: LOAD TEMP[11], CONSTBUF[1], TEMP[10].xxxx
> 16: UADD TEMP[12].x, TEMP[9].xxxx, IMM[3].yyyy
> 17: LOAD TEMP[13], CONSTBUF[1], TEMP[12].xxxx
> 18: UADD TEMP[14].x, TEMP[9].xxxx, IMM[3].zzzz
> 19: LOAD TEMP[15], CONSTBUF[1], TEMP[14].xxxx
> 20: UADD TEMP[16].x, TEMP[9].xxxx, IMM[3].wwww
> 21: LOAD TEMP[17], CONSTBUF[1], TEMP[16].xxxx
> 22: LOAD TEMP[18].x, CONSTBUF[1], IMM[2].xxxx
> 23: UMUL TEMP[19].x, TEMP[18].xxxx, IMM[2].yyyy
> 24: UADD TEMP[20].x, TEMP[19].xxxx, IMM[4].xxxx
> 25: LOAD TEMP[21], CONSTBUF[1], TEMP[20].xxxx
> 26: UADD TEMP[22].x, TEMP[19].xxxx, IMM[4].yyyy
> 27: LOAD TEMP[23], CONSTBUF[1], TEMP[22].xxxx
> 28: UADD TEMP[24].x, TEMP[19].xxxx, IMM[4].zzzz
> 29: LOAD TEMP[25], CONSTBUF[1], TEMP[24].xxxx
> 30: UADD TEMP[26].x, TEMP[19].xxxx, IMM[2].wwww
> 31: LOAD TEMP[27], CONSTBUF[1], TEMP[26].xxxx
> 32: UMUL TEMP[28].x, OUT[3].xxxx, IMM[3].yyyy
> 33: LOAD TEMP[29], BUFFER[8], TEMP[28].xxxx, RESTRICT
> 34: UADD TEMP[30].x, TEMP[28].xxxx, IMM[4].xxxx
> 35: LOAD TEMP[31], BUFFER[8], TEMP[30].xxxx, RESTRICT
> 36: UADD TEMP[32].x, TEMP[28].xxxx, IMM[4].yyyy
> 37: LOAD TEMP[33], BUFFER[8], TEMP[32].xxxx, RESTRICT
> 38: UADD TEMP[34].x, TEMP[28].xxxx, IMM[4].zzzz
> 39: LOAD TEMP[35], BUFFER[8], TEMP[34].xxxx, RESTRICT
> 40: MUL TEMP[36], TEMP[29], TEMP[5].xxxx
> 41: MAD TEMP[37], TEMP[31], TEMP[5].yyyy, TEMP[36]
> 42: MAD TEMP[38], TEMP[33], IMM[1].xxxx, TEMP[37]
> 43: MAD TEMP[39], TEMP[35], IMM[1].yyyy, TEMP[38]
> 44: MUL TEMP[40], TEMP[21], TEMP[39].xxxx
> 45: MAD TEMP[41], TEMP[23], TEMP[39].yyyy, TEMP[40]
> 46: MAD TEMP[42], TEMP[25], TEMP[39].zzzz, TEMP[41]
> 47: MAD TEMP[43], TEMP[27], TEMP[39].wwww, TEMP[42]
> 48: MUL TEMP[44], TEMP[11], TEMP[43].xxxx
> 49: MAD TEMP[45], TEMP[13], TEMP[43].yyyy, TEMP[44]
> 50: MAD TEMP[46], TEMP[15], TEMP[43].zzzz, TEMP[45]
> 51: MAD OUT[0], TEMP[17], TEMP[43].wwww, TEMP[46]
> 52: END
>", }
>[1;33mconstant_buffer 0: [0m{buffer = NULL, buffer_offset = 0, buffer_size = 16, user_buffer = 0x7efba0020570, }
>[1;33mconstant_buffer 1: [0m{buffer = 0x7efba015b690, buffer_offset = 0, buffer_size = 4016, user_buffer = NULL, }
>  buffer: {target = buffer, format = PIPE_FORMAT_R8_UNORM, width0 = 4016, height0 = 1, depth0 = 1, array_size = 1, last_level = 0, nr_samples = 0, nr_storage_samples = 0, usage = 0, bind = 0, flags = 0, }
>[1;33mshader_buffer 8: [0m{buffer = 0x7efba0085d00, buffer_offset = 0, buffer_size = 2331648, }
>  buffer: {target = buffer, format = PIPE_FORMAT_R8_UNORM, width0 = 2331648, height0 = 1, depth0 = 1, array_size = 1, last_level = 0, nr_samples = 0, nr_storage_samples = 0, usage = 0, bind = 0, flags = 3, }
>[1;32mend shader: VERTEX[0m
>
>[1;33mviewport_state 0: [0m{scale = {960, 540, 0.5, }, translate = {960, 540, 0.5, }, }
>[1;33mrasterizer_state: [0m{flatshade = 0, light_twoside = 0, clamp_vertex_color = 0, clamp_fragment_color = 0, front_ccw = 0, cull_face = 2, fill_front = 0, fill_back = 0, offset_point = 0, offset_line = 0, offset_tri = 0, scissor = 0, poly_smooth = 0, poly_stipple_enable = 0, point_smooth = 0, sprite_coord_enable = 0, sprite_coord_mode = 1, point_quad_rasterization = 1, point_tri_clip = 0, point_size_per_vertex = 0, multisample = 0, line_smooth = 0, line_stipple_enable = 0, line_stipple_factor = 0, line_stipple_pattern = 65535, line_last_pixel = 0, flatshade_first = 0, half_pixel_center = 1, bottom_edge_rule = 0, rasterizer_discard = 0, depth_clip = 1, clip_halfz = 0, clip_plane_enable = 0, line_width = 1, point_size = 1, offset_units = 0, offset_scale = 0, offset_clamp = 0, }
>
>[1;32mbegin shader: FRAGMENT[0m
>[1;33mshader_state: [0m{tokens = "
>FRAG
>DCL IN[0].xy, GENERIC[0], PERSPECTIVE
>DCL IN[1].x, GENERIC[1], CONSTANT
>DCL IN[2].x, GENERIC[2], CONSTANT
>DCL SV[0], POSITION
>DCL OUT[0], COLOR
>DCL BUFFER[8]
>DCL CONST[0][0]
>DCL CONST[1][0..260]
>DCL TEMP[0]
>DCL TEMP[1..23], LOCAL
>IMM[0] UINT32 {96, 64, 72, 76}
>IMM[1] UINT32 {80, 0, 16, 3856}
>  0: MOV TEMP[0], SV[0]
>  1: MAD TEMP[0].y, SV[0], CONST[0][0].xxxx, CONST[0][0].yyyy
>  2: UMAD TEMP[1].x, IN[2].xxxx, IMM[0].xxxx, IMM[0].yyyy
>  3: LOAD TEMP[2].xy, BUFFER[8], TEMP[1].xxxx, RESTRICT
>  4: MOV TEMP[3].xy, TEMP[2].xyxy
>  5: MOV TEMP[4].xy, IN[0].xyyy
>  6: TEX TEMP[5], TEMP[4], TEMP[3].xyxy, 2D
>  7: MOV OUT[0].xyz, TEMP[5].xyzx
>  8: UMAD TEMP[6].x, IN[2].xxxx, IMM[0].xxxx, IMM[0].zzzz
>  9: LOAD TEMP[7].x, BUFFER[8], TEMP[6].xxxx, RESTRICT
> 10: MUL TEMP[8].x, TEMP[5].wwww, TEMP[7].xxxx
> 11: MOV OUT[0].w, TEMP[8].xxxx
> 12: MAX TEMP[9].x, TEMP[5].yyyy, TEMP[5].zzzz
> 13: MAX TEMP[10].x, TEMP[5].xxxx, TEMP[9].xxxx
> 14: UMAD TEMP[11].x, IN[2].xxxx, IMM[0].xxxx, IMM[0].wwww
> 15: LOAD TEMP[12].x, BUFFER[8], TEMP[11].xxxx, RESTRICT
> 16: UMAD TEMP[13].x, IN[2].xxxx, IMM[0].xxxx, IMM[1].xxxx
> 17: LOAD TEMP[14].x, BUFFER[8], TEMP[13].xxxx, RESTRICT
> 18: FSGE TEMP[15].x, TEMP[10].xxxx, TEMP[12].xxxx
> 19: FSGE TEMP[16].x, OUT[0].wwww, TEMP[14].xxxx
> 20: OR TEMP[17].x, TEMP[15].xxxx, TEMP[16].xxxx
> 21: UIF TEMP[17].xxxx
> 22:   LOAD TEMP[18].x, CONSTBUF[1], IMM[1].yyyy
> 23:   UMAD TEMP[19].x, TEMP[18].xxxx, IMM[1].zzzz, IMM[1].wwww
> 24:   LOAD TEMP[20].xy, CONSTBUF[1], TEMP[19].xxxx
> 25:   MOV TEMP[21].xy, TEMP[20].xyxy
> 26:   F2I TEMP[22].xy, TEMP[0].xyyy
> 27:   ATOMUMAX TEMP[23].x, TEMP[21].xyxy, TEMP[22].xyxx, IN[1].xxxx, 2D
> 28: ENDIF
> 29: MUL OUT[0].xyz, TEMP[5].xyzz, OUT[0].wwww
> 30: END
>", }
>[1;33mconstant_buffer 0: [0m{buffer = NULL, buffer_offset = 0, buffer_size = 16, user_buffer = 0x7efba0021390, }
>[1;33mconstant_buffer 1: [0m{buffer = 0x7efba015b690, buffer_offset = 0, buffer_size = 4016, user_buffer = NULL, }
>  buffer: {target = buffer, format = PIPE_FORMAT_R8_UNORM, width0 = 4016, height0 = 1, depth0 = 1, array_size = 1, last_level = 0, nr_samples = 0, nr_storage_samples = 0, usage = 0, bind = 0, flags = 0, }
>[1;33mshader_buffer 8: [0m{buffer = 0x7efba0085d00, buffer_offset = 0, buffer_size = 2331648, }
>  buffer: {target = buffer, format = PIPE_FORMAT_R8_UNORM, width0 = 2331648, height0 = 1, depth0 = 1, array_size = 1, last_level = 0, nr_samples = 0, nr_storage_samples = 0, usage = 0, bind = 0, flags = 3, }
>[1;32mend shader: FRAGMENT[0m
>
>[1;33mdepth_stencil_alpha_state: [0m{depth = {enabled = 0, }, stencil = {{enabled = 0, }, {enabled = 0, }, }, alpha = {enabled = 0, }, }
>[1;33mstencil_ref: [0m{ref_value = {0, 0, }, }
>[1;33mblend_state: [0m{dither = 1, alpha_to_coverage = 0, alpha_to_one = 0, logicop_enable = 0, independent_blend_enable = 0, rt = {{blend_enable = 1, rgb_func = add, rgb_src_factor = one, rgb_dst_factor = inv_src_alpha, alpha_func = add, alpha_src_factor = one, alpha_dst_factor = inv_src_alpha, colormask = 15, }, }, }
>[1;33mblend_color: [0m{color = {0, 0, 0, 0, }, }
>[1;33mmin_samples[0m = 1
>[1;33msample_mask[0m = 0xffffffff
>
>[1;33mframebuffer_state: [0m{width = 232, height = 238, samples = 0, layers = 0, nr_cbufs = 1, cbufs = {0x7efba0ba6fe0, NULL, NULL, NULL, NULL, NULL, NULL, NULL, }, zsbuf = NULL, }
>  [1;33mcbufs[0]:[0m
>    [1;33msurface: [0m{format = PIPE_FORMAT_R16G16B16A16_FLOAT, width = 232, height = 238, texture = 0x7efba12d9c70, u.tex.level = 0, u.tex.first_layer = 0, u.tex.last_layer = 0, }
>    [1;33mresource: [0m{target = 2d, format = PIPE_FORMAT_R16G16B16A16_FLOAT, width0 = 232, height0 = 238, depth0 = 1, array_size = 1, last_level = 0, nr_samples = 0, nr_storage_samples = 0, usage = 0, bind = 10, flags = 4, }
>
>
>
>*****************************************************************************
>Context Log:
>
>------------------ IB begin ------------------
>c0044700 [1;32mEVENT_WRITE_EOP[0m:
>00000528         [1;33mVGT_EVENT_INITIATOR[0m <- EVENT_TYPE = BOTTOM_OF_PIPE_TS
>                 [1;33mEVENT_INDEX[0m <- 5
>                 [1;33mTCL1_VOL_ACTION_ENA[0m <- 0
>                 [1;33mTC_VOL_ACTION_ENA[0m <- 0
>                 [1;33mTC_WB_ACTION_ENA[0m <- 0
>                 [1;33mTCL1_ACTION_ENA[0m <- 0
>                 [1;33mTC_ACTION_ENA[0m <- 0
>00000400         [1;33mADDRESS_LO[0m <- 1024 (0x00000400)
>23000001         [1;33mADDRESS_HI[0m <- 0x23000001
>                 [1;33mDST_SEL[0m <- 0
>                 [1;33mINT_SEL[0m <- 3
>                 [1;33mDATA_SEL[0m <- 1
>00000000         [1;33mDATA_LO[0m <- 0
>00000000         [1;33mDATA_HI[0m <- 0
>c0044700 [1;32mEVENT_WRITE_EOP[0m:
>00000528         [1;33mVGT_EVENT_INITIATOR[0m <- EVENT_TYPE = BOTTOM_OF_PIPE_TS
>                 [1;33mEVENT_INDEX[0m <- 5
>                 [1;33mTCL1_VOL_ACTION_ENA[0m <- 0
>                 [1;33mTC_VOL_ACTION_ENA[0m <- 0
>                 [1;33mTC_WB_ACTION_ENA[0m <- 0
>                 [1;33mTCL1_ACTION_ENA[0m <- 0
>                 [1;33mTC_ACTION_ENA[0m <- 0
>001c57bc         [1;33mADDRESS_LO[0m <- 0x001c57bc
>23000001         [1;33mADDRESS_HI[0m <- 0x23000001
>                 [1;33mDST_SEL[0m <- 0
>                 [1;33mINT_SEL[0m <- 3
>                 [1;33mDATA_SEL[0m <- 1
>80000000         [1;33mDATA_LO[0m <- -0.0f (0x80000000)
>00000000         [1;33mDATA_HI[0m <- 0
>c0055000 [1;32mDMA_DATA[0m:
>80000000         [1;33mDMA_DATA_WORD0[0m <- CP_SYNC = 1
>                                   SRC_SEL = SRC_ADDR
>                                   DST_SEL = DST_ADDR
>                                   ENGINE = ME
>00000000         [1;33mSRC_ADDR_LO[0m <- 0
>00000000         [1;33mSRC_ADDR_HI[0m <- 0
>00000000         [1;33mDST_ADDR_LO[0m <- 0
>00000000         [1;33mDST_ADDR_HI[0m <- 0
>00000000         [1;33mCOMMAND[0m <- BYTE_COUNT_GFX6 = 0
>                            BYTE_COUNT_GFX9 = 0
>                            DISABLE_WR_CONFIRM_GFX6 = 0
>                            SRC_SWAP = NONE
>                            DST_SWAP = NONE
>                            SAS = MEMORY
>                            DAS = MEMORY
>                            SAIC = INCREMENT
>                            DAIC = INCREMENT
>                            RAW_WAIT = 0
>                            DISABLE_WR_CONFIRM_GFX9 = 0
>c0004600 [1;32mEVENT_WRITE[0m:
>00000410         [1;33mVGT_EVENT_INITIATOR[0m <- EVENT_TYPE = PS_PARTIAL_FLUSH
>                 [1;33mEVENT_INDEX[0m <- 4
>                 [1;33mINV_L2[0m <- 0
>c0004200 [1;32mPFP_SYNC_ME[0m:
>00000000 
>c0033700 [1;32mWRITE_DATA[0m:
>00100100         [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                            WR_CONFIRM = 1
>                            WR_ONE_ADDR = 0
>                            DST_SEL = MEMORY_SYNC
>00064a00         [1;33mDST_ADDR_LO[0m <- 0x00064a00
>00000001         [1;33mDST_ADDR_HI[0m <- 1
>00000003 
>c0001000 [1;32mNOP[0m:
>                 [31mTrace point ID: 3
>                 [31m!!!!! This is the last trace point that was reached by the CP !!!!![0m
>cafe0003 
>------------------- IB end -------------------
>
>Flushing. Time: 332.014285s
>
>Buffer list (in units of pages = 4kB):
>[1;33m        Size    VM start page         VM end page           Usage[0m
>          32    0x0000000000100       0x0000000000120       SHADER_RINGS
>         512    -- hole --
>          32    0x0000000000320       0x0000000000340       CONST_BUFFER
>          32    0x0000000000340       0x0000000000360       DESCRIPTORS
>        4544    -- hole --
>          32    0x0000000001520       0x0000000001540       DESCRIPTORS, SHADER_RINGS
>     1043136    -- hole --
>          32    0x0000000100000       0x0000000100020       QUERY, IB2, SHADER_BINARY
>          32    0x0000000100020       0x0000000100040       IB1
>          32    0x0000000100040       0x0000000100060       BORDER_COLORS
>          32    0x0000000100060       0x0000000100080       TRACE
>         320    -- hole --
>          32    0x00000001001C0       0x00000001001E0       QUERY
>        7168    -- hole --
>          32    0x0000000101DE0       0x0000000101E00       SHADER_BINARY
>         832    -- hole --
>          32    0x0000000102140       0x0000000102160       SAMPLER_TEXTURE
>          32    -- hole --
>          32    0x0000000102180       0x00000001021A0       SAMPLER_TEXTURE
>          32    -- hole --
>          32    0x00000001021C0       0x00000001021E0       SAMPLER_TEXTURE
>          32    -- hole --
>         514    0x0000000102200       0x0000000102402       SAMPLER_TEXTURE
>         425    -- hole --
>          17    0x00000001025AB       0x00000001025BC       SAMPLER_TEXTURE
>           4    -- hole --
>          32    0x00000001025C0       0x00000001025E0       SAMPLER_TEXTURE
>         273    0x00000001025E0       0x00000001026F1       SAMPLER_TEXTURE
>         297    -- hole --
>          17    0x000000010281A       0x000000010282B       SAMPLER_TEXTURE
>          20    -- hole --
>          17    0x000000010283F       0x0000000102850       SAMPLER_TEXTURE
>          20    -- hole --
>          17    0x0000000102864       0x0000000102875       SAMPLER_TEXTURE
>          20    -- hole --
>          17    0x0000000102889       0x000000010289A       SAMPLER_TEXTURE
>          20    -- hole --
>          17    0x00000001028AE       0x00000001028BF       SAMPLER_TEXTURE
>          20    -- hole --
>          17    0x00000001028D3       0x00000001028E4       SAMPLER_TEXTURE
>          20    -- hole --
>          17    0x00000001028F8       0x0000000102909       SAMPLER_TEXTURE
>          20    -- hole --
>          17    0x000000010291D       0x000000010292E       SAMPLER_TEXTURE
>          20    -- hole --
>          17    0x0000000102942       0x0000000102953       SAMPLER_TEXTURE
>          20    -- hole --
>          17    0x0000000102967       0x0000000102978       SAMPLER_TEXTURE
>          20    -- hole --
>          17    0x000000010298C       0x000000010299D       SAMPLER_TEXTURE
>          20    -- hole --
>          17    0x00000001029B1       0x00000001029C2       SAMPLER_TEXTURE
>          20    -- hole --
>          17    0x00000001029D6       0x00000001029E7       SAMPLER_TEXTURE
>          25    -- hole --
>         579    0x0000000102A00       0x0000000102C43       SAMPLER_TEXTURE
>          17    0x0000000102C43       0x0000000102C54       SAMPLER_TEXTURE
>          20    -- hole --
>          17    0x0000000102C68       0x0000000102C79       SAMPLER_TEXTURE
>          20    -- hole --
>          17    0x0000000102C8D       0x0000000102C9E       SAMPLER_TEXTURE
>          20    -- hole --
>          17    0x0000000102CB2       0x0000000102CC3       SAMPLER_TEXTURE
>          61    -- hole --
>          65    0x0000000102D00       0x0000000102D41       SAMPLER_TEXTURE
>        5375    -- hole --
>         129    0x0000000104240       0x00000001042C1       SAMPLER_TEXTURE
>          15    -- hole --
>         129    0x00000001042D0       0x0000000104351       SAMPLER_TEXTURE
>          15    -- hole --
>         129    0x0000000104360       0x00000001043E1       SAMPLER_TEXTURE
>          31    -- hole --
>        2169    0x0000000104400       0x0000000104C79       SAMPLER_TEXTURE
>           7    -- hole --
>         129    0x0000000104C80       0x0000000104D01       SAMPLER_TEXTURE
>          15    -- hole --
>         129    0x0000000104D10       0x0000000104D91       SAMPLER_TEXTURE
>         256    0x0000000104D91       0x0000000104E91       CP_DMA
>       16815    -- hole --
>         190    0x0000000109040       0x00000001090FE       VERTEX_BUFFER
>          95    0x00000001090FE       0x000000010915D       DRAW_INDIRECT
>          35    -- hole --
>          32    0x0000000109180       0x00000001091A0       CP_DMA, CONST_BUFFER
>        2144    -- hole --
>        2169    0x0000000109A00       0x000000010A279       SAMPLER_TEXTURE
>         384    0x000000010A279       0x000000010A3F9       SHADER_RINGS
>        2055    -- hole --
>        2169    0x000000010AC00       0x000000010B479       SAMPLER_TEXTURE
>        2439    -- hole --
>        2169    0x000000010BE00       0x000000010C679       SAMPLER_TEXTURE
>       69511    -- hole --
>         570    0x000000011D600       0x000000011D83A       SHADER_RW_BUFFER
>         454    -- hole --
>        2304    0x000000011DA00       0x000000011E300       VERTEX_BUFFER
>          32    0x000000011E300       0x000000011E320       SAMPLER_TEXTURE
>          32    -- hole --
>          32    0x000000011E340       0x000000011E360       SAMPLER_TEXTURE
>          32    0x000000011E360       0x000000011E380       SAMPLER_TEXTURE
>          79    -- hole --
>          40    0x000000011E3CF       0x000000011E3F7       SAMPLER_TEXTURE
>           9    -- hole --
>         768    0x000000011E400       0x000000011E700       SHADER_RW_BUFFER
>        2848    -- hole --
>         432    0x000000011F220       0x000000011F3D0       SHADER_RW_BUFFER
>          16    -- hole --
>          32    0x000000011F3E0       0x000000011F400       SAMPLER_TEXTURE
>        3600    -- hole --
>         257    0x0000000120210       0x0000000120311       SAMPLER_TEXTURE
>          15    -- hole --
>         193    0x0000000120320       0x00000001203E1       SAMPLER_TEXTURE
>          31    -- hole --
>        2169    0x0000000120400       0x0000000120C79       SAMPLER_TEXTURE
>         327    -- hole --
>          32    0x0000000120DC0       0x0000000120DE0       SAMPLER_TEXTURE
>          32    0x0000000120DE0       0x0000000120E00       SAMPLER_TEXTURE
>        7312    -- hole --
>         257    0x0000000122A90       0x0000000122B91       SAMPLER_TEXTURE
>         106    0x0000000122B91       0x0000000122BFB       SAMPLER_TEXTURE
>           5    -- hole --
>         643    0x0000000122C00       0x0000000122E83       SAMPLER_TEXTURE
>         356    -- hole --
>          21    0x0000000122FE7       0x0000000122FFC       SAMPLER_TEXTURE
>        1839    -- hole --
>         106    0x000000012372B       0x0000000123795       SAMPLER_TEXTURE
>          11    -- hole --
>          32    0x00000001237A0       0x00000001237C0       SAMPLER_TEXTURE
>          32    0x00000001237C0       0x00000001237E0       SAMPLER_TEXTURE
>        4480    -- hole --
>          32    0x0000000124960       0x0000000124980       SAMPLER_TEXTURE
>          32    -- hole --
>          32    0x00000001249A0       0x00000001249C0       SAMPLER_TEXTURE
>          64    -- hole --
>        2169    0x0000000124A00       0x0000000125279       SAMPLER_TEXTURE
>          39    -- hole --
>         322    0x00000001252A0       0x00000001253E2       SAMPLER_TEXTURE
>          30    0x00000001253E2       0x0000000125400       SAMPLER_TEXTURE
>        4337    -- hole --
>          74    0x00000001264F1       0x000000012653B       SAMPLER_TEXTURE
>          75    0x000000012653B       0x0000000126586       SAMPLER_TEXTURE
>          90    -- hole --
>          32    0x00000001265E0       0x0000000126600       SAMPLER_TEXTURE
>        2025    -- hole --
>          21    0x0000000126DE9       0x0000000126DFE       SAMPLER_TEXTURE
>        1218    -- hole --
>         241    0x00000001272C0       0x00000001273B1       SAMPLER_TEXTURE
>          47    -- hole --
>          32    0x00000001273E0       0x0000000127400       SAMPLER_TEXTURE
>         643    0x0000000127400       0x0000000127683       SAMPLER_TEXTURE
>        2093    -- hole --
>         241    0x0000000127EB0       0x0000000127FA1       SAMPLER_TEXTURE
>          81    0x0000000127FA1       0x0000000127FF2       SAMPLER_TEXTURE
>        2574    -- hole --
>        1028    0x0000000128A00       0x0000000128E04       SAMPLER_TEXTURE
>         398    -- hole --
>          74    0x0000000128F92       0x0000000128FDC       SAMPLER_TEXTURE
>          35    0x0000000128FDC       0x0000000128FFF       SAMPLER_TEXTURE
>        2065    -- hole --
>         402    0x0000000129810       0x00000001299A2       SAMPLER_TEXTURE
>        1646    -- hole --
>         402    0x000000012A010       0x000000012A1A2       SAMPLER_TEXTURE
>          75    0x000000012A1A2       0x000000012A1ED       SAMPLER_TEXTURE
>         547    -- hole --
>         322    0x000000012A410       0x000000012A552       SAMPLER_TEXTURE
>          80    -- hole --
>          37    0x000000012A5A2       0x000000012A5C7       SAMPLER_TEXTURE
>          38    0x000000012A5C7       0x000000012A5ED       SAMPLER_TEXTURE
>        2552    -- hole --
>          21    0x000000012AFE5       0x000000012AFFA       SAMPLER_TEXTURE
>           6    -- hole --
>        1028    0x000000012B000       0x000000012B404       SAMPLER_TEXTURE
>          12    -- hole --
>         241    0x000000012B410       0x000000012B501       SAMPLER_TEXTURE
>        2319    -- hole --
>         241    0x000000012BE10       0x000000012BF01       SAMPLER_TEXTURE
>          15    -- hole --
>         145    0x000000012BF10       0x000000012BFA1       SAMPLER_TEXTURE
>        1087    -- hole --
>          32    0x000000012C3E0       0x000000012C400       SAMPLER_TEXTURE
>         640    -- hole --
>         145    0x000000012C680       0x000000012C711       SAMPLER_TEXTURE
>         111    -- hole --
>          97    0x000000012C780       0x000000012C7E1       SAMPLER_TEXTURE
>         559    -- hole --
>          97    0x000000012CA10       0x000000012CA71       SAMPLER_TEXTURE
>          15    -- hole --
>         241    0x000000012CA80       0x000000012CB71       SAMPLER_TEXTURE
>        1679    -- hole --
>         771    0x000000012D200       0x000000012D503       SAMPLER_TEXTURE
>         221    -- hole --
>          32    0x000000012D5E0       0x000000012D600       SAMPLER_TEXTURE
>        1414    -- hole --
>          37    0x000000012DB86       0x000000012DBAB       SAMPLER_TEXTURE
>          42    -- hole --
>          38    0x000000012DBD5       0x000000012DBFB       SAMPLER_TEXTURE
>         693    -- hole --
>         145    0x000000012DEB0       0x000000012DF41       SAMPLER_TEXTURE
>          15    -- hole --
>         145    0x000000012DF50       0x000000012DFE1       SAMPLER_TEXTURE
>          21    0x000000012DFE1       0x000000012DFF6       SAMPLER_TEXTURE
>        1082    -- hole --
>          97    0x000000012E430       0x000000012E491       SAMPLER_TEXTURE
>          79    -- hole --
>          97    0x000000012E4E0       0x000000012E541       SAMPLER_TEXTURE
>        1215    -- hole --
>         643    0x000000012EA00       0x000000012EC83       SAMPLER_TEXTURE
>          13    -- hole --
>         241    0x000000012EC90       0x000000012ED81       SAMPLER_TEXTURE
>         911    -- hole --
>         145    0x000000012F110       0x000000012F1A1       SAMPLER_TEXTURE
>          37    0x000000012F1A1       0x000000012F1C6       SAMPLER_TEXTURE
>          58    -- hole --
>         643    0x000000012F200       0x000000012F483       SAMPLER_TEXTURE
>          13    -- hole --
>         145    0x000000012F490       0x000000012F521       SAMPLER_TEXTURE
>          38    0x000000012F521       0x000000012F547       SAMPLER_TEXTURE
>          57    -- hole --
>          97    0x000000012F580       0x000000012F5E1       SAMPLER_TEXTURE
>         671    -- hole --
>          97    0x000000012F880       0x000000012F8E1       SAMPLER_TEXTURE
>          79    -- hole --
>         241    0x000000012F930       0x000000012FA21       SAMPLER_TEXTURE
>         223    -- hole --
>         145    0x000000012FB00       0x000000012FB91       SAMPLER_TEXTURE
>         127    -- hole --
>         145    0x000000012FC10       0x000000012FCA1       SAMPLER_TEXTURE
>         111    -- hole --
>          37    0x000000012FD10       0x000000012FD35       SAMPLER_TEXTURE
>          42    -- hole --
>          38    0x000000012FD5F       0x000000012FD85       SAMPLER_TEXTURE
>          43    -- hole --
>          97    0x000000012FDB0       0x000000012FE11       SAMPLER_TEXTURE
>          79    -- hole --
>          97    0x000000012FE60       0x000000012FEC1       SAMPLER_TEXTURE
>          79    -- hole --
>         241    0x000000012FF10       0x0000000130001       SAMPLER_TEXTURE
>         223    -- hole --
>         145    0x00000001300E0       0x0000000130171       SAMPLER_TEXTURE
>         143    -- hole --
>          32    0x0000000130200       0x0000000130220       SAMPLER_TEXTURE
>          32    -- hole --
>         145    0x0000000130240       0x00000001302D1       SAMPLER_TEXTURE
>         111    -- hole --
>          37    0x0000000130340       0x0000000130365       SAMPLER_TEXTURE
>          42    -- hole --
>          38    0x000000013038F       0x00000001303B5       SAMPLER_TEXTURE
>          43    -- hole --
>          97    0x00000001303E0       0x0000000130441       SAMPLER_TEXTURE
>          79    -- hole --
>          97    0x0000000130490       0x00000001304F1       SAMPLER_TEXTURE
>          79    -- hole --
>          32    0x0000000130540       0x0000000130560       SAMPLER_TEXTURE
>         241    0x0000000130560       0x0000000130651       SAMPLER_TEXTURE
>         223    -- hole --
>         145    0x0000000130730       0x00000001307C1       SAMPLER_TEXTURE
>         127    -- hole --
>         145    0x0000000130840       0x00000001308D1       SAMPLER_TEXTURE
>         111    -- hole --
>          37    0x0000000130940       0x0000000130965       SAMPLER_TEXTURE
>          42    -- hole --
>          38    0x000000013098F       0x00000001309B5       SAMPLER_TEXTURE
>          43    -- hole --
>          97    0x00000001309E0       0x0000000130A41       SAMPLER_TEXTURE
>          79    -- hole --
>          97    0x0000000130A90       0x0000000130AF1       SAMPLER_TEXTURE
>          79    -- hole --
>         241    0x0000000130B40       0x0000000130C31       SAMPLER_TEXTURE
>         271    -- hole --
>          32    0x0000000130D40       0x0000000130D60       SAMPLER_TEXTURE
>          64    -- hole --
>          32    0x0000000130DA0       0x0000000130DC0       SAMPLER_TEXTURE
>          64    -- hole --
>        2169    0x0000000130E00       0x0000000131679       SAMPLER_TEXTURE
>          47    0x0000000131679       0x00000001316A8       SAMPLER_TEXTURE
>          48    -- hole --
>          56    0x00000001316D8       0x0000000131710       SAMPLER_TEXTURE
>          57    -- hole --
>          56    0x0000000131749       0x0000000131781       SAMPLER_TEXTURE
>          57    -- hole --
>          56    0x00000001317BA       0x00000001317F2       SAMPLER_TEXTURE
>          14    -- hole --
>         723    0x0000000131800       0x0000000131AD3       SAMPLER_TEXTURE
>          57    -- hole --
>          56    0x0000000131B0C       0x0000000131B44       SAMPLER_TEXTURE
>          57    -- hole --
>          56    0x0000000131B7D       0x0000000131BB5       SAMPLER_TEXTURE
>         683    -- hole --
>          56    0x0000000131E60       0x0000000131E98       SAMPLER_TEXTURE
>          57    -- hole --
>          56    0x0000000131ED1       0x0000000131F09       SAMPLER_TEXTURE
>          57    -- hole --
>          56    0x0000000131F42       0x0000000131F7A       SAMPLER_TEXTURE
>          57    -- hole --
>         107    0x0000000131FB3       0x000000013201E       SAMPLER_TEXTURE
>         110    -- hole --
>         104    0x000000013208C       0x00000001320F4       SAMPLER_TEXTURE
>         124    -- hole --
>          65    0x0000000132170       0x00000001321B1       SAMPLER_TEXTURE
>          60    -- hole --
>          34    0x00000001321ED       0x000000013220F       SAMPLER_TEXTURE
>          34    -- hole --
>          36    0x0000000132231       0x0000000132255       SAMPLER_TEXTURE
>          69    -- hole --
>          21    0x000000013229A       0x00000001322AF       SAMPLER_TEXTURE
>          25    -- hole --
>          21    0x00000001322C8       0x00000001322DD       SAMPLER_TEXTURE
>          25    -- hole --
>          21    0x00000001322F6       0x000000013230B       SAMPLER_TEXTURE
>          25    -- hole --
>          21    0x0000000132324       0x0000000132339       SAMPLER_TEXTURE
>          25    -- hole --
>          21    0x0000000132352       0x0000000132367       SAMPLER_TEXTURE
>          25    -- hole --
>          21    0x0000000132380       0x0000000132395       SAMPLER_TEXTURE
>          25    -- hole --
>          21    0x00000001323AE       0x00000001323C3       SAMPLER_TEXTURE
>          25    -- hole --
>          21    0x00000001323DC       0x00000001323F1       SAMPLER_TEXTURE
>          25    -- hole --
>          21    0x000000013240A       0x000000013241F       SAMPLER_TEXTURE
>          25    -- hole --
>          21    0x0000000132438       0x000000013244D       SAMPLER_TEXTURE
>          25    -- hole --
>          26    0x0000000132466       0x0000000132480       SAMPLER_TEXTURE
>          32    0x0000000132480       0x00000001324A0       SAMPLER_TEXTURE
>          32    -- hole --
>          32    0x00000001324C0       0x00000001324E0       SAMPLER_TEXTURE
>          32    -- hole --
>          32    0x0000000132500       0x0000000132520       SAMPLER_TEXTURE
>          32    -- hole --
>          32    0x0000000132540       0x0000000132560       SAMPLER_TEXTURE
>          32    -- hole --
>          32    0x0000000132580       0x00000001325A0       SAMPLER_TEXTURE
>          32    -- hole --
>          32    0x00000001325C0       0x00000001325E0       SAMPLER_TEXTURE
>          32    -- hole --
>          32    0x0000000132600       0x0000000132620       SAMPLER_TEXTURE
>          32    -- hole --
>          32    0x0000000132640       0x0000000132660       SAMPLER_TEXTURE
>         402    0x0000000132660       0x00000001327F2       SAMPLER_TEXTURE
>         423    -- hole --
>          26    0x0000000132999       0x00000001329B3       SAMPLER_TEXTURE
>          31    -- hole --
>          26    0x00000001329D2       0x00000001329EC       SAMPLER_TEXTURE
>          84    -- hole --
>          32    0x0000000132A40       0x0000000132A60       SAMPLER_TEXTURE
>          32    -- hole --
>          32    0x0000000132A80       0x0000000132AA0       SAMPLER_TEXTURE
>          32    -- hole --
>          32    0x0000000132AC0       0x0000000132AE0       SAMPLER_TEXTURE
>          32    -- hole --
>          32    0x0000000132B00       0x0000000132B20       SAMPLER_TEXTURE
>          32    -- hole --
>          32    0x0000000132B40       0x0000000132B60       SAMPLER_TEXTURE
>          32    -- hole --
>          32    0x0000000132B80       0x0000000132BA0       SAMPLER_TEXTURE
>          32    -- hole --
>          32    0x0000000132BC0       0x0000000132BE0       SAMPLER_TEXTURE
>          32    -- hole --
>          32    0x0000000132C00       0x0000000132C20       SAMPLER_TEXTURE
>          32    -- hole --
>          32    0x0000000132C40       0x0000000132C60       SAMPLER_TEXTURE
>         113    0x0000000132C60       0x0000000132CD1       SAMPLER_TEXTURE
>         143    -- hole --
>          32    0x0000000132D60       0x0000000132D80       SAMPLER_TEXTURE
>         148    0x0000000132D80       0x0000000132E14       SAMPLER_TEXTURE
>         146    -- hole --
>         123    0x0000000132EA6       0x0000000132F21       SAMPLER_TEXTURE
>         223    -- hole --
>         900    0x0000000133000       0x0000000133384       SAMPLER_TEXTURE
>         124    -- hole --
>        2169    0x0000000133400       0x0000000133C79       SAMPLER_TEXTURE
>        2439    -- hole --
>        2169    0x0000000134600       0x0000000134E79       SAMPLER_TEXTURE
>        2439    -- hole --
>        9472    0x0000000135800       0x0000000137D00       SHADER_RINGS
>        2816    -- hole --
>        2160    0x0000000138800       0x0000000139070       COLOR_BUFFER
>
>Note: The holes represent memory not used by the IB.
>      Other buffers can still be allocated there.
>
>------------------ IB2: Init config begin ------------------
>c0012800 [1;32mCONTEXT_CONTROL[0m:
>80000000 
>80000000 
>c0001200 [1;32mCLEAR_STATE[0m:
>00000000 
>c0026900 [1;36mSET_CONTEXT_REG[1;36m:
>000000d4 
>16000012         [1;33mPA_SC_RASTER_CONFIG[0m <- RB_MAP_PKR0 = RASTER_CONFIG_RB_MAP_2
>                                        RB_MAP_PKR1 = RASTER_CONFIG_RB_MAP_0
>                                        RB_XSEL2 = RASTER_CONFIG_RB_XSEL2_1
>                                        RB_XSEL = 0
>                                        RB_YSEL = 0
>                                        PKR_MAP = RASTER_CONFIG_PKR_MAP_0
>                                        PKR_XSEL = RASTER_CONFIG_PKR_XSEL_0
>                                        PKR_YSEL = RASTER_CONFIG_PKR_YSEL_0
>                                        PKR_XSEL2 = RASTER_CONFIG_PKR_XSEL2_0
>                                        SC_MAP = RASTER_CONFIG_SC_MAP_0
>                                        SC_XSEL = RASTER_CONFIG_SC_XSEL_8_WIDE_TILE
>                                        SC_YSEL = RASTER_CONFIG_SC_YSEL_8_WIDE_TILE
>                                        SE_MAP = RASTER_CONFIG_SE_MAP_2
>                                        SE_XSEL_GFX6 = RASTER_CONFIG_SE_XSEL_16_WIDE_TILE
>                                        SE_YSEL_GFX6 = RASTER_CONFIG_SE_YSEL_16_WIDE_TILE
>00000000         [1;33mPA_SC_RASTER_CONFIG_1[0m <- SE_PAIR_MAP = RASTER_CONFIG_SE_PAIR_MAP_0
>                                          SE_PAIR_XSEL_GFX6 = RASTER_CONFIG_SE_PAIR_XSEL_8_WIDE_TILE
>                                          SE_PAIR_YSEL_GFX6 = RASTER_CONFIG_SE_PAIR_YSEL_8_WIDE_TILE
>c0016900 [1;36mSET_CONTEXT_REG[1;36m:
>00000286 
>42800000         [1;33mVGT_HOS_MAX_TESS_LEVEL[0m <- 64.0f (0x42800000)
>c0026900 [1;36mSET_CONTEXT_REG[1;36m:
>00000295 
>00000080         [1;33mVGT_GS_PER_ES[0m <- GS_PER_ES = 128 (0x80)
>00000040         [1;33mVGT_ES_PER_GS[0m <- ES_PER_GS = 64 (0x40)
>c0016900 [1;36mSET_CONTEXT_REG[1;36m:
>000002a8 
>00000001         [1;33mVGT_INSTANCE_STEP_RATE_0[0m <- 1
>c0036900 [1;36mSET_CONTEXT_REG[1;36m:
>00000100 
>ffffffff         [1;33mVGT_MAX_VTX_INDX[0m <- 0xffffffff
>00000000         [1;33mVGT_MIN_VTX_INDX[0m <- 0
>00000000         [1;33mVGT_INDX_OFFSET[0m <- 0
>c0017600 [1;36mSET_SH_REG[1;36m:
>00000147 
>003fffff         [1;33mSPI_SHADER_PGM_RSRC3_LS[0m <- CU_EN = 0xffff
>                                            WAVE_LIMIT = 63 (0x3f)
>                                            LOCK_LOW_THRESHOLD = 0
>                                            GROUP_FIFO_DEPTH = 0
>c0017600 [1;36mSET_SH_REG[1;36m:
>00000107 
>0000003f         [1;33mSPI_SHADER_PGM_RSRC3_HS[0m <- WAVE_LIMIT = 63 (0x3f)
>                                            LOCK_LOW_THRESHOLD = 0
>                                            GROUP_FIFO_DEPTH = 0
>c0017600 [1;36mSET_SH_REG[1;36m:
>000000c7 
>003fffff         [1;33mSPI_SHADER_PGM_RSRC3_ES[0m <- CU_EN = 0xffff
>                                            WAVE_LIMIT = 63 (0x3f)
>                                            LOCK_LOW_THRESHOLD = 0
>                                            GROUP_FIFO_DEPTH = 0
>c0016900 [1;36mSET_CONTEXT_REG[1;36m:
>00000291 
>00002040         [1;33mVGT_GS_ONCHIP_CNTL[0m <- ES_VERTS_PER_SUBGRP = 64 (0x40)
>                                       GS_PRIMS_PER_SUBGRP = 4
>c0017600 [1;36mSET_SH_REG[1;36m:
>00000087 
>003fffff         [1;33mSPI_SHADER_PGM_RSRC3_GS[0m <- CU_EN = 0xffff
>                                            WAVE_LIMIT = 63 (0x3f)
>                                            LOCK_LOW_THRESHOLD = 0
>                                            GROUP_FIFO_DEPTH = 0
>c0027600 [1;36mSET_SH_REG[1;36m:
>00000046 
>003ffffe         [1;33mSPI_SHADER_PGM_RSRC3_VS[0m <- CU_EN = 0xfffe
>                                            WAVE_LIMIT = 63 (0x3f)
>                                            LOCK_LOW_THRESHOLD = 0
>00000013         [1;33mSPI_SHADER_LATE_ALLOC_VS[0m <- LIMIT = 19 (0x13)
>c0017600 [1;36mSET_SH_REG[1;36m:
>00000007 
>003fffff         [1;33mSPI_SHADER_PGM_RSRC3_PS[0m <- CU_EN = 0xffff
>                                            WAVE_LIMIT = 63 (0x3f)
>                                            LOCK_LOW_THRESHOLD = 0
>c0016900 [1;36mSET_CONTEXT_REG[1;36m:
>000002d4 
>700b0b20         [1;33mVGT_TESS_DISTRIBUTION[0m <- ACCUM_ISOLINE = 32 (0x20)
>                                          ACCUM_TRI = 11 (0x0b)
>                                          ACCUM_QUAD = 11 (0x0b)
>                                          DONUT_SPLIT = 16 (0x10)
>                                          TRAP_SPLIT = 3
>c0026900 [1;36mSET_CONTEXT_REG[1;36m:
>00000020 
>01000500         [1;33mTA_BC_BASE_ADDR[0m <- 0x01000500
>00000000         [1;33mTA_BC_BASE_ADDR_HI[0m <- ADDRESS = 0
>c0004600 [1;32mEVENT_WRITE[0m:
>0000040f         [1;33mVGT_EVENT_INITIATOR[0m <- EVENT_TYPE = VS_PARTIAL_FLUSH
>                 [1;33mEVENT_INDEX[0m <- 4
>                 [1;33mINV_L2[0m <- 0
>c0004600 [1;32mEVENT_WRITE[0m:
>00000024         [1;33mVGT_EVENT_INITIATOR[0m <- EVENT_TYPE = VGT_FLUSH
>                 [1;33mEVENT_INDEX[0m <- 0
>                 [1;33mINV_L2[0m <- 0
>         
>------------------- IB2: Init config end -------------------
>
>------------------ IB2: Init GS rings begin ------------------
>c0027900 [1;36mSET_UCONFIG_REG[1;36m:
>00000240 
>00001800         [1;33mVGT_ESGS_RING_SIZE[0m <- 6144 (0x00001800)
>00025000         [1;33mVGT_GSVS_RING_SIZE[0m <- 0x00025000
>         
>------------------- IB2: Init GS rings end -------------------
>
>------------------ IB begin ------------------
>c0033700 [1;32mWRITE_DATA[0m:
>00100100         [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                            WR_CONFIRM = 1
>                            WR_ONE_ADDR = 0
>                            DST_SEL = MEMORY_SYNC
>00065000         [1;33mDST_ADDR_LO[0m <- 0x00065000
>00000001         [1;33mDST_ADDR_HI[0m <- 1
>00000001 
>c0001000 [1;32mNOP[0m:
>                 [31mTrace point ID: 1
>                 [31mThis trace point was reached by the CP.[0m
>cafe0001 
>------------------- IB end -------------------
>
>------------------ IB begin ------------------
>c0023f00 [1;32mINDIRECT_BUFFER_CIK[0m:
>00002800         [1;33mIB_BASE_LO[0m <- 10240 (0x00002800)
>00000001         [1;33mIB_BASE_HI[0m <- 1
>00000040         [1;33mCONTROL[0m <- IB_SIZE = 64 (0x00040)
>                            CHAIN = 0
>                            VALID = 0
>c0027900 [1;36mSET_UCONFIG_REG[1;36m:
>00000240 
>00001800         [1;33mVGT_ESGS_RING_SIZE[0m <- 6144 (0x00001800)
>00025000         [1;33mVGT_GSVS_RING_SIZE[0m <- 0x00025000
>c0004600 [1;32mEVENT_WRITE[0m:
>00000410         [1;33mVGT_EVENT_INITIATOR[0m <- EVENT_TYPE = PS_PARTIAL_FLUSH
>                 [1;33mEVENT_INDEX[0m <- 4
>                 [1;33mINV_L2[0m <- 0
>c0004200 [1;32mPFP_SYNC_ME[0m:
>00000000 
>c0034300 [1;32mSURFACE_SYNC[0m:
>28c40000         [1;33mCP_COHER_CNTL[0m <- DEST_BASE_0_ENA = 0
>                                  DEST_BASE_1_ENA = 0
>                                  TC_SD_ACTION_ENA = 0
>                                  TC_NC_ACTION_ENA = 0
>                                  CB0_DEST_BASE_ENA = 0
>                                  CB1_DEST_BASE_ENA = 0
>                                  CB2_DEST_BASE_ENA = 0
>                                  CB3_DEST_BASE_ENA = 0
>                                  CB4_DEST_BASE_ENA = 0
>                                  CB5_DEST_BASE_ENA = 0
>                                  CB6_DEST_BASE_ENA = 0
>                                  CB7_DEST_BASE_ENA = 0
>                                  DB_DEST_BASE_ENA = 0
>                                  TCL1_VOL_ACTION_ENA = 0
>                                  TC_VOL_ACTION_ENA = 0
>                                  TC_WB_ACTION_ENA = 1
>                                  DEST_BASE_2_ENA = 0
>                                  DEST_BASE_3_ENA = 0
>                                  TCL1_ACTION_ENA = 1
>                                  TC_ACTION_ENA = 1
>                                  CB_ACTION_ENA = 0
>                                  DB_ACTION_ENA = 0
>                                  SH_KCACHE_ACTION_ENA = 1
>                                  SH_KCACHE_VOL_ACTION_ENA = 0
>                                  SH_ICACHE_ACTION_ENA = 1
>                                  SH_KCACHE_WB_ACTION_ENA = 0
>                                  SH_SD_ACTION_ENA = 0
>ffffffff         [1;33mCP_COHER_SIZE[0m <- 0xffffffff
>00000000         [1;33mCP_COHER_BASE[0m <- 0
>0000000a         [1;33mPOLL_INTERVAL[0m <- 10 (0x000a)
>c0004600 [1;32mEVENT_WRITE[0m:
>00000019         [1;33mVGT_EVENT_INITIATOR[0m <- EVENT_TYPE = PIPELINESTAT_START
>                 [1;33mEVENT_INDEX[0m <- 0
>                 [1;33mINV_L2[0m <- 0
>c0055000 [1;32mDMA_DATA[0m:
>e0300000         [1;33mDMA_DATA_WORD0[0m <- CP_SYNC = 1
>                                   SRC_SEL = SRC_ADDR_TC_L2
>                                   DST_SEL = DST_ADDR_TC_L2
>                                   ENGINE = ME
>04d9b780         [1;33mSRC_ADDR_LO[0m <- 0x04d9b780
>00000001         [1;33mSRC_ADDR_HI[0m <- 1
>09182000         [1;33mDST_ADDR_LO[0m <- 0x09182000
>00000001         [1;33mDST_ADDR_HI[0m <- 1
>40000004         [1;33mCOMMAND[0m <- BYTE_COUNT_GFX6 = 4
>                            BYTE_COUNT_GFX9 = 4
>                            DISABLE_WR_CONFIRM_GFX6 = 0
>                            SRC_SWAP = NONE
>                            DST_SWAP = NONE
>                            SAS = MEMORY
>                            DAS = MEMORY
>                            SAIC = INCREMENT
>                            DAIC = INCREMENT
>                            RAW_WAIT = 1
>                            DISABLE_WR_CONFIRM_GFX9 = 0
>c0004200 [1;32mPFP_SYNC_ME[0m:
>00000000 
>c0004600 [1;32mEVENT_WRITE[0m:
>00000410         [1;33mVGT_EVENT_INITIATOR[0m <- EVENT_TYPE = PS_PARTIAL_FLUSH
>                 [1;33mEVENT_INDEX[0m <- 4
>                 [1;33mINV_L2[0m <- 0
>c0004200 [1;32mPFP_SYNC_ME[0m:
>00000000 
>c0034300 [1;32mSURFACE_SYNC[0m:
>08400000         [1;33mCP_COHER_CNTL[0m <- DEST_BASE_0_ENA = 0
>                                  DEST_BASE_1_ENA = 0
>                                  TC_SD_ACTION_ENA = 0
>                                  TC_NC_ACTION_ENA = 0
>                                  CB0_DEST_BASE_ENA = 0
>                                  CB1_DEST_BASE_ENA = 0
>                                  CB2_DEST_BASE_ENA = 0
>                                  CB3_DEST_BASE_ENA = 0
>                                  CB4_DEST_BASE_ENA = 0
>                                  CB5_DEST_BASE_ENA = 0
>                                  CB6_DEST_BASE_ENA = 0
>                                  CB7_DEST_BASE_ENA = 0
>                                  DB_DEST_BASE_ENA = 0
>                                  TCL1_VOL_ACTION_ENA = 0
>                                  TC_VOL_ACTION_ENA = 0
>                                  TC_WB_ACTION_ENA = 0
>                                  DEST_BASE_2_ENA = 0
>                                  DEST_BASE_3_ENA = 0
>                                  TCL1_ACTION_ENA = 1
>                                  TC_ACTION_ENA = 0
>                                  CB_ACTION_ENA = 0
>                                  DB_ACTION_ENA = 0
>                                  SH_KCACHE_ACTION_ENA = 1
>                                  SH_KCACHE_VOL_ACTION_ENA = 0
>                                  SH_ICACHE_ACTION_ENA = 0
>                                  SH_KCACHE_WB_ACTION_ENA = 0
>                                  SH_SD_ACTION_ENA = 0
>ffffffff         [1;33mCP_COHER_SIZE[0m <- 0xffffffff
>00000000         [1;33mCP_COHER_BASE[0m <- 0
>0000000a         [1;33mPOLL_INTERVAL[0m <- 10 (0x000a)
>c0055000 [1;32mDMA_DATA[0m:
>e0300000         [1;33mDMA_DATA_WORD0[0m <- CP_SYNC = 1
>                                   SRC_SEL = SRC_ADDR_TC_L2
>                                   DST_SEL = DST_ADDR_TC_L2
>                                   ENGINE = ME
>04d9b7c4         [1;33mSRC_ADDR_LO[0m <- 0x04d9b7c4
>00000001         [1;33mSRC_ADDR_HI[0m <- 1
>09182004         [1;33mDST_ADDR_LO[0m <- 0x09182004
>00000001         [1;33mDST_ADDR_HI[0m <- 1
>40000004         [1;33mCOMMAND[0m <- BYTE_COUNT_GFX6 = 4
>                            BYTE_COUNT_GFX9 = 4
>                            DISABLE_WR_CONFIRM_GFX6 = 0
>                            SRC_SWAP = NONE
>                            DST_SWAP = NONE
>                            SAS = MEMORY
>                            DAS = MEMORY
>                            SAIC = INCREMENT
>                            DAIC = INCREMENT
>                            RAW_WAIT = 1
>                            DISABLE_WR_CONFIRM_GFX9 = 0
>c0004200 [1;32mPFP_SYNC_ME[0m:
>00000000 
>c0044700 [1;32mEVENT_WRITE_EOP[0m:
>00000528         [1;33mVGT_EVENT_INITIATOR[0m <- EVENT_TYPE = BOTTOM_OF_PIPE_TS
>                 [1;33mEVENT_INDEX[0m <- 5
>                 [1;33mTCL1_VOL_ACTION_ENA[0m <- 0
>                 [1;33mTC_VOL_ACTION_ENA[0m <- 0
>                 [1;33mTC_WB_ACTION_ENA[0m <- 0
>                 [1;33mTCL1_ACTION_ENA[0m <- 0
>                 [1;33mTC_ACTION_ENA[0m <- 0
>00000400         [1;33mADDRESS_LO[0m <- 1024 (0x00000400)
>23000001         [1;33mADDRESS_HI[0m <- 0x23000001
>                 [1;33mDST_SEL[0m <- 0
>                 [1;33mINT_SEL[0m <- 3
>                 [1;33mDATA_SEL[0m <- 1
>00000000         [1;33mDATA_LO[0m <- 0
>00000000         [1;33mDATA_HI[0m <- 0
>c0044700 [1;32mEVENT_WRITE_EOP[0m:
>00000528         [1;33mVGT_EVENT_INITIATOR[0m <- EVENT_TYPE = BOTTOM_OF_PIPE_TS
>                 [1;33mEVENT_INDEX[0m <- 5
>                 [1;33mTCL1_VOL_ACTION_ENA[0m <- 0
>                 [1;33mTC_VOL_ACTION_ENA[0m <- 0
>                 [1;33mTC_WB_ACTION_ENA[0m <- 0
>                 [1;33mTCL1_ACTION_ENA[0m <- 0
>                 [1;33mTC_ACTION_ENA[0m <- 0
>001c57c0         [1;33mADDRESS_LO[0m <- 0x001c57c0
>23000001         [1;33mADDRESS_HI[0m <- 0x23000001
>                 [1;33mDST_SEL[0m <- 0
>                 [1;33mINT_SEL[0m <- 3
>                 [1;33mDATA_SEL[0m <- 1
>80000000         [1;33mDATA_LO[0m <- -0.0f (0x80000000)
>00000000         [1;33mDATA_HI[0m <- 0
>c0033700 [1;32mWRITE_DATA[0m:
>40100500         [1;33mCONTROL[0m <- ENGINE_SEL = PFP
>                            WR_CONFIRM = 1
>                            WR_ONE_ADDR = 0
>                            DST_SEL = MEM_ASYNC
>001c57c4         [1;33mDST_ADDR_LO[0m <- 0x001c57c4
>00000001         [1;33mDST_ADDR_HI[0m <- 1
>80000000 
>------------------- IB end -------------------
>
>
>------------------------------------------------
>Decompress Color (levels 0 - 0, mask 0x1)
>
>------------------ IB begin ------------------
>c0026900 [1;36mSET_CONTEXT_REG[1;36m:
>000002e5 
>00000000         [1;33mVGT_STRMOUT_CONFIG[0m <- STREAMOUT_0_EN = 0
>                                       STREAMOUT_1_EN = 0
>                                       STREAMOUT_2_EN = 0
>                                       STREAMOUT_3_EN = 0
>                                       RAST_STREAM = 0
>                                       RAST_STREAM_MASK = 0
>                                       USE_RAST_STREAM_MASK = 0
>00000000         [1;33mVGT_STRMOUT_BUFFER_CONFIG[0m <- STREAM_0_BUFFER_EN = 0
>                                              STREAM_1_BUFFER_EN = 0
>                                              STREAM_2_BUFFER_EN = 0
>                                              STREAM_3_BUFFER_EN = 0
>c00e6900 [1;36mSET_CONTEXT_REG[1;36m:
>00000318 
>01042d3c         [1;33mCB_COLOR0_BASE[0m <- 0x01042d3c
>01f0001f         [1;33mCB_COLOR0_PITCH[0m <- TILE_MAX = 31 (0x1f)
>                                    FMASK_TILE_MAX = 31 (0x1f)
>000003ff         [1;33mCB_COLOR0_SLICE[0m <- TILE_MAX = 1023 (0x003ff)
>00000000         [1;33mCB_COLOR0_VIEW[0m <- SLICE_START = 0
>                                   SLICE_MAX = 0
>10060730         [1;33mCB_COLOR0_INFO[0m <- ENDIAN = ENDIAN_NONE
>                                   FORMAT = COLOR_16_16_16_16
>                                   LINEAR_GENERAL = 0
>                                   NUMBER_TYPE = NUMBER_FLOAT
>                                   COMP_SWAP = SWAP_STD
>                                   FAST_CLEAR = 0
>                                   COMPRESSION = 0
>                                   BLEND_CLAMP = 0
>                                   BLEND_BYPASS = 0
>                                   SIMPLE_FLOAT = 1
>                                   ROUND_MODE = 1
>                                   CMASK_IS_LINEAR = 0
>                                   BLEND_OPT_DONT_RD_DST = FORCE_OPT_AUTO
>                                   BLEND_OPT_DISCARD_PIXEL = FORCE_OPT_AUTO
>                                   FMASK_COMPRESSION_DISABLE = 0
>                                   FMASK_COMPRESS_1FRAG_ONLY = 0
>                                   DCC_ENABLE = 1
>                                   CMASK_ADDR_TYPE = 0
>000001ce         [1;33mCB_COLOR0_ATTRIB[0m <- TILE_MODE_INDEX = 14 (0xe)
>                                     FMASK_TILE_MODE_INDEX = 14 (0xe)
>                                     FMASK_BANK_HEIGHT = 0
>                                     NUM_SAMPLES = 0
>                                     NUM_FRAGMENTS = 0
>                                     FORCE_DST_ALPHA_1 = 0
>00000208         [1;33mCB_COLOR0_DCC_CONTROL[0m <- OVERWRITE_COMBINER_DISABLE = 0
>                                          KEY_CLEAR_ENABLE = 0
>                                          MAX_UNCOMPRESSED_BLOCK_SIZE = MAX_BLOCK_SIZE_256B
>                                          MIN_COMPRESSED_BLOCK_SIZE = MIN_BLOCK_SIZE_32B
>                                          MAX_COMPRESSED_BLOCK_SIZE = 0
>                                          COLOR_TRANSFORM = 0
>                                          INDEPENDENT_64B_BLOCKS = 1
>                                          LOSSY_RGB_PRECISION = 0
>                                          LOSSY_ALPHA_PRECISION = 0
>01042d00         [1;33mCB_COLOR0_CMASK[0m <- 0x01042d00
>00000003         [1;33mCB_COLOR0_CMASK_SLICE[0m <- TILE_MAX = 3
>01042d3c         [1;33mCB_COLOR0_FMASK[0m <- 0x01042d3c
>000003ff         [1;33mCB_COLOR0_FMASK_SLICE[0m <- TILE_MAX = 1023 (0x003ff)
>00000000         [1;33mCB_COLOR0_CLEAR_WORD0[0m <- 0
>00000000         [1;33mCB_COLOR0_CLEAR_WORD1[0m <- 0
>0104353c         [1;33mCB_COLOR0_DCC_BASE[0m <- 0x0104353c
>c0016900 [1;36mSET_CONTEXT_REG[1;36m:
>00000082 
>00ee00e8         [1;33mPA_SC_WINDOW_SCISSOR_BR[0m <- BR_X = 232 (0x0e8)
>                                            BR_Y = 238 (0x0ee)
>c0026900 [1;36mSET_CONTEXT_REG[1;36m:
>000002f5 
>00000000         [1;33mPA_SC_CENTROID_PRIORITY_0[0m <- DISTANCE_0 = 0
>                                              DISTANCE_1 = 0
>                                              DISTANCE_2 = 0
>                                              DISTANCE_3 = 0
>                                              DISTANCE_4 = 0
>                                              DISTANCE_5 = 0
>                                              DISTANCE_6 = 0
>                                              DISTANCE_7 = 0
>00000000         [1;33mPA_SC_CENTROID_PRIORITY_1[0m <- DISTANCE_8 = 0
>                                              DISTANCE_9 = 0
>                                              DISTANCE_10 = 0
>                                              DISTANCE_11 = 0
>                                              DISTANCE_12 = 0
>                                              DISTANCE_13 = 0
>                                              DISTANCE_14 = 0
>                                              DISTANCE_15 = 0
>c0016900 [1;36mSET_CONTEXT_REG[1;36m:
>000002fe 
>00000000         [1;33mPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0[0m <- S0_X = 0
>                                                      S0_Y = 0
>                                                      S1_X = 0
>                                                      S1_Y = 0
>                                                      S2_X = 0
>                                                      S2_Y = 0
>                                                      S3_X = 0
>                                                      S3_Y = 0
>c0016900 [1;36mSET_CONTEXT_REG[1;36m:
>00000302 
>00000000         [1;33mPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0[0m <- S0_X = 0
>                                                      S0_Y = 0
>                                                      S1_X = 0
>                                                      S1_Y = 0
>                                                      S2_X = 0
>                                                      S2_Y = 0
>                                                      S3_X = 0
>                                                      S3_Y = 0
>c0016900 [1;36mSET_CONTEXT_REG[1;36m:
>00000306 
>00000000         [1;33mPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0[0m <- S0_X = 0
>                                                      S0_Y = 0
>                                                      S1_X = 0
>                                                      S1_Y = 0
>                                                      S2_X = 0
>                                                      S2_Y = 0
>                                                      S3_X = 0
>                                                      S3_Y = 0
>c0016900 [1;36mSET_CONTEXT_REG[1;36m:
>0000030a 
>00000000         [1;33mPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0[0m <- S0_X = 0
>                                                      S0_Y = 0
>                                                      S1_X = 0
>                                                      S1_Y = 0
>                                                      S2_X = 0
>                                                      S2_Y = 0
>                                                      S3_X = 0
>                                                      S3_Y = 0
>c0016900 [1;36mSET_CONTEXT_REG[1;36m:
>0000020c 
>00000005         [1;33mPA_SU_SMALL_PRIM_FILTER_CNTL[0m <- SMALL_PRIM_FILTER_ENABLE = 1
>                                                 TRIANGLE_FILTER_DISABLE = 0
>                                                 LINE_FILTER_DISABLE = 1
>                                                 POINT_FILTER_DISABLE = 0
>                                                 RECTANGLE_FILTER_DISABLE = 0
>c0016900 [1;36mSET_CONTEXT_REG[1;36m:
>00000203 
>00000010         [1;33mDB_SHADER_CONTROL[0m <- Z_EXPORT_ENABLE = 0
>                                      STENCIL_TEST_VAL_EXPORT_ENABLE = 0
>                                      STENCIL_OP_VAL_EXPORT_ENABLE = 0
>                                      Z_ORDER = EARLY_Z_THEN_LATE_Z
>                                      KILL_ENABLE = 0
>                                      COVERAGE_TO_MASK_ENABLE = 0
>                                      MASK_EXPORT_ENABLE = 0
>                                      EXEC_ON_HIER_FAIL = 0
>                                      EXEC_ON_NOOP = 0
>                                      ALPHA_TO_MASK_DISABLE = 0
>                                      DEPTH_BEFORE_SHADER = 0
>                                      CONSERVATIVE_Z_EXPORT = EXPORT_ANY_Z
>                                      DUAL_QUAD_DISABLE = 0
>c0016900 [1;36mSET_CONTEXT_REG[1;36m:
>00000201 
>00170000         [1;33mDB_EQAA[0m <- MAX_ANCHOR_SAMPLES = 0
>                            PS_ITER_SAMPLES = 0
>                            MASK_EXPORT_NUM_SAMPLES = 0
>                            ALPHA_TO_MASK_NUM_SAMPLES = 0
>                            HIGH_QUALITY_INTERSECTIONS = 1
>                            INCOHERENT_EQAA_READS = 1
>                            INTERPOLATE_COMP_Z = 1
>                            INTERPOLATE_SRC_Z = 0
>                            STATIC_ANCHOR_ASSOCIATIONS = 1
>                            ALPHA_TO_MASK_EQAA_DISABLE = 0
>                            OVERRASTERIZATION_AMOUNT = 0
>                            ENABLE_POSTZ_OVERRASTERIZATION = 0
>c0016900 [1;36mSET_CONTEXT_REG[1;36m:
>00000293 
>760201bc         [1;33mPA_SC_MODE_CNTL_1[0m <- WALK_SIZE = 0
>                                      WALK_ALIGNMENT = 0
>                                      WALK_ALIGN8_PRIM_FITS_ST = 1
>                                      WALK_FENCE_ENABLE = 1
>                                      WALK_FENCE_SIZE = 3
>                                      SUPERTILE_WALK_ORDER_ENABLE = 1
>                                      TILE_WALK_ORDER_ENABLE = 1
>                                      TILE_COVER_DISABLE = 0
>                                      TILE_COVER_NO_SCISSOR = 0
>                                      ZMM_LINE_EXTENT = 0
>                                      ZMM_LINE_OFFSET = 0
>                                      ZMM_RECT_EXTENT = 0
>                                      KILL_PIX_POST_HI_Z = 0
>                                      KILL_PIX_POST_DETAIL_MASK = 0
>                                      PS_ITER_SAMPLE = 0
>                                      MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE = 1
>                                      MULTI_GPU_SUPERTILE_ENABLE = 0
>                                      GPU_ID_OVERRIDE_ENABLE = 0
>                                      GPU_ID_OVERRIDE = 0
>                                      MULTI_GPU_PRIM_DISCARD_ENABLE = 0
>                                      FORCE_EOV_CNTDWN_ENABLE = 1
>                                      FORCE_EOV_REZ_ENABLE = 1
>                                      OUT_OF_ORDER_PRIMITIVE_ENABLE = 0
>                                      OUT_OF_ORDER_WATER_MARK = 7
>c0026900 [1;36mSET_CONTEXT_REG[1;36m:
>0000030e 
>ffffffff         [1;33mPA_SC_AA_MASK_X0Y0_X1Y0[0m <- AA_MASK_X0Y0 = 0xffff
>                                            AA_MASK_X1Y0 = 0xffff
>ffffffff         [1;33mPA_SC_AA_MASK_X0Y1_X1Y1[0m <- AA_MASK_X0Y1 = 0xffff
>                                            AA_MASK_X1Y1 = 0xffff
>c0016900 [1;36mSET_CONTEXT_REG[1;36m:
>0000008e 
>0000000f         [1;33mCB_TARGET_MASK[0m <- TARGET0_ENABLE = 15 (0xf)
>                                   TARGET1_ENABLE = 0
>                                   TARGET2_ENABLE = 0
>                                   TARGET3_ENABLE = 0
>                                   TARGET4_ENABLE = 0
>                                   TARGET5_ENABLE = 0
>                                   TARGET6_ENABLE = 0
>                                   TARGET7_ENABLE = 0
>c0016900 [1;36mSET_CONTEXT_REG[1;36m:
>00000109 
>00000012         [1;33mCB_DCC_CONTROL[0m <- OVERWRITE_COMBINER_DISABLE = 0
>                                   OVERWRITE_COMBINER_MRT_SHARING_DISABLE = 1
>                                   OVERWRITE_COMBINER_WATERMARK = 4
>c0016900 [1;36mSET_CONTEXT_REG[1;36m:
>00000204 
>01010000         [1;33mPA_CL_CLIP_CNTL[0m <- UCP_ENA_0 = 0
>                                    UCP_ENA_1 = 0
>                                    UCP_ENA_2 = 0
>                                    UCP_ENA_3 = 0
>                                    UCP_ENA_4 = 0
>                                    UCP_ENA_5 = 0
>                                    PS_UCP_Y_SCALE_NEG = 0
>                                    PS_UCP_MODE = 0
>                                    CLIP_DISABLE = 1
>                                    UCP_CULL_ONLY_ENA = 0
>                                    BOUNDARY_EDGE_FLAG_ENA = 0
>                                    DX_CLIP_SPACE_DEF = 0
>                                    DIS_CLIP_ERR_DETECT = 0
>                                    VTX_KILL_OR = 0
>                                    DX_RASTERIZATION_KILL = 0
>                                    DX_LINEAR_ATTR_CLIP_ENA = 1
>                                    VTE_VPORT_PROVOKE_DISABLE = 0
>                                    ZCLIP_NEAR_DISABLE = 0
>                                    ZCLIP_FAR_DISABLE = 0
>c0017600 [1;36mSET_SH_REG[1;36m:
>0000000c 
>0034f580         [1;33mSPI_SHADER_USER_DATA_PS_0[0m <- 0x0034f580
>c0017600 [1;36mSET_SH_REG[1;36m:
>0000004c 
>0034f580         [1;33mSPI_SHADER_USER_DATA_VS_0[0m <- 0x0034f580
>c0017600 [1;36mSET_SH_REG[1;36m:
>000000cc 
>0034f580         [1;33mSPI_SHADER_USER_DATA_ES_0[0m <- 0x0034f580
>c0017600 [1;36mSET_SH_REG[1;36m:
>0000008c 
>0034f580         [1;33mSPI_SHADER_USER_DATA_GS_0[0m <- 0x0034f580
>c0017600 [1;36mSET_SH_REG[1;36m:
>0000010c 
>0034f580         [1;33mSPI_SHADER_USER_DATA_HS_0[0m <- 0x0034f580
>c0017600 [1;36mSET_SH_REG[1;36m:
>0000014c 
>0034f580         [1;33mSPI_SHADER_USER_DATA_LS_0[0m <- 0x0034f580
>c0027600 [1;36mSET_SH_REG[1;36m:
>0000000e 
>0034f610         [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x0034f610
>0152ff00         [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 0x0152ff00
>c0027600 [1;36mSET_SH_REG[1;36m:
>0000010e 
>00000000         [1;33mSPI_SHADER_USER_DATA_HS_2[0m <- 0
>00000000         [1;33mSPI_SHADER_USER_DATA_HS_3[0m <- 0
>c0027600 [1;36mSET_SH_REG[1;36m:
>0000008e 
>0034dd90         [1;33mSPI_SHADER_USER_DATA_GS_2[0m <- 0x0034dd90
>00000000         [1;33mSPI_SHADER_USER_DATA_GS_3[0m <- 0
>c0017600 [1;36mSET_SH_REG[1;36m:
>0000000d 
>01520000         [1;33mSPI_SHADER_USER_DATA_PS_1[0m <- 0x01520000
>c0017600 [1;36mSET_SH_REG[1;36m:
>0000004d 
>01520000         [1;33mSPI_SHADER_USER_DATA_VS_1[0m <- 0x01520000
>c0017600 [1;36mSET_SH_REG[1;36m:
>000000cd 
>01520000         [1;33mSPI_SHADER_USER_DATA_ES_1[0m <- 0x01520000
>c0017600 [1;36mSET_SH_REG[1;36m:
>0000008d 
>01520000         [1;33mSPI_SHADER_USER_DATA_GS_1[0m <- 0x01520000
>c0017600 [1;36mSET_SH_REG[1;36m:
>0000010d 
>01520000         [1;33mSPI_SHADER_USER_DATA_HS_1[0m <- 0x01520000
>c0017600 [1;36mSET_SH_REG[1;36m:
>0000014d 
>01520000         [1;33mSPI_SHADER_USER_DATA_LS_1[0m <- 0x01520000
>c0046900 [1;36mSET_CONTEXT_REG[1;36m:
>000002fa 
>426eb7f1         [1;33mPA_CL_GB_VERT_CLIP_ADJ[0m <- 0x426eb7f1
>3f800000         [1;33mPA_CL_GB_VERT_DISC_ADJ[0m <- 1.0f (0x3f800000)
>42048777         [1;33mPA_CL_GB_HORZ_CLIP_ADJ[0m <- 0x42048777
>3f800000         [1;33mPA_CL_GB_HORZ_DISC_ADJ[0m <- 1.0f (0x3f800000)
>c0026900 [1;36mSET_CONTEXT_REG[1;36m:
>00000094 
>80000000         [1;33mPA_SC_VPORT_SCISSOR_0_TL[0m <- TL_X = 0
>                                             TL_Y = 0
>                                             WINDOW_OFFSET_DISABLE = 1
>40004000         [1;33mPA_SC_VPORT_SCISSOR_0_BR[0m <- BR_X = 16384 (0x4000)
>                                             BR_Y = 16384 (0x4000)
>c0066900 [1;36mSET_CONTEXT_REG[1;36m:
>0000010f 
>44700000         [1;33mPA_CL_VPORT_XSCALE[0m <- 960.0f (0x44700000)
>44700000         [1;33mPA_CL_VPORT_XOFFSET[0m <- 960.0f (0x44700000)
>44070000         [1;33mPA_CL_VPORT_YSCALE[0m <- 540.0f (0x44070000)
>44070000         [1;33mPA_CL_VPORT_YOFFSET[0m <- 540.0f (0x44070000)
>3f000000         [1;33mPA_CL_VPORT_ZSCALE[0m <- 0.5f (0x3f000000)
>3f000000         [1;33mPA_CL_VPORT_ZOFFSET[0m <- 0.5f (0x3f000000)
>c0026900 [1;36mSET_CONTEXT_REG[1;36m:
>000000b4 
>00000000         [1;33mPA_SC_VPORT_ZMIN_0[0m <- 0
>3f800000         [1;33mPA_SC_VPORT_ZMAX_0[0m <- 1.0f (0x3f800000)
>c0026900 [1;36mSET_CONTEXT_REG[1;36m:
>0000010c 
>01000000         [1;33mDB_STENCILREFMASK[0m <- STENCILTESTVAL = 0
>                                      STENCILMASK = 0
>                                      STENCILWRITEMASK = 0
>                                      STENCILOPVAL = 1
>01000000         [1;33mDB_STENCILREFMASK_BF[0m <- STENCILTESTVAL_BF = 0
>                                         STENCILMASK_BF = 0
>                                         STENCILWRITEMASK_BF = 0
>                                         STENCILOPVAL_BF = 1
>c0016900 [1;36mSET_CONTEXT_REG[1;36m:
>00000191 
>00000020         [1;33mSPI_PS_INPUT_CNTL_0[0m <- OFFSET = 32 (0x20)
>                                        DEFAULT_VAL = X_0_0F
>                                        FLAT_SHADE = 0
>                                        CYL_WRAP = 0
>                                        PT_SPRITE_TEX = 0
>                                        DUP = 0
>                                        FP16_INTERP_MODE = 0
>                                        USE_DEFAULT_ATTR1 = 0
>                                        DEFAULT_VAL_ATTR1 = 0
>                                        PT_SPRITE_TEX_ATTR1 = 0
>                                        ATTR0_VALID = 0
>                                        ATTR1_VALID = 0
>c0016900 [1;36mSET_CONTEXT_REG[1;36m:
>000001ba 
>000001c0         [1;33mSPI_TMPRING_SIZE[0m <- WAVES = 448 (0x1c0)
>                                     WAVESIZE = 0
>c0016900 [1;36mSET_CONTEXT_REG[1;36m:
>000002dc 
>0000aa00         [1;33mDB_ALPHA_TO_MASK[0m <- ALPHA_TO_MASK_ENABLE = 0
>                                     ALPHA_TO_MASK_OFFSET0 = 2
>                                     ALPHA_TO_MASK_OFFSET1 = 2
>                                     ALPHA_TO_MASK_OFFSET2 = 2
>                                     ALPHA_TO_MASK_OFFSET3 = 2
>                                     OFFSET_ROUND = 0
>c0086900 [1;36mSET_CONTEXT_REG[1;36m:
>000001e0 
>00000000         [1;33mCB_BLEND0_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                                      COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                                      COLOR_DESTBLEND = BLEND_ZERO
>                                      ALPHA_SRCBLEND = BLEND_ZERO
>                                      ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                                      ALPHA_DESTBLEND = BLEND_ZERO
>                                      SEPARATE_ALPHA_BLEND = 0
>                                      ENABLE = 0
>                                      DISABLE_ROP3 = 0
>00000000         [1;33mCB_BLEND1_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                                      COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                                      COLOR_DESTBLEND = BLEND_ZERO
>                                      ALPHA_SRCBLEND = BLEND_ZERO
>                                      ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                                      ALPHA_DESTBLEND = BLEND_ZERO
>                                      SEPARATE_ALPHA_BLEND = 0
>                                      ENABLE = 0
>                                      DISABLE_ROP3 = 0
>00000000         [1;33mCB_BLEND2_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                                      COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                                      COLOR_DESTBLEND = BLEND_ZERO
>                                      ALPHA_SRCBLEND = BLEND_ZERO
>                                      ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                                      ALPHA_DESTBLEND = BLEND_ZERO
>                                      SEPARATE_ALPHA_BLEND = 0
>                                      ENABLE = 0
>                                      DISABLE_ROP3 = 0
>00000000         [1;33mCB_BLEND3_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                                      COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                                      COLOR_DESTBLEND = BLEND_ZERO
>                                      ALPHA_SRCBLEND = BLEND_ZERO
>                                      ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                                      ALPHA_DESTBLEND = BLEND_ZERO
>                                      SEPARATE_ALPHA_BLEND = 0
>                                      ENABLE = 0
>                                      DISABLE_ROP3 = 0
>00000000         [1;33mCB_BLEND4_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                                      COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                                      COLOR_DESTBLEND = BLEND_ZERO
>                                      ALPHA_SRCBLEND = BLEND_ZERO
>                                      ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                                      ALPHA_DESTBLEND = BLEND_ZERO
>                                      SEPARATE_ALPHA_BLEND = 0
>                                      ENABLE = 0
>                                      DISABLE_ROP3 = 0
>00000000         [1;33mCB_BLEND5_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                                      COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                                      COLOR_DESTBLEND = BLEND_ZERO
>                                      ALPHA_SRCBLEND = BLEND_ZERO
>                                      ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                                      ALPHA_DESTBLEND = BLEND_ZERO
>                                      SEPARATE_ALPHA_BLEND = 0
>                                      ENABLE = 0
>                                      DISABLE_ROP3 = 0
>00000000         [1;33mCB_BLEND6_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                                      COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                                      COLOR_DESTBLEND = BLEND_ZERO
>                                      ALPHA_SRCBLEND = BLEND_ZERO
>                                      ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                                      ALPHA_DESTBLEND = BLEND_ZERO
>                                      SEPARATE_ALPHA_BLEND = 0
>                                      ENABLE = 0
>                                      DISABLE_ROP3 = 0
>00000000         [1;33mCB_BLEND7_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ZERO
>                                      COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                                      COLOR_DESTBLEND = BLEND_ZERO
>                                      ALPHA_SRCBLEND = BLEND_ZERO
>                                      ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                                      ALPHA_DESTBLEND = BLEND_ZERO
>                                      SEPARATE_ALPHA_BLEND = 0
>                                      ENABLE = 0
>                                      DISABLE_ROP3 = 0
>c0016900 [1;36mSET_CONTEXT_REG[1;36m:
>00000202 
>00cc0060         [1;33mCB_COLOR_CONTROL[0m <- DISABLE_DUAL_QUAD = 0
>                                     DEGAMMA_ENABLE = 0
>                                     MODE = CB_DCC_DECOMPRESS
>                                     ROP3 = ROP3_COPY
>c0016900 [1;36mSET_CONTEXT_REG[1;36m:
>000001b5 
>00000869         [1;33mSPI_INTERP_CONTROL_0[0m <- FLAT_SHADE_ENA = 1
>                                         PNT_SPRITE_ENA = 0
>                                         PNT_SPRITE_OVRD_X = SPI_PNT_SPRITE_SEL_S
>                                         PNT_SPRITE_OVRD_Y = SPI_PNT_SPRITE_SEL_T
>                                         PNT_SPRITE_OVRD_Z = SPI_PNT_SPRITE_SEL_0
>                                         PNT_SPRITE_OVRD_W = SPI_PNT_SPRITE_SEL_1
>                                         PNT_SPRITE_TOP_1 = 0
>c0036900 [1;36mSET_CONTEXT_REG[1;36m:
>00000280 
>00000000         [1;33mPA_SU_POINT_SIZE[0m <- HEIGHT = 0
>                                     WIDTH = 0
>00000000         [1;33mPA_SU_POINT_MINMAX[0m <- MIN_SIZE = 0
>                                       MAX_SIZE = 0
>00000000         [1;33mPA_SU_LINE_CNTL[0m <- WIDTH = 0
>c0016900 [1;36mSET_CONTEXT_REG[1;36m:
>00000292 
>00000002         [1;33mPA_SC_MODE_CNTL_0[0m <- MSAA_ENABLE = 0
>                                      VPORT_SCISSOR_ENABLE = 1
>                                      LINE_STIPPLE_ENABLE = 0
>                                      SEND_UNLIT_STILES_TO_PKR = 0
>c0016900 [1;36mSET_CONTEXT_REG[1;36m:
>000002f9 
>00000029         [1;33mPA_SU_VTX_CNTL[0m <- PIX_CENTER = 1
>                                   ROUND_MODE = X_TRUNCATE
>                                   QUANT_MODE = X_16_8_FIXED_POINT_1_256TH
>c0016900 [1;36mSET_CONTEXT_REG[1;36m:
>000002df 
>00000000         [1;33mPA_SU_POLY_OFFSET_CLAMP[0m <- 0
>c0016900 [1;36mSET_CONTEXT_REG[1;36m:
>00000205 
>00080244         [1;33mPA_SU_SC_MODE_CNTL[0m <- CULL_FRONT = 0
>                                       CULL_BACK = 0
>                                       FACE = 1
>                                       POLY_MODE = X_DISABLE_POLY_MODE
>                                       POLYMODE_FRONT_PTYPE = X_DRAW_TRIANGLES
>                                       POLYMODE_BACK_PTYPE = X_DRAW_TRIANGLES
>                                       POLY_OFFSET_FRONT_ENABLE = 0
>                                       POLY_OFFSET_BACK_ENABLE = 0
>                                       POLY_OFFSET_PARA_ENABLE = 0
>                                       VTX_WINDOW_OFFSET_ENABLE = 0
>                                       PROVOKING_VTX_LAST = 1
>                                       PERSP_CORR_DIS = 0
>                                       MULTI_PRIM_IB_ENA = 0
>c0016900 [1;36mSET_CONTEXT_REG[1;36m:
>00000200 
>00000000         [1;33mDB_DEPTH_CONTROL[0m <- STENCIL_ENABLE = 0
>                                     Z_ENABLE = 0
>                                     Z_WRITE_ENABLE = 0
>                                     DEPTH_BOUNDS_ENABLE = 0
>                                     ZFUNC = FRAG_NEVER
>                                     BACKFACE_ENABLE = 0
>                                     STENCILFUNC = REF_NEVER
>                                     STENCILFUNC_BF = REF_NEVER
>                                     ENABLE_COLOR_WRITES_ON_DEPTH_FAIL = 0
>                                     DISABLE_COLOR_WRITES_ON_DEPTH_PASS = 0
>c0016900 [1;36mSET_CONTEXT_REG[1;36m:
>000002d5 
>00000000         [1;33mVGT_SHADER_STAGES_EN[0m <- LS_EN = LS_STAGE_OFF
>                                         HS_EN = 0
>                                         ES_EN = ES_STAGE_OFF
>                                         GS_EN = 0
>                                         VS_EN = VS_STAGE_REAL
>                                         DYNAMIC_HS = 0
>                                         DISPATCH_DRAW_EN = 0
>                                         DIS_DEALLOC_ACCUM_0 = 0
>                                         DIS_DEALLOC_ACCUM_1 = 0
>                                         VS_WAVE_ID_EN = 0
>c0016900 [1;36mSET_CONTEXT_REG[1;36m:
>00000290 
>00000000         [1;33mVGT_GS_MODE[0m <- MODE = GS_OFF
>                                RESERVED_0 = 0
>                                CUT_MODE = GS_CUT_1024
>                                RESERVED_1 = 0
>                                GS_C_PACK_EN = 0
>                                RESERVED_2 = 0
>                                ES_PASSTHRU = 0
>                                COMPUTE_MODE = 0
>                                FAST_COMPUTE_MODE = 0
>                                ELEMENT_INFO_EN = 0
>                                PARTIAL_THD_AT_EOI = 0
>                                SUPPRESS_CUTS = 0
>                                ES_WRITE_OPTIMIZE = 0
>                                GS_WRITE_OPTIMIZE = 0
>                                ONCHIP = X_0_OFFCHIP_GS
>c0016900 [1;36mSET_CONTEXT_REG[1;36m:
>000002a1 
>00000000         [1;33mVGT_PRIMITIVEID_EN[0m <- PRIMITIVEID_EN = 0
>                                       DISABLE_RESET_ON_EOI = 0
>c0016900 [1;36mSET_CONTEXT_REG[1;36m:
>000002ad 
>00000000         [1;33mVGT_REUSE_OFF[0m <- REUSE_OFF = 0
>c0016900 [1;36mSET_CONTEXT_REG[1;36m:
>000001b1 
>00000000         [1;33mSPI_VS_OUT_CONFIG[0m <- VS_EXPORT_COUNT = 0
>                                      VS_HALF_PACK = 0
>                                      VS_EXPORTS_FOG = 0
>                                      VS_OUT_FOG_VEC_ADDR = 0
>c0016900 [1;36mSET_CONTEXT_REG[1;36m:
>000001c3 
>00000004         [1;33mSPI_SHADER_POS_FORMAT[0m <- POS0_EXPORT_FORMAT = SPI_SHADER_4COMP
>                                          POS1_EXPORT_FORMAT = SPI_SHADER_NONE
>                                          POS2_EXPORT_FORMAT = SPI_SHADER_NONE
>                                          POS3_EXPORT_FORMAT = SPI_SHADER_NONE
>c0047600 [1;36mSET_SH_REG[1;36m:
>00000048 
>0100002a         [1;33mSPI_SHADER_PGM_LO_VS[0m <- 0x0100002a
>00000000         [1;33mSPI_SHADER_PGM_HI_VS[0m <- MEM_BASE = 0
>002c0001         [1;33mSPI_SHADER_PGM_RSRC1_VS[0m <- VGPRS = 1
>                                            SGPRS = 0
>                                            PRIORITY = 0
>                                            FLOAT_MODE = 192 (0xc0)
>                                            PRIV = 0
>                                            DX10_CLAMP = 1
>                                            DEBUG_MODE = 0
>                                            IEEE_MODE = 0
>                                            VGPR_COMP_CNT = 0
>                                            CU_GROUP_ENABLE = 0
>                                            CACHE_CTL = 0
>                                            CDBG_USER = 0
>0000000a         [1;33mSPI_SHADER_PGM_RSRC2_VS[0m <- SCRATCH_EN = 0
>                                            USER_SGPR = 5
>                                            TRAP_PRESENT = 0
>                                            OC_LDS_EN = 0
>                                            SO_BASE0_EN = 0
>                                            SO_BASE1_EN = 0
>                                            SO_BASE2_EN = 0
>                                            SO_BASE3_EN = 0
>                                            SO_EN = 0
>                                            EXCP_EN_SI = 0
>                                            EXCP_EN = 0
>                                            DISPATCH_DRAW_EN = 0
>c0016900 [1;36mSET_CONTEXT_REG[1;36m:
>00000206 
>00000300         [1;33mPA_CL_VTE_CNTL[0m <- VPORT_X_SCALE_ENA = 0
>                                   VPORT_X_OFFSET_ENA = 0
>                                   VPORT_Y_SCALE_ENA = 0
>                                   VPORT_Y_OFFSET_ENA = 0
>                                   VPORT_Z_SCALE_ENA = 0
>                                   VPORT_Z_OFFSET_ENA = 0
>                                   VTX_XY_FMT = 1
>                                   VTX_Z_FMT = 1
>                                   VTX_W0_FMT = 0
>c0016900 [1;36mSET_CONTEXT_REG[1;36m:
>00000316 
>0000001e         [1;33mVGT_VERTEX_REUSE_BLOCK_CNTL[0m <- VTX_REUSE_DEPTH = 30 (0x1e)
>c0026900 [1;36mSET_CONTEXT_REG[1;36m:
>000001b3 
>00000020         [1;33mSPI_PS_INPUT_ENA[0m <- PERSP_SAMPLE_ENA = 0
>                                     PERSP_CENTER_ENA = 0
>                                     PERSP_CENTROID_ENA = 0
>                                     PERSP_PULL_MODEL_ENA = 0
>                                     LINEAR_SAMPLE_ENA = 0
>                                     LINEAR_CENTER_ENA = 1
>                                     LINEAR_CENTROID_ENA = 0
>                                     LINE_STIPPLE_TEX_ENA = 0
>                                     POS_X_FLOAT_ENA = 0
>                                     POS_Y_FLOAT_ENA = 0
>                                     POS_Z_FLOAT_ENA = 0
>                                     POS_W_FLOAT_ENA = 0
>                                     FRONT_FACE_ENA = 0
>                                     ANCILLARY_ENA = 0
>                                     SAMPLE_COVERAGE_ENA = 0
>                                     POS_FIXED_PT_ENA = 0
>0000f077         [1;33mSPI_PS_INPUT_ADDR[0m <- PERSP_SAMPLE_ENA = 1
>                                      PERSP_CENTER_ENA = 1
>                                      PERSP_CENTROID_ENA = 1
>                                      PERSP_PULL_MODEL_ENA = 0
>                                      LINEAR_SAMPLE_ENA = 1
>                                      LINEAR_CENTER_ENA = 1
>                                      LINEAR_CENTROID_ENA = 1
>                                      LINE_STIPPLE_TEX_ENA = 0
>                                      POS_X_FLOAT_ENA = 0
>                                      POS_Y_FLOAT_ENA = 0
>                                      POS_Z_FLOAT_ENA = 0
>                                      POS_W_FLOAT_ENA = 0
>                                      FRONT_FACE_ENA = 1
>                                      ANCILLARY_ENA = 1
>                                      SAMPLE_COVERAGE_ENA = 1
>                                      POS_FIXED_PT_ENA = 1
>c0016900 [1;36mSET_CONTEXT_REG[1;36m:
>000001b8 
>01020000         [1;33mSPI_BARYC_CNTL[0m <- PERSP_CENTER_CNTL = 0
>                                   PERSP_CENTROID_CNTL = 0
>                                   LINEAR_CENTER_CNTL = 0
>                                   LINEAR_CENTROID_CNTL = 0
>                                   POS_FLOAT_LOCATION = 2
>                                   POS_FLOAT_ULC = 0
>                                   FRONT_FACE_ALL_BITS = 1
>c0016900 [1;36mSET_CONTEXT_REG[1;36m:
>000001b6 
>00000001         [1;33mSPI_PS_IN_CONTROL[0m <- NUM_INTERP = 1
>                                      PARAM_GEN = 0
>                                      FOG_ADDR = 0
>                                      BC_OPTIMIZE_DISABLE = 0
>                                      PASS_FOG_THROUGH_PS = 0
>c0026900 [1;36mSET_CONTEXT_REG[1;36m:
>000001c4 
>00000000         [1;33mSPI_SHADER_Z_FORMAT[0m <- Z_EXPORT_FORMAT = SPI_SHADER_ZERO
>00000004         [1;33mSPI_SHADER_COL_FORMAT[0m <- COL0_EXPORT_FORMAT = SPI_SHADER_FP16_ABGR
>                                          COL1_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                          COL2_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                          COL3_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                          COL4_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                          COL5_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                          COL6_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                          COL7_EXPORT_FORMAT = SPI_SHADER_ZERO
>c0016900 [1;36mSET_CONTEXT_REG[1;36m:
>0000008f 
>0000000f         [1;33mCB_SHADER_MASK[0m <- OUTPUT0_ENABLE = 15 (0xf)
>                                   OUTPUT1_ENABLE = 0
>                                   OUTPUT2_ENABLE = 0
>                                   OUTPUT3_ENABLE = 0
>                                   OUTPUT4_ENABLE = 0
>                                   OUTPUT5_ENABLE = 0
>                                   OUTPUT6_ENABLE = 0
>                                   OUTPUT7_ENABLE = 0
>c0047600 [1;36mSET_SH_REG[1;36m:
>00000008 
>01000022         [1;33mSPI_SHADER_PGM_LO_PS[0m <- 0x01000022
>00000000         [1;33mSPI_SHADER_PGM_HI_PS[0m <- MEM_BASE = 0
>002c0005         [1;33mSPI_SHADER_PGM_RSRC1_PS[0m <- VGPRS = 5
>                                            SGPRS = 0
>                                            PRIORITY = 0
>                                            FLOAT_MODE = FP_64_DENORMS
>                                            PRIV = 0
>                                            DX10_CLAMP = 1
>                                            DEBUG_MODE = 0
>                                            IEEE_MODE = 0
>                                            CU_GROUP_DISABLE = 0
>                                            CACHE_CTL = 0
>                                            CDBG_USER = 0
>0000000a         [1;33mSPI_SHADER_PGM_RSRC2_PS[0m <- SCRATCH_EN = 0
>                                            USER_SGPR = 5
>                                            TRAP_PRESENT = 0
>                                            WAVE_CNT_EN = 0
>                                            EXTRA_LDS_SIZE = 0
>                                            EXCP_EN_SI = 0
>                                            EXCP_EN = 0
>c0016900 [1;36mSET_CONTEXT_REG[1;36m:
>100002aa         INDEX = 1
>2010007f         [1;33mIA_MULTI_VGT_PARAM[0m <- PRIMGROUP_SIZE = 127 (0x007f)
>                                       PARTIAL_VS_WAVE_ON = 0
>                                       SWITCH_ON_EOP = 0
>                                       PARTIAL_ES_WAVE_ON = 0
>                                       SWITCH_ON_EOI = 0
>                                       WD_SWITCH_ON_EOP = 1
>                                       MAX_PRIMGRP_IN_WAVE = 2
>c0017900 [1;36mSET_UCONFIG_REG[1;36m:
>10000242         INDEX = 1
>00000011         [1;33mVGT_PRIMITIVE_TYPE[0m <- PRIM_TYPE = DI_PT_RECTLIST
>c0016900 [1;36mSET_CONTEXT_REG[1;36m:
>000002a5 
>00000000         [1;33mVGT_MULTI_PRIM_IB_RESET_EN[0m <- RESET_EN = 0
>c0044700 [1;32mEVENT_WRITE_EOP[0m:
>0000052d         [1;33mVGT_EVENT_INITIATOR[0m <- EVENT_TYPE = FLUSH_AND_INV_CB_DATA_TS
>                 [1;33mEVENT_INDEX[0m <- 5
>                 [1;33mTCL1_VOL_ACTION_ENA[0m <- 0
>                 [1;33mTC_VOL_ACTION_ENA[0m <- 0
>                 [1;33mTC_WB_ACTION_ENA[0m <- 0
>                 [1;33mTCL1_ACTION_ENA[0m <- 0
>                 [1;33mTC_ACTION_ENA[0m <- 0
>00000400         [1;33mADDRESS_LO[0m <- 1024 (0x00000400)
>00000001         [1;33mADDRESS_HI[0m <- 1
>                 [1;33mDST_SEL[0m <- 0
>                 [1;33mINT_SEL[0m <- 0
>                 [1;33mDATA_SEL[0m <- 0
>00000000         [1;33mDATA_LO[0m <- 0
>00000000         [1;33mDATA_HI[0m <- 0
>c0044700 [1;32mEVENT_WRITE_EOP[0m:
>0000052d         [1;33mVGT_EVENT_INITIATOR[0m <- EVENT_TYPE = FLUSH_AND_INV_CB_DATA_TS
>                 [1;33mEVENT_INDEX[0m <- 5
>                 [1;33mTCL1_VOL_ACTION_ENA[0m <- 0
>                 [1;33mTC_VOL_ACTION_ENA[0m <- 0
>                 [1;33mTC_WB_ACTION_ENA[0m <- 0
>                 [1;33mTCL1_ACTION_ENA[0m <- 0
>                 [1;33mTC_ACTION_ENA[0m <- 0
>00000000         [1;33mADDRESS_LO[0m <- 0
>00000000         [1;33mADDRESS_HI[0m <- 0
>                 [1;33mDST_SEL[0m <- 0
>                 [1;33mINT_SEL[0m <- 0
>                 [1;33mDATA_SEL[0m <- 0
>00000000         [1;33mDATA_LO[0m <- 0
>00000000         [1;33mDATA_HI[0m <- 0
>c0004600 [1;32mEVENT_WRITE[0m:
>0000002e         [1;33mVGT_EVENT_INITIATOR[0m <- EVENT_TYPE = FLUSH_AND_INV_CB_META
>                 [1;33mEVENT_INDEX[0m <- 0
>                 [1;33mINV_L2[0m <- 0
>c0004200 [1;32mPFP_SYNC_ME[0m:
>00000000 
>c0034300 [1;32mSURFACE_SYNC[0m:
>02c43fc0         [1;33mCP_COHER_CNTL[0m <- DEST_BASE_0_ENA = 0
>                                  DEST_BASE_1_ENA = 0
>                                  TC_SD_ACTION_ENA = 0
>                                  TC_NC_ACTION_ENA = 0
>                                  CB0_DEST_BASE_ENA = 1
>                                  CB1_DEST_BASE_ENA = 1
>                                  CB2_DEST_BASE_ENA = 1
>                                  CB3_DEST_BASE_ENA = 1
>                                  CB4_DEST_BASE_ENA = 1
>                                  CB5_DEST_BASE_ENA = 1
>                                  CB6_DEST_BASE_ENA = 1
>                                  CB7_DEST_BASE_ENA = 1
>                                  DB_DEST_BASE_ENA = 0
>                                  TCL1_VOL_ACTION_ENA = 0
>                                  TC_VOL_ACTION_ENA = 0
>                                  TC_WB_ACTION_ENA = 1
>                                  DEST_BASE_2_ENA = 0
>                                  DEST_BASE_3_ENA = 0
>                                  TCL1_ACTION_ENA = 1
>                                  TC_ACTION_ENA = 1
>                                  CB_ACTION_ENA = 1
>                                  DB_ACTION_ENA = 0
>                                  SH_KCACHE_ACTION_ENA = 0
>                                  SH_KCACHE_VOL_ACTION_ENA = 0
>                                  SH_ICACHE_ACTION_ENA = 0
>                                  SH_KCACHE_WB_ACTION_ENA = 0
>                                  SH_SD_ACTION_ENA = 0
>ffffffff         [1;33mCP_COHER_SIZE[0m <- 0xffffffff
>00000000         [1;33mCP_COHER_BASE[0m <- 0
>0000000a         [1;33mPOLL_INTERVAL[0m <- 10 (0x000a)
>c0004600 [1;32mEVENT_WRITE[0m:
>0000001a         [1;33mVGT_EVENT_INITIATOR[0m <- EVENT_TYPE = PIPELINESTAT_STOP
>                 [1;33mEVENT_INDEX[0m <- 0
>                 [1;33mINV_L2[0m <- 0
>c0002f00 [1;32mNUM_INSTANCES[0m:
>00000001         [1;33mVGT_NUM_INSTANCES[0m <- 1
>c0037600 [1;36mSET_SH_REG[1;36m:
>0000004e 
>00000000         [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0
>00ee00e8         [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 0x00ee00e8
>00000000         [1;33mSPI_SHADER_USER_DATA_VS_4[0m <- 0
>c0012d00 [1;32mDRAW_INDEX_AUTO[0m:
>00000003         [1;33mVGT_NUM_INDICES[0m <- 3
>00000002         [1;33mVGT_DRAW_INITIATOR[0m <- SOURCE_SELECT = DI_SRC_SEL_AUTO_INDEX
>                                       MAJOR_MODE = DI_MAJOR_MODE_0
>                                       NOT_EOP = 0
>                                       USE_OPAQUE = 0
>c0055000 [1;32mDMA_DATA[0m:
>60300000         [1;33mDMA_DATA_WORD0[0m <- CP_SYNC = 0
>                                   SRC_SEL = SRC_ADDR_TC_L2
>                                   DST_SEL = DST_ADDR_TC_L2
>                                   ENGINE = ME
>00002a00         [1;33mSRC_ADDR_LO[0m <- 10752 (0x00002a00)
>00000001         [1;33mSRC_ADDR_HI[0m <- 1
>00002a00         [1;33mDST_ADDR_LO[0m <- 10752 (0x00002a00)
>00000001         [1;33mDST_ADDR_HI[0m <- 1
>00200060         [1;33mCOMMAND[0m <- BYTE_COUNT_GFX6 = 96 (0x00060)
>                            BYTE_COUNT_GFX9 = 0x200060
>                            DISABLE_WR_CONFIRM_GFX6 = 1
>                            SRC_SWAP = NONE
>                            DST_SWAP = NONE
>                            SAS = MEMORY
>                            DAS = MEMORY
>                            SAIC = INCREMENT
>                            DAIC = INCREMENT
>                            RAW_WAIT = 0
>                            DISABLE_WR_CONFIRM_GFX9 = 0
>c0055000 [1;32mDMA_DATA[0m:
>60300000         [1;33mDMA_DATA_WORD0[0m <- CP_SYNC = 0
>                                   SRC_SEL = SRC_ADDR_TC_L2
>                                   DST_SEL = DST_ADDR_TC_L2
>                                   ENGINE = ME
>0034f380         [1;33mSRC_ADDR_LO[0m <- 0x0034f380
>00000000         [1;33mSRC_ADDR_HI[0m <- 0
>0034f380         [1;33mDST_ADDR_LO[0m <- 0x0034f380
>00000000         [1;33mDST_ADDR_HI[0m <- 0
>00200060         [1;33mCOMMAND[0m <- BYTE_COUNT_GFX6 = 96 (0x00060)
>                            BYTE_COUNT_GFX9 = 0x200060
>                            DISABLE_WR_CONFIRM_GFX6 = 1
>                            SRC_SWAP = NONE
>                            DST_SWAP = NONE
>                            SAS = MEMORY
>                            DAS = MEMORY
>                            SAIC = INCREMENT
>                            DAIC = INCREMENT
>                            RAW_WAIT = 0
>                            DISABLE_WR_CONFIRM_GFX9 = 0
>c0055000 [1;32mDMA_DATA[0m:
>60300000         [1;33mDMA_DATA_WORD0[0m <- CP_SYNC = 0
>                                   SRC_SEL = SRC_ADDR_TC_L2
>                                   DST_SEL = DST_ADDR_TC_L2
>                                   ENGINE = ME
>00002200         [1;33mSRC_ADDR_LO[0m <- 8704 (0x00002200)
>00000001         [1;33mSRC_ADDR_HI[0m <- 1
>00002200         [1;33mDST_ADDR_LO[0m <- 8704 (0x00002200)
>00000001         [1;33mDST_ADDR_HI[0m <- 1
>00200060         [1;33mCOMMAND[0m <- BYTE_COUNT_GFX6 = 96 (0x00060)
>                            BYTE_COUNT_GFX9 = 0x200060
>                            DISABLE_WR_CONFIRM_GFX6 = 1
>                            SRC_SWAP = NONE
>                            DST_SWAP = NONE
>                            SAS = MEMORY
>                            DAS = MEMORY
>                            SAIC = INCREMENT
>                            DAIC = INCREMENT
>                            RAW_WAIT = 0
>                            DISABLE_WR_CONFIRM_GFX9 = 0
>c0033700 [1;32mWRITE_DATA[0m:
>00100100         [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                            WR_CONFIRM = 1
>                            WR_ONE_ADDR = 0
>                            DST_SEL = MEMORY_SYNC
>00065000         [1;33mDST_ADDR_LO[0m <- 0x00065000
>00000001         [1;33mDST_ADDR_HI[0m <- 1
>00000002 
>c0001000 [1;32mNOP[0m:
>                 [31mTrace point ID: 2
>                 [31mThis trace point was reached by the CP.[0m
>cafe0002 
>------------------- IB end -------------------
>
>[1;33mColor buffer 0:[0m
>  Info: npix_x=232, npix_y=238, npix_z=1, blk_w=1, blk_h=1, array_size=1, last_level=0, bpe=8, nsamples=0, flags=0x2000000, r16g16b16a16_float
>  Layout: size=524288, alignment=65536, bankw=1, bankh=2, nbanks=16, mtilea=4, tilesplit=1024, pipeconfig=5, scanout=0
>  DCC: offset=524288, size=2048, alignment=16384
>  DCCLevel[0]: enabled=1, offset=0, fast_clear_size=2048
>  Level[0]: offset=0, slice_size=524288, npix_x=232, npix_y=238, npix_z=1, nblk_x=256, nblk_y=256, mode=3, tiling_index = 14
>
>SHADER KEY
>  part.vs.prolog.instance_divisor_is_one = 31
>  part.vs.prolog.instance_divisor_is_fetched = 0
>  part.vs.prolog.ls_vgpr_fix = 0
>  mono.vs.fix_fetch = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
>  as_es = 0
>  as_ls = 0
>  mono.u.vs_export_prim_id = 0
>  opt.kill_outputs = 0x0
>  opt.clip_disable = 0
>
>Vertex Shader as VS:
>Shader main disassembly:
>main:
>BB4_0:
>	v_mov_b32_e32 v1, s3                                                                ; 7E020203
>	v_mov_b32_e32 v2, s2                                                                ; 7E040202
>	v_cmp_gt_u32_e32 vcc, 2, v0                                                         ; 7D980082
>	v_cndmask_b32_e32 v3, v1, v2, vcc                                                   ; 00060501
>	v_cmp_eq_u32_e32 vcc, 1, v0                                                         ; 7D940081
>	v_cndmask_b32_e32 v0, v2, v1, vcc                                                   ; 00000302
>	v_cvt_f32_i32_sdwa v1, sext(v3) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 ; 7E020AF9 000C0603
>	v_cvt_f32_i32_sdwa v0, sext(v0) dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 ; 7E000AF9 000D0600
>	v_mov_b32_e32 v2, 1.0                                                               ; 7E0402F2
>	v_mov_b32_e32 v3, s4                                                                ; 7E060204
>	exp pos0 v1, v0, v3, v2 done                                                        ; C40008CF 02030001
>	s_endpgm                                                                            ; BF810000
>
>*** SHADER STATS ***
>SGPRS: 8
>VGPRS: 8
>Spilled SGPRs: 0
>Spilled VGPRs: 0
>Private memory VGPRs: 0
>Code Size: 80 bytes
>LDS: 0 blocks
>Scratch: 0 bytes per wave
>Max Waves: 8
>********************
>
>
>SHADER KEY
>  part.ps.prolog.color_two_side = 0
>  part.ps.prolog.flatshade_colors = 0
>  part.ps.prolog.poly_stipple = 0
>  part.ps.prolog.force_persp_sample_interp = 0
>  part.ps.prolog.force_linear_sample_interp = 0
>  part.ps.prolog.force_persp_center_interp = 0
>  part.ps.prolog.force_linear_center_interp = 0
>  part.ps.prolog.bc_optimize_for_persp = 0
>  part.ps.prolog.bc_optimize_for_linear = 0
>  part.ps.epilog.spi_shader_col_format = 0x4
>  part.ps.epilog.color_is_int8 = 0x0
>  part.ps.epilog.color_is_int10 = 0x0
>  part.ps.epilog.last_cbuf = 0
>  part.ps.epilog.alpha_func = 7
>  part.ps.epilog.alpha_to_one = 0
>  part.ps.epilog.poly_line_smoothing = 0
>  part.ps.epilog.clamp_color = 0
>
>Pixel Shader:
>Shader main disassembly:
>main:
>BB2_0:
>	s_mov_b32 m0, s5                     ; BEFC0005
>	v_interp_mov_f32_e32 v0, p0, attr0.x ; D4020002
>	v_interp_mov_f32_e32 v1, p0, attr0.y ; D4060102
>	v_interp_mov_f32_e32 v2, p0, attr0.z ; D40A0202
>	v_interp_mov_f32_e32 v3, p0, attr0.w ; D40E0302
>Shader epilog disassembly:
>ps_epilog:
>BB0_0:
>	v_cvt_pkrtz_f16_f32 v0, v0, v1        ; D2960000 00020300
>	v_cvt_pkrtz_f16_f32 v1, v2, v3        ; D2960001 00020702
>	exp mrt0 v0, v0, v1, v1 done compr vm ; C4001C0F 00000100
>	s_endpgm                              ; BF810000
>
>*** SHADER CONFIG ***
>SPI_PS_INPUT_ADDR = 0xf077
>SPI_PS_INPUT_ENA  = 0x0020
>*** SHADER STATS ***
>SGPRS: 8
>VGPRS: 24
>Spilled SGPRs: 0
>Spilled VGPRs: 0
>Private memory VGPRs: 0
>Code Size: 68 bytes
>LDS: 0 blocks
>Scratch: 0 bytes per wave
>Max Waves: 8
>********************
>
>
>[1;32mRW buffers slot 0 (GPU list):[0m
>        [1;33mSQ_BUF_RSRC_WORD0[0m <- 0x0a279000
>        [1;33mSQ_BUF_RSRC_WORD1[0m <- BASE_ADDRESS_HI = 1
>                             STRIDE = 0
>                             CACHE_SWIZZLE = 0
>                             SWIZZLE_ENABLE = 1
>        [1;33mSQ_BUF_RSRC_WORD2[0m <- 0x00180000
>        [1;33mSQ_BUF_RSRC_WORD3[0m <- DST_SEL_X = SQ_SEL_X
>                             DST_SEL_Y = SQ_SEL_Y
>                             DST_SEL_Z = SQ_SEL_Z
>                             DST_SEL_W = SQ_SEL_W
>                             NUM_FORMAT = BUF_NUM_FORMAT_FLOAT
>                             DATA_FORMAT = BUF_DATA_FORMAT_32
>                             ELEMENT_SIZE = 1
>                             INDEX_STRIDE = 3
>                             ADD_TID_ENABLE = 1
>                             ATC = 0
>                             HASH_ENABLE = 0
>                             HEAP = 0
>                             MTYPE = 0
>                             TYPE = SQ_RSRC_BUF
>
>[1;32mRW buffers slot 1 (GPU list):[0m
>        [1;33mSQ_BUF_RSRC_WORD0[0m <- 0x0a279000
>        [1;33mSQ_BUF_RSRC_WORD1[0m <- BASE_ADDRESS_HI = 1
>                             STRIDE = 0
>                             CACHE_SWIZZLE = 0
>                             SWIZZLE_ENABLE = 0
>        [1;33mSQ_BUF_RSRC_WORD2[0m <- 0x00180000
>        [1;33mSQ_BUF_RSRC_WORD3[0m <- DST_SEL_X = SQ_SEL_X
>                             DST_SEL_Y = SQ_SEL_Y
>                             DST_SEL_Z = SQ_SEL_Z
>                             DST_SEL_W = SQ_SEL_W
>                             NUM_FORMAT = BUF_NUM_FORMAT_FLOAT
>                             DATA_FORMAT = BUF_DATA_FORMAT_32
>                             ELEMENT_SIZE = 0
>                             INDEX_STRIDE = 0
>                             ADD_TID_ENABLE = 0
>                             ATC = 0
>                             HASH_ENABLE = 0
>                             HEAP = 0
>                             MTYPE = 0
>                             TYPE = SQ_RSRC_BUF
>
>[1;32mRW buffers slot 2 (GPU list):[0m
>        [1;33mSQ_BUF_RSRC_WORD0[0m <- 0x35800000
>        [1;33mSQ_BUF_RSRC_WORD1[0m <- BASE_ADDRESS_HI = 1
>                             STRIDE = 0
>                             CACHE_SWIZZLE = 0
>                             SWIZZLE_ENABLE = 0
>        [1;33mSQ_BUF_RSRC_WORD2[0m <- 0x02500000
>        [1;33mSQ_BUF_RSRC_WORD3[0m <- DST_SEL_X = SQ_SEL_X
>                             DST_SEL_Y = SQ_SEL_Y
>                             DST_SEL_Z = SQ_SEL_Z
>                             DST_SEL_W = SQ_SEL_W
>                             NUM_FORMAT = BUF_NUM_FORMAT_FLOAT
>                             DATA_FORMAT = BUF_DATA_FORMAT_32
>                             ELEMENT_SIZE = 0
>                             INDEX_STRIDE = 0
>                             ADD_TID_ENABLE = 0
>                             ATC = 0
>                             HASH_ENABLE = 0
>                             HEAP = 0
>                             MTYPE = 0
>                             TYPE = SQ_RSRC_BUF
>
>[1;32mRW buffers slot 3 (GPU list):[0m
>        [1;33mSQ_BUF_RSRC_WORD0[0m <- 0
>        [1;33mSQ_BUF_RSRC_WORD1[0m <- BASE_ADDRESS_HI = 0
>                             STRIDE = 0
>                             CACHE_SWIZZLE = 0
>                             SWIZZLE_ENABLE = 0
>        [1;33mSQ_BUF_RSRC_WORD2[0m <- 0
>        [1;33mSQ_BUF_RSRC_WORD3[0m <- DST_SEL_X = SQ_SEL_0
>                             DST_SEL_Y = SQ_SEL_0
>                             DST_SEL_Z = SQ_SEL_0
>                             DST_SEL_W = SQ_SEL_0
>                             NUM_FORMAT = BUF_NUM_FORMAT_UNORM
>                             DATA_FORMAT = BUF_DATA_FORMAT_INVALID
>                             ELEMENT_SIZE = 0
>                             INDEX_STRIDE = 0
>                             ADD_TID_ENABLE = 0
>                             ATC = 0
>                             HASH_ENABLE = 0
>                             HEAP = 0
>                             MTYPE = 0
>                             TYPE = SQ_RSRC_BUF
>
>[1;32mRW buffers slot 4 (GPU list):[0m
>        [1;33mSQ_BUF_RSRC_WORD0[0m <- 0
>        [1;33mSQ_BUF_RSRC_WORD1[0m <- BASE_ADDRESS_HI = 0
>                             STRIDE = 0
>                             CACHE_SWIZZLE = 0
>                             SWIZZLE_ENABLE = 0
>        [1;33mSQ_BUF_RSRC_WORD2[0m <- 0
>        [1;33mSQ_BUF_RSRC_WORD3[0m <- DST_SEL_X = SQ_SEL_0
>                             DST_SEL_Y = SQ_SEL_0
>                             DST_SEL_Z = SQ_SEL_0
>                             DST_SEL_W = SQ_SEL_0
>                             NUM_FORMAT = BUF_NUM_FORMAT_UNORM
>                             DATA_FORMAT = BUF_DATA_FORMAT_INVALID
>                             ELEMENT_SIZE = 0
>                             INDEX_STRIDE = 0
>                             ADD_TID_ENABLE = 0
>                             ATC = 0
>                             HASH_ENABLE = 0
>                             HEAP = 0
>                             MTYPE = 0
>                             TYPE = SQ_RSRC_BUF
>
>[1;32mRW buffers slot 5 (GPU list):[0m
>        [1;33mSQ_BUF_RSRC_WORD0[0m <- 0
>        [1;33mSQ_BUF_RSRC_WORD1[0m <- BASE_ADDRESS_HI = 0
>                             STRIDE = 0
>                             CACHE_SWIZZLE = 0
>                             SWIZZLE_ENABLE = 0
>        [1;33mSQ_BUF_RSRC_WORD2[0m <- 0
>        [1;33mSQ_BUF_RSRC_WORD3[0m <- DST_SEL_X = SQ_SEL_0
>                             DST_SEL_Y = SQ_SEL_0
>                             DST_SEL_Z = SQ_SEL_0
>                             DST_SEL_W = SQ_SEL_0
>                             NUM_FORMAT = BUF_NUM_FORMAT_UNORM
>                             DATA_FORMAT = BUF_DATA_FORMAT_INVALID
>                             ELEMENT_SIZE = 0
>                             INDEX_STRIDE = 0
>                             ADD_TID_ENABLE = 0
>                             ATC = 0
>                             HASH_ENABLE = 0
>                             HEAP = 0
>                             MTYPE = 0
>                             TYPE = SQ_RSRC_BUF
>
>[1;32mRW buffers slot 6 (GPU list):[0m
>        [1;33mSQ_BUF_RSRC_WORD0[0m <- 0
>        [1;33mSQ_BUF_RSRC_WORD1[0m <- BASE_ADDRESS_HI = 0
>                             STRIDE = 0
>                             CACHE_SWIZZLE = 0
>                             SWIZZLE_ENABLE = 0
>        [1;33mSQ_BUF_RSRC_WORD2[0m <- 0
>        [1;33mSQ_BUF_RSRC_WORD3[0m <- DST_SEL_X = SQ_SEL_0
>                             DST_SEL_Y = SQ_SEL_0
>                             DST_SEL_Z = SQ_SEL_0
>                             DST_SEL_W = SQ_SEL_0
>                             NUM_FORMAT = BUF_NUM_FORMAT_UNORM
>                             DATA_FORMAT = BUF_DATA_FORMAT_INVALID
>                             ELEMENT_SIZE = 0
>                             INDEX_STRIDE = 0
>                             ADD_TID_ENABLE = 0
>                             ATC = 0
>                             HASH_ENABLE = 0
>                             HEAP = 0
>                             MTYPE = 0
>                             TYPE = SQ_RSRC_BUF
>
>[1;32mRW buffers slot 7 (GPU list):[0m
>        [1;33mSQ_BUF_RSRC_WORD0[0m <- 0x015304c0
>        [1;33mSQ_BUF_RSRC_WORD1[0m <- BASE_ADDRESS_HI = 0
>                             STRIDE = 0
>                             CACHE_SWIZZLE = 0
>                             SWIZZLE_ENABLE = 0
>        [1;33mSQ_BUF_RSRC_WORD2[0m <- 32 (0x00000020)
>        [1;33mSQ_BUF_RSRC_WORD3[0m <- DST_SEL_X = SQ_SEL_X
>                             DST_SEL_Y = SQ_SEL_Y
>                             DST_SEL_Z = SQ_SEL_Z
>                             DST_SEL_W = SQ_SEL_W
>                             NUM_FORMAT = BUF_NUM_FORMAT_FLOAT
>                             DATA_FORMAT = BUF_DATA_FORMAT_32
>                             ELEMENT_SIZE = 0
>                             INDEX_STRIDE = 0
>                             ADD_TID_ENABLE = 0
>                             ATC = 0
>                             HASH_ENABLE = 0
>                             HEAP = 0
>                             MTYPE = 0
>                             TYPE = SQ_RSRC_BUF
>
>[1;32mRW buffers slot 8 (GPU list):[0m
>        [1;33mSQ_BUF_RSRC_WORD0[0m <- 0
>        [1;33mSQ_BUF_RSRC_WORD1[0m <- BASE_ADDRESS_HI = 0
>                             STRIDE = 0
>                             CACHE_SWIZZLE = 0
>                             SWIZZLE_ENABLE = 0
>        [1;33mSQ_BUF_RSRC_WORD2[0m <- 0
>        [1;33mSQ_BUF_RSRC_WORD3[0m <- DST_SEL_X = SQ_SEL_0
>                             DST_SEL_Y = SQ_SEL_0
>                             DST_SEL_Z = SQ_SEL_0
>                             DST_SEL_W = SQ_SEL_0
>                             NUM_FORMAT = BUF_NUM_FORMAT_UNORM
>                             DATA_FORMAT = BUF_DATA_FORMAT_INVALID
>                             ELEMENT_SIZE = 0
>                             INDEX_STRIDE = 0
>                             ADD_TID_ENABLE = 0
>                             ATC = 0
>                             HASH_ENABLE = 0
>                             HEAP = 0
>                             MTYPE = 0
>                             TYPE = SQ_RSRC_BUF
>
>[1;32mRW buffers slot 9 (GPU list):[0m
>        [1;33mSQ_BUF_RSRC_WORD0[0m <- 0
>        [1;33mSQ_BUF_RSRC_WORD1[0m <- BASE_ADDRESS_HI = 0
>                             STRIDE = 0
>                             CACHE_SWIZZLE = 0
>                             SWIZZLE_ENABLE = 0
>        [1;33mSQ_BUF_RSRC_WORD2[0m <- 0
>        [1;33mSQ_BUF_RSRC_WORD3[0m <- DST_SEL_X = SQ_SEL_0
>                             DST_SEL_Y = SQ_SEL_0
>                             DST_SEL_Z = SQ_SEL_0
>                             DST_SEL_W = SQ_SEL_0
>                             NUM_FORMAT = BUF_NUM_FORMAT_UNORM
>                             DATA_FORMAT = BUF_DATA_FORMAT_INVALID
>                             ELEMENT_SIZE = 0
>                             INDEX_STRIDE = 0
>                             ADD_TID_ENABLE = 0
>                             ATC = 0
>                             HASH_ENABLE = 0
>                             HEAP = 0
>                             MTYPE = 0
>                             TYPE = SQ_RSRC_BUF
>
>[1;32mRW buffers slot 10 (GPU list):[0m
>        [1;33mSQ_BUF_RSRC_WORD0[0m <- 0x01530440
>        [1;33mSQ_BUF_RSRC_WORD1[0m <- BASE_ADDRESS_HI = 0
>                             STRIDE = 0
>                             CACHE_SWIZZLE = 0
>                             SWIZZLE_ENABLE = 0
>        [1;33mSQ_BUF_RSRC_WORD2[0m <- 128 (0x00000080)
>        [1;33mSQ_BUF_RSRC_WORD3[0m <- DST_SEL_X = SQ_SEL_X
>                             DST_SEL_Y = SQ_SEL_Y
>                             DST_SEL_Z = SQ_SEL_Z
>                             DST_SEL_W = SQ_SEL_W
>                             NUM_FORMAT = BUF_NUM_FORMAT_FLOAT
>                             DATA_FORMAT = BUF_DATA_FORMAT_32
>                             ELEMENT_SIZE = 0
>                             INDEX_STRIDE = 0
>                             ADD_TID_ENABLE = 0
>                             ATC = 0
>                             HASH_ENABLE = 0
>                             HEAP = 0
>                             MTYPE = 0
>                             TYPE = SQ_RSRC_BUF
>
>[1;32mRW buffers slot 11 (GPU list):[0m
>        [1;33mSQ_BUF_RSRC_WORD0[0m <- 0x00100000
>        [1;33mSQ_BUF_RSRC_WORD1[0m <- BASE_ADDRESS_HI = 0
>                             STRIDE = 0
>                             CACHE_SWIZZLE = 0
>                             SWIZZLE_ENABLE = 0
>        [1;33mSQ_BUF_RSRC_WORD2[0m <- 8
>        [1;33mSQ_BUF_RSRC_WORD3[0m <- DST_SEL_X = SQ_SEL_X
>                             DST_SEL_Y = SQ_SEL_Y
>                             DST_SEL_Z = SQ_SEL_Z
>                             DST_SEL_W = SQ_SEL_W
>                             NUM_FORMAT = BUF_NUM_FORMAT_FLOAT
>                             DATA_FORMAT = BUF_DATA_FORMAT_32
>                             ELEMENT_SIZE = 0
>                             INDEX_STRIDE = 0
>                             ADD_TID_ENABLE = 0
>                             ATC = 0
>                             HASH_ENABLE = 0
>                             HEAP = 0
>                             MTYPE = 0
>                             TYPE = SQ_RSRC_BUF
>
>[1;32mRW buffers slot 12 (GPU list):[0m
>        [1;33mSQ_BUF_RSRC_WORD0[0m <- 0
>        [1;33mSQ_BUF_RSRC_WORD1[0m <- BASE_ADDRESS_HI = 0
>                             STRIDE = 0
>                             CACHE_SWIZZLE = 0
>                             SWIZZLE_ENABLE = 0
>        [1;33mSQ_BUF_RSRC_WORD2[0m <- 0
>        [1;33mSQ_BUF_RSRC_WORD3[0m <- DST_SEL_X = SQ_SEL_0
>                             DST_SEL_Y = SQ_SEL_0
>                             DST_SEL_Z = SQ_SEL_0
>                             DST_SEL_W = SQ_SEL_0
>                             NUM_FORMAT = BUF_NUM_FORMAT_UNORM
>                             DATA_FORMAT = BUF_DATA_FORMAT_INVALID
>                             ELEMENT_SIZE = 0
>                             INDEX_STRIDE = 0
>                             ADD_TID_ENABLE = 0
>                             ATC = 0
>                             HASH_ENABLE = 0
>                             HEAP = 0
>                             MTYPE = 0
>                             TYPE = SQ_RSRC_BUF
>
>[1;32mRW buffers slot 13 (GPU list):[0m
>        [1;33mSQ_BUF_RSRC_WORD0[0m <- 0
>        [1;33mSQ_BUF_RSRC_WORD1[0m <- BASE_ADDRESS_HI = 0
>                             STRIDE = 0
>                             CACHE_SWIZZLE = 0
>                             SWIZZLE_ENABLE = 0
>        [1;33mSQ_BUF_RSRC_WORD2[0m <- 0
>        [1;33mSQ_BUF_RSRC_WORD3[0m <- DST_SEL_X = SQ_SEL_0
>                             DST_SEL_Y = SQ_SEL_0
>                             DST_SEL_Z = SQ_SEL_0
>                             DST_SEL_W = SQ_SEL_0
>                             NUM_FORMAT = BUF_NUM_FORMAT_UNORM
>                             DATA_FORMAT = BUF_DATA_FORMAT_INVALID
>                             ELEMENT_SIZE = 0
>                             INDEX_STRIDE = 0
>                             ADD_TID_ENABLE = 0
>                             ATC = 0
>                             HASH_ENABLE = 0
>                             HEAP = 0
>                             MTYPE = 0
>                             TYPE = SQ_RSRC_BUF
>
>[1;32mRW buffers slot 14 (GPU list):[0m
>        [1;33mSQ_BUF_RSRC_WORD0[0m <- 0
>        [1;33mSQ_BUF_RSRC_WORD1[0m <- BASE_ADDRESS_HI = 0
>                             STRIDE = 0
>                             CACHE_SWIZZLE = 0
>                             SWIZZLE_ENABLE = 0
>        [1;33mSQ_BUF_RSRC_WORD2[0m <- 0
>        [1;33mSQ_BUF_RSRC_WORD3[0m <- DST_SEL_X = SQ_SEL_0
>                             DST_SEL_Y = SQ_SEL_0
>                             DST_SEL_Z = SQ_SEL_0
>                             DST_SEL_W = SQ_SEL_0
>                             NUM_FORMAT = BUF_NUM_FORMAT_UNORM
>                             DATA_FORMAT = BUF_DATA_FORMAT_INVALID
>                             ELEMENT_SIZE = 0
>                             INDEX_STRIDE = 0
>                             ADD_TID_ENABLE = 0
>                             ATC = 0
>                             HASH_ENABLE = 0
>                             HEAP = 0
>                             MTYPE = 0
>                             TYPE = SQ_RSRC_BUF
>
>[1;32mRW buffers slot 15 (GPU list):[0m
>        [1;33mSQ_BUF_RSRC_WORD0[0m <- 0
>        [1;33mSQ_BUF_RSRC_WORD1[0m <- BASE_ADDRESS_HI = 0
>                             STRIDE = 0
>                             CACHE_SWIZZLE = 0
>                             SWIZZLE_ENABLE = 0
>        [1;33mSQ_BUF_RSRC_WORD2[0m <- 0
>        [1;33mSQ_BUF_RSRC_WORD3[0m <- DST_SEL_X = SQ_SEL_0
>                             DST_SEL_Y = SQ_SEL_0
>                             DST_SEL_Z = SQ_SEL_0
>                             DST_SEL_W = SQ_SEL_0
>                             NUM_FORMAT = BUF_NUM_FORMAT_UNORM
>                             DATA_FORMAT = BUF_DATA_FORMAT_INVALID
>                             ELEMENT_SIZE = 0
>                             INDEX_STRIDE = 0
>                             ADD_TID_ENABLE = 0
>                             ATC = 0
>                             HASH_ENABLE = 0
>                             HEAP = 0
>                             MTYPE = 0
>                             TYPE = SQ_RSRC_BUF
>
>[1;32mVS - Vertex buffer slot 0 (GPU list):[0m
>        [1;33mSQ_BUF_RSRC_WORD0[0m <- 0x09040000
>        [1;33mSQ_BUF_RSRC_WORD1[0m <- BASE_ADDRESS_HI = 1
>                             STRIDE = 32 (0x020)
>                             CACHE_SWIZZLE = 0
>                             SWIZZLE_ENABLE = 0
>        [1;33mSQ_BUF_RSRC_WORD2[0m <- 0x000bdc00
>        [1;33mSQ_BUF_RSRC_WORD3[0m <- DST_SEL_X = SQ_SEL_X
>                             DST_SEL_Y = SQ_SEL_Y
>                             DST_SEL_Z = SQ_SEL_0
>                             DST_SEL_W = SQ_SEL_1
>                             NUM_FORMAT = BUF_NUM_FORMAT_FLOAT
>                             DATA_FORMAT = BUF_DATA_FORMAT_32_32
>                             ELEMENT_SIZE = 0
>                             INDEX_STRIDE = 0
>                             ADD_TID_ENABLE = 0
>                             ATC = 0
>                             HASH_ENABLE = 0
>                             HEAP = 0
>                             MTYPE = 0
>                             TYPE = SQ_RSRC_BUF
>
>------------------ IB begin ------------------
>c0055000 [1;32mDMA_DATA[0m:
>80000000         [1;33mDMA_DATA_WORD0[0m <- CP_SYNC = 1
>                                   SRC_SEL = SRC_ADDR
>                                   DST_SEL = DST_ADDR
>                                   ENGINE = ME
>00000000         [1;33mSRC_ADDR_LO[0m <- 0
>00000000         [1;33mSRC_ADDR_HI[0m <- 0
>00000000         [1;33mDST_ADDR_LO[0m <- 0
>00000000         [1;33mDST_ADDR_HI[0m <- 0
>00000000         [1;33mCOMMAND[0m <- BYTE_COUNT_GFX6 = 0
>                            BYTE_COUNT_GFX9 = 0
>                            DISABLE_WR_CONFIRM_GFX6 = 0
>                            SRC_SWAP = NONE
>                            DST_SWAP = NONE
>                            SAS = MEMORY
>                            DAS = MEMORY
>                            SAIC = INCREMENT
>                            DAIC = INCREMENT
>                            RAW_WAIT = 0
>                            DISABLE_WR_CONFIRM_GFX9 = 0
>c0044700 [1;32mEVENT_WRITE_EOP[0m:
>0000052d         [1;33mVGT_EVENT_INITIATOR[0m <- EVENT_TYPE = FLUSH_AND_INV_CB_DATA_TS
>                 [1;33mEVENT_INDEX[0m <- 5
>                 [1;33mTCL1_VOL_ACTION_ENA[0m <- 0
>                 [1;33mTC_VOL_ACTION_ENA[0m <- 0
>                 [1;33mTC_WB_ACTION_ENA[0m <- 0
>                 [1;33mTCL1_ACTION_ENA[0m <- 0
>                 [1;33mTC_ACTION_ENA[0m <- 0
>00000400         [1;33mADDRESS_LO[0m <- 1024 (0x00000400)
>00000001         [1;33mADDRESS_HI[0m <- 1
>                 [1;33mDST_SEL[0m <- 0
>                 [1;33mINT_SEL[0m <- 0
>                 [1;33mDATA_SEL[0m <- 0
>00000000         [1;33mDATA_LO[0m <- 0
>00000000         [1;33mDATA_HI[0m <- 0
>c0044700 [1;32mEVENT_WRITE_EOP[0m:
>0000052d         [1;33mVGT_EVENT_INITIATOR[0m <- EVENT_TYPE = FLUSH_AND_INV_CB_DATA_TS
>                 [1;33mEVENT_INDEX[0m <- 5
>                 [1;33mTCL1_VOL_ACTION_ENA[0m <- 0
>                 [1;33mTC_VOL_ACTION_ENA[0m <- 0
>                 [1;33mTC_WB_ACTION_ENA[0m <- 0
>                 [1;33mTCL1_ACTION_ENA[0m <- 0
>                 [1;33mTC_ACTION_ENA[0m <- 0
>00000000         [1;33mADDRESS_LO[0m <- 0
>00000000         [1;33mADDRESS_HI[0m <- 0
>                 [1;33mDST_SEL[0m <- 0
>                 [1;33mINT_SEL[0m <- 0
>                 [1;33mDATA_SEL[0m <- 0
>00000000         [1;33mDATA_LO[0m <- 0
>00000000         [1;33mDATA_HI[0m <- 0
>c0004600 [1;32mEVENT_WRITE[0m:
>0000002e         [1;33mVGT_EVENT_INITIATOR[0m <- EVENT_TYPE = FLUSH_AND_INV_CB_META
>                 [1;33mEVENT_INDEX[0m <- 0
>                 [1;33mINV_L2[0m <- 0
>c0004200 [1;32mPFP_SYNC_ME[0m:
>00000000 
>c0034300 [1;32mSURFACE_SYNC[0m:
>02c43fc0         [1;33mCP_COHER_CNTL[0m <- DEST_BASE_0_ENA = 0
>                                  DEST_BASE_1_ENA = 0
>                                  TC_SD_ACTION_ENA = 0
>                                  TC_NC_ACTION_ENA = 0
>                                  CB0_DEST_BASE_ENA = 1
>                                  CB1_DEST_BASE_ENA = 1
>                                  CB2_DEST_BASE_ENA = 1
>                                  CB3_DEST_BASE_ENA = 1
>                                  CB4_DEST_BASE_ENA = 1
>                                  CB5_DEST_BASE_ENA = 1
>                                  CB6_DEST_BASE_ENA = 1
>                                  CB7_DEST_BASE_ENA = 1
>                                  DB_DEST_BASE_ENA = 0
>                                  TCL1_VOL_ACTION_ENA = 0
>                                  TC_VOL_ACTION_ENA = 0
>                                  TC_WB_ACTION_ENA = 1
>                                  DEST_BASE_2_ENA = 0
>                                  DEST_BASE_3_ENA = 0
>                                  TCL1_ACTION_ENA = 1
>                                  TC_ACTION_ENA = 1
>                                  CB_ACTION_ENA = 1
>                                  DB_ACTION_ENA = 0
>                                  SH_KCACHE_ACTION_ENA = 0
>                                  SH_KCACHE_VOL_ACTION_ENA = 0
>                                  SH_ICACHE_ACTION_ENA = 0
>                                  SH_KCACHE_WB_ACTION_ENA = 0
>                                  SH_SD_ACTION_ENA = 0
>ffffffff         [1;33mCP_COHER_SIZE[0m <- 0xffffffff
>00000000         [1;33mCP_COHER_BASE[0m <- 0
>0000000a         [1;33mPOLL_INTERVAL[0m <- 10 (0x000a)
>c0004600 [1;32mEVENT_WRITE[0m:
>00000019         [1;33mVGT_EVENT_INITIATOR[0m <- EVENT_TYPE = PIPELINESTAT_START
>                 [1;33mEVENT_INDEX[0m <- 0
>                 [1;33mINV_L2[0m <- 0
>c0033700 [1;32mWRITE_DATA[0m:
>00100100         [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                            WR_CONFIRM = 1
>                            WR_ONE_ADDR = 0
>                            DST_SEL = MEMORY_SYNC
>00065000         [1;33mDST_ADDR_LO[0m <- 0x00065000
>00000001         [1;33mDST_ADDR_HI[0m <- 1
>00000003 
>c0001000 [1;32mNOP[0m:
>                 [31mTrace point ID: 3
>                 [31m!!!!! This is the last trace point that was reached by the CP !!!!![0m
>cafe0003 
>------------------- IB end -------------------
>
>Flushing. Time: 332.014504s
>
>Buffer list (in units of pages = 4kB):
>[1;33m        Size    VM start page         VM end page           Usage[0m
>          32    0x0000000000100       0x0000000000120       SHADER_RINGS
>         512    -- hole --
>          32    0x0000000000320       0x0000000000340       CONST_BUFFER
>          32    0x0000000000340       0x0000000000360       DESCRIPTORS
>        4544    -- hole --
>          32    0x0000000001520       0x0000000001540       DESCRIPTORS, SHADER_RINGS
>     1043136    -- hole --
>          32    0x0000000100000       0x0000000100020       QUERY, IB2, SHADER_BINARY
>          32    0x0000000100020       0x0000000100040       IB1
>          32    0x0000000100040       0x0000000100060       BORDER_COLORS
>          32    0x0000000100060       0x0000000100080       TRACE
>         320    -- hole --
>          32    0x00000001001C0       0x00000001001E0       QUERY
>        8032    -- hole --
>          32    0x0000000102140       0x0000000102160       SAMPLER_TEXTURE
>          32    -- hole --
>          32    0x0000000102180       0x00000001021A0       SAMPLER_TEXTURE
>          32    -- hole --
>          32    0x00000001021C0       0x00000001021E0       SAMPLER_TEXTURE
>          32    -- hole --
>         514    0x0000000102200       0x0000000102402       SAMPLER_TEXTURE
>         425    -- hole --
>          17    0x00000001025AB       0x00000001025BC       SAMPLER_TEXTURE
>           4    -- hole --
>          32    0x00000001025C0       0x00000001025E0       SAMPLER_TEXTURE
>         273    0x00000001025E0       0x00000001026F1       SAMPLER_TEXTURE
>         297    -- hole --
>          17    0x000000010281A       0x000000010282B       SAMPLER_TEXTURE
>          20    -- hole --
>          17    0x000000010283F       0x0000000102850       SAMPLER_TEXTURE
>          20    -- hole --
>          17    0x0000000102864       0x0000000102875       SAMPLER_TEXTURE
>          20    -- hole --
>          17    0x0000000102889       0x000000010289A       SAMPLER_TEXTURE
>          20    -- hole --
>          17    0x00000001028AE       0x00000001028BF       SAMPLER_TEXTURE
>          20    -- hole --
>          17    0x00000001028D3       0x00000001028E4       SAMPLER_TEXTURE
>          20    -- hole --
>          17    0x00000001028F8       0x0000000102909       SAMPLER_TEXTURE
>          20    -- hole --
>          17    0x000000010291D       0x000000010292E       SAMPLER_TEXTURE
>          20    -- hole --
>          17    0x0000000102942       0x0000000102953       SAMPLER_TEXTURE
>          20    -- hole --
>          17    0x0000000102967       0x0000000102978       SAMPLER_TEXTURE
>          20    -- hole --
>          17    0x000000010298C       0x000000010299D       SAMPLER_TEXTURE
>          20    -- hole --
>          17    0x00000001029B1       0x00000001029C2       SAMPLER_TEXTURE
>          20    -- hole --
>          17    0x00000001029D6       0x00000001029E7       SAMPLER_TEXTURE
>          25    -- hole --
>         579    0x0000000102A00       0x0000000102C43       SAMPLER_TEXTURE
>          17    0x0000000102C43       0x0000000102C54       SAMPLER_TEXTURE
>          20    -- hole --
>          17    0x0000000102C68       0x0000000102C79       SAMPLER_TEXTURE
>          20    -- hole --
>          17    0x0000000102C8D       0x0000000102C9E       SAMPLER_TEXTURE
>          20    -- hole --
>          17    0x0000000102CB2       0x0000000102CC3       SAMPLER_TEXTURE
>          61    -- hole --
>          65    0x0000000102D00       0x0000000102D41       SAMPLER_TEXTURE
>        5375    -- hole --
>         129    0x0000000104240       0x00000001042C1       SAMPLER_TEXTURE
>          15    -- hole --
>         129    0x00000001042D0       0x0000000104351       SAMPLER_TEXTURE, COLOR_BUFFER
>          15    -- hole --
>         129    0x0000000104360       0x00000001043E1       SAMPLER_TEXTURE
>          31    -- hole --
>        2169    0x0000000104400       0x0000000104C79       SAMPLER_TEXTURE
>           7    -- hole --
>         129    0x0000000104C80       0x0000000104D01       SAMPLER_TEXTURE
>          15    -- hole --
>         129    0x0000000104D10       0x0000000104D91       SAMPLER_TEXTURE
>         256    0x0000000104D91       0x0000000104E91       CP_DMA
>       16815    -- hole --
>         190    0x0000000109040       0x00000001090FE       VERTEX_BUFFER
>         130    -- hole --
>          32    0x0000000109180       0x00000001091A0       CP_DMA, CONST_BUFFER
>        2144    -- hole --
>        2169    0x0000000109A00       0x000000010A279       SAMPLER_TEXTURE
>         384    0x000000010A279       0x000000010A3F9       SHADER_RINGS
>        2055    -- hole --
>        2169    0x000000010AC00       0x000000010B479       SAMPLER_TEXTURE
>        2439    -- hole --
>        2169    0x000000010BE00       0x000000010C679       SAMPLER_TEXTURE
>       69511    -- hole --
>         570    0x000000011D600       0x000000011D83A       SHADER_RW_BUFFER
>        2758    -- hole --
>          32    0x000000011E300       0x000000011E320       SAMPLER_TEXTURE
>          32    -- hole --
>          32    0x000000011E340       0x000000011E360       SAMPLER_TEXTURE
>          32    0x000000011E360       0x000000011E380       SAMPLER_TEXTURE
>          79    -- hole --
>          40    0x000000011E3CF       0x000000011E3F7       SAMPLER_TEXTURE
>        3625    -- hole --
>         432    0x000000011F220       0x000000011F3D0       SHADER_RW_BUFFER
>          16    -- hole --
>          32    0x000000011F3E0       0x000000011F400       SAMPLER_TEXTURE
>        3600    -- hole --
>         257    0x0000000120210       0x0000000120311       SAMPLER_TEXTURE
>          15    -- hole --
>         193    0x0000000120320       0x00000001203E1       SAMPLER_TEXTURE
>          31    -- hole --
>        2169    0x0000000120400       0x0000000120C79       SAMPLER_TEXTURE
>         327    -- hole --
>          32    0x0000000120DC0       0x0000000120DE0       SAMPLER_TEXTURE
>          32    0x0000000120DE0       0x0000000120E00       SAMPLER_TEXTURE
>        7312    -- hole --
>         257    0x0000000122A90       0x0000000122B91       SAMPLER_TEXTURE
>         106    0x0000000122B91       0x0000000122BFB       SAMPLER_TEXTURE
>           5    -- hole --
>         643    0x0000000122C00       0x0000000122E83       SAMPLER_TEXTURE
>         356    -- hole --
>          21    0x0000000122FE7       0x0000000122FFC       SAMPLER_TEXTURE
>        1839    -- hole --
>         106    0x000000012372B       0x0000000123795       SAMPLER_TEXTURE
>          11    -- hole --
>          32    0x00000001237A0       0x00000001237C0       SAMPLER_TEXTURE
>          32    0x00000001237C0       0x00000001237E0       SAMPLER_TEXTURE
>        4480    -- hole --
>          32    0x0000000124960       0x0000000124980       SAMPLER_TEXTURE
>          32    -- hole --
>          32    0x00000001249A0       0x00000001249C0       SAMPLER_TEXTURE
>          64    -- hole --
>        2169    0x0000000124A00       0x0000000125279       SAMPLER_TEXTURE
>          39    -- hole --
>         322    0x00000001252A0       0x00000001253E2       SAMPLER_TEXTURE
>          30    0x00000001253E2       0x0000000125400       SAMPLER_TEXTURE
>        4337    -- hole --
>          74    0x00000001264F1       0x000000012653B       SAMPLER_TEXTURE
>          75    0x000000012653B       0x0000000126586       SAMPLER_TEXTURE
>          90    -- hole --
>          32    0x00000001265E0       0x0000000126600       SAMPLER_TEXTURE
>        2025    -- hole --
>          21    0x0000000126DE9       0x0000000126DFE       SAMPLER_TEXTURE
>        1218    -- hole --
>         241    0x00000001272C0       0x00000001273B1       SAMPLER_TEXTURE
>          47    -- hole --
>          32    0x00000001273E0       0x0000000127400       SAMPLER_TEXTURE
>         643    0x0000000127400       0x0000000127683       SAMPLER_TEXTURE
>        2093    -- hole --
>         241    0x0000000127EB0       0x0000000127FA1       SAMPLER_TEXTURE
>          81    0x0000000127FA1       0x0000000127FF2       SAMPLER_TEXTURE
>        2574    -- hole --
>        1028    0x0000000128A00       0x0000000128E04       SAMPLER_TEXTURE
>         398    -- hole --
>          74    0x0000000128F92       0x0000000128FDC       SAMPLER_TEXTURE
>          35    0x0000000128FDC       0x0000000128FFF       SAMPLER_TEXTURE
>        2065    -- hole --
>         402    0x0000000129810       0x00000001299A2       SAMPLER_TEXTURE
>        1646    -- hole --
>         402    0x000000012A010       0x000000012A1A2       SAMPLER_TEXTURE
>          75    0x000000012A1A2       0x000000012A1ED       SAMPLER_TEXTURE
>         547    -- hole --
>         322    0x000000012A410       0x000000012A552       SAMPLER_TEXTURE
>          80    -- hole --
>          37    0x000000012A5A2       0x000000012A5C7       SAMPLER_TEXTURE
>          38    0x000000012A5C7       0x000000012A5ED       SAMPLER_TEXTURE
>        2552    -- hole --
>          21    0x000000012AFE5       0x000000012AFFA       SAMPLER_TEXTURE
>           6    -- hole --
>        1028    0x000000012B000       0x000000012B404       SAMPLER_TEXTURE
>          12    -- hole --
>         241    0x000000012B410       0x000000012B501       SAMPLER_TEXTURE
>        2319    -- hole --
>         241    0x000000012BE10       0x000000012BF01       SAMPLER_TEXTURE
>          15    -- hole --
>         145    0x000000012BF10       0x000000012BFA1       SAMPLER_TEXTURE
>        1087    -- hole --
>          32    0x000000012C3E0       0x000000012C400       SAMPLER_TEXTURE
>         640    -- hole --
>         145    0x000000012C680       0x000000012C711       SAMPLER_TEXTURE
>         111    -- hole --
>          97    0x000000012C780       0x000000012C7E1       SAMPLER_TEXTURE
>         559    -- hole --
>          97    0x000000012CA10       0x000000012CA71       SAMPLER_TEXTURE
>          15    -- hole --
>         241    0x000000012CA80       0x000000012CB71       SAMPLER_TEXTURE
>        1679    -- hole --
>         771    0x000000012D200       0x000000012D503       SAMPLER_TEXTURE
>         221    -- hole --
>          32    0x000000012D5E0       0x000000012D600       SAMPLER_TEXTURE
>        1414    -- hole --
>          37    0x000000012DB86       0x000000012DBAB       SAMPLER_TEXTURE
>          42    -- hole --
>          38    0x000000012DBD5       0x000000012DBFB       SAMPLER_TEXTURE
>         693    -- hole --
>         145    0x000000012DEB0       0x000000012DF41       SAMPLER_TEXTURE
>          15    -- hole --
>         145    0x000000012DF50       0x000000012DFE1       SAMPLER_TEXTURE
>          21    0x000000012DFE1       0x000000012DFF6       SAMPLER_TEXTURE
>        1082    -- hole --
>          97    0x000000012E430       0x000000012E491       SAMPLER_TEXTURE
>          79    -- hole --
>          97    0x000000012E4E0       0x000000012E541       SAMPLER_TEXTURE
>        1215    -- hole --
>         643    0x000000012EA00       0x000000012EC83       SAMPLER_TEXTURE
>          13    -- hole --
>         241    0x000000012EC90       0x000000012ED81       SAMPLER_TEXTURE
>         911    -- hole --
>         145    0x000000012F110       0x000000012F1A1       SAMPLER_TEXTURE
>          37    0x000000012F1A1       0x000000012F1C6       SAMPLER_TEXTURE
>          58    -- hole --
>         643    0x000000012F200       0x000000012F483       SAMPLER_TEXTURE
>          13    -- hole --
>         145    0x000000012F490       0x000000012F521       SAMPLER_TEXTURE
>          38    0x000000012F521       0x000000012F547       SAMPLER_TEXTURE
>          57    -- hole --
>          97    0x000000012F580       0x000000012F5E1       SAMPLER_TEXTURE
>         671    -- hole --
>          97    0x000000012F880       0x000000012F8E1       SAMPLER_TEXTURE
>          79    -- hole --
>         241    0x000000012F930       0x000000012FA21       SAMPLER_TEXTURE
>         223    -- hole --
>         145    0x000000012FB00       0x000000012FB91       SAMPLER_TEXTURE
>         127    -- hole --
>         145    0x000000012FC10       0x000000012FCA1       SAMPLER_TEXTURE
>         111    -- hole --
>          37    0x000000012FD10       0x000000012FD35       SAMPLER_TEXTURE
>          42    -- hole --
>          38    0x000000012FD5F       0x000000012FD85       SAMPLER_TEXTURE
>          43    -- hole --
>          97    0x000000012FDB0       0x000000012FE11       SAMPLER_TEXTURE
>          79    -- hole --
>          97    0x000000012FE60       0x000000012FEC1       SAMPLER_TEXTURE
>          79    -- hole --
>         241    0x000000012FF10       0x0000000130001       SAMPLER_TEXTURE
>         223    -- hole --
>         145    0x00000001300E0       0x0000000130171       SAMPLER_TEXTURE
>         143    -- hole --
>          32    0x0000000130200       0x0000000130220       SAMPLER_TEXTURE
>          32    -- hole --
>         145    0x0000000130240       0x00000001302D1       SAMPLER_TEXTURE
>         111    -- hole --
>          37    0x0000000130340       0x0000000130365       SAMPLER_TEXTURE
>          42    -- hole --
>          38    0x000000013038F       0x00000001303B5       SAMPLER_TEXTURE
>          43    -- hole --
>          97    0x00000001303E0       0x0000000130441       SAMPLER_TEXTURE
>          79    -- hole --
>          97    0x0000000130490       0x00000001304F1       SAMPLER_TEXTURE
>          79    -- hole --
>          32    0x0000000130540       0x0000000130560       SAMPLER_TEXTURE
>         241    0x0000000130560       0x0000000130651       SAMPLER_TEXTURE
>         223    -- hole --
>         145    0x0000000130730       0x00000001307C1       SAMPLER_TEXTURE
>         127    -- hole --
>         145    0x0000000130840       0x00000001308D1       SAMPLER_TEXTURE
>         111    -- hole --
>          37    0x0000000130940       0x0000000130965       SAMPLER_TEXTURE
>          42    -- hole --
>          38    0x000000013098F       0x00000001309B5       SAMPLER_TEXTURE
>          43    -- hole --
>          97    0x00000001309E0       0x0000000130A41       SAMPLER_TEXTURE
>          79    -- hole --
>          97    0x0000000130A90       0x0000000130AF1       SAMPLER_TEXTURE
>          79    -- hole --
>         241    0x0000000130B40       0x0000000130C31       SAMPLER_TEXTURE
>         271    -- hole --
>          32    0x0000000130D40       0x0000000130D60       SAMPLER_TEXTURE
>          64    -- hole --
>          32    0x0000000130DA0       0x0000000130DC0       SAMPLER_TEXTURE
>          64    -- hole --
>        2169    0x0000000130E00       0x0000000131679       SAMPLER_TEXTURE
>          47    0x0000000131679       0x00000001316A8       SAMPLER_TEXTURE
>          48    -- hole --
>          56    0x00000001316D8       0x0000000131710       SAMPLER_TEXTURE
>          57    -- hole --
>          56    0x0000000131749       0x0000000131781       SAMPLER_TEXTURE
>          57    -- hole --
>          56    0x00000001317BA       0x00000001317F2       SAMPLER_TEXTURE
>          14    -- hole --
>         723    0x0000000131800       0x0000000131AD3       SAMPLER_TEXTURE
>          57    -- hole --
>          56    0x0000000131B0C       0x0000000131B44       SAMPLER_TEXTURE
>          57    -- hole --
>          56    0x0000000131B7D       0x0000000131BB5       SAMPLER_TEXTURE
>         683    -- hole --
>          56    0x0000000131E60       0x0000000131E98       SAMPLER_TEXTURE
>          57    -- hole --
>          56    0x0000000131ED1       0x0000000131F09       SAMPLER_TEXTURE
>          57    -- hole --
>          56    0x0000000131F42       0x0000000131F7A       SAMPLER_TEXTURE
>          57    -- hole --
>         107    0x0000000131FB3       0x000000013201E       SAMPLER_TEXTURE
>         110    -- hole --
>         104    0x000000013208C       0x00000001320F4       SAMPLER_TEXTURE
>         124    -- hole --
>          65    0x0000000132170       0x00000001321B1       SAMPLER_TEXTURE
>          60    -- hole --
>          34    0x00000001321ED       0x000000013220F       SAMPLER_TEXTURE
>          34    -- hole --
>          36    0x0000000132231       0x0000000132255       SAMPLER_TEXTURE
>          69    -- hole --
>          21    0x000000013229A       0x00000001322AF       SAMPLER_TEXTURE
>          25    -- hole --
>          21    0x00000001322C8       0x00000001322DD       SAMPLER_TEXTURE
>          25    -- hole --
>          21    0x00000001322F6       0x000000013230B       SAMPLER_TEXTURE
>          25    -- hole --
>          21    0x0000000132324       0x0000000132339       SAMPLER_TEXTURE
>          25    -- hole --
>          21    0x0000000132352       0x0000000132367       SAMPLER_TEXTURE
>          25    -- hole --
>          21    0x0000000132380       0x0000000132395       SAMPLER_TEXTURE
>          25    -- hole --
>          21    0x00000001323AE       0x00000001323C3       SAMPLER_TEXTURE
>          25    -- hole --
>          21    0x00000001323DC       0x00000001323F1       SAMPLER_TEXTURE
>          25    -- hole --
>          21    0x000000013240A       0x000000013241F       SAMPLER_TEXTURE
>          25    -- hole --
>          21    0x0000000132438       0x000000013244D       SAMPLER_TEXTURE
>          25    -- hole --
>          26    0x0000000132466       0x0000000132480       SAMPLER_TEXTURE
>          32    0x0000000132480       0x00000001324A0       SAMPLER_TEXTURE
>          32    -- hole --
>          32    0x00000001324C0       0x00000001324E0       SAMPLER_TEXTURE
>          32    -- hole --
>          32    0x0000000132500       0x0000000132520       SAMPLER_TEXTURE
>          32    -- hole --
>          32    0x0000000132540       0x0000000132560       SAMPLER_TEXTURE
>          32    -- hole --
>          32    0x0000000132580       0x00000001325A0       SAMPLER_TEXTURE
>          32    -- hole --
>          32    0x00000001325C0       0x00000001325E0       SAMPLER_TEXTURE
>          32    -- hole --
>          32    0x0000000132600       0x0000000132620       SAMPLER_TEXTURE
>          32    -- hole --
>          32    0x0000000132640       0x0000000132660       SAMPLER_TEXTURE
>         402    0x0000000132660       0x00000001327F2       SAMPLER_TEXTURE
>         423    -- hole --
>          26    0x0000000132999       0x00000001329B3       SAMPLER_TEXTURE
>          31    -- hole --
>          26    0x00000001329D2       0x00000001329EC       SAMPLER_TEXTURE
>          84    -- hole --
>          32    0x0000000132A40       0x0000000132A60       SAMPLER_TEXTURE
>          32    -- hole --
>          32    0x0000000132A80       0x0000000132AA0       SAMPLER_TEXTURE
>          32    -- hole --
>          32    0x0000000132AC0       0x0000000132AE0       SAMPLER_TEXTURE
>          32    -- hole --
>          32    0x0000000132B00       0x0000000132B20       SAMPLER_TEXTURE
>          32    -- hole --
>          32    0x0000000132B40       0x0000000132B60       SAMPLER_TEXTURE
>          32    -- hole --
>          32    0x0000000132B80       0x0000000132BA0       SAMPLER_TEXTURE
>          32    -- hole --
>          32    0x0000000132BC0       0x0000000132BE0       SAMPLER_TEXTURE
>          32    -- hole --
>          32    0x0000000132C00       0x0000000132C20       SAMPLER_TEXTURE
>          32    -- hole --
>          32    0x0000000132C40       0x0000000132C60       SAMPLER_TEXTURE
>         113    0x0000000132C60       0x0000000132CD1       SAMPLER_TEXTURE
>         143    -- hole --
>          32    0x0000000132D60       0x0000000132D80       SAMPLER_TEXTURE
>         148    0x0000000132D80       0x0000000132E14       SAMPLER_TEXTURE
>         146    -- hole --
>         123    0x0000000132EA6       0x0000000132F21       SAMPLER_TEXTURE
>         223    -- hole --
>         900    0x0000000133000       0x0000000133384       SAMPLER_TEXTURE
>         124    -- hole --
>        2169    0x0000000133400       0x0000000133C79       SAMPLER_TEXTURE
>        2439    -- hole --
>        2169    0x0000000134600       0x0000000134E79       SAMPLER_TEXTURE
>        2439    -- hole --
>        9472    0x0000000135800       0x0000000137D00       SHADER_RINGS
>
>Note: The holes represent memory not used by the IB.
>      Other buffers can still be allocated there.
>
>------------------ IB2: Init config begin ------------------
>c0012800 [1;32mCONTEXT_CONTROL[0m:
>80000000 
>80000000 
>c0001200 [1;32mCLEAR_STATE[0m:
>00000000 
>c0026900 [1;36mSET_CONTEXT_REG[1;36m:
>000000d4 
>16000012         [1;33mPA_SC_RASTER_CONFIG[0m <- RB_MAP_PKR0 = RASTER_CONFIG_RB_MAP_2
>                                        RB_MAP_PKR1 = RASTER_CONFIG_RB_MAP_0
>                                        RB_XSEL2 = RASTER_CONFIG_RB_XSEL2_1
>                                        RB_XSEL = 0
>                                        RB_YSEL = 0
>                                        PKR_MAP = RASTER_CONFIG_PKR_MAP_0
>                                        PKR_XSEL = RASTER_CONFIG_PKR_XSEL_0
>                                        PKR_YSEL = RASTER_CONFIG_PKR_YSEL_0
>                                        PKR_XSEL2 = RASTER_CONFIG_PKR_XSEL2_0
>                                        SC_MAP = RASTER_CONFIG_SC_MAP_0
>                                        SC_XSEL = RASTER_CONFIG_SC_XSEL_8_WIDE_TILE
>                                        SC_YSEL = RASTER_CONFIG_SC_YSEL_8_WIDE_TILE
>                                        SE_MAP = RASTER_CONFIG_SE_MAP_2
>                                        SE_XSEL_GFX6 = RASTER_CONFIG_SE_XSEL_16_WIDE_TILE
>                                        SE_YSEL_GFX6 = RASTER_CONFIG_SE_YSEL_16_WIDE_TILE
>00000000         [1;33mPA_SC_RASTER_CONFIG_1[0m <- SE_PAIR_MAP = RASTER_CONFIG_SE_PAIR_MAP_0
>                                          SE_PAIR_XSEL_GFX6 = RASTER_CONFIG_SE_PAIR_XSEL_8_WIDE_TILE
>                                          SE_PAIR_YSEL_GFX6 = RASTER_CONFIG_SE_PAIR_YSEL_8_WIDE_TILE
>c0016900 [1;36mSET_CONTEXT_REG[1;36m:
>00000286 
>42800000         [1;33mVGT_HOS_MAX_TESS_LEVEL[0m <- 64.0f (0x42800000)
>c0026900 [1;36mSET_CONTEXT_REG[1;36m:
>00000295 
>00000080         [1;33mVGT_GS_PER_ES[0m <- GS_PER_ES = 128 (0x80)
>00000040         [1;33mVGT_ES_PER_GS[0m <- ES_PER_GS = 64 (0x40)
>c0016900 [1;36mSET_CONTEXT_REG[1;36m:
>000002a8 
>00000001         [1;33mVGT_INSTANCE_STEP_RATE_0[0m <- 1
>c0036900 [1;36mSET_CONTEXT_REG[1;36m:
>00000100 
>ffffffff         [1;33mVGT_MAX_VTX_INDX[0m <- 0xffffffff
>00000000         [1;33mVGT_MIN_VTX_INDX[0m <- 0
>00000000         [1;33mVGT_INDX_OFFSET[0m <- 0
>c0017600 [1;36mSET_SH_REG[1;36m:
>00000147 
>003fffff         [1;33mSPI_SHADER_PGM_RSRC3_LS[0m <- CU_EN = 0xffff
>                                            WAVE_LIMIT = 63 (0x3f)
>                                            LOCK_LOW_THRESHOLD = 0
>                                            GROUP_FIFO_DEPTH = 0
>c0017600 [1;36mSET_SH_REG[1;36m:
>00000107 
>0000003f         [1;33mSPI_SHADER_PGM_RSRC3_HS[0m <- WAVE_LIMIT = 63 (0x3f)
>                                            LOCK_LOW_THRESHOLD = 0
>                                            GROUP_FIFO_DEPTH = 0
>c0017600 [1;36mSET_SH_REG[1;36m:
>000000c7 
>003fffff         [1;33mSPI_SHADER_PGM_RSRC3_ES[0m <- CU_EN = 0xffff
>                                            WAVE_LIMIT = 63 (0x3f)
>                                            LOCK_LOW_THRESHOLD = 0
>                                            GROUP_FIFO_DEPTH = 0
>c0016900 [1;36mSET_CONTEXT_REG[1;36m:
>00000291 
>00002040         [1;33mVGT_GS_ONCHIP_CNTL[0m <- ES_VERTS_PER_SUBGRP = 64 (0x40)
>                                       GS_PRIMS_PER_SUBGRP = 4
>c0017600 [1;36mSET_SH_REG[1;36m:
>00000087 
>003fffff         [1;33mSPI_SHADER_PGM_RSRC3_GS[0m <- CU_EN = 0xffff
>                                            WAVE_LIMIT = 63 (0x3f)
>                                            LOCK_LOW_THRESHOLD = 0
>                                            GROUP_FIFO_DEPTH = 0
>c0027600 [1;36mSET_SH_REG[1;36m:
>00000046 
>003ffffe         [1;33mSPI_SHADER_PGM_RSRC3_VS[0m <- CU_EN = 0xfffe
>                                            WAVE_LIMIT = 63 (0x3f)
>                                            LOCK_LOW_THRESHOLD = 0
>00000013         [1;33mSPI_SHADER_LATE_ALLOC_VS[0m <- LIMIT = 19 (0x13)
>c0017600 [1;36mSET_SH_REG[1;36m:
>00000007 
>003fffff         [1;33mSPI_SHADER_PGM_RSRC3_PS[0m <- CU_EN = 0xffff
>                                            WAVE_LIMIT = 63 (0x3f)
>                                            LOCK_LOW_THRESHOLD = 0
>c0016900 [1;36mSET_CONTEXT_REG[1;36m:
>000002d4 
>700b0b20         [1;33mVGT_TESS_DISTRIBUTION[0m <- ACCUM_ISOLINE = 32 (0x20)
>                                          ACCUM_TRI = 11 (0x0b)
>                                          ACCUM_QUAD = 11 (0x0b)
>                                          DONUT_SPLIT = 16 (0x10)
>                                          TRAP_SPLIT = 3
>c0026900 [1;36mSET_CONTEXT_REG[1;36m:
>00000020 
>01000500         [1;33mTA_BC_BASE_ADDR[0m <- 0x01000500
>00000000         [1;33mTA_BC_BASE_ADDR_HI[0m <- ADDRESS = 0
>c0004600 [1;32mEVENT_WRITE[0m:
>0000040f         [1;33mVGT_EVENT_INITIATOR[0m <- EVENT_TYPE = VS_PARTIAL_FLUSH
>                 [1;33mEVENT_INDEX[0m <- 4
>                 [1;33mINV_L2[0m <- 0
>c0004600 [1;32mEVENT_WRITE[0m:
>00000024         [1;33mVGT_EVENT_INITIATOR[0m <- EVENT_TYPE = VGT_FLUSH
>                 [1;33mEVENT_INDEX[0m <- 0
>                 [1;33mINV_L2[0m <- 0
>         
>------------------- IB2: Init config end -------------------
>
>------------------ IB2: Init GS rings begin ------------------
>c0027900 [1;36mSET_UCONFIG_REG[1;36m:
>00000240 
>00001800         [1;33mVGT_ESGS_RING_SIZE[0m <- 6144 (0x00001800)
>00025000         [1;33mVGT_GSVS_RING_SIZE[0m <- 0x00025000
>         
>------------------- IB2: Init GS rings end -------------------
>
>------------------ IB begin ------------------
>c0033700 [1;32mWRITE_DATA[0m:
>00100100         [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                            WR_CONFIRM = 1
>                            WR_ONE_ADDR = 0
>                            DST_SEL = MEMORY_SYNC
>00064e00         [1;33mDST_ADDR_LO[0m <- 0x00064e00
>00000001         [1;33mDST_ADDR_HI[0m <- 1
>00000001 
>c0001000 [1;32mNOP[0m:
>                 [31mTrace point ID: 1
>                 [31mThis trace point was reached by the CP.[0m
>cafe0001 
>------------------- IB end -------------------
>
>------------------ IB begin ------------------
>c0023f00 [1;32mINDIRECT_BUFFER_CIK[0m:
>00002800         [1;33mIB_BASE_LO[0m <- 10240 (0x00002800)
>00000001         [1;33mIB_BASE_HI[0m <- 1
>00000040         [1;33mCONTROL[0m <- IB_SIZE = 64 (0x00040)
>                            CHAIN = 0
>                            VALID = 0
>c0027900 [1;36mSET_UCONFIG_REG[1;36m:
>00000240 
>00001800         [1;33mVGT_ESGS_RING_SIZE[0m <- 6144 (0x00001800)
>00025000         [1;33mVGT_GSVS_RING_SIZE[0m <- 0x00025000
>c0004200 [1;32mPFP_SYNC_ME[0m:
>00000000 
>c0034300 [1;32mSURFACE_SYNC[0m:
>28c40000         [1;33mCP_COHER_CNTL[0m <- DEST_BASE_0_ENA = 0
>                                  DEST_BASE_1_ENA = 0
>                                  TC_SD_ACTION_ENA = 0
>                                  TC_NC_ACTION_ENA = 0
>                                  CB0_DEST_BASE_ENA = 0
>                                  CB1_DEST_BASE_ENA = 0
>                                  CB2_DEST_BASE_ENA = 0
>                                  CB3_DEST_BASE_ENA = 0
>                                  CB4_DEST_BASE_ENA = 0
>                                  CB5_DEST_BASE_ENA = 0
>                                  CB6_DEST_BASE_ENA = 0
>                                  CB7_DEST_BASE_ENA = 0
>                                  DB_DEST_BASE_ENA = 0
>                                  TCL1_VOL_ACTION_ENA = 0
>                                  TC_VOL_ACTION_ENA = 0
>                                  TC_WB_ACTION_ENA = 1
>                                  DEST_BASE_2_ENA = 0
>                                  DEST_BASE_3_ENA = 0
>                                  TCL1_ACTION_ENA = 1
>                                  TC_ACTION_ENA = 1
>                                  CB_ACTION_ENA = 0
>                                  DB_ACTION_ENA = 0
>                                  SH_KCACHE_ACTION_ENA = 1
>                                  SH_KCACHE_VOL_ACTION_ENA = 0
>                                  SH_ICACHE_ACTION_ENA = 1
>                                  SH_KCACHE_WB_ACTION_ENA = 0
>                                  SH_SD_ACTION_ENA = 0
>ffffffff         [1;33mCP_COHER_SIZE[0m <- 0xffffffff
>00000000         [1;33mCP_COHER_BASE[0m <- 0
>0000000a         [1;33mPOLL_INTERVAL[0m <- 10 (0x000a)
>c0004600 [1;32mEVENT_WRITE[0m:
>00000019         [1;33mVGT_EVENT_INITIATOR[0m <- EVENT_TYPE = PIPELINESTAT_START
>                 [1;33mEVENT_INDEX[0m <- 0
>                 [1;33mINV_L2[0m <- 0
>c0055000 [1;32mDMA_DATA[0m:
>60300000         [1;33mDMA_DATA_WORD0[0m <- CP_SYNC = 0
>                                   SRC_SEL = SRC_ADDR_TC_L2
>                                   DST_SEL = DST_ADDR_TC_L2
>                                   ENGINE = ME
>01de5000         [1;33mSRC_ADDR_LO[0m <- 0x01de5000
>00000001         [1;33mSRC_ADDR_HI[0m <- 1
>01de5000         [1;33mDST_ADDR_LO[0m <- 0x01de5000
>00000001         [1;33mDST_ADDR_HI[0m <- 1
>00200420         [1;33mCOMMAND[0m <- BYTE_COUNT_GFX6 = 1056 (0x00420)
>                            BYTE_COUNT_GFX9 = 0x200420
>                            DISABLE_WR_CONFIRM_GFX6 = 1
>                            SRC_SWAP = NONE
>                            DST_SWAP = NONE
>                            SAS = MEMORY
>                            DAS = MEMORY
>                            SAIC = INCREMENT
>                            DAIC = INCREMENT
>                            RAW_WAIT = 0
>                            DISABLE_WR_CONFIRM_GFX9 = 0
>c0055000 [1;32mDMA_DATA[0m:
>60300000         [1;33mDMA_DATA_WORD0[0m <- CP_SYNC = 0
>                                   SRC_SEL = SRC_ADDR_TC_L2
>                                   DST_SEL = DST_ADDR_TC_L2
>                                   ENGINE = ME
>0034f380         [1;33mSRC_ADDR_LO[0m <- 0x0034f380
>00000000         [1;33mSRC_ADDR_HI[0m <- 0
>0034f380         [1;33mDST_ADDR_LO[0m <- 0x0034f380
>00000000         [1;33mDST_ADDR_HI[0m <- 0
>00200060         [1;33mCOMMAND[0m <- BYTE_COUNT_GFX6 = 96 (0x00060)
>                            BYTE_COUNT_GFX9 = 0x200060
>                            DISABLE_WR_CONFIRM_GFX6 = 1
>                            SRC_SWAP = NONE
>                            DST_SWAP = NONE
>                            SAS = MEMORY
>                            DAS = MEMORY
>                            SAIC = INCREMENT
>                            DAIC = INCREMENT
>                            RAW_WAIT = 0
>                            DISABLE_WR_CONFIRM_GFX9 = 0
>c0026900 [1;36mSET_CONTEXT_REG[1;36m:
>000002e5 
>00000000         [1;33mVGT_STRMOUT_CONFIG[0m <- STREAMOUT_0_EN = 0
>                                       STREAMOUT_1_EN = 0
>                                       STREAMOUT_2_EN = 0
>                                       STREAMOUT_3_EN = 0
>                                       RAST_STREAM = 0
>                                       RAST_STREAM_MASK = 0
>                                       USE_RAST_STREAM_MASK = 0
>00000000         [1;33mVGT_STRMOUT_BUFFER_CONFIG[0m <- STREAM_0_BUFFER_EN = 0
>                                              STREAM_1_BUFFER_EN = 0
>                                              STREAM_2_BUFFER_EN = 0
>                                              STREAM_3_BUFFER_EN = 0
>c00e6900 [1;36mSET_CONTEXT_REG[1;36m:
>00000318 
>01042d3c         [1;33mCB_COLOR0_BASE[0m <- 0x01042d3c
>01f0001f         [1;33mCB_COLOR0_PITCH[0m <- TILE_MAX = 31 (0x1f)
>                                    FMASK_TILE_MAX = 31 (0x1f)
>000003ff         [1;33mCB_COLOR0_SLICE[0m <- TILE_MAX = 1023 (0x003ff)
>00000000         [1;33mCB_COLOR0_VIEW[0m <- SLICE_START = 0
>                                   SLICE_MAX = 0
>00060730         [1;33mCB_COLOR0_INFO[0m <- ENDIAN = ENDIAN_NONE
>                                   FORMAT = COLOR_16_16_16_16
>                                   LINEAR_GENERAL = 0
>                                   NUMBER_TYPE = NUMBER_FLOAT
>                                   COMP_SWAP = SWAP_STD
>                                   FAST_CLEAR = 0
>                                   COMPRESSION = 0
>                                   BLEND_CLAMP = 0
>                                   BLEND_BYPASS = 0
>                                   SIMPLE_FLOAT = 1
>                                   ROUND_MODE = 1
>                                   CMASK_IS_LINEAR = 0
>                                   BLEND_OPT_DONT_RD_DST = FORCE_OPT_AUTO
>                                   BLEND_OPT_DISCARD_PIXEL = FORCE_OPT_AUTO
>                                   FMASK_COMPRESSION_DISABLE = 0
>                                   FMASK_COMPRESS_1FRAG_ONLY = 0
>                                   DCC_ENABLE = 0
>                                   CMASK_ADDR_TYPE = 0
>000001ce         [1;33mCB_COLOR0_ATTRIB[0m <- TILE_MODE_INDEX = 14 (0xe)
>                                     FMASK_TILE_MODE_INDEX = 14 (0xe)
>                                     FMASK_BANK_HEIGHT = 0
>                                     NUM_SAMPLES = 0
>                                     NUM_FRAGMENTS = 0
>                                     FORCE_DST_ALPHA_1 = 0
>00000208         [1;33mCB_COLOR0_DCC_CONTROL[0m <- OVERWRITE_COMBINER_DISABLE = 0
>                                          KEY_CLEAR_ENABLE = 0
>                                          MAX_UNCOMPRESSED_BLOCK_SIZE = MAX_BLOCK_SIZE_256B
>                                          MIN_COMPRESSED_BLOCK_SIZE = MIN_BLOCK_SIZE_32B
>                                          MAX_COMPRESSED_BLOCK_SIZE = 0
>                                          COLOR_TRANSFORM = 0
>                                          INDEPENDENT_64B_BLOCKS = 1
>                                          LOSSY_RGB_PRECISION = 0
>                                          LOSSY_ALPHA_PRECISION = 0
>01042d00         [1;33mCB_COLOR0_CMASK[0m <- 0x01042d00
>00000003         [1;33mCB_COLOR0_CMASK_SLICE[0m <- TILE_MAX = 3
>01042d3c         [1;33mCB_COLOR0_FMASK[0m <- 0x01042d3c
>000003ff         [1;33mCB_COLOR0_FMASK_SLICE[0m <- TILE_MAX = 1023 (0x003ff)
>00000000         [1;33mCB_COLOR0_CLEAR_WORD0[0m <- 0
>00000000         [1;33mCB_COLOR0_CLEAR_WORD1[0m <- 0
>00000000         [1;33mCB_COLOR0_DCC_BASE[0m <- 0
>c0016900 [1;36mSET_CONTEXT_REG[1;36m:
>00000082 
>00ee00e8         [1;33mPA_SC_WINDOW_SCISSOR_BR[0m <- BR_X = 232 (0x0e8)
>                                            BR_Y = 238 (0x0ee)
>c0026900 [1;36mSET_CONTEXT_REG[1;36m:
>000002f5 
>00000000         [1;33mPA_SC_CENTROID_PRIORITY_0[0m <- DISTANCE_0 = 0
>                                              DISTANCE_1 = 0
>                                              DISTANCE_2 = 0
>                                              DISTANCE_3 = 0
>                                              DISTANCE_4 = 0
>                                              DISTANCE_5 = 0
>                                              DISTANCE_6 = 0
>                                              DISTANCE_7 = 0
>00000000         [1;33mPA_SC_CENTROID_PRIORITY_1[0m <- DISTANCE_8 = 0
>                                              DISTANCE_9 = 0
>                                              DISTANCE_10 = 0
>                                              DISTANCE_11 = 0
>                                              DISTANCE_12 = 0
>                                              DISTANCE_13 = 0
>                                              DISTANCE_14 = 0
>                                              DISTANCE_15 = 0
>c0016900 [1;36mSET_CONTEXT_REG[1;36m:
>000002fe 
>00000000         [1;33mPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0[0m <- S0_X = 0
>                                                      S0_Y = 0
>                                                      S1_X = 0
>                                                      S1_Y = 0
>                                                      S2_X = 0
>                                                      S2_Y = 0
>                                                      S3_X = 0
>                                                      S3_Y = 0
>c0016900 [1;36mSET_CONTEXT_REG[1;36m:
>00000302 
>00000000         [1;33mPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0[0m <- S0_X = 0
>                                                      S0_Y = 0
>                                                      S1_X = 0
>                                                      S1_Y = 0
>                                                      S2_X = 0
>                                                      S2_Y = 0
>                                                      S3_X = 0
>                                                      S3_Y = 0
>c0016900 [1;36mSET_CONTEXT_REG[1;36m:
>00000306 
>00000000         [1;33mPA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0[0m <- S0_X = 0
>                                                      S0_Y = 0
>                                                      S1_X = 0
>                                                      S1_Y = 0
>                                                      S2_X = 0
>                                                      S2_Y = 0
>                                                      S3_X = 0
>                                                      S3_Y = 0
>c0016900 [1;36mSET_CONTEXT_REG[1;36m:
>0000030a 
>00000000         [1;33mPA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0[0m <- S0_X = 0
>                                                      S0_Y = 0
>                                                      S1_X = 0
>                                                      S1_Y = 0
>                                                      S2_X = 0
>                                                      S2_Y = 0
>                                                      S3_X = 0
>                                                      S3_Y = 0
>c0016900 [1;36mSET_CONTEXT_REG[1;36m:
>0000020c 
>00000005         [1;33mPA_SU_SMALL_PRIM_FILTER_CNTL[0m <- SMALL_PRIM_FILTER_ENABLE = 1
>                                                 TRIANGLE_FILTER_DISABLE = 0
>                                                 LINE_FILTER_DISABLE = 1
>                                                 POINT_FILTER_DISABLE = 0
>                                                 RECTANGLE_FILTER_DISABLE = 0
>c0016900 [1;36mSET_CONTEXT_REG[1;36m:
>00000203 
>00000010         [1;33mDB_SHADER_CONTROL[0m <- Z_EXPORT_ENABLE = 0
>                                      STENCIL_TEST_VAL_EXPORT_ENABLE = 0
>                                      STENCIL_OP_VAL_EXPORT_ENABLE = 0
>                                      Z_ORDER = EARLY_Z_THEN_LATE_Z
>                                      KILL_ENABLE = 0
>                                      COVERAGE_TO_MASK_ENABLE = 0
>                                      MASK_EXPORT_ENABLE = 0
>                                      EXEC_ON_HIER_FAIL = 0
>                                      EXEC_ON_NOOP = 0
>                                      ALPHA_TO_MASK_DISABLE = 0
>                                      DEPTH_BEFORE_SHADER = 0
>                                      CONSERVATIVE_Z_EXPORT = EXPORT_ANY_Z
>                                      DUAL_QUAD_DISABLE = 0
>c0016900 [1;36mSET_CONTEXT_REG[1;36m:
>00000201 
>00170000         [1;33mDB_EQAA[0m <- MAX_ANCHOR_SAMPLES = 0
>                            PS_ITER_SAMPLES = 0
>                            MASK_EXPORT_NUM_SAMPLES = 0
>                            ALPHA_TO_MASK_NUM_SAMPLES = 0
>                            HIGH_QUALITY_INTERSECTIONS = 1
>                            INCOHERENT_EQAA_READS = 1
>                            INTERPOLATE_COMP_Z = 1
>                            INTERPOLATE_SRC_Z = 0
>                            STATIC_ANCHOR_ASSOCIATIONS = 1
>                            ALPHA_TO_MASK_EQAA_DISABLE = 0
>                            OVERRASTERIZATION_AMOUNT = 0
>                            ENABLE_POSTZ_OVERRASTERIZATION = 0
>c0016900 [1;36mSET_CONTEXT_REG[1;36m:
>00000293 
>760201bc         [1;33mPA_SC_MODE_CNTL_1[0m <- WALK_SIZE = 0
>                                      WALK_ALIGNMENT = 0
>                                      WALK_ALIGN8_PRIM_FITS_ST = 1
>                                      WALK_FENCE_ENABLE = 1
>                                      WALK_FENCE_SIZE = 3
>                                      SUPERTILE_WALK_ORDER_ENABLE = 1
>                                      TILE_WALK_ORDER_ENABLE = 1
>                                      TILE_COVER_DISABLE = 0
>                                      TILE_COVER_NO_SCISSOR = 0
>                                      ZMM_LINE_EXTENT = 0
>                                      ZMM_LINE_OFFSET = 0
>                                      ZMM_RECT_EXTENT = 0
>                                      KILL_PIX_POST_HI_Z = 0
>                                      KILL_PIX_POST_DETAIL_MASK = 0
>                                      PS_ITER_SAMPLE = 0
>                                      MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE = 1
>                                      MULTI_GPU_SUPERTILE_ENABLE = 0
>                                      GPU_ID_OVERRIDE_ENABLE = 0
>                                      GPU_ID_OVERRIDE = 0
>                                      MULTI_GPU_PRIM_DISCARD_ENABLE = 0
>                                      FORCE_EOV_CNTDWN_ENABLE = 1
>                                      FORCE_EOV_REZ_ENABLE = 1
>                                      OUT_OF_ORDER_PRIMITIVE_ENABLE = 0
>                                      OUT_OF_ORDER_WATER_MARK = 7
>c0016900 [1;36mSET_CONTEXT_REG[1;36m:
>0000008e 
>0000000f         [1;33mCB_TARGET_MASK[0m <- TARGET0_ENABLE = 15 (0xf)
>                                   TARGET1_ENABLE = 0
>                                   TARGET2_ENABLE = 0
>                                   TARGET3_ENABLE = 0
>                                   TARGET4_ENABLE = 0
>                                   TARGET5_ENABLE = 0
>                                   TARGET6_ENABLE = 0
>                                   TARGET7_ENABLE = 0
>c0016900 [1;36mSET_CONTEXT_REG[1;36m:
>00000109 
>00000012         [1;33mCB_DCC_CONTROL[0m <- OVERWRITE_COMBINER_DISABLE = 0
>                                   OVERWRITE_COMBINER_MRT_SHARING_DISABLE = 1
>                                   OVERWRITE_COMBINER_WATERMARK = 4
>c0016900 [1;36mSET_CONTEXT_REG[1;36m:
>00000204 
>01000000         [1;33mPA_CL_CLIP_CNTL[0m <- UCP_ENA_0 = 0
>                                    UCP_ENA_1 = 0
>                                    UCP_ENA_2 = 0
>                                    UCP_ENA_3 = 0
>                                    UCP_ENA_4 = 0
>                                    UCP_ENA_5 = 0
>                                    PS_UCP_Y_SCALE_NEG = 0
>                                    PS_UCP_MODE = 0
>                                    CLIP_DISABLE = 0
>                                    UCP_CULL_ONLY_ENA = 0
>                                    BOUNDARY_EDGE_FLAG_ENA = 0
>                                    DX_CLIP_SPACE_DEF = 0
>                                    DIS_CLIP_ERR_DETECT = 0
>                                    VTX_KILL_OR = 0
>                                    DX_RASTERIZATION_KILL = 0
>                                    DX_LINEAR_ATTR_CLIP_ENA = 1
>                                    VTE_VPORT_PROVOKE_DISABLE = 0
>                                    ZCLIP_NEAR_DISABLE = 0
>                                    ZCLIP_FAR_DISABLE = 0
>c0017600 [1;36mSET_SH_REG[1;36m:
>0000000c 
>0034f740         [1;33mSPI_SHADER_USER_DATA_PS_0[0m <- 0x0034f740
>c0017600 [1;36mSET_SH_REG[1;36m:
>0000004c 
>0034f740         [1;33mSPI_SHADER_USER_DATA_VS_0[0m <- 0x0034f740
>c0017600 [1;36mSET_SH_REG[1;36m:
>000000cc 
>0034f740         [1;33mSPI_SHADER_USER_DATA_ES_0[0m <- 0x0034f740
>c0017600 [1;36mSET_SH_REG[1;36m:
>0000008c 
>0034f740         [1;33mSPI_SHADER_USER_DATA_GS_0[0m <- 0x0034f740
>c0017600 [1;36mSET_SH_REG[1;36m:
>0000010c 
>0034f740         [1;33mSPI_SHADER_USER_DATA_HS_0[0m <- 0x0034f740
>c0017600 [1;36mSET_SH_REG[1;36m:
>0000014c 
>0034f740         [1;33mSPI_SHADER_USER_DATA_LS_0[0m <- 0x0034f740
>c0027600 [1;36mSET_SH_REG[1;36m:
>0000004e 
>0034f390         [1;33mSPI_SHADER_USER_DATA_VS_2[0m <- 0x0034f390
>00000000         [1;33mSPI_SHADER_USER_DATA_VS_3[0m <- 0
>c0027600 [1;36mSET_SH_REG[1;36m:
>0000000e 
>0034f610         [1;33mSPI_SHADER_USER_DATA_PS_2[0m <- 0x0034f610
>0152ff00         [1;33mSPI_SHADER_USER_DATA_PS_3[0m <- 0x0152ff00
>c0027600 [1;36mSET_SH_REG[1;36m:
>0000010e 
>00000000         [1;33mSPI_SHADER_USER_DATA_HS_2[0m <- 0
>00000000         [1;33mSPI_SHADER_USER_DATA_HS_3[0m <- 0
>c0027600 [1;36mSET_SH_REG[1;36m:
>0000008e 
>0034dd90         [1;33mSPI_SHADER_USER_DATA_GS_2[0m <- 0x0034dd90
>00000000         [1;33mSPI_SHADER_USER_DATA_GS_3[0m <- 0
>c0017600 [1;36mSET_SH_REG[1;36m:
>00000054 
>0034f380         [1;33mSPI_SHADER_USER_DATA_VS_8[0m <- 0x0034f380
>c0017600 [1;36mSET_SH_REG[1;36m:
>0000000d 
>01520000         [1;33mSPI_SHADER_USER_DATA_PS_1[0m <- 0x01520000
>c0017600 [1;36mSET_SH_REG[1;36m:
>0000004d 
>01520000         [1;33mSPI_SHADER_USER_DATA_VS_1[0m <- 0x01520000
>c0017600 [1;36mSET_SH_REG[1;36m:
>000000cd 
>01520000         [1;33mSPI_SHADER_USER_DATA_ES_1[0m <- 0x01520000
>c0017600 [1;36mSET_SH_REG[1;36m:
>0000008d 
>01520000         [1;33mSPI_SHADER_USER_DATA_GS_1[0m <- 0x01520000
>c0017600 [1;36mSET_SH_REG[1;36m:
>0000010d 
>01520000         [1;33mSPI_SHADER_USER_DATA_HS_1[0m <- 0x01520000
>c0017600 [1;36mSET_SH_REG[1;36m:
>0000014d 
>01520000         [1;33mSPI_SHADER_USER_DATA_LS_1[0m <- 0x01520000
>c0046900 [1;36mSET_CONTEXT_REG[1;36m:
>000002fa 
>426eb7f1         [1;33mPA_CL_GB_VERT_CLIP_ADJ[0m <- 0x426eb7f1
>3f800000         [1;33mPA_CL_GB_VERT_DISC_ADJ[0m <- 1.0f (0x3f800000)
>42048777         [1;33mPA_CL_GB_HORZ_CLIP_ADJ[0m <- 0x42048777
>3f800000         [1;33mPA_CL_GB_HORZ_DISC_ADJ[0m <- 1.0f (0x3f800000)
>c0026900 [1;36mSET_CONTEXT_REG[1;36m:
>00000094 
>80000000         [1;33mPA_SC_VPORT_SCISSOR_0_TL[0m <- TL_X = 0
>                                             TL_Y = 0
>                                             WINDOW_OFFSET_DISABLE = 1
>04380780         [1;33mPA_SC_VPORT_SCISSOR_0_BR[0m <- BR_X = 1920 (0x780)
>                                             BR_Y = 1080 (0x438)
>c0066900 [1;36mSET_CONTEXT_REG[1;36m:
>0000010f 
>44700000         [1;33mPA_CL_VPORT_XSCALE[0m <- 960.0f (0x44700000)
>44700000         [1;33mPA_CL_VPORT_XOFFSET[0m <- 960.0f (0x44700000)
>44070000         [1;33mPA_CL_VPORT_YSCALE[0m <- 540.0f (0x44070000)
>44070000         [1;33mPA_CL_VPORT_YOFFSET[0m <- 540.0f (0x44070000)
>3f000000         [1;33mPA_CL_VPORT_ZSCALE[0m <- 0.5f (0x3f000000)
>3f000000         [1;33mPA_CL_VPORT_ZOFFSET[0m <- 0.5f (0x3f000000)
>c0026900 [1;36mSET_CONTEXT_REG[1;36m:
>000000b4 
>00000000         [1;33mPA_SC_VPORT_ZMIN_0[0m <- 0
>3f800000         [1;33mPA_SC_VPORT_ZMAX_0[0m <- 1.0f (0x3f800000)
>c0026900 [1;36mSET_CONTEXT_REG[1;36m:
>0000010c 
>01000000         [1;33mDB_STENCILREFMASK[0m <- STENCILTESTVAL = 0
>                                      STENCILMASK = 0
>                                      STENCILWRITEMASK = 0
>                                      STENCILOPVAL = 1
>01000000         [1;33mDB_STENCILREFMASK_BF[0m <- STENCILTESTVAL_BF = 0
>                                         STENCILMASK_BF = 0
>                                         STENCILWRITEMASK_BF = 0
>                                         STENCILOPVAL_BF = 1
>c0036900 [1;36mSET_CONTEXT_REG[1;36m:
>00000191 
>00000000         [1;33mSPI_PS_INPUT_CNTL_0[0m <- OFFSET = 0
>                                        DEFAULT_VAL = X_0_0F
>                                        FLAT_SHADE = 0
>                                        CYL_WRAP = 0
>                                        PT_SPRITE_TEX = 0
>                                        DUP = 0
>                                        FP16_INTERP_MODE = 0
>                                        USE_DEFAULT_ATTR1 = 0
>                                        DEFAULT_VAL_ATTR1 = 0
>                                        PT_SPRITE_TEX_ATTR1 = 0
>                                        ATTR0_VALID = 0
>                                        ATTR1_VALID = 0
>00000401         [1;33mSPI_PS_INPUT_CNTL_1[0m <- OFFSET = 1
>                                        DEFAULT_VAL = X_0_0F
>                                        FLAT_SHADE = 1
>                                        CYL_WRAP = 0
>                                        PT_SPRITE_TEX = 0
>                                        DUP = 0
>                                        FP16_INTERP_MODE = 0
>                                        USE_DEFAULT_ATTR1 = 0
>                                        DEFAULT_VAL_ATTR1 = 0
>                                        PT_SPRITE_TEX_ATTR1 = 0
>                                        ATTR0_VALID = 0
>                                        ATTR1_VALID = 0
>00000402         [1;33mSPI_PS_INPUT_CNTL_2[0m <- OFFSET = 2
>                                        DEFAULT_VAL = X_0_0F
>                                        FLAT_SHADE = 1
>                                        CYL_WRAP = 0
>                                        PT_SPRITE_TEX = 0
>                                        DUP = 0
>                                        FP16_INTERP_MODE = 0
>                                        USE_DEFAULT_ATTR1 = 0
>                                        DEFAULT_VAL_ATTR1 = 0
>                                        PT_SPRITE_TEX_ATTR1 = 0
>                                        ATTR0_VALID = 0
>                                        ATTR1_VALID = 0
>c0016900 [1;36mSET_CONTEXT_REG[1;36m:
>000001ba 
>000001c0         [1;33mSPI_TMPRING_SIZE[0m <- WAVES = 448 (0x1c0)
>                                     WAVESIZE = 0
>c0016900 [1;36mSET_CONTEXT_REG[1;36m:
>000002dc 
>0000aa00         [1;33mDB_ALPHA_TO_MASK[0m <- ALPHA_TO_MASK_ENABLE = 0
>                                     ALPHA_TO_MASK_OFFSET0 = 2
>                                     ALPHA_TO_MASK_OFFSET1 = 2
>                                     ALPHA_TO_MASK_OFFSET2 = 2
>                                     ALPHA_TO_MASK_OFFSET3 = 2
>                                     OFFSET_ROUND = 0
>c0086900 [1;36mSET_CONTEXT_REG[1;36m:
>000001e0 
>40000501         [1;33mCB_BLEND0_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ONE
>                                      COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                                      COLOR_DESTBLEND = BLEND_ONE_MINUS_SRC_ALPHA
>                                      ALPHA_SRCBLEND = BLEND_ZERO
>                                      ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                                      ALPHA_DESTBLEND = BLEND_ZERO
>                                      SEPARATE_ALPHA_BLEND = 0
>                                      ENABLE = 1
>                                      DISABLE_ROP3 = 0
>40000501         [1;33mCB_BLEND1_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ONE
>                                      COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                                      COLOR_DESTBLEND = BLEND_ONE_MINUS_SRC_ALPHA
>                                      ALPHA_SRCBLEND = BLEND_ZERO
>                                      ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                                      ALPHA_DESTBLEND = BLEND_ZERO
>                                      SEPARATE_ALPHA_BLEND = 0
>                                      ENABLE = 1
>                                      DISABLE_ROP3 = 0
>40000501         [1;33mCB_BLEND2_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ONE
>                                      COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                                      COLOR_DESTBLEND = BLEND_ONE_MINUS_SRC_ALPHA
>                                      ALPHA_SRCBLEND = BLEND_ZERO
>                                      ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                                      ALPHA_DESTBLEND = BLEND_ZERO
>                                      SEPARATE_ALPHA_BLEND = 0
>                                      ENABLE = 1
>                                      DISABLE_ROP3 = 0
>40000501         [1;33mCB_BLEND3_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ONE
>                                      COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                                      COLOR_DESTBLEND = BLEND_ONE_MINUS_SRC_ALPHA
>                                      ALPHA_SRCBLEND = BLEND_ZERO
>                                      ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                                      ALPHA_DESTBLEND = BLEND_ZERO
>                                      SEPARATE_ALPHA_BLEND = 0
>                                      ENABLE = 1
>                                      DISABLE_ROP3 = 0
>40000501         [1;33mCB_BLEND4_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ONE
>                                      COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                                      COLOR_DESTBLEND = BLEND_ONE_MINUS_SRC_ALPHA
>                                      ALPHA_SRCBLEND = BLEND_ZERO
>                                      ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                                      ALPHA_DESTBLEND = BLEND_ZERO
>                                      SEPARATE_ALPHA_BLEND = 0
>                                      ENABLE = 1
>                                      DISABLE_ROP3 = 0
>40000501         [1;33mCB_BLEND5_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ONE
>                                      COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                                      COLOR_DESTBLEND = BLEND_ONE_MINUS_SRC_ALPHA
>                                      ALPHA_SRCBLEND = BLEND_ZERO
>                                      ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                                      ALPHA_DESTBLEND = BLEND_ZERO
>                                      SEPARATE_ALPHA_BLEND = 0
>                                      ENABLE = 1
>                                      DISABLE_ROP3 = 0
>40000501         [1;33mCB_BLEND6_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ONE
>                                      COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                                      COLOR_DESTBLEND = BLEND_ONE_MINUS_SRC_ALPHA
>                                      ALPHA_SRCBLEND = BLEND_ZERO
>                                      ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                                      ALPHA_DESTBLEND = BLEND_ZERO
>                                      SEPARATE_ALPHA_BLEND = 0
>                                      ENABLE = 1
>                                      DISABLE_ROP3 = 0
>40000501         [1;33mCB_BLEND7_CONTROL[0m <- COLOR_SRCBLEND = BLEND_ONE
>                                      COLOR_COMB_FCN = COMB_DST_PLUS_SRC
>                                      COLOR_DESTBLEND = BLEND_ONE_MINUS_SRC_ALPHA
>                                      ALPHA_SRCBLEND = BLEND_ZERO
>                                      ALPHA_COMB_FCN = COMB_DST_PLUS_SRC
>                                      ALPHA_DESTBLEND = BLEND_ZERO
>                                      SEPARATE_ALPHA_BLEND = 0
>                                      ENABLE = 1
>                                      DISABLE_ROP3 = 0
>c0016900 [1;36mSET_CONTEXT_REG[1;36m:
>00000202 
>00cc0010         [1;33mCB_COLOR_CONTROL[0m <- DISABLE_DUAL_QUAD = 0
>                                     DEGAMMA_ENABLE = 0
>                                     MODE = CB_NORMAL
>                                     ROP3 = ROP3_COPY
>c0016900 [1;36mSET_CONTEXT_REG[1;36m:
>000001b5 
>0000486b         [1;33mSPI_INTERP_CONTROL_0[0m <- FLAT_SHADE_ENA = 1
>                                         PNT_SPRITE_ENA = 1
>                                         PNT_SPRITE_OVRD_X = SPI_PNT_SPRITE_SEL_S
>                                         PNT_SPRITE_OVRD_Y = SPI_PNT_SPRITE_SEL_T
>                                         PNT_SPRITE_OVRD_Z = SPI_PNT_SPRITE_SEL_0
>                                         PNT_SPRITE_OVRD_W = SPI_PNT_SPRITE_SEL_1
>                                         PNT_SPRITE_TOP_1 = 1
>c0036900 [1;36mSET_CONTEXT_REG[1;36m:
>00000280 
>00080008         [1;33mPA_SU_POINT_SIZE[0m <- HEIGHT = 8
>                                     WIDTH = 8
>00080008         [1;33mPA_SU_POINT_MINMAX[0m <- MIN_SIZE = 8
>                                       MAX_SIZE = 8
>00000008         [1;33mPA_SU_LINE_CNTL[0m <- WIDTH = 8
>c0016900 [1;36mSET_CONTEXT_REG[1;36m:
>00000292 
>00000002         [1;33mPA_SC_MODE_CNTL_0[0m <- MSAA_ENABLE = 0
>                                      VPORT_SCISSOR_ENABLE = 1
>                                      LINE_STIPPLE_ENABLE = 0
>                                      SEND_UNLIT_STILES_TO_PKR = 0
>c0016900 [1;36mSET_CONTEXT_REG[1;36m:
>000002f9 
>00000029         [1;33mPA_SU_VTX_CNTL[0m <- PIX_CENTER = 1
>                                   ROUND_MODE = X_TRUNCATE
>                                   QUANT_MODE = X_16_8_FIXED_POINT_1_256TH
>c0016900 [1;36mSET_CONTEXT_REG[1;36m:
>000002df 
>00000000         [1;33mPA_SU_POLY_OFFSET_CLAMP[0m <- 0
>c0016900 [1;36mSET_CONTEXT_REG[1;36m:
>00000205 
>00080246         [1;33mPA_SU_SC_MODE_CNTL[0m <- CULL_FRONT = 0
>                                       CULL_BACK = 1
>                                       FACE = 1
>                                       POLY_MODE = X_DISABLE_POLY_MODE
>                                       POLYMODE_FRONT_PTYPE = X_DRAW_TRIANGLES
>                                       POLYMODE_BACK_PTYPE = X_DRAW_TRIANGLES
>                                       POLY_OFFSET_FRONT_ENABLE = 0
>                                       POLY_OFFSET_BACK_ENABLE = 0
>                                       POLY_OFFSET_PARA_ENABLE = 0
>                                       VTX_WINDOW_OFFSET_ENABLE = 0
>                                       PROVOKING_VTX_LAST = 1
>                                       PERSP_CORR_DIS = 0
>                                       MULTI_PRIM_IB_ENA = 0
>c0016900 [1;36mSET_CONTEXT_REG[1;36m:
>00000200 
>00000000         [1;33mDB_DEPTH_CONTROL[0m <- STENCIL_ENABLE = 0
>                                     Z_ENABLE = 0
>                                     Z_WRITE_ENABLE = 0
>                                     DEPTH_BOUNDS_ENABLE = 0
>                                     ZFUNC = FRAG_NEVER
>                                     BACKFACE_ENABLE = 0
>                                     STENCILFUNC = REF_NEVER
>                                     STENCILFUNC_BF = REF_NEVER
>                                     ENABLE_COLOR_WRITES_ON_DEPTH_FAIL = 0
>                                     DISABLE_COLOR_WRITES_ON_DEPTH_PASS = 0
>c0016900 [1;36mSET_CONTEXT_REG[1;36m:
>000002d5 
>00000000         [1;33mVGT_SHADER_STAGES_EN[0m <- LS_EN = LS_STAGE_OFF
>                                         HS_EN = 0
>                                         ES_EN = ES_STAGE_OFF
>                                         GS_EN = 0
>                                         VS_EN = VS_STAGE_REAL
>                                         DYNAMIC_HS = 0
>                                         DISPATCH_DRAW_EN = 0
>                                         DIS_DEALLOC_ACCUM_0 = 0
>                                         DIS_DEALLOC_ACCUM_1 = 0
>                                         VS_WAVE_ID_EN = 0
>c0016900 [1;36mSET_CONTEXT_REG[1;36m:
>00000290 
>00000000         [1;33mVGT_GS_MODE[0m <- MODE = GS_OFF
>                                RESERVED_0 = 0
>                                CUT_MODE = GS_CUT_1024
>                                RESERVED_1 = 0
>                                GS_C_PACK_EN = 0
>                                RESERVED_2 = 0
>                                ES_PASSTHRU = 0
>                                COMPUTE_MODE = 0
>                                FAST_COMPUTE_MODE = 0
>                                ELEMENT_INFO_EN = 0
>                                PARTIAL_THD_AT_EOI = 0
>                                SUPPRESS_CUTS = 0
>                                ES_WRITE_OPTIMIZE = 0
>                                GS_WRITE_OPTIMIZE = 0
>                                ONCHIP = X_0_OFFCHIP_GS
>c0016900 [1;36mSET_CONTEXT_REG[1;36m:
>000002a1 
>00000000         [1;33mVGT_PRIMITIVEID_EN[0m <- PRIMITIVEID_EN = 0
>                                       DISABLE_RESET_ON_EOI = 0
>c0016900 [1;36mSET_CONTEXT_REG[1;36m:
>000002ad 
>00000000         [1;33mVGT_REUSE_OFF[0m <- REUSE_OFF = 0
>c0016900 [1;36mSET_CONTEXT_REG[1;36m:
>000001b1 
>00000004         [1;33mSPI_VS_OUT_CONFIG[0m <- VS_EXPORT_COUNT = 2
>                                      VS_HALF_PACK = 0
>                                      VS_EXPORTS_FOG = 0
>                                      VS_OUT_FOG_VEC_ADDR = 0
>c0016900 [1;36mSET_CONTEXT_REG[1;36m:
>000001c3 
>00000004         [1;33mSPI_SHADER_POS_FORMAT[0m <- POS0_EXPORT_FORMAT = SPI_SHADER_4COMP
>                                          POS1_EXPORT_FORMAT = SPI_SHADER_NONE
>                                          POS2_EXPORT_FORMAT = SPI_SHADER_NONE
>                                          POS3_EXPORT_FORMAT = SPI_SHADER_NONE
>c0047600 [1;36mSET_SH_REG[1;36m:
>00000048 
>0101de50         [1;33mSPI_SHADER_PGM_LO_VS[0m <- 0x0101de50
>00000000         [1;33mSPI_SHADER_PGM_HI_VS[0m <- MEM_BASE = 0
>012c0144         [1;33mSPI_SHADER_PGM_RSRC1_VS[0m <- VGPRS = 4
>                                            SGPRS = 5
>                                            PRIORITY = 0
>                                            FLOAT_MODE = 192 (0xc0)
>                                            PRIV = 0
>                                            DX10_CLAMP = 1
>                                            DEBUG_MODE = 0
>                                            IEEE_MODE = 0
>                                            VGPR_COMP_CNT = 1
>                                            CU_GROUP_ENABLE = 0
>                                            CACHE_CTL = 0
>                                            CDBG_USER = 0
>00000012         [1;33mSPI_SHADER_PGM_RSRC2_VS[0m <- SCRATCH_EN = 0
>                                            USER_SGPR = 9
>                                            TRAP_PRESENT = 0
>                                            OC_LDS_EN = 0
>                                            SO_BASE0_EN = 0
>                                            SO_BASE1_EN = 0
>                                            SO_BASE2_EN = 0
>                                            SO_BASE3_EN = 0
>                                            SO_EN = 0
>                                            EXCP_EN_SI = 0
>                                            EXCP_EN = 0
>                                            DISPATCH_DRAW_EN = 0
>c0016900 [1;36mSET_CONTEXT_REG[1;36m:
>00000206 
>0000043f         [1;33mPA_CL_VTE_CNTL[0m <- VPORT_X_SCALE_ENA = 1
>                                   VPORT_X_OFFSET_ENA = 1
>                                   VPORT_Y_SCALE_ENA = 1
>                                   VPORT_Y_OFFSET_ENA = 1
>                                   VPORT_Z_SCALE_ENA = 1
>                                   VPORT_Z_OFFSET_ENA = 1
>                                   VTX_XY_FMT = 0
>                                   VTX_Z_FMT = 0
>                                   VTX_W0_FMT = 1
>c0016900 [1;36mSET_CONTEXT_REG[1;36m:
>00000316 
>0000001e         [1;33mVGT_VERTEX_REUSE_BLOCK_CNTL[0m <- VTX_REUSE_DEPTH = 30 (0x1e)
>c0026900 [1;36mSET_CONTEXT_REG[1;36m:
>000001b3 
>00000302         [1;33mSPI_PS_INPUT_ENA[0m <- PERSP_SAMPLE_ENA = 0
>                                     PERSP_CENTER_ENA = 1
>                                     PERSP_CENTROID_ENA = 0
>                                     PERSP_PULL_MODEL_ENA = 0
>                                     LINEAR_SAMPLE_ENA = 0
>                                     LINEAR_CENTER_ENA = 0
>                                     LINEAR_CENTROID_ENA = 0
>                                     LINE_STIPPLE_TEX_ENA = 0
>                                     POS_X_FLOAT_ENA = 1
>                                     POS_Y_FLOAT_ENA = 1
>                                     POS_Z_FLOAT_ENA = 0
>                                     POS_W_FLOAT_ENA = 0
>                                     FRONT_FACE_ENA = 0
>                                     ANCILLARY_ENA = 0
>                                     SAMPLE_COVERAGE_ENA = 0
>                                     POS_FIXED_PT_ENA = 0
>0000f377         [1;33mSPI_PS_INPUT_ADDR[0m <- PERSP_SAMPLE_ENA = 1
>                                      PERSP_CENTER_ENA = 1
>                                      PERSP_CENTROID_ENA = 1
>                                      PERSP_PULL_MODEL_ENA = 0
>                                      LINEAR_SAMPLE_ENA = 1
>                                      LINEAR_CENTER_ENA = 1
>                                      LINEAR_CENTROID_ENA = 1
>                                      LINE_STIPPLE_TEX_ENA = 0
>                                      POS_X_FLOAT_ENA = 1
>                                      POS_Y_FLOAT_ENA = 1
>                                      POS_Z_FLOAT_ENA = 0
>                                      POS_W_FLOAT_ENA = 0
>                                      FRONT_FACE_ENA = 1
>                                      ANCILLARY_ENA = 1
>                                      SAMPLE_COVERAGE_ENA = 1
>                                      POS_FIXED_PT_ENA = 1
>c0016900 [1;36mSET_CONTEXT_REG[1;36m:
>000001b8 
>01020000         [1;33mSPI_BARYC_CNTL[0m <- PERSP_CENTER_CNTL = 0
>                                   PERSP_CENTROID_CNTL = 0
>                                   LINEAR_CENTER_CNTL = 0
>                                   LINEAR_CENTROID_CNTL = 0
>                                   POS_FLOAT_LOCATION = 2
>                                   POS_FLOAT_ULC = 0
>                                   FRONT_FACE_ALL_BITS = 1
>c0016900 [1;36mSET_CONTEXT_REG[1;36m:
>000001b6 
>00000003         [1;33mSPI_PS_IN_CONTROL[0m <- NUM_INTERP = 3
>                                      PARAM_GEN = 0
>                                      FOG_ADDR = 0
>                                      BC_OPTIMIZE_DISABLE = 0
>                                      PASS_FOG_THROUGH_PS = 0
>c0026900 [1;36mSET_CONTEXT_REG[1;36m:
>000001c4 
>00000000         [1;33mSPI_SHADER_Z_FORMAT[0m <- Z_EXPORT_FORMAT = SPI_SHADER_ZERO
>00000004         [1;33mSPI_SHADER_COL_FORMAT[0m <- COL0_EXPORT_FORMAT = SPI_SHADER_FP16_ABGR
>                                          COL1_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                          COL2_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                          COL3_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                          COL4_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                          COL5_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                          COL6_EXPORT_FORMAT = SPI_SHADER_ZERO
>                                          COL7_EXPORT_FORMAT = SPI_SHADER_ZERO
>c0016900 [1;36mSET_CONTEXT_REG[1;36m:
>0000008f 
>0000000f         [1;33mCB_SHADER_MASK[0m <- OUTPUT0_ENABLE = 15 (0xf)
>                                   OUTPUT1_ENABLE = 0
>                                   OUTPUT2_ENABLE = 0
>                                   OUTPUT3_ENABLE = 0
>                                   OUTPUT4_ENABLE = 0
>                                   OUTPUT5_ENABLE = 0
>                                   OUTPUT6_ENABLE = 0
>                                   OUTPUT7_ENABLE = 0
>c0047600 [1;36mSET_SH_REG[1;36m:
>00000008 
>01000024         [1;33mSPI_SHADER_PGM_LO_PS[0m <- 0x01000024
>00000000         [1;33mSPI_SHADER_PGM_HI_PS[0m <- MEM_BASE = 0
>002c00c5         [1;33mSPI_SHADER_PGM_RSRC1_PS[0m <- VGPRS = 5
>                                            SGPRS = 3
>                                            PRIORITY = 0
>                                            FLOAT_MODE = FP_64_DENORMS
>                                            PRIV = 0
>                                            DX10_CLAMP = 1
>                                            DEBUG_MODE = 0
>                                            IEEE_MODE = 0
>                                            CU_GROUP_DISABLE = 0
>                                            CACHE_CTL = 0
>                                            CDBG_USER = 0
>0000000a         [1;33mSPI_SHADER_PGM_RSRC2_PS[0m <- SCRATCH_EN = 0
>                                            USER_SGPR = 5
>                                            TRAP_PRESENT = 0
>                                            WAVE_CNT_EN = 0
>                                            EXTRA_LDS_SIZE = 0
>                                            EXCP_EN_SI = 0
>                                            EXCP_EN = 0
>c0017600 [1;36mSET_SH_REG[1;36m:
>00000050 
>00000000         [1;33mSPI_SHADER_USER_DATA_VS_4[0m <- 0
>c0016900 [1;36mSET_CONTEXT_REG[1;36m:
>100002aa         INDEX = 1
>2010007f         [1;33mIA_MULTI_VGT_PARAM[0m <- PRIMGROUP_SIZE = 127 (0x007f)
>                                       PARTIAL_VS_WAVE_ON = 0
>                                       SWITCH_ON_EOP = 0
>                                       PARTIAL_ES_WAVE_ON = 0
>                                       SWITCH_ON_EOI = 0
>                                       WD_SWITCH_ON_EOP = 1
>                                       MAX_PRIMGRP_IN_WAVE = 2
>c0017900 [1;36mSET_UCONFIG_REG[1;36m:
>10000242         INDEX = 1
>00000006         [1;33mVGT_PRIMITIVE_TYPE[0m <- PRIM_TYPE = DI_PT_TRISTRIP
>c0016900 [1;36mSET_CONTEXT_REG[1;36m:
>000002a5 
>00000000         [1;33mVGT_MULTI_PRIM_IB_RESET_EN[0m <- RESET_EN = 0
>c0021100 [1;32mSET_BASE[0m:
>00000001 
>090fe000 
>00000001 
>c0082c00 [1;32mDRAW_INDIRECT_MULTI[0m:
>0003f450 
>00000051 
>00000052 
>80000053 
>00000001 
>00000000 
>00000000 
>00000010 
>00000002 
>c0055000 [1;32mDMA_DATA[0m:
>60300000         [1;33mDMA_DATA_WORD0[0m <- CP_SYNC = 0
>                                   SRC_SEL = SRC_ADDR_TC_L2
>                                   DST_SEL = DST_ADDR_TC_L2
>                                   ENGINE = ME
>00002400         [1;33mSRC_ADDR_LO[0m <- 9216 (0x00002400)
>00000001         [1;33mSRC_ADDR_HI[0m <- 1
>00002400         [1;33mDST_ADDR_LO[0m <- 9216 (0x00002400)
>00000001         [1;33mDST_ADDR_HI[0m <- 1
>002001a0         [1;33mCOMMAND[0m <- BYTE_COUNT_GFX6 = 416 (0x001a0)
>                            BYTE_COUNT_GFX9 = 0x2001a0
>                            DISABLE_WR_CONFIRM_GFX6 = 1
>                            SRC_SWAP = NONE
>                            DST_SWAP = NONE
>                            SAS = MEMORY
>                            DAS = MEMORY
>                            SAIC = INCREMENT
>                            DAIC = INCREMENT
>                            RAW_WAIT = 0
>                            DISABLE_WR_CONFIRM_GFX9 = 0
>c0033700 [1;32mWRITE_DATA[0m:
>00100100         [1;33mCONTROL[0m <- ENGINE_SEL = ME
>                            WR_CONFIRM = 1
>                            WR_ONE_ADDR = 0
>                            DST_SEL = MEMORY_SYNC
>00064e00         [1;33mDST_ADDR_LO[0m <- 0x00064e00
>00000001         [1;33mDST_ADDR_HI[0m <- 1
>00000002 
>c0001000 [1;32mNOP[0m:
>                 [31mTrace point ID: 2
>                 [31m!!!!! This is the last trace point that was reached by the CP !!!!![0m
>cafe0002 
>------------------- IB end -------------------
>
>[1;33mColor buffer 0:[0m
>  Info: npix_x=232, npix_y=238, npix_z=1, blk_w=1, blk_h=1, array_size=1, last_level=0, bpe=8, nsamples=0, flags=0x2000000, r16g16b16a16_float
>  Layout: size=524288, alignment=65536, bankw=1, bankh=2, nbanks=16, mtilea=4, tilesplit=1024, pipeconfig=5, scanout=0
>  Level[0]: offset=0, slice_size=524288, npix_x=232, npix_y=238, npix_z=1, nblk_x=256, nblk_y=256, mode=3, tiling_index = 14
>
>SHADER KEY
>  part.vs.prolog.instance_divisor_is_one = 31
>  part.vs.prolog.instance_divisor_is_fetched = 0
>  part.vs.prolog.ls_vgpr_fix = 0
>  mono.vs.fix_fetch = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
>  as_es = 0
>  as_ls = 0
>  mono.u.vs_export_prim_id = 0
>  opt.kill_outputs = 0x0
>  opt.clip_disable = 0
>
>Vertex Shader as VS:
>Shader prolog disassembly:
>vs_prolog:
>BB2_0:
>	v_add_u32_e32 v4, vcc, s6, v1 ; 32080206
>	v_mov_b32_e32 v5, v4          ; 7E0A0304
>	v_mov_b32_e32 v6, v4          ; 7E0C0304
>	v_mov_b32_e32 v7, v4          ; 7E0E0304
>	v_mov_b32_e32 v8, v4          ; 7E100304
>Shader main disassembly:
>main:
>BB0_0:
>	s_mov_b32 s9, 0                                            ; BE890080
>	s_load_dwordx4 s[24:27], s[8:9], 0x0                       ; C00A0604 00000000
>	s_add_i32 s0, s8, 16                                       ; 81009008
>	s_add_i32 s6, s8, 32                                       ; 8106A008
>	s_add_i32 s10, s8, 48                                      ; 810AB008
>	s_add_i32 s8, s8, 64                                       ; 8108C008
>	s_load_dwordx4 s[16:19], s[8:9], 0x0                       ; C00A0404 00000000
>	s_mov_b32 s1, s9                                           ; BE810009
>	s_mov_b32 s7, s9                                           ; BE870009
>	s_waitcnt lgkmcnt(0)                                       ; BF8C007F
>	buffer_load_format_xy v[1:2], v4, s[24:27], 0 idxen        ; E0042000 80060104
>	s_load_dwordx4 s[24:27], s[0:1], 0x0                       ; C00A0600 00000000
>	buffer_load_format_x v8, v8, s[16:19], 0 idxen             ; E0002000 80040808
>	s_load_dwordx4 s[28:31], s[6:7], 0x0                       ; C00A0703 00000000
>	s_mov_b32 s11, s9                                          ; BE8B0009
>	s_load_dwordx4 s[32:35], s[10:11], 0x0                     ; C00A0805 00000000
>	s_add_i32 s8, s2, 0x100                                    ; 8108FF02 00000100
>	s_load_dwordx4 s[20:23], s[8:9], 0x0                       ; C00A0504 00000000
>	s_waitcnt lgkmcnt(0)                                       ; BF8C007F
>	buffer_load_format_xy v[3:4], v6, s[28:31], 0 idxen        ; E0042000 80070306
>	buffer_load_format_xy v[5:6], v5, s[24:27], 0 idxen        ; E0042000 80060505
>	s_add_i32 s8, s2, 0x110                                    ; 8108FF02 00000110
>	s_load_dwordx4 s[12:15], s[8:9], 0x0                       ; C00A0304 00000000
>	v_add_u32_e32 v0, vcc, s5, v0                              ; 32000005
>	s_buffer_load_dword s5, s[20:23], 0x0                      ; C022014A 00000000
>	s_movk_i32 s3, 0x60                                        ; B0030060
>	s_movk_i32 s4, 0x70                                        ; B0040070
>	s_waitcnt lgkmcnt(0)                                       ; BF8C007F
>	s_buffer_load_dwordx2 s[0:1], s[12:15], 0x0                ; C0260006 00000000
>	buffer_load_format_x v9, v7, s[32:35], 0 idxen             ; E0002000 80080907
>	v_ashrrev_i32_e32 v7, 1, v0                                ; 220E0081
>	v_and_b32_e32 v0, 1, v0                                    ; 26000081
>	v_cvt_f32_i32_e32 v7, v7                                   ; 7E0E0B07
>	s_waitcnt lgkmcnt(0)                                       ; BF8C007F
>	s_mulk_i32 s0, 0xc0                                        ; B78000C0
>	s_lshl_b32 s1, s1, 6                                       ; 8E018601
>	s_add_i32 s1, s0, s1                                       ; 81010100
>	s_or_b32 s6, s0, 16                                        ; 87069000
>	s_or_b32 s7, s0, 20                                        ; 87079400
>	s_add_i32 s8, s1, 0x50                                     ; 8108FF01 00000050
>	s_add_i32 s10, s1, 0x54                                    ; 810AFF01 00000054
>	s_add_i32 s11, s1, 0x58                                    ; 810BFF01 00000058
>	s_add_i32 s16, s1, 0x5c                                    ; 8110FF01 0000005C
>	s_add_i32 s17, s1, s3                                      ; 81110301
>	s_add_i32 s18, s1, 0x64                                    ; 8112FF01 00000064
>	s_add_i32 s19, s1, 0x68                                    ; 8113FF01 00000068
>	s_add_i32 s20, s1, 0x6c                                    ; 8114FF01 0000006C
>	s_add_i32 s21, s1, s4                                      ; 81150401
>	s_add_i32 s22, s1, 0x74                                    ; 8116FF01 00000074
>	s_add_i32 s23, s1, 0x78                                    ; 8117FF01 00000078
>	s_add_i32 s24, s1, 0x7c                                    ; 8118FF01 0000007C
>	s_add_i32 s25, s1, 0x80                                    ; 8119FF01 00000080
>	s_add_i32 s26, s1, 0x84                                    ; 811AFF01 00000084
>	s_add_i32 s27, s1, 0x88                                    ; 811BFF01 00000088
>	s_addk_i32 s1, 0x8c                                        ; B701008C
>	s_buffer_load_dword s6, s[12:15], s6                       ; C0200186 00000006
>	s_buffer_load_dword s28, s[12:15], s7                      ; C0200706 00000007
>	s_buffer_load_dword s29, s[12:15], s8                      ; C0200746 00000008
>	s_buffer_load_dword s10, s[12:15], s10                     ; C0200286 0000000A
>	s_buffer_load_dword s11, s[12:15], s11                     ; C02002C6 0000000B
>	s_buffer_load_dword s16, s[12:15], s16                     ; C0200406 00000010
>	s_buffer_load_dword s17, s[12:15], s17                     ; C0200446 00000011
>	s_buffer_load_dword s18, s[12:15], s18                     ; C0200486 00000012
>	s_buffer_load_dword s19, s[12:15], s19                     ; C02004C6 00000013
>	s_buffer_load_dword s20, s[12:15], s20                     ; C0200506 00000014
>	s_buffer_load_dword s21, s[12:15], s21                     ; C0200546 00000015
>	s_buffer_load_dword s22, s[12:15], s22                     ; C0200586 00000016
>	s_buffer_load_dword s23, s[12:15], s23                     ; C02005C6 00000017
>	s_buffer_load_dword s24, s[12:15], s24                     ; C0200606 00000018
>	s_buffer_load_dword s25, s[12:15], s25                     ; C0200646 00000019
>	s_buffer_load_dword s26, s[12:15], s26                     ; C0200686 0000001A
>	s_buffer_load_dword s27, s[12:15], s27                     ; C02006C6 0000001B
>	s_buffer_load_dword s30, s[12:15], s1                      ; C0200786 00000001
>	s_add_i32 s7, s7, 4                                        ; 81078407
>	s_or_b32 s1, s0, 28                                        ; 87019C00
>	s_add_i32 s8, s2, s4                                       ; 81080402
>	v_cvt_f32_ubyte0_e32 v0, v0                                ; 7E002300
>	s_waitcnt vmcnt(4)                                         ; BF8C0F74
>	v_mul_f32_e32 v10, v1, v7                                  ; 0A140F01
>	v_mul_f32_e32 v11, v2, v0                                  ; 0A160102
>	s_waitcnt vmcnt(3)                                         ; BF8C0F73
>	v_add_u32_e32 v8, vcc, s5, v8                              ; 32101005
>	s_buffer_load_dword s5, s[12:15], s7                       ; C0200146 00000007
>	s_buffer_load_dword s7, s[12:15], s1                       ; C02001C6 00000001
>	s_or_b32 s1, s0, 32                                        ; 8701A000
>	s_buffer_load_dword s31, s[12:15], s1                      ; C02007C6 00000001
>	s_or_b32 s1, s0, 36                                        ; 8701A400
>	s_buffer_load_dword s32, s[12:15], s1                      ; C0200806 00000001
>	s_add_i32 s1, s1, 4                                        ; 81018401
>	s_buffer_load_dword s33, s[12:15], s1                      ; C0200846 00000001
>	s_or_b32 s1, s0, 44                                        ; 8701AC00
>	s_buffer_load_dword s34, s[12:15], s1                      ; C0200886 00000001
>	s_or_b32 s1, s0, 48                                        ; 8701B000
>	s_buffer_load_dword s35, s[12:15], s1                      ; C02008C6 00000001
>	s_or_b32 s1, s0, 52                                        ; 8701B400
>	s_buffer_load_dword s36, s[12:15], s1                      ; C0200906 00000001
>	s_add_i32 s1, s1, 4                                        ; 81018401
>	s_buffer_load_dword s37, s[12:15], s1                      ; C0200946 00000001
>	s_or_b32 s1, s0, 60                                        ; 8701BC00
>	s_buffer_load_dword s38, s[12:15], s1                      ; C0200986 00000001
>	s_add_i32 s1, s0, 64                                       ; 8101C000
>	s_buffer_load_dword s39, s[12:15], s1                      ; C02009C6 00000001
>	s_add_i32 s1, s0, 0x44                                     ; 8101FF00 00000044
>	s_buffer_load_dword s40, s[12:15], s1                      ; C0200A06 00000001
>	s_add_i32 s1, s0, 0x48                                     ; 8101FF00 00000048
>	s_addk_i32 s0, 0x4c                                        ; B700004C
>	s_buffer_load_dword s41, s[12:15], s1                      ; C0200A46 00000001
>	s_buffer_load_dword s12, s[12:15], s0                      ; C0200306 00000000
>	v_mul_lo_i32 v14, v8, s3                                   ; D285000E 00000708
>	s_load_dwordx4 s[0:3], s[8:9], 0x0                         ; C00A0004 00000000
>	s_waitcnt vmcnt(2)                                         ; BF8C0F72
>	v_add_f32_e32 v1, v3, v7                                   ; 02020F03
>	v_add_f32_e32 v0, v4, v0                                   ; 02000104
>	s_waitcnt vmcnt(1)                                         ; BF8C0F71
>	v_mul_f32_e32 v12, v5, v1                                  ; 0A180305
>	v_mul_f32_e32 v13, v6, v0                                  ; 0A1A0106
>	s_waitcnt lgkmcnt(0)                                       ; BF8C007F
>	buffer_load_dwordx4 v[0:3], v14, s[0:3], 0 offen           ; E05C1000 8000000E
>	buffer_load_dwordx4 v[4:7], v14, s[0:3], 0 offen offset:16 ; E05C1010 8000040E
>	s_waitcnt vmcnt(1)                                         ; BF8C0F71
>	v_mul_f32_e32 v15, v0, v10                                 ; 0A1E1500
>	v_mul_f32_e32 v16, v1, v10                                 ; 0A201501
>	v_mul_f32_e32 v17, v2, v10                                 ; 0A221502
>	v_mul_f32_e32 v10, v3, v10                                 ; 0A141503
>	s_waitcnt vmcnt(0)                                         ; BF8C0F70
>	v_mac_f32_e32 v15, v4, v11                                 ; 2C1E1704
>	v_mac_f32_e32 v16, v5, v11                                 ; 2C201705
>	v_mac_f32_e32 v17, v6, v11                                 ; 2C221706
>	v_mac_f32_e32 v10, v7, v11                                 ; 2C141707
>	buffer_load_dwordx4 v[0:3], v14, s[0:3], 0 offen offset:32 ; E05C1020 8000000E
>	buffer_load_dwordx4 v[4:7], v14, s[0:3], 0 offen offset:48 ; E05C1030 8000040E
>	s_waitcnt vmcnt(1)                                         ; BF8C0F71
>	v_mac_f32_e32 v15, 0, v0                                   ; 2C1E0080
>	v_mac_f32_e32 v16, 0, v1                                   ; 2C200280
>	s_waitcnt vmcnt(0)                                         ; BF8C0F70
>	v_add_f32_e32 v0, v4, v15                                  ; 02001F04
>	v_mac_f32_e32 v17, 0, v2                                   ; 2C220480
>	v_add_f32_e32 v1, v5, v16                                  ; 02022105
>	v_mul_f32_e32 v4, s6, v0                                   ; 0A080006
>	v_mac_f32_e32 v10, 0, v3                                   ; 2C140680
>	v_mul_f32_e32 v5, s28, v0                                  ; 0A0A001C
>	v_add_f32_e32 v2, v6, v17                                  ; 02042306
>	v_mul_f32_e32 v6, s5, v0                                   ; 0A0C0005
>	v_mul_f32_e32 v0, s7, v0                                   ; 0A000007
>	v_mac_f32_e32 v4, s31, v1                                  ; 2C08021F
>	v_mac_f32_e32 v5, s32, v1                                  ; 2C0A0220
>	v_mac_f32_e32 v6, s33, v1                                  ; 2C0C0221
>	v_mac_f32_e32 v0, s34, v1                                  ; 2C000222
>	v_add_f32_e32 v3, v7, v10                                  ; 02061507
>	v_mac_f32_e32 v4, s35, v2                                  ; 2C080423
>	v_mac_f32_e32 v5, s36, v2                                  ; 2C0A0424
>	v_mac_f32_e32 v6, s37, v2                                  ; 2C0C0425
>	v_mac_f32_e32 v0, s38, v2                                  ; 2C000426
>	v_mac_f32_e32 v4, s39, v3                                  ; 2C080627
>	v_mac_f32_e32 v5, s40, v3                                  ; 2C0A0628
>	v_mul_f32_e32 v1, s29, v4                                  ; 0A02081D
>	v_mul_f32_e32 v2, s10, v4                                  ; 0A04080A
>	v_mac_f32_e32 v6, s41, v3                                  ; 2C0C0629
>	v_mac_f32_e32 v0, s12, v3                                  ; 2C00060C
>	v_mul_f32_e32 v3, s11, v4                                  ; 0A06080B
>	v_mul_f32_e32 v4, s16, v4                                  ; 0A080810
>	v_mac_f32_e32 v1, s17, v5                                  ; 2C020A11
>	v_mac_f32_e32 v2, s18, v5                                  ; 2C040A12
>	v_mac_f32_e32 v3, s19, v5                                  ; 2C060A13
>	v_mac_f32_e32 v4, s20, v5                                  ; 2C080A14
>	v_mac_f32_e32 v1, s21, v6                                  ; 2C020C15
>	v_mac_f32_e32 v2, s22, v6                                  ; 2C040C16
>	v_mac_f32_e32 v3, s23, v6                                  ; 2C060C17
>	v_mac_f32_e32 v4, s24, v6                                  ; 2C080C18
>	v_mac_f32_e32 v1, s25, v0                                  ; 2C020019
>	v_mac_f32_e32 v2, s26, v0                                  ; 2C04001A
>	v_mac_f32_e32 v3, s27, v0                                  ; 2C06001B
>	v_mac_f32_e32 v4, s30, v0                                  ; 2C08001E
>	exp pos0 v1, v2, v3, v4 done                               ; C40008CF 04030201
>	exp param0 v12, v13, v0, v0                                ; C400020F 00000D0C
>	exp param1 v9, v0, v0, v0                                  ; C400021F 00000009
>	exp param2 v8, v0, v0, v0                                  ; C400022F 00000008
>	s_endpgm                                                   ; BF810000
>
>*** SHADER STATS ***
>SGPRS: 48
>VGPRS: 20
>Spilled SGPRs: 0
>Spilled VGPRs: 0
>Private memory VGPRs: 0
>Code Size: 1044 bytes
>LDS: 0 blocks
>Scratch: 0 bytes per wave
>Max Waves: 8
>********************
>
>
>SHADER KEY
>  part.ps.prolog.color_two_side = 0
>  part.ps.prolog.flatshade_colors = 0
>  part.ps.prolog.poly_stipple = 0
>  part.ps.prolog.force_persp_sample_interp = 0
>  part.ps.prolog.force_linear_sample_interp = 0
>  part.ps.prolog.force_persp_center_interp = 0
>  part.ps.prolog.force_linear_center_interp = 0
>  part.ps.prolog.bc_optimize_for_persp = 0
>  part.ps.prolog.bc_optimize_for_linear = 0
>  part.ps.epilog.spi_shader_col_format = 0x4
>  part.ps.epilog.color_is_int8 = 0x0
>  part.ps.epilog.color_is_int10 = 0x0
>  part.ps.epilog.last_cbuf = 0
>  part.ps.epilog.alpha_func = 7
>  part.ps.epilog.alpha_to_one = 0
>  part.ps.epilog.poly_line_smoothing = 0
>  part.ps.epilog.clamp_color = 0
>
>Pixel Shader:
>Shader main disassembly:
>main:
>BB0_0:
>	s_mov_b64 s[6:7], exec                                      ; BE86017E
>	v_mov_b32_e32 v14, v16                                      ; 7E1C0310
>	s_wqm_b64 exec, exec                                        ; BEFE077E
>	s_mov_b32 m0, s5                                            ; BEFC0005
>	s_add_i32 s8, s2, 0x70                                      ; 8108FF02 00000070
>	s_mov_b32 s9, 0                                             ; BE890080
>	v_interp_mov_f32_e32 v0, p0, attr2.x                        ; D4020802
>	s_movk_i32 s0, 0x60                                         ; B0000060
>	s_load_dwordx4 s[12:15], s[8:9], 0x0                        ; C00A0304 00000000
>	v_mul_lo_i32 v6, v0, s0                                     ; D2850006 00000100
>	v_interp_p1_f32_e32 v0, v2, attr0.x                         ; D4000002
>	v_interp_p1_f32_e32 v1, v2, attr0.y                         ; D4040102
>	v_mov_b32_e32 v2, 0                                         ; 7E040280
>	v_readfirstlane_b32 s11, v2                                 ; 7E160502
>	v_readfirstlane_b32 s17, v2                                 ; 7E220502
>	s_waitcnt lgkmcnt(0)                                        ; BF8C007F
>	buffer_load_dword v2, v6, s[12:15], 0 offen offset:64       ; E0501040 80030206
>	buffer_load_dwordx2 v[4:5], v6, s[12:15], 0 offen offset:72 ; E0541048 80030406
>	buffer_load_dword v6, v6, s[12:15], 0 offen offset:80       ; E0501050 80030606
>	v_interp_p2_f32_e32 v0, v3, attr0.x                         ; D4010003
>	v_interp_p2_f32_e32 v1, v3, attr0.y                         ; D4050103
>	s_waitcnt vmcnt(2)                                          ; BF8C0F72
>	v_lshlrev_b32_e32 v2, 6, v2                                 ; 24040486
>	v_add_u32_e32 v2, vcc, s1, v2                               ; 32040401
>	v_readfirstlane_b32 s10, v2                                 ; 7E140502
>	v_add_u32_e32 v2, vcc, 48, v2                               ; 320404B0
>	v_readfirstlane_b32 s16, v2                                 ; 7E200502
>	s_load_dwordx4 s[20:23], s[16:17], 0x0                      ; C00A0508 00000000
>	s_load_dwordx8 s[12:19], s[10:11], 0x0                      ; C00E0305 00000000
>	s_and_b64 exec, exec, s[6:7]                                ; 86FE067E
>	s_waitcnt lgkmcnt(0)                                        ; BF8C007F
>	s_nop 0                                                     ; BF800000
>	image_sample v[0:3], v[0:1], s[12:19], s[20:23] dmask:0xf   ; F0800F00 00A30000
>	s_waitcnt vmcnt(0)                                          ; BF8C0F70
>	v_mul_f32_e32 v3, v3, v4                                    ; 0A060903
>	v_max3_f32 v4, v0, v1, v2                                   ; D1D30004 040A0300
>	v_cmp_ge_f32_e32 vcc, v4, v5                                ; 7C8C0B04
>	v_cmp_ge_f32_e64 s[6:7], v3, v6                             ; D0460006 00020D03
>	s_or_b64 s[10:11], vcc, s[6:7]                              ; 878A066A
>	s_and_saveexec_b64 s[6:7], s[10:11]                         ; BE86200A
>	s_cbranch_execz BB0_2                                       ; BF880000
>BB0_1:
>	s_add_i32 s8, s2, 0x100                                     ; 8108FF02 00000100
>	s_load_dwordx4 s[12:15], s[8:9], 0x0                        ; C00A0304 00000000
>	s_add_i32 s8, s2, 0x110                                     ; 8108FF02 00000110
>	s_load_dwordx4 s[16:19], s[8:9], 0x0                        ; C00A0404 00000000
>	s_mov_b32 m0, s5                                            ; BEFC0005
>	v_interp_mov_f32_e32 v6, p0, attr1.x                        ; D41A0402
>	s_waitcnt lgkmcnt(0)                                        ; BF8C007F
>	s_buffer_load_dwordx2 s[2:3], s[12:15], 0x0                 ; C0260086 00000000
>	s_buffer_load_dword s0, s[16:19], 0x0                       ; C0220008 00000000
>	s_waitcnt lgkmcnt(0)                                        ; BF8C007F
>	v_mov_b32_e32 v4, s3                                        ; 7E080203
>	v_mad_f32 v5, s2, v13, v4                                   ; D1C10005 04121A02
>	s_lshl_b32 s0, s0, 4                                        ; 8E008400
>	s_addk_i32 s0, 0xf10                                        ; B7000F10
>	s_buffer_load_dword s0, s[16:19], s0                        ; C0200008 00000000
>	v_cvt_i32_f32_e32 v4, v12                                   ; 7E08110C
>	v_cvt_i32_f32_e32 v5, v5                                    ; 7E0A1105
>	s_waitcnt lgkmcnt(0)                                        ; BF8C007F
>	s_lshl_b32 s0, s0, 6                                        ; 8E008600
>	s_add_i32 s8, s1, s0                                        ; 81080001
>	s_load_dwordx8 s[8:15], s[8:9], 0x0                         ; C00E0204 00000000
>	s_waitcnt lgkmcnt(0)                                        ; BF8C007F
>	s_and_b32 s14, s14, 0xffdfffff                              ; 860EFF0E FFDFFFFF
>	image_atomic_umax v6, v[4:5], s[8:15] dmask:0x1 unorm glc   ; F05C3100 00020604
>BB0_2:
>	s_or_b64 exec, exec, s[6:7]                                 ; 87FE067E
>	v_mul_f32_e32 v0, v0, v3                                    ; 0A000700
>	v_mul_f32_e32 v1, v1, v3                                    ; 0A020701
>	v_mul_f32_e32 v2, v2, v3                                    ; 0A040702
>	s_waitcnt vmcnt(0)                                          ; BF8C0F70
>Shader epilog disassembly:
>ps_epilog:
>BB0_0:
>	v_cvt_pkrtz_f16_f32 v0, v0, v1        ; D2960000 00020300
>	v_cvt_pkrtz_f16_f32 v1, v2, v3        ; D2960001 00020702
>	exp mrt0 v0, v0, v1, v1 done compr vm ; C4001C0F 00000100
>	s_endpgm                              ; BF810000
>
>*** SHADER CONFIG ***
>SPI_PS_INPUT_ADDR = 0xf377
>SPI_PS_INPUT_ENA  = 0x0302
>*** SHADER STATS ***
>SGPRS: 32
>VGPRS: 24
>Spilled SGPRs: 0
>Spilled VGPRs: 0
>Private memory VGPRs: 0
>Code Size: 416 bytes
>LDS: 0 blocks
>Scratch: 0 bytes per wave
>Max Waves: 8
>********************
>
>
>[1;32mRW buffers slot 0 (GPU list):[0m
>        [1;33mSQ_BUF_RSRC_WORD0[0m <- 0x0a279000
>        [1;33mSQ_BUF_RSRC_WORD1[0m <- BASE_ADDRESS_HI = 1
>                             STRIDE = 0
>                             CACHE_SWIZZLE = 0
>                             SWIZZLE_ENABLE = 1
>        [1;33mSQ_BUF_RSRC_WORD2[0m <- 0x00180000
>        [1;33mSQ_BUF_RSRC_WORD3[0m <- DST_SEL_X = SQ_SEL_X
>                             DST_SEL_Y = SQ_SEL_Y
>                             DST_SEL_Z = SQ_SEL_Z
>                             DST_SEL_W = SQ_SEL_W
>                             NUM_FORMAT = BUF_NUM_FORMAT_FLOAT
>                             DATA_FORMAT = BUF_DATA_FORMAT_32
>                             ELEMENT_SIZE = 1
>                             INDEX_STRIDE = 3
>                             ADD_TID_ENABLE = 1
>                             ATC = 0
>                             HASH_ENABLE = 0
>                             HEAP = 0
>                             MTYPE = 0
>                             TYPE = SQ_RSRC_BUF
>
>[1;32mRW buffers slot 1 (GPU list):[0m
>        [1;33mSQ_BUF_RSRC_WORD0[0m <- 0x0a279000
>        [1;33mSQ_BUF_RSRC_WORD1[0m <- BASE_ADDRESS_HI = 1
>                             STRIDE = 0
>                             CACHE_SWIZZLE = 0
>                             SWIZZLE_ENABLE = 0
>        [1;33mSQ_BUF_RSRC_WORD2[0m <- 0x00180000
>        [1;33mSQ_BUF_RSRC_WORD3[0m <- DST_SEL_X = SQ_SEL_X
>                             DST_SEL_Y = SQ_SEL_Y
>                             DST_SEL_Z = SQ_SEL_Z
>                             DST_SEL_W = SQ_SEL_W
>                             NUM_FORMAT = BUF_NUM_FORMAT_FLOAT
>                             DATA_FORMAT = BUF_DATA_FORMAT_32
>                             ELEMENT_SIZE = 0
>                             INDEX_STRIDE = 0
>                             ADD_TID_ENABLE = 0
>                             ATC = 0
>                             HASH_ENABLE = 0
>                             HEAP = 0
>                             MTYPE = 0
>                             TYPE = SQ_RSRC_BUF
>
>[1;32mRW buffers slot 2 (GPU list):[0m
>        [1;33mSQ_BUF_RSRC_WORD0[0m <- 0x35800000
>        [1;33mSQ_BUF_RSRC_WORD1[0m <- BASE_ADDRESS_HI = 1
>                             STRIDE = 0
>                             CACHE_SWIZZLE = 0
>                             SWIZZLE_ENABLE = 0
>        [1;33mSQ_BUF_RSRC_WORD2[0m <- 0x02500000
>        [1;33mSQ_BUF_RSRC_WORD3[0m <- DST_SEL_X = SQ_SEL_X
>                             DST_SEL_Y = SQ_SEL_Y
>                             DST_SEL_Z = SQ_SEL_Z
>                             DST_SEL_W = SQ_SEL_W
>                             NUM_FORMAT = BUF_NUM_FORMAT_FLOAT
>                             DATA_FORMAT = BUF_DATA_FORMAT_32
>                             ELEMENT_SIZE = 0
>                             INDEX_STRIDE = 0
>                             ADD_TID_ENABLE = 0
>                             ATC = 0
>                             HASH_ENABLE = 0
>                             HEAP = 0
>                             MTYPE = 0
>                             TYPE = SQ_RSRC_BUF
>
>[1;32mRW buffers slot 3 (GPU list):[0m
>        [1;33mSQ_BUF_RSRC_WORD0[0m <- 0
>        [1;33mSQ_BUF_RSRC_WORD1[0m <- BASE_ADDRESS_HI = 0
>                             STRIDE = 0
>                             CACHE_SWIZZLE = 0
>                             SWIZZLE_ENABLE = 0
>        [1;33mSQ_BUF_RSRC_WORD2[0m <- 0
>        [1;33mSQ_BUF_RSRC_WORD3[0m <- DST_SEL_X = SQ_SEL_0
>                             DST_SEL_Y = SQ_SEL_0
>                             DST_SEL_Z = SQ_SEL_0
>                             DST_SEL_W = SQ_SEL_0
>                             NUM_FORMAT = BUF_NUM_FORMAT_UNORM
>                             DATA_FORMAT = BUF_DATA_FORMAT_INVALID
>                             ELEMENT_SIZE = 0
>                             INDEX_STRIDE = 0
>                             ADD_TID_ENABLE = 0
>                             ATC = 0
>                             HASH_ENABLE = 0
>                             HEAP = 0
>                             MTYPE = 0
>                             TYPE = SQ_RSRC_BUF
>
>[1;32mRW buffers slot 4 (GPU list):[0m
>        [1;33mSQ_BUF_RSRC_WORD0[0m <- 0
>        [1;33mSQ_BUF_RSRC_WORD1[0m <- BASE_ADDRESS_HI = 0
>                             STRIDE = 0
>                             CACHE_SWIZZLE = 0
>                             SWIZZLE_ENABLE = 0
>        [1;33mSQ_BUF_RSRC_WORD2[0m <- 0
>        [1;33mSQ_BUF_RSRC_WORD3[0m <- DST_SEL_X = SQ_SEL_0
>                             DST_SEL_Y = SQ_SEL_0
>                             DST_SEL_Z = SQ_SEL_0
>                             DST_SEL_W = SQ_SEL_0
>                             NUM_FORMAT = BUF_NUM_FORMAT_UNORM
>                             DATA_FORMAT = BUF_DATA_FORMAT_INVALID
>                             ELEMENT_SIZE = 0
>                             INDEX_STRIDE = 0
>                             ADD_TID_ENABLE = 0
>                             ATC = 0
>                             HASH_ENABLE = 0
>                             HEAP = 0
>                             MTYPE = 0
>                             TYPE = SQ_RSRC_BUF
>
>[1;32mRW buffers slot 5 (GPU list):[0m
>        [1;33mSQ_BUF_RSRC_WORD0[0m <- 0
>        [1;33mSQ_BUF_RSRC_WORD1[0m <- BASE_ADDRESS_HI = 0
>                             STRIDE = 0
>                             CACHE_SWIZZLE = 0
>                             SWIZZLE_ENABLE = 0
>        [1;33mSQ_BUF_RSRC_WORD2[0m <- 0
>        [1;33mSQ_BUF_RSRC_WORD3[0m <- DST_SEL_X = SQ_SEL_0
>                             DST_SEL_Y = SQ_SEL_0
>                             DST_SEL_Z = SQ_SEL_0
>                             DST_SEL_W = SQ_SEL_0
>                             NUM_FORMAT = BUF_NUM_FORMAT_UNORM
>                             DATA_FORMAT = BUF_DATA_FORMAT_INVALID
>                             ELEMENT_SIZE = 0
>                             INDEX_STRIDE = 0
>                             ADD_TID_ENABLE = 0
>                             ATC = 0
>                             HASH_ENABLE = 0
>                             HEAP = 0
>                             MTYPE = 0
>                             TYPE = SQ_RSRC_BUF
>
>[1;32mRW buffers slot 6 (GPU list):[0m
>        [1;33mSQ_BUF_RSRC_WORD0[0m <- 0
>        [1;33mSQ_BUF_RSRC_WORD1[0m <- BASE_ADDRESS_HI = 0
>                             STRIDE = 0
>                             CACHE_SWIZZLE = 0
>                             SWIZZLE_ENABLE = 0
>        [1;33mSQ_BUF_RSRC_WORD2[0m <- 0
>        [1;33mSQ_BUF_RSRC_WORD3[0m <- DST_SEL_X = SQ_SEL_0
>                             DST_SEL_Y = SQ_SEL_0
>                             DST_SEL_Z = SQ_SEL_0
>                             DST_SEL_W = SQ_SEL_0
>                             NUM_FORMAT = BUF_NUM_FORMAT_UNORM
>                             DATA_FORMAT = BUF_DATA_FORMAT_INVALID
>                             ELEMENT_SIZE = 0
>                             INDEX_STRIDE = 0
>                             ADD_TID_ENABLE = 0
>                             ATC = 0
>                             HASH_ENABLE = 0
>                             HEAP = 0
>                             MTYPE = 0
>                             TYPE = SQ_RSRC_BUF
>
>[1;32mRW buffers slot 7 (GPU list):[0m
>        [1;33mSQ_BUF_RSRC_WORD0[0m <- 0x015304c0
>        [1;33mSQ_BUF_RSRC_WORD1[0m <- BASE_ADDRESS_HI = 0
>                             STRIDE = 0
>                             CACHE_SWIZZLE = 0
>                             SWIZZLE_ENABLE = 0
>        [1;33mSQ_BUF_RSRC_WORD2[0m <- 32 (0x00000020)
>        [1;33mSQ_BUF_RSRC_WORD3[0m <- DST_SEL_X = SQ_SEL_X
>                             DST_SEL_Y = SQ_SEL_Y
>                             DST_SEL_Z = SQ_SEL_Z
>                             DST_SEL_W = SQ_SEL_W
>                             NUM_FORMAT = BUF_NUM_FORMAT_FLOAT
>                             DATA_FORMAT = BUF_DATA_FORMAT_32
>                             ELEMENT_SIZE = 0
>                             INDEX_STRIDE = 0
>                             ADD_TID_ENABLE = 0
>                             ATC = 0
>                             HASH_ENABLE = 0
>                             HEAP = 0
>                             MTYPE = 0
>                             TYPE = SQ_RSRC_BUF
>
>[1;32mRW buffers slot 8 (GPU list):[0m
>        [1;33mSQ_BUF_RSRC_WORD0[0m <- 0
>        [1;33mSQ_BUF_RSRC_WORD1[0m <- BASE_ADDRESS_HI = 0
>                             STRIDE = 0
>                             CACHE_SWIZZLE = 0
>                             SWIZZLE_ENABLE = 0
>        [1;33mSQ_BUF_RSRC_WORD2[0m <- 0
>        [1;33mSQ_BUF_RSRC_WORD3[0m <- DST_SEL_X = SQ_SEL_0
>                             DST_SEL_Y = SQ_SEL_0
>                             DST_SEL_Z = SQ_SEL_0
>                             DST_SEL_W = SQ_SEL_0
>                             NUM_FORMAT = BUF_NUM_FORMAT_UNORM
>                             DATA_FORMAT = BUF_DATA_FORMAT_INVALID
>                             ELEMENT_SIZE = 0
>                             INDEX_STRIDE = 0
>                             ADD_TID_ENABLE = 0
>                             ATC = 0
>                             HASH_ENABLE = 0
>                             HEAP = 0
>                             MTYPE = 0
>                             TYPE = SQ_RSRC_BUF
>
>[1;32mRW buffers slot 9 (GPU list):[0m
>        [1;33mSQ_BUF_RSRC_WORD0[0m <- 0
>        [1;33mSQ_BUF_RSRC_WORD1[0m <- BASE_ADDRESS_HI = 0
>                             STRIDE = 0
>                             CACHE_SWIZZLE = 0
>                             SWIZZLE_ENABLE = 0
>        [1;33mSQ_BUF_RSRC_WORD2[0m <- 0
>        [1;33mSQ_BUF_RSRC_WORD3[0m <- DST_SEL_X = SQ_SEL_0
>                             DST_SEL_Y = SQ_SEL_0
>                             DST_SEL_Z = SQ_SEL_0
>                             DST_SEL_W = SQ_SEL_0
>                             NUM_FORMAT = BUF_NUM_FORMAT_UNORM
>                             DATA_FORMAT = BUF_DATA_FORMAT_INVALID
>                             ELEMENT_SIZE = 0
>                             INDEX_STRIDE = 0
>                             ADD_TID_ENABLE = 0
>                             ATC = 0
>                             HASH_ENABLE = 0
>                             HEAP = 0
>                             MTYPE = 0
>                             TYPE = SQ_RSRC_BUF
>
>[1;32mRW buffers slot 10 (GPU list):[0m
>        [1;33mSQ_BUF_RSRC_WORD0[0m <- 0x01530440
>        [1;33mSQ_BUF_RSRC_WORD1[0m <- BASE_ADDRESS_HI = 0
>                             STRIDE = 0
>                             CACHE_SWIZZLE = 0
>                             SWIZZLE_ENABLE = 0
>        [1;33mSQ_BUF_RSRC_WORD2[0m <- 128 (0x00000080)
>        [1;33mSQ_BUF_RSRC_WORD3[0m <- DST_SEL_X = SQ_SEL_X
>                             DST_SEL_Y = SQ_SEL_Y
>                             DST_SEL_Z = SQ_SEL_Z
>                             DST_SEL_W = SQ_SEL_W
>                             NUM_FORMAT = BUF_NUM_FORMAT_FLOAT
>                             DATA_FORMAT = BUF_DATA_FORMAT_32
>                             ELEMENT_SIZE = 0
>                             INDEX_STRIDE = 0
>                             ADD_TID_ENABLE = 0
>                             ATC = 0
>                             HASH_ENABLE = 0
>                             HEAP = 0
>                             MTYPE = 0
>                             TYPE = SQ_RSRC_BUF
>
>[1;32mRW buffers slot 11 (GPU list):[0m
>        [1;33mSQ_BUF_RSRC_WORD0[0m <- 0x00100000
>        [1;33mSQ_BUF_RSRC_WORD1[0m <- BASE_ADDRESS_HI = 0
>                             STRIDE = 0
>                             CACHE_SWIZZLE = 0
>                             SWIZZLE_ENABLE = 0
>        [1;33mSQ_BUF_RSRC_WORD2[0m <- 8
>        [1;33mSQ_BUF_RSRC_WORD3[0m <- DST_SEL_X = SQ_SEL_X
>                             DST_SEL_Y = SQ_SEL_Y
>                             DST_SEL_Z = SQ_SEL_Z
>                             DST_SEL_W = SQ_SEL_W
>                             NUM_FORMAT = BUF_NUM_FORMAT_FLOAT
>                             DATA_FORMAT = BUF_DATA_FORMAT_32
>                             ELEMENT_SIZE = 0
>                             INDEX_STRIDE = 0
>                             ADD_TID_ENABLE = 0
>                             ATC = 0
>                             HASH_ENABLE = 0
>                             HEAP = 0
>                             MTYPE = 0
>                             TYPE = SQ_RSRC_BUF
>
>[1;32mRW buffers slot 12 (GPU list):[0m
>        [1;33mSQ_BUF_RSRC_WORD0[0m <- 0
>        [1;33mSQ_BUF_RSRC_WORD1[0m <- BASE_ADDRESS_HI = 0
>                             STRIDE = 0
>                             CACHE_SWIZZLE = 0
>                             SWIZZLE_ENABLE = 0
>        [1;33mSQ_BUF_RSRC_WORD2[0m <- 0
>        [1;33mSQ_BUF_RSRC_WORD3[0m <- DST_SEL_X = SQ_SEL_0
>                             DST_SEL_Y = SQ_SEL_0
>                             DST_SEL_Z = SQ_SEL_0
>                             DST_SEL_W = SQ_SEL_0
>                             NUM_FORMAT = BUF_NUM_FORMAT_UNORM
>                             DATA_FORMAT = BUF_DATA_FORMAT_INVALID
>                             ELEMENT_SIZE = 0
>                             INDEX_STRIDE = 0
>                             ADD_TID_ENABLE = 0
>                             ATC = 0
>                             HASH_ENABLE = 0
>                             HEAP = 0
>                             MTYPE = 0
>                             TYPE = SQ_RSRC_BUF
>
>[1;32mRW buffers slot 13 (GPU list):[0m
>        [1;33mSQ_BUF_RSRC_WORD0[0m <- 0
>        [1;33mSQ_BUF_RSRC_WORD1[0m <- BASE_ADDRESS_HI = 0
>                             STRIDE = 0
>                             CACHE_SWIZZLE = 0
>                             SWIZZLE_ENABLE = 0
>        [1;33mSQ_BUF_RSRC_WORD2[0m <- 0
>        [1;33mSQ_BUF_RSRC_WORD3[0m <- DST_SEL_X = SQ_SEL_0
>                             DST_SEL_Y = SQ_SEL_0
>                             DST_SEL_Z = SQ_SEL_0
>                             DST_SEL_W = SQ_SEL_0
>                             NUM_FORMAT = BUF_NUM_FORMAT_UNORM
>                             DATA_FORMAT = BUF_DATA_FORMAT_INVALID
>                             ELEMENT_SIZE = 0
>                             INDEX_STRIDE = 0
>                             ADD_TID_ENABLE = 0
>                             ATC = 0
>                             HASH_ENABLE = 0
>                             HEAP = 0
>                             MTYPE = 0
>                             TYPE = SQ_RSRC_BUF
>
>[1;32mRW buffers slot 14 (GPU list):[0m
>        [1;33mSQ_BUF_RSRC_WORD0[0m <- 0
>        [1;33mSQ_BUF_RSRC_WORD1[0m <- BASE_ADDRESS_HI = 0
>                             STRIDE = 0
>                             CACHE_SWIZZLE = 0
>                             SWIZZLE_ENABLE = 0
>        [1;33mSQ_BUF_RSRC_WORD2[0m <- 0
>        [1;33mSQ_BUF_RSRC_WORD3[0m <- DST_SEL_X = SQ_SEL_0
>                             DST_SEL_Y = SQ_SEL_0
>                             DST_SEL_Z = SQ_SEL_0
>                             DST_SEL_W = SQ_SEL_0
>                             NUM_FORMAT = BUF_NUM_FORMAT_UNORM
>                             DATA_FORMAT = BUF_DATA_FORMAT_INVALID
>                             ELEMENT_SIZE = 0
>                             INDEX_STRIDE = 0
>                             ADD_TID_ENABLE = 0
>                             ATC = 0
>                             HASH_ENABLE = 0
>                             HEAP = 0
>                             MTYPE = 0
>                             TYPE = SQ_RSRC_BUF
>
>[1;32mRW buffers slot 15 (GPU list):[0m
>        [1;33mSQ_BUF_RSRC_WORD0[0m <- 0
>        [1;33mSQ_BUF_RSRC_WORD1[0m <- BASE_ADDRESS_HI = 0
>                             STRIDE = 0
>                             CACHE_SWIZZLE = 0
>                             SWIZZLE_ENABLE = 0
>        [1;33mSQ_BUF_RSRC_WORD2[0m <- 0
>        [1;33mSQ_BUF_RSRC_WORD3[0m <- DST_SEL_X = SQ_SEL_0
>                             DST_SEL_Y = SQ_SEL_0
>                             DST_SEL_Z = SQ_SEL_0
>                             DST_SEL_W = SQ_SEL_0
>                             NUM_FORMAT = BUF_NUM_FORMAT_UNORM
>                             DATA_FORMAT = BUF_DATA_FORMAT_INVALID
>                             ELEMENT_SIZE = 0
>                             INDEX_STRIDE = 0
>                             ADD_TID_ENABLE = 0
>                             ATC = 0
>                             HASH_ENABLE = 0
>                             HEAP = 0
>                             MTYPE = 0
>                             TYPE = SQ_RSRC_BUF
>
>[1;32mVS - Vertex buffer slot 0 (GPU list):[0m
>        [1;33mSQ_BUF_RSRC_WORD0[0m <- 0x09040000
>        [1;33mSQ_BUF_RSRC_WORD1[0m <- BASE_ADDRESS_HI = 1
>                             STRIDE = 32 (0x020)
>                             CACHE_SWIZZLE = 0
>                             SWIZZLE_ENABLE = 0
>        [1;33mSQ_BUF_RSRC_WORD2[0m <- 0x000bdc00
>        [1;33mSQ_BUF_RSRC_WORD3[0m <- DST_SEL_X = SQ_SEL_X
>                             DST_SEL_Y = SQ_SEL_Y
>                             DST_SEL_Z = SQ_SEL_0
>                             DST_SEL_W = SQ_SEL_1
>                             NUM_FORMAT = BUF_NUM_FORMAT_FLOAT
>                             DATA_FORMAT = BUF_DATA_FORMAT_32_32
>                             ELEMENT_SIZE = 0
>                             INDEX_STRIDE = 0
>                             ADD_TID_ENABLE = 0
>                             ATC = 0
>                             HASH_ENABLE = 0
>                             HEAP = 0
>                             MTYPE = 0
>                             TYPE = SQ_RSRC_BUF
>
>[1;32mVS - Vertex buffer slot 1 (GPU list):[0m
>        [1;33mSQ_BUF_RSRC_WORD0[0m <- 0x09040008
>        [1;33mSQ_BUF_RSRC_WORD1[0m <- BASE_ADDRESS_HI = 1
>                             STRIDE = 32 (0x020)
>                             CACHE_SWIZZLE = 0
>                             SWIZZLE_ENABLE = 0
>        [1;33mSQ_BUF_RSRC_WORD2[0m <- 0x000bdbf8
>        [1;33mSQ_BUF_RSRC_WORD3[0m <- DST_SEL_X = SQ_SEL_X
>                             DST_SEL_Y = SQ_SEL_Y
>                             DST_SEL_Z = SQ_SEL_0
>                             DST_SEL_W = SQ_SEL_1
>                             NUM_FORMAT = BUF_NUM_FORMAT_FLOAT
>                             DATA_FORMAT = BUF_DATA_FORMAT_32_32
>                             ELEMENT_SIZE = 0
>                             INDEX_STRIDE = 0
>                             ADD_TID_ENABLE = 0
>                             ATC = 0
>                             HASH_ENABLE = 0
>                             HEAP = 0
>                             MTYPE = 0
>                             TYPE = SQ_RSRC_BUF
>
>[1;32mVS - Vertex buffer slot 2 (GPU list):[0m
>        [1;33mSQ_BUF_RSRC_WORD0[0m <- 0x09040010
>        [1;33mSQ_BUF_RSRC_WORD1[0m <- BASE_ADDRESS_HI = 1
>                             STRIDE = 32 (0x020)
>                             CACHE_SWIZZLE = 0
>                             SWIZZLE_ENABLE = 0
>        [1;33mSQ_BUF_RSRC_WORD2[0m <- 0x000bdbf0
>        [1;33mSQ_BUF_RSRC_WORD3[0m <- DST_SEL_X = SQ_SEL_X
>                             DST_SEL_Y = SQ_SEL_Y
>                             DST_SEL_Z = SQ_SEL_0
>                             DST_SEL_W = SQ_SEL_1
>                             NUM_FORMAT = BUF_NUM_FORMAT_FLOAT
>                             DATA_FORMAT = BUF_DATA_FORMAT_32_32
>                             ELEMENT_SIZE = 0
>                             INDEX_STRIDE = 0
>                             ADD_TID_ENABLE = 0
>                             ATC = 0
>                             HASH_ENABLE = 0
>                             HEAP = 0
>                             MTYPE = 0
>                             TYPE = SQ_RSRC_BUF
>
>[1;32mVS - Vertex buffer slot 3 (GPU list):[0m
>        [1;33mSQ_BUF_RSRC_WORD0[0m <- 0x09040018
>        [1;33mSQ_BUF_RSRC_WORD1[0m <- BASE_ADDRESS_HI = 1
>                             STRIDE = 32 (0x020)
>                             CACHE_SWIZZLE = 0
>                             SWIZZLE_ENABLE = 0
>        [1;33mSQ_BUF_RSRC_WORD2[0m <- 0x000bdbe8
>        [1;33mSQ_BUF_RSRC_WORD3[0m <- DST_SEL_X = SQ_SEL_X
>                             DST_SEL_Y = SQ_SEL_0
>                             DST_SEL_Z = SQ_SEL_0
>                             DST_SEL_W = SQ_SEL_1
>                             NUM_FORMAT = BUF_NUM_FORMAT_UINT
>                             DATA_FORMAT = BUF_DATA_FORMAT_32
>                             ELEMENT_SIZE = 0
>                             INDEX_STRIDE = 0
>                             ADD_TID_ENABLE = 0
>                             ATC = 0
>                             HASH_ENABLE = 0
>                             HEAP = 0
>                             MTYPE = 0
>                             TYPE = SQ_RSRC_BUF
>
>[1;32mVS - Vertex buffer slot 4 (GPU list):[0m
>        [1;33mSQ_BUF_RSRC_WORD0[0m <- 0x0904001c
>        [1;33mSQ_BUF_RSRC_WORD1[0m <- BASE_ADDRESS_HI = 1
>                             STRIDE = 32 (0x020)
>                             CACHE_SWIZZLE = 0
>                             SWIZZLE_ENABLE = 0
>        [1;33mSQ_BUF_RSRC_WORD2[0m <- 0x000bdbe4
>        [1;33mSQ_BUF_RSRC_WORD3[0m <- DST_SEL_X = SQ_SEL_X
>                             DST_SEL_Y = SQ_SEL_0
>                             DST_SEL_Z = SQ_SEL_0
>                             DST_SEL_W = SQ_SEL_1
>                             NUM_FORMAT = BUF_NUM_FORMAT_UINT
>                             DATA_FORMAT = BUF_DATA_FORMAT_32
>                             ELEMENT_SIZE = 0
>                             INDEX_STRIDE = 0
>                             ADD_TID_ENABLE = 0
>                             ATC = 0
>                             HASH_ENABLE = 0
>                             HEAP = 0
>                             MTYPE = 0
>                             TYPE = SQ_RSRC_BUF
>
>[1;32mVS - Constant buffer slot 0 (GPU list):[0m
>        [1;33mSQ_BUF_RSRC_WORD0[0m <- 0x00326ec0
>        [1;33mSQ_BUF_RSRC_WORD1[0m <- BASE_ADDRESS_HI = 0
>                             STRIDE = 0
>                             CACHE_SWIZZLE = 0
>                             SWIZZLE_ENABLE = 0
>        [1;33mSQ_BUF_RSRC_WORD2[0m <- 16 (0x00000010)
>        [1;33mSQ_BUF_RSRC_WORD3[0m <- DST_SEL_X = SQ_SEL_X
>                             DST_SEL_Y = SQ_SEL_Y
>                             DST_SEL_Z = SQ_SEL_Z
>                             DST_SEL_W = SQ_SEL_W
>                             NUM_FORMAT = BUF_NUM_FORMAT_FLOAT
>                             DATA_FORMAT = BUF_DATA_FORMAT_32
>                             ELEMENT_SIZE = 0
>                             INDEX_STRIDE = 0
>                             ADD_TID_ENABLE = 0
>                             ATC = 0
>                             HASH_ENABLE = 0
>                             HEAP = 0
>                             MTYPE = 0
>                             TYPE = SQ_RSRC_BUF
>
>[1;32mVS - Constant buffer slot 1 (GPU list):[0m
>        [1;33mSQ_BUF_RSRC_WORD0[0m <- 0x09182000
>        [1;33mSQ_BUF_RSRC_WORD1[0m <- BASE_ADDRESS_HI = 1
>                             STRIDE = 0
>                             CACHE_SWIZZLE = 0
>                             SWIZZLE_ENABLE = 0
>        [1;33mSQ_BUF_RSRC_WORD2[0m <- 4016 (0x00000fb0)
>        [1;33mSQ_BUF_RSRC_WORD3[0m <- DST_SEL_X = SQ_SEL_X
>                             DST_SEL_Y = SQ_SEL_Y
>                             DST_SEL_Z = SQ_SEL_Z
>                             DST_SEL_W = SQ_SEL_W
>                             NUM_FORMAT = BUF_NUM_FORMAT_FLOAT
>                             DATA_FORMAT = BUF_DATA_FORMAT_32
>                             ELEMENT_SIZE = 0
>                             INDEX_STRIDE = 0
>                             ADD_TID_ENABLE = 0
>                             ATC = 0
>                             HASH_ENABLE = 0
>                             HEAP = 0
>                             MTYPE = 0
>                             TYPE = SQ_RSRC_BUF
>
>[1;32mVS - Shader buffer slot 0 (GPU list):[0m
>        [1;33mSQ_BUF_RSRC_WORD0[0m <- 0
>        [1;33mSQ_BUF_RSRC_WORD1[0m <- BASE_ADDRESS_HI = 0
>                             STRIDE = 0
>                             CACHE_SWIZZLE = 0
>                             SWIZZLE_ENABLE = 0
>        [1;33mSQ_BUF_RSRC_WORD2[0m <- 0
>        [1;33mSQ_BUF_RSRC_WORD3[0m <- DST_SEL_X = SQ_SEL_0
>                             DST_SEL_Y = SQ_SEL_0
>                             DST_SEL_Z = SQ_SEL_0
>                             DST_SEL_W = SQ_SEL_0
>                             NUM_FORMAT = BUF_NUM_FORMAT_UNORM
>                             DATA_FORMAT = BUF_DATA_FORMAT_INVALID
>                             ELEMENT_SIZE = 0
>                             INDEX_STRIDE = 0
>                             ADD_TID_ENABLE = 0
>                             ATC = 0
>                             HASH_ENABLE = 0
>                             HEAP = 0
>                             MTYPE = 0
>                             TYPE = SQ_RSRC_BUF
>
>[1;32mVS - Shader buffer slot 1 (GPU list):[0m
>        [1;33mSQ_BUF_RSRC_WORD0[0m <- 0
>        [1;33mSQ_BUF_RSRC_WORD1[0m <- BASE_ADDRESS_HI = 0
>                             STRIDE = 0
>                             CACHE_SWIZZLE = 0
>                             SWIZZLE_ENABLE = 0
>        [1;33mSQ_BUF_RSRC_WORD2[0m <- 0
>        [1;33mSQ_BUF_RSRC_WORD3[0m <- DST_SEL_X = SQ_SEL_0
>                             DST_SEL_Y = SQ_SEL_0
>                             DST_SEL_Z = SQ_SEL_0
>                             DST_SEL_W = SQ_SEL_0
>                             NUM_FORMAT = BUF_NUM_FORMAT_UNORM
>                             DATA_FORMAT = BUF_DATA_FORMAT_INVALID
>                             ELEMENT_SIZE = 0
>                             INDEX_STRIDE = 0
>                             ADD_TID_ENABLE = 0
>                             ATC = 0
>                             HASH_ENABLE = 0
>                             HEAP = 0
>                             MTYPE = 0
>                             TYPE = SQ_RSRC_BUF
>
>[1;32mVS - Shader buffer slot 2 (GPU list):[0m
>        [1;33mSQ_BUF_RSRC_WORD0[0m <- 0
>        [1;33mSQ_BUF_RSRC_WORD1[0m <- BASE_ADDRESS_HI = 0
>                             STRIDE = 0
>                             CACHE_SWIZZLE = 0
>                             SWIZZLE_ENABLE = 0
>        [1;33mSQ_BUF_RSRC_WORD2[0m <- 0
>        [1;33mSQ_BUF_RSRC_WORD3[0m <- DST_SEL_X = SQ_SEL_0
>                             DST_SEL_Y = SQ_SEL_0
>                             DST_SEL_Z = SQ_SEL_0
>                             DST_SEL_W = SQ_SEL_0
>                             NUM_FORMAT = BUF_NUM_FORMAT_UNORM
>                             DATA_FORMAT = BUF_DATA_FORMAT_INVALID
>                             ELEMENT_SIZE = 0
>                             INDEX_STRIDE = 0
>                             ADD_TID_ENABLE = 0
>                             ATC = 0
>                             HASH_ENABLE = 0
>                             HEAP = 0
>                             MTYPE = 0
>                             TYPE = SQ_RSRC_BUF
>
>[1;32mVS - Shader buffer slot 3 (GPU list):[0m
>        [1;33mSQ_BUF_RSRC_WORD0[0m <- 0
>        [1;33mSQ_BUF_RSRC_WORD1[0m <- BASE_ADDRESS_HI = 0
>                             STRIDE = 0
>                             CACHE_SWIZZLE = 0
>                             SWIZZLE_ENABLE = 0
>        [1;33mSQ_BUF_RSRC_WORD2[0m <- 0
>        [1;33mSQ_BUF_RSRC_WORD3[0m <- DST_SEL_X = SQ_SEL_0
>                             DST_SEL_Y = SQ_SEL_0
>                             DST_SEL_Z = SQ_SEL_0
>                             DST_SEL_W = SQ_SEL_0
>                             NUM_FORMAT = BUF_NUM_FORMAT_UNORM
>                             DATA_FORMAT = BUF_DATA_FORMAT_INVALID
>                             ELEMENT_SIZE = 0
>                             INDEX_STRIDE = 0
>                             ADD_TID_ENABLE = 0
>                             ATC = 0
>                             HASH_ENABLE = 0
>                             HEAP = 0
>                             MTYPE = 0
>                             TYPE = SQ_RSRC_BUF
>
>[1;32mVS - Shader buffer slot 4 (GPU list):[0m
>        [1;33mSQ_BUF_RSRC_WORD0[0m <- 0
>        [1;33mSQ_BUF_RSRC_WORD1[0m <- BASE_ADDRESS_HI = 0
>                             STRIDE = 0
>                             CACHE_SWIZZLE = 0
>                             SWIZZLE_ENABLE = 0
>        [1;33mSQ_BUF_RSRC_WORD2[0m <- 0
>        [1;33mSQ_BUF_RSRC_WORD3[0m <- DST_SEL_X = SQ_SEL_0
>                             DST_SEL_Y = SQ_SEL_0
>                             DST_SEL_Z = SQ_SEL_0
>                             DST_SEL_W = SQ_SEL_0
>                             NUM_FORMAT = BUF_NUM_FORMAT_UNORM
>                             DATA_FORMAT = BUF_DATA_FORMAT_INVALID
>                             ELEMENT_SIZE = 0
>                             INDEX_STRIDE = 0
>                             ADD_TID_ENABLE = 0
>                             ATC = 0
>                             HASH_ENABLE = 0
>                             HEAP = 0
>                             MTYPE = 0
>                             TYPE = SQ_RSRC_BUF
>
>[1;32mVS - Shader buffer slot 5 (GPU list):[0m
>        [1;33mSQ_BUF_RSRC_WORD0[0m <- 0
>        [1;33mSQ_BUF_RSRC_WORD1[0m <- BASE_ADDRESS_HI = 0
>                             STRIDE = 0
>                             CACHE_SWIZZLE = 0
>                             SWIZZLE_ENABLE = 0
>        [1;33mSQ_BUF_RSRC_WORD2[0m <- 0
>        [1;33mSQ_BUF_RSRC_WORD3[0m <- DST_SEL_X = SQ_SEL_0
>                             DST_SEL_Y = SQ_SEL_0
>                             DST_SEL_Z = SQ_SEL_0
>                             DST_SEL_W = SQ_SEL_0
>                             NUM_FORMAT = BUF_NUM_FORMAT_UNORM
>                             DATA_FORMAT = BUF_DATA_FORMAT_INVALID
>                             ELEMENT_SIZE = 0
>                             INDEX_STRIDE = 0
>                             ADD_TID_ENABLE = 0
>                             ATC = 0
>                             HASH_ENABLE = 0
>                             HEAP = 0
>                             MTYPE = 0
>                             TYPE = SQ_RSRC_BUF
>
>[1;32mVS - Shader buffer slot 6 (GPU list):[0m
>        [1;33mSQ_BUF_RSRC_WORD0[0m <- 0
>        [1;33mSQ_BUF_RSRC_WORD1[0m <- BASE_ADDRESS_HI = 0
>                             STRIDE = 0
>                             CACHE_SWIZZLE = 0
>                             SWIZZLE_ENABLE = 0
>        [1;33mSQ_BUF_RSRC_WORD2[0m <- 0
>        [1;33mSQ_BUF_RSRC_WORD3[0m <- DST_SEL_X = SQ_SEL_0
>                             DST_SEL_Y = SQ_SEL_0
>                             DST_SEL_Z = SQ_SEL_0
>                             DST_SEL_W = SQ_SEL_0
>                             NUM_FORMAT = BUF_NUM_FORMAT_UNORM
>                             DATA_FORMAT = BUF_DATA_FORMAT_INVALID
>                             ELEMENT_SIZE = 0
>                             INDEX_STRIDE = 0
>                             ADD_TID_ENABLE = 0
>                             ATC = 0
>                             HASH_ENABLE = 0
>                             HEAP = 0
>                             MTYPE = 0
>                             TYPE = SQ_RSRC_BUF
>
>[1;32mVS - Shader buffer slot 7 (GPU list):[0m
>        [1;33mSQ_BUF_RSRC_WORD0[0m <- 0
>        [1;33mSQ_BUF_RSRC_WORD1[0m <- BASE_ADDRESS_HI = 0
>                             STRIDE = 0
>                             CACHE_SWIZZLE = 0
>                             SWIZZLE_ENABLE = 0
>        [1;33mSQ_BUF_RSRC_WORD2[0m <- 0
>        [1;33mSQ_BUF_RSRC_WORD3[0m <- DST_SEL_X = SQ_SEL_0
>                             DST_SEL_Y = SQ_SEL_0
>                             DST_SEL_Z = SQ_SEL_0
>                             DST_SEL_W = SQ_SEL_0
>                             NUM_FORMAT = BUF_NUM_FORMAT_UNORM
>                             DATA_FORMAT = BUF_DATA_FORMAT_INVALID
>                             ELEMENT_SIZE = 0
>                             INDEX_STRIDE = 0
>                             ADD_TID_ENABLE = 0
>                             ATC = 0
>                             HASH_ENABLE = 0
>                             HEAP = 0
>                             MTYPE = 0
>                             TYPE = SQ_RSRC_BUF
>
>[1;32mVS - Shader buffer slot 8 (GPU list):[0m
>        [1;33mSQ_BUF_RSRC_WORD0[0m <- 0x1d600000
>        [1;33mSQ_BUF_RSRC_WORD1[0m <- BASE_ADDRESS_HI = 1
>                             STRIDE = 0
>                             CACHE_SWIZZLE = 0
>                             SWIZZLE_ENABLE = 0
>        [1;33mSQ_BUF_RSRC_WORD2[0m <- 0x00239400
>        [1;33mSQ_BUF_RSRC_WORD3[0m <- DST_SEL_X = SQ_SEL_X
>                             DST_SEL_Y = SQ_SEL_Y
>                             DST_SEL_Z = SQ_SEL_Z
>                             DST_SEL_W = SQ_SEL_W
>                             NUM_FORMAT = BUF_NUM_FORMAT_FLOAT
>                             DATA_FORMAT = BUF_DATA_FORMAT_32
>                             ELEMENT_SIZE = 0
>                             INDEX_STRIDE = 0
>                             ADD_TID_ENABLE = 0
>                             ATC = 0
>                             HASH_ENABLE = 0
>                             HEAP = 0
>                             MTYPE = 0
>                             TYPE = SQ_RSRC_BUF
>
>[1;32mPS - Constant buffer slot 0 (GPU list):[0m
>        [1;33mSQ_BUF_RSRC_WORD0[0m <- 0x00326f40
>        [1;33mSQ_BUF_RSRC_WORD1[0m <- BASE_ADDRESS_HI = 0
>                             STRIDE = 0
>                             CACHE_SWIZZLE = 0
>                             SWIZZLE_ENABLE = 0
>        [1;33mSQ_BUF_RSRC_WORD2[0m <- 16 (0x00000010)
>        [1;33mSQ_BUF_RSRC_WORD3[0m <- DST_SEL_X = SQ_SEL_X
>                             DST_SEL_Y = SQ_SEL_Y
>                             DST_SEL_Z = SQ_SEL_Z
>                             DST_SEL_W = SQ_SEL_W
>                             NUM_FORMAT = BUF_NUM_FORMAT_FLOAT
>                             DATA_FORMAT = BUF_DATA_FORMAT_32
>                             ELEMENT_SIZE = 0
>                             INDEX_STRIDE = 0
>                             ADD_TID_ENABLE = 0
>                             ATC = 0
>                             HASH_ENABLE = 0
>                             HEAP = 0
>                             MTYPE = 0
>                             TYPE = SQ_RSRC_BUF
>
>[1;32mPS - Constant buffer slot 1 (GPU list):[0m
>        [1;33mSQ_BUF_RSRC_WORD0[0m <- 0x09182000
>        [1;33mSQ_BUF_RSRC_WORD1[0m <- BASE_ADDRESS_HI = 1
>                             STRIDE = 0
>                             CACHE_SWIZZLE = 0
>                             SWIZZLE_ENABLE = 0
>        [1;33mSQ_BUF_RSRC_WORD2[0m <- 4016 (0x00000fb0)
>        [1;33mSQ_BUF_RSRC_WORD3[0m <- DST_SEL_X = SQ_SEL_X
>                             DST_SEL_Y = SQ_SEL_Y
>                             DST_SEL_Z = SQ_SEL_Z
>                             DST_SEL_W = SQ_SEL_W
>                             NUM_FORMAT = BUF_NUM_FORMAT_FLOAT
>                             DATA_FORMAT = BUF_DATA_FORMAT_32
>                             ELEMENT_SIZE = 0
>                             INDEX_STRIDE = 0
>                             ADD_TID_ENABLE = 0
>                             ATC = 0
>                             HASH_ENABLE = 0
>                             HEAP = 0
>                             MTYPE = 0
>                             TYPE = SQ_RSRC_BUF
>
>[1;32mPS - Shader buffer slot 0 (GPU list):[0m
>        [1;33mSQ_BUF_RSRC_WORD0[0m <- 0
>        [1;33mSQ_BUF_RSRC_WORD1[0m <- BASE_ADDRESS_HI = 0
>                             STRIDE = 0
>                             CACHE_SWIZZLE = 0
>                             SWIZZLE_ENABLE = 0
>        [1;33mSQ_BUF_RSRC_WORD2[0m <- 0
>        [1;33mSQ_BUF_RSRC_WORD3[0m <- DST_SEL_X = SQ_SEL_0
>                             DST_SEL_Y = SQ_SEL_0
>                             DST_SEL_Z = SQ_SEL_0
>                             DST_SEL_W = SQ_SEL_0
>                             NUM_FORMAT = BUF_NUM_FORMAT_UNORM
>                             DATA_FORMAT = BUF_DATA_FORMAT_INVALID
>                             ELEMENT_SIZE = 0
>                             INDEX_STRIDE = 0
>                             ADD_TID_ENABLE = 0
>                             ATC = 0
>                             HASH_ENABLE = 0
>                             HEAP = 0
>                             MTYPE = 0
>                             TYPE = SQ_RSRC_BUF
>
>[1;32mPS - Shader buffer slot 1 (GPU list):[0m
>        [1;33mSQ_BUF_RSRC_WORD0[0m <- 0
>        [1;33mSQ_BUF_RSRC_WORD1[0m <- BASE_ADDRESS_HI = 0
>                             STRIDE = 0
>                             CACHE_SWIZZLE = 0
>                             SWIZZLE_ENABLE = 0
>        [1;33mSQ_BUF_RSRC_WORD2[0m <- 0
>        [1;33mSQ_BUF_RSRC_WORD3[0m <- DST_SEL_X = SQ_SEL_0
>                             DST_SEL_Y = SQ_SEL_0
>                             DST_SEL_Z = SQ_SEL_0
>                             DST_SEL_W = SQ_SEL_0
>                             NUM_FORMAT = BUF_NUM_FORMAT_UNORM
>                             DATA_FORMAT = BUF_DATA_FORMAT_INVALID
>                             ELEMENT_SIZE = 0
>                             INDEX_STRIDE = 0
>                             ADD_TID_ENABLE = 0
>                             ATC = 0
>                             HASH_ENABLE = 0
>                             HEAP = 0
>                             MTYPE = 0
>                             TYPE = SQ_RSRC_BUF
>
>[1;32mPS - Shader buffer slot 2 (GPU list):[0m
>        [1;33mSQ_BUF_RSRC_WORD0[0m <- 0
>        [1;33mSQ_BUF_RSRC_WORD1[0m <- BASE_ADDRESS_HI = 0
>                             STRIDE = 0
>                             CACHE_SWIZZLE = 0
>                             SWIZZLE_ENABLE = 0
>        [1;33mSQ_BUF_RSRC_WORD2[0m <- 0
>        [1;33mSQ_BUF_RSRC_WORD3[0m <- DST_SEL_X = SQ_SEL_0
>                             DST_SEL_Y = SQ_SEL_0
>                             DST_SEL_Z = SQ_SEL_0
>                             DST_SEL_W = SQ_SEL_0
>                             NUM_FORMAT = BUF_NUM_FORMAT_UNORM
>                             DATA_FORMAT = BUF_DATA_FORMAT_INVALID
>                             ELEMENT_SIZE = 0
>                             INDEX_STRIDE = 0
>                             ADD_TID_ENABLE = 0
>                             ATC = 0
>                             HASH_ENABLE = 0
>                             HEAP = 0
>                             MTYPE = 0
>                             TYPE = SQ_RSRC_BUF
>
>[1;32mPS - Shader buffer slot 3 (GPU list):[0m
>        [1;33mSQ_BUF_RSRC_WORD0[0m <- 0
>        [1;33mSQ_BUF_RSRC_WORD1[0m <- BASE_ADDRESS_HI = 0
>                             STRIDE = 0
>                             CACHE_SWIZZLE = 0
>                             SWIZZLE_ENABLE = 0
>        [1;33mSQ_BUF_RSRC_WORD2[0m <- 0
>        [1;33mSQ_BUF_RSRC_WORD3[0m <- DST_SEL_X = SQ_SEL_0
>                             DST_SEL_Y = SQ_SEL_0
>                             DST_SEL_Z = SQ_SEL_0
>                             DST_SEL_W = SQ_SEL_0
>                             NUM_FORMAT = BUF_NUM_FORMAT_UNORM
>                             DATA_FORMAT = BUF_DATA_FORMAT_INVALID
>                             ELEMENT_SIZE = 0
>                             INDEX_STRIDE = 0
>                             ADD_TID_ENABLE = 0
>                             ATC = 0
>                             HASH_ENABLE = 0
>                             HEAP = 0
>                             MTYPE = 0
>                             TYPE = SQ_RSRC_BUF
>
>[1;32mPS - Shader buffer slot 4 (GPU list):[0m
>        [1;33mSQ_BUF_RSRC_WORD0[0m <- 0
>        [1;33mSQ_BUF_RSRC_WORD1[0m <- BASE_ADDRESS_HI = 0
>                             STRIDE = 0
>                             CACHE_SWIZZLE = 0
>                             SWIZZLE_ENABLE = 0
>        [1;33mSQ_BUF_RSRC_WORD2[0m <- 0
>        [1;33mSQ_BUF_RSRC_WORD3[0m <- DST_SEL_X = SQ_SEL_0
>                             DST_SEL_Y = SQ_SEL_0
>                             DST_SEL_Z = SQ_SEL_0
>                             DST_SEL_W = SQ_SEL_0
>                             NUM_FORMAT = BUF_NUM_FORMAT_UNORM
>                             DATA_FORMAT = BUF_DATA_FORMAT_INVALID
>                             ELEMENT_SIZE = 0
>                             INDEX_STRIDE = 0
>                             ADD_TID_ENABLE = 0
>                             ATC = 0
>                             HASH_ENABLE = 0
>                             HEAP = 0
>                             MTYPE = 0
>                             TYPE = SQ_RSRC_BUF
>
>[1;32mPS - Shader buffer slot 5 (GPU list):[0m
>        [1;33mSQ_BUF_RSRC_WORD0[0m <- 0
>        [1;33mSQ_BUF_RSRC_WORD1[0m <- BASE_ADDRESS_HI = 0
>                             STRIDE = 0
>                             CACHE_SWIZZLE = 0
>                             SWIZZLE_ENABLE = 0
>        [1;33mSQ_BUF_RSRC_WORD2[0m <- 0
>        [1;33mSQ_BUF_RSRC_WORD3[0m <- DST_SEL_X = SQ_SEL_0
>                             DST_SEL_Y = SQ_SEL_0
>                             DST_SEL_Z = SQ_SEL_0
>                             DST_SEL_W = SQ_SEL_0
>                             NUM_FORMAT = BUF_NUM_FORMAT_UNORM
>                             DATA_FORMAT = BUF_DATA_FORMAT_INVALID
>                             ELEMENT_SIZE = 0
>                             INDEX_STRIDE = 0
>                             ADD_TID_ENABLE = 0
>                             ATC = 0
>                             HASH_ENABLE = 0
>                             HEAP = 0
>                             MTYPE = 0
>                             TYPE = SQ_RSRC_BUF
>
>[1;32mPS - Shader buffer slot 6 (GPU list):[0m
>        [1;33mSQ_BUF_RSRC_WORD0[0m <- 0
>        [1;33mSQ_BUF_RSRC_WORD1[0m <- BASE_ADDRESS_HI = 0
>                             STRIDE = 0
>                             CACHE_SWIZZLE = 0
>                             SWIZZLE_ENABLE = 0
>        [1;33mSQ_BUF_RSRC_WORD2[0m <- 0
>        [1;33mSQ_BUF_RSRC_WORD3[0m <- DST_SEL_X = SQ_SEL_0
>                             DST_SEL_Y = SQ_SEL_0
>                             DST_SEL_Z = SQ_SEL_0
>                             DST_SEL_W = SQ_SEL_0
>                             NUM_FORMAT = BUF_NUM_FORMAT_UNORM
>                             DATA_FORMAT = BUF_DATA_FORMAT_INVALID
>                             ELEMENT_SIZE = 0
>

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Attachments on bug 108814: 142535 | 142536 | 142537 | 142538 | 142598

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