Attachment 143949 Details for Bug 110412 – output from Mesa Git

output from Mesa Git

fs_mesa_git.txt (text/plain), 824.10 KB, created by Kevin Rogovin on 2019-04-12 11:23:41 UTC

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Creator: Kevin Rogovin

Created: 2019-04-12 11:23:41 UTC

Size: 824.10 KB

patch

obsolete

>ATTENTION: default value of option vblank_mode overridden by environment.
>GLSL IR for native fragment shader 0:
>(
>(declare (location=1 shader_in ) vec4 gl_Color)
>(declare (location=2 shader_out ) vec4 gl_FragColor)
>( function main
>  (signature void
>    (parameters
>    )
>    (
>      (assign  (xyzw) (var_ref gl_FragColor)  (var_ref gl_Color) ) 
>    ))
>
>)
>
>)
>
>
>NIR (SSA form) for fragment shader:
>shader: MESA_SHADER_FRAGMENT
>name: GLSL0
>inputs: 0
>outputs: 0
>uniforms: 0
>shared: 0
>decl_var shader_in INTERP_MODE_SMOOTH vec4 gl_Color (VARYING_SLOT_COL0, 1, 0)
>decl_var shader_out INTERP_MODE_NONE vec4 gl_FragColor (FRAG_RESULT_COLOR, 4, 0)
>decl_function main (0 params)
>
>impl main {
>	block block_0:
>	/* preds: */
>	vec2 32 ssa_0 = intrinsic load_barycentric_pixel () (1) /* interp_mode=1 */
>	vec1 32 ssa_1 = load_const (0x00000000 /* 0.000000 */)
>	vec4 32 ssa_2 = intrinsic load_interpolated_input (ssa_0, ssa_1) (1, 0) /* base=1 */ /* component=0 */	/* gl_Color */
>	intrinsic store_output (ssa_2, ssa_1) (4, 15, 0) /* base=4 */ /* wrmask=xyzw */ /* component=0 */	/* gl_FragColor */
>	/* succs: block_1 */
>	block block_1:
>}
>
>NIR (final form) for fragment shader:
>shader: MESA_SHADER_FRAGMENT
>name: GLSL0
>inputs: 0
>outputs: 0
>uniforms: 0
>shared: 0
>decl_var shader_in INTERP_MODE_SMOOTH vec4 gl_Color (VARYING_SLOT_COL0, 1, 0)
>decl_var shader_out INTERP_MODE_NONE vec4 gl_FragColor (FRAG_RESULT_COLOR, 4, 0)
>decl_function main (0 params)
>
>impl main {
>	block block_0:
>	/* preds: */
>	vec2 32 ssa_0 = intrinsic load_barycentric_pixel () (1) /* interp_mode=1 */
>	vec1 32 ssa_1 = load_const (0x00000000 /* 0.000000 */)
>	vec4 32 ssa_2 = intrinsic load_interpolated_input (ssa_0, ssa_1) (1, 0) /* base=1 */ /* component=0 */	/* gl_Color */
>	intrinsic store_output (ssa_2, ssa_1) (4, 15, 0) /* base=4 */ /* wrmask=xyzw */ /* component=0 */	/* gl_FragColor */
>	/* succs: block_1 */
>	block block_1:
>}
>
>Native code for unnamed fragment shader GLSL0
>SIMD8 shader: 5 instructions. 0 loops. 24 cycles. 0:0 spills:fills. Promoted 0 constants. Compacted 80 to 48 bytes (40%)
>   START B0 (24 cycles)
>pln(8)          g124<1>F        g4<0,1,0>F      g2<8,8,1>F      { align1 1Q compacted };
>pln(8)          g125<1>F        g4.4<0,1,0>F    g2<8,8,1>F      { align1 1Q compacted };
>pln(8)          g126<1>F        g5<0,1,0>F      g2<8,8,1>F      { align1 1Q compacted };
>pln(8)          g127<1>F        g5.4<0,1,0>F    g2<8,8,1>F      { align1 1Q compacted };
>sendc(8)        null<1>UW       g124<0,1,0>F    0x88031400
>                            render MsgDesc: RT write SIMD8 LastRT Surface = 0 mlen 4 rlen 0 { align1 1Q EOT };
>   END B0
>
>Native code for unnamed fragment shader GLSL0
>SIMD16 shader: 5 instructions. 0 loops. 34 cycles. 0:0 spills:fills. Promoted 0 constants. Compacted 80 to 48 bytes (40%)
>   START B0 (34 cycles)
>pln(16)         g120<1>F        g6<0,1,0>F      g2<8,8,1>F      { align1 1H compacted };
>pln(16)         g122<1>F        g6.4<0,1,0>F    g2<8,8,1>F      { align1 1H compacted };
>pln(16)         g124<1>F        g7<0,1,0>F      g2<8,8,1>F      { align1 1H compacted };
>pln(16)         g126<1>F        g7.4<0,1,0>F    g2<8,8,1>F      { align1 1H compacted };
>sendc(16)       null<1>UW       g120<0,1,0>F    0x90031000
>                            render MsgDesc: RT write SIMD16 LastRT Surface = 0 mlen 8 rlen 0 { align1 1H EOT };
>   END B0
>
>NIR (SSA form) for fragment shader:
>shader: MESA_SHADER_FRAGMENT
>name: BLORP-clear
>inputs: 0
>outputs: 0
>uniforms: 0
>shared: 0
>decl_var shader_in INTERP_MODE_FLAT vec4 clear_color (VARYING_SLOT_VAR0, 31, 0)
>decl_var shader_out INTERP_MODE_NONE vec4 gl_FragColor (FRAG_RESULT_COLOR, 4, 0)
>decl_function main (0 params)
>
>impl main {
>	block block_0:
>	/* preds: */
>	vec1 32 ssa_0 = load_const (0x00000000 /* 0.000000 */)
>	vec4 32 ssa_1 = intrinsic load_input (ssa_0) (31, 0) /* base=31 */ /* component=0 */	/* clear_color */
>	intrinsic store_output (ssa_1, ssa_0) (4, 15, 0) /* base=4 */ /* wrmask=xyzw */ /* component=0 */	/* gl_FragColor */
>	/* succs: block_1 */
>	block block_1:
>}
>
>NIR (final form) for fragment shader:
>shader: MESA_SHADER_FRAGMENT
>name: BLORP-clear
>inputs: 0
>outputs: 0
>uniforms: 0
>shared: 0
>decl_var shader_in INTERP_MODE_FLAT vec4 clear_color (VARYING_SLOT_VAR0, 31, 0)
>decl_var shader_out INTERP_MODE_NONE vec4 gl_FragColor (FRAG_RESULT_COLOR, 4, 0)
>decl_function main (0 params)
>
>impl main {
>	block block_0:
>	/* preds: */
>	vec1 32 ssa_0 = load_const (0x00000000 /* 0.000000 */)
>	vec4 32 ssa_1 = intrinsic load_input (ssa_0) (31, 0) /* base=31 */ /* component=0 */	/* clear_color */
>	intrinsic store_output (ssa_1, ssa_0) (4, 15, 0) /* base=4 */ /* wrmask=xyzw */ /* component=0 */	/* gl_FragColor */
>	/* succs: block_1 */
>	block block_1:
>}
>
>Native code for unnamed fragment shader BLORP-clear
>SIMD16 shader: 2 instructions. 0 loops. 0 cycles. 0:0 spills:fills. Promoted 0 constants. Compacted 32 to 32 bytes (0%)
>   START B0 (0 cycles)
>mov(4)          g114<1>F        g2.3<8,2,4>F                    { align1 WE_all 1N };
>sendc(16)       null<1>UW       g114<0,1,0>F    0x82031100
>                            render MsgDesc: RT write SIMD16/RepData LastRT Surface = 0 mlen 1 rlen 0 { align1 1H EOT };
>   END B0
>
>GLSL IR for native fragment shader 1:
>(
>(declare (location=0 shader_in ) vec4 gl_FragCoord)
>(declare (location=31 shader_in flat) uvec4 fastuidraw_uint_varying0)
>(declare (location=32 shader_in flat) uvec4 fastuidraw_uint_varying1)
>(declare (location=33 shader_in flat) uvec4 fastuidraw_uint_varying2)
>(declare (location=34 shader_in ) vec4 fastuidraw_float_smooth_varying0)
>(declare (location=35 shader_in ) vec4 fastuidraw_float_smooth_varying1)
>(declare (location=36 shader_in ) float fastuidraw_float_smooth_varying2)
>(declare (location=37 shader_in flat) vec4 fastuidraw_float_flat_varying0)
>(declare (location=38 shader_in flat) vec4 fastuidraw_float_flat_varying1)
>(declare (location=39 shader_in flat) vec4 fastuidraw_float_flat_varying2)
>(declare (location=40 shader_in flat) vec4 fastuidraw_float_flat_varying3)
>(declare (location=41 shader_in flat) vec4 fastuidraw_float_flat_varying4)
>(declare (location=42 shader_in flat) vec3 fastuidraw_float_flat_varying5)
>(declare (location=0 readonly restrict shader_storage ) (array uvec4 0) fastuidraw_painterStore)
>(declare (binding=1 location=0 readonly restrict shader_storage ) (array uint 0) fastuidraw_glyphDataStore_data)
>(declare (location=0 uniform ) (array vec4 2) fastuidraw_uniforms)
>(declare (location=3 uniform ) sampler1DArray fastuidraw_colorStopAtlas)
>(declare (binding=2 location=4 uniform ) sampler2DArray fastuidraw_imageAtlasLinear)
>(declare (binding=1 location=5 uniform ) sampler2DArray fastuidraw_imageAtlasNearest)
>(declare (binding=3 location=6 uniform ) usampler2DArray fastuidraw_imageIndexAtlas)
>(declare (binding=5 location=7 uniform ) (array sampler2D 8) fastuidraw_external_texture)
>(declare () ivec2 fastuidraw_deferred_buffer_offset)
>(declare (binding=4 location=8 uniform ) sampler2D fastuidraw_deferred_coverage_buffer)
>(declare (location=4 shader_out ) vec4 fastuidraw_final_color0)
>(declare (location=4 shader_out ) vec4 fastuidraw_final_color1)
>( function main
>  (signature void
>    (parameters
>    )
>    (
>      (declare () uvec2 tmp)
>      (declare () vec4 v)
>      (assign  (xyzw) (var_ref v)  (constant vec4 (0.000000 0.000000 0.000000 0.000000)) ) 
>      (assign  (x) (var_ref tmp)  (expression uint >> (expression uint << (swiz w (var_ref fastuidraw_uint_varying2) )(constant uint (16)) ) (constant uint (16)) ) ) 
>      (assign  (y) (var_ref tmp)  (expression uint >> (swiz w (var_ref fastuidraw_uint_varying2) )(constant uint (16)) ) ) 
>      (assign  (xy) (var_ref fastuidraw_deferred_buffer_offset)  (expression ivec2 + (expression ivec2 u2i (var_ref tmp) ) (constant ivec2 (-32768 -32768)) ) ) 
>      (if (expression bool != (swiz x (var_ref fastuidraw_uint_varying2) )(constant uint (4294967295)) ) (
>        (declare () vec4 b)
>        (if (expression bool != (expression uint & (swiz y (var_ref fastuidraw_uint_varying2) )(constant uint (2147483648)) ) (constant uint (0)) ) (
>          (declare () vec4 return_value)
>          (declare () vec2 dpdy)
>          (declare () vec2 dpdx)
>          (declare () vec2 p)
>          (declare (temporary ) vec4 compiler_temp)
>          (assign  (x) (var_ref compiler_temp)  (swiz w (var_ref fastuidraw_float_flat_varying4) )) 
>          (assign  (y) (var_ref compiler_temp)  (swiz x (var_ref fastuidraw_float_flat_varying5) )) 
>          (assign  (z) (var_ref compiler_temp)  (swiz y (var_ref fastuidraw_float_flat_varying5) )) 
>          (assign  (w) (var_ref compiler_temp)  (swiz z (var_ref fastuidraw_float_flat_varying5) )) 
>          (assign  (xyzw) (var_ref return_value)  (var_ref compiler_temp) ) 
>          (declare (temporary ) vec2 compiler_temp@2)
>          (assign  (x) (var_ref compiler_temp@2)  (swiz w (var_ref fastuidraw_float_smooth_varying1) )) 
>          (assign  (y) (var_ref compiler_temp@2)  (var_ref fastuidraw_float_smooth_varying2) ) 
>          (assign  (xy) (var_ref p)  (var_ref compiler_temp@2) ) 
>          (assign  (xy) (var_ref dpdx)  (expression vec2 dFdx (var_ref compiler_temp@2) ) ) 
>          (assign  (xy) (var_ref dpdy)  (expression vec2 dFdy (var_ref compiler_temp@2) ) ) 
>          (if (expression bool != (expression uint & (swiz y (var_ref fastuidraw_uint_varying2) )(constant uint (8192)) ) (constant uint (0)) ) (
>            (declare () uint y_spread)
>            (declare (temporary ) uint compiler_temp@3)
>            (assign  (x) (var_ref compiler_temp@3)  (expression uint >> (expression uint << (swiz y (var_ref fastuidraw_uint_varying2) )(constant uint (16)) ) (constant uint (30)) ) ) 
>            (assign  (x) (var_ref y_spread)  (expression uint >> (expression uint << (swiz y (var_ref fastuidraw_uint_varying2) )(constant uint (14)) ) (constant uint (30)) ) ) 
>            (assign  (xy) (var_ref p)  (expression vec2 + (var_ref compiler_temp@2) (expression vec2 neg (swiz xy (var_ref fastuidraw_float_flat_varying0) )) ) ) 
>            (declare (temporary ) float compiler_temp@4)
>            (assign  (x) (var_ref compiler_temp@4)  (swiz x (var_ref p) )) 
>            (if (expression bool == (var_ref compiler_temp@3) (constant uint (1)) ) (
>              (assign  (x) (var_ref compiler_temp@4)  (expression float min (expression float max (expression float abs (swiz x (var_ref p) )) (constant float (0.000000)) ) (swiz z (var_ref fastuidraw_float_flat_varying0) )) ) 
>            )
>            (
>              (if (expression bool == (var_ref compiler_temp@3) (constant uint (2)) ) (
>                (assign  (x) (var_ref compiler_temp@4)  (expression float % (swiz x (var_ref p) )(swiz z (var_ref fastuidraw_float_flat_varying0) )) ) 
>              )
>              (
>                (if (expression bool == (var_ref compiler_temp@3) (constant uint (3)) ) (
>                  (assign  (x) (var_ref compiler_temp@4)  (expression float + (swiz z (var_ref fastuidraw_float_flat_varying0) )(expression float neg (expression float abs (expression float + (expression float % (swiz x (var_ref p) )(expression float * (constant float (2.000000)) (swiz z (var_ref fastuidraw_float_flat_varying0) )) ) (expression float neg (swiz z (var_ref fastuidraw_float_flat_varying0) )) ) ) ) ) ) 
>                )
>                (
>                  (assign  (x) (var_ref compiler_temp@4)  (expression float min (expression float max (swiz x (var_ref p) )(constant float (0.000000)) ) (swiz z (var_ref fastuidraw_float_flat_varying0) )) ) 
>                ))
>
>              ))
>
>            ))
>
>            (assign  (x) (var_ref p)  (var_ref compiler_temp@4) ) 
>            (declare (temporary ) float compiler_temp@5)
>            (assign  (x) (var_ref compiler_temp@5)  (swiz y (var_ref p) )) 
>            (if (expression bool == (var_ref y_spread) (constant uint (1)) ) (
>              (assign  (x) (var_ref compiler_temp@5)  (expression float min (expression float max (expression float abs (swiz y (var_ref p) )) (constant float (0.000000)) ) (swiz w (var_ref fastuidraw_float_flat_varying0) )) ) 
>            )
>            (
>              (if (expression bool == (var_ref y_spread) (constant uint (2)) ) (
>                (assign  (x) (var_ref compiler_temp@5)  (expression float % (swiz y (var_ref p) )(swiz w (var_ref fastuidraw_float_flat_varying0) )) ) 
>              )
>              (
>                (if (expression bool == (var_ref y_spread) (constant uint (3)) ) (
>                  (assign  (x) (var_ref compiler_temp@5)  (expression float + (swiz w (var_ref fastuidraw_float_flat_varying0) )(expression float neg (expression float abs (expression float + (expression float % (swiz y (var_ref p) )(expression float * (constant float (2.000000)) (swiz w (var_ref fastuidraw_float_flat_varying0) )) ) (expression float neg (swiz w (var_ref fastuidraw_float_flat_varying0) )) ) ) ) ) ) 
>                )
>                (
>                  (assign  (x) (var_ref compiler_temp@5)  (expression float min (expression float max (swiz y (var_ref p) )(constant float (0.000000)) ) (swiz w (var_ref fastuidraw_float_flat_varying0) )) ) 
>                ))
>
>              ))
>
>            ))
>
>            (assign  (y) (var_ref p)  (var_ref compiler_temp@5) ) 
>            (assign  (xy) (var_ref p)  (expression vec2 + (var_ref p) (swiz xy (var_ref fastuidraw_float_flat_varying0) )) ) 
>          )
>          ())
>
>          (declare (temporary ) uint compiler_temp@6)
>          (assign  (x) (var_ref compiler_temp@6)  (expression uint >> (expression uint << (swiz y (var_ref fastuidraw_uint_varying2) )(constant uint (21)) ) (constant uint (30)) ) ) 
>          (if (expression bool != (var_ref compiler_temp@6) (constant uint (0)) ) (
>            (declare () float t)
>            (declare (temporary ) float compiler_temp@7)
>            (declare () float t@8)
>            (assign  (x) (var_ref t@8)  (constant float (1.000000)) ) 
>            (if (expression bool == (var_ref compiler_temp@6) (constant uint (2)) ) (
>              (declare (temporary ) float good)
>              (declare () float recip_two_a)
>              (declare () float t1)
>              (declare () float t0)
>              (declare () float desc)
>              (declare () float b@9)
>              (declare () float a)
>              (declare () float delta_r)
>              (declare () float t@10)
>              (declare () vec2 delta_p)
>              (declare () vec2 q)
>              (assign  (xy) (var_ref q)  (expression vec2 + (var_ref p) (expression vec2 neg (swiz xy (var_ref fastuidraw_float_flat_varying1) )) ) ) 
>              (assign  (xy) (var_ref delta_p)  (expression vec2 + (swiz zw (var_ref fastuidraw_float_flat_varying1) )(expression vec2 neg (swiz xy (var_ref fastuidraw_float_flat_varying1) )) ) ) 
>              (assign  (x) (var_ref delta_r)  (expression float + (swiz y (var_ref fastuidraw_float_flat_varying2) )(expression float neg (swiz x (var_ref fastuidraw_float_flat_varying2) )) ) ) 
>              (assign  (x) (var_ref b@9)  (expression float * (constant float (2.000000)) (expression float + (expression float dot (var_ref q) (var_ref delta_p) ) (expression float neg (expression float * (swiz x (var_ref fastuidraw_float_flat_varying2) )(var_ref delta_r) ) ) ) ) ) 
>              (assign  (x) (var_ref a)  (expression float + (expression float dot (var_ref delta_p) (var_ref delta_p) ) (expression float neg (expression float * (var_ref delta_r) (var_ref delta_r) ) ) ) ) 
>              (assign  (x) (var_ref desc)  (expression float + (expression float * (var_ref b@9) (var_ref b@9) ) (expression float neg (expression float * (expression float * (constant float (4.000000)) (var_ref a) ) (expression float + (expression float dot (var_ref q) (var_ref q) ) (expression float neg (expression float * (swiz x (var_ref fastuidraw_float_flat_varying2) )(swiz x (var_ref fastuidraw_float_flat_varying2) )) ) ) ) ) ) ) 
>              (if (expression bool < (var_ref desc) (constant float (0.000000)) ) (
>                (assign  (x) (var_ref good)  (constant float (0.000000)) ) 
>                (assign  (x) (var_ref t@10)  (constant float (0.000000)) ) 
>              )
>              (
>                (declare () vec2 G)
>                (assign  (x) (var_ref good)  (constant float (1.000000)) ) 
>                (declare (temporary ) float compiler_temp@11)
>                (assign  (x) (var_ref compiler_temp@11)  (expression float sqrt (expression float abs (var_ref desc) ) ) ) 
>                (assign  (x) (var_ref desc)  (var_ref compiler_temp@11) ) 
>                (assign  (x) (var_ref recip_two_a)  (expression float * (constant float (0.500000)) (expression float rcp (var_ref a) ) ) ) 
>                (assign  (x) (var_ref t0)  (expression float * (expression float + (expression float neg (var_ref b@9) ) (var_ref compiler_temp@11) ) (var_ref recip_two_a) ) ) 
>                (assign  (x) (var_ref t1)  (expression float * (expression float + (expression float neg (var_ref b@9) ) (expression float neg (var_ref compiler_temp@11) ) ) (var_ref recip_two_a) ) ) 
>                (declare (temporary ) vec2 compiler_temp@12)
>                (assign  (x) (var_ref compiler_temp@12)  (expression float b2f (expression bool >= (var_ref t0) (constant float (0.000000)) ) ) ) 
>                (assign  (y) (var_ref compiler_temp@12)  (expression float b2f (expression bool >= (var_ref t1) (constant float (0.000000)) ) ) ) 
>                (declare (temporary ) vec2 compiler_temp@13)
>                (assign  (x) (var_ref compiler_temp@13)  (expression float b2f (expression bool >= (constant float (1.000000)) (var_ref t0) ) ) ) 
>                (assign  (y) (var_ref compiler_temp@13)  (expression float b2f (expression bool >= (constant float (1.000000)) (var_ref t1) ) ) ) 
>                (assign  (xy) (var_ref G)  (expression vec2 * (var_ref compiler_temp@12) (var_ref compiler_temp@13) ) ) 
>                (if (expression bool == (swiz x (var_ref G) )(swiz y (var_ref G) )) (
>                  (assign  (x) (var_ref t@10)  (expression float max (var_ref t0) (var_ref t1) ) ) 
>                )
>                (
>                  (declare (temporary ) vec2 compiler_temp@14)
>                  (assign  (x) (var_ref compiler_temp@14)  (var_ref t0) ) 
>                  (assign  (y) (var_ref compiler_temp@14)  (var_ref t1) ) 
>                  (assign  (x) (var_ref t@10)  (expression float dot (var_ref G) (var_ref compiler_temp@14) ) ) 
>                ))
>
>              ))
>
>              (assign  (x) (var_ref compiler_temp@7)  (var_ref good) ) 
>              (assign  (x) (var_ref t@8)  (var_ref t@10) ) 
>            )
>            (
>              (if (expression bool == (var_ref compiler_temp@6) (constant uint (1)) ) (
>                (assign  (x) (var_ref compiler_temp@7)  (constant float (1.000000)) ) 
>                (declare () vec2 v@15)
>                (assign  (xy) (var_ref v@15)  (expression vec2 + (swiz zw (var_ref fastuidraw_float_flat_varying1) )(expression vec2 neg (swiz xy (var_ref fastuidraw_float_flat_varying1) )) ) ) 
>                (assign  (x) (var_ref t@8)  (expression float * (expression float dot (var_ref v@15) (expression vec2 + (var_ref p) (expression vec2 neg (swiz xy (var_ref fastuidraw_float_flat_varying1) )) ) ) (expression float rcp (expression float dot (var_ref v@15) (var_ref v@15) ) ) ) ) 
>              )
>              (
>                (if (expression bool == (var_ref compiler_temp@6) (constant uint (3)) ) (
>                  (assign  (x) (var_ref compiler_temp@7)  (constant float (1.000000)) ) 
>                  (declare () float angle)
>                  (declare () float t@16)
>                  (declare () vec2 d)
>                  (assign  (xy) (var_ref d)  (expression vec2 + (var_ref p) (expression vec2 neg (swiz xy (var_ref fastuidraw_float_flat_varying1) )) ) ) 
>                  (declare (temporary ) float compiler_temp@17)
>                  (declare (temporary ) bool compiler_temp@18)
>                  (assign  (x) (var_ref compiler_temp@18)  (expression bool >= (constant float (0.000000)) (swiz x (var_ref d) )) ) 
>                  (declare (temporary ) float compiler_temp@19)
>                  (assign  (x) (var_ref compiler_temp@19)  (expression float csel (var_ref compiler_temp@18) (expression float abs (swiz x (var_ref d) )) (swiz y (var_ref d) )) ) 
>                  (declare (temporary ) float compiler_temp@20)
>                  (assign  (x) (var_ref compiler_temp@20)  (expression float csel (var_ref compiler_temp@18) (swiz y (var_ref d) )(expression float abs (swiz x (var_ref d) )) ) ) 
>                  (declare (temporary ) float compiler_temp@21)
>                  (assign  (x) (var_ref compiler_temp@21)  (expression float csel (expression bool >= (expression float abs (var_ref compiler_temp@20) ) (constant float (1.000000e+18)) ) (constant float (0.250000)) (constant float (1.000000)) ) ) 
>                  (declare (temporary ) float compiler_temp@22)
>                  (assign  (x) (var_ref compiler_temp@22)  (expression float rcp (expression float * (var_ref compiler_temp@20) (var_ref compiler_temp@21) ) ) ) 
>                  (declare (temporary ) float compiler_temp@23)
>                  (declare (temporary ) float compiler_temp@24)
>                  (assign  (x) (var_ref compiler_temp@24)  (expression float * (expression float min (expression float abs (expression float csel (expression bool == (expression float abs (swiz x (var_ref d) )) (expression float abs (swiz y (var_ref d) )) ) (constant float (1.000000)) (expression float abs (expression float * (expression float * (var_ref compiler_temp@19) (var_ref compiler_temp@21) ) (var_ref compiler_temp@22) ) ) ) ) (constant float (1.000000)) ) (expression float rcp (expression float max (expression float abs (expression float csel (expression bool == (expression float abs (swiz x (var_ref d) )) (expression float abs (swiz y (var_ref d) )) ) (constant float (1.000000)) (expression float abs (expression float * (expression float * (var_ref compiler_temp@19) (var_ref compiler_temp@21) ) (var_ref compiler_temp@22) ) ) ) ) (constant float (1.000000)) ) ) ) ) 
>                  (declare (temporary ) float compiler_temp@25)
>                  (assign  (x) (var_ref compiler_temp@25)  (expression float * (var_ref compiler_temp@24) (var_ref compiler_temp@24) ) ) 
>                  (assign  (x) (var_ref compiler_temp@25)  (expression float * (expression float + (expression float * (expression float + (expression float * (expression float + (expression float * (expression float + (expression float * (expression float + (expression float * (constant float (-0.012132)) (var_ref compiler_temp@25) ) (constant float (0.053681)) ) (var_ref compiler_temp@25) ) (constant float (-0.117350)) ) (var_ref compiler_temp@25) ) (constant float (0.193892)) ) (var_ref compiler_temp@25) ) (constant float (-0.332676)) ) (var_ref compiler_temp@25) ) (constant float (0.999979)) ) (var_ref compiler_temp@24) ) ) 
>                  (assign  (x) (var_ref compiler_temp@25)  (expression float + (var_ref compiler_temp@25) (expression float * (expression float b2f (expression bool < (constant float (1.000000)) (expression float abs (expression float csel (expression bool == (expression float abs (swiz x (var_ref d) )) (expression float abs (swiz y (var_ref d) )) ) (constant float (1.000000)) (expression float abs (expression float * (expression float * (var_ref compiler_temp@19) (var_ref compiler_temp@21) ) (var_ref compiler_temp@22) ) ) ) ) ) ) (expression float + (expression float * (var_ref compiler_temp@25) (constant float (-2.000000)) ) (constant float (1.570796)) ) ) ) ) 
>                  (assign  (x) (var_ref compiler_temp@23)  (expression float * (var_ref compiler_temp@25) (expression float sign (expression float csel (expression bool == (expression float abs (swiz x (var_ref d) )) (expression float abs (swiz y (var_ref d) )) ) (constant float (1.000000)) (expression float abs (expression float * (expression float * (var_ref compiler_temp@19) (var_ref compiler_temp@21) ) (var_ref compiler_temp@22) ) ) ) ) ) ) 
>                  (assign  (x) (var_ref compiler_temp@23)  (expression float + (var_ref compiler_temp@23) (expression float * (expression float b2f (var_ref compiler_temp@18) ) (constant float (1.570796)) ) ) ) 
>                  (assign  (x) (var_ref compiler_temp@17)  (expression float csel (expression bool < (expression float min (swiz y (var_ref d) )(var_ref compiler_temp@22) ) (constant float (0.000000)) ) (expression float neg (var_ref compiler_temp@23) ) (var_ref compiler_temp@23) ) ) 
>                  (assign  (x) (var_ref angle)  (var_ref compiler_temp@17) ) 
>                  (if (expression bool < (var_ref compiler_temp@17) (swiz z (var_ref fastuidraw_float_flat_varying1) )) (
>                    (assign  (x) (var_ref angle)  (expression float + (var_ref compiler_temp@17) (constant float (6.283185)) ) ) 
>                  )
>                  ())
>
>                  (assign  (x) (var_ref t@16)  (expression float * (expression float + (var_ref angle) (expression float neg (swiz z (var_ref fastuidraw_float_flat_varying1) )) ) (constant float (0.159155)) ) ) 
>                  (if (expression bool < (swiz w (var_ref fastuidraw_float_flat_varying1) )(constant float (0.000000)) ) (
>                    (assign  (x) (var_ref t@16)  (expression float + (constant float (1.000000)) (expression float neg (var_ref t@16) ) ) ) 
>                  )
>                  ())
>
>                  (assign  (x) (var_ref t@16)  (expression float * (var_ref t@16) (expression float abs (swiz w (var_ref fastuidraw_float_flat_varying1) )) ) ) 
>                  (assign  (x) (var_ref t@8)  (var_ref t@16) ) 
>                )
>                ())
>
>              ))
>
>            ))
>
>            (assign  (x) (var_ref t)  (var_ref t@8) ) 
>            (declare (temporary ) uint compiler_temp@26)
>            (assign  (x) (var_ref compiler_temp@26)  (expression uint >> (expression uint << (swiz y (var_ref fastuidraw_uint_varying2) )(constant uint (19)) ) (constant uint (30)) ) ) 
>            (if (expression bool == (var_ref compiler_temp@26) (constant uint (1)) ) (
>              (assign  (x) (var_ref t)  (expression float sat (expression float abs (var_ref t@8) ) ) ) 
>            )
>            (
>              (if (expression bool == (var_ref compiler_temp@26) (constant uint (2)) ) (
>                (assign  (x) (var_ref t)  (expression float fract (var_ref t@8) ) ) 
>              )
>              (
>                (if (expression bool == (var_ref compiler_temp@26) (constant uint (3)) ) (
>                  (assign  (x) (var_ref t)  (expression float + (constant float (1.000000)) (expression float neg (expression float abs (expression float + (expression float % (var_ref t@8) (constant float (2.000000)) ) (constant float (-1.000000)) ) ) ) ) ) 
>                )
>                (
>                  (assign  (x) (var_ref t)  (expression float sat (var_ref t@8) ) ) 
>                ))
>
>              ))
>
>            ))
>
>            (assign  (x) (var_ref t)  (expression float + (swiz x (var_ref fastuidraw_float_flat_varying4) )(expression float * (var_ref t) (swiz z (var_ref fastuidraw_float_flat_varying4) )) ) ) 
>            (declare (temporary ) vec2 compiler_temp@27)
>            (assign  (x) (var_ref compiler_temp@27)  (var_ref t) ) 
>            (assign  (y) (var_ref compiler_temp@27)  (swiz y (var_ref fastuidraw_float_flat_varying4) )) 
>            (assign  (xyzw) (var_ref return_value)  (expression vec4 * (var_ref compiler_temp) (expression vec4 * (var_ref compiler_temp@7) (txl vec4 (var_ref fastuidraw_colorStopAtlas)  (var_ref compiler_temp@27)  0 1 () (constant float (0.000000)) )) ) ) 
>          )
>          ())
>
>          (assign  (xyz) (var_ref return_value)  (expression vec3 * (swiz xyz (var_ref return_value) )(swiz w (var_ref return_value) )) ) 
>          (if (expression bool != (expression uint & (swiz y (var_ref fastuidraw_uint_varying2) )(constant uint (3)) ) (constant uint (0)) ) (
>            (declare () vec4 image_color)
>            (declare () float lod)
>            (declare () vec2 q@28)
>            (assign  (x) (var_ref q@28)  (expression float min (expression float max (swiz x (var_ref p) )(constant float (0.000000)) ) (expression float + (swiz x (var_ref fastuidraw_float_flat_varying3) )(constant float (-1.000000)) ) ) ) 
>            (assign  (y) (var_ref q@28)  (expression float min (expression float max (swiz y (var_ref p) )(constant float (0.000000)) ) (expression float + (swiz y (var_ref fastuidraw_float_flat_varying3) )(constant float (-1.000000)) ) ) ) 
>            (declare (temporary ) uint compiler_temp@29)
>            (assign  (x) (var_ref compiler_temp@29)  (expression uint >> (expression uint << (swiz y (var_ref fastuidraw_uint_varying2) )(constant uint (10)) ) (constant uint (30)) ) ) 
>            (declare (temporary ) uint compiler_temp@30)
>            (assign  (x) (var_ref compiler_temp@30)  (expression uint >> (expression uint << (swiz y (var_ref fastuidraw_uint_varying2) )(constant uint (30)) ) (constant uint (30)) ) ) 
>            (declare (temporary ) uint compiler_temp@31)
>            (assign  (x) (var_ref compiler_temp@31)  (expression uint >> (expression uint << (swiz y (var_ref fastuidraw_uint_varying2) )(constant uint (23)) ) (constant uint (25)) ) ) 
>            (if (expression bool < (constant uint (0)) (var_ref compiler_temp@31) ) (
>              (assign  (x) (var_ref lod)  (expression float * (constant float (0.500000)) (expression float log2 (expression float max (constant float (1.000000)) (expression float * (expression float + (expression float dot (var_ref dpdx) (var_ref dpdx) ) (expression float dot (var_ref dpdy) (var_ref dpdy) ) ) (constant float (0.500000)) ) ) ) ) ) 
>              (assign  (x) (var_ref lod)  (expression float min (expression float u2f (var_ref compiler_temp@31) ) (var_ref lod) ) ) 
>            )
>            (
>              (assign  (x) (var_ref lod)  (constant float (0.000000)) ) 
>            ))
>
>            (if (expression bool == (var_ref compiler_temp@29) (constant uint (0)) ) (
>              (declare () vec4 image_color@32)
>              (declare (temporary ) float compiler_temp@33)
>              (assign  (x) (var_ref compiler_temp@33)  (expression float min (var_ref lod) (constant float (4.500000)) ) ) 
>              (if (expression bool == (var_ref compiler_temp@30) (constant uint (1)) ) (
>                (declare (temporary ) float lod@34)
>                (assign  (x) (var_ref lod@34)  (expression float ceil (var_ref compiler_temp@33) ) ) 
>                (declare () vec2 return_value@35)
>                (assign  (xy) (var_ref return_value@35)  (expression vec2 + (expression vec2 * (expression vec2 min (expression vec2 max (var_ref q@28) (constant vec2 (0.000000 0.000000)) ) (swiz xy (var_ref fastuidraw_float_flat_varying3) )) (swiz z (var_ref fastuidraw_float_flat_varying3) )) (swiz zw (var_ref fastuidraw_float_flat_varying2) )) ) 
>                (declare () uint i)
>                (declare () vec2 v_master_tile_texel_coord)
>                (declare () uint v_index_layer)
>                (declare () uvec4 v_tile_id)
>                (declare (temporary ) uvec4 compiler_temp@36)
>                (declare (temporary ) ivec3 compiler_temp@37)
>                (assign  (xy) (var_ref compiler_temp@37)  (expression ivec2 f2i (var_ref return_value@35) ) ) 
>                (assign  (z) (var_ref compiler_temp@37)  (expression int u2i (swiz w (var_ref fastuidraw_uint_varying0) )) ) 
>                (assign  (xyzw) (var_ref compiler_temp@36)  (txf uvec4 (var_ref fastuidraw_imageIndexAtlas)  (var_ref compiler_temp@37)  0  (constant int (0)) )) 
>                (assign  (xy) (var_ref v_master_tile_texel_coord)  (var_ref return_value@35) ) 
>                (assign  (x) (var_ref v_index_layer)  (expression uint + (swiz z (var_ref compiler_temp@36) )(expression uint * (constant uint (256)) (swiz w (var_ref compiler_temp@36) )) ) ) 
>                (assign  (xyzw) (var_ref v_tile_id)  (var_ref compiler_temp@36) ) 
>                (assign  (x) (var_ref i)  (constant uint (1)) ) 
>                (loop (
>                  (if (expression bool >= (var_ref i) (swiz x (var_ref fastuidraw_uint_varying1) )) (
>                    break
>                  )
>                  ())
>
>                  (declare (temporary ) vec2 compiler_temp@38)
>                  (declare (temporary ) uvec4 compiler_temp@39)
>                  (declare () vec2 texel_coordinate)
>                  (assign  (xy) (var_ref compiler_temp@38)  (expression vec2 + (var_ref v_master_tile_texel_coord) (expression vec2 neg (expression vec2 floor (var_ref v_master_tile_texel_coord) ) ) ) ) 
>                  (assign  (xy) (var_ref texel_coordinate)  (expression vec2 + (expression vec2 * (var_ref compiler_temp@38) (constant float (4.000000)) ) (expression vec2 * (expression vec2 u2f (swiz xy (var_ref v_tile_id) )) (constant float (4.000000)) ) ) ) 
>                  (declare (temporary ) ivec3 compiler_temp@40)
>                  (assign  (xy) (var_ref compiler_temp@40)  (expression ivec2 f2i (var_ref texel_coordinate) ) ) 
>                  (assign  (z) (var_ref compiler_temp@40)  (expression int u2i (var_ref v_index_layer) ) ) 
>                  (assign  (xyzw) (var_ref compiler_temp@39)  (txf uvec4 (var_ref fastuidraw_imageIndexAtlas)  (var_ref compiler_temp@40)  0  (constant int (0)) )) 
>                  (assign  (xy) (var_ref compiler_temp@38)  (var_ref texel_coordinate) ) 
>                  (assign  (xy) (var_ref v_master_tile_texel_coord)  (var_ref texel_coordinate) ) 
>                  (assign  (x) (var_ref v_index_layer)  (expression uint + (swiz z (var_ref compiler_temp@39) )(expression uint * (constant uint (256)) (swiz w (var_ref compiler_temp@39) )) ) ) 
>                  (assign  (xyzw) (var_ref v_tile_id)  (var_ref compiler_temp@39) ) 
>                  (assign  (x) (var_ref i)  (expression uint + (var_ref i) (constant uint (1)) ) ) 
>                ))
>
>                (declare (temporary ) vec3 compiler_temp@41)
>                (assign  (xy) (var_ref compiler_temp@41)  (expression vec2 * (expression vec2 + (expression vec2 * (expression vec2 + (var_ref v_master_tile_texel_coord) (expression vec2 neg (expression vec2 floor (var_ref v_master_tile_texel_coord) ) ) ) (constant float (32.000000)) ) (expression vec2 * (expression vec2 u2f (swiz xy (var_ref v_tile_id) )) (constant float (32.000000)) ) ) (constant vec2 (0.000122 0.000122)) ) ) 
>                (assign  (z) (var_ref compiler_temp@41)  (expression float u2f (var_ref v_index_layer) ) ) 
>                (assign  (xyzw) (var_ref image_color@32)  (txl vec4 (var_ref fastuidraw_imageAtlasNearest)  (var_ref compiler_temp@41)  0 1 () (var_ref lod@34) )) 
>              )
>              (
>                (if (expression bool || (expression bool == (var_ref compiler_temp@30) (constant uint (2)) ) (expression bool < (constant float (0.500000)) (var_ref compiler_temp@33) ) ) (
>                  (declare (temporary ) int lod_i)
>                  (assign  (x) (var_ref lod_i)  (expression int f2i (expression float round_even (var_ref compiler_temp@33) ) ) ) 
>                  (declare () float lod_factor)
>                  (assign  (x) (var_ref lod_factor)  (expression float i2f (expression int << (constant int (1)) (var_ref lod_i) ) ) ) 
>                  (declare () vec2 return_value@42)
>                  (assign  (xy) (var_ref return_value@42)  (expression vec2 + (expression vec2 * (expression vec2 min (expression vec2 max (var_ref q@28) (swiz xx (expression float * (constant float (0.500000)) (var_ref lod_factor) ) )) (expression vec2 + (swiz xy (var_ref fastuidraw_float_flat_varying3) )(expression vec2 neg (swiz xx (expression float * (constant float (0.500000)) (var_ref lod_factor) ) )) ) ) (swiz z (var_ref fastuidraw_float_flat_varying3) )) (swiz zw (var_ref fastuidraw_float_flat_varying2) )) ) 
>                  (declare () float slack_requirement)
>                  (declare () vec4 image_color@43)
>                  (assign  (x) (var_ref slack_requirement)  (expression float * (constant float (0.500000)) (var_ref lod_factor) ) ) 
>                  (declare (temporary ) vec2 compiler_temp@44)
>                  (assign  (xy) (var_ref compiler_temp@44)  (expression vec2 * (expression vec2 + (var_ref return_value@42) (expression vec2 neg (expression vec2 * (constant vec2 (4.000000 4.000000)) (expression vec2 floor (expression vec2 * (constant float (0.250000)) (var_ref return_value@42) ) ) ) ) ) (swiz w (var_ref fastuidraw_float_flat_varying3) )) ) 
>                  (declare (temporary ) float compiler_temp@45)
>                  (declare (temporary ) float compiler_temp@46)
>                  (declare () float tile_coord)
>                  (assign  (x) (var_ref tile_coord)  (expression float + (swiz x (var_ref compiler_temp@44) )(expression float neg (expression float * (constant float (32.000000)) (expression float floor (expression float * (swiz x (var_ref compiler_temp@44) )(constant float (0.031250)) ) ) ) ) ) ) 
>                  (assign  (x) (var_ref compiler_temp@45)  (expression float neg (var_ref tile_coord) ) ) 
>                  (assign  (x) (var_ref compiler_temp@46)  (expression float + (constant float (31.000000)) (expression float neg (var_ref tile_coord) ) ) ) 
>                  (declare (temporary ) float compiler_temp@47)
>                  (declare (temporary ) float compiler_temp@48)
>                  (declare () float tile_coord@49)
>                  (assign  (x) (var_ref tile_coord@49)  (expression float + (swiz y (var_ref compiler_temp@44) )(expression float neg (expression float * (constant float (32.000000)) (expression float floor (expression float * (swiz y (var_ref compiler_temp@44) )(constant float (0.031250)) ) ) ) ) ) ) 
>                  (assign  (x) (var_ref compiler_temp@47)  (expression float neg (var_ref tile_coord@49) ) ) 
>                  (assign  (x) (var_ref compiler_temp@48)  (expression float + (constant float (31.000000)) (expression float neg (var_ref tile_coord@49) ) ) ) 
>                  (declare () uint i@50)
>                  (declare () vec2 v_master_tile_texel_coord@51)
>                  (declare () uint v_index_layer@52)
>                  (declare () uvec4 v_tile_id@53)
>                  (declare (temporary ) uvec4 compiler_temp@54)
>                  (declare (temporary ) ivec3 compiler_temp@55)
>                  (assign  (xy) (var_ref compiler_temp@55)  (expression ivec2 f2i (var_ref return_value@42) ) ) 
>                  (assign  (z) (var_ref compiler_temp@55)  (expression int u2i (swiz w (var_ref fastuidraw_uint_varying0) )) ) 
>                  (assign  (xyzw) (var_ref compiler_temp@54)  (txf uvec4 (var_ref fastuidraw_imageIndexAtlas)  (var_ref compiler_temp@55)  0  (constant int (0)) )) 
>                  (assign  (xy) (var_ref v_master_tile_texel_coord@51)  (var_ref return_value@42) ) 
>                  (assign  (x) (var_ref v_index_layer@52)  (expression uint + (swiz z (var_ref compiler_temp@54) )(expression uint * (constant uint (256)) (swiz w (var_ref compiler_temp@54) )) ) ) 
>                  (assign  (xyzw) (var_ref v_tile_id@53)  (var_ref compiler_temp@54) ) 
>                  (assign  (x) (var_ref i@50)  (constant uint (1)) ) 
>                  (loop (
>                    (if (expression bool >= (var_ref i@50) (swiz x (var_ref fastuidraw_uint_varying1) )) (
>                      break
>                    )
>                    ())
>
>                    (declare (temporary ) vec2 compiler_temp@56)
>                    (declare (temporary ) uvec4 compiler_temp@57)
>                    (declare () vec2 texel_coordinate@58)
>                    (assign  (xy) (var_ref compiler_temp@56)  (expression vec2 + (var_ref v_master_tile_texel_coord@51) (expression vec2 neg (expression vec2 floor (var_ref v_master_tile_texel_coord@51) ) ) ) ) 
>                    (assign  (xy) (var_ref texel_coordinate@58)  (expression vec2 + (expression vec2 * (var_ref compiler_temp@56) (constant float (4.000000)) ) (expression vec2 * (expression vec2 u2f (swiz xy (var_ref v_tile_id@53) )) (constant float (4.000000)) ) ) ) 
>                    (declare (temporary ) ivec3 compiler_temp@59)
>                    (assign  (xy) (var_ref compiler_temp@59)  (expression ivec2 f2i (var_ref texel_coordinate@58) ) ) 
>                    (assign  (z) (var_ref compiler_temp@59)  (expression int u2i (var_ref v_index_layer@52) ) ) 
>                    (assign  (xyzw) (var_ref compiler_temp@57)  (txf uvec4 (var_ref fastuidraw_imageIndexAtlas)  (var_ref compiler_temp@59)  0  (constant int (0)) )) 
>                    (assign  (xy) (var_ref compiler_temp@56)  (var_ref texel_coordinate@58) ) 
>                    (assign  (xy) (var_ref v_master_tile_texel_coord@51)  (var_ref texel_coordinate@58) ) 
>                    (assign  (x) (var_ref v_index_layer@52)  (expression uint + (swiz z (var_ref compiler_temp@57) )(expression uint * (constant uint (256)) (swiz w (var_ref compiler_temp@57) )) ) ) 
>                    (assign  (xyzw) (var_ref v_tile_id@53)  (var_ref compiler_temp@57) ) 
>                    (assign  (x) (var_ref i@50)  (expression uint + (var_ref i@50) (constant uint (1)) ) ) 
>                  ))
>
>                  (declare (temporary ) vec2 compiler_temp@60)
>                  (assign  (xy) (var_ref compiler_temp@60)  (expression vec2 + (expression vec2 * (expression vec2 + (var_ref v_master_tile_texel_coord@51) (expression vec2 neg (expression vec2 floor (var_ref v_master_tile_texel_coord@51) ) ) ) (constant float (32.000000)) ) (expression vec2 * (expression vec2 u2f (swiz xy (var_ref v_tile_id@53) )) (constant float (32.000000)) ) ) ) 
>                  (if (expression bool && (expression bool && (expression bool && (expression bool >= (var_ref compiler_temp@46) (var_ref slack_requirement) ) (expression bool >= (var_ref compiler_temp@48) (var_ref slack_requirement) ) ) (expression bool >= (expression float neg (var_ref slack_requirement) ) (var_ref compiler_temp@45) ) ) (expression bool >= (expression float neg (var_ref slack_requirement) ) (var_ref compiler_temp@47) ) ) (
>                    (declare (temporary ) vec3 compiler_temp@61)
>                    (assign  (xy) (var_ref compiler_temp@61)  (expression vec2 * (var_ref compiler_temp@60) (constant vec2 (0.000122 0.000122)) ) ) 
>                    (assign  (z) (var_ref compiler_temp@61)  (expression float u2f (var_ref v_index_layer@52) ) ) 
>                    (assign  (xyzw) (var_ref image_color@43)  (txl vec4 (var_ref fastuidraw_imageAtlasLinear)  (var_ref compiler_temp@61)  0 1 () (expression float i2f (var_ref lod_i) ) )) 
>                  )
>                  (
>                    (declare (temporary ) vec3 compiler_temp@62)
>                    (assign  (xy) (var_ref compiler_temp@62)  (expression vec2 * (var_ref compiler_temp@60) (constant vec2 (0.000122 0.000122)) ) ) 
>                    (assign  (z) (var_ref compiler_temp@62)  (expression float u2f (var_ref v_index_layer@52) ) ) 
>                    (assign  (xyzw) (var_ref image_color@43)  (txl vec4 (var_ref fastuidraw_imageAtlasNearest)  (var_ref compiler_temp@62)  0 1 () (expression float i2f (var_ref lod_i) ) )) 
>                  ))
>
>                  (assign  (xyzw) (var_ref image_color@32)  (var_ref image_color@43) ) 
>                )
>                (
>                  (declare () vec4 t11)
>                  (declare () vec4 t01)
>                  (declare () vec4 t10)
>                  (declare () vec4 t00)
>                  (declare () vec4 recip_weight_sums)
>                  (declare () vec2 linear_weight)
>                  (declare () vec2 master_tile_texel_coord)
>                  (assign  (xy) (var_ref master_tile_texel_coord)  (expression vec2 + (expression vec2 + (expression vec2 * (expression vec2 min (expression vec2 max (var_ref q@28) (constant vec2 (2.000000 2.000000)) ) (expression vec2 + (swiz xy (var_ref fastuidraw_float_flat_varying3) )(constant vec2 (-2.000000 -2.000000)) ) ) (swiz z (var_ref fastuidraw_float_flat_varying3) )) (swiz zw (var_ref fastuidraw_float_flat_varying2) )) (expression vec2 neg (swiz xx (expression float * (constant float (0.500000)) (swiz z (var_ref fastuidraw_float_flat_varying3) )) )) ) ) 
>                  (declare () vec2 return_value@63)
>                  (assign  (xy) (var_ref return_value@63)  (expression vec2 * (expression vec2 + (var_ref master_tile_texel_coord) (expression vec2 neg (swiz zw (var_ref fastuidraw_float_flat_varying2) )) ) (swiz w (var_ref fastuidraw_float_flat_varying3) )) ) 
>                  (declare (temporary ) float compiler_temp@64)
>                  (declare (temporary ) float compiler_temp@65)
>                  (declare () float tile_coord@66)
>                  (assign  (x) (var_ref tile_coord@66)  (expression float + (swiz x (var_ref return_value@63) )(expression float neg (expression float * (constant float (32.000000)) (expression float floor (expression float * (swiz x (var_ref return_value@63) )(constant float (0.031250)) ) ) ) ) ) ) 
>                  (assign  (x) (var_ref compiler_temp@64)  (expression float neg (var_ref tile_coord@66) ) ) 
>                  (assign  (x) (var_ref compiler_temp@65)  (expression float + (constant float (31.000000)) (expression float neg (var_ref tile_coord@66) ) ) ) 
>                  (declare (temporary ) float compiler_temp@67)
>                  (declare (temporary ) float compiler_temp@68)
>                  (declare () float tile_coord@69)
>                  (assign  (x) (var_ref tile_coord@69)  (expression float + (swiz y (var_ref return_value@63) )(expression float neg (expression float * (constant float (32.000000)) (expression float floor (expression float * (swiz y (var_ref return_value@63) )(constant float (0.031250)) ) ) ) ) ) ) 
>                  (assign  (x) (var_ref compiler_temp@67)  (expression float neg (var_ref tile_coord@69) ) ) 
>                  (assign  (x) (var_ref compiler_temp@68)  (expression float + (constant float (31.000000)) (expression float neg (var_ref tile_coord@69) ) ) ) 
>                  (declare (temporary ) vec2 compiler_temp@70)
>                  (assign  (xy) (var_ref compiler_temp@70)  (expression vec2 fract (var_ref return_value@63) ) ) 
>                  (declare (temporary ) vec4 compiler_temp@71)
>                  (declare () vec4 w)
>                  (declare (temporary ) float compiler_temp@72)
>                  (assign  (x) (var_ref compiler_temp@72)  (expression float * (swiz x (var_ref compiler_temp@70) )(swiz x (var_ref compiler_temp@70) )) ) 
>                  (declare (temporary ) float compiler_temp@73)
>                  (assign  (x) (var_ref compiler_temp@73)  (expression float * (var_ref compiler_temp@72) (swiz x (var_ref compiler_temp@70) )) ) 
>                  (declare (temporary ) float compiler_temp@74)
>                  (assign  (x) (var_ref compiler_temp@74)  (expression float + (constant float (1.000000)) (expression float neg (swiz x (var_ref compiler_temp@70) )) ) ) 
>                  (declare (temporary ) float compiler_temp@75)
>                  (assign  (x) (var_ref compiler_temp@75)  (expression float * (var_ref compiler_temp@74) (var_ref compiler_temp@74) ) ) 
>                  (declare (temporary ) float compiler_temp@76)
>                  (assign  (x) (var_ref compiler_temp@76)  (expression float * (var_ref compiler_temp@75) (var_ref compiler_temp@74) ) ) 
>                  (assign  (x) (var_ref w)  (var_ref compiler_temp@76) ) 
>                  (assign  (y) (var_ref w)  (expression float + (expression float + (expression float * (constant float (3.000000)) (var_ref compiler_temp@73) ) (expression float neg (expression float * (constant float (6.000000)) (var_ref compiler_temp@72) ) ) ) (constant float (4.000000)) ) ) 
>                  (assign  (z) (var_ref w)  (expression float + (expression float + (expression float * (constant float (3.000000)) (var_ref compiler_temp@76) ) (expression float neg (expression float * (constant float (6.000000)) (var_ref compiler_temp@75) ) ) ) (constant float (4.000000)) ) ) 
>                  (assign  (w) (var_ref w)  (var_ref compiler_temp@73) ) 
>                  (assign  (xyzw) (var_ref compiler_temp@71)  (expression vec4 * (var_ref w) (expression float rcp (constant float (6.000000)) ) ) ) 
>                  (declare (temporary ) vec4 compiler_temp@77)
>                  (declare () vec4 w@78)
>                  (declare (temporary ) float compiler_temp@79)
>                  (assign  (x) (var_ref compiler_temp@79)  (expression float * (swiz y (var_ref compiler_temp@70) )(swiz y (var_ref compiler_temp@70) )) ) 
>                  (declare (temporary ) float compiler_temp@80)
>                  (assign  (x) (var_ref compiler_temp@80)  (expression float * (var_ref compiler_temp@79) (swiz y (var_ref compiler_temp@70) )) ) 
>                  (declare (temporary ) float compiler_temp@81)
>                  (assign  (x) (var_ref compiler_temp@81)  (expression float + (constant float (1.000000)) (expression float neg (swiz y (var_ref compiler_temp@70) )) ) ) 
>                  (declare (temporary ) float compiler_temp@82)
>                  (assign  (x) (var_ref compiler_temp@82)  (expression float * (var_ref compiler_temp@81) (var_ref compiler_temp@81) ) ) 
>                  (declare (temporary ) float compiler_temp@83)
>                  (assign  (x) (var_ref compiler_temp@83)  (expression float * (var_ref compiler_temp@82) (var_ref compiler_temp@81) ) ) 
>                  (assign  (x) (var_ref w@78)  (var_ref compiler_temp@83) ) 
>                  (assign  (y) (var_ref w@78)  (expression float + (expression float + (expression float * (constant float (3.000000)) (var_ref compiler_temp@80) ) (expression float neg (expression float * (constant float (6.000000)) (var_ref compiler_temp@79) ) ) ) (constant float (4.000000)) ) ) 
>                  (assign  (z) (var_ref w@78)  (expression float + (expression float + (expression float * (constant float (3.000000)) (var_ref compiler_temp@83) ) (expression float neg (expression float * (constant float (6.000000)) (var_ref compiler_temp@82) ) ) ) (constant float (4.000000)) ) ) 
>                  (assign  (w) (var_ref w@78)  (var_ref compiler_temp@80) ) 
>                  (assign  (xyzw) (var_ref compiler_temp@77)  (expression vec4 * (var_ref w@78) (expression float rcp (constant float (6.000000)) ) ) ) 
>                  (declare (temporary ) vec4 compiler_temp@84)
>                  (assign  (x) (var_ref compiler_temp@84)  (expression float + (swiz x (var_ref compiler_temp@71) )(swiz y (var_ref compiler_temp@71) )) ) 
>                  (assign  (y) (var_ref compiler_temp@84)  (expression float + (swiz z (var_ref compiler_temp@71) )(swiz w (var_ref compiler_temp@71) )) ) 
>                  (assign  (z) (var_ref compiler_temp@84)  (expression float + (swiz x (var_ref compiler_temp@77) )(swiz y (var_ref compiler_temp@77) )) ) 
>                  (assign  (w) (var_ref compiler_temp@84)  (expression float + (swiz z (var_ref compiler_temp@77) )(swiz w (var_ref compiler_temp@77) )) ) 
>                  (assign  (xyzw) (var_ref recip_weight_sums)  (expression vec4 rcp (var_ref compiler_temp@84) ) ) 
>                  (assign  (x) (var_ref linear_weight)  (expression float * (swiz y (var_ref compiler_temp@84) )(expression float rcp (expression float + (swiz x (var_ref compiler_temp@84) )(swiz y (var_ref compiler_temp@84) )) ) ) ) 
>                  (assign  (y) (var_ref linear_weight)  (expression float * (swiz w (var_ref compiler_temp@84) )(expression float rcp (expression float + (swiz z (var_ref compiler_temp@84) )(swiz w (var_ref compiler_temp@84) )) ) ) ) 
>                  (if (expression bool && (expression bool && (expression bool && (expression bool >= (constant float (-1.500000)) (var_ref compiler_temp@64) ) (expression bool >= (constant float (-1.500000)) (var_ref compiler_temp@67) ) ) (expression bool >= (var_ref compiler_temp@65) (constant float (2.500000)) ) ) (expression bool >= (var_ref compiler_temp@68) (constant float (2.500000)) ) ) (
>                    (declare () vec4 texture_coords)
>                    (declare () vec4 corner_coords)
>                    (declare () vec2 texel_coord)
>                    (declare () uint i@85)
>                    (declare () vec2 v_master_tile_texel_coord@86)
>                    (declare () uint v_index_layer@87)
>                    (declare () uvec4 v_tile_id@88)
>                    (declare (temporary ) uvec4 compiler_temp@89)
>                    (declare (temporary ) ivec3 compiler_temp@90)
>                    (assign  (xy) (var_ref compiler_temp@90)  (expression ivec2 f2i (var_ref master_tile_texel_coord) ) ) 
>                    (assign  (z) (var_ref compiler_temp@90)  (expression int u2i (swiz w (var_ref fastuidraw_uint_varying0) )) ) 
>                    (assign  (xyzw) (var_ref compiler_temp@89)  (txf uvec4 (var_ref fastuidraw_imageIndexAtlas)  (var_ref compiler_temp@90)  0  (constant int (0)) )) 
>                    (assign  (xy) (var_ref v_master_tile_texel_coord@86)  (var_ref master_tile_texel_coord) ) 
>                    (assign  (x) (var_ref v_index_layer@87)  (expression uint + (swiz z (var_ref compiler_temp@89) )(expression uint * (constant uint (256)) (swiz w (var_ref compiler_temp@89) )) ) ) 
>                    (assign  (xyzw) (var_ref v_tile_id@88)  (var_ref compiler_temp@89) ) 
>                    (assign  (x) (var_ref i@85)  (constant uint (1)) ) 
>                    (loop (
>                      (if (expression bool >= (var_ref i@85) (swiz x (var_ref fastuidraw_uint_varying1) )) (
>                        break
>                      )
>                      ())
>
>                      (declare (temporary ) vec2 compiler_temp@91)
>                      (declare (temporary ) uvec4 compiler_temp@92)
>                      (declare () vec2 texel_coordinate@93)
>                      (assign  (xy) (var_ref compiler_temp@91)  (expression vec2 + (var_ref v_master_tile_texel_coord@86) (expression vec2 neg (expression vec2 floor (var_ref v_master_tile_texel_coord@86) ) ) ) ) 
>                      (assign  (xy) (var_ref texel_coordinate@93)  (expression vec2 + (expression vec2 * (var_ref compiler_temp@91) (constant float (4.000000)) ) (expression vec2 * (expression vec2 u2f (swiz xy (var_ref v_tile_id@88) )) (constant float (4.000000)) ) ) ) 
>                      (declare (temporary ) ivec3 compiler_temp@94)
>                      (assign  (xy) (var_ref compiler_temp@94)  (expression ivec2 f2i (var_ref texel_coordinate@93) ) ) 
>                      (assign  (z) (var_ref compiler_temp@94)  (expression int u2i (var_ref v_index_layer@87) ) ) 
>                      (assign  (xyzw) (var_ref compiler_temp@92)  (txf uvec4 (var_ref fastuidraw_imageIndexAtlas)  (var_ref compiler_temp@94)  0  (constant int (0)) )) 
>                      (assign  (xy) (var_ref compiler_temp@91)  (var_ref texel_coordinate@93) ) 
>                      (assign  (xy) (var_ref v_master_tile_texel_coord@86)  (var_ref texel_coordinate@93) ) 
>                      (assign  (x) (var_ref v_index_layer@87)  (expression uint + (swiz z (var_ref compiler_temp@92) )(expression uint * (constant uint (256)) (swiz w (var_ref compiler_temp@92) )) ) ) 
>                      (assign  (xyzw) (var_ref v_tile_id@88)  (var_ref compiler_temp@92) ) 
>                      (assign  (x) (var_ref i@85)  (expression uint + (var_ref i@85) (constant uint (1)) ) ) 
>                    ))
>
>                    (assign  (xy) (var_ref texel_coord)  (expression vec2 + (expression vec2 + (expression vec2 * (expression vec2 + (var_ref v_master_tile_texel_coord@86) (expression vec2 neg (expression vec2 floor (var_ref v_master_tile_texel_coord@86) ) ) ) (constant float (32.000000)) ) (expression vec2 * (expression vec2 u2f (swiz xy (var_ref v_tile_id@88) )) (constant float (32.000000)) ) ) (expression vec2 neg (var_ref compiler_temp@70) ) ) ) 
>                    (assign  (xz) (var_ref corner_coords)  (expression vec2 + (var_ref texel_coord) (constant vec2 (-0.500000 -0.500000)) ) ) 
>                    (assign  (yw) (var_ref corner_coords)  (expression vec2 + (var_ref texel_coord) (constant vec2 (1.500000 1.500000)) ) ) 
>                    (declare (temporary ) vec4 compiler_temp@95)
>                    (assign  (x) (var_ref compiler_temp@95)  (swiz y (var_ref compiler_temp@71) )) 
>                    (assign  (y) (var_ref compiler_temp@95)  (swiz w (var_ref compiler_temp@71) )) 
>                    (assign  (z) (var_ref compiler_temp@95)  (swiz y (var_ref compiler_temp@77) )) 
>                    (assign  (w) (var_ref compiler_temp@95)  (swiz w (var_ref compiler_temp@77) )) 
>                    (assign  (xyzw) (var_ref texture_coords)  (expression vec4 + (var_ref corner_coords) (expression vec4 * (var_ref compiler_temp@95) (var_ref recip_weight_sums) ) ) ) 
>                    (assign  (xyzw) (var_ref texture_coords)  (expression vec4 * (var_ref texture_coords) (constant vec4 (0.000122 0.000122 0.000122 0.000122)) ) ) 
>                    (declare (temporary ) vec3 compiler_temp@96)
>                    (assign  (xy) (var_ref compiler_temp@96)  (swiz xz (var_ref texture_coords) )) 
>                    (assign  (z) (var_ref compiler_temp@96)  (expression float u2f (var_ref v_index_layer@87) ) ) 
>                    (assign  (xyzw) (var_ref t00)  (txl vec4 (var_ref fastuidraw_imageAtlasLinear)  (var_ref compiler_temp@96)  0 1 () (constant float (0.000000)) )) 
>                    (declare (temporary ) vec3 compiler_temp@97)
>                    (assign  (xy) (var_ref compiler_temp@97)  (swiz yz (var_ref texture_coords) )) 
>                    (assign  (z) (var_ref compiler_temp@97)  (expression float u2f (var_ref v_index_layer@87) ) ) 
>                    (assign  (xyzw) (var_ref t10)  (txl vec4 (var_ref fastuidraw_imageAtlasLinear)  (var_ref compiler_temp@97)  0 1 () (constant float (0.000000)) )) 
>                    (declare (temporary ) vec3 compiler_temp@98)
>                    (assign  (xy) (var_ref compiler_temp@98)  (swiz xw (var_ref texture_coords) )) 
>                    (assign  (z) (var_ref compiler_temp@98)  (expression float u2f (var_ref v_index_layer@87) ) ) 
>                    (assign  (xyzw) (var_ref t01)  (txl vec4 (var_ref fastuidraw_imageAtlasLinear)  (var_ref compiler_temp@98)  0 1 () (constant float (0.000000)) )) 
>                    (declare (temporary ) vec3 compiler_temp@99)
>                    (assign  (xy) (var_ref compiler_temp@99)  (swiz yw (var_ref texture_coords) )) 
>                    (assign  (z) (var_ref compiler_temp@99)  (expression float u2f (var_ref v_index_layer@87) ) ) 
>                    (assign  (xyzw) (var_ref t11)  (txl vec4 (var_ref fastuidraw_imageAtlasLinear)  (var_ref compiler_temp@99)  0 1 () (constant float (0.000000)) )) 
>                  )
>                  (
>                    (declare () vec4 master_coords)
>                    (declare () vec4 offset_coords)
>                    (declare () vec4 corner_coords@100)
>                    (declare () vec2 master_texel_coord)
>                    (assign  (xy) (var_ref master_texel_coord)  (expression vec2 + (var_ref master_tile_texel_coord) (expression vec2 neg (expression vec2 * (var_ref compiler_temp@70) (swiz zz (var_ref fastuidraw_float_flat_varying3) )) ) ) ) 
>                    (assign  (xz) (var_ref corner_coords@100)  (expression vec2 + (var_ref master_texel_coord) (expression vec2 neg (swiz xx (expression float * (constant float (0.500000)) (swiz z (var_ref fastuidraw_float_flat_varying3) )) )) ) ) 
>                    (assign  (yw) (var_ref corner_coords@100)  (expression vec2 + (var_ref master_texel_coord) (swiz xx (expression float * (constant float (1.500000)) (swiz z (var_ref fastuidraw_float_flat_varying3) )) )) ) 
>                    (declare (temporary ) vec4 compiler_temp@101)
>                    (assign  (x) (var_ref compiler_temp@101)  (swiz y (var_ref compiler_temp@71) )) 
>                    (assign  (y) (var_ref compiler_temp@101)  (swiz w (var_ref compiler_temp@71) )) 
>                    (assign  (z) (var_ref compiler_temp@101)  (swiz y (var_ref compiler_temp@77) )) 
>                    (assign  (w) (var_ref compiler_temp@101)  (swiz w (var_ref compiler_temp@77) )) 
>                    (assign  (xyzw) (var_ref offset_coords)  (expression vec4 * (var_ref compiler_temp@101) (var_ref recip_weight_sums) ) ) 
>                    (assign  (xyzw) (var_ref offset_coords)  (expression vec4 * (var_ref offset_coords) (swiz z (var_ref fastuidraw_float_flat_varying3) )) ) 
>                    (assign  (xyzw) (var_ref master_coords)  (expression vec4 + (var_ref corner_coords@100) (var_ref offset_coords) ) ) 
>                    (declare () vec4 image_color@102)
>                    (declare (temporary ) vec2 compiler_temp@103)
>                    (assign  (xy) (var_ref compiler_temp@103)  (expression vec2 * (expression vec2 + (swiz xz (var_ref master_coords) )(expression vec2 neg (expression vec2 * (constant vec2 (4.000000 4.000000)) (expression vec2 floor (expression vec2 * (constant float (0.250000)) (swiz xz (var_ref master_coords) )) ) ) ) ) (swiz w (var_ref fastuidraw_float_flat_varying3) )) ) 
>                    (declare (temporary ) float compiler_temp@104)
>                    (declare (temporary ) float compiler_temp@105)
>                    (declare () float tile_coord@106)
>                    (assign  (x) (var_ref tile_coord@106)  (expression float + (swiz x (var_ref compiler_temp@103) )(expression float neg (expression float * (constant float (32.000000)) (expression float floor (expression float * (swiz x (var_ref compiler_temp@103) )(constant float (0.031250)) ) ) ) ) ) ) 
>                    (assign  (x) (var_ref compiler_temp@104)  (expression float neg (var_ref tile_coord@106) ) ) 
>                    (assign  (x) (var_ref compiler_temp@105)  (expression float + (constant float (31.000000)) (expression float neg (var_ref tile_coord@106) ) ) ) 
>                    (declare (temporary ) float compiler_temp@107)
>                    (declare (temporary ) float compiler_temp@108)
>                    (declare () float tile_coord@109)
>                    (assign  (x) (var_ref tile_coord@109)  (expression float + (swiz y (var_ref compiler_temp@103) )(expression float neg (expression float * (constant float (32.000000)) (expression float floor (expression float * (swiz y (var_ref compiler_temp@103) )(constant float (0.031250)) ) ) ) ) ) ) 
>                    (assign  (x) (var_ref compiler_temp@107)  (expression float neg (var_ref tile_coord@109) ) ) 
>                    (assign  (x) (var_ref compiler_temp@108)  (expression float + (constant float (31.000000)) (expression float neg (var_ref tile_coord@109) ) ) ) 
>                    (declare () uint i@110)
>                    (declare () vec2 v_master_tile_texel_coord@111)
>                    (declare () uint v_index_layer@112)
>                    (declare () uvec4 v_tile_id@113)
>                    (declare (temporary ) uvec4 compiler_temp@114)
>                    (declare (temporary ) ivec3 compiler_temp@115)
>                    (assign  (xy) (var_ref compiler_temp@115)  (expression ivec2 f2i (swiz xz (var_ref master_coords) )) ) 
>                    (assign  (z) (var_ref compiler_temp@115)  (expression int u2i (swiz w (var_ref fastuidraw_uint_varying0) )) ) 
>                    (assign  (xyzw) (var_ref compiler_temp@114)  (txf uvec4 (var_ref fastuidraw_imageIndexAtlas)  (var_ref compiler_temp@115)  0  (constant int (0)) )) 
>                    (assign  (xy) (var_ref v_master_tile_texel_coord@111)  (swiz xz (var_ref master_coords) )) 
>                    (assign  (x) (var_ref v_index_layer@112)  (expression uint + (swiz z (var_ref compiler_temp@114) )(expression uint * (constant uint (256)) (swiz w (var_ref compiler_temp@114) )) ) ) 
>                    (assign  (xyzw) (var_ref v_tile_id@113)  (var_ref compiler_temp@114) ) 
>                    (assign  (x) (var_ref i@110)  (constant uint (1)) ) 
>                    (loop (
>                      (if (expression bool >= (var_ref i@110) (swiz x (var_ref fastuidraw_uint_varying1) )) (
>                        break
>                      )
>                      ())
>
>                      (declare (temporary ) vec2 compiler_temp@116)
>                      (declare (temporary ) uvec4 compiler_temp@117)
>                      (declare () vec2 texel_coordinate@118)
>                      (assign  (xy) (var_ref compiler_temp@116)  (expression vec2 + (var_ref v_master_tile_texel_coord@111) (expression vec2 neg (expression vec2 floor (var_ref v_master_tile_texel_coord@111) ) ) ) ) 
>                      (assign  (xy) (var_ref texel_coordinate@118)  (expression vec2 + (expression vec2 * (var_ref compiler_temp@116) (constant float (4.000000)) ) (expression vec2 * (expression vec2 u2f (swiz xy (var_ref v_tile_id@113) )) (constant float (4.000000)) ) ) ) 
>                      (declare (temporary ) ivec3 compiler_temp@119)
>                      (assign  (xy) (var_ref compiler_temp@119)  (expression ivec2 f2i (var_ref texel_coordinate@118) ) ) 
>                      (assign  (z) (var_ref compiler_temp@119)  (expression int u2i (var_ref v_index_layer@112) ) ) 
>                      (assign  (xyzw) (var_ref compiler_temp@117)  (txf uvec4 (var_ref fastuidraw_imageIndexAtlas)  (var_ref compiler_temp@119)  0  (constant int (0)) )) 
>                      (assign  (xy) (var_ref compiler_temp@116)  (var_ref texel_coordinate@118) ) 
>                      (assign  (xy) (var_ref v_master_tile_texel_coord@111)  (var_ref texel_coordinate@118) ) 
>                      (assign  (x) (var_ref v_index_layer@112)  (expression uint + (swiz z (var_ref compiler_temp@117) )(expression uint * (constant uint (256)) (swiz w (var_ref compiler_temp@117) )) ) ) 
>                      (assign  (xyzw) (var_ref v_tile_id@113)  (var_ref compiler_temp@117) ) 
>                      (assign  (x) (var_ref i@110)  (expression uint + (var_ref i@110) (constant uint (1)) ) ) 
>                    ))
>
>                    (declare (temporary ) vec2 compiler_temp@120)
>                    (assign  (xy) (var_ref compiler_temp@120)  (expression vec2 + (expression vec2 * (expression vec2 + (var_ref v_master_tile_texel_coord@111) (expression vec2 neg (expression vec2 floor (var_ref v_master_tile_texel_coord@111) ) ) ) (constant float (32.000000)) ) (expression vec2 * (expression vec2 u2f (swiz xy (var_ref v_tile_id@113) )) (constant float (32.000000)) ) ) ) 
>                    (if (expression bool && (expression bool && (expression bool && (expression bool >= (var_ref compiler_temp@105) (constant float (0.500000)) ) (expression bool >= (var_ref compiler_temp@108) (constant float (0.500000)) ) ) (expression bool >= (constant float (-0.500000)) (var_ref compiler_temp@104) ) ) (expression bool >= (constant float (-0.500000)) (var_ref compiler_temp@107) ) ) (
>                      (declare (temporary ) vec3 compiler_temp@121)
>                      (assign  (xy) (var_ref compiler_temp@121)  (expression vec2 * (var_ref compiler_temp@120) (constant vec2 (0.000122 0.000122)) ) ) 
>                      (assign  (z) (var_ref compiler_temp@121)  (expression float u2f (var_ref v_index_layer@112) ) ) 
>                      (assign  (xyzw) (var_ref image_color@102)  (txl vec4 (var_ref fastuidraw_imageAtlasLinear)  (var_ref compiler_temp@121)  0 1 () (constant float (0.000000)) )) 
>                    )
>                    (
>                      (declare (temporary ) vec3 compiler_temp@122)
>                      (assign  (xy) (var_ref compiler_temp@122)  (expression vec2 * (var_ref compiler_temp@120) (constant vec2 (0.000122 0.000122)) ) ) 
>                      (assign  (z) (var_ref compiler_temp@122)  (expression float u2f (var_ref v_index_layer@112) ) ) 
>                      (assign  (xyzw) (var_ref image_color@102)  (txl vec4 (var_ref fastuidraw_imageAtlasNearest)  (var_ref compiler_temp@122)  0 1 () (constant float (0.000000)) )) 
>                    ))
>
>                    (assign  (xyzw) (var_ref t00)  (var_ref image_color@102) ) 
>                    (declare () vec4 image_color@123)
>                    (declare (temporary ) vec2 compiler_temp@124)
>                    (assign  (xy) (var_ref compiler_temp@124)  (expression vec2 * (expression vec2 + (swiz yz (var_ref master_coords) )(expression vec2 neg (expression vec2 * (constant vec2 (4.000000 4.000000)) (expression vec2 floor (expression vec2 * (constant float (0.250000)) (swiz yz (var_ref master_coords) )) ) ) ) ) (swiz w (var_ref fastuidraw_float_flat_varying3) )) ) 
>                    (declare (temporary ) float compiler_temp@125)
>                    (declare (temporary ) float compiler_temp@126)
>                    (declare () float tile_coord@127)
>                    (assign  (x) (var_ref tile_coord@127)  (expression float + (swiz x (var_ref compiler_temp@124) )(expression float neg (expression float * (constant float (32.000000)) (expression float floor (expression float * (swiz x (var_ref compiler_temp@124) )(constant float (0.031250)) ) ) ) ) ) ) 
>                    (assign  (x) (var_ref compiler_temp@125)  (expression float neg (var_ref tile_coord@127) ) ) 
>                    (assign  (x) (var_ref compiler_temp@126)  (expression float + (constant float (31.000000)) (expression float neg (var_ref tile_coord@127) ) ) ) 
>                    (declare (temporary ) float compiler_temp@128)
>                    (declare (temporary ) float compiler_temp@129)
>                    (declare () float tile_coord@130)
>                    (assign  (x) (var_ref tile_coord@130)  (expression float + (swiz y (var_ref compiler_temp@124) )(expression float neg (expression float * (constant float (32.000000)) (expression float floor (expression float * (swiz y (var_ref compiler_temp@124) )(constant float (0.031250)) ) ) ) ) ) ) 
>                    (assign  (x) (var_ref compiler_temp@128)  (expression float neg (var_ref tile_coord@130) ) ) 
>                    (assign  (x) (var_ref compiler_temp@129)  (expression float + (constant float (31.000000)) (expression float neg (var_ref tile_coord@130) ) ) ) 
>                    (declare () uint i@131)
>                    (declare () vec2 v_master_tile_texel_coord@132)
>                    (declare () uint v_index_layer@133)
>                    (declare () uvec4 v_tile_id@134)
>                    (declare (temporary ) uvec4 compiler_temp@135)
>                    (declare (temporary ) ivec3 compiler_temp@136)
>                    (assign  (xy) (var_ref compiler_temp@136)  (expression ivec2 f2i (swiz yz (var_ref master_coords) )) ) 
>                    (assign  (z) (var_ref compiler_temp@136)  (expression int u2i (swiz w (var_ref fastuidraw_uint_varying0) )) ) 
>                    (assign  (xyzw) (var_ref compiler_temp@135)  (txf uvec4 (var_ref fastuidraw_imageIndexAtlas)  (var_ref compiler_temp@136)  0  (constant int (0)) )) 
>                    (assign  (xy) (var_ref v_master_tile_texel_coord@132)  (swiz yz (var_ref master_coords) )) 
>                    (assign  (x) (var_ref v_index_layer@133)  (expression uint + (swiz z (var_ref compiler_temp@135) )(expression uint * (constant uint (256)) (swiz w (var_ref compiler_temp@135) )) ) ) 
>                    (assign  (xyzw) (var_ref v_tile_id@134)  (var_ref compiler_temp@135) ) 
>                    (assign  (x) (var_ref i@131)  (constant uint (1)) ) 
>                    (loop (
>                      (if (expression bool >= (var_ref i@131) (swiz x (var_ref fastuidraw_uint_varying1) )) (
>                        break
>                      )
>                      ())
>
>                      (declare (temporary ) vec2 compiler_temp@137)
>                      (declare (temporary ) uvec4 compiler_temp@138)
>                      (declare () vec2 texel_coordinate@139)
>                      (assign  (xy) (var_ref compiler_temp@137)  (expression vec2 + (var_ref v_master_tile_texel_coord@132) (expression vec2 neg (expression vec2 floor (var_ref v_master_tile_texel_coord@132) ) ) ) ) 
>                      (assign  (xy) (var_ref texel_coordinate@139)  (expression vec2 + (expression vec2 * (var_ref compiler_temp@137) (constant float (4.000000)) ) (expression vec2 * (expression vec2 u2f (swiz xy (var_ref v_tile_id@134) )) (constant float (4.000000)) ) ) ) 
>                      (declare (temporary ) ivec3 compiler_temp@140)
>                      (assign  (xy) (var_ref compiler_temp@140)  (expression ivec2 f2i (var_ref texel_coordinate@139) ) ) 
>                      (assign  (z) (var_ref compiler_temp@140)  (expression int u2i (var_ref v_index_layer@133) ) ) 
>                      (assign  (xyzw) (var_ref compiler_temp@138)  (txf uvec4 (var_ref fastuidraw_imageIndexAtlas)  (var_ref compiler_temp@140)  0  (constant int (0)) )) 
>                      (assign  (xy) (var_ref compiler_temp@137)  (var_ref texel_coordinate@139) ) 
>                      (assign  (xy) (var_ref v_master_tile_texel_coord@132)  (var_ref texel_coordinate@139) ) 
>                      (assign  (x) (var_ref v_index_layer@133)  (expression uint + (swiz z (var_ref compiler_temp@138) )(expression uint * (constant uint (256)) (swiz w (var_ref compiler_temp@138) )) ) ) 
>                      (assign  (xyzw) (var_ref v_tile_id@134)  (var_ref compiler_temp@138) ) 
>                      (assign  (x) (var_ref i@131)  (expression uint + (var_ref i@131) (constant uint (1)) ) ) 
>                    ))
>
>                    (declare (temporary ) vec2 compiler_temp@141)
>                    (assign  (xy) (var_ref compiler_temp@141)  (expression vec2 + (expression vec2 * (expression vec2 + (var_ref v_master_tile_texel_coord@132) (expression vec2 neg (expression vec2 floor (var_ref v_master_tile_texel_coord@132) ) ) ) (constant float (32.000000)) ) (expression vec2 * (expression vec2 u2f (swiz xy (var_ref v_tile_id@134) )) (constant float (32.000000)) ) ) ) 
>                    (if (expression bool && (expression bool && (expression bool && (expression bool >= (var_ref compiler_temp@126) (constant float (0.500000)) ) (expression bool >= (var_ref compiler_temp@129) (constant float (0.500000)) ) ) (expression bool >= (constant float (-0.500000)) (var_ref compiler_temp@125) ) ) (expression bool >= (constant float (-0.500000)) (var_ref compiler_temp@128) ) ) (
>                      (declare (temporary ) vec3 compiler_temp@142)
>                      (assign  (xy) (var_ref compiler_temp@142)  (expression vec2 * (var_ref compiler_temp@141) (constant vec2 (0.000122 0.000122)) ) ) 
>                      (assign  (z) (var_ref compiler_temp@142)  (expression float u2f (var_ref v_index_layer@133) ) ) 
>                      (assign  (xyzw) (var_ref image_color@123)  (txl vec4 (var_ref fastuidraw_imageAtlasLinear)  (var_ref compiler_temp@142)  0 1 () (constant float (0.000000)) )) 
>                    )
>                    (
>                      (declare (temporary ) vec3 compiler_temp@143)
>                      (assign  (xy) (var_ref compiler_temp@143)  (expression vec2 * (var_ref compiler_temp@141) (constant vec2 (0.000122 0.000122)) ) ) 
>                      (assign  (z) (var_ref compiler_temp@143)  (expression float u2f (var_ref v_index_layer@133) ) ) 
>                      (assign  (xyzw) (var_ref image_color@123)  (txl vec4 (var_ref fastuidraw_imageAtlasNearest)  (var_ref compiler_temp@143)  0 1 () (constant float (0.000000)) )) 
>                    ))
>
>                    (assign  (xyzw) (var_ref t10)  (var_ref image_color@123) ) 
>                    (declare () vec4 image_color@144)
>                    (declare (temporary ) vec2 compiler_temp@145)
>                    (assign  (xy) (var_ref compiler_temp@145)  (expression vec2 * (expression vec2 + (swiz xw (var_ref master_coords) )(expression vec2 neg (expression vec2 * (constant vec2 (4.000000 4.000000)) (expression vec2 floor (expression vec2 * (constant float (0.250000)) (swiz xw (var_ref master_coords) )) ) ) ) ) (swiz w (var_ref fastuidraw_float_flat_varying3) )) ) 
>                    (declare (temporary ) float compiler_temp@146)
>                    (declare (temporary ) float compiler_temp@147)
>                    (declare () float tile_coord@148)
>                    (assign  (x) (var_ref tile_coord@148)  (expression float + (swiz x (var_ref compiler_temp@145) )(expression float neg (expression float * (constant float (32.000000)) (expression float floor (expression float * (swiz x (var_ref compiler_temp@145) )(constant float (0.031250)) ) ) ) ) ) ) 
>                    (assign  (x) (var_ref compiler_temp@146)  (expression float neg (var_ref tile_coord@148) ) ) 
>                    (assign  (x) (var_ref compiler_temp@147)  (expression float + (constant float (31.000000)) (expression float neg (var_ref tile_coord@148) ) ) ) 
>                    (declare (temporary ) float compiler_temp@149)
>                    (declare (temporary ) float compiler_temp@150)
>                    (declare () float tile_coord@151)
>                    (assign  (x) (var_ref tile_coord@151)  (expression float + (swiz y (var_ref compiler_temp@145) )(expression float neg (expression float * (constant float (32.000000)) (expression float floor (expression float * (swiz y (var_ref compiler_temp@145) )(constant float (0.031250)) ) ) ) ) ) ) 
>                    (assign  (x) (var_ref compiler_temp@149)  (expression float neg (var_ref tile_coord@151) ) ) 
>                    (assign  (x) (var_ref compiler_temp@150)  (expression float + (constant float (31.000000)) (expression float neg (var_ref tile_coord@151) ) ) ) 
>                    (declare () uint i@152)
>                    (declare () vec2 v_master_tile_texel_coord@153)
>                    (declare () uint v_index_layer@154)
>                    (declare () uvec4 v_tile_id@155)
>                    (declare (temporary ) uvec4 compiler_temp@156)
>                    (declare (temporary ) ivec3 compiler_temp@157)
>                    (assign  (xy) (var_ref compiler_temp@157)  (expression ivec2 f2i (swiz xw (var_ref master_coords) )) ) 
>                    (assign  (z) (var_ref compiler_temp@157)  (expression int u2i (swiz w (var_ref fastuidraw_uint_varying0) )) ) 
>                    (assign  (xyzw) (var_ref compiler_temp@156)  (txf uvec4 (var_ref fastuidraw_imageIndexAtlas)  (var_ref compiler_temp@157)  0  (constant int (0)) )) 
>                    (assign  (xy) (var_ref v_master_tile_texel_coord@153)  (swiz xw (var_ref master_coords) )) 
>                    (assign  (x) (var_ref v_index_layer@154)  (expression uint + (swiz z (var_ref compiler_temp@156) )(expression uint * (constant uint (256)) (swiz w (var_ref compiler_temp@156) )) ) ) 
>                    (assign  (xyzw) (var_ref v_tile_id@155)  (var_ref compiler_temp@156) ) 
>                    (assign  (x) (var_ref i@152)  (constant uint (1)) ) 
>                    (loop (
>                      (if (expression bool >= (var_ref i@152) (swiz x (var_ref fastuidraw_uint_varying1) )) (
>                        break
>                      )
>                      ())
>
>                      (declare (temporary ) vec2 compiler_temp@158)
>                      (declare (temporary ) uvec4 compiler_temp@159)
>                      (declare () vec2 texel_coordinate@160)
>                      (assign  (xy) (var_ref compiler_temp@158)  (expression vec2 + (var_ref v_master_tile_texel_coord@153) (expression vec2 neg (expression vec2 floor (var_ref v_master_tile_texel_coord@153) ) ) ) ) 
>                      (assign  (xy) (var_ref texel_coordinate@160)  (expression vec2 + (expression vec2 * (var_ref compiler_temp@158) (constant float (4.000000)) ) (expression vec2 * (expression vec2 u2f (swiz xy (var_ref v_tile_id@155) )) (constant float (4.000000)) ) ) ) 
>                      (declare (temporary ) ivec3 compiler_temp@161)
>                      (assign  (xy) (var_ref compiler_temp@161)  (expression ivec2 f2i (var_ref texel_coordinate@160) ) ) 
>                      (assign  (z) (var_ref compiler_temp@161)  (expression int u2i (var_ref v_index_layer@154) ) ) 
>                      (assign  (xyzw) (var_ref compiler_temp@159)  (txf uvec4 (var_ref fastuidraw_imageIndexAtlas)  (var_ref compiler_temp@161)  0  (constant int (0)) )) 
>                      (assign  (xy) (var_ref compiler_temp@158)  (var_ref texel_coordinate@160) ) 
>                      (assign  (xy) (var_ref v_master_tile_texel_coord@153)  (var_ref texel_coordinate@160) ) 
>                      (assign  (x) (var_ref v_index_layer@154)  (expression uint + (swiz z (var_ref compiler_temp@159) )(expression uint * (constant uint (256)) (swiz w (var_ref compiler_temp@159) )) ) ) 
>                      (assign  (xyzw) (var_ref v_tile_id@155)  (var_ref compiler_temp@159) ) 
>                      (assign  (x) (var_ref i@152)  (expression uint + (var_ref i@152) (constant uint (1)) ) ) 
>                    ))
>
>                    (declare (temporary ) vec2 compiler_temp@162)
>                    (assign  (xy) (var_ref compiler_temp@162)  (expression vec2 + (expression vec2 * (expression vec2 + (var_ref v_master_tile_texel_coord@153) (expression vec2 neg (expression vec2 floor (var_ref v_master_tile_texel_coord@153) ) ) ) (constant float (32.000000)) ) (expression vec2 * (expression vec2 u2f (swiz xy (var_ref v_tile_id@155) )) (constant float (32.000000)) ) ) ) 
>                    (if (expression bool && (expression bool && (expression bool && (expression bool >= (var_ref compiler_temp@147) (constant float (0.500000)) ) (expression bool >= (var_ref compiler_temp@150) (constant float (0.500000)) ) ) (expression bool >= (constant float (-0.500000)) (var_ref compiler_temp@146) ) ) (expression bool >= (constant float (-0.500000)) (var_ref compiler_temp@149) ) ) (
>                      (declare (temporary ) vec3 compiler_temp@163)
>                      (assign  (xy) (var_ref compiler_temp@163)  (expression vec2 * (var_ref compiler_temp@162) (constant vec2 (0.000122 0.000122)) ) ) 
>                      (assign  (z) (var_ref compiler_temp@163)  (expression float u2f (var_ref v_index_layer@154) ) ) 
>                      (assign  (xyzw) (var_ref image_color@144)  (txl vec4 (var_ref fastuidraw_imageAtlasLinear)  (var_ref compiler_temp@163)  0 1 () (constant float (0.000000)) )) 
>                    )
>                    (
>                      (declare (temporary ) vec3 compiler_temp@164)
>                      (assign  (xy) (var_ref compiler_temp@164)  (expression vec2 * (var_ref compiler_temp@162) (constant vec2 (0.000122 0.000122)) ) ) 
>                      (assign  (z) (var_ref compiler_temp@164)  (expression float u2f (var_ref v_index_layer@154) ) ) 
>                      (assign  (xyzw) (var_ref image_color@144)  (txl vec4 (var_ref fastuidraw_imageAtlasNearest)  (var_ref compiler_temp@164)  0 1 () (constant float (0.000000)) )) 
>                    ))
>
>                    (assign  (xyzw) (var_ref t01)  (var_ref image_color@144) ) 
>                    (declare () vec4 image_color@165)
>                    (declare (temporary ) vec2 compiler_temp@166)
>                    (assign  (xy) (var_ref compiler_temp@166)  (expression vec2 * (expression vec2 + (swiz yw (var_ref master_coords) )(expression vec2 neg (expression vec2 * (constant vec2 (4.000000 4.000000)) (expression vec2 floor (expression vec2 * (constant float (0.250000)) (swiz yw (var_ref master_coords) )) ) ) ) ) (swiz w (var_ref fastuidraw_float_flat_varying3) )) ) 
>                    (declare (temporary ) float compiler_temp@167)
>                    (declare (temporary ) float compiler_temp@168)
>                    (declare () float tile_coord@169)
>                    (assign  (x) (var_ref tile_coord@169)  (expression float + (swiz x (var_ref compiler_temp@166) )(expression float neg (expression float * (constant float (32.000000)) (expression float floor (expression float * (swiz x (var_ref compiler_temp@166) )(constant float (0.031250)) ) ) ) ) ) ) 
>                    (assign  (x) (var_ref compiler_temp@167)  (expression float neg (var_ref tile_coord@169) ) ) 
>                    (assign  (x) (var_ref compiler_temp@168)  (expression float + (constant float (31.000000)) (expression float neg (var_ref tile_coord@169) ) ) ) 
>                    (declare (temporary ) float compiler_temp@170)
>                    (declare (temporary ) float compiler_temp@171)
>                    (declare () float tile_coord@172)
>                    (assign  (x) (var_ref tile_coord@172)  (expression float + (swiz y (var_ref compiler_temp@166) )(expression float neg (expression float * (constant float (32.000000)) (expression float floor (expression float * (swiz y (var_ref compiler_temp@166) )(constant float (0.031250)) ) ) ) ) ) ) 
>                    (assign  (x) (var_ref compiler_temp@170)  (expression float neg (var_ref tile_coord@172) ) ) 
>                    (assign  (x) (var_ref compiler_temp@171)  (expression float + (constant float (31.000000)) (expression float neg (var_ref tile_coord@172) ) ) ) 
>                    (declare () uint i@173)
>                    (declare () vec2 v_master_tile_texel_coord@174)
>                    (declare () uint v_index_layer@175)
>                    (declare () uvec4 v_tile_id@176)
>                    (declare (temporary ) uvec4 compiler_temp@177)
>                    (declare (temporary ) ivec3 compiler_temp@178)
>                    (assign  (xy) (var_ref compiler_temp@178)  (expression ivec2 f2i (swiz yw (var_ref master_coords) )) ) 
>                    (assign  (z) (var_ref compiler_temp@178)  (expression int u2i (swiz w (var_ref fastuidraw_uint_varying0) )) ) 
>                    (assign  (xyzw) (var_ref compiler_temp@177)  (txf uvec4 (var_ref fastuidraw_imageIndexAtlas)  (var_ref compiler_temp@178)  0  (constant int (0)) )) 
>                    (assign  (xy) (var_ref v_master_tile_texel_coord@174)  (swiz yw (var_ref master_coords) )) 
>                    (assign  (x) (var_ref v_index_layer@175)  (expression uint + (swiz z (var_ref compiler_temp@177) )(expression uint * (constant uint (256)) (swiz w (var_ref compiler_temp@177) )) ) ) 
>                    (assign  (xyzw) (var_ref v_tile_id@176)  (var_ref compiler_temp@177) ) 
>                    (assign  (x) (var_ref i@173)  (constant uint (1)) ) 
>                    (loop (
>                      (if (expression bool >= (var_ref i@173) (swiz x (var_ref fastuidraw_uint_varying1) )) (
>                        break
>                      )
>                      ())
>
>                      (declare (temporary ) vec2 compiler_temp@179)
>                      (declare (temporary ) uvec4 compiler_temp@180)
>                      (declare () vec2 texel_coordinate@181)
>                      (assign  (xy) (var_ref compiler_temp@179)  (expression vec2 + (var_ref v_master_tile_texel_coord@174) (expression vec2 neg (expression vec2 floor (var_ref v_master_tile_texel_coord@174) ) ) ) ) 
>                      (assign  (xy) (var_ref texel_coordinate@181)  (expression vec2 + (expression vec2 * (var_ref compiler_temp@179) (constant float (4.000000)) ) (expression vec2 * (expression vec2 u2f (swiz xy (var_ref v_tile_id@176) )) (constant float (4.000000)) ) ) ) 
>                      (declare (temporary ) ivec3 compiler_temp@182)
>                      (assign  (xy) (var_ref compiler_temp@182)  (expression ivec2 f2i (var_ref texel_coordinate@181) ) ) 
>                      (assign  (z) (var_ref compiler_temp@182)  (expression int u2i (var_ref v_index_layer@175) ) ) 
>                      (assign  (xyzw) (var_ref compiler_temp@180)  (txf uvec4 (var_ref fastuidraw_imageIndexAtlas)  (var_ref compiler_temp@182)  0  (constant int (0)) )) 
>                      (assign  (xy) (var_ref compiler_temp@179)  (var_ref texel_coordinate@181) ) 
>                      (assign  (xy) (var_ref v_master_tile_texel_coord@174)  (var_ref texel_coordinate@181) ) 
>                      (assign  (x) (var_ref v_index_layer@175)  (expression uint + (swiz z (var_ref compiler_temp@180) )(expression uint * (constant uint (256)) (swiz w (var_ref compiler_temp@180) )) ) ) 
>                      (assign  (xyzw) (var_ref v_tile_id@176)  (var_ref compiler_temp@180) ) 
>                      (assign  (x) (var_ref i@173)  (expression uint + (var_ref i@173) (constant uint (1)) ) ) 
>                    ))
>
>                    (declare (temporary ) vec2 compiler_temp@183)
>                    (assign  (xy) (var_ref compiler_temp@183)  (expression vec2 + (expression vec2 * (expression vec2 + (var_ref v_master_tile_texel_coord@174) (expression vec2 neg (expression vec2 floor (var_ref v_master_tile_texel_coord@174) ) ) ) (constant float (32.000000)) ) (expression vec2 * (expression vec2 u2f (swiz xy (var_ref v_tile_id@176) )) (constant float (32.000000)) ) ) ) 
>                    (if (expression bool && (expression bool && (expression bool && (expression bool >= (var_ref compiler_temp@168) (constant float (0.500000)) ) (expression bool >= (var_ref compiler_temp@171) (constant float (0.500000)) ) ) (expression bool >= (constant float (-0.500000)) (var_ref compiler_temp@167) ) ) (expression bool >= (constant float (-0.500000)) (var_ref compiler_temp@170) ) ) (
>                      (declare (temporary ) vec3 compiler_temp@184)
>                      (assign  (xy) (var_ref compiler_temp@184)  (expression vec2 * (var_ref compiler_temp@183) (constant vec2 (0.000122 0.000122)) ) ) 
>                      (assign  (z) (var_ref compiler_temp@184)  (expression float u2f (var_ref v_index_layer@175) ) ) 
>                      (assign  (xyzw) (var_ref image_color@165)  (txl vec4 (var_ref fastuidraw_imageAtlasLinear)  (var_ref compiler_temp@184)  0 1 () (constant float (0.000000)) )) 
>                    )
>                    (
>                      (declare (temporary ) vec3 compiler_temp@185)
>                      (assign  (xy) (var_ref compiler_temp@185)  (expression vec2 * (var_ref compiler_temp@183) (constant vec2 (0.000122 0.000122)) ) ) 
>                      (assign  (z) (var_ref compiler_temp@185)  (expression float u2f (var_ref v_index_layer@175) ) ) 
>                      (assign  (xyzw) (var_ref image_color@165)  (txl vec4 (var_ref fastuidraw_imageAtlasNearest)  (var_ref compiler_temp@185)  0 1 () (constant float (0.000000)) )) 
>                    ))
>
>                    (assign  (xyzw) (var_ref t11)  (var_ref image_color@165) ) 
>                  ))
>
>                  (assign  (xyzw) (var_ref image_color@32)  (expression vec4 lrp (expression vec4 lrp (var_ref t00) (var_ref t10) (swiz x (var_ref linear_weight) )) (expression vec4 lrp (var_ref t01) (var_ref t11) (swiz x (var_ref linear_weight) )) (swiz y (var_ref linear_weight) )) ) 
>                ))
>
>              ))
>
>              (assign  (xyzw) (var_ref image_color)  (var_ref image_color@32) ) 
>            )
>            (
>              (if (expression bool == (var_ref compiler_temp@29) (constant uint (1)) ) (
>                (assign  (xyzw) (var_ref image_color)  (constant vec4 (1.000000 1.000000 1.000000 1.000000)) ) 
>              )
>              (
>                (declare (temporary ) vec2 texel_coord@186)
>                (declare () vec4 image_color@187)
>                (assign  (xy) (var_ref texel_coord@186)  (expression vec2 + (var_ref q@28) (swiz zw (var_ref fastuidraw_float_flat_varying2) )) ) 
>                (if (expression bool == (var_ref compiler_temp@30) (constant uint (1)) ) (
>                  (declare () int L)
>                  (assign  (x) (var_ref L)  (expression int f2i (expression float ceil (var_ref lod) ) ) ) 
>                  (assign  (xyzw) (var_ref image_color@187)  (txf vec4 (array_ref (var_ref fastuidraw_external_texture) (constant int (0)) )  (expression ivec2 f2i (expression vec2 * (var_ref texel_coord@186) (expression float rcp (expression float i2f (expression int << (constant int (1)) (var_ref L) ) ) ) ) )  0  (var_ref L) )) 
>                )
>                (
>                  (if (expression bool || (expression bool == (var_ref compiler_temp@30) (constant uint (2)) ) (expression bool < (constant float (0.500000)) (var_ref lod) ) ) (
>                    (assign  (xyzw) (var_ref image_color@187)  (txl vec4 (array_ref (var_ref fastuidraw_external_texture) (constant int (0)) )  (expression vec2 * (var_ref texel_coord@186) (expression vec2 rcp (expression vec2 i2f (txs ivec2 (array_ref (var_ref fastuidraw_external_texture) (constant int (0)) )   (constant int (0)) )) ) )  0 1 () (var_ref lod) )) 
>                  )
>                  (
>                    (declare (temporary ) vec2 compiler_temp@188)
>                    (declare () vec4 texture_coords@189)
>                    (declare () vec4 corner_coords@190)
>                    (declare () vec2 linear_weight@191)
>                    (assign  (xy) (var_ref compiler_temp@188)  (expression vec2 + (var_ref texel_coord@186) (constant vec2 (-0.500000 -0.500000)) ) ) 
>                    (declare (temporary ) vec2 compiler_temp@192)
>                    (assign  (xy) (var_ref compiler_temp@192)  (expression vec2 fract (var_ref compiler_temp@188) ) ) 
>                    (assign  (xy) (var_ref compiler_temp@188)  (expression vec2 + (var_ref compiler_temp@188) (expression vec2 neg (var_ref compiler_temp@192) ) ) ) 
>                    (declare (temporary ) vec4 compiler_temp@193)
>                    (declare () vec4 w@194)
>                    (declare (temporary ) float compiler_temp@195)
>                    (assign  (x) (var_ref compiler_temp@195)  (expression float * (swiz x (var_ref compiler_temp@192) )(swiz x (var_ref compiler_temp@192) )) ) 
>                    (declare (temporary ) float compiler_temp@196)
>                    (assign  (x) (var_ref compiler_temp@196)  (expression float * (var_ref compiler_temp@195) (swiz x (var_ref compiler_temp@192) )) ) 
>                    (declare (temporary ) float compiler_temp@197)
>                    (assign  (x) (var_ref compiler_temp@197)  (expression float + (constant float (1.000000)) (expression float neg (swiz x (var_ref compiler_temp@192) )) ) ) 
>                    (declare (temporary ) float compiler_temp@198)
>                    (assign  (x) (var_ref compiler_temp@198)  (expression float * (var_ref compiler_temp@197) (var_ref compiler_temp@197) ) ) 
>                    (declare (temporary ) float compiler_temp@199)
>                    (assign  (x) (var_ref compiler_temp@199)  (expression float * (var_ref compiler_temp@198) (var_ref compiler_temp@197) ) ) 
>                    (assign  (x) (var_ref w@194)  (var_ref compiler_temp@199) ) 
>                    (assign  (y) (var_ref w@194)  (expression float + (expression float + (expression float * (constant float (3.000000)) (var_ref compiler_temp@196) ) (expression float neg (expression float * (constant float (6.000000)) (var_ref compiler_temp@195) ) ) ) (constant float (4.000000)) ) ) 
>                    (assign  (z) (var_ref w@194)  (expression float + (expression float + (expression float * (constant float (3.000000)) (var_ref compiler_temp@199) ) (expression float neg (expression float * (constant float (6.000000)) (var_ref compiler_temp@198) ) ) ) (constant float (4.000000)) ) ) 
>                    (assign  (w) (var_ref w@194)  (var_ref compiler_temp@196) ) 
>                    (assign  (xyzw) (var_ref compiler_temp@193)  (expression vec4 * (var_ref w@194) (expression float rcp (constant float (6.000000)) ) ) ) 
>                    (declare (temporary ) vec4 compiler_temp@200)
>                    (declare () vec4 w@201)
>                    (declare (temporary ) float compiler_temp@202)
>                    (assign  (x) (var_ref compiler_temp@202)  (expression float * (swiz y (var_ref compiler_temp@192) )(swiz y (var_ref compiler_temp@192) )) ) 
>                    (declare (temporary ) float compiler_temp@203)
>                    (assign  (x) (var_ref compiler_temp@203)  (expression float * (var_ref compiler_temp@202) (swiz y (var_ref compiler_temp@192) )) ) 
>                    (declare (temporary ) float compiler_temp@204)
>                    (assign  (x) (var_ref compiler_temp@204)  (expression float + (constant float (1.000000)) (expression float neg (swiz y (var_ref compiler_temp@192) )) ) ) 
>                    (declare (temporary ) float compiler_temp@205)
>                    (assign  (x) (var_ref compiler_temp@205)  (expression float * (var_ref compiler_temp@204) (var_ref compiler_temp@204) ) ) 
>                    (declare (temporary ) float compiler_temp@206)
>                    (assign  (x) (var_ref compiler_temp@206)  (expression float * (var_ref compiler_temp@205) (var_ref compiler_temp@204) ) ) 
>                    (assign  (x) (var_ref w@201)  (var_ref compiler_temp@206) ) 
>                    (assign  (y) (var_ref w@201)  (expression float + (expression float + (expression float * (constant float (3.000000)) (var_ref compiler_temp@203) ) (expression float neg (expression float * (constant float (6.000000)) (var_ref compiler_temp@202) ) ) ) (constant float (4.000000)) ) ) 
>                    (assign  (z) (var_ref w@201)  (expression float + (expression float + (expression float * (constant float (3.000000)) (var_ref compiler_temp@206) ) (expression float neg (expression float * (constant float (6.000000)) (var_ref compiler_temp@205) ) ) ) (constant float (4.000000)) ) ) 
>                    (assign  (w) (var_ref w@201)  (var_ref compiler_temp@203) ) 
>                    (assign  (xyzw) (var_ref compiler_temp@200)  (expression vec4 * (var_ref w@201) (expression float rcp (constant float (6.000000)) ) ) ) 
>                    (assign  (xz) (var_ref corner_coords@190)  (expression vec2 + (var_ref compiler_temp@188) (constant vec2 (-0.500000 -0.500000)) ) ) 
>                    (assign  (yw) (var_ref corner_coords@190)  (expression vec2 + (var_ref compiler_temp@188) (constant vec2 (1.500000 1.500000)) ) ) 
>                    (declare (temporary ) vec4 compiler_temp@207)
>                    (assign  (x) (var_ref compiler_temp@207)  (expression float + (swiz x (var_ref compiler_temp@193) )(swiz y (var_ref compiler_temp@193) )) ) 
>                    (assign  (y) (var_ref compiler_temp@207)  (expression float + (swiz z (var_ref compiler_temp@193) )(swiz w (var_ref compiler_temp@193) )) ) 
>                    (assign  (z) (var_ref compiler_temp@207)  (expression float + (swiz x (var_ref compiler_temp@200) )(swiz y (var_ref compiler_temp@200) )) ) 
>                    (assign  (w) (var_ref compiler_temp@207)  (expression float + (swiz z (var_ref compiler_temp@200) )(swiz w (var_ref compiler_temp@200) )) ) 
>                    (declare (temporary ) vec4 compiler_temp@208)
>                    (assign  (xy) (var_ref compiler_temp@208)  (swiz yw (var_ref compiler_temp@193) )) 
>                    (assign  (zw) (var_ref compiler_temp@208)  (swiz yw (var_ref compiler_temp@200) )) 
>                    (assign  (xyzw) (var_ref texture_coords@189)  (expression vec4 + (var_ref corner_coords@190) (expression vec4 * (var_ref compiler_temp@208) (expression vec4 rcp (var_ref compiler_temp@207) ) ) ) ) 
>                    (assign  (xyzw) (var_ref texture_coords@189)  (expression vec4 * (var_ref texture_coords@189) (swiz xyxy (expression vec2 rcp (expression vec2 i2f (txs ivec2 (array_ref (var_ref fastuidraw_external_texture) (constant int (0)) )   (constant int (0)) )) ) )) ) 
>                    (assign  (x) (var_ref linear_weight@191)  (expression float * (swiz y (var_ref compiler_temp@207) )(expression float rcp (expression float + (swiz x (var_ref compiler_temp@207) )(swiz y (var_ref compiler_temp@207) )) ) ) ) 
>                    (assign  (y) (var_ref linear_weight@191)  (expression float * (swiz w (var_ref compiler_temp@207) )(expression float rcp (expression float + (swiz z (var_ref compiler_temp@207) )(swiz w (var_ref compiler_temp@207) )) ) ) ) 
>                    (assign  (xyzw) (var_ref image_color@187)  (expression vec4 lrp (expression vec4 lrp (txl vec4 (array_ref (var_ref fastuidraw_external_texture) (constant int (0)) )  (swiz xz (var_ref texture_coords@189) ) 0 1 () (constant float (0.000000)) )(txl vec4 (array_ref (var_ref fastuidraw_external_texture) (constant int (0)) )  (swiz yz (var_ref texture_coords@189) ) 0 1 () (constant float (0.000000)) )(swiz x (var_ref linear_weight@191) )) (expression vec4 lrp (txl vec4 (array_ref (var_ref fastuidraw_external_texture) (constant int (0)) )  (swiz xw (var_ref texture_coords@189) ) 0 1 () (constant float (0.000000)) )(txl vec4 (array_ref (var_ref fastuidraw_external_texture) (constant int (0)) )  (swiz yw (var_ref texture_coords@189) ) 0 1 () (constant float (0.000000)) )(swiz x (var_ref linear_weight@191) )) (swiz y (var_ref linear_weight@191) )) ) 
>                  ))
>
>                ))
>
>                (assign  (xyzw) (var_ref image_color)  (var_ref image_color@187) ) 
>              ))
>
>            ))
>
>            (if (expression bool == (expression uint & (swiz y (var_ref fastuidraw_uint_varying2) )(constant uint (16777216)) ) (constant uint (0)) ) (
>              (assign  (xyz) (var_ref image_color)  (expression vec3 * (swiz xyz (var_ref image_color) )(swiz w (var_ref image_color) )) ) 
>            )
>            ())
>
>            (assign  (xyzw) (var_ref return_value)  (expression vec4 * (var_ref return_value) (var_ref image_color) ) ) 
>          )
>          ())
>
>          (assign  (xyzw) (var_ref b)  (var_ref return_value) ) 
>        )
>        (
>          (declare () vec4 p@209)
>          (assign  (xyzw) (var_ref b)  (var_ref p@209) ) 
>        ))
>
>        (declare () vec4 p@210)
>        (if (expression bool && (expression bool >= (swiz y (var_ref fastuidraw_uint_varying1) )(constant uint (2)) ) (expression bool < (swiz y (var_ref fastuidraw_uint_varying1) )(constant uint (6)) ) ) (
>          (assign  (xyzw) (var_ref p@210)  (swiz xxxx (txf vec4 (var_ref fastuidraw_deferred_coverage_buffer)  (expression ivec2 + (expression ivec2 f2i (swiz xy (var_ref gl_FragCoord) )) (var_ref fastuidraw_deferred_buffer_offset) )  0  (constant int (0)) ))) 
>        )
>        (
>          (if (expression bool && (expression bool >= (swiz y (var_ref fastuidraw_uint_varying1) )(constant uint (10)) ) (expression bool < (swiz y (var_ref fastuidraw_uint_varying1) )(constant uint (14)) ) ) (
>            (assign  (xyzw) (var_ref p@210)  (swiz xxxx (txf vec4 (var_ref fastuidraw_deferred_coverage_buffer)  (expression ivec2 + (expression ivec2 f2i (swiz xy (var_ref gl_FragCoord) )) (var_ref fastuidraw_deferred_buffer_offset) )  0  (constant int (0)) ))) 
>          )
>          (
>            (if (expression bool == (swiz y (var_ref fastuidraw_uint_varying1) )(constant uint (1)) ) (
>              (assign  (xyzw) (var_ref p@210)  (constant vec4 (1.000000 1.000000 1.000000 1.000000)) ) 
>            )
>            (
>              (if (expression bool == (swiz y (var_ref fastuidraw_uint_varying1) )(constant uint (18)) ) (
>                (assign  (xyzw) (var_ref p@210)  (constant vec4 (1.000000 1.000000 1.000000 1.000000)) ) 
>              )
>              (
>                (if (expression bool == (swiz y (var_ref fastuidraw_uint_varying1) )(constant uint (19)) ) (
>                  (assign  (xyzw) (var_ref p@210)  (swiz xxxx (txf vec4 (var_ref fastuidraw_deferred_coverage_buffer)  (expression ivec2 + (expression ivec2 f2i (swiz xy (var_ref gl_FragCoord) )) (var_ref fastuidraw_deferred_buffer_offset) )  0  (constant int (0)) ))) 
>                )
>                (
>                  (if (expression bool == (swiz y (var_ref fastuidraw_uint_varying1) )(constant uint (20)) ) (
>                    (declare () vec2 mixer)
>                    (declare () ivec2 coord11)
>                    (declare () ivec2 coord10)
>                    (declare () ivec2 coord01)
>                    (declare () ivec2 coord00)
>                    (declare (temporary ) uvec2 compiler_temp@211)
>                    (assign  (x) (var_ref compiler_temp@211)  (expression uint f2u (swiz w (var_ref fastuidraw_float_smooth_varying0) )) ) 
>                    (assign  (y) (var_ref compiler_temp@211)  (expression uint f2u (swiz z (var_ref fastuidraw_float_smooth_varying0) )) ) 
>                    (declare (temporary ) vec2 compiler_temp@212)
>                    (assign  (xy) (var_ref compiler_temp@212)  (expression vec2 + (swiz xy (var_ref fastuidraw_float_smooth_varying0) )(constant vec2 (0.500000 0.500000)) ) ) 
>                    (assign  (xy) (var_ref coord00)  (expression ivec2 + (expression ivec2 f2i (var_ref compiler_temp@212) ) (constant ivec2 (-1 -1)) ) ) 
>                    (assign  (xy) (var_ref coord10)  (expression ivec2 + (var_ref coord00) (constant ivec2 (1 0)) ) ) 
>                    (assign  (xy) (var_ref coord01)  (expression ivec2 + (var_ref coord00) (constant ivec2 (0 1)) ) ) 
>                    (assign  (xy) (var_ref coord11)  (expression ivec2 + (var_ref coord00) (constant ivec2 (1 1)) ) ) 
>                    (assign  (xy) (var_ref mixer)  (expression vec2 + (var_ref compiler_temp@212) (expression vec2 neg (expression vec2 i2f (expression ivec2 f2i (var_ref compiler_temp@212) ) ) ) ) ) 
>                    (declare (temporary ) uint compiler_temp@213)
>                    (declare () uint block)
>                    (declare () uint y)
>                    (declare () uint x)
>                    (if (expression bool || (expression bool < (swiz x (var_ref coord00) )(constant int (0)) ) (expression bool < (swiz y (var_ref coord00) )(constant int (0)) ) ) (
>                      (assign  (x) (var_ref compiler_temp@213)  (constant uint (0)) ) 
>                    )
>                    (
>                      (assign  (x) (var_ref x)  (expression uint i2u (swiz x (var_ref coord00) )) ) 
>                      (assign  (x) (var_ref y)  (expression uint i2u (swiz y (var_ref coord00) )) ) 
>                      (if (expression bool || (expression bool >= (var_ref x) (swiz x (var_ref compiler_temp@211) )) (expression bool >= (var_ref y) (swiz y (var_ref compiler_temp@211) )) ) (
>                        (assign  (x) (var_ref compiler_temp@213)  (constant uint (0)) ) 
>                      )
>                      (
>                        (assign  (x) (var_ref block)  (array_ref (var_ref fastuidraw_glyphDataStore_data) (expression int u2i (expression uint + (expression uint + (swiz x (var_ref fastuidraw_uint_varying0) )(expression uint >> (var_ref x) (constant uint (1)) ) ) (expression uint * (expression uint >> (var_ref y) (constant uint (1)) ) (expression uint >> (expression uint + (swiz x (var_ref compiler_temp@211) )(constant uint (1)) ) (constant uint (1)) ) ) ) ) ) ) 
>                        (declare (temporary ) uint compiler_temp@214)
>                        (if (expression bool != (expression uint & (var_ref x) (constant uint (1)) ) (constant uint (0)) ) (
>                          (assign  (x) (var_ref compiler_temp@214)  (constant uint (8)) ) 
>                        )
>                        (
>                          (assign  (x) (var_ref compiler_temp@214)  (constant uint (0)) ) 
>                        ))
>
>                        (declare (temporary ) uint compiler_temp@215)
>                        (if (expression bool != (expression uint & (var_ref y) (constant uint (1)) ) (constant uint (0)) ) (
>                          (assign  (x) (var_ref compiler_temp@215)  (constant uint (16)) ) 
>                        )
>                        (
>                          (assign  (x) (var_ref compiler_temp@215)  (constant uint (0)) ) 
>                        ))
>
>                        (assign  (x) (var_ref compiler_temp@213)  (expression uint >> (expression uint << (var_ref block) (expression uint + (constant uint (24)) (expression uint neg (expression uint + (var_ref compiler_temp@214) (var_ref compiler_temp@215) ) ) ) ) (constant uint (24)) ) ) 
>                      ))
>
>                    ))
>
>                    (declare (temporary ) uint compiler_temp@216)
>                    (declare () uint block@217)
>                    (declare () uint y@218)
>                    (declare () uint x@219)
>                    (if (expression bool || (expression bool < (swiz x (var_ref coord01) )(constant int (0)) ) (expression bool < (swiz y (var_ref coord01) )(constant int (0)) ) ) (
>                      (assign  (x) (var_ref compiler_temp@216)  (constant uint (0)) ) 
>                    )
>                    (
>                      (assign  (x) (var_ref x@219)  (expression uint i2u (swiz x (var_ref coord01) )) ) 
>                      (assign  (x) (var_ref y@218)  (expression uint i2u (swiz y (var_ref coord01) )) ) 
>                      (if (expression bool || (expression bool >= (var_ref x@219) (swiz x (var_ref compiler_temp@211) )) (expression bool >= (var_ref y@218) (swiz y (var_ref compiler_temp@211) )) ) (
>                        (assign  (x) (var_ref compiler_temp@216)  (constant uint (0)) ) 
>                      )
>                      (
>                        (assign  (x) (var_ref block@217)  (array_ref (var_ref fastuidraw_glyphDataStore_data) (expression int u2i (expression uint + (expression uint + (swiz x (var_ref fastuidraw_uint_varying0) )(expression uint >> (var_ref x@219) (constant uint (1)) ) ) (expression uint * (expression uint >> (var_ref y@218) (constant uint (1)) ) (expression uint >> (expression uint + (swiz x (var_ref compiler_temp@211) )(constant uint (1)) ) (constant uint (1)) ) ) ) ) ) ) 
>                        (declare (temporary ) uint compiler_temp@220)
>                        (if (expression bool != (expression uint & (var_ref x@219) (constant uint (1)) ) (constant uint (0)) ) (
>                          (assign  (x) (var_ref compiler_temp@220)  (constant uint (8)) ) 
>                        )
>                        (
>                          (assign  (x) (var_ref compiler_temp@220)  (constant uint (0)) ) 
>                        ))
>
>                        (declare (temporary ) uint compiler_temp@221)
>                        (if (expression bool != (expression uint & (var_ref y@218) (constant uint (1)) ) (constant uint (0)) ) (
>                          (assign  (x) (var_ref compiler_temp@221)  (constant uint (16)) ) 
>                        )
>                        (
>                          (assign  (x) (var_ref compiler_temp@221)  (constant uint (0)) ) 
>                        ))
>
>                        (assign  (x) (var_ref compiler_temp@216)  (expression uint >> (expression uint << (var_ref block@217) (expression uint + (constant uint (24)) (expression uint neg (expression uint + (var_ref compiler_temp@220) (var_ref compiler_temp@221) ) ) ) ) (constant uint (24)) ) ) 
>                      ))
>
>                    ))
>
>                    (declare (temporary ) uint compiler_temp@222)
>                    (declare () uint block@223)
>                    (declare () uint y@224)
>                    (declare () uint x@225)
>                    (if (expression bool || (expression bool < (swiz x (var_ref coord10) )(constant int (0)) ) (expression bool < (swiz y (var_ref coord10) )(constant int (0)) ) ) (
>                      (assign  (x) (var_ref compiler_temp@222)  (constant uint (0)) ) 
>                    )
>                    (
>                      (assign  (x) (var_ref x@225)  (expression uint i2u (swiz x (var_ref coord10) )) ) 
>                      (assign  (x) (var_ref y@224)  (expression uint i2u (swiz y (var_ref coord10) )) ) 
>                      (if (expression bool || (expression bool >= (var_ref x@225) (swiz x (var_ref compiler_temp@211) )) (expression bool >= (var_ref y@224) (swiz y (var_ref compiler_temp@211) )) ) (
>                        (assign  (x) (var_ref compiler_temp@222)  (constant uint (0)) ) 
>                      )
>                      (
>                        (assign  (x) (var_ref block@223)  (array_ref (var_ref fastuidraw_glyphDataStore_data) (expression int u2i (expression uint + (expression uint + (swiz x (var_ref fastuidraw_uint_varying0) )(expression uint >> (var_ref x@225) (constant uint (1)) ) ) (expression uint * (expression uint >> (var_ref y@224) (constant uint (1)) ) (expression uint >> (expression uint + (swiz x (var_ref compiler_temp@211) )(constant uint (1)) ) (constant uint (1)) ) ) ) ) ) ) 
>                        (declare (temporary ) uint compiler_temp@226)
>                        (if (expression bool != (expression uint & (var_ref x@225) (constant uint (1)) ) (constant uint (0)) ) (
>                          (assign  (x) (var_ref compiler_temp@226)  (constant uint (8)) ) 
>                        )
>                        (
>                          (assign  (x) (var_ref compiler_temp@226)  (constant uint (0)) ) 
>                        ))
>
>                        (declare (temporary ) uint compiler_temp@227)
>                        (if (expression bool != (expression uint & (var_ref y@224) (constant uint (1)) ) (constant uint (0)) ) (
>                          (assign  (x) (var_ref compiler_temp@227)  (constant uint (16)) ) 
>                        )
>                        (
>                          (assign  (x) (var_ref compiler_temp@227)  (constant uint (0)) ) 
>                        ))
>
>                        (assign  (x) (var_ref compiler_temp@222)  (expression uint >> (expression uint << (var_ref block@223) (expression uint + (constant uint (24)) (expression uint neg (expression uint + (var_ref compiler_temp@226) (var_ref compiler_temp@227) ) ) ) ) (constant uint (24)) ) ) 
>                      ))
>
>                    ))
>
>                    (declare (temporary ) uint compiler_temp@228)
>                    (declare () uint block@229)
>                    (declare () uint y@230)
>                    (declare () uint x@231)
>                    (if (expression bool || (expression bool < (swiz x (var_ref coord11) )(constant int (0)) ) (expression bool < (swiz y (var_ref coord11) )(constant int (0)) ) ) (
>                      (assign  (x) (var_ref compiler_temp@228)  (constant uint (0)) ) 
>                    )
>                    (
>                      (assign  (x) (var_ref x@231)  (expression uint i2u (swiz x (var_ref coord11) )) ) 
>                      (assign  (x) (var_ref y@230)  (expression uint i2u (swiz y (var_ref coord11) )) ) 
>                      (if (expression bool || (expression bool >= (var_ref x@231) (swiz x (var_ref compiler_temp@211) )) (expression bool >= (var_ref y@230) (swiz y (var_ref compiler_temp@211) )) ) (
>                        (assign  (x) (var_ref compiler_temp@228)  (constant uint (0)) ) 
>                      )
>                      (
>                        (assign  (x) (var_ref block@229)  (array_ref (var_ref fastuidraw_glyphDataStore_data) (expression int u2i (expression uint + (expression uint + (swiz x (var_ref fastuidraw_uint_varying0) )(expression uint >> (var_ref x@231) (constant uint (1)) ) ) (expression uint * (expression uint >> (var_ref y@230) (constant uint (1)) ) (expression uint >> (expression uint + (swiz x (var_ref compiler_temp@211) )(constant uint (1)) ) (constant uint (1)) ) ) ) ) ) ) 
>                        (declare (temporary ) uint compiler_temp@232)
>                        (if (expression bool != (expression uint & (var_ref x@231) (constant uint (1)) ) (constant uint (0)) ) (
>                          (assign  (x) (var_ref compiler_temp@232)  (constant uint (8)) ) 
>                        )
>                        (
>                          (assign  (x) (var_ref compiler_temp@232)  (constant uint (0)) ) 
>                        ))
>
>                        (declare (temporary ) uint compiler_temp@233)
>                        (if (expression bool != (expression uint & (var_ref y@230) (constant uint (1)) ) (constant uint (0)) ) (
>                          (assign  (x) (var_ref compiler_temp@233)  (constant uint (16)) ) 
>                        )
>                        (
>                          (assign  (x) (var_ref compiler_temp@233)  (constant uint (0)) ) 
>                        ))
>
>                        (assign  (x) (var_ref compiler_temp@228)  (expression uint >> (expression uint << (var_ref block@229) (expression uint + (constant uint (24)) (expression uint neg (expression uint + (var_ref compiler_temp@232) (var_ref compiler_temp@233) ) ) ) ) (constant uint (24)) ) ) 
>                      ))
>
>                    ))
>
>                    (assign  (xyzw) (var_ref p@210)  (swiz xxxx (expression float * (expression float lrp (expression float lrp (expression float u2f (var_ref compiler_temp@213) ) (expression float u2f (var_ref compiler_temp@216) ) (swiz y (var_ref mixer) )) (expression float lrp (expression float u2f (var_ref compiler_temp@222) ) (expression float u2f (var_ref compiler_temp@228) ) (swiz y (var_ref mixer) )) (swiz x (var_ref mixer) )) (expression float rcp (constant float (255.000000)) ) ) )) 
>                  )
>                  (
>                    (if (expression bool == (swiz y (var_ref fastuidraw_uint_varying1) )(constant uint (21)) ) (
>                      (declare () vec2 mixer@234)
>                      (declare () ivec2 coord11@235)
>                      (declare () ivec2 coord10@236)
>                      (declare () ivec2 coord01@237)
>                      (declare () ivec2 coord00@238)
>                      (declare () float dist)
>                      (declare (temporary ) uvec2 compiler_temp@239)
>                      (assign  (x) (var_ref compiler_temp@239)  (expression uint f2u (swiz w (var_ref fastuidraw_float_smooth_varying0) )) ) 
>                      (assign  (y) (var_ref compiler_temp@239)  (expression uint f2u (swiz z (var_ref fastuidraw_float_smooth_varying0) )) ) 
>                      (declare (temporary ) vec2 compiler_temp@240)
>                      (assign  (xy) (var_ref compiler_temp@240)  (expression vec2 + (swiz xy (var_ref fastuidraw_float_smooth_varying0) )(constant vec2 (0.500000 0.500000)) ) ) 
>                      (assign  (xy) (var_ref coord00@238)  (expression ivec2 + (expression ivec2 f2i (var_ref compiler_temp@240) ) (constant ivec2 (-1 -1)) ) ) 
>                      (assign  (xy) (var_ref coord10@236)  (expression ivec2 + (var_ref coord00@238) (constant ivec2 (1 0)) ) ) 
>                      (assign  (xy) (var_ref coord01@237)  (expression ivec2 + (var_ref coord00@238) (constant ivec2 (0 1)) ) ) 
>                      (assign  (xy) (var_ref coord11@235)  (expression ivec2 + (var_ref coord00@238) (constant ivec2 (1 1)) ) ) 
>                      (assign  (xy) (var_ref mixer@234)  (expression vec2 + (var_ref compiler_temp@240) (expression vec2 neg (expression vec2 i2f (expression ivec2 f2i (var_ref compiler_temp@240) ) ) ) ) ) 
>                      (declare (temporary ) uint compiler_temp@241)
>                      (declare () uint block@242)
>                      (declare () uint y@243)
>                      (declare () uint x@244)
>                      (if (expression bool || (expression bool < (swiz x (var_ref coord00@238) )(constant int (0)) ) (expression bool < (swiz y (var_ref coord00@238) )(constant int (0)) ) ) (
>                        (assign  (x) (var_ref compiler_temp@241)  (constant uint (0)) ) 
>                      )
>                      (
>                        (assign  (x) (var_ref x@244)  (expression uint i2u (swiz x (var_ref coord00@238) )) ) 
>                        (assign  (x) (var_ref y@243)  (expression uint i2u (swiz y (var_ref coord00@238) )) ) 
>                        (if (expression bool || (expression bool >= (var_ref x@244) (swiz x (var_ref compiler_temp@239) )) (expression bool >= (var_ref y@243) (swiz y (var_ref compiler_temp@239) )) ) (
>                          (assign  (x) (var_ref compiler_temp@241)  (constant uint (0)) ) 
>                        )
>                        (
>                          (assign  (x) (var_ref block@242)  (array_ref (var_ref fastuidraw_glyphDataStore_data) (expression int u2i (expression uint + (expression uint + (swiz x (var_ref fastuidraw_uint_varying0) )(expression uint >> (var_ref x@244) (constant uint (1)) ) ) (expression uint * (expression uint >> (var_ref y@243) (constant uint (1)) ) (expression uint >> (expression uint + (swiz x (var_ref compiler_temp@239) )(constant uint (1)) ) (constant uint (1)) ) ) ) ) ) ) 
>                          (declare (temporary ) uint compiler_temp@245)
>                          (if (expression bool != (expression uint & (var_ref x@244) (constant uint (1)) ) (constant uint (0)) ) (
>                            (assign  (x) (var_ref compiler_temp@245)  (constant uint (8)) ) 
>                          )
>                          (
>                            (assign  (x) (var_ref compiler_temp@245)  (constant uint (0)) ) 
>                          ))
>
>                          (declare (temporary ) uint compiler_temp@246)
>                          (if (expression bool != (expression uint & (var_ref y@243) (constant uint (1)) ) (constant uint (0)) ) (
>                            (assign  (x) (var_ref compiler_temp@246)  (constant uint (16)) ) 
>                          )
>                          (
>                            (assign  (x) (var_ref compiler_temp@246)  (constant uint (0)) ) 
>                          ))
>
>                          (assign  (x) (var_ref compiler_temp@241)  (expression uint >> (expression uint << (var_ref block@242) (expression uint + (constant uint (24)) (expression uint neg (expression uint + (var_ref compiler_temp@245) (var_ref compiler_temp@246) ) ) ) ) (constant uint (24)) ) ) 
>                        ))
>
>                      ))
>
>                      (declare (temporary ) uint compiler_temp@247)
>                      (declare () uint block@248)
>                      (declare () uint y@249)
>                      (declare () uint x@250)
>                      (if (expression bool || (expression bool < (swiz x (var_ref coord01@237) )(constant int (0)) ) (expression bool < (swiz y (var_ref coord01@237) )(constant int (0)) ) ) (
>                        (assign  (x) (var_ref compiler_temp@247)  (constant uint (0)) ) 
>                      )
>                      (
>                        (assign  (x) (var_ref x@250)  (expression uint i2u (swiz x (var_ref coord01@237) )) ) 
>                        (assign  (x) (var_ref y@249)  (expression uint i2u (swiz y (var_ref coord01@237) )) ) 
>                        (if (expression bool || (expression bool >= (var_ref x@250) (swiz x (var_ref compiler_temp@239) )) (expression bool >= (var_ref y@249) (swiz y (var_ref compiler_temp@239) )) ) (
>                          (assign  (x) (var_ref compiler_temp@247)  (constant uint (0)) ) 
>                        )
>                        (
>                          (assign  (x) (var_ref block@248)  (array_ref (var_ref fastuidraw_glyphDataStore_data) (expression int u2i (expression uint + (expression uint + (swiz x (var_ref fastuidraw_uint_varying0) )(expression uint >> (var_ref x@250) (constant uint (1)) ) ) (expression uint * (expression uint >> (var_ref y@249) (constant uint (1)) ) (expression uint >> (expression uint + (swiz x (var_ref compiler_temp@239) )(constant uint (1)) ) (constant uint (1)) ) ) ) ) ) ) 
>                          (declare (temporary ) uint compiler_temp@251)
>                          (if (expression bool != (expression uint & (var_ref x@250) (constant uint (1)) ) (constant uint (0)) ) (
>                            (assign  (x) (var_ref compiler_temp@251)  (constant uint (8)) ) 
>                          )
>                          (
>                            (assign  (x) (var_ref compiler_temp@251)  (constant uint (0)) ) 
>                          ))
>
>                          (declare (temporary ) uint compiler_temp@252)
>                          (if (expression bool != (expression uint & (var_ref y@249) (constant uint (1)) ) (constant uint (0)) ) (
>                            (assign  (x) (var_ref compiler_temp@252)  (constant uint (16)) ) 
>                          )
>                          (
>                            (assign  (x) (var_ref compiler_temp@252)  (constant uint (0)) ) 
>                          ))
>
>                          (assign  (x) (var_ref compiler_temp@247)  (expression uint >> (expression uint << (var_ref block@248) (expression uint + (constant uint (24)) (expression uint neg (expression uint + (var_ref compiler_temp@251) (var_ref compiler_temp@252) ) ) ) ) (constant uint (24)) ) ) 
>                        ))
>
>                      ))
>
>                      (declare (temporary ) uint compiler_temp@253)
>                      (declare () uint block@254)
>                      (declare () uint y@255)
>                      (declare () uint x@256)
>                      (if (expression bool || (expression bool < (swiz x (var_ref coord10@236) )(constant int (0)) ) (expression bool < (swiz y (var_ref coord10@236) )(constant int (0)) ) ) (
>                        (assign  (x) (var_ref compiler_temp@253)  (constant uint (0)) ) 
>                      )
>                      (
>                        (assign  (x) (var_ref x@256)  (expression uint i2u (swiz x (var_ref coord10@236) )) ) 
>                        (assign  (x) (var_ref y@255)  (expression uint i2u (swiz y (var_ref coord10@236) )) ) 
>                        (if (expression bool || (expression bool >= (var_ref x@256) (swiz x (var_ref compiler_temp@239) )) (expression bool >= (var_ref y@255) (swiz y (var_ref compiler_temp@239) )) ) (
>                          (assign  (x) (var_ref compiler_temp@253)  (constant uint (0)) ) 
>                        )
>                        (
>                          (assign  (x) (var_ref block@254)  (array_ref (var_ref fastuidraw_glyphDataStore_data) (expression int u2i (expression uint + (expression uint + (swiz x (var_ref fastuidraw_uint_varying0) )(expression uint >> (var_ref x@256) (constant uint (1)) ) ) (expression uint * (expression uint >> (var_ref y@255) (constant uint (1)) ) (expression uint >> (expression uint + (swiz x (var_ref compiler_temp@239) )(constant uint (1)) ) (constant uint (1)) ) ) ) ) ) ) 
>                          (declare (temporary ) uint compiler_temp@257)
>                          (if (expression bool != (expression uint & (var_ref x@256) (constant uint (1)) ) (constant uint (0)) ) (
>                            (assign  (x) (var_ref compiler_temp@257)  (constant uint (8)) ) 
>                          )
>                          (
>                            (assign  (x) (var_ref compiler_temp@257)  (constant uint (0)) ) 
>                          ))
>
>                          (declare (temporary ) uint compiler_temp@258)
>                          (if (expression bool != (expression uint & (var_ref y@255) (constant uint (1)) ) (constant uint (0)) ) (
>                            (assign  (x) (var_ref compiler_temp@258)  (constant uint (16)) ) 
>                          )
>                          (
>                            (assign  (x) (var_ref compiler_temp@258)  (constant uint (0)) ) 
>                          ))
>
>                          (assign  (x) (var_ref compiler_temp@253)  (expression uint >> (expression uint << (var_ref block@254) (expression uint + (constant uint (24)) (expression uint neg (expression uint + (var_ref compiler_temp@257) (var_ref compiler_temp@258) ) ) ) ) (constant uint (24)) ) ) 
>                        ))
>
>                      ))
>
>                      (declare (temporary ) uint compiler_temp@259)
>                      (declare () uint block@260)
>                      (declare () uint y@261)
>                      (declare () uint x@262)
>                      (if (expression bool || (expression bool < (swiz x (var_ref coord11@235) )(constant int (0)) ) (expression bool < (swiz y (var_ref coord11@235) )(constant int (0)) ) ) (
>                        (assign  (x) (var_ref compiler_temp@259)  (constant uint (0)) ) 
>                      )
>                      (
>                        (assign  (x) (var_ref x@262)  (expression uint i2u (swiz x (var_ref coord11@235) )) ) 
>                        (assign  (x) (var_ref y@261)  (expression uint i2u (swiz y (var_ref coord11@235) )) ) 
>                        (if (expression bool || (expression bool >= (var_ref x@262) (swiz x (var_ref compiler_temp@239) )) (expression bool >= (var_ref y@261) (swiz y (var_ref compiler_temp@239) )) ) (
>                          (assign  (x) (var_ref compiler_temp@259)  (constant uint (0)) ) 
>                        )
>                        (
>                          (assign  (x) (var_ref block@260)  (array_ref (var_ref fastuidraw_glyphDataStore_data) (expression int u2i (expression uint + (expression uint + (swiz x (var_ref fastuidraw_uint_varying0) )(expression uint >> (var_ref x@262) (constant uint (1)) ) ) (expression uint * (expression uint >> (var_ref y@261) (constant uint (1)) ) (expression uint >> (expression uint + (swiz x (var_ref compiler_temp@239) )(constant uint (1)) ) (constant uint (1)) ) ) ) ) ) ) 
>                          (declare (temporary ) uint compiler_temp@263)
>                          (if (expression bool != (expression uint & (var_ref x@262) (constant uint (1)) ) (constant uint (0)) ) (
>                            (assign  (x) (var_ref compiler_temp@263)  (constant uint (8)) ) 
>                          )
>                          (
>                            (assign  (x) (var_ref compiler_temp@263)  (constant uint (0)) ) 
>                          ))
>
>                          (declare (temporary ) uint compiler_temp@264)
>                          (if (expression bool != (expression uint & (var_ref y@261) (constant uint (1)) ) (constant uint (0)) ) (
>                            (assign  (x) (var_ref compiler_temp@264)  (constant uint (16)) ) 
>                          )
>                          (
>                            (assign  (x) (var_ref compiler_temp@264)  (constant uint (0)) ) 
>                          ))
>
>                          (assign  (x) (var_ref compiler_temp@259)  (expression uint >> (expression uint << (var_ref block@260) (expression uint + (constant uint (24)) (expression uint neg (expression uint + (var_ref compiler_temp@263) (var_ref compiler_temp@264) ) ) ) ) (constant uint (24)) ) ) 
>                        ))
>
>                      ))
>
>                      (assign  (x) (var_ref dist)  (expression float + (expression float * (constant float (2.000000)) (expression float * (expression float lrp (expression float lrp (expression float u2f (var_ref compiler_temp@241) ) (expression float u2f (var_ref compiler_temp@247) ) (swiz y (var_ref mixer@234) )) (expression float lrp (expression float u2f (var_ref compiler_temp@253) ) (expression float u2f (var_ref compiler_temp@259) ) (swiz y (var_ref mixer@234) )) (swiz x (var_ref mixer@234) )) (expression float rcp (constant float (255.000000)) ) ) ) (constant float (-1.000000)) ) ) 
>                      (declare (temporary ) float dx)
>                      (assign  (x) (var_ref dx)  (expression float dFdx (var_ref dist) ) ) 
>                      (declare (temporary ) float dy)
>                      (assign  (x) (var_ref dy)  (expression float dFdy (var_ref dist) ) ) 
>                      (assign  (xyzw) (var_ref p@210)  (swiz xxxx (expression float sat (expression float + (constant float (0.500000)) (expression float * (var_ref dist) (expression float rsq (expression float + (expression float * (var_ref dx) (var_ref dx) ) (expression float * (var_ref dy) (var_ref dy) ) ) ) ) ) ) )) 
>                    )
>                    (
>                      (if (expression bool == (swiz y (var_ref fastuidraw_uint_varying1) )(constant uint (22)) ) (
>                        (declare () float cvg)
>                        (declare (temporary ) uint glyph_data_location)
>                        (assign  (x) (var_ref glyph_data_location)  (expression uint & (swiz x (var_ref fastuidraw_uint_varying0) )(constant uint (1073741823)) ) ) 
>                        (declare (temporary ) vec2 glyph_coord_dx)
>                        (assign  (xy) (var_ref glyph_coord_dx)  (expression vec2 dFdx (swiz xy (var_ref fastuidraw_float_smooth_varying0) )) ) 
>                        (declare (temporary ) vec2 glyph_coord_dy)
>                        (assign  (xy) (var_ref glyph_coord_dy)  (expression vec2 dFdy (swiz xy (var_ref fastuidraw_float_smooth_varying0) )) ) 
>                        (declare (temporary ) bool use_odd_even_rule)
>                        (assign  (x) (var_ref use_odd_even_rule)  (expression bool != (expression uint & (swiz x (var_ref fastuidraw_uint_varying0) )(constant uint (2147483648)) ) (constant uint (0)) ) ) 
>                        (declare () float distance)
>                        (declare () float nv_distance_increment)
>                        (declare () float nv_distance_decrement)
>                        (declare () int winding_number)
>                        (declare () uint c)
>                        (declare () uint src)
>                        (declare (temporary ) vec2 compiler_temp@265)
>                        (declare (temporary ) vec2 compiler_temp@266)
>                        (declare () uint offset)
>                        (declare () uint v@267)
>                        (assign  (xy) (var_ref compiler_temp@265)  (constant vec2 (-2048.000000 -2048.000000)) ) 
>                        (assign  (xy) (var_ref compiler_temp@266)  (constant vec2 (2048.000000 2048.000000)) ) 
>                        (assign  (x) (var_ref offset)  (var_ref glyph_data_location) ) 
>                        (assign  (x) (var_ref v@267)  (array_ref (var_ref fastuidraw_glyphDataStore_data) (expression int u2i (var_ref glyph_data_location) ) ) ) 
>                        (loop (
>                          (declare () bool take_max_choice)
>                          (declare () float split_pt)
>                          (if (expression bool == (expression uint & (var_ref v@267) (constant uint (1)) ) (constant uint (0)) ) (
>                            break
>                          )
>                          ())
>
>                          (declare (temporary ) uint compiler_temp@268)
>                          (assign  (x) (var_ref compiler_temp@268)  (expression uint >> (expression uint << (var_ref v@267) (constant uint (30)) ) (constant uint (31)) ) ) 
>                          (if (expression bool == (var_ref compiler_temp@268) (constant uint (0)) ) (
>                            (assign  (x) (var_ref split_pt)  (expression float * (constant float (0.500000)) (expression float + (swiz x (var_ref compiler_temp@265) )(swiz x (var_ref compiler_temp@266) )) ) ) 
>                            (assign  (x) (var_ref take_max_choice)  (expression bool < (var_ref split_pt) (swiz x (var_ref fastuidraw_float_smooth_varying0) )) ) 
>                            (declare (temporary ) float compiler_temp@269)
>                            (if (var_ref take_max_choice) (
>                              (assign  (x) (var_ref compiler_temp@269)  (var_ref split_pt) ) 
>                            )
>                            (
>                              (assign  (x) (var_ref compiler_temp@269)  (swiz x (var_ref compiler_temp@265) )) 
>                            ))
>
>                            (assign  (x) (var_ref compiler_temp@265)  (var_ref compiler_temp@269) ) 
>                            (declare (temporary ) float compiler_temp@270)
>                            (if (var_ref take_max_choice) (
>                              (assign  (x) (var_ref compiler_temp@270)  (swiz x (var_ref compiler_temp@266) )) 
>                            )
>                            (
>                              (assign  (x) (var_ref compiler_temp@270)  (var_ref split_pt) ) 
>                            ))
>
>                            (assign  (x) (var_ref compiler_temp@266)  (var_ref compiler_temp@270) ) 
>                          )
>                          (
>                            (assign  (x) (var_ref split_pt)  (expression float * (constant float (0.500000)) (expression float + (swiz y (var_ref compiler_temp@265) )(swiz y (var_ref compiler_temp@266) )) ) ) 
>                            (assign  (x) (var_ref take_max_choice)  (expression bool < (var_ref split_pt) (swiz y (var_ref fastuidraw_float_smooth_varying0) )) ) 
>                            (declare (temporary ) float compiler_temp@271)
>                            (if (var_ref take_max_choice) (
>                              (assign  (x) (var_ref compiler_temp@271)  (var_ref split_pt) ) 
>                            )
>                            (
>                              (assign  (x) (var_ref compiler_temp@271)  (swiz y (var_ref compiler_temp@265) )) 
>                            ))
>
>                            (assign  (y) (var_ref compiler_temp@265)  (var_ref compiler_temp@271) ) 
>                            (declare (temporary ) float compiler_temp@272)
>                            (if (var_ref take_max_choice) (
>                              (assign  (x) (var_ref compiler_temp@272)  (swiz y (var_ref compiler_temp@266) )) 
>                            )
>                            (
>                              (assign  (x) (var_ref compiler_temp@272)  (var_ref split_pt) ) 
>                            ))
>
>                            (assign  (y) (var_ref compiler_temp@266)  (var_ref compiler_temp@272) ) 
>                          ))
>
>                          (declare (temporary ) uint compiler_temp@273)
>                          (if (var_ref take_max_choice) (
>                            (assign  (x) (var_ref compiler_temp@273)  (constant uint (17)) ) 
>                          )
>                          (
>                            (assign  (x) (var_ref compiler_temp@273)  (constant uint (2)) ) 
>                          ))
>
>                          (assign  (x) (var_ref offset)  (expression uint + (expression uint >> (expression uint << (var_ref v@267) (expression uint + (constant uint (17)) (expression uint neg (var_ref compiler_temp@273) ) ) ) (constant uint (17)) ) (var_ref glyph_data_location) ) ) 
>                          (assign  (x) (var_ref v@267)  (array_ref (var_ref fastuidraw_glyphDataStore_data) (expression int u2i (var_ref offset) ) ) ) 
>                        ))
>
>                        (declare (temporary ) uint compiler_temp@274)
>                        (assign  (x) (var_ref compiler_temp@274)  (expression uint >> (expression uint << (var_ref v@267) (constant uint (15)) ) (constant uint (16)) ) ) 
>                        (declare (temporary ) uint compiler_temp@275)
>                        (assign  (x) (var_ref compiler_temp@275)  (expression uint >> (var_ref v@267) (constant uint (17)) ) ) 
>                        (assign  (x) (var_ref nv_distance_increment)  (constant float (120.000000)) ) 
>                        (assign  (x) (var_ref nv_distance_decrement)  (constant float (120.000000)) ) 
>                        (declare (temporary ) int compiler_temp@276)
>                        (declare () vec2 delta)
>                        (declare () uvec2 uint_delta)
>                        (declare () uint texel)
>                        (assign  (x) (var_ref texel)  (array_ref (var_ref fastuidraw_glyphDataStore_data) (expression int u2i (expression uint + (var_ref offset) (constant uint (1)) ) ) ) ) 
>                        (assign  (x) (var_ref uint_delta)  (expression uint >> (expression uint << (var_ref texel) (constant uint (8)) ) (constant uint (24)) ) ) 
>                        (assign  (y) (var_ref uint_delta)  (expression uint >> (var_ref texel) (constant uint (24)) ) ) 
>                        (assign  (xy) (var_ref delta)  (expression vec2 * (expression vec2 u2f (var_ref uint_delta) ) (expression vec2 + (var_ref compiler_temp@266) (expression vec2 neg (var_ref compiler_temp@265) ) ) ) ) 
>                        (assign  (xy) (var_ref delta)  (expression vec2 * (var_ref delta) (expression float rcp (constant float (256.000000)) ) ) ) 
>                        (assign  (x) (var_ref compiler_temp@276)  (expression int + (expression int u2i (expression uint >> (expression uint << (var_ref texel) (constant uint (16)) ) (constant uint (16)) ) ) (constant int (-32768)) ) ) 
>                        (declare (temporary ) vec2 compiler_temp@277)
>                        (declare (temporary ) vec2 compiler_temp@278)
>                        (declare (temporary ) float compiler_temp@279)
>                        (declare () float det)
>                        (declare () vec2 em)
>                        (declare () vec2 bottom_row)
>                        (declare () vec2 top_row)
>                        (declare () vec2 q@280)
>                        (assign  (xy) (var_ref q@280)  (expression vec2 + (expression vec2 + (var_ref compiler_temp@265) (var_ref delta) ) (expression vec2 neg (swiz xy (var_ref fastuidraw_float_smooth_varying0) )) ) ) 
>                        (assign  (x) (var_ref compiler_temp@278)  (expression float neg (swiz y (var_ref q@280) )) ) 
>                        (assign  (y) (var_ref compiler_temp@278)  (swiz x (var_ref q@280) )) 
>                        (assign  (x) (var_ref top_row)  (expression float neg (expression float + (expression float * (swiz y (var_ref glyph_coord_dx) )(swiz y (var_ref glyph_coord_dx) )) (expression float * (swiz y (var_ref glyph_coord_dy) )(swiz y (var_ref glyph_coord_dy) )) ) ) ) 
>                        (declare (temporary ) float compiler_temp@281)
>                        (assign  (x) (var_ref compiler_temp@281)  (expression float + (expression float * (swiz x (var_ref glyph_coord_dx) )(swiz y (var_ref glyph_coord_dx) )) (expression float * (swiz x (var_ref glyph_coord_dy) )(swiz y (var_ref glyph_coord_dy) )) ) ) 
>                        (assign  (x) (var_ref bottom_row)  (var_ref compiler_temp@281) ) 
>                        (assign  (y) (var_ref top_row)  (var_ref compiler_temp@281) ) 
>                        (assign  (y) (var_ref bottom_row)  (expression float neg (expression float + (expression float * (swiz x (var_ref glyph_coord_dx) )(swiz x (var_ref glyph_coord_dx) )) (expression float * (swiz x (var_ref glyph_coord_dy) )(swiz x (var_ref glyph_coord_dy) )) ) ) ) 
>                        (assign  (x) (var_ref compiler_temp@277)  (expression float dot (var_ref top_row) (var_ref q@280) ) ) 
>                        (assign  (y) (var_ref compiler_temp@277)  (expression float dot (var_ref bottom_row) (var_ref q@280) ) ) 
>                        (assign  (x) (var_ref em)  (expression float + (expression float abs (expression float dot (var_ref compiler_temp@277) (var_ref glyph_coord_dx) ) ) (expression float abs (expression float dot (var_ref compiler_temp@277) (var_ref glyph_coord_dy) ) ) ) ) 
>                        (assign  (y) (var_ref em)  (expression float + (expression float abs (expression float dot (var_ref compiler_temp@278) (var_ref glyph_coord_dx) ) ) (expression float abs (expression float dot (var_ref compiler_temp@278) (var_ref glyph_coord_dy) ) ) ) ) 
>                        (assign  (x) (var_ref em)  (expression float max (swiz x (var_ref em) )(constant float (0x1.ad7f2ap-24)) ) ) 
>                        (assign  (y) (var_ref em)  (expression float max (swiz y (var_ref em) )(constant float (0x1.ad7f2ap-24)) ) ) 
>                        (assign  (xy) (var_ref compiler_temp@277)  (expression vec2 * (var_ref compiler_temp@277) (expression float rcp (swiz x (var_ref em) )) ) ) 
>                        (assign  (xy) (var_ref compiler_temp@278)  (expression vec2 * (var_ref compiler_temp@278) (expression float rcp (swiz y (var_ref em) )) ) ) 
>                        (assign  (x) (var_ref compiler_temp@279)  (expression float dot (var_ref compiler_temp@277) (var_ref q@280) ) ) 
>                        (if (expression bool < (var_ref compiler_temp@279) (constant float (0.000000)) ) (
>                          (assign  (xy) (var_ref compiler_temp@277)  (expression vec2 neg (var_ref compiler_temp@277) ) ) 
>                          (assign  (x) (var_ref compiler_temp@279)  (expression float neg (var_ref compiler_temp@279) ) ) 
>                        )
>                        ())
>
>                        (assign  (x) (var_ref det)  (expression float + (expression float * (swiz x (var_ref compiler_temp@277) )(swiz y (var_ref compiler_temp@278) )) (expression float neg (expression float * (swiz y (var_ref compiler_temp@277) )(swiz x (var_ref compiler_temp@278) )) ) ) ) 
>                        (if (expression bool < (var_ref det) (constant float (0.000000)) ) (
>                          (assign  (xy) (var_ref compiler_temp@278)  (expression vec2 neg (var_ref compiler_temp@278) ) ) 
>                        )
>                        ())
>
>                        (assign  (x) (var_ref winding_number)  (var_ref compiler_temp@276) ) 
>                        (assign  (x) (var_ref src)  (expression uint + (var_ref compiler_temp@274) (var_ref glyph_data_location) ) ) 
>                        (assign  (x) (var_ref c)  (constant uint (0)) ) 
>                        (loop (
>                          (declare () uint curve_pair)
>                          (if (expression bool >= (var_ref c) (var_ref compiler_temp@275) ) (
>                            break
>                          )
>                          ())
>
>                          (assign  (x) (var_ref curve_pair)  (array_ref (var_ref fastuidraw_glyphDataStore_data) (expression int u2i (var_ref src) ) ) ) 
>                          (assign  (x) (var_ref src)  (expression uint + (var_ref src) (constant uint (1)) ) ) 
>                          (declare (temporary ) uint compiler_temp@282)
>                          (assign  (x) (var_ref compiler_temp@282)  (expression uint >> (expression uint << (var_ref curve_pair) (constant uint (16)) ) (constant uint (16)) ) ) 
>                          (declare (temporary ) vec2 compiler_temp@283)
>                          (declare (temporary ) vec2 compiler_temp@284)
>                          (declare (temporary ) bool compiler_temp@285)
>                          (declare () uint curve_src)
>                          (assign  (x) (var_ref curve_src)  (expression uint + (var_ref glyph_data_location) (expression uint >> (expression uint << (var_ref compiler_temp@282) (constant uint (17)) ) (constant uint (17)) ) ) ) 
>                          (assign  (x) (var_ref compiler_temp@285)  (expression bool != (expression uint & (var_ref compiler_temp@282) (constant uint (32768)) ) (constant uint (0)) ) ) 
>                          (declare (temporary ) vec2 compiler_temp@286)
>                          (assign  (xy) (var_ref compiler_temp@286)  (expression vec2 unpackHalf2x16 (array_ref (var_ref fastuidraw_glyphDataStore_data) (expression int u2i (var_ref curve_src) ) ) ) ) 
>                          (declare (temporary ) vec2 compiler_temp@287)
>                          (assign  (xy) (var_ref compiler_temp@287)  (expression vec2 unpackHalf2x16 (array_ref (var_ref fastuidraw_glyphDataStore_data) (expression int u2i (expression uint + (var_ref curve_src) (constant uint (1)) ) ) ) ) ) 
>                          (assign  (xy) (var_ref compiler_temp@283)  (var_ref compiler_temp@287) ) 
>                          (if (var_ref compiler_temp@285) (
>                            (assign  (xy) (var_ref compiler_temp@284)  (expression vec2 unpackHalf2x16 (array_ref (var_ref fastuidraw_glyphDataStore_data) (expression int u2i (expression uint + (var_ref curve_src) (constant uint (2)) ) ) ) ) ) 
>                          )
>                          (
>                            (assign  (xy) (var_ref compiler_temp@284)  (var_ref compiler_temp@287) ) 
>                            (assign  (xy) (var_ref compiler_temp@283)  (expression vec2 * (constant float (0.500000)) (expression vec2 + (var_ref compiler_temp@286) (var_ref compiler_temp@287) ) ) ) 
>                          ))
>
>                          (declare (temporary ) float compiler_temp@288)
>                          (declare (temporary ) float compiler_temp@289)
>                          (assign  (x) (var_ref compiler_temp@288)  (var_ref nv_distance_increment) ) 
>                          (assign  (x) (var_ref compiler_temp@289)  (var_ref nv_distance_decrement) ) 
>                          (declare () uvec2 code)
>                          (declare () int R)
>                          (declare () vec2 B)
>                          (declare () vec2 A)
>                          (assign  (x) (var_ref R)  (constant int (0)) ) 
>                          (declare (temporary ) vec2 compiler_temp@290)
>                          (assign  (xy) (var_ref compiler_temp@290)  (expression vec2 + (var_ref compiler_temp@286) (expression vec2 neg (swiz xy (var_ref fastuidraw_float_smooth_varying0) )) ) ) 
>                          (declare (temporary ) vec2 compiler_temp@291)
>                          (assign  (x) (var_ref compiler_temp@291)  (expression float dot (var_ref compiler_temp@277) (var_ref compiler_temp@290) ) ) 
>                          (assign  (y) (var_ref compiler_temp@291)  (expression float dot (var_ref compiler_temp@278) (var_ref compiler_temp@290) ) ) 
>                          (declare (temporary ) vec2 compiler_temp@292)
>                          (assign  (xy) (var_ref compiler_temp@292)  (expression vec2 + (var_ref compiler_temp@283) (expression vec2 neg (swiz xy (var_ref fastuidraw_float_smooth_varying0) )) ) ) 
>                          (declare (temporary ) vec2 compiler_temp@293)
>                          (assign  (x) (var_ref compiler_temp@293)  (expression float dot (var_ref compiler_temp@277) (var_ref compiler_temp@292) ) ) 
>                          (assign  (y) (var_ref compiler_temp@293)  (expression float dot (var_ref compiler_temp@278) (var_ref compiler_temp@292) ) ) 
>                          (declare (temporary ) vec2 compiler_temp@294)
>                          (assign  (xy) (var_ref compiler_temp@294)  (expression vec2 + (var_ref compiler_temp@284) (expression vec2 neg (swiz xy (var_ref fastuidraw_float_smooth_varying0) )) ) ) 
>                          (declare (temporary ) vec2 compiler_temp@295)
>                          (assign  (x) (var_ref compiler_temp@295)  (expression float dot (var_ref compiler_temp@277) (var_ref compiler_temp@294) ) ) 
>                          (assign  (y) (var_ref compiler_temp@295)  (expression float dot (var_ref compiler_temp@278) (var_ref compiler_temp@294) ) ) 
>                          (assign  (xy) (var_ref A)  (expression vec2 + (expression vec2 + (var_ref compiler_temp@291) (expression vec2 neg (expression vec2 * (constant float (2.000000)) (var_ref compiler_temp@293) ) ) ) (var_ref compiler_temp@295) ) ) 
>                          (assign  (xy) (var_ref B)  (expression vec2 + (var_ref compiler_temp@291) (expression vec2 neg (var_ref compiler_temp@293) ) ) ) 
>                          (declare (temporary ) uint compiler_temp@296)
>                          (declare (temporary ) uint compiler_temp@297)
>                          (if (expression bool < (constant float (0.000000)) (swiz x (var_ref compiler_temp@291) )) (
>                            (assign  (x) (var_ref compiler_temp@297)  (constant uint (2)) ) 
>                          )
>                          (
>                            (assign  (x) (var_ref compiler_temp@297)  (constant uint (0)) ) 
>                          ))
>
>                          (declare (temporary ) uint compiler_temp@298)
>                          (if (expression bool < (constant float (0.000000)) (swiz x (var_ref compiler_temp@293) )) (
>                            (assign  (x) (var_ref compiler_temp@298)  (constant uint (4)) ) 
>                          )
>                          (
>                            (assign  (x) (var_ref compiler_temp@298)  (constant uint (0)) ) 
>                          ))
>
>                          (declare (temporary ) uint compiler_temp@299)
>                          (if (expression bool < (constant float (0.000000)) (swiz x (var_ref compiler_temp@295) )) (
>                            (assign  (x) (var_ref compiler_temp@299)  (constant uint (8)) ) 
>                          )
>                          (
>                            (assign  (x) (var_ref compiler_temp@299)  (constant uint (0)) ) 
>                          ))
>
>                          (assign  (x) (var_ref compiler_temp@296)  (expression uint & (expression uint >> (constant uint (11892)) (expression uint + (expression uint + (var_ref compiler_temp@297) (var_ref compiler_temp@298) ) (var_ref compiler_temp@299) ) ) (constant uint (3)) ) ) 
>                          (assign  (x) (var_ref code)  (var_ref compiler_temp@296) ) 
>                          (declare (temporary ) uint compiler_temp@300)
>                          (declare (temporary ) uint compiler_temp@301)
>                          (if (expression bool < (constant float (0.000000)) (swiz y (var_ref compiler_temp@291) )) (
>                            (assign  (x) (var_ref compiler_temp@301)  (constant uint (2)) ) 
>                          )
>                          (
>                            (assign  (x) (var_ref compiler_temp@301)  (constant uint (0)) ) 
>                          ))
>
>                          (declare (temporary ) uint compiler_temp@302)
>                          (if (expression bool < (constant float (0.000000)) (swiz y (var_ref compiler_temp@293) )) (
>                            (assign  (x) (var_ref compiler_temp@302)  (constant uint (4)) ) 
>                          )
>                          (
>                            (assign  (x) (var_ref compiler_temp@302)  (constant uint (0)) ) 
>                          ))
>
>                          (declare (temporary ) uint compiler_temp@303)
>                          (if (expression bool < (constant float (0.000000)) (swiz y (var_ref compiler_temp@295) )) (
>                            (assign  (x) (var_ref compiler_temp@303)  (constant uint (8)) ) 
>                          )
>                          (
>                            (assign  (x) (var_ref compiler_temp@303)  (constant uint (0)) ) 
>                          ))
>
>                          (assign  (x) (var_ref compiler_temp@300)  (expression uint & (expression uint >> (constant uint (11892)) (expression uint + (expression uint + (var_ref compiler_temp@301) (var_ref compiler_temp@302) ) (var_ref compiler_temp@303) ) ) (constant uint (3)) ) ) 
>                          (assign  (y) (var_ref code)  (var_ref compiler_temp@300) ) 
>                          (if (expression bool != (var_ref compiler_temp@300) (constant uint (0)) ) (
>                            (declare () float x2)
>                            (declare () float x1)
>                            (declare () float t2)
>                            (declare () float t1@304)
>                            (declare (temporary ) bool compiler_temp@305)
>                            (if (var_ref compiler_temp@285) (
>                              (assign  (x) (var_ref compiler_temp@305)  (expression bool < (constant float (0.000100)) (expression float abs (swiz y (var_ref A) )) ) ) 
>                            )
>                            (
>                              (assign  (x) (var_ref compiler_temp@305)  (constant bool (0)) ) 
>                            ))
>
>                            (if (var_ref compiler_temp@305) (
>                              (declare () float D)
>                              (declare (temporary ) float compiler_temp@306)
>                              (assign  (x) (var_ref compiler_temp@306)  (expression float rcp (swiz y (var_ref A) )) ) 
>                              (assign  (x) (var_ref D)  (expression float + (expression float * (swiz y (var_ref B) )(swiz y (var_ref B) )) (expression float neg (expression float * (swiz y (var_ref A) )(swiz y (var_ref compiler_temp@291) )) ) ) ) 
>                              (if (expression bool < (var_ref D) (constant float (0.000000)) ) (
>                                (assign  (y) (var_ref code)  (constant uint (0)) ) 
>                                (assign  (x) (var_ref D)  (constant float (0.000000)) ) 
>                              )
>                              ())
>
>                              (declare (temporary ) float compiler_temp@307)
>                              (assign  (x) (var_ref compiler_temp@307)  (expression float sqrt (var_ref D) ) ) 
>                              (assign  (x) (var_ref D)  (var_ref compiler_temp@307) ) 
>                              (assign  (x) (var_ref t1@304)  (expression float * (expression float + (swiz y (var_ref B) )(expression float neg (var_ref compiler_temp@307) ) ) (var_ref compiler_temp@306) ) ) 
>                              (assign  (x) (var_ref t2)  (expression float * (expression float + (swiz y (var_ref B) )(var_ref compiler_temp@307) ) (var_ref compiler_temp@306) ) ) 
>                            )
>                            (
>                              (declare (temporary ) float compiler_temp@308)
>                              (assign  (x) (var_ref compiler_temp@308)  (expression float * (expression float * (constant float (0.500000)) (swiz y (var_ref compiler_temp@291) )) (expression float rcp (swiz y (var_ref B) )) ) ) 
>                              (assign  (x) (var_ref t2)  (var_ref compiler_temp@308) ) 
>                              (assign  (x) (var_ref t1@304)  (var_ref compiler_temp@308) ) 
>                            ))
>
>                            (assign  (x) (var_ref x1)  (expression float + (expression float * (expression float + (expression float * (swiz x (var_ref A) )(var_ref t1@304) ) (expression float neg (expression float * (swiz x (var_ref B) )(constant float (2.000000)) ) ) ) (var_ref t1@304) ) (swiz x (var_ref compiler_temp@291) )) ) 
>                            (assign  (x) (var_ref x2)  (expression float + (expression float * (expression float + (expression float * (swiz x (var_ref A) )(var_ref t2) ) (expression float neg (expression float * (swiz x (var_ref B) )(constant float (2.000000)) ) ) ) (var_ref t2) ) (swiz x (var_ref compiler_temp@291) )) ) 
>                            (if (expression bool != (expression uint & (swiz y (var_ref code) )(constant uint (1)) ) (constant uint (0)) ) (
>                              (if (expression bool && (expression bool >= (var_ref compiler_temp@279) (var_ref x1) ) (expression bool >= (var_ref x1) (constant float (0.000000)) ) ) (
>                                (assign  (x) (var_ref R)  (constant int (1)) ) 
>                              )
>                              ())
>
>                              (declare (temporary ) float compiler_temp@309)
>                              (assign  (x) (var_ref compiler_temp@309)  (expression float abs (var_ref x1) ) ) 
>                              (declare (temporary ) float compiler_temp@310)
>                              (declare (temporary ) float compiler_temp@311)
>                              (assign  (x) (var_ref compiler_temp@310)  (var_ref nv_distance_increment) ) 
>                              (assign  (x) (var_ref compiler_temp@311)  (var_ref nv_distance_decrement) ) 
>                              (if (expression bool < (var_ref x1) (constant float (0.000000)) ) (
>                                (assign  (x) (var_ref compiler_temp@310)  (expression float min (var_ref nv_distance_increment) (var_ref compiler_temp@309) ) ) 
>                              )
>                              (
>                                (assign  (x) (var_ref compiler_temp@311)  (expression float min (var_ref nv_distance_decrement) (var_ref compiler_temp@309) ) ) 
>                              ))
>
>                              (assign  (x) (var_ref compiler_temp@288)  (var_ref compiler_temp@310) ) 
>                              (assign  (x) (var_ref compiler_temp@289)  (var_ref compiler_temp@311) ) 
>                            )
>                            ())
>
>                            (if (expression bool < (constant uint (1)) (swiz y (var_ref code) )) (
>                              (if (expression bool && (expression bool >= (var_ref compiler_temp@279) (var_ref x2) ) (expression bool >= (var_ref x2) (constant float (0.000000)) ) ) (
>                                (assign  (x) (var_ref R)  (expression int + (var_ref R) (constant int (-1)) ) ) 
>                              )
>                              ())
>
>                              (declare (temporary ) float compiler_temp@312)
>                              (assign  (x) (var_ref compiler_temp@312)  (expression float abs (var_ref x2) ) ) 
>                              (declare (temporary ) float compiler_temp@313)
>                              (declare (temporary ) float compiler_temp@314)
>                              (assign  (x) (var_ref compiler_temp@313)  (var_ref compiler_temp@288) ) 
>                              (assign  (x) (var_ref compiler_temp@314)  (var_ref compiler_temp@289) ) 
>                              (if (expression bool < (constant float (0.000000)) (var_ref x2) ) (
>                                (assign  (x) (var_ref compiler_temp@313)  (expression float min (var_ref compiler_temp@288) (var_ref compiler_temp@312) ) ) 
>                              )
>                              (
>                                (assign  (x) (var_ref compiler_temp@314)  (expression float min (var_ref compiler_temp@289) (var_ref compiler_temp@312) ) ) 
>                              ))
>
>                              (assign  (x) (var_ref compiler_temp@288)  (var_ref compiler_temp@313) ) 
>                              (assign  (x) (var_ref compiler_temp@289)  (var_ref compiler_temp@314) ) 
>                            )
>                            ())
>
>                          )
>                          ())
>
>                          (if (expression bool != (var_ref compiler_temp@296) (constant uint (0)) ) (
>                            (declare () float y2)
>                            (declare () float y1)
>                            (declare () float t2@315)
>                            (declare () float t1@316)
>                            (declare (temporary ) bool compiler_temp@317)
>                            (if (var_ref compiler_temp@285) (
>                              (assign  (x) (var_ref compiler_temp@317)  (expression bool < (constant float (0.000100)) (expression float abs (swiz x (var_ref A) )) ) ) 
>                            )
>                            (
>                              (assign  (x) (var_ref compiler_temp@317)  (constant bool (0)) ) 
>                            ))
>
>                            (if (var_ref compiler_temp@317) (
>                              (declare () float D@318)
>                              (declare (temporary ) float compiler_temp@319)
>                              (assign  (x) (var_ref compiler_temp@319)  (expression float rcp (swiz x (var_ref A) )) ) 
>                              (assign  (x) (var_ref D@318)  (expression float + (expression float * (swiz x (var_ref B) )(swiz x (var_ref B) )) (expression float neg (expression float * (swiz x (var_ref A) )(swiz x (var_ref compiler_temp@291) )) ) ) ) 
>                              (if (expression bool < (var_ref D@318) (constant float (0.000000)) ) (
>                                (assign  (x) (var_ref code)  (constant uint (0)) ) 
>                                (assign  (x) (var_ref D@318)  (constant float (0.000000)) ) 
>                              )
>                              ())
>
>                              (declare (temporary ) float compiler_temp@320)
>                              (assign  (x) (var_ref compiler_temp@320)  (expression float sqrt (var_ref D@318) ) ) 
>                              (assign  (x) (var_ref D@318)  (var_ref compiler_temp@320) ) 
>                              (assign  (x) (var_ref t1@316)  (expression float * (expression float + (swiz x (var_ref B) )(expression float neg (var_ref compiler_temp@320) ) ) (var_ref compiler_temp@319) ) ) 
>                              (assign  (x) (var_ref t2@315)  (expression float * (expression float + (swiz x (var_ref B) )(var_ref compiler_temp@320) ) (var_ref compiler_temp@319) ) ) 
>                            )
>                            (
>                              (declare (temporary ) float compiler_temp@321)
>                              (assign  (x) (var_ref compiler_temp@321)  (expression float * (expression float * (constant float (0.500000)) (swiz x (var_ref compiler_temp@291) )) (expression float rcp (swiz x (var_ref B) )) ) ) 
>                              (assign  (x) (var_ref t2@315)  (var_ref compiler_temp@321) ) 
>                              (assign  (x) (var_ref t1@316)  (var_ref compiler_temp@321) ) 
>                            ))
>
>                            (assign  (x) (var_ref y1)  (expression float + (expression float * (expression float + (expression float * (swiz y (var_ref A) )(var_ref t1@316) ) (expression float neg (expression float * (swiz y (var_ref B) )(constant float (2.000000)) ) ) ) (var_ref t1@316) ) (swiz y (var_ref compiler_temp@291) )) ) 
>                            (assign  (x) (var_ref y2)  (expression float + (expression float * (expression float + (expression float * (swiz y (var_ref A) )(var_ref t2@315) ) (expression float neg (expression float * (swiz y (var_ref B) )(constant float (2.000000)) ) ) ) (var_ref t2@315) ) (swiz y (var_ref compiler_temp@291) )) ) 
>                            (if (expression bool != (expression uint & (swiz x (var_ref code) )(constant uint (1)) ) (constant uint (0)) ) (
>                              (declare (temporary ) float compiler_temp@322)
>                              (assign  (x) (var_ref compiler_temp@322)  (expression float abs (var_ref y1) ) ) 
>                              (declare (temporary ) float compiler_temp@323)
>                              (declare (temporary ) float compiler_temp@324)
>                              (assign  (x) (var_ref compiler_temp@323)  (var_ref compiler_temp@288) ) 
>                              (assign  (x) (var_ref compiler_temp@324)  (var_ref compiler_temp@289) ) 
>                              (if (expression bool < (constant float (0.000000)) (var_ref y1) ) (
>                                (assign  (x) (var_ref compiler_temp@323)  (expression float min (var_ref compiler_temp@288) (var_ref compiler_temp@322) ) ) 
>                              )
>                              (
>                                (assign  (x) (var_ref compiler_temp@324)  (expression float min (var_ref compiler_temp@289) (var_ref compiler_temp@322) ) ) 
>                              ))
>
>                              (assign  (x) (var_ref compiler_temp@288)  (var_ref compiler_temp@323) ) 
>                              (assign  (x) (var_ref compiler_temp@289)  (var_ref compiler_temp@324) ) 
>                            )
>                            ())
>
>                            (if (expression bool < (constant uint (1)) (swiz x (var_ref code) )) (
>                              (declare (temporary ) float compiler_temp@325)
>                              (assign  (x) (var_ref compiler_temp@325)  (expression float abs (var_ref y2) ) ) 
>                              (declare (temporary ) float compiler_temp@326)
>                              (declare (temporary ) float compiler_temp@327)
>                              (assign  (x) (var_ref compiler_temp@326)  (var_ref compiler_temp@288) ) 
>                              (assign  (x) (var_ref compiler_temp@327)  (var_ref compiler_temp@289) ) 
>                              (if (expression bool < (var_ref y2) (constant float (0.000000)) ) (
>                                (assign  (x) (var_ref compiler_temp@326)  (expression float min (var_ref compiler_temp@288) (var_ref compiler_temp@325) ) ) 
>                              )
>                              (
>                                (assign  (x) (var_ref compiler_temp@327)  (expression float min (var_ref compiler_temp@289) (var_ref compiler_temp@325) ) ) 
>                              ))
>
>                              (assign  (x) (var_ref compiler_temp@288)  (var_ref compiler_temp@326) ) 
>                              (assign  (x) (var_ref compiler_temp@289)  (var_ref compiler_temp@327) ) 
>                            )
>                            ())
>
>                          )
>                          ())
>
>                          (assign  (x) (var_ref nv_distance_increment)  (var_ref compiler_temp@288) ) 
>                          (assign  (x) (var_ref nv_distance_decrement)  (var_ref compiler_temp@289) ) 
>                          (assign  (x) (var_ref winding_number)  (expression int + (var_ref winding_number) (var_ref R) ) ) 
>                          (if (expression bool < (expression uint + (var_ref c) (constant uint (1)) ) (var_ref compiler_temp@275) ) (
>                            (declare (temporary ) uint compiler_temp@328)
>                            (assign  (x) (var_ref compiler_temp@328)  (expression uint >> (var_ref curve_pair) (constant uint (16)) ) ) 
>                            (declare (temporary ) vec2 compiler_temp@329)
>                            (declare (temporary ) vec2 compiler_temp@330)
>                            (declare (temporary ) bool compiler_temp@331)
>                            (declare () uint curve_src@332)
>                            (assign  (x) (var_ref curve_src@332)  (expression uint + (var_ref glyph_data_location) (expression uint >> (expression uint << (var_ref compiler_temp@328) (constant uint (17)) ) (constant uint (17)) ) ) ) 
>                            (assign  (x) (var_ref compiler_temp@331)  (expression bool != (expression uint & (var_ref compiler_temp@328) (constant uint (32768)) ) (constant uint (0)) ) ) 
>                            (declare (temporary ) vec2 compiler_temp@333)
>                            (assign  (xy) (var_ref compiler_temp@333)  (expression vec2 unpackHalf2x16 (array_ref (var_ref fastuidraw_glyphDataStore_data) (expression int u2i (var_ref curve_src@332) ) ) ) ) 
>                            (declare (temporary ) vec2 compiler_temp@334)
>                            (assign  (xy) (var_ref compiler_temp@334)  (expression vec2 unpackHalf2x16 (array_ref (var_ref fastuidraw_glyphDataStore_data) (expression int u2i (expression uint + (var_ref curve_src@332) (constant uint (1)) ) ) ) ) ) 
>                            (assign  (xy) (var_ref compiler_temp@329)  (var_ref compiler_temp@334) ) 
>                            (if (var_ref compiler_temp@331) (
>                              (assign  (xy) (var_ref compiler_temp@330)  (expression vec2 unpackHalf2x16 (array_ref (var_ref fastuidraw_glyphDataStore_data) (expression int u2i (expression uint + (var_ref curve_src@332) (constant uint (2)) ) ) ) ) ) 
>                            )
>                            (
>                              (assign  (xy) (var_ref compiler_temp@330)  (var_ref compiler_temp@334) ) 
>                              (assign  (xy) (var_ref compiler_temp@329)  (expression vec2 * (constant float (0.500000)) (expression vec2 + (var_ref compiler_temp@333) (var_ref compiler_temp@334) ) ) ) 
>                            ))
>
>                            (declare (temporary ) float compiler_temp@335)
>                            (declare (temporary ) float compiler_temp@336)
>                            (assign  (x) (var_ref compiler_temp@335)  (var_ref compiler_temp@288) ) 
>                            (assign  (x) (var_ref compiler_temp@336)  (var_ref compiler_temp@289) ) 
>                            (declare () uvec2 code@337)
>                            (declare () int R@338)
>                            (declare () vec2 B@339)
>                            (declare () vec2 A@340)
>                            (assign  (x) (var_ref R@338)  (constant int (0)) ) 
>                            (declare (temporary ) vec2 compiler_temp@341)
>                            (assign  (xy) (var_ref compiler_temp@341)  (expression vec2 + (var_ref compiler_temp@333) (expression vec2 neg (swiz xy (var_ref fastuidraw_float_smooth_varying0) )) ) ) 
>                            (declare (temporary ) vec2 compiler_temp@342)
>                            (assign  (x) (var_ref compiler_temp@342)  (expression float dot (var_ref compiler_temp@277) (var_ref compiler_temp@341) ) ) 
>                            (assign  (y) (var_ref compiler_temp@342)  (expression float dot (var_ref compiler_temp@278) (var_ref compiler_temp@341) ) ) 
>                            (declare (temporary ) vec2 compiler_temp@343)
>                            (assign  (xy) (var_ref compiler_temp@343)  (expression vec2 + (var_ref compiler_temp@329) (expression vec2 neg (swiz xy (var_ref fastuidraw_float_smooth_varying0) )) ) ) 
>                            (declare (temporary ) vec2 compiler_temp@344)
>                            (assign  (x) (var_ref compiler_temp@344)  (expression float dot (var_ref compiler_temp@277) (var_ref compiler_temp@343) ) ) 
>                            (assign  (y) (var_ref compiler_temp@344)  (expression float dot (var_ref compiler_temp@278) (var_ref compiler_temp@343) ) ) 
>                            (declare (temporary ) vec2 compiler_temp@345)
>                            (assign  (xy) (var_ref compiler_temp@345)  (expression vec2 + (var_ref compiler_temp@330) (expression vec2 neg (swiz xy (var_ref fastuidraw_float_smooth_varying0) )) ) ) 
>                            (declare (temporary ) vec2 compiler_temp@346)
>                            (assign  (x) (var_ref compiler_temp@346)  (expression float dot (var_ref compiler_temp@277) (var_ref compiler_temp@345) ) ) 
>                            (assign  (y) (var_ref compiler_temp@346)  (expression float dot (var_ref compiler_temp@278) (var_ref compiler_temp@345) ) ) 
>                            (assign  (xy) (var_ref A@340)  (expression vec2 + (expression vec2 + (var_ref compiler_temp@342) (expression vec2 neg (expression vec2 * (constant float (2.000000)) (var_ref compiler_temp@344) ) ) ) (var_ref compiler_temp@346) ) ) 
>                            (assign  (xy) (var_ref B@339)  (expression vec2 + (var_ref compiler_temp@342) (expression vec2 neg (var_ref compiler_temp@344) ) ) ) 
>                            (declare (temporary ) uint compiler_temp@347)
>                            (declare (temporary ) uint compiler_temp@348)
>                            (if (expression bool < (constant float (0.000000)) (swiz x (var_ref compiler_temp@342) )) (
>                              (assign  (x) (var_ref compiler_temp@348)  (constant uint (2)) ) 
>                            )
>                            (
>                              (assign  (x) (var_ref compiler_temp@348)  (constant uint (0)) ) 
>                            ))
>
>                            (declare (temporary ) uint compiler_temp@349)
>                            (if (expression bool < (constant float (0.000000)) (swiz x (var_ref compiler_temp@344) )) (
>                              (assign  (x) (var_ref compiler_temp@349)  (constant uint (4)) ) 
>                            )
>                            (
>                              (assign  (x) (var_ref compiler_temp@349)  (constant uint (0)) ) 
>                            ))
>
>                            (declare (temporary ) uint compiler_temp@350)
>                            (if (expression bool < (constant float (0.000000)) (swiz x (var_ref compiler_temp@346) )) (
>                              (assign  (x) (var_ref compiler_temp@350)  (constant uint (8)) ) 
>                            )
>                            (
>                              (assign  (x) (var_ref compiler_temp@350)  (constant uint (0)) ) 
>                            ))
>
>                            (assign  (x) (var_ref compiler_temp@347)  (expression uint & (expression uint >> (constant uint (11892)) (expression uint + (expression uint + (var_ref compiler_temp@348) (var_ref compiler_temp@349) ) (var_ref compiler_temp@350) ) ) (constant uint (3)) ) ) 
>                            (assign  (x) (var_ref code@337)  (var_ref compiler_temp@347) ) 
>                            (declare (temporary ) uint compiler_temp@351)
>                            (declare (temporary ) uint compiler_temp@352)
>                            (if (expression bool < (constant float (0.000000)) (swiz y (var_ref compiler_temp@342) )) (
>                              (assign  (x) (var_ref compiler_temp@352)  (constant uint (2)) ) 
>                            )
>                            (
>                              (assign  (x) (var_ref compiler_temp@352)  (constant uint (0)) ) 
>                            ))
>
>                            (declare (temporary ) uint compiler_temp@353)
>                            (if (expression bool < (constant float (0.000000)) (swiz y (var_ref compiler_temp@344) )) (
>                              (assign  (x) (var_ref compiler_temp@353)  (constant uint (4)) ) 
>                            )
>                            (
>                              (assign  (x) (var_ref compiler_temp@353)  (constant uint (0)) ) 
>                            ))
>
>                            (declare (temporary ) uint compiler_temp@354)
>                            (if (expression bool < (constant float (0.000000)) (swiz y (var_ref compiler_temp@346) )) (
>                              (assign  (x) (var_ref compiler_temp@354)  (constant uint (8)) ) 
>                            )
>                            (
>                              (assign  (x) (var_ref compiler_temp@354)  (constant uint (0)) ) 
>                            ))
>
>                            (assign  (x) (var_ref compiler_temp@351)  (expression uint & (expression uint >> (constant uint (11892)) (expression uint + (expression uint + (var_ref compiler_temp@352) (var_ref compiler_temp@353) ) (var_ref compiler_temp@354) ) ) (constant uint (3)) ) ) 
>                            (assign  (y) (var_ref code@337)  (var_ref compiler_temp@351) ) 
>                            (if (expression bool != (var_ref compiler_temp@351) (constant uint (0)) ) (
>                              (declare () float x2@355)
>                              (declare () float x1@356)
>                              (declare () float t2@357)
>                              (declare () float t1@358)
>                              (declare (temporary ) bool compiler_temp@359)
>                              (if (var_ref compiler_temp@331) (
>                                (assign  (x) (var_ref compiler_temp@359)  (expression bool < (constant float (0.000100)) (expression float abs (swiz y (var_ref A@340) )) ) ) 
>                              )
>                              (
>                                (assign  (x) (var_ref compiler_temp@359)  (constant bool (0)) ) 
>                              ))
>
>                              (if (var_ref compiler_temp@359) (
>                                (declare () float D@360)
>                                (declare (temporary ) float compiler_temp@361)
>                                (assign  (x) (var_ref compiler_temp@361)  (expression float rcp (swiz y (var_ref A@340) )) ) 
>                                (assign  (x) (var_ref D@360)  (expression float + (expression float * (swiz y (var_ref B@339) )(swiz y (var_ref B@339) )) (expression float neg (expression float * (swiz y (var_ref A@340) )(swiz y (var_ref compiler_temp@342) )) ) ) ) 
>                                (if (expression bool < (var_ref D@360) (constant float (0.000000)) ) (
>                                  (assign  (y) (var_ref code@337)  (constant uint (0)) ) 
>                                  (assign  (x) (var_ref D@360)  (constant float (0.000000)) ) 
>                                )
>                                ())
>
>                                (declare (temporary ) float compiler_temp@362)
>                                (assign  (x) (var_ref compiler_temp@362)  (expression float sqrt (var_ref D@360) ) ) 
>                                (assign  (x) (var_ref D@360)  (var_ref compiler_temp@362) ) 
>                                (assign  (x) (var_ref t1@358)  (expression float * (expression float + (swiz y (var_ref B@339) )(expression float neg (var_ref compiler_temp@362) ) ) (var_ref compiler_temp@361) ) ) 
>                                (assign  (x) (var_ref t2@357)  (expression float * (expression float + (swiz y (var_ref B@339) )(var_ref compiler_temp@362) ) (var_ref compiler_temp@361) ) ) 
>                              )
>                              (
>                                (declare (temporary ) float compiler_temp@363)
>                                (assign  (x) (var_ref compiler_temp@363)  (expression float * (expression float * (constant float (0.500000)) (swiz y (var_ref compiler_temp@342) )) (expression float rcp (swiz y (var_ref B@339) )) ) ) 
>                                (assign  (x) (var_ref t2@357)  (var_ref compiler_temp@363) ) 
>                                (assign  (x) (var_ref t1@358)  (var_ref compiler_temp@363) ) 
>                              ))
>
>                              (assign  (x) (var_ref x1@356)  (expression float + (expression float * (expression float + (expression float * (swiz x (var_ref A@340) )(var_ref t1@358) ) (expression float neg (expression float * (swiz x (var_ref B@339) )(constant float (2.000000)) ) ) ) (var_ref t1@358) ) (swiz x (var_ref compiler_temp@342) )) ) 
>                              (assign  (x) (var_ref x2@355)  (expression float + (expression float * (expression float + (expression float * (swiz x (var_ref A@340) )(var_ref t2@357) ) (expression float neg (expression float * (swiz x (var_ref B@339) )(constant float (2.000000)) ) ) ) (var_ref t2@357) ) (swiz x (var_ref compiler_temp@342) )) ) 
>                              (if (expression bool != (expression uint & (swiz y (var_ref code@337) )(constant uint (1)) ) (constant uint (0)) ) (
>                                (if (expression bool && (expression bool >= (var_ref compiler_temp@279) (var_ref x1@356) ) (expression bool >= (var_ref x1@356) (constant float (0.000000)) ) ) (
>                                  (assign  (x) (var_ref R@338)  (constant int (1)) ) 
>                                )
>                                ())
>
>                                (declare (temporary ) float compiler_temp@364)
>                                (assign  (x) (var_ref compiler_temp@364)  (expression float abs (var_ref x1@356) ) ) 
>                                (declare (temporary ) float compiler_temp@365)
>                                (declare (temporary ) float compiler_temp@366)
>                                (assign  (x) (var_ref compiler_temp@365)  (var_ref compiler_temp@288) ) 
>                                (assign  (x) (var_ref compiler_temp@366)  (var_ref compiler_temp@289) ) 
>                                (if (expression bool < (var_ref x1@356) (constant float (0.000000)) ) (
>                                  (assign  (x) (var_ref compiler_temp@365)  (expression float min (var_ref compiler_temp@288) (var_ref compiler_temp@364) ) ) 
>                                )
>                                (
>                                  (assign  (x) (var_ref compiler_temp@366)  (expression float min (var_ref compiler_temp@289) (var_ref compiler_temp@364) ) ) 
>                                ))
>
>                                (assign  (x) (var_ref compiler_temp@335)  (var_ref compiler_temp@365) ) 
>                                (assign  (x) (var_ref compiler_temp@336)  (var_ref compiler_temp@366) ) 
>                              )
>                              ())
>
>                              (if (expression bool < (constant uint (1)) (swiz y (var_ref code@337) )) (
>                                (if (expression bool && (expression bool >= (var_ref compiler_temp@279) (var_ref x2@355) ) (expression bool >= (var_ref x2@355) (constant float (0.000000)) ) ) (
>                                  (assign  (x) (var_ref R@338)  (expression int + (var_ref R@338) (constant int (-1)) ) ) 
>                                )
>                                ())
>
>                                (declare (temporary ) float compiler_temp@367)
>                                (assign  (x) (var_ref compiler_temp@367)  (expression float abs (var_ref x2@355) ) ) 
>                                (declare (temporary ) float compiler_temp@368)
>                                (declare (temporary ) float compiler_temp@369)
>                                (assign  (x) (var_ref compiler_temp@368)  (var_ref compiler_temp@335) ) 
>                                (assign  (x) (var_ref compiler_temp@369)  (var_ref compiler_temp@336) ) 
>                                (if (expression bool < (constant float (0.000000)) (var_ref x2@355) ) (
>                                  (assign  (x) (var_ref compiler_temp@368)  (expression float min (var_ref compiler_temp@335) (var_ref compiler_temp@367) ) ) 
>                                )
>                                (
>                                  (assign  (x) (var_ref compiler_temp@369)  (expression float min (var_ref compiler_temp@336) (var_ref compiler_temp@367) ) ) 
>                                ))
>
>                                (assign  (x) (var_ref compiler_temp@335)  (var_ref compiler_temp@368) ) 
>                                (assign  (x) (var_ref compiler_temp@336)  (var_ref compiler_temp@369) ) 
>                              )
>                              ())
>
>                            )
>                            ())
>
>                            (if (expression bool != (var_ref compiler_temp@347) (constant uint (0)) ) (
>                              (declare () float y2@370)
>                              (declare () float y1@371)
>                              (declare () float t2@372)
>                              (declare () float t1@373)
>                              (declare (temporary ) bool compiler_temp@374)
>                              (if (var_ref compiler_temp@331) (
>                                (assign  (x) (var_ref compiler_temp@374)  (expression bool < (constant float (0.000100)) (expression float abs (swiz x (var_ref A@340) )) ) ) 
>                              )
>                              (
>                                (assign  (x) (var_ref compiler_temp@374)  (constant bool (0)) ) 
>                              ))
>
>                              (if (var_ref compiler_temp@374) (
>                                (declare () float D@375)
>                                (declare (temporary ) float compiler_temp@376)
>                                (assign  (x) (var_ref compiler_temp@376)  (expression float rcp (swiz x (var_ref A@340) )) ) 
>                                (assign  (x) (var_ref D@375)  (expression float + (expression float * (swiz x (var_ref B@339) )(swiz x (var_ref B@339) )) (expression float neg (expression float * (swiz x (var_ref A@340) )(swiz x (var_ref compiler_temp@342) )) ) ) ) 
>                                (if (expression bool < (var_ref D@375) (constant float (0.000000)) ) (
>                                  (assign  (x) (var_ref code@337)  (constant uint (0)) ) 
>                                  (assign  (x) (var_ref D@375)  (constant float (0.000000)) ) 
>                                )
>                                ())
>
>                                (declare (temporary ) float compiler_temp@377)
>                                (assign  (x) (var_ref compiler_temp@377)  (expression float sqrt (var_ref D@375) ) ) 
>                                (assign  (x) (var_ref D@375)  (var_ref compiler_temp@377) ) 
>                                (assign  (x) (var_ref t1@373)  (expression float * (expression float + (swiz x (var_ref B@339) )(expression float neg (var_ref compiler_temp@377) ) ) (var_ref compiler_temp@376) ) ) 
>                                (assign  (x) (var_ref t2@372)  (expression float * (expression float + (swiz x (var_ref B@339) )(var_ref compiler_temp@377) ) (var_ref compiler_temp@376) ) ) 
>                              )
>                              (
>                                (declare (temporary ) float compiler_temp@378)
>                                (assign  (x) (var_ref compiler_temp@378)  (expression float * (expression float * (constant float (0.500000)) (swiz x (var_ref compiler_temp@342) )) (expression float rcp (swiz x (var_ref B@339) )) ) ) 
>                                (assign  (x) (var_ref t2@372)  (var_ref compiler_temp@378) ) 
>                                (assign  (x) (var_ref t1@373)  (var_ref compiler_temp@378) ) 
>                              ))
>
>                              (assign  (x) (var_ref y1@371)  (expression float + (expression float * (expression float + (expression float * (swiz y (var_ref A@340) )(var_ref t1@373) ) (expression float neg (expression float * (swiz y (var_ref B@339) )(constant float (2.000000)) ) ) ) (var_ref t1@373) ) (swiz y (var_ref compiler_temp@342) )) ) 
>                              (assign  (x) (var_ref y2@370)  (expression float + (expression float * (expression float + (expression float * (swiz y (var_ref A@340) )(var_ref t2@372) ) (expression float neg (expression float * (swiz y (var_ref B@339) )(constant float (2.000000)) ) ) ) (var_ref t2@372) ) (swiz y (var_ref compiler_temp@342) )) ) 
>                              (if (expression bool != (expression uint & (swiz x (var_ref code@337) )(constant uint (1)) ) (constant uint (0)) ) (
>                                (declare (temporary ) float compiler_temp@379)
>                                (assign  (x) (var_ref compiler_temp@379)  (expression float abs (var_ref y1@371) ) ) 
>                                (declare (temporary ) float compiler_temp@380)
>                                (declare (temporary ) float compiler_temp@381)
>                                (assign  (x) (var_ref compiler_temp@380)  (var_ref compiler_temp@335) ) 
>                                (assign  (x) (var_ref compiler_temp@381)  (var_ref compiler_temp@336) ) 
>                                (if (expression bool < (constant float (0.000000)) (var_ref y1@371) ) (
>                                  (assign  (x) (var_ref compiler_temp@380)  (expression float min (var_ref compiler_temp@335) (var_ref compiler_temp@379) ) ) 
>                                )
>                                (
>                                  (assign  (x) (var_ref compiler_temp@381)  (expression float min (var_ref compiler_temp@336) (var_ref compiler_temp@379) ) ) 
>                                ))
>
>                                (assign  (x) (var_ref compiler_temp@335)  (var_ref compiler_temp@380) ) 
>                                (assign  (x) (var_ref compiler_temp@336)  (var_ref compiler_temp@381) ) 
>                              )
>                              ())
>
>                              (if (expression bool < (constant uint (1)) (swiz x (var_ref code@337) )) (
>                                (declare (temporary ) float compiler_temp@382)
>                                (assign  (x) (var_ref compiler_temp@382)  (expression float abs (var_ref y2@370) ) ) 
>                                (declare (temporary ) float compiler_temp@383)
>                                (declare (temporary ) float compiler_temp@384)
>                                (assign  (x) (var_ref compiler_temp@383)  (var_ref compiler_temp@335) ) 
>                                (assign  (x) (var_ref compiler_temp@384)  (var_ref compiler_temp@336) ) 
>                                (if (expression bool < (var_ref y2@370) (constant float (0.000000)) ) (
>                                  (assign  (x) (var_ref compiler_temp@383)  (expression float min (var_ref compiler_temp@335) (var_ref compiler_temp@382) ) ) 
>                                )
>                                (
>                                  (assign  (x) (var_ref compiler_temp@384)  (expression float min (var_ref compiler_temp@336) (var_ref compiler_temp@382) ) ) 
>                                ))
>
>                                (assign  (x) (var_ref compiler_temp@335)  (var_ref compiler_temp@383) ) 
>                                (assign  (x) (var_ref compiler_temp@336)  (var_ref compiler_temp@384) ) 
>                              )
>                              ())
>
>                            )
>                            ())
>
>                            (assign  (x) (var_ref nv_distance_increment)  (var_ref compiler_temp@335) ) 
>                            (assign  (x) (var_ref nv_distance_decrement)  (var_ref compiler_temp@336) ) 
>                            (assign  (x) (var_ref winding_number)  (expression int + (var_ref winding_number) (var_ref R@338) ) ) 
>                          )
>                          ())
>
>                          (assign  (x) (var_ref c)  (expression uint + (var_ref c) (constant uint (2)) ) ) 
>                        ))
>
>                        (if (expression bool || (expression bool == (var_ref winding_number) (constant int (0)) ) (var_ref use_odd_even_rule) ) (
>                          (assign  (x) (var_ref distance)  (expression float min (var_ref nv_distance_increment) (var_ref nv_distance_decrement) ) ) 
>                        )
>                        (
>                          (if (expression bool == (var_ref winding_number) (constant int (-1)) ) (
>                            (assign  (x) (var_ref distance)  (var_ref nv_distance_increment) ) 
>                          )
>                          (
>                            (if (expression bool == (var_ref winding_number) (constant int (1)) ) (
>                              (assign  (x) (var_ref distance)  (var_ref nv_distance_decrement) ) 
>                            )
>                            (
>                              (assign  (x) (var_ref distance)  (constant float (0.500000)) ) 
>                            ))
>
>                          ))
>
>                        ))
>
>                        (declare (temporary ) float compiler_temp@385)
>                        (assign  (x) (var_ref compiler_temp@385)  (expression float min (var_ref distance) (constant float (0.500000)) ) ) 
>                        (assign  (x) (var_ref distance)  (var_ref compiler_temp@385) ) 
>                        (declare (temporary ) int compiler_temp@386)
>                        (if (expression bool && (var_ref use_odd_even_rule) (expression bool == (expression int & (var_ref winding_number) (constant int (1)) ) (constant int (0)) ) ) (
>                          (assign  (x) (var_ref compiler_temp@386)  (constant int (0)) ) 
>                        )
>                        (
>                          (assign  (x) (var_ref compiler_temp@386)  (var_ref winding_number) ) 
>                        ))
>
>                        (assign  (x) (var_ref winding_number)  (var_ref compiler_temp@386) ) 
>                        (declare (temporary ) float compiler_temp@387)
>                        (if (expression bool != (var_ref compiler_temp@386) (constant int (0)) ) (
>                          (assign  (x) (var_ref compiler_temp@387)  (expression float + (constant float (0.500000)) (var_ref compiler_temp@385) ) ) 
>                        )
>                        (
>                          (assign  (x) (var_ref compiler_temp@387)  (expression float + (constant float (0.500000)) (expression float neg (var_ref compiler_temp@385) ) ) ) 
>                        ))
>
>                        (assign  (x) (var_ref cvg)  (var_ref compiler_temp@387) ) 
>                        (if (expression bool != (expression uint & (swiz x (var_ref fastuidraw_uint_varying0) )(constant uint (1073741824)) ) (constant uint (0)) ) (
>                          (assign  (x) (var_ref cvg)  (expression float + (constant float (1.000000)) (expression float neg (var_ref compiler_temp@387) ) ) ) 
>                        )
>                        ())
>
>                        (assign  (xyzw) (var_ref p@210)  (swiz xxxx (var_ref cvg) )) 
>                      )
>                      (
>                        (if (expression bool == (swiz y (var_ref fastuidraw_uint_varying1) )(constant uint (23)) ) (
>                          (declare () float cvg@388)
>                          (declare (temporary ) vec2 compiler_temp@389)
>                          (assign  (x) (var_ref compiler_temp@389)  (expression float + (expression float abs (expression float dFdx (swiz x (var_ref fastuidraw_float_smooth_varying0) )) ) (expression float abs (expression float dFdy (swiz x (var_ref fastuidraw_float_smooth_varying0) )) ) ) ) 
>                          (assign  (y) (var_ref compiler_temp@389)  (expression float + (expression float abs (expression float dFdx (swiz y (var_ref fastuidraw_float_smooth_varying0) )) ) (expression float abs (expression float dFdy (swiz y (var_ref fastuidraw_float_smooth_varying0) )) ) ) ) 
>                          (declare (temporary ) uint glyph_data_location@390)
>                          (assign  (x) (var_ref glyph_data_location@390)  (expression uint & (swiz x (var_ref fastuidraw_uint_varying0) )(constant uint (1073741823)) ) ) 
>                          (declare (temporary ) bool use_odd_even_rule@391)
>                          (assign  (x) (var_ref use_odd_even_rule@391)  (expression bool != (expression uint & (swiz x (var_ref fastuidraw_uint_varying0) )(constant uint (2147483648)) ) (constant uint (0)) ) ) 
>                          (declare () vec2 weight)
>                          (declare () float weight_sum)
>                          (declare () float sy)
>                          (declare () float sx)
>                          (declare () vec2 nearest_curve_distance)
>                          (declare () vec2 coverage)
>                          (declare () vec2 band_factor)
>                          (declare () vec2 em@392)
>                          (declare () uint vert_band_offset)
>                          (declare () uint horiz_band_offset)
>                          (assign  (xy) (var_ref em@392)  (expression vec2 rcp (var_ref compiler_temp@389) ) ) 
>                          (declare (temporary ) vec2 compiler_temp@393)
>                          (assign  (x) (var_ref compiler_temp@393)  (expression float u2f (swiz z (var_ref fastuidraw_uint_varying0) )) ) 
>                          (assign  (y) (var_ref compiler_temp@393)  (expression float u2f (swiz y (var_ref fastuidraw_uint_varying0) )) ) 
>                          (assign  (xy) (var_ref band_factor)  (expression vec2 * (constant float (0.015625)) (var_ref compiler_temp@393) ) ) 
>                          (declare (temporary ) uint compiler_temp@394)
>                          (assign  (x) (var_ref compiler_temp@394)  (expression uint min (expression uint + (swiz z (var_ref fastuidraw_uint_varying0) )(constant uint (4294967295)) ) (expression uint f2u (expression float * (swiz x (var_ref band_factor) )(expression float + (swiz x (var_ref fastuidraw_float_smooth_varying0) )(constant float (32.000000)) ) ) ) ) ) 
>                          (declare (temporary ) uint compiler_temp@395)
>                          (assign  (x) (var_ref compiler_temp@395)  (expression uint min (expression uint + (swiz y (var_ref fastuidraw_uint_varying0) )(constant uint (4294967295)) ) (expression uint f2u (expression float * (swiz y (var_ref band_factor) )(expression float + (swiz y (var_ref fastuidraw_float_smooth_varying0) )(constant float (32.000000)) ) ) ) ) ) 
>                          (assign  (x) (var_ref horiz_band_offset)  (var_ref compiler_temp@395) ) 
>                          (if (expression bool < (swiz x (var_ref fastuidraw_float_smooth_varying0) )(constant float (0.000000)) ) (
>                            (assign  (x) (var_ref horiz_band_offset)  (expression uint + (var_ref compiler_temp@395) (swiz y (var_ref fastuidraw_uint_varying0) )) ) 
>                            (assign  (x) (var_ref sx)  (constant float (-1.000000)) ) 
>                          )
>                          (
>                            (assign  (x) (var_ref sx)  (constant float (1.000000)) ) 
>                          ))
>
>                          (assign  (x) (var_ref vert_band_offset)  (expression uint + (var_ref compiler_temp@394) (expression uint * (constant uint (2)) (swiz y (var_ref fastuidraw_uint_varying0) )) ) ) 
>                          (if (expression bool < (swiz y (var_ref fastuidraw_float_smooth_varying0) )(constant float (0.000000)) ) (
>                            (assign  (x) (var_ref vert_band_offset)  (expression uint + (var_ref vert_band_offset) (swiz z (var_ref fastuidraw_uint_varying0) )) ) 
>                            (assign  (x) (var_ref sy)  (constant float (-1.000000)) ) 
>                          )
>                          (
>                            (assign  (x) (var_ref sy)  (constant float (1.000000)) ) 
>                          ))
>
>                          (declare () uint raw)
>                          (assign  (x) (var_ref raw)  (array_ref (var_ref fastuidraw_glyphDataStore_data) (expression int u2i (expression uint + (var_ref glyph_data_location@390) (var_ref horiz_band_offset) ) ) ) ) 
>                          (declare (temporary ) uint compiler_temp@396)
>                          (assign  (x) (var_ref compiler_temp@396)  (expression uint >> (expression uint << (var_ref raw) (constant uint (24)) ) (constant uint (24)) ) ) 
>                          (declare () uint raw@397)
>                          (assign  (x) (var_ref raw@397)  (array_ref (var_ref fastuidraw_glyphDataStore_data) (expression int u2i (expression uint + (var_ref glyph_data_location@390) (var_ref vert_band_offset) ) ) ) ) 
>                          (declare (temporary ) uint compiler_temp@398)
>                          (assign  (x) (var_ref compiler_temp@398)  (expression uint >> (expression uint << (var_ref raw@397) (constant uint (24)) ) (constant uint (24)) ) ) 
>                          (declare (temporary ) uint compiler_temp@399)
>                          (assign  (x) (var_ref compiler_temp@399)  (expression uint >> (var_ref raw@397) (constant uint (8)) ) ) 
>                          (declare (temporary ) float compiler_temp@400)
>                          (declare (temporary ) float compiler_temp@401)
>                          (declare () uint curve_src@402)
>                          (declare () uint c@403)
>                          (assign  (x) (var_ref compiler_temp@400)  (constant float (0.000000)) ) 
>                          (assign  (x) (var_ref compiler_temp@401)  (constant float (0.500000)) ) 
>                          (assign  (x) (var_ref c@403)  (constant uint (0)) ) 
>                          (assign  (x) (var_ref curve_src@402)  (expression uint + (expression uint >> (var_ref raw) (constant uint (8)) ) (var_ref glyph_data_location@390) ) ) 
>                          (loop (
>                            (declare () vec2 curve_p0)
>                            (declare () vec2 curve_p1)
>                            (declare () vec2 curve_p2)
>                            (if (expression bool >= (var_ref c@403) (var_ref compiler_temp@396) ) (
>                              break
>                            )
>                            ())
>
>                            (assign  (xy) (var_ref curve_p0)  (expression vec2 + (expression vec2 unpackHalf2x16 (array_ref (var_ref fastuidraw_glyphDataStore_data) (expression int u2i (var_ref curve_src@402) ) ) ) (expression vec2 neg (swiz xy (var_ref fastuidraw_float_smooth_varying0) )) ) ) 
>                            (assign  (xy) (var_ref curve_p1)  (expression vec2 + (expression vec2 unpackHalf2x16 (array_ref (var_ref fastuidraw_glyphDataStore_data) (expression int u2i (expression uint + (var_ref curve_src@402) (constant uint (1)) ) ) ) ) (expression vec2 neg (swiz xy (var_ref fastuidraw_float_smooth_varying0) )) ) ) 
>                            (assign  (xy) (var_ref curve_p2)  (expression vec2 + (expression vec2 unpackHalf2x16 (array_ref (var_ref fastuidraw_glyphDataStore_data) (expression int u2i (expression uint + (var_ref curve_src@402) (constant uint (2)) ) ) ) ) (expression vec2 neg (swiz xy (var_ref fastuidraw_float_smooth_varying0) )) ) ) 
>                            (declare (temporary ) bool compiler_temp@404)
>                            (if (expression bool < (constant float (0.000000)) (var_ref sx) ) (
>                              (assign  (x) (var_ref compiler_temp@404)  (expression bool < (expression float * (expression float max (swiz x (var_ref curve_p0) )(expression float max (swiz x (var_ref curve_p1) )(swiz x (var_ref curve_p2) )) ) (swiz x (var_ref em@392) )) (constant float (-0.500000)) ) ) 
>                            )
>                            (
>                              (assign  (x) (var_ref compiler_temp@404)  (constant bool (0)) ) 
>                            ))
>
>                            (if (var_ref compiler_temp@404) (
>                              break
>                            )
>                            ())
>
>                            (declare (temporary ) bool compiler_temp@405)
>                            (if (expression bool < (var_ref sx) (constant float (0.000000)) ) (
>                              (assign  (x) (var_ref compiler_temp@405)  (expression bool < (constant float (0.500000)) (expression float * (expression float min (swiz x (var_ref curve_p0) )(expression float min (swiz x (var_ref curve_p1) )(swiz x (var_ref curve_p2) )) ) (swiz x (var_ref em@392) )) ) ) 
>                            )
>                            (
>                              (assign  (x) (var_ref compiler_temp@405)  (constant bool (0)) ) 
>                            ))
>
>                            (if (var_ref compiler_temp@405) (
>                              break
>                            )
>                            ())
>
>                            (declare () uint code@406)
>                            (declare (temporary ) uint compiler_temp@407)
>                            (if (expression bool < (constant float (0.000000)) (swiz y (var_ref curve_p0) )) (
>                              (assign  (x) (var_ref compiler_temp@407)  (constant uint (2)) ) 
>                            )
>                            (
>                              (assign  (x) (var_ref compiler_temp@407)  (constant uint (0)) ) 
>                            ))
>
>                            (declare (temporary ) uint compiler_temp@408)
>                            (if (expression bool < (constant float (0.000000)) (swiz y (var_ref curve_p1) )) (
>                              (assign  (x) (var_ref compiler_temp@408)  (constant uint (4)) ) 
>                            )
>                            (
>                              (assign  (x) (var_ref compiler_temp@408)  (constant uint (0)) ) 
>                            ))
>
>                            (declare (temporary ) uint compiler_temp@409)
>                            (if (expression bool < (constant float (0.000000)) (swiz y (var_ref curve_p2) )) (
>                              (assign  (x) (var_ref compiler_temp@409)  (constant uint (8)) ) 
>                            )
>                            (
>                              (assign  (x) (var_ref compiler_temp@409)  (constant uint (0)) ) 
>                            ))
>
>                            (assign  (x) (var_ref code@406)  (expression uint | (expression uint | (var_ref compiler_temp@407) (var_ref compiler_temp@408) ) (var_ref compiler_temp@409) ) ) 
>                            (assign  (x) (var_ref code@406)  (expression uint & (expression uint >> (constant uint (11892)) (var_ref code@406) ) (constant uint (3)) ) ) 
>                            (if (expression bool != (var_ref code@406) (constant uint (0)) ) (
>                              (declare () vec2 x1x2)
>                              (declare () vec2 B@410)
>                              (declare () vec2 A@411)
>                              (declare () float t2@412)
>                              (declare () float t1@413)
>                              (declare () float rA)
>                              (assign  (xy) (var_ref A@411)  (expression vec2 + (expression vec2 + (var_ref curve_p0) (expression vec2 neg (expression vec2 * (constant float (2.000000)) (var_ref curve_p1) ) ) ) (var_ref curve_p2) ) ) 
>                              (assign  (xy) (var_ref B@410)  (expression vec2 + (var_ref curve_p0) (expression vec2 neg (var_ref curve_p1) ) ) ) 
>                              (assign  (x) (var_ref rA)  (expression float rcp (swiz y (var_ref A@411) )) ) 
>                              (declare (temporary ) float compiler_temp@414)
>                              (assign  (x) (var_ref compiler_temp@414)  (expression float sqrt (expression float max (expression float + (expression float * (swiz y (var_ref B@410) )(swiz y (var_ref B@410) )) (expression float neg (expression float * (swiz y (var_ref A@411) )(swiz y (var_ref curve_p0) )) ) ) (constant float (0.000000)) ) ) ) 
>                              (assign  (x) (var_ref t1@413)  (expression float * (expression float + (swiz y (var_ref B@410) )(expression float neg (var_ref compiler_temp@414) ) ) (var_ref rA) ) ) 
>                              (assign  (x) (var_ref t2@412)  (expression float * (expression float + (swiz y (var_ref B@410) )(var_ref compiler_temp@414) ) (var_ref rA) ) ) 
>                              (declare (temporary ) float compiler_temp@415)
>                              (assign  (x) (var_ref compiler_temp@415)  (expression float abs (swiz y (var_ref A@411) )) ) 
>                              (if (expression bool < (var_ref compiler_temp@415) (constant float (0.000100)) ) (
>                                (declare (temporary ) float compiler_temp@416)
>                                (assign  (x) (var_ref compiler_temp@416)  (expression float * (expression float * (constant float (0.500000)) (swiz y (var_ref curve_p0) )) (expression float rcp (swiz y (var_ref B@410) )) ) ) 
>                                (assign  (x) (var_ref t2@412)  (var_ref compiler_temp@416) ) 
>                                (assign  (x) (var_ref t1@413)  (var_ref compiler_temp@416) ) 
>                              )
>                              ())
>
>                              (declare (temporary ) vec2 compiler_temp@417)
>                              (assign  (x) (var_ref compiler_temp@417)  (expression float + (expression float * (expression float + (expression float * (swiz x (var_ref A@411) )(var_ref t1@413) ) (expression float neg (expression float * (swiz x (var_ref B@410) )(constant float (2.000000)) ) ) ) (var_ref t1@413) ) (swiz x (var_ref curve_p0) )) ) 
>                              (assign  (y) (var_ref compiler_temp@417)  (expression float + (expression float * (expression float + (expression float * (swiz x (var_ref A@411) )(var_ref t2@412) ) (expression float neg (expression float * (swiz x (var_ref B@410) )(constant float (2.000000)) ) ) ) (var_ref t2@412) ) (swiz x (var_ref curve_p0) )) ) 
>                              (assign  (xy) (var_ref x1x2)  (expression vec2 * (swiz x (var_ref em@392) )(var_ref compiler_temp@417) ) ) 
>                              (if (expression bool != (expression uint & (var_ref code@406) (constant uint (1)) ) (constant uint (0)) ) (
>                                (assign  (x) (var_ref compiler_temp@400)  (expression float + (var_ref compiler_temp@400) (expression float sat (expression float + (constant float (0.500000)) (expression float * (swiz x (var_ref x1x2) )(var_ref sx) ) ) ) ) ) 
>                                (assign  (x) (var_ref compiler_temp@401)  (expression float min (var_ref compiler_temp@401) (expression float abs (swiz x (var_ref x1x2) )) ) ) 
>                              )
>                              ())
>
>                              (if (expression bool < (constant uint (1)) (var_ref code@406) ) (
>                                (assign  (x) (var_ref compiler_temp@400)  (expression float + (var_ref compiler_temp@400) (expression float neg (expression float sat (expression float + (constant float (0.500000)) (expression float * (swiz y (var_ref x1x2) )(var_ref sx) ) ) ) ) ) ) 
>                                (assign  (x) (var_ref compiler_temp@401)  (expression float min (var_ref compiler_temp@401) (expression float abs (swiz y (var_ref x1x2) )) ) ) 
>                              )
>                              ())
>
>                            )
>                            ())
>
>                            (assign  (x) (var_ref curve_src@402)  (expression uint + (var_ref curve_src@402) (constant uint (3)) ) ) 
>                            (assign  (x) (var_ref c@403)  (expression uint + (var_ref c@403) (constant uint (1)) ) ) 
>                          ))
>
>                          (assign  (x) (var_ref compiler_temp@400)  (expression float abs (var_ref compiler_temp@400) ) ) 
>                          (assign  (x) (var_ref coverage)  (var_ref compiler_temp@400) ) 
>                          (assign  (x) (var_ref nearest_curve_distance)  (var_ref compiler_temp@401) ) 
>                          (declare (temporary ) float compiler_temp@418)
>                          (declare (temporary ) float compiler_temp@419)
>                          (declare () uint curve_src@420)
>                          (declare () uint c@421)
>                          (assign  (x) (var_ref compiler_temp@418)  (constant float (0.000000)) ) 
>                          (assign  (x) (var_ref compiler_temp@419)  (constant float (0.500000)) ) 
>                          (assign  (x) (var_ref c@421)  (constant uint (0)) ) 
>                          (assign  (x) (var_ref curve_src@420)  (expression uint + (var_ref compiler_temp@399) (var_ref glyph_data_location@390) ) ) 
>                          (loop (
>                            (declare () vec2 curve_p0@422)
>                            (declare () vec2 curve_p1@423)
>                            (declare () vec2 curve_p2@424)
>                            (if (expression bool >= (var_ref c@421) (var_ref compiler_temp@398) ) (
>                              break
>                            )
>                            ())
>
>                            (assign  (xy) (var_ref curve_p0@422)  (expression vec2 + (expression vec2 unpackHalf2x16 (array_ref (var_ref fastuidraw_glyphDataStore_data) (expression int u2i (var_ref curve_src@420) ) ) ) (expression vec2 neg (swiz yx (var_ref fastuidraw_float_smooth_varying0) )) ) ) 
>                            (assign  (xy) (var_ref curve_p1@423)  (expression vec2 + (expression vec2 unpackHalf2x16 (array_ref (var_ref fastuidraw_glyphDataStore_data) (expression int u2i (expression uint + (var_ref curve_src@420) (constant uint (1)) ) ) ) ) (expression vec2 neg (swiz yx (var_ref fastuidraw_float_smooth_varying0) )) ) ) 
>                            (assign  (xy) (var_ref curve_p2@424)  (expression vec2 + (expression vec2 unpackHalf2x16 (array_ref (var_ref fastuidraw_glyphDataStore_data) (expression int u2i (expression uint + (var_ref curve_src@420) (constant uint (2)) ) ) ) ) (expression vec2 neg (swiz yx (var_ref fastuidraw_float_smooth_varying0) )) ) ) 
>                            (declare (temporary ) bool compiler_temp@425)
>                            (if (expression bool < (constant float (0.000000)) (var_ref sy) ) (
>                              (assign  (x) (var_ref compiler_temp@425)  (expression bool < (expression float * (expression float max (swiz x (var_ref curve_p0@422) )(expression float max (swiz x (var_ref curve_p1@423) )(swiz x (var_ref curve_p2@424) )) ) (swiz y (var_ref em@392) )) (constant float (-0.500000)) ) ) 
>                            )
>                            (
>                              (assign  (x) (var_ref compiler_temp@425)  (constant bool (0)) ) 
>                            ))
>
>                            (if (var_ref compiler_temp@425) (
>                              break
>                            )
>                            ())
>
>                            (declare (temporary ) bool compiler_temp@426)
>                            (if (expression bool < (var_ref sy) (constant float (0.000000)) ) (
>                              (assign  (x) (var_ref compiler_temp@426)  (expression bool < (constant float (0.500000)) (expression float * (expression float min (swiz x (var_ref curve_p0@422) )(expression float min (swiz x (var_ref curve_p1@423) )(swiz x (var_ref curve_p2@424) )) ) (swiz y (var_ref em@392) )) ) ) 
>                            )
>                            (
>                              (assign  (x) (var_ref compiler_temp@426)  (constant bool (0)) ) 
>                            ))
>
>                            (if (var_ref compiler_temp@426) (
>                              break
>                            )
>                            ())
>
>                            (declare () uint code@427)
>                            (declare (temporary ) uint compiler_temp@428)
>                            (if (expression bool < (constant float (0.000000)) (swiz y (var_ref curve_p0@422) )) (
>                              (assign  (x) (var_ref compiler_temp@428)  (constant uint (2)) ) 
>                            )
>                            (
>                              (assign  (x) (var_ref compiler_temp@428)  (constant uint (0)) ) 
>                            ))
>
>                            (declare (temporary ) uint compiler_temp@429)
>                            (if (expression bool < (constant float (0.000000)) (swiz y (var_ref curve_p1@423) )) (
>                              (assign  (x) (var_ref compiler_temp@429)  (constant uint (4)) ) 
>                            )
>                            (
>                              (assign  (x) (var_ref compiler_temp@429)  (constant uint (0)) ) 
>                            ))
>
>                            (declare (temporary ) uint compiler_temp@430)
>                            (if (expression bool < (constant float (0.000000)) (swiz y (var_ref curve_p2@424) )) (
>                              (assign  (x) (var_ref compiler_temp@430)  (constant uint (8)) ) 
>                            )
>                            (
>                              (assign  (x) (var_ref compiler_temp@430)  (constant uint (0)) ) 
>                            ))
>
>                            (assign  (x) (var_ref code@427)  (expression uint | (expression uint | (var_ref compiler_temp@428) (var_ref compiler_temp@429) ) (var_ref compiler_temp@430) ) ) 
>                            (assign  (x) (var_ref code@427)  (expression uint & (expression uint >> (constant uint (11892)) (var_ref code@427) ) (constant uint (3)) ) ) 
>                            (if (expression bool != (var_ref code@427) (constant uint (0)) ) (
>                              (declare () vec2 x1x2@431)
>                              (declare () vec2 B@432)
>                              (declare () vec2 A@433)
>                              (declare () float t2@434)
>                              (declare () float t1@435)
>                              (declare () float rA@436)
>                              (assign  (xy) (var_ref A@433)  (expression vec2 + (expression vec2 + (var_ref curve_p0@422) (expression vec2 neg (expression vec2 * (constant float (2.000000)) (var_ref curve_p1@423) ) ) ) (var_ref curve_p2@424) ) ) 
>                              (assign  (xy) (var_ref B@432)  (expression vec2 + (var_ref curve_p0@422) (expression vec2 neg (var_ref curve_p1@423) ) ) ) 
>                              (assign  (x) (var_ref rA@436)  (expression float rcp (swiz y (var_ref A@433) )) ) 
>                              (declare (temporary ) float compiler_temp@437)
>                              (assign  (x) (var_ref compiler_temp@437)  (expression float sqrt (expression float max (expression float + (expression float * (swiz y (var_ref B@432) )(swiz y (var_ref B@432) )) (expression float neg (expression float * (swiz y (var_ref A@433) )(swiz y (var_ref curve_p0@422) )) ) ) (constant float (0.000000)) ) ) ) 
>                              (assign  (x) (var_ref t1@435)  (expression float * (expression float + (swiz y (var_ref B@432) )(expression float neg (var_ref compiler_temp@437) ) ) (var_ref rA@436) ) ) 
>                              (assign  (x) (var_ref t2@434)  (expression float * (expression float + (swiz y (var_ref B@432) )(var_ref compiler_temp@437) ) (var_ref rA@436) ) ) 
>                              (declare (temporary ) float compiler_temp@438)
>                              (assign  (x) (var_ref compiler_temp@438)  (expression float abs (swiz y (var_ref A@433) )) ) 
>                              (if (expression bool < (var_ref compiler_temp@438) (constant float (0.000100)) ) (
>                                (declare (temporary ) float compiler_temp@439)
>                                (assign  (x) (var_ref compiler_temp@439)  (expression float * (expression float * (constant float (0.500000)) (swiz y (var_ref curve_p0@422) )) (expression float rcp (swiz y (var_ref B@432) )) ) ) 
>                                (assign  (x) (var_ref t2@434)  (var_ref compiler_temp@439) ) 
>                                (assign  (x) (var_ref t1@435)  (var_ref compiler_temp@439) ) 
>                              )
>                              ())
>
>                              (declare (temporary ) vec2 compiler_temp@440)
>                              (assign  (x) (var_ref compiler_temp@440)  (expression float + (expression float * (expression float + (expression float * (swiz x (var_ref A@433) )(var_ref t1@435) ) (expression float neg (expression float * (swiz x (var_ref B@432) )(constant float (2.000000)) ) ) ) (var_ref t1@435) ) (swiz x (var_ref curve_p0@422) )) ) 
>                              (assign  (y) (var_ref compiler_temp@440)  (expression float + (expression float * (expression float + (expression float * (swiz x (var_ref A@433) )(var_ref t2@434) ) (expression float neg (expression float * (swiz x (var_ref B@432) )(constant float (2.000000)) ) ) ) (var_ref t2@434) ) (swiz x (var_ref curve_p0@422) )) ) 
>                              (assign  (xy) (var_ref x1x2@431)  (expression vec2 * (swiz y (var_ref em@392) )(var_ref compiler_temp@440) ) ) 
>                              (if (expression bool != (expression uint & (var_ref code@427) (constant uint (1)) ) (constant uint (0)) ) (
>                                (assign  (x) (var_ref compiler_temp@418)  (expression float + (var_ref compiler_temp@418) (expression float sat (expression float + (constant float (0.500000)) (expression float * (swiz x (var_ref x1x2@431) )(var_ref sy) ) ) ) ) ) 
>                                (assign  (x) (var_ref compiler_temp@419)  (expression float min (var_ref compiler_temp@419) (expression float abs (swiz x (var_ref x1x2@431) )) ) ) 
>                              )
>                              ())
>
>                              (if (expression bool < (constant uint (1)) (var_ref code@427) ) (
>                                (assign  (x) (var_ref compiler_temp@418)  (expression float + (var_ref compiler_temp@418) (expression float neg (expression float sat (expression float + (constant float (0.500000)) (expression float * (swiz y (var_ref x1x2@431) )(var_ref sy) ) ) ) ) ) ) 
>                                (assign  (x) (var_ref compiler_temp@419)  (expression float min (var_ref compiler_temp@419) (expression float abs (swiz y (var_ref x1x2@431) )) ) ) 
>                              )
>                              ())
>
>                            )
>                            ())
>
>                            (assign  (x) (var_ref curve_src@420)  (expression uint + (var_ref curve_src@420) (constant uint (3)) ) ) 
>                            (assign  (x) (var_ref c@421)  (expression uint + (var_ref c@421) (constant uint (1)) ) ) 
>                          ))
>
>                          (assign  (x) (var_ref compiler_temp@418)  (expression float abs (var_ref compiler_temp@418) ) ) 
>                          (assign  (y) (var_ref coverage)  (var_ref compiler_temp@418) ) 
>                          (assign  (y) (var_ref nearest_curve_distance)  (var_ref compiler_temp@419) ) 
>                          (if (var_ref use_odd_even_rule@391) (
>                            (assign  (xy) (var_ref coverage)  (expression vec2 * (constant float (2.000000)) (expression vec2 fract (expression vec2 * (constant float (0.500000)) (var_ref coverage) ) ) ) ) 
>                          )
>                          ())
>
>                          (assign  (xy) (var_ref weight)  (expression vec2 + (constant vec2 (1.000000 1.000000)) (expression vec2 neg (expression vec2 * (constant float (2.000000)) (expression vec2 sat (expression vec2 min (expression vec2 abs (var_ref nearest_curve_distance) ) (constant float (0.500000)) ) ) ) ) ) ) 
>                          (assign  (x) (var_ref weight_sum)  (expression float + (swiz x (var_ref weight) )(swiz y (var_ref weight) )) ) 
>                          (declare (temporary ) float compiler_temp@441)
>                          (if (expression bool < (constant float (0.001000)) (var_ref weight_sum) ) (
>                            (assign  (x) (var_ref compiler_temp@441)  (expression float * (expression float dot (var_ref coverage) (var_ref weight) ) (expression float rcp (var_ref weight_sum) ) ) ) 
>                          )
>                          (
>                            (assign  (x) (var_ref compiler_temp@441)  (expression float * (constant float (0.500000)) (expression float + (swiz x (var_ref coverage) )(swiz y (var_ref coverage) )) ) ) 
>                          ))
>
>                          (assign  (x) (var_ref cvg@388)  (var_ref compiler_temp@441) ) 
>                          (if (expression bool != (expression uint & (swiz x (var_ref fastuidraw_uint_varying0) )(constant uint (1073741824)) ) (constant uint (0)) ) (
>                            (assign  (x) (var_ref cvg@388)  (expression float + (constant float (1.000000)) (expression float neg (var_ref compiler_temp@441) ) ) ) 
>                          )
>                          ())
>
>                          (assign  (xyzw) (var_ref p@210)  (swiz xxxx (var_ref cvg@388) )) 
>                        )
>                        ())
>
>                      ))
>
>                    ))
>
>                  ))
>
>                ))
>
>              ))
>
>            ))
>
>          ))
>
>        ))
>
>        (assign  (xyzw) (var_ref v)  (expression vec4 * (var_ref b) (var_ref p@210) ) ) 
>      )
>      (
>        (assign  (xyzw) (var_ref v)  (constant vec4 (0.000000 0.000000 0.000000 0.000000)) ) 
>      ))
>
>      (declare (temporary ) vec4 src0)
>      (declare (temporary ) vec4 src1)
>      (if (expression bool == (swiz w (var_ref fastuidraw_uint_varying1) )(constant uint (1)) ) (
>        (assign  (xyzw) (var_ref src0)  (constant vec4 (0.000000 0.000000 0.000000 0.000000)) ) 
>        (assign  (xyzw) (var_ref src1)  (constant vec4 (0.000000 0.000000 0.000000 0.000000)) ) 
>      )
>      (
>        (if (expression bool == (swiz w (var_ref fastuidraw_uint_varying1) )(constant uint (2)) ) (
>          (assign  (xyzw) (var_ref src0)  (var_ref v) ) 
>          (assign  (xyzw) (var_ref src1)  (constant vec4 (0.000000 0.000000 0.000000 0.000000)) ) 
>        )
>        (
>          (if (expression bool == (swiz w (var_ref fastuidraw_uint_varying1) )(constant uint (3)) ) (
>            (assign  (xyzw) (var_ref src0)  (constant vec4 (0.000000 0.000000 0.000000 0.000000)) ) 
>            (assign  (xyzw) (var_ref src1)  (constant vec4 (1.000000 1.000000 1.000000 1.000000)) ) 
>          )
>          (
>            (if (expression bool == (swiz w (var_ref fastuidraw_uint_varying1) )(constant uint (4)) ) (
>              (assign  (xyzw) (var_ref src0)  (var_ref v) ) 
>              (assign  (xyzw) (var_ref src1)  (swiz xxxx (expression float + (constant float (1.000000)) (expression float neg (swiz w (var_ref v) )) ) )) 
>            )
>            (
>              (if (expression bool == (swiz w (var_ref fastuidraw_uint_varying1) )(constant uint (5)) ) (
>                (assign  (xyzw) (var_ref src0)  (var_ref v) ) 
>                (assign  (xyzw) (var_ref src1)  (constant vec4 (1.000000 1.000000 1.000000 1.000000)) ) 
>              )
>              (
>                (if (expression bool == (swiz w (var_ref fastuidraw_uint_varying1) )(constant uint (6)) ) (
>                  (assign  (xyzw) (var_ref src0)  (var_ref v) ) 
>                  (assign  (xyzw) (var_ref src1)  (constant vec4 (0.000000 0.000000 0.000000 0.000000)) ) 
>                )
>                (
>                  (if (expression bool == (swiz w (var_ref fastuidraw_uint_varying1) )(constant uint (7)) ) (
>                    (assign  (xyzw) (var_ref src0)  (constant vec4 (0.000000 0.000000 0.000000 0.000000)) ) 
>                    (assign  (xyzw) (var_ref src1)  (swiz wwww (var_ref v) )) 
>                  )
>                  (
>                    (if (expression bool == (swiz w (var_ref fastuidraw_uint_varying1) )(constant uint (8)) ) (
>                      (assign  (xyzw) (var_ref src0)  (var_ref v) ) 
>                      (assign  (xyzw) (var_ref src1)  (constant vec4 (0.000000 0.000000 0.000000 0.000000)) ) 
>                    )
>                    (
>                      (if (expression bool == (swiz w (var_ref fastuidraw_uint_varying1) )(constant uint (9)) ) (
>                        (assign  (xyzw) (var_ref src0)  (constant vec4 (0.000000 0.000000 0.000000 0.000000)) ) 
>                        (assign  (xyzw) (var_ref src1)  (swiz xxxx (expression float + (constant float (1.000000)) (expression float neg (swiz w (var_ref v) )) ) )) 
>                      )
>                      (
>                        (if (expression bool == (swiz w (var_ref fastuidraw_uint_varying1) )(constant uint (10)) ) (
>                          (assign  (xyzw) (var_ref src0)  (var_ref v) ) 
>                          (assign  (xyzw) (var_ref src1)  (swiz xxxx (expression float + (constant float (1.000000)) (expression float neg (swiz w (var_ref v) )) ) )) 
>                        )
>                        (
>                          (if (expression bool == (swiz w (var_ref fastuidraw_uint_varying1) )(constant uint (11)) ) (
>                            (assign  (xyzw) (var_ref src0)  (var_ref v) ) 
>                            (assign  (xyzw) (var_ref src1)  (swiz wwww (var_ref v) )) 
>                          )
>                          (
>                            (if (expression bool == (swiz w (var_ref fastuidraw_uint_varying1) )(constant uint (12)) ) (
>                              (assign  (xyzw) (var_ref src0)  (var_ref v) ) 
>                              (assign  (xyzw) (var_ref src1)  (swiz xxxx (expression float + (constant float (1.000000)) (expression float neg (swiz w (var_ref v) )) ) )) 
>                            )
>                            (
>                              (if (expression bool == (swiz w (var_ref fastuidraw_uint_varying1) )(constant uint (13)) ) (
>                                (assign  (xyzw) (var_ref src0)  (var_ref v) ) 
>                                (assign  (xyzw) (var_ref src1)  (constant vec4 (1.000000 1.000000 1.000000 1.000000)) ) 
>                              )
>                              (
>                                (if (expression bool == (swiz w (var_ref fastuidraw_uint_varying1) )(constant uint (14)) ) (
>                                  (assign  (xyzw) (var_ref src0)  (constant vec4 (0.000000 0.000000 0.000000 0.000000)) ) 
>                                  (assign  (xyzw) (var_ref src1)  (var_ref v) ) 
>                                )
>                                (
>                                  (if (expression bool == (swiz w (var_ref fastuidraw_uint_varying1) )(constant uint (15)) ) (
>                                    (assign  (xyzw) (var_ref src0)  (var_ref v) ) 
>                                    (assign  (xyzw) (var_ref src1)  (expression vec4 + (constant vec4 (1.000000 1.000000 1.000000 1.000000)) (expression vec4 neg (var_ref v) ) ) ) 
>                                  )
>                                  ())
>
>                                ))
>
>                              ))
>
>                            ))
>
>                          ))
>
>                        ))
>
>                      ))
>
>                    ))
>
>                  ))
>
>                ))
>
>              ))
>
>            ))
>
>          ))
>
>        ))
>
>      ))
>
>      (assign  (xyzw) (var_ref fastuidraw_final_color0)  (var_ref src0) ) 
>      (assign  (xyzw) (var_ref fastuidraw_final_color1)  (var_ref src1) ) 
>    ))
>
>)
>
>)
>
>
>NIR (SSA form) for fragment shader:
>shader: MESA_SHADER_FRAGMENT
>name: GLSL1
>inputs: 0
>outputs: 0
>uniforms: 16
>shared: 0
>decl_var ssbo INTERP_MODE_NONE restrict readonly uvec4[] fastuidraw_painterStore (0, 0, 0)
>decl_var ssbo INTERP_MODE_NONE restrict readonly uint[] fastuidraw_glyphDataStore_data (0, 0, 1)
>decl_var ubo INTERP_MODE_NONE vec4[2] fastuidraw_uniforms (0, 0, 0)
>decl_var uniform INTERP_MODE_NONE sampler1DArray fastuidraw_colorStopAtlas (3, 0, 0)
>decl_var uniform INTERP_MODE_NONE sampler2DArray fastuidraw_imageAtlasLinear (4, 0, 1)
>decl_var uniform INTERP_MODE_NONE sampler2DArray fastuidraw_imageAtlasNearest (5, 0, 2)
>decl_var uniform INTERP_MODE_NONE usampler2DArray fastuidraw_imageIndexAtlas (6, 0, 3)
>decl_var uniform INTERP_MODE_NONE sampler2D[8] fastuidraw_external_texture (7, 0, 4)
>decl_var uniform INTERP_MODE_NONE sampler2D fastuidraw_deferred_coverage_buffer (8, 0, 12)
>decl_var uniform INTERP_MODE_NONE vec4 gl_FbWposYTransform (0, 0, 0)
>decl_var shader_in INTERP_MODE_SMOOTH vec4 gl_FragCoord (VARYING_SLOT_POS, 0, 0)
>decl_var shader_in INTERP_MODE_SMOOTH float fastuidraw_float_smooth_varying2 (VARYING_SLOT_VAR5.x, 36, 0)
>decl_var shader_in INTERP_MODE_FLAT uint fastuidraw_uint_varying2 (VARYING_SLOT_VAR2.x, 33, 0)
>decl_var shader_in INTERP_MODE_FLAT uint fastuidraw_uint_varying2@0 (VARYING_SLOT_VAR2.y, 33, 0)
>decl_var shader_in INTERP_MODE_FLAT uint fastuidraw_uint_varying2@1 (VARYING_SLOT_VAR2.w, 33, 0)
>decl_var shader_in INTERP_MODE_FLAT float fastuidraw_float_flat_varying4 (VARYING_SLOT_VAR10.x, 41, 0)
>decl_var shader_in INTERP_MODE_FLAT float fastuidraw_float_flat_varying4@2 (VARYING_SLOT_VAR10.y, 41, 0)
>decl_var shader_in INTERP_MODE_FLAT float fastuidraw_float_flat_varying4@3 (VARYING_SLOT_VAR10.z, 41, 0)
>decl_var shader_in INTERP_MODE_FLAT float fastuidraw_float_flat_varying4@4 (VARYING_SLOT_VAR10.w, 41, 0)
>decl_var shader_in INTERP_MODE_FLAT float fastuidraw_float_flat_varying5 (VARYING_SLOT_VAR11.x, 42, 0)
>decl_var shader_in INTERP_MODE_FLAT float fastuidraw_float_flat_varying5@5 (VARYING_SLOT_VAR11.y, 42, 0)
>decl_var shader_in INTERP_MODE_FLAT float fastuidraw_float_flat_varying5@6 (VARYING_SLOT_VAR11.z, 42, 0)
>decl_var shader_in INTERP_MODE_SMOOTH float fastuidraw_float_smooth_varying1 (VARYING_SLOT_VAR4.w, 35, 0)
>decl_var shader_in INTERP_MODE_FLAT float fastuidraw_float_flat_varying0 (VARYING_SLOT_VAR6.x, 37, 0)
>decl_var shader_in INTERP_MODE_FLAT float fastuidraw_float_flat_varying0@7 (VARYING_SLOT_VAR6.y, 37, 0)
>decl_var shader_in INTERP_MODE_FLAT float fastuidraw_float_flat_varying0@8 (VARYING_SLOT_VAR6.z, 37, 0)
>decl_var shader_in INTERP_MODE_FLAT float fastuidraw_float_flat_varying0@9 (VARYING_SLOT_VAR6.w, 37, 0)
>decl_var shader_in INTERP_MODE_FLAT float fastuidraw_float_flat_varying1 (VARYING_SLOT_VAR7.x, 38, 0)
>decl_var shader_in INTERP_MODE_FLAT float fastuidraw_float_flat_varying1@10 (VARYING_SLOT_VAR7.y, 38, 0)
>decl_var shader_in INTERP_MODE_FLAT float fastuidraw_float_flat_varying1@11 (VARYING_SLOT_VAR7.z, 38, 0)
>decl_var shader_in INTERP_MODE_FLAT float fastuidraw_float_flat_varying1@12 (VARYING_SLOT_VAR7.w, 38, 0)
>decl_var shader_in INTERP_MODE_FLAT float fastuidraw_float_flat_varying2 (VARYING_SLOT_VAR8.x, 39, 0)
>decl_var shader_in INTERP_MODE_FLAT float fastuidraw_float_flat_varying2@13 (VARYING_SLOT_VAR8.y, 39, 0)
>decl_var shader_in INTERP_MODE_FLAT float fastuidraw_float_flat_varying2@14 (VARYING_SLOT_VAR8.z, 39, 0)
>decl_var shader_in INTERP_MODE_FLAT float fastuidraw_float_flat_varying2@15 (VARYING_SLOT_VAR8.w, 39, 0)
>decl_var shader_in INTERP_MODE_FLAT float fastuidraw_float_flat_varying3 (VARYING_SLOT_VAR9.x, 40, 0)
>decl_var shader_in INTERP_MODE_FLAT float fastuidraw_float_flat_varying3@16 (VARYING_SLOT_VAR9.y, 40, 0)
>decl_var shader_in INTERP_MODE_FLAT float fastuidraw_float_flat_varying3@17 (VARYING_SLOT_VAR9.z, 40, 0)
>decl_var shader_in INTERP_MODE_FLAT float fastuidraw_float_flat_varying3@18 (VARYING_SLOT_VAR9.w, 40, 0)
>decl_var shader_in INTERP_MODE_FLAT uint fastuidraw_uint_varying0 (VARYING_SLOT_VAR0.x, 31, 0)
>decl_var shader_in INTERP_MODE_FLAT uint fastuidraw_uint_varying0@19 (VARYING_SLOT_VAR0.y, 31, 0)
>decl_var shader_in INTERP_MODE_FLAT uint fastuidraw_uint_varying0@20 (VARYING_SLOT_VAR0.z, 31, 0)
>decl_var shader_in INTERP_MODE_FLAT uint fastuidraw_uint_varying0@21 (VARYING_SLOT_VAR0.w, 31, 0)
>decl_var shader_in INTERP_MODE_FLAT uint fastuidraw_uint_varying1 (VARYING_SLOT_VAR1.x, 32, 0)
>decl_var shader_in INTERP_MODE_FLAT uint fastuidraw_uint_varying1@22 (VARYING_SLOT_VAR1.y, 32, 0)
>decl_var shader_in INTERP_MODE_FLAT uint fastuidraw_uint_varying1@23 (VARYING_SLOT_VAR1.w, 32, 0)
>decl_var shader_in INTERP_MODE_SMOOTH float fastuidraw_float_smooth_varying0 (VARYING_SLOT_VAR3.x, 34, 0)
>decl_var shader_in INTERP_MODE_SMOOTH float fastuidraw_float_smooth_varying0@24 (VARYING_SLOT_VAR3.y, 34, 0)
>decl_var shader_in INTERP_MODE_SMOOTH float fastuidraw_float_smooth_varying0@25 (VARYING_SLOT_VAR3.z, 34, 0)
>decl_var shader_in INTERP_MODE_SMOOTH float fastuidraw_float_smooth_varying0@26 (VARYING_SLOT_VAR3.w, 34, 0)
>decl_var shader_in INTERP_MODE_FLAT uvec4 fastuidraw_uint_varying0@27 (VARYING_SLOT_VAR0, 31, 0)
>decl_var shader_in INTERP_MODE_FLAT uvec2 fastuidraw_uint_varying1@28 (VARYING_SLOT_VAR1.xy, 32, 0)
>decl_var shader_in INTERP_MODE_FLAT uvec2 fastuidraw_uint_varying2@29 (VARYING_SLOT_VAR2.xy, 33, 0)
>decl_var shader_in INTERP_MODE_SMOOTH vec4 fastuidraw_float_smooth_varying0@30 (VARYING_SLOT_VAR3, 34, 0)
>decl_var shader_in INTERP_MODE_FLAT vec4 fastuidraw_float_flat_varying0@31 (VARYING_SLOT_VAR6, 37, 0)
>decl_var shader_in INTERP_MODE_FLAT vec4 fastuidraw_float_flat_varying1@32 (VARYING_SLOT_VAR7, 38, 0)
>decl_var shader_in INTERP_MODE_FLAT vec4 fastuidraw_float_flat_varying2@33 (VARYING_SLOT_VAR8, 39, 0)
>decl_var shader_in INTERP_MODE_FLAT vec4 fastuidraw_float_flat_varying3@34 (VARYING_SLOT_VAR9, 40, 0)
>decl_var shader_in INTERP_MODE_FLAT vec4 fastuidraw_float_flat_varying4@35 (VARYING_SLOT_VAR10, 41, 0)
>decl_var shader_in INTERP_MODE_FLAT vec3 fastuidraw_float_flat_varying5@36 (VARYING_SLOT_VAR11.xyz, 42, 0)
>decl_var shader_out INTERP_MODE_NONE vec4 fastuidraw_final_color0 (FRAG_RESULT_DATA0, 8, 0)
>decl_var shader_out INTERP_MODE_NONE vec4 fastuidraw_final_color1 (FRAG_RESULT_DATA0, 9, 0)
>decl_function main (0 params)
>
>impl main {
>	block block_0:
>	/* preds: */
>	vec2 32 ssa_0 = intrinsic load_barycentric_pixel () (1) /* interp_mode=1 */
>	vec1 32 ssa_1 = load_const (0x00000000 /* 0.000000 */)
>	vec1 32 ssa_2 = intrinsic load_interpolated_input (ssa_0, ssa_1) (35, 3) /* base=35 */ /* component=3 */	/* fastuidraw_float_smooth_varying1 */
>	vec1 32 ssa_3 = intrinsic load_interpolated_input (ssa_0, ssa_1) (36, 0) /* base=36 */ /* component=0 */	/* fastuidraw_float_smooth_varying2 */
>	vec4 32 ssa_4 = intrinsic load_interpolated_input (ssa_0, ssa_1) (0, 0) /* base=0 */ /* component=0 */	/* gl_FragCoord */
>	vec4 32 ssa_5 = intrinsic load_interpolated_input (ssa_0, ssa_1) (34, 0) /* base=34 */ /* component=0 */	/* fastuidraw_float_smooth_varying0 */
>	vec1 32 ssa_6 = undefined
>	vec1 32 ssa_7 = undefined
>	vec1 32 ssa_8 = undefined
>	vec1 32 ssa_9 = undefined
>	vec1 32 ssa_10 = undefined
>	vec1 32 ssa_11 = undefined
>	vec1 32 ssa_12 = undefined
>	vec1 32 ssa_13 = undefined
>	vec1 32 ssa_14 = undefined
>	vec1 32 ssa_15 = undefined
>	vec1 32 ssa_16 = undefined
>	vec1 32 ssa_17 = undefined
>	vec1 32 ssa_18 = undefined
>	vec1 32 ssa_19 = undefined
>	vec1 32 ssa_20 = undefined
>	vec1 32 ssa_21 = undefined
>	vec1 32 ssa_22 = undefined
>	vec1 32 ssa_23 = load_const (0x00000010 /* 0.000000 */)
>	vec1 32 ssa_24 = load_const (0xffff8000 /* -nan */)
>	vec1 32 ssa_25 = load_const (0xffffffff /* -nan */)
>	vec1 32 ssa_26 = load_const (0x80000000 /* -0.000000 */)
>	vec1 32 ssa_27 = load_const (0x00002000 /* 0.000000 */)
>	vec1 32 ssa_28 = load_const (0x0000001e /* 0.000000 */)
>	vec1 32 ssa_29 = load_const (0x0000000e /* 0.000000 */)
>	vec1 32 ssa_30 = load_const (0x00000001 /* 0.000000 */)
>	vec1 32 ssa_31 = load_const (0x00000002 /* 0.000000 */)
>	vec1 32 ssa_32 = load_const (0x00000003 /* 0.000000 */)
>	vec1 32 ssa_33 = load_const (0x40000000 /* 2.000000 */)
>	vec1 32 ssa_34 = load_const (0x00000015 /* 0.000000 */)
>	vec1 32 ssa_35 = load_const (0x3f800000 /* 1.000000 */)
>	vec1 32 ssa_36 = load_const (0x40800000 /* 4.000000 */)
>	vec1 32 ssa_37 = load_const (0x3f000000 /* 0.500000 */)
>	vec1 32 ssa_38 = load_const (0x5d5e0b6b /* 999999984306749440.000000 */)
>	vec1 32 ssa_39 = load_const (0x3e800000 /* 0.250000 */)
>	vec1 32 ssa_40 = load_const (0xbc46c6a5 /* -0.012132 */)
>	vec1 32 ssa_41 = load_const (0x3d5be101 /* 0.053681 */)
>	vec1 32 ssa_42 = load_const (0xbdf0555d /* -0.117350 */)
>	vec1 32 ssa_43 = load_const (0x3e468bc1 /* 0.193892 */)
>	vec1 32 ssa_44 = load_const (0xbeaa5476 /* -0.332676 */)
>	vec1 32 ssa_45 = load_const (0x3f7ffea5 /* 0.999979 */)
>	vec1 32 ssa_46 = load_const (0xc0000000 /* -2.000000 */)
>	vec1 32 ssa_47 = load_const (0x3fc90fdb /* 1.570796 */)
>	vec1 32 ssa_48 = load_const (0x40c90fdb /* 6.283185 */)
>	vec1 32 ssa_49 = load_const (0x3e22f983 /* 0.159155 */)
>	vec1 32 ssa_50 = load_const (0x00000013 /* 0.000000 */)
>	vec1 32 ssa_51 = load_const (0xbf800000 /* -1.000000 */)
>	vec1 32 ssa_52 = load_const (0x0000000a /* 0.000000 */)
>	vec1 32 ssa_53 = load_const (0x00000017 /* 0.000000 */)
>	vec1 32 ssa_54 = load_const (0x00000019 /* 0.000000 */)
>	vec1 32 ssa_55 = load_const (0x40900000 /* 4.500000 */)
>	vec1 32 ssa_56 = load_const (0x42000000 /* 32.000000 */)
>	vec1 32 ssa_57 = load_const (0x3d000000 /* 0.031250 */)
>	vec1 32 ssa_58 = load_const (0x41f80000 /* 31.000000 */)
>	vec1 32 ssa_59 = load_const (0x40400000 /* 3.000000 */)
>	vec1 32 ssa_60 = load_const (0x40c00000 /* 6.000000 */)
>	vec1 32 ssa_61 = load_const (0xbfc00000 /* -1.500000 */)
>	vec1 32 ssa_62 = load_const (0x40200000 /* 2.500000 */)
>	vec1 32 ssa_63 = load_const (0xbf000000 /* -0.500000 */)
>	vec1 32 ssa_64 = load_const (0x3fc00000 /* 1.500000 */)
>	vec1 32 ssa_65 = load_const (0x39000000 /* 0.000122 */)
>	vec1 32 ssa_66 = load_const (0x01000000 /* 0.000000 */)
>	vec1 32 ssa_67 = load_const (0x00000006 /* 0.000000 */)
>	vec1 32 ssa_68 = load_const (0x00000012 /* 0.000000 */)
>	vec1 32 ssa_69 = load_const (0x00000014 /* 0.000000 */)
>	vec1 32 ssa_70 = load_const (0x00000008 /* 0.000000 */)
>	vec1 32 ssa_71 = load_const (0x00000018 /* 0.000000 */)
>	vec1 32 ssa_72 = load_const (0x00000016 /* 0.000000 */)
>	vec1 32 ssa_73 = load_const (0x3fffffff /* 2.000000 */)
>	vec1 32 ssa_74 = load_const (0x0000001f /* 0.000000 */)
>	vec1 32 ssa_75 = load_const (0x00000011 /* 0.000000 */)
>	vec1 32 ssa_76 = load_const (0x0000000f /* 0.000000 */)
>	vec1 32 ssa_77 = load_const (0x42f00000 /* 120.000000 */)
>	vec1 32 ssa_78 = load_const (0x33d6bf95 /* 0.000000 */)
>	vec1 32 ssa_79 = load_const (0x00008000 /* 0.000000 */)
>	vec1 32 ssa_80 = load_const (0x00000004 /* 0.000000 */)
>	vec1 32 ssa_81 = load_const (0x00002e74 /* 0.000000 */)
>	vec1 32 ssa_82 = load_const (0x38d1b717 /* 0.000100 */)
>	vec1 32 ssa_83 = load_const (0x00000000 /* 0.000000 */)
>	vec1 32 ssa_84 = load_const (0x3c800000 /* 0.015625 */)
>	vec1 32 ssa_85 = load_const (0x3a83126f /* 0.001000 */)
>	vec1 32 ssa_86 = load_const (0x00000005 /* 0.000000 */)
>	vec1 32 ssa_87 = load_const (0x00000007 /* 0.000000 */)
>	vec1 32 ssa_88 = load_const (0x00000009 /* 0.000000 */)
>	vec1 32 ssa_89 = load_const (0x0000000b /* 0.000000 */)
>	vec1 32 ssa_90 = load_const (0x0000000c /* 0.000000 */)
>	vec1 32 ssa_91 = load_const (0x0000000d /* 0.000000 */)
>	vec2 32 ssa_92 = intrinsic load_input (ssa_1) (33, 0) /* base=33 */ /* component=0 */	/* fastuidraw_uint_varying2 */
>	vec1 32 ssa_93 = intrinsic load_input (ssa_1) (33, 3) /* base=33 */ /* component=3 */	/* fastuidraw_uint_varying2 */
>	vec1 32 ssa_94 = extract_u16 ssa_93, ssa_1
>	vec1 32 ssa_95 = extract_u16 ssa_93, ssa_30
>	vec1 32 ssa_96 = iadd ssa_94, ssa_24
>	vec1 32 ssa_97 = iadd ssa_95, ssa_24
>	vec1 32 ssa_98 = ine32 ssa_92.x, ssa_25
>	/* succs: block_1 block_396 */
>	if ssa_98 {
>		block block_1:
>		/* preds: block_0 */
>		vec1 32 ssa_99 = iand ssa_92.y, ssa_26
>		vec1 32 ssa_100 = ine32 ssa_99, ssa_1
>		/* succs: block_2 block_134 */
>		if ssa_100 {
>			block block_2:
>			/* preds: block_1 */
>			vec4 32 ssa_101 = intrinsic load_input (ssa_1) (41, 0) /* base=41 */ /* component=0 */	/* fastuidraw_float_flat_varying4 */
>			vec1 32 ssa_102 = imov ssa_101.w
>			vec3 32 ssa_103 = intrinsic load_input (ssa_1) (42, 0) /* base=42 */ /* component=0 */	/* fastuidraw_float_flat_varying5 */
>			vec1 32 ssa_104 = imov ssa_103.x
>			vec1 32 ssa_105 = imov ssa_103.y
>			vec1 32 ssa_106 = imov ssa_103.z
>			vec1 32 ssa_107 = fddx ssa_2
>			vec1 32 ssa_108 = fddx ssa_3
>			vec4 32 ssa_109 = intrinsic load_uniform (ssa_1) (0, 16) /* base=0 */ /* range=16 */	/* fastuidraw_painterStore */
>			vec1 32 ssa_110 = fmul ssa_2, ssa_109.x
>			vec1 32 ssa_111 = fddy ssa_110
>			vec1 32 ssa_112 = fmul ssa_3, ssa_109.x
>			vec1 32 ssa_113 = fddy ssa_112
>			vec1 32 ssa_114 = iand ssa_92.y, ssa_27
>			vec1 32 ssa_115 = ine32 ssa_114, ssa_1
>			/* succs: block_3 block_22 */
>			if ssa_115 {
>				block block_3:
>				/* preds: block_2 */
>				vec1 32 ssa_116 = ishl ssa_92.y, ssa_23
>				vec1 32 ssa_117 = ushr ssa_116, ssa_28
>				vec1 32 ssa_118 = ishl ssa_92.y, ssa_29
>				vec1 32 ssa_119 = ushr ssa_118, ssa_28
>				vec4 32 ssa_120 = intrinsic load_input (ssa_1) (37, 0) /* base=37 */ /* component=0 */	/* fastuidraw_float_flat_varying0 */
>				vec1 32 ssa_121 = fadd ssa_2, -ssa_120.x
>				vec1 32 ssa_122 = fadd ssa_3, -ssa_120.y
>				vec1 32 ssa_123 = ieq32 ssa_117, ssa_30
>				/* succs: block_4 block_5 */
>				if ssa_123 {
>					block block_4:
>					/* preds: block_3 */
>					vec1 32 ssa_124 = fmax abs(ssa_121), ssa_1
>					vec1 32 ssa_125 = fmin ssa_124, ssa_120.z
>					/* succs: block_12 */
>				} else {
>					block block_5:
>					/* preds: block_3 */
>					vec1 32 ssa_126 = ieq32 ssa_117, ssa_31
>					/* succs: block_6 block_7 */
>					if ssa_126 {
>						block block_6:
>						/* preds: block_5 */
>						vec1 32 ssa_127 = frcp ssa_120.z
>						vec1 32 ssa_128 = fmul ssa_121, ssa_127
>						vec1 32 ssa_129 = ffloor ssa_128
>						vec1 32 ssa_130 = ffma -ssa_120.z, ssa_129, ssa_121
>						/* succs: block_11 */
>					} else {
>						block block_7:
>						/* preds: block_5 */
>						vec1 32 ssa_131 = ieq32 ssa_117, ssa_32
>						/* succs: block_8 block_9 */
>						if ssa_131 {
>							block block_8:
>							/* preds: block_7 */
>							vec1 32 ssa_132 = fmul ssa_33, ssa_120.z
>							vec1 32 ssa_133 = frcp ssa_132
>							vec1 32 ssa_134 = fmul ssa_121, ssa_133
>							vec1 32 ssa_135 = ffloor ssa_134
>							vec1 32 ssa_136 = ffma -ssa_132, ssa_135, ssa_121
>							vec1 32 ssa_137 = fadd ssa_136, -ssa_120.z
>							vec1 32 ssa_138 = fadd ssa_120.z, -abs(ssa_137)
>							/* succs: block_10 */
>						} else {
>							block block_9:
>							/* preds: block_7 */
>							vec1 32 ssa_139 = fmax ssa_121, ssa_1
>							vec1 32 ssa_140 = fmin ssa_139, ssa_120.z
>							/* succs: block_10 */
>						}
>						block block_10:
>						/* preds: block_8 block_9 */
>						vec1 32 ssa_141 = phi block_8: ssa_138, block_9: ssa_140
>						/* succs: block_11 */
>					}
>					block block_11:
>					/* preds: block_6 block_10 */
>					vec1 32 ssa_142 = phi block_6: ssa_130, block_10: ssa_141
>					/* succs: block_12 */
>				}
>				block block_12:
>				/* preds: block_4 block_11 */
>				vec1 32 ssa_143 = phi block_4: ssa_125, block_11: ssa_142
>				vec1 32 ssa_144 = ieq32 ssa_119, ssa_30
>				/* succs: block_13 block_14 */
>				if ssa_144 {
>					block block_13:
>					/* preds: block_12 */
>					vec1 32 ssa_145 = fmax abs(ssa_122), ssa_1
>					vec1 32 ssa_146 = fmin ssa_145, ssa_120.w
>					/* succs: block_21 */
>				} else {
>					block block_14:
>					/* preds: block_12 */
>					vec1 32 ssa_147 = ieq32 ssa_119, ssa_31
>					/* succs: block_15 block_16 */
>					if ssa_147 {
>						block block_15:
>						/* preds: block_14 */
>						vec1 32 ssa_148 = frcp ssa_120.w
>						vec1 32 ssa_149 = fmul ssa_122, ssa_148
>						vec1 32 ssa_150 = ffloor ssa_149
>						vec1 32 ssa_151 = ffma -ssa_120.w, ssa_150, ssa_122
>						/* succs: block_20 */
>					} else {
>						block block_16:
>						/* preds: block_14 */
>						vec1 32 ssa_152 = ieq32 ssa_119, ssa_32
>						/* succs: block_17 block_18 */
>						if ssa_152 {
>							block block_17:
>							/* preds: block_16 */
>							vec1 32 ssa_153 = fmul ssa_33, ssa_120.w
>							vec1 32 ssa_154 = frcp ssa_153
>							vec1 32 ssa_155 = fmul ssa_122, ssa_154
>							vec1 32 ssa_156 = ffloor ssa_155
>							vec1 32 ssa_157 = ffma -ssa_153, ssa_156, ssa_122
>							vec1 32 ssa_158 = fadd ssa_157, -ssa_120.w
>							vec1 32 ssa_159 = fadd ssa_120.w, -abs(ssa_158)
>							/* succs: block_19 */
>						} else {
>							block block_18:
>							/* preds: block_16 */
>							vec1 32 ssa_160 = fmax ssa_122, ssa_1
>							vec1 32 ssa_161 = fmin ssa_160, ssa_120.w
>							/* succs: block_19 */
>						}
>						block block_19:
>						/* preds: block_17 block_18 */
>						vec1 32 ssa_162 = phi block_17: ssa_159, block_18: ssa_161
>						/* succs: block_20 */
>					}
>					block block_20:
>					/* preds: block_15 block_19 */
>					vec1 32 ssa_163 = phi block_15: ssa_151, block_19: ssa_162
>					/* succs: block_21 */
>				}
>				block block_21:
>				/* preds: block_13 block_20 */
>				vec1 32 ssa_164 = phi block_13: ssa_146, block_20: ssa_163
>				vec1 32 ssa_165 = fadd ssa_143, ssa_120.x
>				vec1 32 ssa_166 = fadd ssa_164, ssa_120.y
>				/* succs: block_23 */
>			} else {
>				block block_22:
>				/* preds: block_2 */
>				/* succs: block_23 */
>			}
>			block block_23:
>			/* preds: block_21 block_22 */
>			vec1 32 ssa_167 = phi block_21: ssa_165, block_22: ssa_2
>			vec1 32 ssa_168 = phi block_21: ssa_166, block_22: ssa_3
>			vec1 32 ssa_169 = ishl ssa_92.y, ssa_34
>			vec1 32 ssa_170 = ushr ssa_169, ssa_28
>			vec1 32 ssa_171 = ine32 ssa_170, ssa_1
>			/* succs: block_24 block_52 */
>			if ssa_171 {
>				block block_24:
>				/* preds: block_23 */
>				vec1 32 ssa_172 = ieq32 ssa_170, ssa_31
>				/* succs: block_25 block_32 */
>				if ssa_172 {
>					block block_25:
>					/* preds: block_24 */
>					vec4 32 ssa_173 = intrinsic load_input (ssa_1) (38, 0) /* base=38 */ /* component=0 */	/* fastuidraw_float_flat_varying1 */
>					vec1 32 ssa_174 = fadd ssa_167, -ssa_173.x
>					vec1 32 ssa_175 = fadd ssa_168, -ssa_173.y
>					vec1 32 ssa_176 = fadd ssa_173.z, -ssa_173.x
>					vec1 32 ssa_177 = fadd ssa_173.w, -ssa_173.y
>					vec4 32 ssa_178 = intrinsic load_input (ssa_1) (39, 0) /* base=39 */ /* component=0 */	/* fastuidraw_float_flat_varying2 */
>					vec1 32 ssa_179 = fadd ssa_178.y, -ssa_178.x
>					vec1 32 ssa_180 = fmul ssa_175, ssa_177
>					vec1 32 ssa_181 = ffma ssa_174, ssa_176, ssa_180
>					vec1 32 ssa_182 = ffma -ssa_178.x, ssa_179, ssa_181
>					vec1 32 ssa_183 = fmul ssa_33, ssa_182
>					vec1 32 ssa_184 = fmul ssa_177, ssa_177
>					vec1 32 ssa_185 = ffma ssa_176, ssa_176, ssa_184
>					vec1 32 ssa_186 = ffma -ssa_179, ssa_179, ssa_185
>					vec1 32 ssa_187 = fmul ssa_175, ssa_175
>					vec1 32 ssa_188 = ffma ssa_174, ssa_174, ssa_187
>					vec1 32 ssa_189 = ffma -ssa_178.x, ssa_178.x, ssa_188
>					vec1 32 ssa_190 = fmul ssa_186, ssa_36
>					vec1 32 ssa_191 = fmul ssa_190, ssa_189
>					vec1 32 ssa_192 = ffma ssa_183, ssa_183, -ssa_191
>					vec1 32 ssa_193 = fge32 ssa_192, ssa_1
>					/* succs: block_26 block_30 */
>					if ssa_193 {
>						block block_26:
>						/* preds: block_25 */
>						vec1 32 ssa_194 = fsqrt abs(ssa_192)
>						vec1 32 ssa_195 = frcp ssa_186
>						vec1 32 ssa_196 = fmul ssa_37, ssa_195
>						vec1 32 ssa_197 = fadd -ssa_183, ssa_194
>						vec1 32 ssa_198 = fmul ssa_197, ssa_196
>						vec1 32 ssa_199 = fadd -ssa_183, -ssa_194
>						vec1 32 ssa_200 = fmul ssa_199, ssa_196
>						vec1 32 ssa_201 = fge32 ssa_35, ssa_198
>						vec1 32 ssa_202 = fge32 ssa_198, ssa_1
>						vec1 32 ssa_203 = iand ssa_202, ssa_201
>						vec1 32 ssa_204 = b2f32 ssa_203
>						vec1 32 ssa_205 = fge32 ssa_35, ssa_200
>						vec1 32 ssa_206 = fge32 ssa_200, ssa_1
>						vec1 32 ssa_207 = iand ssa_206, ssa_205
>						vec1 32 ssa_208 = b2f32 ssa_207
>						vec1 32 ssa_209 = ieq32 ssa_203, ssa_207
>						/* succs: block_27 block_28 */
>						if ssa_209 {
>							block block_27:
>							/* preds: block_26 */
>							vec1 32 ssa_210 = fmax ssa_198, ssa_200
>							/* succs: block_29 */
>						} else {
>							block block_28:
>							/* preds: block_26 */
>							vec1 32 ssa_211 = fmul ssa_208, ssa_200
>							vec1 32 ssa_212 = ffma ssa_204, ssa_198, ssa_211
>							/* succs: block_29 */
>						}
>						block block_29:
>						/* preds: block_27 block_28 */
>						vec1 32 ssa_213 = phi block_27: ssa_210, block_28: ssa_212
>						/* succs: block_31 */
>					} else {
>						block block_30:
>						/* preds: block_25 */
>						/* succs: block_31 */
>					}
>					block block_31:
>					/* preds: block_29 block_30 */
>					vec1 32 ssa_214 = phi block_30: ssa_1, block_29: ssa_213
>					vec1 32 ssa_215 = phi block_30: ssa_1, block_29: ssa_35
>					/* succs: block_42 */
>				} else {
>					block block_32:
>					/* preds: block_24 */
>					vec1 32 ssa_216 = ieq32 ssa_170, ssa_30
>					/* succs: block_33 block_34 */
>					if ssa_216 {
>						block block_33:
>						/* preds: block_32 */
>						vec4 32 ssa_217 = intrinsic load_input (ssa_1) (38, 0) /* base=38 */ /* component=0 */	/* fastuidraw_float_flat_varying1 */
>						vec1 32 ssa_218 = fadd ssa_217.z, -ssa_217.x
>						vec1 32 ssa_219 = fadd ssa_217.w, -ssa_217.y
>						vec1 32 ssa_220 = fadd ssa_167, -ssa_217.x
>						vec1 32 ssa_221 = fadd ssa_168, -ssa_217.y
>						vec1 32 ssa_222 = fmul ssa_219, ssa_221
>						vec1 32 ssa_223 = ffma ssa_218, ssa_220, ssa_222
>						vec1 32 ssa_224 = fmul ssa_219, ssa_219
>						vec1 32 ssa_225 = ffma ssa_218, ssa_218, ssa_224
>						vec1 32 ssa_226 = frcp ssa_225
>						vec1 32 ssa_227 = fmul ssa_223, ssa_226
>						/* succs: block_41 */
>					} else {
>						block block_34:
>						/* preds: block_32 */
>						vec1 32 ssa_228 = ieq32 ssa_170, ssa_32
>						/* succs: block_35 block_39 */
>						if ssa_228 {
>							block block_35:
>							/* preds: block_34 */
>							vec4 32 ssa_229 = intrinsic load_input (ssa_1) (38, 0) /* base=38 */ /* component=0 */	/* fastuidraw_float_flat_varying1 */
>							vec1 32 ssa_230 = fadd ssa_167, -ssa_229.x
>							vec1 32 ssa_231 = fadd ssa_168, -ssa_229.y
>							vec1 32 ssa_232 = fmov abs(ssa_230)
>							vec1 32 ssa_233 = fge32 ssa_1, ssa_230
>							vec1 32 ssa_234 = b32csel ssa_233, ssa_232, ssa_231
>							vec1 32 ssa_235 = b32csel ssa_233, ssa_231, ssa_232
>							vec1 32 ssa_236 = fge32 abs(ssa_235), ssa_38
>							vec1 32 ssa_237 = b32csel ssa_236, ssa_39, ssa_35
>							vec1 32 ssa_238 = fmul ssa_235, ssa_237
>							vec1 32 ssa_239 = frcp ssa_238
>							vec1 32 ssa_240 = fmul ssa_234, ssa_237
>							vec1 32 ssa_241 = fmul ssa_240, ssa_239
>							vec1 32 ssa_242 = fmov abs(ssa_241)
>							vec1 32 ssa_243 = feq32 abs(ssa_230), abs(ssa_231)
>							vec1 32 ssa_244 = b32csel ssa_243, ssa_35, ssa_242
>							vec1 32 ssa_245 = fmin abs(ssa_244), ssa_35
>							vec1 32 ssa_246 = fmax abs(ssa_244), ssa_35
>							vec1 32 ssa_247 = frcp ssa_246
>							vec1 32 ssa_248 = fmul ssa_245, ssa_247
>							vec1 32 ssa_249 = fmul ssa_248, ssa_248
>							vec1 32 ssa_250 = fmul ssa_40, ssa_249
>							vec1 32 ssa_251 = fadd ssa_250, ssa_41
>							vec1 32 ssa_252 = ffma ssa_251, ssa_249, ssa_42
>							vec1 32 ssa_253 = ffma ssa_252, ssa_249, ssa_43
>							vec1 32 ssa_254 = ffma ssa_253, ssa_249, ssa_44
>							vec1 32 ssa_255 = ffma ssa_254, ssa_249, ssa_45
>							vec1 32 ssa_256 = fmul ssa_255, ssa_248
>							vec1 32 ssa_257 = flt32 ssa_35, abs(ssa_244)
>							vec1 32 ssa_258 = b2f32 ssa_257
>							vec1 32 ssa_259 = ffma ssa_256, ssa_46, ssa_47
>							vec1 32 ssa_260 = ffma ssa_258, ssa_259, ssa_256
>							vec1 32 ssa_261 = fsign ssa_244
>							vec1 32 ssa_262 = b2f32 ssa_233
>							vec1 32 ssa_263 = fmul ssa_262, ssa_47
>							vec1 32 ssa_264 = ffma ssa_260, ssa_261, ssa_263
>							vec1 32 ssa_265 = fmin ssa_231, ssa_239
>							vec1 32 ssa_266 = fmov -ssa_264
>							vec1 32 ssa_267 = flt32 ssa_265, ssa_1
>							vec1 32 ssa_268 = b32csel ssa_267, ssa_266, ssa_264
>							vec1 32 ssa_269 = fadd ssa_268, ssa_48
>							vec1 32 ssa_270 = flt32 ssa_268, ssa_229.z
>							vec1 32 ssa_271 = b32csel ssa_270, ssa_269, ssa_268
>							vec1 32 ssa_272 = fadd ssa_271, -ssa_229.z
>							vec1 32 ssa_273 = fmul ssa_272, ssa_49
>							vec1 32 ssa_274 = flt32 ssa_229.w, ssa_1
>							/* succs: block_36 block_37 */
>							if ssa_274 {
>								block block_36:
>								/* preds: block_35 */
>								vec1 32 ssa_275 = fadd ssa_35, -ssa_273
>								/* succs: block_38 */
>							} else {
>								block block_37:
>								/* preds: block_35 */
>								/* succs: block_38 */
>							}
>							block block_38:
>							/* preds: block_36 block_37 */
>							vec1 32 ssa_276 = phi block_36: ssa_275, block_37: ssa_273
>							vec1 32 ssa_277 = fmul ssa_276, abs(ssa_229.w)
>							/* succs: block_40 */
>						} else {
>							block block_39:
>							/* preds: block_34 */
>							/* succs: block_40 */
>						}
>						block block_40:
>						/* preds: block_38 block_39 */
>						vec1 32 ssa_278 = phi block_38: ssa_35, block_39: ssa_22
>						vec1 32 ssa_279 = phi block_38: ssa_277, block_39: ssa_35
>						/* succs: block_41 */
>					}
>					block block_41:
>					/* preds: block_33 block_40 */
>					vec1 32 ssa_280 = phi block_33: ssa_35, block_40: ssa_278
>					vec1 32 ssa_281 = phi block_33: ssa_227, block_40: ssa_279
>					/* succs: block_42 */
>				}
>				block block_42:
>				/* preds: block_31 block_41 */
>				vec1 32 ssa_282 = phi block_31: ssa_215, block_41: ssa_280
>				vec1 32 ssa_283 = phi block_31: ssa_214, block_41: ssa_281
>				vec1 32 ssa_284 = ishl ssa_92.y, ssa_50
>				vec1 32 ssa_285 = ushr ssa_284, ssa_28
>				vec1 32 ssa_286 = ieq32 ssa_285, ssa_30
>				/* succs: block_43 block_44 */
>				if ssa_286 {
>					block block_43:
>					/* preds: block_42 */
>					vec1 32 ssa_287 = fmov.sat abs(ssa_283)
>					/* succs: block_51 */
>				} else {
>					block block_44:
>					/* preds: block_42 */
>					vec1 32 ssa_288 = ieq32 ssa_285, ssa_31
>					/* succs: block_45 block_46 */
>					if ssa_288 {
>						block block_45:
>						/* preds: block_44 */
>						vec1 32 ssa_289 = ffract ssa_283
>						/* succs: block_50 */
>					} else {
>						block block_46:
>						/* preds: block_44 */
>						vec1 32 ssa_290 = ieq32 ssa_285, ssa_32
>						/* succs: block_47 block_48 */
>						if ssa_290 {
>							block block_47:
>							/* preds: block_46 */
>							vec1 32 ssa_291 = fmul ssa_283, ssa_37
>							vec1 32 ssa_292 = ffloor ssa_291
>							vec1 32 ssa_293 = fadd ssa_283, ssa_51
>							vec1 32 ssa_294 = ffma -ssa_33, ssa_292, ssa_293
>							vec1 32 ssa_295 = fadd ssa_35, -abs(ssa_294)
>							/* succs: block_49 */
>						} else {
>							block block_48:
>							/* preds: block_46 */
>							vec1 32 ssa_296 = fmov.sat ssa_283
>							/* succs: block_49 */
>						}
>						block block_49:
>						/* preds: block_47 block_48 */
>						vec1 32 ssa_297 = phi block_47: ssa_295, block_48: ssa_296
>						/* succs: block_50 */
>					}
>					block block_50:
>					/* preds: block_45 block_49 */
>					vec1 32 ssa_298 = phi block_45: ssa_289, block_49: ssa_297
>					/* succs: block_51 */
>				}
>				block block_51:
>				/* preds: block_43 block_50 */
>				vec1 32 ssa_299 = phi block_43: ssa_287, block_50: ssa_298
>				vec1 32 ssa_300 = ffma ssa_299, ssa_101.z, ssa_101.x
>				vec2 32 ssa_301 = vec2 ssa_300, ssa_101.y
>				vec4 32 ssa_302 = txl ssa_301 (coord), ssa_1 (lod), 0 (texture), 0 (sampler), 
>				vec1 32 ssa_303 = fmul ssa_282, ssa_302.x
>				vec1 32 ssa_304 = fmul ssa_282, ssa_302.y
>				vec1 32 ssa_305 = fmul ssa_282, ssa_302.z
>				vec1 32 ssa_306 = fmul ssa_282, ssa_302.w
>				vec1 32 ssa_307 = fmul ssa_101.w, ssa_303
>				vec1 32 ssa_308 = fmul ssa_103.x, ssa_304
>				vec1 32 ssa_309 = fmul ssa_103.y, ssa_305
>				vec1 32 ssa_310 = fmul ssa_103.z, ssa_306
>				/* succs: block_53 */
>			} else {
>				block block_52:
>				/* preds: block_23 */
>				/* succs: block_53 */
>			}
>			block block_53:
>			/* preds: block_51 block_52 */
>			vec1 32 ssa_311 = phi block_51: ssa_307, block_52: ssa_102
>			vec1 32 ssa_312 = phi block_51: ssa_308, block_52: ssa_104
>			vec1 32 ssa_313 = phi block_51: ssa_309, block_52: ssa_105
>			vec1 32 ssa_314 = phi block_51: ssa_310, block_52: ssa_106
>			vec1 32 ssa_315 = fmul ssa_311, ssa_314
>			vec1 32 ssa_316 = fmul ssa_312, ssa_314
>			vec1 32 ssa_317 = fmul ssa_313, ssa_314
>			vec1 32 ssa_318 = iand ssa_92.y, ssa_32
>			vec1 32 ssa_319 = ine32 ssa_318, ssa_1
>			/* succs: block_54 block_132 */
>			if ssa_319 {
>				block block_54:
>				/* preds: block_53 */
>				vec1 32 ssa_320 = fmax ssa_167, ssa_1
>				vec4 32 ssa_321 = intrinsic load_input (ssa_1) (40, 0) /* base=40 */ /* component=0 */	/* fastuidraw_float_flat_varying3 */
>				vec1 32 ssa_322 = fadd ssa_321.x, ssa_51
>				vec1 32 ssa_323 = fmin ssa_320, ssa_322
>				vec1 32 ssa_324 = fmax ssa_168, ssa_1
>				vec1 32 ssa_325 = fadd ssa_321.y, ssa_51
>				vec1 32 ssa_326 = fmin ssa_324, ssa_325
>				vec1 32 ssa_327 = ishl ssa_92.y, ssa_52
>				vec1 32 ssa_328 = ushr ssa_327, ssa_28
>				vec1 32 ssa_329 = ishl ssa_92.y, ssa_28
>				vec1 32 ssa_330 = ushr ssa_329, ssa_28
>				vec1 32 ssa_331 = ishl ssa_92.y, ssa_53
>				vec1 32 ssa_332 = ushr ssa_331, ssa_54
>				vec1 32 ssa_333 = ult32 ssa_1, ssa_332
>				/* succs: block_55 block_56 */
>				if ssa_333 {
>					block block_55:
>					/* preds: block_54 */
>					vec1 32 ssa_334 = fmul ssa_108, ssa_108
>					vec1 32 ssa_335 = ffma ssa_107, ssa_107, ssa_334
>					vec1 32 ssa_336 = fmul ssa_113, ssa_113
>					vec1 32 ssa_337 = ffma ssa_111, ssa_111, ssa_336
>					vec1 32 ssa_338 = fadd ssa_335, ssa_337
>					vec1 32 ssa_339 = fmul ssa_338, ssa_37
>					vec1 32 ssa_340 = fmax ssa_35, ssa_339
>					vec1 32 ssa_341 = flog2 ssa_340
>					vec1 32 ssa_342 = fmul ssa_37, ssa_341
>					vec1 32 ssa_343 = u2f32 ssa_332
>					vec1 32 ssa_344 = fmin ssa_343, ssa_342
>					/* succs: block_57 */
>				} else {
>					block block_56:
>					/* preds: block_54 */
>					/* succs: block_57 */
>				}
>				block block_57:
>				/* preds: block_55 block_56 */
>				vec1 32 ssa_345 = phi block_55: ssa_344, block_56: ssa_1
>				vec1 32 ssa_346 = ieq32 ssa_328, ssa_1
>				/* succs: block_58 block_118 */
>				if ssa_346 {
>					block block_58:
>					/* preds: block_57 */
>					vec1 32 ssa_347 = fmin ssa_345, ssa_55
>					vec1 32 ssa_348 = ieq32 ssa_330, ssa_30
>					/* succs: block_59 block_65 */
>					if ssa_348 {
>						block block_59:
>						/* preds: block_58 */
>						vec1 32 ssa_349 = fceil ssa_347
>						vec1 32 ssa_350 = fmax ssa_323, ssa_1
>						vec1 32 ssa_351 = fmax ssa_326, ssa_1
>						vec1 32 ssa_352 = fmin ssa_350, ssa_321.x
>						vec1 32 ssa_353 = fmin ssa_351, ssa_321.y
>						vec4 32 ssa_354 = intrinsic load_input (ssa_1) (39, 0) /* base=39 */ /* component=0 */	/* fastuidraw_float_flat_varying2 */
>						vec1 32 ssa_355 = ffma ssa_352, ssa_321.z, ssa_354.z
>						vec1 32 ssa_356 = ffma ssa_353, ssa_321.z, ssa_354.w
>						vec1 32 ssa_357 = f2i32 ssa_355
>						vec1 32 ssa_358 = f2i32 ssa_356
>						vec4 32 ssa_359 = intrinsic load_input (ssa_1) (31, 0) /* base=31 */ /* component=0 */	/* fastuidraw_uint_varying0 */
>						vec3 32 ssa_360 = vec3 ssa_357, ssa_358, ssa_359.w
>						vec4 32 ssa_361 = txf ssa_360 (coord), ssa_1 (lod), 3 (texture), 3 (sampler), 
>						vec1 32 ssa_362 = ishl ssa_361.w, ssa_70
>						vec1 32 ssa_363 = iadd ssa_361.z, ssa_362
>						vec1 32 ssa_364 = imov ssa_361.x
>						vec1 32 ssa_365 = imov ssa_361.y
>						/* succs: block_60 */
>						loop {
>							block block_60:
>							/* preds: block_59 block_63 */
>							vec1 32 ssa_366 = phi block_59: ssa_364, block_63: ssa_391
>							vec1 32 ssa_367 = phi block_59: ssa_365, block_63: ssa_392
>							vec1 32 ssa_368 = phi block_59: ssa_363, block_63: ssa_389
>							vec1 32 ssa_369 = phi block_59: ssa_355, block_63: ssa_381
>							vec1 32 ssa_370 = phi block_59: ssa_356, block_63: ssa_383
>							vec1 32 ssa_371 = phi block_59: ssa_30, block_63: ssa_390
>							vec2 32 ssa_372 = intrinsic load_input (ssa_1) (32, 0) /* base=32 */ /* component=0 */	/* fastuidraw_uint_varying1 */
>							vec1 32 ssa_373 = uge32 ssa_371, ssa_372.x
>							/* succs: block_61 block_62 */
>							if ssa_373 {
>								block block_61:
>								/* preds: block_60 */
>								break
>								/* succs: block_64 */
>							} else {
>								block block_62:
>								/* preds: block_60 */
>								/* succs: block_63 */
>							}
>							block block_63:
>							/* preds: block_62 */
>							vec1 32 ssa_374 = ffloor ssa_369
>							vec1 32 ssa_375 = ffloor ssa_370
>							vec1 32 ssa_376 = fadd ssa_369, -ssa_374
>							vec1 32 ssa_377 = fadd ssa_370, -ssa_375
>							vec1 32 ssa_378 = u2f32 ssa_366
>							vec1 32 ssa_379 = u2f32 ssa_367
>							vec1 32 ssa_380 = fadd ssa_376, ssa_378
>							vec1 32 ssa_381 = fmul ssa_36, ssa_380
>							vec1 32 ssa_382 = fadd ssa_377, ssa_379
>							vec1 32 ssa_383 = fmul ssa_36, ssa_382
>							vec1 32 ssa_384 = f2i32 ssa_381
>							vec1 32 ssa_385 = f2i32 ssa_383
>							vec3 32 ssa_386 = vec3 ssa_384, ssa_385, ssa_368
>							vec4 32 ssa_387 = txf ssa_386 (coord), ssa_1 (lod), 3 (texture), 3 (sampler), 
>							vec1 32 ssa_388 = ishl ssa_387.w, ssa_70
>							vec1 32 ssa_389 = iadd ssa_387.z, ssa_388
>							vec1 32 ssa_390 = iadd ssa_371, ssa_30
>							vec1 32 ssa_391 = imov ssa_387.x
>							vec1 32 ssa_392 = imov ssa_387.y
>							/* succs: block_60 */
>						}
>						block block_64:
>						/* preds: block_61 */
>						vec1 32 ssa_393 = ffloor ssa_369
>						vec1 32 ssa_394 = ffloor ssa_370
>						vec1 32 ssa_395 = fadd ssa_369, -ssa_393
>						vec1 32 ssa_396 = fadd ssa_370, -ssa_394
>						vec1 32 ssa_397 = u2f32 ssa_366
>						vec1 32 ssa_398 = u2f32 ssa_367
>						vec1 32 ssa_399 = fadd ssa_395, ssa_397
>						vec1 32 ssa_400 = fadd ssa_396, ssa_398
>						vec1 32 ssa_401 = load_const (0x3b800000 /* 0.003906 */)
>						vec1 32 ssa_402 = fmul ssa_401, ssa_399
>						vec1 32 ssa_403 = fmul ssa_401, ssa_400
>						vec1 32 ssa_404 = u2f32 ssa_368
>						vec3 32 ssa_405 = vec3 ssa_402, ssa_403, ssa_404
>						vec4 32 ssa_406 = txl ssa_405 (coord), ssa_349 (lod), 2 (texture), 2 (sampler), 
>						vec1 32 ssa_407 = imov ssa_406.x
>						vec1 32 ssa_408 = imov ssa_406.y
>						vec1 32 ssa_409 = imov ssa_406.z
>						vec1 32 ssa_410 = imov ssa_406.w
>						/* succs: block_117 */
>					} else {
>						block block_65:
>						/* preds: block_58 */
>						vec1 32 ssa_411 = flt32 ssa_37, ssa_347
>						vec1 32 ssa_412 = ieq32 ssa_330, ssa_31
>						vec1 32 ssa_413 = ior ssa_412, ssa_411
>						/* succs: block_66 block_75 */
>						if ssa_413 {
>							block block_66:
>							/* preds: block_65 */
>							vec1 32 ssa_414 = fround_even ssa_347
>							vec1 32 ssa_415 = f2i32 ssa_414
>							vec1 32 ssa_416 = ishl ssa_30, ssa_415
>							vec1 32 ssa_417 = i2f32 ssa_416
>							vec1 32 ssa_418 = fmul ssa_37, ssa_417
>							vec1 32 ssa_419 = fmax ssa_323, ssa_418
>							vec1 32 ssa_420 = fmax ssa_326, ssa_418
>							vec1 32 ssa_421 = fadd ssa_321.x, -ssa_418
>							vec1 32 ssa_422 = fadd ssa_321.y, -ssa_418
>							vec1 32 ssa_423 = fmin ssa_419, ssa_421
>							vec1 32 ssa_424 = fmin ssa_420, ssa_422
>							vec4 32 ssa_425 = intrinsic load_input (ssa_1) (39, 0) /* base=39 */ /* component=0 */	/* fastuidraw_float_flat_varying2 */
>							vec1 32 ssa_426 = ffma ssa_423, ssa_321.z, ssa_425.z
>							vec1 32 ssa_427 = ffma ssa_424, ssa_321.z, ssa_425.w
>							vec1 32 ssa_428 = fmul ssa_39, ssa_426
>							vec1 32 ssa_429 = fmul ssa_39, ssa_427
>							vec1 32 ssa_430 = ffloor ssa_428
>							vec1 32 ssa_431 = ffloor ssa_429
>							vec1 32 ssa_432 = ffma -ssa_36, ssa_430, ssa_426
>							vec1 32 ssa_433 = ffma -ssa_36, ssa_431, ssa_427
>							vec1 32 ssa_434 = fmul ssa_432, ssa_321.w
>							vec1 32 ssa_435 = fmul ssa_433, ssa_321.w
>							vec1 32 ssa_436 = fmul ssa_434, ssa_57
>							vec1 32 ssa_437 = ffloor ssa_436
>							vec1 32 ssa_438 = ffma -ssa_56, ssa_437, ssa_434
>							vec1 32 ssa_439 = fmul ssa_435, ssa_57
>							vec1 32 ssa_440 = ffloor ssa_439
>							vec1 32 ssa_441 = ffma -ssa_56, ssa_440, ssa_435
>							vec1 32 ssa_442 = f2i32 ssa_426
>							vec1 32 ssa_443 = f2i32 ssa_427
>							vec4 32 ssa_444 = intrinsic load_input (ssa_1) (31, 0) /* base=31 */ /* component=0 */	/* fastuidraw_uint_varying0 */
>							vec3 32 ssa_445 = vec3 ssa_442, ssa_443, ssa_444.w
>							vec4 32 ssa_446 = txf ssa_445 (coord), ssa_1 (lod), 3 (texture), 3 (sampler), 
>							vec1 32 ssa_447 = ishl ssa_446.w, ssa_70
>							vec1 32 ssa_448 = iadd ssa_446.z, ssa_447
>							vec1 32 ssa_449 = imov ssa_446.x
>							vec1 32 ssa_450 = imov ssa_446.y
>							/* succs: block_67 */
>							loop {
>								block block_67:
>								/* preds: block_66 block_70 */
>								vec1 32 ssa_451 = phi block_66: ssa_449, block_70: ssa_476
>								vec1 32 ssa_452 = phi block_66: ssa_450, block_70: ssa_477
>								vec1 32 ssa_453 = phi block_66: ssa_448, block_70: ssa_474
>								vec1 32 ssa_454 = phi block_66: ssa_426, block_70: ssa_466
>								vec1 32 ssa_455 = phi block_66: ssa_427, block_70: ssa_468
>								vec1 32 ssa_456 = phi block_66: ssa_30, block_70: ssa_475
>								vec2 32 ssa_457 = intrinsic load_input (ssa_1) (32, 0) /* base=32 */ /* component=0 */	/* fastuidraw_uint_varying1 */
>								vec1 32 ssa_458 = uge32 ssa_456, ssa_457.x
>								/* succs: block_68 block_69 */
>								if ssa_458 {
>									block block_68:
>									/* preds: block_67 */
>									break
>									/* succs: block_71 */
>								} else {
>									block block_69:
>									/* preds: block_67 */
>									/* succs: block_70 */
>								}
>								block block_70:
>								/* preds: block_69 */
>								vec1 32 ssa_459 = ffloor ssa_454
>								vec1 32 ssa_460 = ffloor ssa_455
>								vec1 32 ssa_461 = fadd ssa_454, -ssa_459
>								vec1 32 ssa_462 = fadd ssa_455, -ssa_460
>								vec1 32 ssa_463 = u2f32 ssa_451
>								vec1 32 ssa_464 = u2f32 ssa_452
>								vec1 32 ssa_465 = fadd ssa_461, ssa_463
>								vec1 32 ssa_466 = fmul ssa_36, ssa_465
>								vec1 32 ssa_467 = fadd ssa_462, ssa_464
>								vec1 32 ssa_468 = fmul ssa_36, ssa_467
>								vec1 32 ssa_469 = f2i32 ssa_466
>								vec1 32 ssa_470 = f2i32 ssa_468
>								vec3 32 ssa_471 = vec3 ssa_469, ssa_470, ssa_453
>								vec4 32 ssa_472 = txf ssa_471 (coord), ssa_1 (lod), 3 (texture), 3 (sampler), 
>								vec1 32 ssa_473 = ishl ssa_472.w, ssa_70
>								vec1 32 ssa_474 = iadd ssa_472.z, ssa_473
>								vec1 32 ssa_475 = iadd ssa_456, ssa_30
>								vec1 32 ssa_476 = imov ssa_472.x
>								vec1 32 ssa_477 = imov ssa_472.y
>								/* succs: block_67 */
>							}
>							block block_71:
>							/* preds: block_68 */
>							vec1 32 ssa_478 = ffloor ssa_454
>							vec1 32 ssa_479 = ffloor ssa_455
>							vec1 32 ssa_480 = fadd ssa_454, -ssa_478
>							vec1 32 ssa_481 = fadd ssa_455, -ssa_479
>							vec1 32 ssa_482 = u2f32 ssa_451
>							vec1 32 ssa_483 = u2f32 ssa_452
>							vec1 32 ssa_484 = fadd ssa_480, ssa_482
>							vec1 32 ssa_485 = fadd ssa_481, ssa_483
>							vec1 32 ssa_486 = fmin -ssa_438, -ssa_441
>							vec1 32 ssa_487 = fadd ssa_58, ssa_486
>							vec1 32 ssa_488 = fge32 -ssa_418, -ssa_438
>							vec1 32 ssa_489 = fge32 ssa_487, ssa_418
>							vec1 32 ssa_490 = iand ssa_489, ssa_488
>							vec1 32 ssa_491 = fge32 -ssa_418, -ssa_441
>							vec1 32 ssa_492 = iand ssa_490, ssa_491
>							/* succs: block_72 block_73 */
>							if ssa_492 {
>								block block_72:
>								/* preds: block_71 */
>								vec1 32 ssa_493 = load_const (0x3b800000 /* 0.003906 */)
>								vec1 32 ssa_494 = fmul ssa_493, ssa_484
>								vec1 32 ssa_495 = fmul ssa_493, ssa_485
>								vec1 32 ssa_496 = u2f32 ssa_453
>								vec3 32 ssa_497 = vec3 ssa_494, ssa_495, ssa_496
>								vec1 32 ssa_498 = i2f32 ssa_415
>								vec4 32 ssa_499 = txl ssa_497 (coord), ssa_498 (lod), 1 (texture), 1 (sampler), 
>								/* succs: block_74 */
>							} else {
>								block block_73:
>								/* preds: block_71 */
>								vec1 32 ssa_500 = load_const (0x3b800000 /* 0.003906 */)
>								vec1 32 ssa_501 = fmul ssa_500, ssa_484
>								vec1 32 ssa_502 = fmul ssa_500, ssa_485
>								vec1 32 ssa_503 = u2f32 ssa_453
>								vec3 32 ssa_504 = vec3 ssa_501, ssa_502, ssa_503
>								vec1 32 ssa_505 = i2f32 ssa_415
>								vec4 32 ssa_506 = txl ssa_504 (coord), ssa_505 (lod), 2 (texture), 2 (sampler), 
>								/* succs: block_74 */
>							}
>							block block_74:
>							/* preds: block_72 block_73 */
>							vec4 32 ssa_507 = phi block_72: ssa_499, block_73: ssa_506
>							vec1 32 ssa_508 = imov ssa_507.x
>							vec1 32 ssa_509 = imov ssa_507.y
>							vec1 32 ssa_510 = imov ssa_507.z
>							vec1 32 ssa_511 = imov ssa_507.w
>							/* succs: block_116 */
>						} else {
>							block block_75:
>							/* preds: block_65 */
>							vec1 32 ssa_512 = fmax ssa_323, ssa_33
>							vec1 32 ssa_513 = fmax ssa_326, ssa_33
>							vec1 32 ssa_514 = fadd ssa_321.x, ssa_46
>							vec1 32 ssa_515 = fadd ssa_321.y, ssa_46
>							vec1 32 ssa_516 = fmin ssa_512, ssa_514
>							vec1 32 ssa_517 = fmin ssa_513, ssa_515
>							vec4 32 ssa_518 = intrinsic load_input (ssa_1) (39, 0) /* base=39 */ /* component=0 */	/* fastuidraw_float_flat_varying2 */
>							vec1 32 ssa_519 = ffma ssa_516, ssa_321.z, ssa_518.z
>							vec1 32 ssa_520 = ffma ssa_517, ssa_321.z, ssa_518.w
>							vec1 32 ssa_521 = ffma -ssa_37, ssa_321.z, ssa_519
>							vec1 32 ssa_522 = ffma -ssa_37, ssa_321.z, ssa_520
>							vec1 32 ssa_523 = fadd ssa_521, -ssa_518.z
>							vec1 32 ssa_524 = fadd ssa_522, -ssa_518.w
>							vec1 32 ssa_525 = fmul ssa_523, ssa_321.w
>							vec1 32 ssa_526 = fmul ssa_524, ssa_321.w
>							vec1 32 ssa_527 = fmul ssa_525, ssa_57
>							vec1 32 ssa_528 = ffloor ssa_527
>							vec1 32 ssa_529 = ffma -ssa_56, ssa_528, ssa_525
>							vec1 32 ssa_530 = fadd ssa_58, -ssa_529
>							vec1 32 ssa_531 = fmul ssa_526, ssa_57
>							vec1 32 ssa_532 = ffloor ssa_531
>							vec1 32 ssa_533 = ffma -ssa_56, ssa_532, ssa_526
>							vec1 32 ssa_534 = fadd ssa_58, -ssa_533
>							vec1 32 ssa_535 = ffract ssa_525
>							vec1 32 ssa_536 = ffract ssa_526
>							vec1 32 ssa_537 = fmul ssa_535, ssa_535
>							vec1 32 ssa_538 = fmul ssa_537, ssa_535
>							vec1 32 ssa_539 = fadd ssa_35, -ssa_535
>							vec1 32 ssa_540 = fmul ssa_539, ssa_539
>							vec1 32 ssa_541 = fmul ssa_540, ssa_539
>							vec1 32 ssa_542 = fmul ssa_60, ssa_537
>							vec1 32 ssa_543 = ffma ssa_59, ssa_538, -ssa_542
>							vec1 32 ssa_544 = fadd ssa_543, ssa_36
>							vec1 32 ssa_545 = ffma ssa_59, ssa_541, ssa_36
>							vec1 32 ssa_546 = ffma -ssa_60, ssa_540, ssa_545
>							vec1 32 ssa_547 = load_const (0x3e2aaaab /* 0.166667 */)
>							vec1 32 ssa_548 = fmul ssa_544, ssa_547
>							vec1 32 ssa_549 = fmul ssa_538, ssa_547
>							vec1 32 ssa_550 = fmul ssa_536, ssa_536
>							vec1 32 ssa_551 = fmul ssa_550, ssa_536
>							vec1 32 ssa_552 = fadd ssa_35, -ssa_536
>							vec1 32 ssa_553 = fmul ssa_552, ssa_552
>							vec1 32 ssa_554 = fmul ssa_553, ssa_552
>							vec1 32 ssa_555 = fmul ssa_60, ssa_550
>							vec1 32 ssa_556 = ffma ssa_59, ssa_551, -ssa_555
>							vec1 32 ssa_557 = fadd ssa_556, ssa_36
>							vec1 32 ssa_558 = ffma ssa_59, ssa_554, ssa_36
>							vec1 32 ssa_559 = ffma -ssa_60, ssa_553, ssa_558
>							vec1 32 ssa_560 = fmul ssa_557, ssa_547
>							vec1 32 ssa_561 = fmul ssa_551, ssa_547
>							vec1 32 ssa_562 = fadd ssa_541, ssa_544
>							vec1 32 ssa_563 = fmul ssa_547, ssa_562
>							vec1 32 ssa_564 = fadd ssa_546, ssa_538
>							vec1 32 ssa_565 = fmul ssa_547, ssa_564
>							vec1 32 ssa_566 = fadd ssa_554, ssa_557
>							vec1 32 ssa_567 = fmul ssa_547, ssa_566
>							vec1 32 ssa_568 = fadd ssa_559, ssa_551
>							vec1 32 ssa_569 = fmul ssa_547, ssa_568
>							vec1 32 ssa_570 = frcp ssa_563
>							vec1 32 ssa_571 = frcp ssa_565
>							vec1 32 ssa_572 = frcp ssa_567
>							vec1 32 ssa_573 = frcp ssa_569
>							vec1 32 ssa_574 = fadd ssa_562, ssa_564
>							vec1 32 ssa_575 = fmul ssa_547, ssa_574
>							vec1 32 ssa_576 = frcp ssa_575
>							vec1 32 ssa_577 = fmul ssa_565, ssa_576
>							vec1 32 ssa_578 = fadd ssa_566, ssa_568
>							vec1 32 ssa_579 = fmul ssa_547, ssa_578
>							vec1 32 ssa_580 = frcp ssa_579
>							vec1 32 ssa_581 = fmul ssa_569, ssa_580
>							vec1 32 ssa_582 = fmax -ssa_529, -ssa_533
>							vec1 32 ssa_583 = fge32 ssa_530, ssa_62
>							vec1 32 ssa_584 = fge32 ssa_61, ssa_582
>							vec1 32 ssa_585 = iand ssa_584, ssa_583
>							vec1 32 ssa_586 = fge32 ssa_534, ssa_62
>							vec1 32 ssa_587 = iand ssa_585, ssa_586
>							/* succs: block_76 block_82 */
>							if ssa_587 {
>								block block_76:
>								/* preds: block_75 */
>								vec1 32 ssa_588 = f2i32 ssa_521
>								vec1 32 ssa_589 = f2i32 ssa_522
>								vec4 32 ssa_590 = intrinsic load_input (ssa_1) (31, 0) /* base=31 */ /* component=0 */	/* fastuidraw_uint_varying0 */
>								vec3 32 ssa_591 = vec3 ssa_588, ssa_589, ssa_590.w
>								vec4 32 ssa_592 = txf ssa_591 (coord), ssa_1 (lod), 3 (texture), 3 (sampler), 
>								vec1 32 ssa_593 = ishl ssa_592.w, ssa_70
>								vec1 32 ssa_594 = iadd ssa_592.z, ssa_593
>								vec1 32 ssa_595 = imov ssa_592.x
>								vec1 32 ssa_596 = imov ssa_592.y
>								/* succs: block_77 */
>								loop {
>									block block_77:
>									/* preds: block_76 block_80 */
>									vec1 32 ssa_597 = phi block_76: ssa_595, block_80: ssa_622
>									vec1 32 ssa_598 = phi block_76: ssa_596, block_80: ssa_623
>									vec1 32 ssa_599 = phi block_76: ssa_594, block_80: ssa_620
>									vec1 32 ssa_600 = phi block_76: ssa_521, block_80: ssa_612
>									vec1 32 ssa_601 = phi block_76: ssa_522, block_80: ssa_614
>									vec1 32 ssa_602 = phi block_76: ssa_30, block_80: ssa_621
>									vec2 32 ssa_603 = intrinsic load_input (ssa_1) (32, 0) /* base=32 */ /* component=0 */	/* fastuidraw_uint_varying1 */
>									vec1 32 ssa_604 = uge32 ssa_602, ssa_603.x
>									/* succs: block_78 block_79 */
>									if ssa_604 {
>										block block_78:
>										/* preds: block_77 */
>										break
>										/* succs: block_81 */
>									} else {
>										block block_79:
>										/* preds: block_77 */
>										/* succs: block_80 */
>									}
>									block block_80:
>									/* preds: block_79 */
>									vec1 32 ssa_605 = ffloor ssa_600
>									vec1 32 ssa_606 = ffloor ssa_601
>									vec1 32 ssa_607 = fadd ssa_600, -ssa_605
>									vec1 32 ssa_608 = fadd ssa_601, -ssa_606
>									vec1 32 ssa_609 = u2f32 ssa_597
>									vec1 32 ssa_610 = u2f32 ssa_598
>									vec1 32 ssa_611 = fadd ssa_607, ssa_609
>									vec1 32 ssa_612 = fmul ssa_36, ssa_611
>									vec1 32 ssa_613 = fadd ssa_608, ssa_610
>									vec1 32 ssa_614 = fmul ssa_36, ssa_613
>									vec1 32 ssa_615 = f2i32 ssa_612
>									vec1 32 ssa_616 = f2i32 ssa_614
>									vec3 32 ssa_617 = vec3 ssa_615, ssa_616, ssa_599
>									vec4 32 ssa_618 = txf ssa_617 (coord), ssa_1 (lod), 3 (texture), 3 (sampler), 
>									vec1 32 ssa_619 = ishl ssa_618.w, ssa_70
>									vec1 32 ssa_620 = iadd ssa_618.z, ssa_619
>									vec1 32 ssa_621 = iadd ssa_602, ssa_30
>									vec1 32 ssa_622 = imov ssa_618.x
>									vec1 32 ssa_623 = imov ssa_618.y
>									/* succs: block_77 */
>								}
>								block block_81:
>								/* preds: block_78 */
>								vec1 32 ssa_624 = ffloor ssa_600
>								vec1 32 ssa_625 = ffloor ssa_601
>								vec1 32 ssa_626 = fadd ssa_600, -ssa_624
>								vec1 32 ssa_627 = fadd ssa_601, -ssa_625
>								vec1 32 ssa_628 = u2f32 ssa_597
>								vec1 32 ssa_629 = u2f32 ssa_598
>								vec1 32 ssa_630 = fadd ssa_626, ssa_628
>								vec1 32 ssa_631 = fadd ssa_627, ssa_629
>								vec1 32 ssa_632 = ffma ssa_56, ssa_630, -ssa_535
>								vec1 32 ssa_633 = ffma ssa_56, ssa_631, -ssa_536
>								vec1 32 ssa_634 = fadd ssa_632, ssa_63
>								vec1 32 ssa_635 = ffma ssa_548, ssa_570, ssa_634
>								vec1 32 ssa_636 = fadd ssa_632, ssa_64
>								vec1 32 ssa_637 = ffma ssa_549, ssa_571, ssa_636
>								vec1 32 ssa_638 = fadd ssa_633, ssa_63
>								vec1 32 ssa_639 = ffma ssa_560, ssa_572, ssa_638
>								vec1 32 ssa_640 = fadd ssa_633, ssa_64
>								vec1 32 ssa_641 = ffma ssa_561, ssa_573, ssa_640
>								vec1 32 ssa_642 = fmul ssa_635, ssa_65
>								vec1 32 ssa_643 = fmul ssa_637, ssa_65
>								vec1 32 ssa_644 = fmul ssa_639, ssa_65
>								vec1 32 ssa_645 = fmul ssa_641, ssa_65
>								vec1 32 ssa_646 = u2f32 ssa_599
>								vec3 32 ssa_647 = vec3 ssa_642, ssa_644, ssa_646
>								vec4 32 ssa_648 = txl ssa_647 (coord), ssa_1 (lod), 1 (texture), 1 (sampler), 
>								vec3 32 ssa_649 = vec3 ssa_643, ssa_644, ssa_646
>								vec4 32 ssa_650 = txl ssa_649 (coord), ssa_1 (lod), 1 (texture), 1 (sampler), 
>								vec3 32 ssa_651 = vec3 ssa_642, ssa_645, ssa_646
>								vec4 32 ssa_652 = txl ssa_651 (coord), ssa_1 (lod), 1 (texture), 1 (sampler), 
>								vec3 32 ssa_653 = vec3 ssa_643, ssa_645, ssa_646
>								vec4 32 ssa_654 = txl ssa_653 (coord), ssa_1 (lod), 1 (texture), 1 (sampler), 
>								/* succs: block_115 */
>							} else {
>								block block_82:
>								/* preds: block_75 */
>								vec1 32 ssa_655 = ffma -ssa_535, ssa_321.z, ssa_521
>								vec1 32 ssa_656 = ffma -ssa_536, ssa_321.z, ssa_522
>								vec1 32 ssa_657 = ffma -ssa_37, ssa_321.z, ssa_655
>								vec1 32 ssa_658 = ffma -ssa_37, ssa_321.z, ssa_656
>								vec1 32 ssa_659 = ffma ssa_64, ssa_321.z, ssa_655
>								vec1 32 ssa_660 = ffma ssa_64, ssa_321.z, ssa_656
>								vec1 32 ssa_661 = fmul ssa_548, ssa_570
>								vec1 32 ssa_662 = fmul ssa_549, ssa_571
>								vec1 32 ssa_663 = fmul ssa_560, ssa_572
>								vec1 32 ssa_664 = fmul ssa_561, ssa_573
>								vec1 32 ssa_665 = ffma ssa_661, ssa_321.z, ssa_657
>								vec1 32 ssa_666 = ffma ssa_662, ssa_321.z, ssa_659
>								vec1 32 ssa_667 = ffma ssa_663, ssa_321.z, ssa_658
>								vec1 32 ssa_668 = ffma ssa_664, ssa_321.z, ssa_660
>								vec1 32 ssa_669 = fmul ssa_39, ssa_665
>								vec1 32 ssa_670 = fmul ssa_39, ssa_667
>								vec1 32 ssa_671 = ffloor ssa_669
>								vec1 32 ssa_672 = ffloor ssa_670
>								vec1 32 ssa_673 = ffma -ssa_36, ssa_671, ssa_665
>								vec1 32 ssa_674 = ffma -ssa_36, ssa_672, ssa_667
>								vec1 32 ssa_675 = fmul ssa_673, ssa_321.w
>								vec1 32 ssa_676 = fmul ssa_674, ssa_321.w
>								vec1 32 ssa_677 = fmul ssa_675, ssa_57
>								vec1 32 ssa_678 = ffloor ssa_677
>								vec1 32 ssa_679 = ffma -ssa_56, ssa_678, ssa_675
>								vec1 32 ssa_680 = fadd ssa_58, -ssa_679
>								vec1 32 ssa_681 = fmul ssa_676, ssa_57
>								vec1 32 ssa_682 = ffloor ssa_681
>								vec1 32 ssa_683 = ffma -ssa_56, ssa_682, ssa_676
>								vec1 32 ssa_684 = fadd ssa_58, -ssa_683
>								vec1 32 ssa_685 = f2i32 ssa_665
>								vec1 32 ssa_686 = f2i32 ssa_667
>								vec4 32 ssa_687 = intrinsic load_input (ssa_1) (31, 0) /* base=31 */ /* component=0 */	/* fastuidraw_uint_varying0 */
>								vec3 32 ssa_688 = vec3 ssa_685, ssa_686, ssa_687.w
>								vec4 32 ssa_689 = txf ssa_688 (coord), ssa_1 (lod), 3 (texture), 3 (sampler), 
>								vec1 32 ssa_690 = ishl ssa_689.w, ssa_70
>								vec1 32 ssa_691 = iadd ssa_689.z, ssa_690
>								vec1 32 ssa_692 = imov ssa_689.x
>								vec1 32 ssa_693 = imov ssa_689.y
>								/* succs: block_83 */
>								loop {
>									block block_83:
>									/* preds: block_82 block_86 */
>									vec1 32 ssa_694 = phi block_82: ssa_692, block_86: ssa_719
>									vec1 32 ssa_695 = phi block_82: ssa_693, block_86: ssa_720
>									vec1 32 ssa_696 = phi block_82: ssa_691, block_86: ssa_717
>									vec1 32 ssa_697 = phi block_82: ssa_665, block_86: ssa_709
>									vec1 32 ssa_698 = phi block_82: ssa_667, block_86: ssa_711
>									vec1 32 ssa_699 = phi block_82: ssa_30, block_86: ssa_718
>									vec2 32 ssa_700 = intrinsic load_input (ssa_1) (32, 0) /* base=32 */ /* component=0 */	/* fastuidraw_uint_varying1 */
>									vec1 32 ssa_701 = uge32 ssa_699, ssa_700.x
>									/* succs: block_84 block_85 */
>									if ssa_701 {
>										block block_84:
>										/* preds: block_83 */
>										break
>										/* succs: block_87 */
>									} else {
>										block block_85:
>										/* preds: block_83 */
>										/* succs: block_86 */
>									}
>									block block_86:
>									/* preds: block_85 */
>									vec1 32 ssa_702 = ffloor ssa_697
>									vec1 32 ssa_703 = ffloor ssa_698
>									vec1 32 ssa_704 = fadd ssa_697, -ssa_702
>									vec1 32 ssa_705 = fadd ssa_698, -ssa_703
>									vec1 32 ssa_706 = u2f32 ssa_694
>									vec1 32 ssa_707 = u2f32 ssa_695
>									vec1 32 ssa_708 = fadd ssa_704, ssa_706
>									vec1 32 ssa_709 = fmul ssa_36, ssa_708
>									vec1 32 ssa_710 = fadd ssa_705, ssa_707
>									vec1 32 ssa_711 = fmul ssa_36, ssa_710
>									vec1 32 ssa_712 = f2i32 ssa_709
>									vec1 32 ssa_713 = f2i32 ssa_711
>									vec3 32 ssa_714 = vec3 ssa_712, ssa_713, ssa_696
>									vec4 32 ssa_715 = txf ssa_714 (coord), ssa_1 (lod), 3 (texture), 3 (sampler), 
>									vec1 32 ssa_716 = ishl ssa_715.w, ssa_70
>									vec1 32 ssa_717 = iadd ssa_715.z, ssa_716
>									vec1 32 ssa_718 = iadd ssa_699, ssa_30
>									vec1 32 ssa_719 = imov ssa_715.x
>									vec1 32 ssa_720 = imov ssa_715.y
>									/* succs: block_83 */
>								}
>								block block_87:
>								/* preds: block_84 */
>								vec1 32 ssa_721 = ffloor ssa_697
>								vec1 32 ssa_722 = ffloor ssa_698
>								vec1 32 ssa_723 = fadd ssa_697, -ssa_721
>								vec1 32 ssa_724 = fadd ssa_698, -ssa_722
>								vec1 32 ssa_725 = u2f32 ssa_694
>								vec1 32 ssa_726 = u2f32 ssa_695
>								vec1 32 ssa_727 = fadd ssa_723, ssa_725
>								vec1 32 ssa_728 = fadd ssa_724, ssa_726
>								vec1 32 ssa_729 = fge32 ssa_684, ssa_37
>								vec1 32 ssa_730 = fge32 ssa_680, ssa_37
>								vec1 32 ssa_731 = iand ssa_730, ssa_729
>								vec1 32 ssa_732 = fge32 ssa_63, -ssa_679
>								vec1 32 ssa_733 = iand ssa_731, ssa_732
>								vec1 32 ssa_734 = fge32 ssa_63, -ssa_683
>								vec1 32 ssa_735 = iand ssa_733, ssa_734
>								/* succs: block_88 block_89 */
>								if ssa_735 {
>									block block_88:
>									/* preds: block_87 */
>									vec1 32 ssa_736 = load_const (0x3b800000 /* 0.003906 */)
>									vec1 32 ssa_737 = fmul ssa_736, ssa_727
>									vec1 32 ssa_738 = fmul ssa_736, ssa_728
>									vec1 32 ssa_739 = u2f32 ssa_696
>									vec3 32 ssa_740 = vec3 ssa_737, ssa_738, ssa_739
>									vec4 32 ssa_741 = txl ssa_740 (coord), ssa_1 (lod), 1 (texture), 1 (sampler), 
>									/* succs: block_90 */
>								} else {
>									block block_89:
>									/* preds: block_87 */
>									vec1 32 ssa_742 = load_const (0x3b800000 /* 0.003906 */)
>									vec1 32 ssa_743 = fmul ssa_742, ssa_727
>									vec1 32 ssa_744 = fmul ssa_742, ssa_728
>									vec1 32 ssa_745 = u2f32 ssa_696
>									vec3 32 ssa_746 = vec3 ssa_743, ssa_744, ssa_745
>									vec4 32 ssa_747 = txl ssa_746 (coord), ssa_1 (lod), 2 (texture), 2 (sampler), 
>									/* succs: block_90 */
>								}
>								block block_90:
>								/* preds: block_88 block_89 */
>								vec4 32 ssa_748 = phi block_88: ssa_741, block_89: ssa_747
>								vec1 32 ssa_749 = fmul ssa_39, ssa_666
>								vec1 32 ssa_750 = ffloor ssa_749
>								vec1 32 ssa_751 = ffma -ssa_36, ssa_750, ssa_666
>								vec1 32 ssa_752 = fmul ssa_751, ssa_321.w
>								vec1 32 ssa_753 = fmul ssa_752, ssa_57
>								vec1 32 ssa_754 = ffloor ssa_753
>								vec1 32 ssa_755 = ffma -ssa_56, ssa_754, ssa_752
>								vec1 32 ssa_756 = fadd ssa_58, -ssa_755
>								vec1 32 ssa_757 = f2i32 ssa_666
>								vec3 32 ssa_758 = vec3 ssa_757, ssa_686, ssa_687.w
>								vec4 32 ssa_759 = txf ssa_758 (coord), ssa_1 (lod), 3 (texture), 3 (sampler), 
>								vec1 32 ssa_760 = ishl ssa_759.w, ssa_70
>								vec1 32 ssa_761 = iadd ssa_759.z, ssa_760
>								vec1 32 ssa_762 = imov ssa_759.x
>								vec1 32 ssa_763 = imov ssa_759.y
>								/* succs: block_91 */
>								loop {
>									block block_91:
>									/* preds: block_90 block_94 */
>									vec1 32 ssa_764 = phi block_90: ssa_762, block_94: ssa_788
>									vec1 32 ssa_765 = phi block_90: ssa_763, block_94: ssa_789
>									vec1 32 ssa_766 = phi block_90: ssa_761, block_94: ssa_786
>									vec1 32 ssa_767 = phi block_90: ssa_666, block_94: ssa_778
>									vec1 32 ssa_768 = phi block_90: ssa_667, block_94: ssa_780
>									vec1 32 ssa_769 = phi block_90: ssa_30, block_94: ssa_787
>									vec1 32 ssa_770 = uge32 ssa_769, ssa_700.x
>									/* succs: block_92 block_93 */
>									if ssa_770 {
>										block block_92:
>										/* preds: block_91 */
>										break
>										/* succs: block_95 */
>									} else {
>										block block_93:
>										/* preds: block_91 */
>										/* succs: block_94 */
>									}
>									block block_94:
>									/* preds: block_93 */
>									vec1 32 ssa_771 = ffloor ssa_767
>									vec1 32 ssa_772 = ffloor ssa_768
>									vec1 32 ssa_773 = fadd ssa_767, -ssa_771
>									vec1 32 ssa_774 = fadd ssa_768, -ssa_772
>									vec1 32 ssa_775 = u2f32 ssa_764
>									vec1 32 ssa_776 = u2f32 ssa_765
>									vec1 32 ssa_777 = fadd ssa_773, ssa_775
>									vec1 32 ssa_778 = fmul ssa_36, ssa_777
>									vec1 32 ssa_779 = fadd ssa_774, ssa_776
>									vec1 32 ssa_780 = fmul ssa_36, ssa_779
>									vec1 32 ssa_781 = f2i32 ssa_778
>									vec1 32 ssa_782 = f2i32 ssa_780
>									vec3 32 ssa_783 = vec3 ssa_781, ssa_782, ssa_766
>									vec4 32 ssa_784 = txf ssa_783 (coord), ssa_1 (lod), 3 (texture), 3 (sampler), 
>									vec1 32 ssa_785 = ishl ssa_784.w, ssa_70
>									vec1 32 ssa_786 = iadd ssa_784.z, ssa_785
>									vec1 32 ssa_787 = iadd ssa_769, ssa_30
>									vec1 32 ssa_788 = imov ssa_784.x
>									vec1 32 ssa_789 = imov ssa_784.y
>									/* succs: block_91 */
>								}
>								block block_95:
>								/* preds: block_92 */
>								vec1 32 ssa_790 = ffloor ssa_767
>								vec1 32 ssa_791 = ffloor ssa_768
>								vec1 32 ssa_792 = fadd ssa_767, -ssa_790
>								vec1 32 ssa_793 = fadd ssa_768, -ssa_791
>								vec1 32 ssa_794 = u2f32 ssa_764
>								vec1 32 ssa_795 = u2f32 ssa_765
>								vec1 32 ssa_796 = fadd ssa_792, ssa_794
>								vec1 32 ssa_797 = fadd ssa_793, ssa_795
>								vec1 32 ssa_798 = fge32 ssa_756, ssa_37
>								vec1 32 ssa_799 = iand ssa_798, ssa_729
>								vec1 32 ssa_800 = fge32 ssa_63, -ssa_755
>								vec1 32 ssa_801 = iand ssa_799, ssa_800
>								vec1 32 ssa_802 = iand ssa_801, ssa_734
>								/* succs: block_96 block_97 */
>								if ssa_802 {
>									block block_96:
>									/* preds: block_95 */
>									vec1 32 ssa_803 = load_const (0x3b800000 /* 0.003906 */)
>									vec1 32 ssa_804 = fmul ssa_803, ssa_796
>									vec1 32 ssa_805 = fmul ssa_803, ssa_797
>									vec1 32 ssa_806 = u2f32 ssa_766
>									vec3 32 ssa_807 = vec3 ssa_804, ssa_805, ssa_806
>									vec4 32 ssa_808 = txl ssa_807 (coord), ssa_1 (lod), 1 (texture), 1 (sampler), 
>									/* succs: block_98 */
>								} else {
>									block block_97:
>									/* preds: block_95 */
>									vec1 32 ssa_809 = load_const (0x3b800000 /* 0.003906 */)
>									vec1 32 ssa_810 = fmul ssa_809, ssa_796
>									vec1 32 ssa_811 = fmul ssa_809, ssa_797
>									vec1 32 ssa_812 = u2f32 ssa_766
>									vec3 32 ssa_813 = vec3 ssa_810, ssa_811, ssa_812
>									vec4 32 ssa_814 = txl ssa_813 (coord), ssa_1 (lod), 2 (texture), 2 (sampler), 
>									/* succs: block_98 */
>								}
>								block block_98:
>								/* preds: block_96 block_97 */
>								vec4 32 ssa_815 = phi block_96: ssa_808, block_97: ssa_814
>								vec1 32 ssa_816 = fmul ssa_39, ssa_668
>								vec1 32 ssa_817 = ffloor ssa_816
>								vec1 32 ssa_818 = ffma -ssa_36, ssa_817, ssa_668
>								vec1 32 ssa_819 = fmul ssa_818, ssa_321.w
>								vec1 32 ssa_820 = fmul ssa_819, ssa_57
>								vec1 32 ssa_821 = ffloor ssa_820
>								vec1 32 ssa_822 = ffma -ssa_56, ssa_821, ssa_819
>								vec1 32 ssa_823 = fadd ssa_58, -ssa_822
>								vec1 32 ssa_824 = f2i32 ssa_668
>								vec3 32 ssa_825 = vec3 ssa_685, ssa_824, ssa_687.w
>								vec4 32 ssa_826 = txf ssa_825 (coord), ssa_1 (lod), 3 (texture), 3 (sampler), 
>								vec1 32 ssa_827 = ishl ssa_826.w, ssa_70
>								vec1 32 ssa_828 = iadd ssa_826.z, ssa_827
>								vec1 32 ssa_829 = imov ssa_826.x
>								vec1 32 ssa_830 = imov ssa_826.y
>								/* succs: block_99 */
>								loop {
>									block block_99:
>									/* preds: block_98 block_102 */
>									vec1 32 ssa_831 = phi block_98: ssa_829, block_102: ssa_855
>									vec1 32 ssa_832 = phi block_98: ssa_830, block_102: ssa_856
>									vec1 32 ssa_833 = phi block_98: ssa_828, block_102: ssa_853
>									vec1 32 ssa_834 = phi block_98: ssa_665, block_102: ssa_845
>									vec1 32 ssa_835 = phi block_98: ssa_668, block_102: ssa_847
>									vec1 32 ssa_836 = phi block_98: ssa_30, block_102: ssa_854
>									vec1 32 ssa_837 = uge32 ssa_836, ssa_700.x
>									/* succs: block_100 block_101 */
>									if ssa_837 {
>										block block_100:
>										/* preds: block_99 */
>										break
>										/* succs: block_103 */
>									} else {
>										block block_101:
>										/* preds: block_99 */
>										/* succs: block_102 */
>									}
>									block block_102:
>									/* preds: block_101 */
>									vec1 32 ssa_838 = ffloor ssa_834
>									vec1 32 ssa_839 = ffloor ssa_835
>									vec1 32 ssa_840 = fadd ssa_834, -ssa_838
>									vec1 32 ssa_841 = fadd ssa_835, -ssa_839
>									vec1 32 ssa_842 = u2f32 ssa_831
>									vec1 32 ssa_843 = u2f32 ssa_832
>									vec1 32 ssa_844 = fadd ssa_840, ssa_842
>									vec1 32 ssa_845 = fmul ssa_36, ssa_844
>									vec1 32 ssa_846 = fadd ssa_841, ssa_843
>									vec1 32 ssa_847 = fmul ssa_36, ssa_846
>									vec1 32 ssa_848 = f2i32 ssa_845
>									vec1 32 ssa_849 = f2i32 ssa_847
>									vec3 32 ssa_850 = vec3 ssa_848, ssa_849, ssa_833
>									vec4 32 ssa_851 = txf ssa_850 (coord), ssa_1 (lod), 3 (texture), 3 (sampler), 
>									vec1 32 ssa_852 = ishl ssa_851.w, ssa_70
>									vec1 32 ssa_853 = iadd ssa_851.z, ssa_852
>									vec1 32 ssa_854 = iadd ssa_836, ssa_30
>									vec1 32 ssa_855 = imov ssa_851.x
>									vec1 32 ssa_856 = imov ssa_851.y
>									/* succs: block_99 */
>								}
>								block block_103:
>								/* preds: block_100 */
>								vec1 32 ssa_857 = ffloor ssa_834
>								vec1 32 ssa_858 = ffloor ssa_835
>								vec1 32 ssa_859 = fadd ssa_834, -ssa_857
>								vec1 32 ssa_860 = fadd ssa_835, -ssa_858
>								vec1 32 ssa_861 = u2f32 ssa_831
>								vec1 32 ssa_862 = u2f32 ssa_832
>								vec1 32 ssa_863 = fadd ssa_859, ssa_861
>								vec1 32 ssa_864 = fadd ssa_860, ssa_862
>								vec1 32 ssa_865 = fge32 ssa_823, ssa_37
>								vec1 32 ssa_866 = iand ssa_730, ssa_865
>								vec1 32 ssa_867 = iand ssa_866, ssa_732
>								vec1 32 ssa_868 = fge32 ssa_63, -ssa_822
>								vec1 32 ssa_869 = iand ssa_867, ssa_868
>								/* succs: block_104 block_105 */
>								if ssa_869 {
>									block block_104:
>									/* preds: block_103 */
>									vec1 32 ssa_870 = load_const (0x3b800000 /* 0.003906 */)
>									vec1 32 ssa_871 = fmul ssa_870, ssa_863
>									vec1 32 ssa_872 = fmul ssa_870, ssa_864
>									vec1 32 ssa_873 = u2f32 ssa_833
>									vec3 32 ssa_874 = vec3 ssa_871, ssa_872, ssa_873
>									vec4 32 ssa_875 = txl ssa_874 (coord), ssa_1 (lod), 1 (texture), 1 (sampler), 
>									/* succs: block_106 */
>								} else {
>									block block_105:
>									/* preds: block_103 */
>									vec1 32 ssa_876 = load_const (0x3b800000 /* 0.003906 */)
>									vec1 32 ssa_877 = fmul ssa_876, ssa_863
>									vec1 32 ssa_878 = fmul ssa_876, ssa_864
>									vec1 32 ssa_879 = u2f32 ssa_833
>									vec3 32 ssa_880 = vec3 ssa_877, ssa_878, ssa_879
>									vec4 32 ssa_881 = txl ssa_880 (coord), ssa_1 (lod), 2 (texture), 2 (sampler), 
>									/* succs: block_106 */
>								}
>								block block_106:
>								/* preds: block_104 block_105 */
>								vec4 32 ssa_882 = phi block_104: ssa_875, block_105: ssa_881
>								vec3 32 ssa_883 = vec3 ssa_757, ssa_824, ssa_687.w
>								vec4 32 ssa_884 = txf ssa_883 (coord), ssa_1 (lod), 3 (texture), 3 (sampler), 
>								vec1 32 ssa_885 = ishl ssa_884.w, ssa_70
>								vec1 32 ssa_886 = iadd ssa_884.z, ssa_885
>								vec1 32 ssa_887 = imov ssa_884.x
>								vec1 32 ssa_888 = imov ssa_884.y
>								/* succs: block_107 */
>								loop {
>									block block_107:
>									/* preds: block_106 block_110 */
>									vec1 32 ssa_889 = phi block_106: ssa_887, block_110: ssa_913
>									vec1 32 ssa_890 = phi block_106: ssa_888, block_110: ssa_914
>									vec1 32 ssa_891 = phi block_106: ssa_886, block_110: ssa_911
>									vec1 32 ssa_892 = phi block_106: ssa_666, block_110: ssa_903
>									vec1 32 ssa_893 = phi block_106: ssa_668, block_110: ssa_905
>									vec1 32 ssa_894 = phi block_106: ssa_30, block_110: ssa_912
>									vec1 32 ssa_895 = uge32 ssa_894, ssa_700.x
>									/* succs: block_108 block_109 */
>									if ssa_895 {
>										block block_108:
>										/* preds: block_107 */
>										break
>										/* succs: block_111 */
>									} else {
>										block block_109:
>										/* preds: block_107 */
>										/* succs: block_110 */
>									}
>									block block_110:
>									/* preds: block_109 */
>									vec1 32 ssa_896 = ffloor ssa_892
>									vec1 32 ssa_897 = ffloor ssa_893
>									vec1 32 ssa_898 = fadd ssa_892, -ssa_896
>									vec1 32 ssa_899 = fadd ssa_893, -ssa_897
>									vec1 32 ssa_900 = u2f32 ssa_889
>									vec1 32 ssa_901 = u2f32 ssa_890
>									vec1 32 ssa_902 = fadd ssa_898, ssa_900
>									vec1 32 ssa_903 = fmul ssa_36, ssa_902
>									vec1 32 ssa_904 = fadd ssa_899, ssa_901
>									vec1 32 ssa_905 = fmul ssa_36, ssa_904
>									vec1 32 ssa_906 = f2i32 ssa_903
>									vec1 32 ssa_907 = f2i32 ssa_905
>									vec3 32 ssa_908 = vec3 ssa_906, ssa_907, ssa_891
>									vec4 32 ssa_909 = txf ssa_908 (coord), ssa_1 (lod), 3 (texture), 3 (sampler), 
>									vec1 32 ssa_910 = ishl ssa_909.w, ssa_70
>									vec1 32 ssa_911 = iadd ssa_909.z, ssa_910
>									vec1 32 ssa_912 = iadd ssa_894, ssa_30
>									vec1 32 ssa_913 = imov ssa_909.x
>									vec1 32 ssa_914 = imov ssa_909.y
>									/* succs: block_107 */
>								}
>								block block_111:
>								/* preds: block_108 */
>								vec1 32 ssa_915 = ffloor ssa_892
>								vec1 32 ssa_916 = ffloor ssa_893
>								vec1 32 ssa_917 = fadd ssa_892, -ssa_915
>								vec1 32 ssa_918 = fadd ssa_893, -ssa_916
>								vec1 32 ssa_919 = u2f32 ssa_889
>								vec1 32 ssa_920 = u2f32 ssa_890
>								vec1 32 ssa_921 = fadd ssa_917, ssa_919
>								vec1 32 ssa_922 = fadd ssa_918, ssa_920
>								vec1 32 ssa_923 = iand ssa_798, ssa_865
>								vec1 32 ssa_924 = iand ssa_923, ssa_800
>								vec1 32 ssa_925 = iand ssa_924, ssa_868
>								/* succs: block_112 block_113 */
>								if ssa_925 {
>									block block_112:
>									/* preds: block_111 */
>									vec1 32 ssa_926 = load_const (0x3b800000 /* 0.003906 */)
>									vec1 32 ssa_927 = fmul ssa_926, ssa_921
>									vec1 32 ssa_928 = fmul ssa_926, ssa_922
>									vec1 32 ssa_929 = u2f32 ssa_891
>									vec3 32 ssa_930 = vec3 ssa_927, ssa_928, ssa_929
>									vec4 32 ssa_931 = txl ssa_930 (coord), ssa_1 (lod), 1 (texture), 1 (sampler), 
>									/* succs: block_114 */
>								} else {
>									block block_113:
>									/* preds: block_111 */
>									vec1 32 ssa_932 = load_const (0x3b800000 /* 0.003906 */)
>									vec1 32 ssa_933 = fmul ssa_932, ssa_921
>									vec1 32 ssa_934 = fmul ssa_932, ssa_922
>									vec1 32 ssa_935 = u2f32 ssa_891
>									vec3 32 ssa_936 = vec3 ssa_933, ssa_934, ssa_935
>									vec4 32 ssa_937 = txl ssa_936 (coord), ssa_1 (lod), 2 (texture), 2 (sampler), 
>									/* succs: block_114 */
>								}
>								block block_114:
>								/* preds: block_112 block_113 */
>								vec4 32 ssa_938 = phi block_112: ssa_931, block_113: ssa_937
>								/* succs: block_115 */
>							}
>							block block_115:
>							/* preds: block_81 block_114 */
>							vec4 32 ssa_939 = phi block_81: ssa_654, block_114: ssa_938
>							vec4 32 ssa_940 = phi block_81: ssa_652, block_114: ssa_882
>							vec4 32 ssa_941 = phi block_81: ssa_650, block_114: ssa_815
>							vec4 32 ssa_942 = phi block_81: ssa_648, block_114: ssa_748
>							vec1 32 ssa_943 = flrp ssa_942.x, ssa_941.x, ssa_577
>							vec1 32 ssa_944 = flrp ssa_942.y, ssa_941.y, ssa_577
>							vec1 32 ssa_945 = flrp ssa_942.z, ssa_941.z, ssa_577
>							vec1 32 ssa_946 = flrp ssa_942.w, ssa_941.w, ssa_577
>							vec1 32 ssa_947 = flrp ssa_940.x, ssa_939.x, ssa_577
>							vec1 32 ssa_948 = flrp ssa_940.y, ssa_939.y, ssa_577
>							vec1 32 ssa_949 = flrp ssa_940.z, ssa_939.z, ssa_577
>							vec1 32 ssa_950 = flrp ssa_940.w, ssa_939.w, ssa_577
>							vec1 32 ssa_951 = flrp ssa_943, ssa_947, ssa_581
>							vec1 32 ssa_952 = flrp ssa_944, ssa_948, ssa_581
>							vec1 32 ssa_953 = flrp ssa_945, ssa_949, ssa_581
>							vec1 32 ssa_954 = flrp ssa_946, ssa_950, ssa_581
>							/* succs: block_116 */
>						}
>						block block_116:
>						/* preds: block_74 block_115 */
>						vec1 32 ssa_955 = phi block_74: ssa_508, block_115: ssa_951
>						vec1 32 ssa_956 = phi block_74: ssa_509, block_115: ssa_952
>						vec1 32 ssa_957 = phi block_74: ssa_510, block_115: ssa_953
>						vec1 32 ssa_958 = phi block_74: ssa_511, block_115: ssa_954
>						/* succs: block_117 */
>					}
>					block block_117:
>					/* preds: block_64 block_116 */
>					vec1 32 ssa_959 = phi block_64: ssa_407, block_116: ssa_955
>					vec1 32 ssa_960 = phi block_64: ssa_408, block_116: ssa_956
>					vec1 32 ssa_961 = phi block_64: ssa_409, block_116: ssa_957
>					vec1 32 ssa_962 = phi block_64: ssa_410, block_116: ssa_958
>					/* succs: block_128 */
>				} else {
>					block block_118:
>					/* preds: block_57 */
>					vec1 32 ssa_963 = ine32 ssa_328, ssa_30
>					/* succs: block_119 block_126 */
>					if ssa_963 {
>						block block_119:
>						/* preds: block_118 */
>						vec4 32 ssa_964 = intrinsic load_input (ssa_1) (39, 0) /* base=39 */ /* component=0 */	/* fastuidraw_float_flat_varying2 */
>						vec1 32 ssa_965 = fadd ssa_323, ssa_964.z
>						vec1 32 ssa_966 = fadd ssa_326, ssa_964.w
>						vec1 32 ssa_967 = ieq32 ssa_330, ssa_30
>						/* succs: block_120 block_121 */
>						if ssa_967 {
>							block block_120:
>							/* preds: block_119 */
>							vec1 32 ssa_968 = fceil ssa_345
>							vec1 32 ssa_969 = f2i32 ssa_968
>							vec1 32 ssa_970 = ishl ssa_30, ssa_969
>							vec1 32 ssa_971 = i2f32 ssa_970
>							vec1 32 ssa_972 = frcp ssa_971
>							vec1 32 ssa_973 = fmul ssa_965, ssa_972
>							vec1 32 ssa_974 = fmul ssa_966, ssa_972
>							vec1 32 ssa_975 = f2i32 ssa_973
>							vec1 32 ssa_976 = f2i32 ssa_974
>							vec2 32 ssa_977 = vec2 ssa_975, ssa_976
>							vec4 32 ssa_978 = txf ssa_977 (coord), ssa_969 (lod), 4 (texture), 4 (sampler), 
>							vec1 32 ssa_979 = imov ssa_978.x
>							vec1 32 ssa_980 = imov ssa_978.y
>							vec1 32 ssa_981 = imov ssa_978.z
>							vec1 32 ssa_982 = imov ssa_978.w
>							/* succs: block_125 */
>						} else {
>							block block_121:
>							/* preds: block_119 */
>							vec1 32 ssa_983 = flt32 ssa_37, ssa_345
>							vec1 32 ssa_984 = ieq32 ssa_330, ssa_31
>							vec1 32 ssa_985 = ior ssa_984, ssa_983
>							/* succs: block_122 block_123 */
>							if ssa_985 {
>								block block_122:
>								/* preds: block_121 */
>								vec2 32 ssa_986 = txs ssa_1 (lod), 4 (texture), 4 (sampler), 
>								vec1 32 ssa_987 = i2f32 ssa_986.x
>								vec1 32 ssa_988 = i2f32 ssa_986.y
>								vec1 32 ssa_989 = frcp ssa_987
>								vec1 32 ssa_990 = frcp ssa_988
>								vec1 32 ssa_991 = fmul ssa_965, ssa_989
>								vec1 32 ssa_992 = fmul ssa_966, ssa_990
>								vec2 32 ssa_993 = vec2 ssa_991, ssa_992
>								vec4 32 ssa_994 = txl ssa_993 (coord), ssa_345 (lod), 4 (texture), 4 (sampler), 
>								vec1 32 ssa_995 = imov ssa_994.x
>								vec1 32 ssa_996 = imov ssa_994.y
>								vec1 32 ssa_997 = imov ssa_994.z
>								vec1 32 ssa_998 = imov ssa_994.w
>								/* succs: block_124 */
>							} else {
>								block block_123:
>								/* preds: block_121 */
>								vec1 32 ssa_999 = fadd ssa_965, ssa_63
>								vec1 32 ssa_1000 = fadd ssa_966, ssa_63
>								vec1 32 ssa_1001 = ffract ssa_999
>								vec1 32 ssa_1002 = ffract ssa_1000
>								vec1 32 ssa_1003 = ffloor ssa_999
>								vec1 32 ssa_1004 = ffloor ssa_1000
>								vec1 32 ssa_1005 = fmul ssa_1001, ssa_1001
>								vec1 32 ssa_1006 = fmul ssa_1005, ssa_1001
>								vec1 32 ssa_1007 = fadd ssa_35, -ssa_1001
>								vec1 32 ssa_1008 = fmul ssa_1007, ssa_1007
>								vec1 32 ssa_1009 = fmul ssa_1008, ssa_1007
>								vec1 32 ssa_1010 = fmul ssa_60, ssa_1005
>								vec1 32 ssa_1011 = ffma ssa_59, ssa_1006, -ssa_1010
>								vec1 32 ssa_1012 = fadd ssa_1011, ssa_36
>								vec1 32 ssa_1013 = ffma ssa_59, ssa_1009, ssa_36
>								vec1 32 ssa_1014 = ffma -ssa_60, ssa_1008, ssa_1013
>								vec1 32 ssa_1015 = load_const (0x3e2aaaab /* 0.166667 */)
>								vec1 32 ssa_1016 = fmul ssa_1002, ssa_1002
>								vec1 32 ssa_1017 = fmul ssa_1016, ssa_1002
>								vec1 32 ssa_1018 = fadd ssa_35, -ssa_1002
>								vec1 32 ssa_1019 = fmul ssa_1018, ssa_1018
>								vec1 32 ssa_1020 = fmul ssa_1019, ssa_1018
>								vec1 32 ssa_1021 = fmul ssa_60, ssa_1016
>								vec1 32 ssa_1022 = ffma ssa_59, ssa_1017, -ssa_1021
>								vec1 32 ssa_1023 = fadd ssa_1022, ssa_36
>								vec1 32 ssa_1024 = ffma ssa_59, ssa_1020, ssa_36
>								vec1 32 ssa_1025 = ffma -ssa_60, ssa_1019, ssa_1024
>								vec1 32 ssa_1026 = fadd ssa_1009, ssa_1012
>								vec1 32 ssa_1027 = fmul ssa_1015, ssa_1026
>								vec1 32 ssa_1028 = fadd ssa_1014, ssa_1006
>								vec1 32 ssa_1029 = fmul ssa_1015, ssa_1028
>								vec1 32 ssa_1030 = fadd ssa_1020, ssa_1023
>								vec1 32 ssa_1031 = fmul ssa_1015, ssa_1030
>								vec1 32 ssa_1032 = fadd ssa_1025, ssa_1017
>								vec1 32 ssa_1033 = fmul ssa_1015, ssa_1032
>								vec1 32 ssa_1034 = frcp ssa_1027
>								vec1 32 ssa_1035 = frcp ssa_1029
>								vec1 32 ssa_1036 = frcp ssa_1031
>								vec1 32 ssa_1037 = frcp ssa_1033
>								vec1 32 ssa_1038 = fmul ssa_1012, ssa_1015
>								vec1 32 ssa_1039 = fmul ssa_1006, ssa_1015
>								vec1 32 ssa_1040 = fmul ssa_1023, ssa_1015
>								vec1 32 ssa_1041 = fmul ssa_1017, ssa_1015
>								vec1 32 ssa_1042 = fadd ssa_1003, ssa_63
>								vec1 32 ssa_1043 = ffma ssa_1038, ssa_1034, ssa_1042
>								vec1 32 ssa_1044 = fadd ssa_1003, ssa_64
>								vec1 32 ssa_1045 = ffma ssa_1039, ssa_1035, ssa_1044
>								vec1 32 ssa_1046 = fadd ssa_1004, ssa_63
>								vec1 32 ssa_1047 = ffma ssa_1040, ssa_1036, ssa_1046
>								vec1 32 ssa_1048 = fadd ssa_1004, ssa_64
>								vec1 32 ssa_1049 = ffma ssa_1041, ssa_1037, ssa_1048
>								vec2 32 ssa_1050 = txs ssa_1 (lod), 4 (texture), 4 (sampler), 
>								vec1 32 ssa_1051 = i2f32 ssa_1050.x
>								vec1 32 ssa_1052 = i2f32 ssa_1050.y
>								vec1 32 ssa_1053 = frcp ssa_1051
>								vec1 32 ssa_1054 = frcp ssa_1052
>								vec1 32 ssa_1055 = fmul ssa_1043, ssa_1053
>								vec1 32 ssa_1056 = fmul ssa_1045, ssa_1054
>								vec1 32 ssa_1057 = fmul ssa_1047, ssa_1053
>								vec1 32 ssa_1058 = fmul ssa_1049, ssa_1054
>								vec1 32 ssa_1059 = fadd ssa_1026, ssa_1028
>								vec1 32 ssa_1060 = fmul ssa_1015, ssa_1059
>								vec1 32 ssa_1061 = frcp ssa_1060
>								vec1 32 ssa_1062 = fmul ssa_1029, ssa_1061
>								vec1 32 ssa_1063 = fadd ssa_1030, ssa_1032
>								vec1 32 ssa_1064 = fmul ssa_1015, ssa_1063
>								vec1 32 ssa_1065 = frcp ssa_1064
>								vec1 32 ssa_1066 = fmul ssa_1033, ssa_1065
>								vec2 32 ssa_1067 = vec2 ssa_1055, ssa_1057
>								vec4 32 ssa_1068 = txl ssa_1067 (coord), ssa_1 (lod), 4 (texture), 4 (sampler), 
>								vec2 32 ssa_1069 = vec2 ssa_1056, ssa_1057
>								vec4 32 ssa_1070 = txl ssa_1069 (coord), ssa_1 (lod), 4 (texture), 4 (sampler), 
>								vec1 32 ssa_1071 = flrp ssa_1068.x, ssa_1070.x, ssa_1062
>								vec1 32 ssa_1072 = flrp ssa_1068.y, ssa_1070.y, ssa_1062
>								vec1 32 ssa_1073 = flrp ssa_1068.z, ssa_1070.z, ssa_1062
>								vec1 32 ssa_1074 = flrp ssa_1068.w, ssa_1070.w, ssa_1062
>								vec2 32 ssa_1075 = vec2 ssa_1055, ssa_1058
>								vec4 32 ssa_1076 = txl ssa_1075 (coord), ssa_1 (lod), 4 (texture), 4 (sampler), 
>								vec2 32 ssa_1077 = vec2 ssa_1056, ssa_1058
>								vec4 32 ssa_1078 = txl ssa_1077 (coord), ssa_1 (lod), 4 (texture), 4 (sampler), 
>								vec1 32 ssa_1079 = flrp ssa_1076.x, ssa_1078.x, ssa_1062
>								vec1 32 ssa_1080 = flrp ssa_1076.y, ssa_1078.y, ssa_1062
>								vec1 32 ssa_1081 = flrp ssa_1076.z, ssa_1078.z, ssa_1062
>								vec1 32 ssa_1082 = flrp ssa_1076.w, ssa_1078.w, ssa_1062
>								vec1 32 ssa_1083 = flrp ssa_1071, ssa_1079, ssa_1066
>								vec1 32 ssa_1084 = flrp ssa_1072, ssa_1080, ssa_1066
>								vec1 32 ssa_1085 = flrp ssa_1073, ssa_1081, ssa_1066
>								vec1 32 ssa_1086 = flrp ssa_1074, ssa_1082, ssa_1066
>								/* succs: block_124 */
>							}
>							block block_124:
>							/* preds: block_122 block_123 */
>							vec1 32 ssa_1087 = phi block_122: ssa_995, block_123: ssa_1083
>							vec1 32 ssa_1088 = phi block_122: ssa_996, block_123: ssa_1084
>							vec1 32 ssa_1089 = phi block_122: ssa_997, block_123: ssa_1085
>							vec1 32 ssa_1090 = phi block_122: ssa_998, block_123: ssa_1086
>							/* succs: block_125 */
>						}
>						block block_125:
>						/* preds: block_120 block_124 */
>						vec1 32 ssa_1091 = phi block_120: ssa_979, block_124: ssa_1087
>						vec1 32 ssa_1092 = phi block_120: ssa_980, block_124: ssa_1088
>						vec1 32 ssa_1093 = phi block_120: ssa_981, block_124: ssa_1089
>						vec1 32 ssa_1094 = phi block_120: ssa_982, block_124: ssa_1090
>						/* succs: block_127 */
>					} else {
>						block block_126:
>						/* preds: block_118 */
>						/* succs: block_127 */
>					}
>					block block_127:
>					/* preds: block_125 block_126 */
>					vec1 32 ssa_1095 = phi block_126: ssa_35, block_125: ssa_1091
>					vec1 32 ssa_1096 = phi block_126: ssa_35, block_125: ssa_1092
>					vec1 32 ssa_1097 = phi block_126: ssa_35, block_125: ssa_1093
>					vec1 32 ssa_1098 = phi block_126: ssa_35, block_125: ssa_1094
>					/* succs: block_128 */
>				}
>				block block_128:
>				/* preds: block_117 block_127 */
>				vec1 32 ssa_1099 = phi block_117: ssa_959, block_127: ssa_1095
>				vec1 32 ssa_1100 = phi block_117: ssa_960, block_127: ssa_1096
>				vec1 32 ssa_1101 = phi block_117: ssa_961, block_127: ssa_1097
>				vec1 32 ssa_1102 = phi block_117: ssa_962, block_127: ssa_1098
>				vec1 32 ssa_1103 = iand ssa_92.y, ssa_66
>				vec1 32 ssa_1104 = ieq32 ssa_1103, ssa_1
>				/* succs: block_129 block_130 */
>				if ssa_1104 {
>					block block_129:
>					/* preds: block_128 */
>					vec1 32 ssa_1105 = fmul ssa_1099, ssa_1102
>					vec1 32 ssa_1106 = fmul ssa_1100, ssa_1102
>					vec1 32 ssa_1107 = fmul ssa_1101, ssa_1102
>					/* succs: block_131 */
>				} else {
>					block block_130:
>					/* preds: block_128 */
>					/* succs: block_131 */
>				}
>				block block_131:
>				/* preds: block_129 block_130 */
>				vec1 32 ssa_1108 = phi block_129: ssa_1105, block_130: ssa_1099
>				vec1 32 ssa_1109 = phi block_129: ssa_1106, block_130: ssa_1100
>				vec1 32 ssa_1110 = phi block_129: ssa_1107, block_130: ssa_1101
>				vec1 32 ssa_1111 = fmul ssa_315, ssa_1108
>				vec1 32 ssa_1112 = fmul ssa_316, ssa_1109
>				vec1 32 ssa_1113 = fmul ssa_317, ssa_1110
>				vec1 32 ssa_1114 = fmul ssa_314, ssa_1102
>				/* succs: block_133 */
>			} else {
>				block block_132:
>				/* preds: block_53 */
>				/* succs: block_133 */
>			}
>			block block_133:
>			/* preds: block_131 block_132 */
>			vec1 32 ssa_1115 = phi block_131: ssa_1111, block_132: ssa_315
>			vec1 32 ssa_1116 = phi block_131: ssa_1112, block_132: ssa_316
>			vec1 32 ssa_1117 = phi block_131: ssa_1113, block_132: ssa_317
>			vec1 32 ssa_1118 = phi block_131: ssa_1114, block_132: ssa_314
>			/* succs: block_135 */
>		} else {
>			block block_134:
>			/* preds: block_1 */
>			/* succs: block_135 */
>		}
>		block block_135:
>		/* preds: block_133 block_134 */
>		vec1 32 ssa_1119 = phi block_133: ssa_1115, block_134: ssa_21
>		vec1 32 ssa_1120 = phi block_133: ssa_1116, block_134: ssa_20
>		vec1 32 ssa_1121 = phi block_133: ssa_1117, block_134: ssa_19
>		vec1 32 ssa_1122 = phi block_133: ssa_1118, block_134: ssa_18
>		vec2 32 ssa_1123 = intrinsic load_input (ssa_1) (32, 0) /* base=32 */ /* component=0 */	/* fastuidraw_uint_varying1 */
>		vec1 32 ssa_1124 = ult32 ssa_1123.y, ssa_67
>		vec1 32 ssa_1125 = uge32 ssa_1123.y, ssa_31
>		vec1 32 ssa_1126 = iand ssa_1125, ssa_1124
>		/* succs: block_136 block_137 */
>		if ssa_1126 {
>			block block_136:
>			/* preds: block_135 */
>			vec4 32 ssa_1127 = intrinsic load_uniform (ssa_1) (0, 16) /* base=0 */ /* range=16 */	/* fastuidraw_painterStore */
>			vec4 32 ssa_1128 = load_const (0x3f000000 /* 0.500000 */, 0x3f000000 /* 0.500000 */, 0x00000000 /* 0.000000 */, 0x00000000 /* 0.000000 */)
>			vec1 32 ssa_1129 = fadd ssa_4.x, ssa_1128.x
>			vec1 32 ssa_1130 = fadd ssa_4.y, ssa_1128.y
>			vec1 32 ssa_1131 = ffma ssa_1130, ssa_1127.x, ssa_1127.y
>			vec1 32 ssa_1132 = f2i32 ssa_1129
>			vec1 32 ssa_1133 = f2i32 ssa_1131
>			vec1 32 ssa_1134 = iadd ssa_1132, ssa_96
>			vec1 32 ssa_1135 = iadd ssa_1133, ssa_97
>			vec2 32 ssa_1136 = vec2 ssa_1134, ssa_1135
>			vec4 32 ssa_1137 = txf ssa_1136 (coord), ssa_1 (lod), 12 (texture), 12 (sampler), 
>			vec1 32 ssa_1138 = imov ssa_1137.x
>			/* succs: block_395 */
>		} else {
>			block block_137:
>			/* preds: block_135 */
>			vec1 32 ssa_1139 = ult32 ssa_1123.y, ssa_29
>			vec1 32 ssa_1140 = uge32 ssa_1123.y, ssa_52
>			vec1 32 ssa_1141 = iand ssa_1140, ssa_1139
>			/* succs: block_138 block_139 */
>			if ssa_1141 {
>				block block_138:
>				/* preds: block_137 */
>				vec4 32 ssa_1142 = intrinsic load_uniform (ssa_1) (0, 16) /* base=0 */ /* range=16 */	/* fastuidraw_painterStore */
>				vec4 32 ssa_1143 = load_const (0x3f000000 /* 0.500000 */, 0x3f000000 /* 0.500000 */, 0x00000000 /* 0.000000 */, 0x00000000 /* 0.000000 */)
>				vec1 32 ssa_1144 = fadd ssa_4.x, ssa_1143.x
>				vec1 32 ssa_1145 = fadd ssa_4.y, ssa_1143.y
>				vec1 32 ssa_1146 = ffma ssa_1145, ssa_1142.x, ssa_1142.y
>				vec1 32 ssa_1147 = f2i32 ssa_1144
>				vec1 32 ssa_1148 = f2i32 ssa_1146
>				vec1 32 ssa_1149 = iadd ssa_1147, ssa_96
>				vec1 32 ssa_1150 = iadd ssa_1148, ssa_97
>				vec2 32 ssa_1151 = vec2 ssa_1149, ssa_1150
>				vec4 32 ssa_1152 = txf ssa_1151 (coord), ssa_1 (lod), 12 (texture), 12 (sampler), 
>				vec1 32 ssa_1153 = imov ssa_1152.x
>				/* succs: block_394 */
>			} else {
>				block block_139:
>				/* preds: block_137 */
>				vec1 32 ssa_1154 = ine32 ssa_1123.y, ssa_30
>				/* succs: block_140 block_392 */
>				if ssa_1154 {
>					block block_140:
>					/* preds: block_139 */
>					vec1 32 ssa_1155 = ine32 ssa_1123.y, ssa_68
>					/* succs: block_141 block_390 */
>					if ssa_1155 {
>						block block_141:
>						/* preds: block_140 */
>						vec1 32 ssa_1156 = ieq32 ssa_1123.y, ssa_50
>						/* succs: block_142 block_143 */
>						if ssa_1156 {
>							block block_142:
>							/* preds: block_141 */
>							vec4 32 ssa_1157 = intrinsic load_uniform (ssa_1) (0, 16) /* base=0 */ /* range=16 */	/* fastuidraw_painterStore */
>							vec4 32 ssa_1158 = load_const (0x3f000000 /* 0.500000 */, 0x3f000000 /* 0.500000 */, 0x00000000 /* 0.000000 */, 0x00000000 /* 0.000000 */)
>							vec1 32 ssa_1159 = fadd ssa_4.x, ssa_1158.x
>							vec1 32 ssa_1160 = fadd ssa_4.y, ssa_1158.y
>							vec1 32 ssa_1161 = ffma ssa_1160, ssa_1157.x, ssa_1157.y
>							vec1 32 ssa_1162 = f2i32 ssa_1159
>							vec1 32 ssa_1163 = f2i32 ssa_1161
>							vec1 32 ssa_1164 = iadd ssa_1162, ssa_96
>							vec1 32 ssa_1165 = iadd ssa_1163, ssa_97
>							vec2 32 ssa_1166 = vec2 ssa_1164, ssa_1165
>							vec4 32 ssa_1167 = txf ssa_1166 (coord), ssa_1 (lod), 12 (texture), 12 (sampler), 
>							vec1 32 ssa_1168 = imov ssa_1167.x
>							/* succs: block_389 */
>						} else {
>							block block_143:
>							/* preds: block_141 */
>							vec1 32 ssa_1169 = ieq32 ssa_1123.y, ssa_69
>							/* succs: block_144 block_169 */
>							if ssa_1169 {
>								block block_144:
>								/* preds: block_143 */
>								vec1 32 ssa_1170 = f2u32 ssa_5.w
>								vec1 32 ssa_1171 = f2u32 ssa_5.z
>								vec1 32 ssa_1172 = fadd ssa_5.x, ssa_37
>								vec1 32 ssa_1173 = fadd ssa_5.y, ssa_37
>								vec1 32 ssa_1174 = f2i32 ssa_1172
>								vec1 32 ssa_1175 = f2i32 ssa_1173
>								vec1 32 ssa_1176 = iadd ssa_1174, ssa_25
>								vec1 32 ssa_1177 = iadd ssa_1175, ssa_25
>								vec1 32 ssa_1178 = i2f32 ssa_1174
>								vec1 32 ssa_1179 = i2f32 ssa_1175
>								vec1 32 ssa_1180 = fadd ssa_1172, -ssa_1178
>								vec1 32 ssa_1181 = fadd ssa_1173, -ssa_1179
>								vec1 32 ssa_1182 = imin ssa_1176, ssa_1177
>								vec1 32 ssa_1183 = ige32 ssa_1182, ssa_1
>								/* succs: block_145 block_149 */
>								if ssa_1183 {
>									block block_145:
>									/* preds: block_144 */
>									vec1 32 ssa_1184 = uge32 ssa_1177, ssa_1171
>									vec1 32 ssa_1185 = uge32 ssa_1176, ssa_1170
>									vec1 32 ssa_1186 = ior ssa_1185, ssa_1184
>									/* succs: block_146 block_147 */
>									if ssa_1186 {
>										block block_146:
>										/* preds: block_145 */
>										/* succs: block_148 */
>									} else {
>										block block_147:
>										/* preds: block_145 */
>										vec4 32 ssa_1187 = intrinsic load_input (ssa_1) (31, 0) /* base=31 */ /* component=0 */	/* fastuidraw_uint_varying0 */
>										vec1 32 ssa_1188 = ushr ssa_1176, ssa_30
>										vec1 32 ssa_1189 = iadd ssa_1187.x, ssa_1188
>										vec1 32 ssa_1190 = ushr ssa_1177, ssa_30
>										vec1 32 ssa_1191 = iadd ssa_1170, ssa_30
>										vec1 32 ssa_1192 = ushr ssa_1191, ssa_30
>										vec1 32 ssa_1193 = imul ssa_1190, ssa_1192
>										vec1 32 ssa_1194 = iadd ssa_1189, ssa_1193
>										vec1 32 ssa_1195 = ishl ssa_1194, ssa_31
>										vec1 32 ssa_1196 = intrinsic load_ssbo (ssa_30, ssa_1195) (0, 4, 0) /* access=0 */ /* align_mul=4 */ /* align_offset=0 */
>										vec1 32 ssa_1197 = iand ssa_1176, ssa_30
>										vec1 32 ssa_1198 = ine32 ssa_1197, ssa_1
>										vec1 32 ssa_1199 = b32csel ssa_1198, ssa_70, ssa_1
>										vec1 32 ssa_1200 = iand ssa_1177, ssa_30
>										vec1 32 ssa_1201 = ine32 ssa_1200, ssa_1
>										vec1 32 ssa_1202 = b32csel ssa_1201, ssa_23, ssa_1
>										vec1 32 ssa_1203 = iadd ssa_1199, ssa_1202
>										vec1 32 ssa_1204 = iadd ssa_71, -ssa_1203
>										vec1 32 ssa_1205 = ishl ssa_1196, ssa_1204
>										vec1 32 ssa_1206 = extract_u8 ssa_1205, ssa_32
>										/* succs: block_148 */
>									}
>									block block_148:
>									/* preds: block_146 block_147 */
>									vec1 32 ssa_1207 = phi block_146: ssa_1, block_147: ssa_1206
>									/* succs: block_150 */
>								} else {
>									block block_149:
>									/* preds: block_144 */
>									/* succs: block_150 */
>								}
>								block block_150:
>								/* preds: block_148 block_149 */
>								vec1 32 ssa_1208 = phi block_149: ssa_1, block_148: ssa_1207
>								vec1 32 ssa_1209 = imin ssa_1176, ssa_1175
>								vec1 32 ssa_1210 = ige32 ssa_1209, ssa_1
>								/* succs: block_151 block_155 */
>								if ssa_1210 {
>									block block_151:
>									/* preds: block_150 */
>									vec1 32 ssa_1211 = uge32 ssa_1175, ssa_1171
>									vec1 32 ssa_1212 = uge32 ssa_1176, ssa_1170
>									vec1 32 ssa_1213 = ior ssa_1212, ssa_1211
>									/* succs: block_152 block_153 */
>									if ssa_1213 {
>										block block_152:
>										/* preds: block_151 */
>										/* succs: block_154 */
>									} else {
>										block block_153:
>										/* preds: block_151 */
>										vec4 32 ssa_1214 = intrinsic load_input (ssa_1) (31, 0) /* base=31 */ /* component=0 */	/* fastuidraw_uint_varying0 */
>										vec1 32 ssa_1215 = ushr ssa_1176, ssa_30
>										vec1 32 ssa_1216 = iadd ssa_1214.x, ssa_1215
>										vec1 32 ssa_1217 = ushr ssa_1175, ssa_30
>										vec1 32 ssa_1218 = iadd ssa_1170, ssa_30
>										vec1 32 ssa_1219 = ushr ssa_1218, ssa_30
>										vec1 32 ssa_1220 = imul ssa_1217, ssa_1219
>										vec1 32 ssa_1221 = iadd ssa_1216, ssa_1220
>										vec1 32 ssa_1222 = ishl ssa_1221, ssa_31
>										vec1 32 ssa_1223 = intrinsic load_ssbo (ssa_30, ssa_1222) (0, 4, 0) /* access=0 */ /* align_mul=4 */ /* align_offset=0 */
>										vec1 32 ssa_1224 = iand ssa_1176, ssa_30
>										vec1 32 ssa_1225 = ine32 ssa_1224, ssa_1
>										vec1 32 ssa_1226 = b32csel ssa_1225, ssa_70, ssa_1
>										vec1 32 ssa_1227 = iand ssa_1175, ssa_30
>										vec1 32 ssa_1228 = ine32 ssa_1227, ssa_1
>										vec1 32 ssa_1229 = b32csel ssa_1228, ssa_23, ssa_1
>										vec1 32 ssa_1230 = iadd ssa_1226, ssa_1229
>										vec1 32 ssa_1231 = iadd ssa_71, -ssa_1230
>										vec1 32 ssa_1232 = ishl ssa_1223, ssa_1231
>										vec1 32 ssa_1233 = extract_u8 ssa_1232, ssa_32
>										/* succs: block_154 */
>									}
>									block block_154:
>									/* preds: block_152 block_153 */
>									vec1 32 ssa_1234 = phi block_152: ssa_1, block_153: ssa_1233
>									/* succs: block_156 */
>								} else {
>									block block_155:
>									/* preds: block_150 */
>									/* succs: block_156 */
>								}
>								block block_156:
>								/* preds: block_154 block_155 */
>								vec1 32 ssa_1235 = phi block_155: ssa_1, block_154: ssa_1234
>								vec1 32 ssa_1236 = imin ssa_1174, ssa_1177
>								vec1 32 ssa_1237 = ige32 ssa_1236, ssa_1
>								/* succs: block_157 block_161 */
>								if ssa_1237 {
>									block block_157:
>									/* preds: block_156 */
>									vec1 32 ssa_1238 = uge32 ssa_1177, ssa_1171
>									vec1 32 ssa_1239 = uge32 ssa_1174, ssa_1170
>									vec1 32 ssa_1240 = ior ssa_1239, ssa_1238
>									/* succs: block_158 block_159 */
>									if ssa_1240 {
>										block block_158:
>										/* preds: block_157 */
>										/* succs: block_160 */
>									} else {
>										block block_159:
>										/* preds: block_157 */
>										vec4 32 ssa_1241 = intrinsic load_input (ssa_1) (31, 0) /* base=31 */ /* component=0 */	/* fastuidraw_uint_varying0 */
>										vec1 32 ssa_1242 = ushr ssa_1174, ssa_30
>										vec1 32 ssa_1243 = iadd ssa_1241.x, ssa_1242
>										vec1 32 ssa_1244 = ushr ssa_1177, ssa_30
>										vec1 32 ssa_1245 = iadd ssa_1170, ssa_30
>										vec1 32 ssa_1246 = ushr ssa_1245, ssa_30
>										vec1 32 ssa_1247 = imul ssa_1244, ssa_1246
>										vec1 32 ssa_1248 = iadd ssa_1243, ssa_1247
>										vec1 32 ssa_1249 = ishl ssa_1248, ssa_31
>										vec1 32 ssa_1250 = intrinsic load_ssbo (ssa_30, ssa_1249) (0, 4, 0) /* access=0 */ /* align_mul=4 */ /* align_offset=0 */
>										vec1 32 ssa_1251 = iand ssa_1174, ssa_30
>										vec1 32 ssa_1252 = ine32 ssa_1251, ssa_1
>										vec1 32 ssa_1253 = b32csel ssa_1252, ssa_70, ssa_1
>										vec1 32 ssa_1254 = iand ssa_1177, ssa_30
>										vec1 32 ssa_1255 = ine32 ssa_1254, ssa_1
>										vec1 32 ssa_1256 = b32csel ssa_1255, ssa_23, ssa_1
>										vec1 32 ssa_1257 = iadd ssa_1253, ssa_1256
>										vec1 32 ssa_1258 = iadd ssa_71, -ssa_1257
>										vec1 32 ssa_1259 = ishl ssa_1250, ssa_1258
>										vec1 32 ssa_1260 = extract_u8 ssa_1259, ssa_32
>										/* succs: block_160 */
>									}
>									block block_160:
>									/* preds: block_158 block_159 */
>									vec1 32 ssa_1261 = phi block_158: ssa_1, block_159: ssa_1260
>									/* succs: block_162 */
>								} else {
>									block block_161:
>									/* preds: block_156 */
>									/* succs: block_162 */
>								}
>								block block_162:
>								/* preds: block_160 block_161 */
>								vec1 32 ssa_1262 = phi block_161: ssa_1, block_160: ssa_1261
>								vec1 32 ssa_1263 = imin ssa_1174, ssa_1175
>								vec1 32 ssa_1264 = ige32 ssa_1263, ssa_1
>								/* succs: block_163 block_167 */
>								if ssa_1264 {
>									block block_163:
>									/* preds: block_162 */
>									vec1 32 ssa_1265 = uge32 ssa_1175, ssa_1171
>									vec1 32 ssa_1266 = uge32 ssa_1174, ssa_1170
>									vec1 32 ssa_1267 = ior ssa_1266, ssa_1265
>									/* succs: block_164 block_165 */
>									if ssa_1267 {
>										block block_164:
>										/* preds: block_163 */
>										/* succs: block_166 */
>									} else {
>										block block_165:
>										/* preds: block_163 */
>										vec4 32 ssa_1268 = intrinsic load_input (ssa_1) (31, 0) /* base=31 */ /* component=0 */	/* fastuidraw_uint_varying0 */
>										vec1 32 ssa_1269 = ushr ssa_1174, ssa_30
>										vec1 32 ssa_1270 = iadd ssa_1268.x, ssa_1269
>										vec1 32 ssa_1271 = ushr ssa_1175, ssa_30
>										vec1 32 ssa_1272 = iadd ssa_1170, ssa_30
>										vec1 32 ssa_1273 = ushr ssa_1272, ssa_30
>										vec1 32 ssa_1274 = imul ssa_1271, ssa_1273
>										vec1 32 ssa_1275 = iadd ssa_1270, ssa_1274
>										vec1 32 ssa_1276 = ishl ssa_1275, ssa_31
>										vec1 32 ssa_1277 = intrinsic load_ssbo (ssa_30, ssa_1276) (0, 4, 0) /* access=0 */ /* align_mul=4 */ /* align_offset=0 */
>										vec1 32 ssa_1278 = iand ssa_1174, ssa_30
>										vec1 32 ssa_1279 = ine32 ssa_1278, ssa_1
>										vec1 32 ssa_1280 = b32csel ssa_1279, ssa_70, ssa_1
>										vec1 32 ssa_1281 = iand ssa_1175, ssa_30
>										vec1 32 ssa_1282 = ine32 ssa_1281, ssa_1
>										vec1 32 ssa_1283 = b32csel ssa_1282, ssa_23, ssa_1
>										vec1 32 ssa_1284 = iadd ssa_1280, ssa_1283
>										vec1 32 ssa_1285 = iadd ssa_71, -ssa_1284
>										vec1 32 ssa_1286 = ishl ssa_1277, ssa_1285
>										vec1 32 ssa_1287 = extract_u8 ssa_1286, ssa_32
>										/* succs: block_166 */
>									}
>									block block_166:
>									/* preds: block_164 block_165 */
>									vec1 32 ssa_1288 = phi block_164: ssa_1, block_165: ssa_1287
>									/* succs: block_168 */
>								} else {
>									block block_167:
>									/* preds: block_162 */
>									/* succs: block_168 */
>								}
>								block block_168:
>								/* preds: block_166 block_167 */
>								vec1 32 ssa_1289 = phi block_167: ssa_1, block_166: ssa_1288
>								vec1 32 ssa_1290 = u2f32 ssa_1208
>								vec1 32 ssa_1291 = u2f32 ssa_1235
>								vec1 32 ssa_1292 = flrp ssa_1290, ssa_1291, ssa_1181
>								vec1 32 ssa_1293 = u2f32 ssa_1262
>								vec1 32 ssa_1294 = u2f32 ssa_1289
>								vec1 32 ssa_1295 = flrp ssa_1293, ssa_1294, ssa_1181
>								vec1 32 ssa_1296 = flrp ssa_1292, ssa_1295, ssa_1180
>								vec1 32 ssa_1297 = load_const (0x3b808081 /* 0.003922 */)
>								vec1 32 ssa_1298 = fmul ssa_1296, ssa_1297
>								/* succs: block_388 */
>							} else {
>								block block_169:
>								/* preds: block_143 */
>								vec1 32 ssa_1299 = ieq32 ssa_1123.y, ssa_34
>								/* succs: block_170 block_195 */
>								if ssa_1299 {
>									block block_170:
>									/* preds: block_169 */
>									vec1 32 ssa_1300 = f2u32 ssa_5.w
>									vec1 32 ssa_1301 = f2u32 ssa_5.z
>									vec1 32 ssa_1302 = fadd ssa_5.x, ssa_37
>									vec1 32 ssa_1303 = fadd ssa_5.y, ssa_37
>									vec1 32 ssa_1304 = f2i32 ssa_1302
>									vec1 32 ssa_1305 = f2i32 ssa_1303
>									vec1 32 ssa_1306 = iadd ssa_1304, ssa_25
>									vec1 32 ssa_1307 = iadd ssa_1305, ssa_25
>									vec1 32 ssa_1308 = i2f32 ssa_1304
>									vec1 32 ssa_1309 = i2f32 ssa_1305
>									vec1 32 ssa_1310 = fadd ssa_1302, -ssa_1308
>									vec1 32 ssa_1311 = fadd ssa_1303, -ssa_1309
>									vec1 32 ssa_1312 = imin ssa_1306, ssa_1307
>									vec1 32 ssa_1313 = ige32 ssa_1312, ssa_1
>									/* succs: block_171 block_175 */
>									if ssa_1313 {
>										block block_171:
>										/* preds: block_170 */
>										vec1 32 ssa_1314 = uge32 ssa_1307, ssa_1301
>										vec1 32 ssa_1315 = uge32 ssa_1306, ssa_1300
>										vec1 32 ssa_1316 = ior ssa_1315, ssa_1314
>										/* succs: block_172 block_173 */
>										if ssa_1316 {
>											block block_172:
>											/* preds: block_171 */
>											/* succs: block_174 */
>										} else {
>											block block_173:
>											/* preds: block_171 */
>											vec4 32 ssa_1317 = intrinsic load_input (ssa_1) (31, 0) /* base=31 */ /* component=0 */	/* fastuidraw_uint_varying0 */
>											vec1 32 ssa_1318 = ushr ssa_1306, ssa_30
>											vec1 32 ssa_1319 = iadd ssa_1317.x, ssa_1318
>											vec1 32 ssa_1320 = ushr ssa_1307, ssa_30
>											vec1 32 ssa_1321 = iadd ssa_1300, ssa_30
>											vec1 32 ssa_1322 = ushr ssa_1321, ssa_30
>											vec1 32 ssa_1323 = imul ssa_1320, ssa_1322
>											vec1 32 ssa_1324 = iadd ssa_1319, ssa_1323
>											vec1 32 ssa_1325 = ishl ssa_1324, ssa_31
>											vec1 32 ssa_1326 = intrinsic load_ssbo (ssa_30, ssa_1325) (0, 4, 0) /* access=0 */ /* align_mul=4 */ /* align_offset=0 */
>											vec1 32 ssa_1327 = iand ssa_1306, ssa_30
>											vec1 32 ssa_1328 = ine32 ssa_1327, ssa_1
>											vec1 32 ssa_1329 = b32csel ssa_1328, ssa_70, ssa_1
>											vec1 32 ssa_1330 = iand ssa_1307, ssa_30
>											vec1 32 ssa_1331 = ine32 ssa_1330, ssa_1
>											vec1 32 ssa_1332 = b32csel ssa_1331, ssa_23, ssa_1
>											vec1 32 ssa_1333 = iadd ssa_1329, ssa_1332
>											vec1 32 ssa_1334 = iadd ssa_71, -ssa_1333
>											vec1 32 ssa_1335 = ishl ssa_1326, ssa_1334
>											vec1 32 ssa_1336 = extract_u8 ssa_1335, ssa_32
>											/* succs: block_174 */
>										}
>										block block_174:
>										/* preds: block_172 block_173 */
>										vec1 32 ssa_1337 = phi block_172: ssa_1, block_173: ssa_1336
>										/* succs: block_176 */
>									} else {
>										block block_175:
>										/* preds: block_170 */
>										/* succs: block_176 */
>									}
>									block block_176:
>									/* preds: block_174 block_175 */
>									vec1 32 ssa_1338 = phi block_175: ssa_1, block_174: ssa_1337
>									vec1 32 ssa_1339 = imin ssa_1306, ssa_1305
>									vec1 32 ssa_1340 = ige32 ssa_1339, ssa_1
>									/* succs: block_177 block_181 */
>									if ssa_1340 {
>										block block_177:
>										/* preds: block_176 */
>										vec1 32 ssa_1341 = uge32 ssa_1305, ssa_1301
>										vec1 32 ssa_1342 = uge32 ssa_1306, ssa_1300
>										vec1 32 ssa_1343 = ior ssa_1342, ssa_1341
>										/* succs: block_178 block_179 */
>										if ssa_1343 {
>											block block_178:
>											/* preds: block_177 */
>											/* succs: block_180 */
>										} else {
>											block block_179:
>											/* preds: block_177 */
>											vec4 32 ssa_1344 = intrinsic load_input (ssa_1) (31, 0) /* base=31 */ /* component=0 */	/* fastuidraw_uint_varying0 */
>											vec1 32 ssa_1345 = ushr ssa_1306, ssa_30
>											vec1 32 ssa_1346 = iadd ssa_1344.x, ssa_1345
>											vec1 32 ssa_1347 = ushr ssa_1305, ssa_30
>											vec1 32 ssa_1348 = iadd ssa_1300, ssa_30
>											vec1 32 ssa_1349 = ushr ssa_1348, ssa_30
>											vec1 32 ssa_1350 = imul ssa_1347, ssa_1349
>											vec1 32 ssa_1351 = iadd ssa_1346, ssa_1350
>											vec1 32 ssa_1352 = ishl ssa_1351, ssa_31
>											vec1 32 ssa_1353 = intrinsic load_ssbo (ssa_30, ssa_1352) (0, 4, 0) /* access=0 */ /* align_mul=4 */ /* align_offset=0 */
>											vec1 32 ssa_1354 = iand ssa_1306, ssa_30
>											vec1 32 ssa_1355 = ine32 ssa_1354, ssa_1
>											vec1 32 ssa_1356 = b32csel ssa_1355, ssa_70, ssa_1
>											vec1 32 ssa_1357 = iand ssa_1305, ssa_30
>											vec1 32 ssa_1358 = ine32 ssa_1357, ssa_1
>											vec1 32 ssa_1359 = b32csel ssa_1358, ssa_23, ssa_1
>											vec1 32 ssa_1360 = iadd ssa_1356, ssa_1359
>											vec1 32 ssa_1361 = iadd ssa_71, -ssa_1360
>											vec1 32 ssa_1362 = ishl ssa_1353, ssa_1361
>											vec1 32 ssa_1363 = extract_u8 ssa_1362, ssa_32
>											/* succs: block_180 */
>										}
>										block block_180:
>										/* preds: block_178 block_179 */
>										vec1 32 ssa_1364 = phi block_178: ssa_1, block_179: ssa_1363
>										/* succs: block_182 */
>									} else {
>										block block_181:
>										/* preds: block_176 */
>										/* succs: block_182 */
>									}
>									block block_182:
>									/* preds: block_180 block_181 */
>									vec1 32 ssa_1365 = phi block_181: ssa_1, block_180: ssa_1364
>									vec1 32 ssa_1366 = imin ssa_1304, ssa_1307
>									vec1 32 ssa_1367 = ige32 ssa_1366, ssa_1
>									/* succs: block_183 block_187 */
>									if ssa_1367 {
>										block block_183:
>										/* preds: block_182 */
>										vec1 32 ssa_1368 = uge32 ssa_1307, ssa_1301
>										vec1 32 ssa_1369 = uge32 ssa_1304, ssa_1300
>										vec1 32 ssa_1370 = ior ssa_1369, ssa_1368
>										/* succs: block_184 block_185 */
>										if ssa_1370 {
>											block block_184:
>											/* preds: block_183 */
>											/* succs: block_186 */
>										} else {
>											block block_185:
>											/* preds: block_183 */
>											vec4 32 ssa_1371 = intrinsic load_input (ssa_1) (31, 0) /* base=31 */ /* component=0 */	/* fastuidraw_uint_varying0 */
>											vec1 32 ssa_1372 = ushr ssa_1304, ssa_30
>											vec1 32 ssa_1373 = iadd ssa_1371.x, ssa_1372
>											vec1 32 ssa_1374 = ushr ssa_1307, ssa_30
>											vec1 32 ssa_1375 = iadd ssa_1300, ssa_30
>											vec1 32 ssa_1376 = ushr ssa_1375, ssa_30
>											vec1 32 ssa_1377 = imul ssa_1374, ssa_1376
>											vec1 32 ssa_1378 = iadd ssa_1373, ssa_1377
>											vec1 32 ssa_1379 = ishl ssa_1378, ssa_31
>											vec1 32 ssa_1380 = intrinsic load_ssbo (ssa_30, ssa_1379) (0, 4, 0) /* access=0 */ /* align_mul=4 */ /* align_offset=0 */
>											vec1 32 ssa_1381 = iand ssa_1304, ssa_30
>											vec1 32 ssa_1382 = ine32 ssa_1381, ssa_1
>											vec1 32 ssa_1383 = b32csel ssa_1382, ssa_70, ssa_1
>											vec1 32 ssa_1384 = iand ssa_1307, ssa_30
>											vec1 32 ssa_1385 = ine32 ssa_1384, ssa_1
>											vec1 32 ssa_1386 = b32csel ssa_1385, ssa_23, ssa_1
>											vec1 32 ssa_1387 = iadd ssa_1383, ssa_1386
>											vec1 32 ssa_1388 = iadd ssa_71, -ssa_1387
>											vec1 32 ssa_1389 = ishl ssa_1380, ssa_1388
>											vec1 32 ssa_1390 = extract_u8 ssa_1389, ssa_32
>											/* succs: block_186 */
>										}
>										block block_186:
>										/* preds: block_184 block_185 */
>										vec1 32 ssa_1391 = phi block_184: ssa_1, block_185: ssa_1390
>										/* succs: block_188 */
>									} else {
>										block block_187:
>										/* preds: block_182 */
>										/* succs: block_188 */
>									}
>									block block_188:
>									/* preds: block_186 block_187 */
>									vec1 32 ssa_1392 = phi block_187: ssa_1, block_186: ssa_1391
>									vec1 32 ssa_1393 = imin ssa_1304, ssa_1305
>									vec1 32 ssa_1394 = ige32 ssa_1393, ssa_1
>									/* succs: block_189 block_193 */
>									if ssa_1394 {
>										block block_189:
>										/* preds: block_188 */
>										vec1 32 ssa_1395 = uge32 ssa_1305, ssa_1301
>										vec1 32 ssa_1396 = uge32 ssa_1304, ssa_1300
>										vec1 32 ssa_1397 = ior ssa_1396, ssa_1395
>										/* succs: block_190 block_191 */
>										if ssa_1397 {
>											block block_190:
>											/* preds: block_189 */
>											/* succs: block_192 */
>										} else {
>											block block_191:
>											/* preds: block_189 */
>											vec4 32 ssa_1398 = intrinsic load_input (ssa_1) (31, 0) /* base=31 */ /* component=0 */	/* fastuidraw_uint_varying0 */
>											vec1 32 ssa_1399 = ushr ssa_1304, ssa_30
>											vec1 32 ssa_1400 = iadd ssa_1398.x, ssa_1399
>											vec1 32 ssa_1401 = ushr ssa_1305, ssa_30
>											vec1 32 ssa_1402 = iadd ssa_1300, ssa_30
>											vec1 32 ssa_1403 = ushr ssa_1402, ssa_30
>											vec1 32 ssa_1404 = imul ssa_1401, ssa_1403
>											vec1 32 ssa_1405 = iadd ssa_1400, ssa_1404
>											vec1 32 ssa_1406 = ishl ssa_1405, ssa_31
>											vec1 32 ssa_1407 = intrinsic load_ssbo (ssa_30, ssa_1406) (0, 4, 0) /* access=0 */ /* align_mul=4 */ /* align_offset=0 */
>											vec1 32 ssa_1408 = iand ssa_1304, ssa_30
>											vec1 32 ssa_1409 = ine32 ssa_1408, ssa_1
>											vec1 32 ssa_1410 = b32csel ssa_1409, ssa_70, ssa_1
>											vec1 32 ssa_1411 = iand ssa_1305, ssa_30
>											vec1 32 ssa_1412 = ine32 ssa_1411, ssa_1
>											vec1 32 ssa_1413 = b32csel ssa_1412, ssa_23, ssa_1
>											vec1 32 ssa_1414 = iadd ssa_1410, ssa_1413
>											vec1 32 ssa_1415 = iadd ssa_71, -ssa_1414
>											vec1 32 ssa_1416 = ishl ssa_1407, ssa_1415
>											vec1 32 ssa_1417 = extract_u8 ssa_1416, ssa_32
>											/* succs: block_192 */
>										}
>										block block_192:
>										/* preds: block_190 block_191 */
>										vec1 32 ssa_1418 = phi block_190: ssa_1, block_191: ssa_1417
>										/* succs: block_194 */
>									} else {
>										block block_193:
>										/* preds: block_188 */
>										/* succs: block_194 */
>									}
>									block block_194:
>									/* preds: block_192 block_193 */
>									vec1 32 ssa_1419 = phi block_193: ssa_1, block_192: ssa_1418
>									vec1 32 ssa_1420 = u2f32 ssa_1338
>									vec1 32 ssa_1421 = u2f32 ssa_1365
>									vec1 32 ssa_1422 = flrp ssa_1420, ssa_1421, ssa_1311
>									vec1 32 ssa_1423 = u2f32 ssa_1392
>									vec1 32 ssa_1424 = u2f32 ssa_1419
>									vec1 32 ssa_1425 = flrp ssa_1423, ssa_1424, ssa_1311
>									vec1 32 ssa_1426 = flrp ssa_1422, ssa_1425, ssa_1310
>									vec1 32 ssa_1427 = load_const (0x3c008081 /* 0.007843 */)
>									vec1 32 ssa_1428 = ffma ssa_1427, ssa_1426, ssa_51
>									vec1 32 ssa_1429 = fddx ssa_1428
>									vec4 32 ssa_1430 = intrinsic load_uniform (ssa_1) (0, 16) /* base=0 */ /* range=16 */	/* fastuidraw_painterStore */
>									vec1 32 ssa_1431 = fmul ssa_1428, ssa_1430.x
>									vec1 32 ssa_1432 = fddy ssa_1431
>									vec1 32 ssa_1433 = fmul ssa_1432, ssa_1432
>									vec1 32 ssa_1434 = ffma ssa_1429, ssa_1429, ssa_1433
>									vec1 32 ssa_1435 = frsq ssa_1434
>									vec1 32 ssa_1436 = ffma.sat ssa_1428, ssa_1435, ssa_37
>									/* succs: block_387 */
>								} else {
>									block block_195:
>									/* preds: block_169 */
>									vec1 32 ssa_1437 = ieq32 ssa_1123.y, ssa_72
>									/* succs: block_196 block_315 */
>									if ssa_1437 {
>										block block_196:
>										/* preds: block_195 */
>										vec4 32 ssa_1438 = intrinsic load_input (ssa_1) (31, 0) /* base=31 */ /* component=0 */	/* fastuidraw_uint_varying0 */
>										vec1 32 ssa_1439 = iand ssa_1438.x, ssa_73
>										vec1 32 ssa_1440 = fddx ssa_5.x
>										vec1 32 ssa_1441 = fddx ssa_5.y
>										vec4 32 ssa_1442 = intrinsic load_uniform (ssa_1) (0, 16) /* base=0 */ /* range=16 */	/* fastuidraw_painterStore */
>										vec1 32 ssa_1443 = fmul ssa_5.x, ssa_1442.x
>										vec1 32 ssa_1444 = fddy ssa_1443
>										vec1 32 ssa_1445 = fmul ssa_5.y, ssa_1442.x
>										vec1 32 ssa_1446 = fddy ssa_1445
>										vec1 32 ssa_1447 = iand ssa_1438.x, ssa_26
>										vec1 32 ssa_1448 = ine32 ssa_1447, ssa_1
>										vec1 32 ssa_1449 = ishl ssa_1439, ssa_31
>										vec1 32 ssa_1450 = intrinsic load_ssbo (ssa_30, ssa_1449) (0, 4, 0) /* access=0 */ /* align_mul=4 */ /* align_offset=0 */
>										vec1 32 ssa_1451 = load_const (0x45000000 /* 2048.000000 */)
>										vec1 32 ssa_1452 = load_const (0xc5000000 /* -2048.000000 */)
>										/* succs: block_197 */
>										loop {
>											block block_197:
>											/* preds: block_196 block_203 */
>											vec1 32 ssa_1453 = phi block_196: ssa_1450, block_203: ssa_1485
>											vec1 32 ssa_1454 = phi block_196: ssa_1439, block_203: ssa_1483
>											vec1 32 ssa_1455 = phi block_196: ssa_1451, block_203: ssa_1475
>											vec1 32 ssa_1456 = phi block_196: ssa_1451, block_203: ssa_1476
>											vec1 32 ssa_1457 = phi block_196: ssa_1452, block_203: ssa_1477
>											vec1 32 ssa_1458 = phi block_196: ssa_1452, block_203: ssa_1478
>											vec1 32 ssa_1459 = iand ssa_1453, ssa_30
>											vec1 32 ssa_1460 = ieq32 ssa_1459, ssa_1
>											/* succs: block_198 block_199 */
>											if ssa_1460 {
>												block block_198:
>												/* preds: block_197 */
>												break
>												/* succs: block_204 */
>											} else {
>												block block_199:
>												/* preds: block_197 */
>												/* succs: block_200 */
>											}
>											block block_200:
>											/* preds: block_199 */
>											vec1 32 ssa_1461 = ishl ssa_1453, ssa_28
>											vec1 32 ssa_1462 = ushr ssa_1461, ssa_74
>											vec1 32 ssa_1463 = ieq32 ssa_1462, ssa_1
>											/* succs: block_201 block_202 */
>											if ssa_1463 {
>												block block_201:
>												/* preds: block_200 */
>												vec1 32 ssa_1464 = fadd ssa_1457, ssa_1455
>												vec1 32 ssa_1465 = fmul ssa_37, ssa_1464
>												vec1 32 ssa_1466 = flt32 ssa_1465, ssa_5.x
>												vec1 32 ssa_1467 = b32csel ssa_1466, ssa_1465, ssa_1457
>												vec1 32 ssa_1468 = b32csel ssa_1466, ssa_1455, ssa_1465
>												/* succs: block_203 */
>											} else {
>												block block_202:
>												/* preds: block_200 */
>												vec1 32 ssa_1469 = fadd ssa_1458, ssa_1456
>												vec1 32 ssa_1470 = fmul ssa_37, ssa_1469
>												vec1 32 ssa_1471 = flt32 ssa_1470, ssa_5.y
>												vec1 32 ssa_1472 = b32csel ssa_1471, ssa_1470, ssa_1458
>												vec1 32 ssa_1473 = b32csel ssa_1471, ssa_1456, ssa_1470
>												/* succs: block_203 */
>											}
>											block block_203:
>											/* preds: block_201 block_202 */
>											vec1 32 ssa_1474 = phi block_201: ssa_1466, block_202: ssa_1471
>											vec1 32 ssa_1475 = phi block_201: ssa_1468, block_202: ssa_1455
>											vec1 32 ssa_1476 = phi block_201: ssa_1456, block_202: ssa_1473
>											vec1 32 ssa_1477 = phi block_201: ssa_1467, block_202: ssa_1457
>											vec1 32 ssa_1478 = phi block_201: ssa_1458, block_202: ssa_1472
>											vec1 32 ssa_1479 = b32csel ssa_1474, ssa_75, ssa_31
>											vec1 32 ssa_1480 = iadd ssa_75, -ssa_1479
>											vec1 32 ssa_1481 = ishl ssa_1453, ssa_1480
>											vec1 32 ssa_1482 = ushr ssa_1481, ssa_75
>											vec1 32 ssa_1483 = iadd ssa_1482, ssa_1439
>											vec1 32 ssa_1484 = ishl ssa_1483, ssa_31
>											vec1 32 ssa_1485 = intrinsic load_ssbo (ssa_30, ssa_1484) (0, 4, 0) /* access=0 */ /* align_mul=4 */ /* align_offset=0 */
>											/* succs: block_197 */
>										}
>										block block_204:
>										/* preds: block_198 */
>										vec1 32 ssa_1486 = ishl ssa_1453, ssa_76
>										vec1 32 ssa_1487 = extract_u16 ssa_1486, ssa_30
>										vec1 32 ssa_1488 = ushr ssa_1453, ssa_75
>										vec1 32 ssa_1489 = iadd ssa_1454, ssa_30
>										vec1 32 ssa_1490 = ishl ssa_1489, ssa_31
>										vec1 32 ssa_1491 = intrinsic load_ssbo (ssa_30, ssa_1490) (0, 4, 0) /* access=0 */ /* align_mul=4 */ /* align_offset=0 */
>										vec1 32 ssa_1492 = extract_u8 ssa_1491, ssa_31
>										vec1 32 ssa_1493 = extract_u8 ssa_1491, ssa_32
>										vec1 32 ssa_1494 = u2f32 ssa_1492
>										vec1 32 ssa_1495 = u2f32 ssa_1493
>										vec1 32 ssa_1496 = load_const (0x3b800000 /* 0.003906 */)
>										vec1 32 ssa_1497 = fmul ssa_1494, ssa_1496
>										vec1 32 ssa_1498 = fmul ssa_1495, ssa_1496
>										vec1 32 ssa_1499 = extract_u16 ssa_1491, ssa_1
>										vec1 32 ssa_1500 = iadd ssa_1499, ssa_24
>										vec1 32 ssa_1501 = flrp ssa_1457, ssa_1455, ssa_1497
>										vec1 32 ssa_1502 = flrp ssa_1458, ssa_1456, ssa_1498
>										vec1 32 ssa_1503 = fadd ssa_1501, -ssa_5.x
>										vec1 32 ssa_1504 = fadd ssa_1502, -ssa_5.y
>										vec1 32 ssa_1505 = fmul ssa_1446, ssa_1446
>										vec1 32 ssa_1506 = ffma ssa_1441, ssa_1441, ssa_1505
>										vec1 32 ssa_1507 = fmul ssa_1444, ssa_1446
>										vec1 32 ssa_1508 = ffma ssa_1440, ssa_1441, ssa_1507
>										vec1 32 ssa_1509 = fmul ssa_1444, ssa_1444
>										vec1 32 ssa_1510 = ffma ssa_1440, ssa_1440, ssa_1509
>										vec1 32 ssa_1511 = fmul ssa_1508, ssa_1504
>										vec1 32 ssa_1512 = ffma -ssa_1506, ssa_1503, ssa_1511
>										vec1 32 ssa_1513 = fmul ssa_1510, ssa_1504
>										vec1 32 ssa_1514 = ffma ssa_1508, ssa_1503, -ssa_1513
>										vec1 32 ssa_1515 = fmul ssa_1514, ssa_1441
>										vec1 32 ssa_1516 = ffma ssa_1512, ssa_1440, ssa_1515
>										vec1 32 ssa_1517 = fmul ssa_1514, ssa_1446
>										vec1 32 ssa_1518 = ffma ssa_1512, ssa_1444, ssa_1517
>										vec1 32 ssa_1519 = fadd abs(ssa_1516), abs(ssa_1518)
>										vec1 32 ssa_1520 = fmul ssa_1503, ssa_1441
>										vec1 32 ssa_1521 = ffma -ssa_1504, ssa_1440, ssa_1520
>										vec1 32 ssa_1522 = fmul ssa_1503, ssa_1446
>										vec1 32 ssa_1523 = ffma -ssa_1504, ssa_1444, ssa_1522
>										vec1 32 ssa_1524 = fadd abs(ssa_1521), abs(ssa_1523)
>										vec1 32 ssa_1525 = fmax ssa_1519, ssa_78
>										vec1 32 ssa_1526 = fmax ssa_1524, ssa_78
>										vec1 32 ssa_1527 = frcp ssa_1525
>										vec1 32 ssa_1528 = fmul ssa_1512, ssa_1527
>										vec1 32 ssa_1529 = fmul ssa_1514, ssa_1527
>										vec1 32 ssa_1530 = frcp ssa_1526
>										vec1 32 ssa_1531 = fmul ssa_1504, ssa_1530
>										vec1 32 ssa_1532 = fmov -ssa_1531
>										vec1 32 ssa_1533 = fmul ssa_1503, ssa_1530
>										vec1 32 ssa_1534 = fmul ssa_1529, ssa_1504
>										vec1 32 ssa_1535 = ffma ssa_1528, ssa_1503, ssa_1534
>										vec1 32 ssa_1536 = fmov -ssa_1528
>										vec1 32 ssa_1537 = fmov -ssa_1529
>										vec1 32 ssa_1538 = fmov -ssa_1535
>										vec1 32 ssa_1539 = flt32 ssa_1535, ssa_1
>										vec1 32 ssa_1540 = b32csel ssa_1539, ssa_1538, ssa_1535
>										vec1 32 ssa_1541 = b32csel ssa_1539, ssa_1536, ssa_1528
>										vec1 32 ssa_1542 = b32csel ssa_1539, ssa_1537, ssa_1529
>										vec1 32 ssa_1543 = fmul ssa_1541, ssa_1533
>										vec1 32 ssa_1544 = fmul ssa_1531, ssa_1542
>										vec1 32 ssa_1545 = fmov -ssa_1533
>										vec1 32 ssa_1546 = flt32 ssa_1543, -ssa_1544
>										vec1 32 ssa_1547 = b32csel ssa_1546, ssa_1531, ssa_1532
>										vec1 32 ssa_1548 = b32csel ssa_1546, ssa_1545, ssa_1533
>										vec1 32 ssa_1549 = iadd ssa_1487, ssa_1439
>										/* succs: block_205 */
>										loop {
>											block block_205:
>											/* preds: block_204 block_301 */
>											vec1 32 ssa_1550 = phi block_204: ssa_1, block_301: ssa_1910
>											vec1 32 ssa_1551 = phi block_204: ssa_1549, block_301: ssa_1558
>											vec1 32 ssa_1552 = phi block_204: ssa_1500, block_301: ssa_1907
>											vec1 32 ssa_1553 = phi block_204: ssa_77, block_301: ssa_1908
>											vec1 32 ssa_1554 = phi block_204: ssa_77, block_301: ssa_1909
>											vec1 32 ssa_1555 = uge32 ssa_1550, ssa_1488
>											/* succs: block_206 block_207 */
>											if ssa_1555 {
>												block block_206:
>												/* preds: block_205 */
>												break
>												/* succs: block_302 */
>											} else {
>												block block_207:
>												/* preds: block_205 */
>												/* succs: block_208 */
>											}
>											block block_208:
>											/* preds: block_207 */
>											vec1 32 ssa_1556 = ishl ssa_1551, ssa_31
>											vec1 32 ssa_1557 = intrinsic load_ssbo (ssa_30, ssa_1556) (0, 4, 0) /* access=0 */ /* align_mul=4 */ /* align_offset=0 */
>											vec1 32 ssa_1558 = iadd ssa_1551, ssa_30
>											vec1 32 ssa_1559 = extract_u16 ssa_1557, ssa_1
>											vec1 32 ssa_1560 = ishl ssa_1559, ssa_75
>											vec1 32 ssa_1561 = ushr ssa_1560, ssa_75
>											vec1 32 ssa_1562 = iadd ssa_1439, ssa_1561
>											vec1 32 ssa_1563 = iand ssa_1559, ssa_79
>											vec1 32 ssa_1564 = ishl ssa_1562, ssa_31
>											vec1 32 ssa_1565 = intrinsic load_ssbo (ssa_30, ssa_1564) (0, 4, 0) /* access=0 */ /* align_mul=4 */ /* align_offset=0 */
>											vec1 32 ssa_1566 = unpack_half_2x16_split_x ssa_1565
>											vec1 32 ssa_1567 = unpack_half_2x16_split_y ssa_1565
>											vec1 32 ssa_1568 = iadd ssa_1562, ssa_30
>											vec1 32 ssa_1569 = ishl ssa_1568, ssa_31
>											vec1 32 ssa_1570 = intrinsic load_ssbo (ssa_30, ssa_1569) (0, 4, 0) /* access=0 */ /* align_mul=4 */ /* align_offset=0 */
>											vec1 32 ssa_1571 = unpack_half_2x16_split_x ssa_1570
>											vec1 32 ssa_1572 = unpack_half_2x16_split_y ssa_1570
>											vec1 32 ssa_1573 = ine32 ssa_1563, ssa_1
>											/* succs: block_209 block_210 */
>											if ssa_1573 {
>												block block_209:
>												/* preds: block_208 */
>												vec1 32 ssa_1574 = iadd ssa_1562, ssa_31
>												vec1 32 ssa_1575 = ishl ssa_1574, ssa_31
>												vec1 32 ssa_1576 = intrinsic load_ssbo (ssa_30, ssa_1575) (0, 4, 0) /* access=0 */ /* align_mul=4 */ /* align_offset=0 */
>												vec1 32 ssa_1577 = unpack_half_2x16_split_x ssa_1576
>												vec1 32 ssa_1578 = unpack_half_2x16_split_y ssa_1576
>												/* succs: block_211 */
>											} else {
>												block block_210:
>												/* preds: block_208 */
>												vec1 32 ssa_1579 = fadd ssa_1566, ssa_1571
>												vec1 32 ssa_1580 = fadd ssa_1567, ssa_1572
>												vec1 32 ssa_1581 = fmul ssa_37, ssa_1579
>												vec1 32 ssa_1582 = fmul ssa_37, ssa_1580
>												/* succs: block_211 */
>											}
>											block block_211:
>											/* preds: block_209 block_210 */
>											vec1 32 ssa_1583 = phi block_209: ssa_1577, block_210: ssa_1571
>											vec1 32 ssa_1584 = phi block_209: ssa_1578, block_210: ssa_1572
>											vec1 32 ssa_1585 = phi block_209: ssa_1571, block_210: ssa_1581
>											vec1 32 ssa_1586 = phi block_209: ssa_1572, block_210: ssa_1582
>											vec1 32 ssa_1587 = fadd ssa_1566, -ssa_5.x
>											vec1 32 ssa_1588 = fadd ssa_1567, -ssa_5.y
>											vec1 32 ssa_1589 = fmul ssa_1542, ssa_1588
>											vec1 32 ssa_1590 = ffma ssa_1541, ssa_1587, ssa_1589
>											vec1 32 ssa_1591 = fmul ssa_1548, ssa_1588
>											vec1 32 ssa_1592 = ffma ssa_1547, ssa_1587, ssa_1591
>											vec1 32 ssa_1593 = fadd ssa_1585, -ssa_5.x
>											vec1 32 ssa_1594 = fadd ssa_1586, -ssa_5.y
>											vec1 32 ssa_1595 = fmul ssa_1542, ssa_1594
>											vec1 32 ssa_1596 = ffma ssa_1541, ssa_1593, ssa_1595
>											vec1 32 ssa_1597 = fmul ssa_1548, ssa_1594
>											vec1 32 ssa_1598 = ffma ssa_1547, ssa_1593, ssa_1597
>											vec1 32 ssa_1599 = fadd ssa_1583, -ssa_5.x
>											vec1 32 ssa_1600 = fadd ssa_1584, -ssa_5.y
>											vec1 32 ssa_1601 = fmul ssa_1542, ssa_1600
>											vec1 32 ssa_1602 = ffma ssa_1541, ssa_1599, ssa_1601
>											vec1 32 ssa_1603 = fmul ssa_1548, ssa_1600
>											vec1 32 ssa_1604 = ffma ssa_1547, ssa_1599, ssa_1603
>											vec1 32 ssa_1605 = ffma -ssa_33, ssa_1596, ssa_1590
>											vec1 32 ssa_1606 = ffma -ssa_33, ssa_1598, ssa_1592
>											vec1 32 ssa_1607 = fadd ssa_1605, ssa_1602
>											vec1 32 ssa_1608 = fadd ssa_1606, ssa_1604
>											vec1 32 ssa_1609 = fadd ssa_1590, -ssa_1596
>											vec1 32 ssa_1610 = fadd ssa_1592, -ssa_1598
>											vec1 32 ssa_1611 = flt32 ssa_1, ssa_1590
>											vec1 32 ssa_1612 = b32csel ssa_1611, ssa_31, ssa_1
>											vec1 32 ssa_1613 = flt32 ssa_1, ssa_1596
>											vec1 32 ssa_1614 = b32csel ssa_1613, ssa_80, ssa_1
>											vec1 32 ssa_1615 = flt32 ssa_1, ssa_1602
>											vec1 32 ssa_1616 = b32csel ssa_1615, ssa_70, ssa_1
>											vec1 32 ssa_1617 = iadd ssa_1612, ssa_1614
>											vec1 32 ssa_1618 = iadd ssa_1617, ssa_1616
>											vec1 32 ssa_1619 = ushr ssa_81, ssa_1618
>											vec1 32 ssa_1620 = iand ssa_1619, ssa_32
>											vec1 32 ssa_1621 = flt32 ssa_1, ssa_1592
>											vec1 32 ssa_1622 = b32csel ssa_1621, ssa_31, ssa_1
>											vec1 32 ssa_1623 = flt32 ssa_1, ssa_1598
>											vec1 32 ssa_1624 = b32csel ssa_1623, ssa_80, ssa_1
>											vec1 32 ssa_1625 = flt32 ssa_1, ssa_1604
>											vec1 32 ssa_1626 = b32csel ssa_1625, ssa_70, ssa_1
>											vec1 32 ssa_1627 = iadd ssa_1622, ssa_1624
>											vec1 32 ssa_1628 = iadd ssa_1627, ssa_1626
>											vec1 32 ssa_1629 = ushr ssa_81, ssa_1628
>											vec1 32 ssa_1630 = iand ssa_1629, ssa_32
>											vec1 32 ssa_1631 = ine32 ssa_1630, ssa_1
>											/* succs: block_212 block_231 */
>											if ssa_1631 {
>												block block_212:
>												/* preds: block_211 */
>												/* succs: block_213 block_214 */
>												if ssa_1573 {
>													block block_213:
>													/* preds: block_212 */
>													vec1 32 ssa_1632 = flt32 ssa_82, abs(ssa_1608)
>													/* succs: block_215 */
>												} else {
>													block block_214:
>													/* preds: block_212 */
>													/* succs: block_215 */
>												}
>												block block_215:
>												/* preds: block_213 block_214 */
>												vec1 32 ssa_1633 = phi block_213: ssa_1632, block_214: ssa_83
>												/* succs: block_216 block_217 */
>												if ssa_1633 {
>													block block_216:
>													/* preds: block_215 */
>													vec1 32 ssa_1634 = frcp ssa_1608
>													vec1 32 ssa_1635 = fmul ssa_1608, ssa_1592
>													vec1 32 ssa_1636 = ffma ssa_1610, ssa_1610, -ssa_1635
>													vec1 32 ssa_1637 = fmax ssa_1636, ssa_1
>													vec1 32 ssa_1638 = flt32 ssa_1636, ssa_1
>													vec1 32 ssa_1639 = b32csel ssa_1638, ssa_1, ssa_1630
>													vec1 32 ssa_1640 = fsqrt ssa_1637
>													vec1 32 ssa_1641 = fadd ssa_1610, -ssa_1640
>													vec1 32 ssa_1642 = fmul ssa_1641, ssa_1634
>													vec1 32 ssa_1643 = fadd ssa_1610, ssa_1640
>													vec1 32 ssa_1644 = fmul ssa_1643, ssa_1634
>													/* succs: block_218 */
>												} else {
>													block block_217:
>													/* preds: block_215 */
>													vec1 32 ssa_1645 = fmul ssa_37, ssa_1592
>													vec1 32 ssa_1646 = frcp ssa_1610
>													vec1 32 ssa_1647 = fmul ssa_1645, ssa_1646
>													/* succs: block_218 */
>												}
>												block block_218:
>												/* preds: block_216 block_217 */
>												vec1 32 ssa_1648 = phi block_216: ssa_1644, block_217: ssa_1647
>												vec1 32 ssa_1649 = phi block_216: ssa_1642, block_217: ssa_1647
>												vec1 32 ssa_1650 = phi block_216: ssa_1639, block_217: ssa_1630
>												vec1 32 ssa_1651 = fmul ssa_1609, ssa_33
>												vec1 32 ssa_1652 = ffma ssa_1607, ssa_1649, -ssa_1651
>												vec1 32 ssa_1653 = ffma ssa_1652, ssa_1649, ssa_1590
>												vec1 32 ssa_1654 = ffma ssa_1607, ssa_1648, -ssa_1651
>												vec1 32 ssa_1655 = ffma ssa_1654, ssa_1648, ssa_1590
>												vec1 32 ssa_1656 = iand ssa_1650, ssa_30
>												vec1 32 ssa_1657 = ine32 ssa_1656, ssa_1
>												/* succs: block_219 block_223 */
>												if ssa_1657 {
>													block block_219:
>													/* preds: block_218 */
>													vec1 32 ssa_1658 = fge32 ssa_1653, ssa_1
>													vec1 32 ssa_1659 = fge32 ssa_1540, ssa_1653
>													vec1 32 ssa_1660 = iand ssa_1659, ssa_1658
>													vec1 32 ssa_1661 = b32csel ssa_1660, ssa_30, ssa_1
>													vec1 32 ssa_1662 = flt32 ssa_1653, ssa_1
>													/* succs: block_220 block_221 */
>													if ssa_1662 {
>														block block_220:
>														/* preds: block_219 */
>														vec1 32 ssa_1663 = fmin ssa_1554, abs(ssa_1653)
>														/* succs: block_222 */
>													} else {
>														block block_221:
>														/* preds: block_219 */
>														vec1 32 ssa_1664 = fmin ssa_1553, abs(ssa_1653)
>														/* succs: block_222 */
>													}
>													block block_222:
>													/* preds: block_220 block_221 */
>													vec1 32 ssa_1665 = phi block_220: ssa_1553, block_221: ssa_1664
>													vec1 32 ssa_1666 = phi block_220: ssa_1663, block_221: ssa_1554
>													/* succs: block_224 */
>												} else {
>													block block_223:
>													/* preds: block_218 */
>													/* succs: block_224 */
>												}
>												block block_224:
>												/* preds: block_222 block_223 */
>												vec1 32 ssa_1667 = phi block_222: ssa_1665, block_223: ssa_1553
>												vec1 32 ssa_1668 = phi block_222: ssa_1666, block_223: ssa_1554
>												vec1 32 ssa_1669 = phi block_222: ssa_1661, block_223: ssa_1
>												vec1 32 ssa_1670 = ult32 ssa_30, ssa_1650
>												/* succs: block_225 block_229 */
>												if ssa_1670 {
>													block block_225:
>													/* preds: block_224 */
>													vec1 32 ssa_1671 = fge32 ssa_1655, ssa_1
>													vec1 32 ssa_1672 = fge32 ssa_1540, ssa_1655
>													vec1 32 ssa_1673 = iand ssa_1672, ssa_1671
>													vec1 32 ssa_1674 = iadd ssa_1669, ssa_25
>													vec1 32 ssa_1675 = b32csel ssa_1673, ssa_1674, ssa_1669
>													vec1 32 ssa_1676 = flt32 ssa_1, ssa_1655
>													/* succs: block_226 block_227 */
>													if ssa_1676 {
>														block block_226:
>														/* preds: block_225 */
>														vec1 32 ssa_1677 = fmin ssa_1668, abs(ssa_1655)
>														/* succs: block_228 */
>													} else {
>														block block_227:
>														/* preds: block_225 */
>														vec1 32 ssa_1678 = fmin ssa_1667, abs(ssa_1655)
>														/* succs: block_228 */
>													}
>													block block_228:
>													/* preds: block_226 block_227 */
>													vec1 32 ssa_1679 = phi block_226: ssa_1667, block_227: ssa_1678
>													vec1 32 ssa_1680 = phi block_226: ssa_1677, block_227: ssa_1668
>													/* succs: block_230 */
>												} else {
>													block block_229:
>													/* preds: block_224 */
>													/* succs: block_230 */
>												}
>												block block_230:
>												/* preds: block_228 block_229 */
>												vec1 32 ssa_1681 = phi block_228: ssa_1679, block_229: ssa_1667
>												vec1 32 ssa_1682 = phi block_228: ssa_1680, block_229: ssa_1668
>												vec1 32 ssa_1683 = phi block_228: ssa_1675, block_229: ssa_1669
>												/* succs: block_232 */
>											} else {
>												block block_231:
>												/* preds: block_211 */
>												/* succs: block_232 */
>											}
>											block block_232:
>											/* preds: block_230 block_231 */
>											vec1 32 ssa_1684 = phi block_230: ssa_1681, block_231: ssa_1553
>											vec1 32 ssa_1685 = phi block_230: ssa_1682, block_231: ssa_1554
>											vec1 32 ssa_1686 = phi block_230: ssa_1683, block_231: ssa_1
>											vec1 32 ssa_1687 = ine32 ssa_1620, ssa_1
>											/* succs: block_233 block_252 */
>											if ssa_1687 {
>												block block_233:
>												/* preds: block_232 */
>												/* succs: block_234 block_235 */
>												if ssa_1573 {
>													block block_234:
>													/* preds: block_233 */
>													vec1 32 ssa_1688 = flt32 ssa_82, abs(ssa_1607)
>													/* succs: block_236 */
>												} else {
>													block block_235:
>													/* preds: block_233 */
>													/* succs: block_236 */
>												}
>												block block_236:
>												/* preds: block_234 block_235 */
>												vec1 32 ssa_1689 = phi block_234: ssa_1688, block_235: ssa_83
>												/* succs: block_237 block_238 */
>												if ssa_1689 {
>													block block_237:
>													/* preds: block_236 */
>													vec1 32 ssa_1690 = frcp ssa_1607
>													vec1 32 ssa_1691 = fmul ssa_1607, ssa_1590
>													vec1 32 ssa_1692 = ffma ssa_1609, ssa_1609, -ssa_1691
>													vec1 32 ssa_1693 = fmax ssa_1692, ssa_1
>													vec1 32 ssa_1694 = flt32 ssa_1692, ssa_1
>													vec1 32 ssa_1695 = b32csel ssa_1694, ssa_1, ssa_1620
>													vec1 32 ssa_1696 = fsqrt ssa_1693
>													vec1 32 ssa_1697 = fadd ssa_1609, -ssa_1696
>													vec1 32 ssa_1698 = fmul ssa_1697, ssa_1690
>													vec1 32 ssa_1699 = fadd ssa_1609, ssa_1696
>													vec1 32 ssa_1700 = fmul ssa_1699, ssa_1690
>													/* succs: block_239 */
>												} else {
>													block block_238:
>													/* preds: block_236 */
>													vec1 32 ssa_1701 = fmul ssa_37, ssa_1590
>													vec1 32 ssa_1702 = frcp ssa_1609
>													vec1 32 ssa_1703 = fmul ssa_1701, ssa_1702
>													/* succs: block_239 */
>												}
>												block block_239:
>												/* preds: block_237 block_238 */
>												vec1 32 ssa_1704 = phi block_237: ssa_1700, block_238: ssa_1703
>												vec1 32 ssa_1705 = phi block_237: ssa_1698, block_238: ssa_1703
>												vec1 32 ssa_1706 = phi block_237: ssa_1695, block_238: ssa_1620
>												vec1 32 ssa_1707 = fmul ssa_1610, ssa_33
>												vec1 32 ssa_1708 = ffma ssa_1608, ssa_1705, -ssa_1707
>												vec1 32 ssa_1709 = ffma ssa_1708, ssa_1705, ssa_1592
>												vec1 32 ssa_1710 = ffma ssa_1608, ssa_1704, -ssa_1707
>												vec1 32 ssa_1711 = ffma ssa_1710, ssa_1704, ssa_1592
>												vec1 32 ssa_1712 = iand ssa_1706, ssa_30
>												vec1 32 ssa_1713 = ine32 ssa_1712, ssa_1
>												/* succs: block_240 block_244 */
>												if ssa_1713 {
>													block block_240:
>													/* preds: block_239 */
>													vec1 32 ssa_1714 = flt32 ssa_1, ssa_1709
>													/* succs: block_241 block_242 */
>													if ssa_1714 {
>														block block_241:
>														/* preds: block_240 */
>														vec1 32 ssa_1715 = fmin ssa_1685, abs(ssa_1709)
>														/* succs: block_243 */
>													} else {
>														block block_242:
>														/* preds: block_240 */
>														vec1 32 ssa_1716 = fmin ssa_1684, abs(ssa_1709)
>														/* succs: block_243 */
>													}
>													block block_243:
>													/* preds: block_241 block_242 */
>													vec1 32 ssa_1717 = phi block_241: ssa_1684, block_242: ssa_1716
>													vec1 32 ssa_1718 = phi block_241: ssa_1715, block_242: ssa_1685
>													/* succs: block_245 */
>												} else {
>													block block_244:
>													/* preds: block_239 */
>													/* succs: block_245 */
>												}
>												block block_245:
>												/* preds: block_243 block_244 */
>												vec1 32 ssa_1719 = phi block_243: ssa_1717, block_244: ssa_1684
>												vec1 32 ssa_1720 = phi block_243: ssa_1718, block_244: ssa_1685
>												vec1 32 ssa_1721 = ult32 ssa_30, ssa_1706
>												/* succs: block_246 block_250 */
>												if ssa_1721 {
>													block block_246:
>													/* preds: block_245 */
>													vec1 32 ssa_1722 = flt32 ssa_1711, ssa_1
>													/* succs: block_247 block_248 */
>													if ssa_1722 {
>														block block_247:
>														/* preds: block_246 */
>														vec1 32 ssa_1723 = fmin ssa_1720, abs(ssa_1711)
>														/* succs: block_249 */
>													} else {
>														block block_248:
>														/* preds: block_246 */
>														vec1 32 ssa_1724 = fmin ssa_1719, abs(ssa_1711)
>														/* succs: block_249 */
>													}
>													block block_249:
>													/* preds: block_247 block_248 */
>													vec1 32 ssa_1725 = phi block_247: ssa_1719, block_248: ssa_1724
>													vec1 32 ssa_1726 = phi block_247: ssa_1723, block_248: ssa_1720
>													/* succs: block_251 */
>												} else {
>													block block_250:
>													/* preds: block_245 */
>													/* succs: block_251 */
>												}
>												block block_251:
>												/* preds: block_249 block_250 */
>												vec1 32 ssa_1727 = phi block_249: ssa_1725, block_250: ssa_1719
>												vec1 32 ssa_1728 = phi block_249: ssa_1726, block_250: ssa_1720
>												/* succs: block_253 */
>											} else {
>												block block_252:
>												/* preds: block_232 */
>												/* succs: block_253 */
>											}
>											block block_253:
>											/* preds: block_251 block_252 */
>											vec1 32 ssa_1729 = phi block_251: ssa_1727, block_252: ssa_1684
>											vec1 32 ssa_1730 = phi block_251: ssa_1728, block_252: ssa_1685
>											vec1 32 ssa_1731 = iadd ssa_1552, ssa_1686
>											vec1 32 ssa_1732 = iadd ssa_1550, ssa_30
>											vec1 32 ssa_1733 = ult32 ssa_1732, ssa_1488
>											/* succs: block_254 block_300 */
>											if ssa_1733 {
>												block block_254:
>												/* preds: block_253 */
>												vec1 32 ssa_1734 = extract_u16 ssa_1557, ssa_30
>												vec1 32 ssa_1735 = ishl ssa_1734, ssa_75
>												vec1 32 ssa_1736 = ushr ssa_1735, ssa_75
>												vec1 32 ssa_1737 = iadd ssa_1439, ssa_1736
>												vec1 32 ssa_1738 = iand ssa_1734, ssa_79
>												vec1 32 ssa_1739 = ishl ssa_1737, ssa_31
>												vec1 32 ssa_1740 = intrinsic load_ssbo (ssa_30, ssa_1739) (0, 4, 0) /* access=0 */ /* align_mul=4 */ /* align_offset=0 */
>												vec1 32 ssa_1741 = unpack_half_2x16_split_x ssa_1740
>												vec1 32 ssa_1742 = unpack_half_2x16_split_y ssa_1740
>												vec1 32 ssa_1743 = iadd ssa_1737, ssa_30
>												vec1 32 ssa_1744 = ishl ssa_1743, ssa_31
>												vec1 32 ssa_1745 = intrinsic load_ssbo (ssa_30, ssa_1744) (0, 4, 0) /* access=0 */ /* align_mul=4 */ /* align_offset=0 */
>												vec1 32 ssa_1746 = unpack_half_2x16_split_x ssa_1745
>												vec1 32 ssa_1747 = unpack_half_2x16_split_y ssa_1745
>												vec1 32 ssa_1748 = ine32 ssa_1738, ssa_1
>												/* succs: block_255 block_256 */
>												if ssa_1748 {
>													block block_255:
>													/* preds: block_254 */
>													vec1 32 ssa_1749 = iadd ssa_1737, ssa_31
>													vec1 32 ssa_1750 = ishl ssa_1749, ssa_31
>													vec1 32 ssa_1751 = intrinsic load_ssbo (ssa_30, ssa_1750) (0, 4, 0) /* access=0 */ /* align_mul=4 */ /* align_offset=0 */
>													vec1 32 ssa_1752 = unpack_half_2x16_split_x ssa_1751
>													vec1 32 ssa_1753 = unpack_half_2x16_split_y ssa_1751
>													/* succs: block_257 */
>												} else {
>													block block_256:
>													/* preds: block_254 */
>													vec1 32 ssa_1754 = fadd ssa_1741, ssa_1746
>													vec1 32 ssa_1755 = fadd ssa_1742, ssa_1747
>													vec1 32 ssa_1756 = fmul ssa_37, ssa_1754
>													vec1 32 ssa_1757 = fmul ssa_37, ssa_1755
>													/* succs: block_257 */
>												}
>												block block_257:
>												/* preds: block_255 block_256 */
>												vec1 32 ssa_1758 = phi block_255: ssa_1752, block_256: ssa_1746
>												vec1 32 ssa_1759 = phi block_255: ssa_1753, block_256: ssa_1747
>												vec1 32 ssa_1760 = phi block_255: ssa_1746, block_256: ssa_1756
>												vec1 32 ssa_1761 = phi block_255: ssa_1747, block_256: ssa_1757
>												vec1 32 ssa_1762 = fadd ssa_1741, -ssa_5.x
>												vec1 32 ssa_1763 = fadd ssa_1742, -ssa_5.y
>												vec1 32 ssa_1764 = fmul ssa_1542, ssa_1763
>												vec1 32 ssa_1765 = ffma ssa_1541, ssa_1762, ssa_1764
>												vec1 32 ssa_1766 = fmul ssa_1548, ssa_1763
>												vec1 32 ssa_1767 = ffma ssa_1547, ssa_1762, ssa_1766
>												vec1 32 ssa_1768 = fadd ssa_1760, -ssa_5.x
>												vec1 32 ssa_1769 = fadd ssa_1761, -ssa_5.y
>												vec1 32 ssa_1770 = fmul ssa_1542, ssa_1769
>												vec1 32 ssa_1771 = ffma ssa_1541, ssa_1768, ssa_1770
>												vec1 32 ssa_1772 = fmul ssa_1548, ssa_1769
>												vec1 32 ssa_1773 = ffma ssa_1547, ssa_1768, ssa_1772
>												vec1 32 ssa_1774 = fadd ssa_1758, -ssa_5.x
>												vec1 32 ssa_1775 = fadd ssa_1759, -ssa_5.y
>												vec1 32 ssa_1776 = fmul ssa_1542, ssa_1775
>												vec1 32 ssa_1777 = ffma ssa_1541, ssa_1774, ssa_1776
>												vec1 32 ssa_1778 = fmul ssa_1548, ssa_1775
>												vec1 32 ssa_1779 = ffma ssa_1547, ssa_1774, ssa_1778
>												vec1 32 ssa_1780 = ffma -ssa_33, ssa_1771, ssa_1765
>												vec1 32 ssa_1781 = ffma -ssa_33, ssa_1773, ssa_1767
>												vec1 32 ssa_1782 = fadd ssa_1780, ssa_1777
>												vec1 32 ssa_1783 = fadd ssa_1781, ssa_1779
>												vec1 32 ssa_1784 = fadd ssa_1765, -ssa_1771
>												vec1 32 ssa_1785 = fadd ssa_1767, -ssa_1773
>												vec1 32 ssa_1786 = flt32 ssa_1, ssa_1765
>												vec1 32 ssa_1787 = b32csel ssa_1786, ssa_31, ssa_1
>												vec1 32 ssa_1788 = flt32 ssa_1, ssa_1771
>												vec1 32 ssa_1789 = b32csel ssa_1788, ssa_80, ssa_1
>												vec1 32 ssa_1790 = flt32 ssa_1, ssa_1777
>												vec1 32 ssa_1791 = b32csel ssa_1790, ssa_70, ssa_1
>												vec1 32 ssa_1792 = iadd ssa_1787, ssa_1789
>												vec1 32 ssa_1793 = iadd ssa_1792, ssa_1791
>												vec1 32 ssa_1794 = ushr ssa_81, ssa_1793
>												vec1 32 ssa_1795 = iand ssa_1794, ssa_32
>												vec1 32 ssa_1796 = flt32 ssa_1, ssa_1767
>												vec1 32 ssa_1797 = b32csel ssa_1796, ssa_31, ssa_1
>												vec1 32 ssa_1798 = flt32 ssa_1, ssa_1773
>												vec1 32 ssa_1799 = b32csel ssa_1798, ssa_80, ssa_1
>												vec1 32 ssa_1800 = flt32 ssa_1, ssa_1779
>												vec1 32 ssa_1801 = b32csel ssa_1800, ssa_70, ssa_1
>												vec1 32 ssa_1802 = iadd ssa_1797, ssa_1799
>												vec1 32 ssa_1803 = iadd ssa_1802, ssa_1801
>												vec1 32 ssa_1804 = ushr ssa_81, ssa_1803
>												vec1 32 ssa_1805 = iand ssa_1804, ssa_32
>												vec1 32 ssa_1806 = ine32 ssa_1805, ssa_1
>												/* succs: block_258 block_277 */
>												if ssa_1806 {
>													block block_258:
>													/* preds: block_257 */
>													/* succs: block_259 block_260 */
>													if ssa_1748 {
>														block block_259:
>														/* preds: block_258 */
>														vec1 32 ssa_1807 = flt32 ssa_82, abs(ssa_1783)
>														/* succs: block_261 */
>													} else {
>														block block_260:
>														/* preds: block_258 */
>														/* succs: block_261 */
>													}
>													block block_261:
>													/* preds: block_259 block_260 */
>													vec1 32 ssa_1808 = phi block_259: ssa_1807, block_260: ssa_83
>													/* succs: block_262 block_263 */
>													if ssa_1808 {
>														block block_262:
>														/* preds: block_261 */
>														vec1 32 ssa_1809 = frcp ssa_1783
>														vec1 32 ssa_1810 = fmul ssa_1783, ssa_1767
>														vec1 32 ssa_1811 = ffma ssa_1785, ssa_1785, -ssa_1810
>														vec1 32 ssa_1812 = fmax ssa_1811, ssa_1
>														vec1 32 ssa_1813 = flt32 ssa_1811, ssa_1
>														vec1 32 ssa_1814 = b32csel ssa_1813, ssa_1, ssa_1805
>														vec1 32 ssa_1815 = fsqrt ssa_1812
>														vec1 32 ssa_1816 = fadd ssa_1785, -ssa_1815
>														vec1 32 ssa_1817 = fmul ssa_1816, ssa_1809
>														vec1 32 ssa_1818 = fadd ssa_1785, ssa_1815
>														vec1 32 ssa_1819 = fmul ssa_1818, ssa_1809
>														/* succs: block_264 */
>													} else {
>														block block_263:
>														/* preds: block_261 */
>														vec1 32 ssa_1820 = fmul ssa_37, ssa_1767
>														vec1 32 ssa_1821 = frcp ssa_1785
>														vec1 32 ssa_1822 = fmul ssa_1820, ssa_1821
>														/* succs: block_264 */
>													}
>													block block_264:
>													/* preds: block_262 block_263 */
>													vec1 32 ssa_1823 = phi block_262: ssa_1819, block_263: ssa_1822
>													vec1 32 ssa_1824 = phi block_262: ssa_1817, block_263: ssa_1822
>													vec1 32 ssa_1825 = phi block_262: ssa_1814, block_263: ssa_1805
>													vec1 32 ssa_1826 = fmul ssa_1784, ssa_33
>													vec1 32 ssa_1827 = ffma ssa_1782, ssa_1824, -ssa_1826
>													vec1 32 ssa_1828 = ffma ssa_1827, ssa_1824, ssa_1765
>													vec1 32 ssa_1829 = ffma ssa_1782, ssa_1823, -ssa_1826
>													vec1 32 ssa_1830 = ffma ssa_1829, ssa_1823, ssa_1765
>													vec1 32 ssa_1831 = iand ssa_1825, ssa_30
>													vec1 32 ssa_1832 = ine32 ssa_1831, ssa_1
>													/* succs: block_265 block_269 */
>													if ssa_1832 {
>														block block_265:
>														/* preds: block_264 */
>														vec1 32 ssa_1833 = fge32 ssa_1828, ssa_1
>														vec1 32 ssa_1834 = fge32 ssa_1540, ssa_1828
>														vec1 32 ssa_1835 = iand ssa_1834, ssa_1833
>														vec1 32 ssa_1836 = b32csel ssa_1835, ssa_30, ssa_1
>														vec1 32 ssa_1837 = flt32 ssa_1828, ssa_1
>														/* succs: block_266 block_267 */
>														if ssa_1837 {
>															block block_266:
>															/* preds: block_265 */
>															vec1 32 ssa_1838 = fmin ssa_1730, abs(ssa_1828)
>															/* succs: block_268 */
>														} else {
>															block block_267:
>															/* preds: block_265 */
>															vec1 32 ssa_1839 = fmin ssa_1729, abs(ssa_1828)
>															/* succs: block_268 */
>														}
>														block block_268:
>														/* preds: block_266 block_267 */
>														vec1 32 ssa_1840 = phi block_266: ssa_1729, block_267: ssa_1839
>														vec1 32 ssa_1841 = phi block_266: ssa_1838, block_267: ssa_1730
>														/* succs: block_270 */
>													} else {
>														block block_269:
>														/* preds: block_264 */
>														/* succs: block_270 */
>													}
>													block block_270:
>													/* preds: block_268 block_269 */
>													vec1 32 ssa_1842 = phi block_268: ssa_1840, block_269: ssa_1729
>													vec1 32 ssa_1843 = phi block_268: ssa_1841, block_269: ssa_1730
>													vec1 32 ssa_1844 = phi block_268: ssa_1836, block_269: ssa_1
>													vec1 32 ssa_1845 = ult32 ssa_30, ssa_1825
>													/* succs: block_271 block_275 */
>													if ssa_1845 {
>														block block_271:
>														/* preds: block_270 */
>														vec1 32 ssa_1846 = fge32 ssa_1830, ssa_1
>														vec1 32 ssa_1847 = fge32 ssa_1540, ssa_1830
>														vec1 32 ssa_1848 = iand ssa_1847, ssa_1846
>														vec1 32 ssa_1849 = iadd ssa_1844, ssa_25
>														vec1 32 ssa_1850 = b32csel ssa_1848, ssa_1849, ssa_1844
>														vec1 32 ssa_1851 = flt32 ssa_1, ssa_1830
>														/* succs: block_272 block_273 */
>														if ssa_1851 {
>															block block_272:
>															/* preds: block_271 */
>															vec1 32 ssa_1852 = fmin ssa_1843, abs(ssa_1830)
>															/* succs: block_274 */
>														} else {
>															block block_273:
>															/* preds: block_271 */
>															vec1 32 ssa_1853 = fmin ssa_1842, abs(ssa_1830)
>															/* succs: block_274 */
>														}
>														block block_274:
>														/* preds: block_272 block_273 */
>														vec1 32 ssa_1854 = phi block_272: ssa_1842, block_273: ssa_1853
>														vec1 32 ssa_1855 = phi block_272: ssa_1852, block_273: ssa_1843
>														/* succs: block_276 */
>													} else {
>														block block_275:
>														/* preds: block_270 */
>														/* succs: block_276 */
>													}
>													block block_276:
>													/* preds: block_274 block_275 */
>													vec1 32 ssa_1856 = phi block_274: ssa_1854, block_275: ssa_1842
>													vec1 32 ssa_1857 = phi block_274: ssa_1855, block_275: ssa_1843
>													vec1 32 ssa_1858 = phi block_274: ssa_1850, block_275: ssa_1844
>													/* succs: block_278 */
>												} else {
>													block block_277:
>													/* preds: block_257 */
>													/* succs: block_278 */
>												}
>												block block_278:
>												/* preds: block_276 block_277 */
>												vec1 32 ssa_1859 = phi block_276: ssa_1856, block_277: ssa_1729
>												vec1 32 ssa_1860 = phi block_276: ssa_1857, block_277: ssa_1730
>												vec1 32 ssa_1861 = phi block_276: ssa_1858, block_277: ssa_1
>												vec1 32 ssa_1862 = ine32 ssa_1795, ssa_1
>												/* succs: block_279 block_298 */
>												if ssa_1862 {
>													block block_279:
>													/* preds: block_278 */
>													/* succs: block_280 block_281 */
>													if ssa_1748 {
>														block block_280:
>														/* preds: block_279 */
>														vec1 32 ssa_1863 = flt32 ssa_82, abs(ssa_1782)
>														/* succs: block_282 */
>													} else {
>														block block_281:
>														/* preds: block_279 */
>														/* succs: block_282 */
>													}
>													block block_282:
>													/* preds: block_280 block_281 */
>													vec1 32 ssa_1864 = phi block_280: ssa_1863, block_281: ssa_83
>													/* succs: block_283 block_284 */
>													if ssa_1864 {
>														block block_283:
>														/* preds: block_282 */
>														vec1 32 ssa_1865 = frcp ssa_1782
>														vec1 32 ssa_1866 = fmul ssa_1782, ssa_1765
>														vec1 32 ssa_1867 = ffma ssa_1784, ssa_1784, -ssa_1866
>														vec1 32 ssa_1868 = fmax ssa_1867, ssa_1
>														vec1 32 ssa_1869 = flt32 ssa_1867, ssa_1
>														vec1 32 ssa_1870 = b32csel ssa_1869, ssa_1, ssa_1795
>														vec1 32 ssa_1871 = fsqrt ssa_1868
>														vec1 32 ssa_1872 = fadd ssa_1784, -ssa_1871
>														vec1 32 ssa_1873 = fmul ssa_1872, ssa_1865
>														vec1 32 ssa_1874 = fadd ssa_1784, ssa_1871
>														vec1 32 ssa_1875 = fmul ssa_1874, ssa_1865
>														/* succs: block_285 */
>													} else {
>														block block_284:
>														/* preds: block_282 */
>														vec1 32 ssa_1876 = fmul ssa_37, ssa_1765
>														vec1 32 ssa_1877 = frcp ssa_1784
>														vec1 32 ssa_1878 = fmul ssa_1876, ssa_1877
>														/* succs: block_285 */
>													}
>													block block_285:
>													/* preds: block_283 block_284 */
>													vec1 32 ssa_1879 = phi block_283: ssa_1875, block_284: ssa_1878
>													vec1 32 ssa_1880 = phi block_283: ssa_1873, block_284: ssa_1878
>													vec1 32 ssa_1881 = phi block_283: ssa_1870, block_284: ssa_1795
>													vec1 32 ssa_1882 = fmul ssa_1785, ssa_33
>													vec1 32 ssa_1883 = ffma ssa_1783, ssa_1880, -ssa_1882
>													vec1 32 ssa_1884 = ffma ssa_1883, ssa_1880, ssa_1767
>													vec1 32 ssa_1885 = ffma ssa_1783, ssa_1879, -ssa_1882
>													vec1 32 ssa_1886 = ffma ssa_1885, ssa_1879, ssa_1767
>													vec1 32 ssa_1887 = iand ssa_1881, ssa_30
>													vec1 32 ssa_1888 = ine32 ssa_1887, ssa_1
>													/* succs: block_286 block_290 */
>													if ssa_1888 {
>														block block_286:
>														/* preds: block_285 */
>														vec1 32 ssa_1889 = flt32 ssa_1, ssa_1884
>														/* succs: block_287 block_288 */
>														if ssa_1889 {
>															block block_287:
>															/* preds: block_286 */
>															vec1 32 ssa_1890 = fmin ssa_1860, abs(ssa_1884)
>															/* succs: block_289 */
>														} else {
>															block block_288:
>															/* preds: block_286 */
>															vec1 32 ssa_1891 = fmin ssa_1859, abs(ssa_1884)
>															/* succs: block_289 */
>														}
>														block block_289:
>														/* preds: block_287 block_288 */
>														vec1 32 ssa_1892 = phi block_287: ssa_1859, block_288: ssa_1891
>														vec1 32 ssa_1893 = phi block_287: ssa_1890, block_288: ssa_1860
>														/* succs: block_291 */
>													} else {
>														block block_290:
>														/* preds: block_285 */
>														/* succs: block_291 */
>													}
>													block block_291:
>													/* preds: block_289 block_290 */
>													vec1 32 ssa_1894 = phi block_289: ssa_1892, block_290: ssa_1859
>													vec1 32 ssa_1895 = phi block_289: ssa_1893, block_290: ssa_1860
>													vec1 32 ssa_1896 = ult32 ssa_30, ssa_1881
>													/* succs: block_292 block_296 */
>													if ssa_1896 {
>														block block_292:
>														/* preds: block_291 */
>														vec1 32 ssa_1897 = flt32 ssa_1886, ssa_1
>														/* succs: block_293 block_294 */
>														if ssa_1897 {
>															block block_293:
>															/* preds: block_292 */
>															vec1 32 ssa_1898 = fmin ssa_1895, abs(ssa_1886)
>															/* succs: block_295 */
>														} else {
>															block block_294:
>															/* preds: block_292 */
>															vec1 32 ssa_1899 = fmin ssa_1894, abs(ssa_1886)
>															/* succs: block_295 */
>														}
>														block block_295:
>														/* preds: block_293 block_294 */
>														vec1 32 ssa_1900 = phi block_293: ssa_1894, block_294: ssa_1899
>														vec1 32 ssa_1901 = phi block_293: ssa_1898, block_294: ssa_1895
>														/* succs: block_297 */
>													} else {
>														block block_296:
>														/* preds: block_291 */
>														/* succs: block_297 */
>													}
>													block block_297:
>													/* preds: block_295 block_296 */
>													vec1 32 ssa_1902 = phi block_295: ssa_1900, block_296: ssa_1894
>													vec1 32 ssa_1903 = phi block_295: ssa_1901, block_296: ssa_1895
>													/* succs: block_299 */
>												} else {
>													block block_298:
>													/* preds: block_278 */
>													/* succs: block_299 */
>												}
>												block block_299:
>												/* preds: block_297 block_298 */
>												vec1 32 ssa_1904 = phi block_297: ssa_1902, block_298: ssa_1859
>												vec1 32 ssa_1905 = phi block_297: ssa_1903, block_298: ssa_1860
>												vec1 32 ssa_1906 = iadd ssa_1731, ssa_1861
>												/* succs: block_301 */
>											} else {
>												block block_300:
>												/* preds: block_253 */
>												/* succs: block_301 */
>											}
>											block block_301:
>											/* preds: block_299 block_300 */
>											vec1 32 ssa_1907 = phi block_299: ssa_1906, block_300: ssa_1731
>											vec1 32 ssa_1908 = phi block_299: ssa_1904, block_300: ssa_1729
>											vec1 32 ssa_1909 = phi block_299: ssa_1905, block_300: ssa_1730
>											vec1 32 ssa_1910 = iadd ssa_1550, ssa_31
>											/* succs: block_205 */
>										}
>										block block_302:
>										/* preds: block_206 */
>										vec1 32 ssa_1911 = ieq32 ssa_1552, ssa_1
>										vec1 32 ssa_1912 = ior ssa_1911, ssa_1448
>										/* succs: block_303 block_304 */
>										if ssa_1912 {
>											block block_303:
>											/* preds: block_302 */
>											vec1 32 ssa_1913 = fmin ssa_1554, ssa_1553
>											/* succs: block_308 */
>										} else {
>											block block_304:
>											/* preds: block_302 */
>											vec1 32 ssa_1914 = ine32 ssa_1552, ssa_25
>											/* succs: block_305 block_306 */
>											if ssa_1914 {
>												block block_305:
>												/* preds: block_304 */
>												vec1 32 ssa_1915 = ieq32 ssa_1552, ssa_30
>												vec1 32 ssa_1916 = b32csel ssa_1915, ssa_1553, ssa_37
>												/* succs: block_307 */
>											} else {
>												block block_306:
>												/* preds: block_304 */
>												/* succs: block_307 */
>											}
>											block block_307:
>											/* preds: block_305 block_306 */
>											vec1 32 ssa_1917 = phi block_306: ssa_1554, block_305: ssa_1916
>											/* succs: block_308 */
>										}
>										block block_308:
>										/* preds: block_303 block_307 */
>										vec1 32 ssa_1918 = phi block_303: ssa_1913, block_307: ssa_1917
>										vec1 32 ssa_1919 = fmin ssa_1918, ssa_37
>										vec1 32 ssa_1920 = iand ssa_1552, ssa_30
>										vec1 32 ssa_1921 = ieq32 ssa_1920, ssa_1
>										vec1 32 ssa_1922 = iand ssa_1448, ssa_1921
>										vec1 32 ssa_1923 = b32csel ssa_1922, ssa_1, ssa_1552
>										vec1 32 ssa_1924 = ine32 ssa_1923, ssa_1
>										/* succs: block_309 block_310 */
>										if ssa_1924 {
>											block block_309:
>											/* preds: block_308 */
>											vec1 32 ssa_1925 = fadd ssa_37, ssa_1919
>											/* succs: block_311 */
>										} else {
>											block block_310:
>											/* preds: block_308 */
>											vec1 32 ssa_1926 = fadd ssa_37, -ssa_1919
>											/* succs: block_311 */
>										}
>										block block_311:
>										/* preds: block_309 block_310 */
>										vec1 32 ssa_1927 = phi block_309: ssa_1925, block_310: ssa_1926
>										vec1 32 ssa_1928 = iand ssa_1438.x, ssa_33
>										vec1 32 ssa_1929 = ine32 ssa_1928, ssa_1
>										/* succs: block_312 block_313 */
>										if ssa_1929 {
>											block block_312:
>											/* preds: block_311 */
>											vec1 32 ssa_1930 = fadd ssa_35, -ssa_1927
>											/* succs: block_314 */
>										} else {
>											block block_313:
>											/* preds: block_311 */
>											/* succs: block_314 */
>										}
>										block block_314:
>										/* preds: block_312 block_313 */
>										vec1 32 ssa_1931 = phi block_312: ssa_1930, block_313: ssa_1927
>										/* succs: block_386 */
>									} else {
>										block block_315:
>										/* preds: block_195 */
>										vec1 32 ssa_1932 = ieq32 ssa_1123.y, ssa_53
>										/* succs: block_316 block_384 */
>										if ssa_1932 {
>											block block_316:
>											/* preds: block_315 */
>											vec1 32 ssa_1933 = fddx ssa_5.x
>											vec4 32 ssa_1934 = intrinsic load_uniform (ssa_1) (0, 16) /* base=0 */ /* range=16 */	/* fastuidraw_painterStore */
>											vec1 32 ssa_1935 = fmul ssa_5.x, ssa_1934.x
>											vec1 32 ssa_1936 = fddy ssa_1935
>											vec1 32 ssa_1937 = fadd abs(ssa_1933), abs(ssa_1936)
>											vec1 32 ssa_1938 = fddx ssa_5.y
>											vec1 32 ssa_1939 = fmul ssa_5.y, ssa_1934.x
>											vec1 32 ssa_1940 = fddy ssa_1939
>											vec1 32 ssa_1941 = fadd abs(ssa_1938), abs(ssa_1940)
>											vec4 32 ssa_1942 = intrinsic load_input (ssa_1) (31, 0) /* base=31 */ /* component=0 */	/* fastuidraw_uint_varying0 */
>											vec1 32 ssa_1943 = iand ssa_1942.x, ssa_73
>											vec1 32 ssa_1944 = iand ssa_1942.x, ssa_26
>											vec1 32 ssa_1945 = ine32 ssa_1944, ssa_1
>											vec1 32 ssa_1946 = frcp ssa_1937
>											vec1 32 ssa_1947 = frcp ssa_1941
>											vec1 32 ssa_1948 = u2f32 ssa_1942.z
>											vec1 32 ssa_1949 = u2f32 ssa_1942.y
>											vec1 32 ssa_1950 = iadd ssa_1942.z, ssa_25
>											vec1 32 ssa_1951 = fadd ssa_5.x, ssa_56
>											vec1 32 ssa_1952 = fmul ssa_1948, ssa_84
>											vec1 32 ssa_1953 = fmul ssa_1952, ssa_1951
>											vec1 32 ssa_1954 = f2u32 ssa_1953
>											vec1 32 ssa_1955 = umin ssa_1950, ssa_1954
>											vec1 32 ssa_1956 = iadd ssa_1942.y, ssa_25
>											vec1 32 ssa_1957 = fadd ssa_5.y, ssa_56
>											vec1 32 ssa_1958 = fmul ssa_1949, ssa_84
>											vec1 32 ssa_1959 = fmul ssa_1958, ssa_1957
>											vec1 32 ssa_1960 = f2u32 ssa_1959
>											vec1 32 ssa_1961 = umin ssa_1956, ssa_1960
>											vec1 32 ssa_1962 = iadd ssa_1961, ssa_1942.y
>											vec1 32 ssa_1963 = flt32 ssa_5.x, ssa_1
>											vec1 32 ssa_1964 = b32csel ssa_1963, ssa_51, ssa_35
>											vec1 32 ssa_1965 = b32csel ssa_1963, ssa_1962, ssa_1961
>											vec1 32 ssa_1966 = ishl ssa_1942.y, ssa_30
>											vec1 32 ssa_1967 = iadd ssa_1955, ssa_1966
>											vec1 32 ssa_1968 = iadd ssa_1967, ssa_1942.z
>											vec1 32 ssa_1969 = flt32 ssa_5.y, ssa_1
>											vec1 32 ssa_1970 = b32csel ssa_1969, ssa_51, ssa_35
>											vec1 32 ssa_1971 = b32csel ssa_1969, ssa_1968, ssa_1967
>											vec1 32 ssa_1972 = iadd ssa_1943, ssa_1965
>											vec1 32 ssa_1973 = ishl ssa_1972, ssa_31
>											vec1 32 ssa_1974 = intrinsic load_ssbo (ssa_30, ssa_1973) (0, 4, 0) /* access=0 */ /* align_mul=4 */ /* align_offset=0 */
>											vec1 32 ssa_1975 = extract_u8 ssa_1974, ssa_1
>											vec1 32 ssa_1976 = iadd ssa_1943, ssa_1971
>											vec1 32 ssa_1977 = ishl ssa_1976, ssa_31
>											vec1 32 ssa_1978 = intrinsic load_ssbo (ssa_30, ssa_1977) (0, 4, 0) /* access=0 */ /* align_mul=4 */ /* align_offset=0 */
>											vec1 32 ssa_1979 = extract_u8 ssa_1978, ssa_1
>											vec1 32 ssa_1980 = ushr ssa_1978, ssa_70
>											vec1 32 ssa_1981 = ushr ssa_1974, ssa_70
>											vec1 32 ssa_1982 = iadd ssa_1981, ssa_1943
>											/* succs: block_317 */
>											loop {
>												block block_317:
>												/* preds: block_316 block_344 */
>												vec1 32 ssa_1983 = phi block_316: ssa_1982, block_344: ssa_2073
>												vec1 32 ssa_1984 = phi block_316: ssa_37, block_344: ssa_2071
>												vec1 32 ssa_1985 = phi block_316: ssa_1, block_344: ssa_2072
>												vec1 32 ssa_1986 = phi block_316: ssa_1, block_344: ssa_2074
>												vec1 32 ssa_1987 = uge32 ssa_1986, ssa_1975
>												/* succs: block_318 block_319 */
>												if ssa_1987 {
>													block block_318:
>													/* preds: block_317 */
>													break
>													/* succs: block_345 */
>												} else {
>													block block_319:
>													/* preds: block_317 */
>													/* succs: block_320 */
>												}
>												block block_320:
>												/* preds: block_319 */
>												vec1 32 ssa_1988 = ishl ssa_1983, ssa_31
>												vec1 32 ssa_1989 = intrinsic load_ssbo (ssa_30, ssa_1988) (0, 4, 0) /* access=0 */ /* align_mul=4 */ /* align_offset=0 */
>												vec1 32 ssa_1990 = unpack_half_2x16_split_x ssa_1989
>												vec1 32 ssa_1991 = unpack_half_2x16_split_y ssa_1989
>												vec1 32 ssa_1992 = fadd ssa_1990, -ssa_5.x
>												vec1 32 ssa_1993 = fadd ssa_1991, -ssa_5.y
>												vec1 32 ssa_1994 = iadd ssa_1983, ssa_30
>												vec1 32 ssa_1995 = ishl ssa_1994, ssa_31
>												vec1 32 ssa_1996 = intrinsic load_ssbo (ssa_30, ssa_1995) (0, 4, 0) /* access=0 */ /* align_mul=4 */ /* align_offset=0 */
>												vec1 32 ssa_1997 = unpack_half_2x16_split_x ssa_1996
>												vec1 32 ssa_1998 = unpack_half_2x16_split_y ssa_1996
>												vec1 32 ssa_1999 = fadd ssa_1997, -ssa_5.x
>												vec1 32 ssa_2000 = fadd ssa_1998, -ssa_5.y
>												vec1 32 ssa_2001 = iadd ssa_1983, ssa_31
>												vec1 32 ssa_2002 = ishl ssa_2001, ssa_31
>												vec1 32 ssa_2003 = intrinsic load_ssbo (ssa_30, ssa_2002) (0, 4, 0) /* access=0 */ /* align_mul=4 */ /* align_offset=0 */
>												vec1 32 ssa_2004 = unpack_half_2x16_split_x ssa_2003
>												vec1 32 ssa_2005 = unpack_half_2x16_split_y ssa_2003
>												vec1 32 ssa_2006 = fadd ssa_2004, -ssa_5.x
>												vec1 32 ssa_2007 = fadd ssa_2005, -ssa_5.y
>												vec1 32 ssa_2008 = fge32 ssa_5.x, ssa_1
>												/* succs: block_321 block_322 */
>												if ssa_2008 {
>													block block_321:
>													/* preds: block_320 */
>													vec1 32 ssa_2009 = fmax ssa_1999, ssa_2006
>													vec1 32 ssa_2010 = fmax ssa_1992, ssa_2009
>													vec1 32 ssa_2011 = fmul ssa_2010, ssa_1946
>													vec1 32 ssa_2012 = flt32 ssa_2011, ssa_63
>													/* succs: block_323 */
>												} else {
>													block block_322:
>													/* preds: block_320 */
>													/* succs: block_323 */
>												}
>												block block_323:
>												/* preds: block_321 block_322 */
>												vec1 32 ssa_2013 = phi block_321: ssa_2012, block_322: ssa_83
>												/* succs: block_324 block_325 */
>												if ssa_2013 {
>													block block_324:
>													/* preds: block_323 */
>													break
>													/* succs: block_345 */
>												} else {
>													block block_325:
>													/* preds: block_323 */
>													/* succs: block_326 */
>												}
>												block block_326:
>												/* preds: block_325 */
>												/* succs: block_327 block_328 */
>												if ssa_1963 {
>													block block_327:
>													/* preds: block_326 */
>													vec1 32 ssa_2014 = fmin ssa_1999, ssa_2006
>													vec1 32 ssa_2015 = fmin ssa_1992, ssa_2014
>													vec1 32 ssa_2016 = fmul ssa_2015, ssa_1946
>													vec1 32 ssa_2017 = flt32 ssa_37, ssa_2016
>													/* succs: block_329 */
>												} else {
>													block block_328:
>													/* preds: block_326 */
>													/* succs: block_329 */
>												}
>												block block_329:
>												/* preds: block_327 block_328 */
>												vec1 32 ssa_2018 = phi block_327: ssa_2017, block_328: ssa_83
>												/* succs: block_330 block_331 */
>												if ssa_2018 {
>													block block_330:
>													/* preds: block_329 */
>													break
>													/* succs: block_345 */
>												} else {
>													block block_331:
>													/* preds: block_329 */
>													/* succs: block_332 */
>												}
>												block block_332:
>												/* preds: block_331 */
>												vec1 32 ssa_2019 = flt32 ssa_1, ssa_1993
>												vec1 32 ssa_2020 = b32csel ssa_2019, ssa_31, ssa_1
>												vec1 32 ssa_2021 = flt32 ssa_1, ssa_2000
>												vec1 32 ssa_2022 = b32csel ssa_2021, ssa_80, ssa_1
>												vec1 32 ssa_2023 = flt32 ssa_1, ssa_2007
>												vec1 32 ssa_2024 = b32csel ssa_2023, ssa_70, ssa_1
>												vec1 32 ssa_2025 = ior ssa_2020, ssa_2022
>												vec1 32 ssa_2026 = ior ssa_2025, ssa_2024
>												vec1 32 ssa_2027 = ushr ssa_81, ssa_2026
>												vec1 32 ssa_2028 = iand ssa_2027, ssa_32
>												vec1 32 ssa_2029 = ine32 ssa_2028, ssa_1
>												/* succs: block_333 block_343 */
>												if ssa_2029 {
>													block block_333:
>													/* preds: block_332 */
>													vec1 32 ssa_2030 = ffma -ssa_33, ssa_1999, ssa_1992
>													vec1 32 ssa_2031 = ffma -ssa_33, ssa_2000, ssa_1993
>													vec1 32 ssa_2032 = fadd ssa_2030, ssa_2006
>													vec1 32 ssa_2033 = fadd ssa_2031, ssa_2007
>													vec1 32 ssa_2034 = fadd ssa_1992, -ssa_1999
>													vec1 32 ssa_2035 = fadd ssa_1993, -ssa_2000
>													vec1 32 ssa_2036 = frcp ssa_2033
>													vec1 32 ssa_2037 = fmul ssa_2033, ssa_1993
>													vec1 32 ssa_2038 = ffma ssa_2035, ssa_2035, -ssa_2037
>													vec1 32 ssa_2039 = fmax ssa_2038, ssa_1
>													vec1 32 ssa_2040 = fsqrt ssa_2039
>													vec1 32 ssa_2041 = fadd ssa_2035, -ssa_2040
>													vec1 32 ssa_2042 = fmul ssa_2041, ssa_2036
>													vec1 32 ssa_2043 = fadd ssa_2035, ssa_2040
>													vec1 32 ssa_2044 = fmul ssa_2043, ssa_2036
>													vec1 32 ssa_2045 = flt32 abs(ssa_2033), ssa_82
>													/* succs: block_334 block_335 */
>													if ssa_2045 {
>														block block_334:
>														/* preds: block_333 */
>														vec1 32 ssa_2046 = fmul ssa_37, ssa_1993
>														vec1 32 ssa_2047 = frcp ssa_2035
>														vec1 32 ssa_2048 = fmul ssa_2046, ssa_2047
>														/* succs: block_336 */
>													} else {
>														block block_335:
>														/* preds: block_333 */
>														/* succs: block_336 */
>													}
>													block block_336:
>													/* preds: block_334 block_335 */
>													vec1 32 ssa_2049 = phi block_334: ssa_2048, block_335: ssa_2044
>													vec1 32 ssa_2050 = phi block_334: ssa_2048, block_335: ssa_2042
>													vec1 32 ssa_2051 = fmul ssa_2034, ssa_33
>													vec1 32 ssa_2052 = ffma ssa_2032, ssa_2050, -ssa_2051
>													vec1 32 ssa_2053 = ffma ssa_2052, ssa_2050, ssa_1992
>													vec1 32 ssa_2054 = ffma ssa_2032, ssa_2049, -ssa_2051
>													vec1 32 ssa_2055 = ffma ssa_2054, ssa_2049, ssa_1992
>													vec1 32 ssa_2056 = fmul ssa_1946, ssa_2053
>													vec1 32 ssa_2057 = fmul ssa_1946, ssa_2055
>													vec1 32 ssa_2058 = iand ssa_2028, ssa_30
>													vec1 32 ssa_2059 = ine32 ssa_2058, ssa_1
>													/* succs: block_337 block_338 */
>													if ssa_2059 {
>														block block_337:
>														/* preds: block_336 */
>														vec1 32 ssa_2060 = ffma.sat ssa_2056, ssa_1964, ssa_37
>														vec1 32 ssa_2061 = fadd ssa_1985, ssa_2060
>														vec1 32 ssa_2062 = fmin ssa_1984, abs(ssa_2056)
>														/* succs: block_339 */
>													} else {
>														block block_338:
>														/* preds: block_336 */
>														/* succs: block_339 */
>													}
>													block block_339:
>													/* preds: block_337 block_338 */
>													vec1 32 ssa_2063 = phi block_337: ssa_2062, block_338: ssa_1984
>													vec1 32 ssa_2064 = phi block_337: ssa_2061, block_338: ssa_1985
>													vec1 32 ssa_2065 = ult32 ssa_30, ssa_2028
>													/* succs: block_340 block_341 */
>													if ssa_2065 {
>														block block_340:
>														/* preds: block_339 */
>														vec1 32 ssa_2066 = ffma.sat ssa_2057, ssa_1964, ssa_37
>														vec1 32 ssa_2067 = fadd ssa_2064, -ssa_2066
>														vec1 32 ssa_2068 = fmin ssa_2063, abs(ssa_2057)
>														/* succs: block_342 */
>													} else {
>														block block_341:
>														/* preds: block_339 */
>														/* succs: block_342 */
>													}
>													block block_342:
>													/* preds: block_340 block_341 */
>													vec1 32 ssa_2069 = phi block_340: ssa_2068, block_341: ssa_2063
>													vec1 32 ssa_2070 = phi block_340: ssa_2067, block_341: ssa_2064
>													/* succs: block_344 */
>												} else {
>													block block_343:
>													/* preds: block_332 */
>													/* succs: block_344 */
>												}
>												block block_344:
>												/* preds: block_342 block_343 */
>												vec1 32 ssa_2071 = phi block_342: ssa_2069, block_343: ssa_1984
>												vec1 32 ssa_2072 = phi block_342: ssa_2070, block_343: ssa_1985
>												vec1 32 ssa_2073 = iadd ssa_1983, ssa_32
>												vec1 32 ssa_2074 = iadd ssa_1986, ssa_30
>												/* succs: block_317 */
>											}
>											block block_345:
>											/* preds: block_318 block_324 block_330 */
>											vec1 32 ssa_2075 = fmov abs(ssa_1985)
>											vec1 32 ssa_2076 = iadd ssa_1980, ssa_1943
>											/* succs: block_346 */
>											loop {
>												block block_346:
>												/* preds: block_345 block_373 */
>												vec1 32 ssa_2077 = phi block_345: ssa_2076, block_373: ssa_2167
>												vec1 32 ssa_2078 = phi block_345: ssa_37, block_373: ssa_2165
>												vec1 32 ssa_2079 = phi block_345: ssa_1, block_373: ssa_2166
>												vec1 32 ssa_2080 = phi block_345: ssa_1, block_373: ssa_2168
>												vec1 32 ssa_2081 = uge32 ssa_2080, ssa_1979
>												/* succs: block_347 block_348 */
>												if ssa_2081 {
>													block block_347:
>													/* preds: block_346 */
>													break
>													/* succs: block_374 */
>												} else {
>													block block_348:
>													/* preds: block_346 */
>													/* succs: block_349 */
>												}
>												block block_349:
>												/* preds: block_348 */
>												vec1 32 ssa_2082 = ishl ssa_2077, ssa_31
>												vec1 32 ssa_2083 = intrinsic load_ssbo (ssa_30, ssa_2082) (0, 4, 0) /* access=0 */ /* align_mul=4 */ /* align_offset=0 */
>												vec1 32 ssa_2084 = unpack_half_2x16_split_x ssa_2083
>												vec1 32 ssa_2085 = unpack_half_2x16_split_y ssa_2083
>												vec1 32 ssa_2086 = fadd ssa_2084, -ssa_5.y
>												vec1 32 ssa_2087 = fadd ssa_2085, -ssa_5.x
>												vec1 32 ssa_2088 = iadd ssa_2077, ssa_30
>												vec1 32 ssa_2089 = ishl ssa_2088, ssa_31
>												vec1 32 ssa_2090 = intrinsic load_ssbo (ssa_30, ssa_2089) (0, 4, 0) /* access=0 */ /* align_mul=4 */ /* align_offset=0 */
>												vec1 32 ssa_2091 = unpack_half_2x16_split_x ssa_2090
>												vec1 32 ssa_2092 = unpack_half_2x16_split_y ssa_2090
>												vec1 32 ssa_2093 = fadd ssa_2091, -ssa_5.y
>												vec1 32 ssa_2094 = fadd ssa_2092, -ssa_5.x
>												vec1 32 ssa_2095 = iadd ssa_2077, ssa_31
>												vec1 32 ssa_2096 = ishl ssa_2095, ssa_31
>												vec1 32 ssa_2097 = intrinsic load_ssbo (ssa_30, ssa_2096) (0, 4, 0) /* access=0 */ /* align_mul=4 */ /* align_offset=0 */
>												vec1 32 ssa_2098 = unpack_half_2x16_split_x ssa_2097
>												vec1 32 ssa_2099 = unpack_half_2x16_split_y ssa_2097
>												vec1 32 ssa_2100 = fadd ssa_2098, -ssa_5.y
>												vec1 32 ssa_2101 = fadd ssa_2099, -ssa_5.x
>												vec1 32 ssa_2102 = fge32 ssa_5.y, ssa_1
>												/* succs: block_350 block_351 */
>												if ssa_2102 {
>													block block_350:
>													/* preds: block_349 */
>													vec1 32 ssa_2103 = fmax ssa_2093, ssa_2100
>													vec1 32 ssa_2104 = fmax ssa_2086, ssa_2103
>													vec1 32 ssa_2105 = fmul ssa_2104, ssa_1947
>													vec1 32 ssa_2106 = flt32 ssa_2105, ssa_63
>													/* succs: block_352 */
>												} else {
>													block block_351:
>													/* preds: block_349 */
>													/* succs: block_352 */
>												}
>												block block_352:
>												/* preds: block_350 block_351 */
>												vec1 32 ssa_2107 = phi block_350: ssa_2106, block_351: ssa_83
>												/* succs: block_353 block_354 */
>												if ssa_2107 {
>													block block_353:
>													/* preds: block_352 */
>													break
>													/* succs: block_374 */
>												} else {
>													block block_354:
>													/* preds: block_352 */
>													/* succs: block_355 */
>												}
>												block block_355:
>												/* preds: block_354 */
>												/* succs: block_356 block_357 */
>												if ssa_1969 {
>													block block_356:
>													/* preds: block_355 */
>													vec1 32 ssa_2108 = fmin ssa_2093, ssa_2100
>													vec1 32 ssa_2109 = fmin ssa_2086, ssa_2108
>													vec1 32 ssa_2110 = fmul ssa_2109, ssa_1947
>													vec1 32 ssa_2111 = flt32 ssa_37, ssa_2110
>													/* succs: block_358 */
>												} else {
>													block block_357:
>													/* preds: block_355 */
>													/* succs: block_358 */
>												}
>												block block_358:
>												/* preds: block_356 block_357 */
>												vec1 32 ssa_2112 = phi block_356: ssa_2111, block_357: ssa_83
>												/* succs: block_359 block_360 */
>												if ssa_2112 {
>													block block_359:
>													/* preds: block_358 */
>													break
>													/* succs: block_374 */
>												} else {
>													block block_360:
>													/* preds: block_358 */
>													/* succs: block_361 */
>												}
>												block block_361:
>												/* preds: block_360 */
>												vec1 32 ssa_2113 = flt32 ssa_1, ssa_2087
>												vec1 32 ssa_2114 = b32csel ssa_2113, ssa_31, ssa_1
>												vec1 32 ssa_2115 = flt32 ssa_1, ssa_2094
>												vec1 32 ssa_2116 = b32csel ssa_2115, ssa_80, ssa_1
>												vec1 32 ssa_2117 = flt32 ssa_1, ssa_2101
>												vec1 32 ssa_2118 = b32csel ssa_2117, ssa_70, ssa_1
>												vec1 32 ssa_2119 = ior ssa_2114, ssa_2116
>												vec1 32 ssa_2120 = ior ssa_2119, ssa_2118
>												vec1 32 ssa_2121 = ushr ssa_81, ssa_2120
>												vec1 32 ssa_2122 = iand ssa_2121, ssa_32
>												vec1 32 ssa_2123 = ine32 ssa_2122, ssa_1
>												/* succs: block_362 block_372 */
>												if ssa_2123 {
>													block block_362:
>													/* preds: block_361 */
>													vec1 32 ssa_2124 = ffma -ssa_33, ssa_2093, ssa_2086
>													vec1 32 ssa_2125 = ffma -ssa_33, ssa_2094, ssa_2087
>													vec1 32 ssa_2126 = fadd ssa_2124, ssa_2100
>													vec1 32 ssa_2127 = fadd ssa_2125, ssa_2101
>													vec1 32 ssa_2128 = fadd ssa_2086, -ssa_2093
>													vec1 32 ssa_2129 = fadd ssa_2087, -ssa_2094
>													vec1 32 ssa_2130 = frcp ssa_2127
>													vec1 32 ssa_2131 = fmul ssa_2127, ssa_2087
>													vec1 32 ssa_2132 = ffma ssa_2129, ssa_2129, -ssa_2131
>													vec1 32 ssa_2133 = fmax ssa_2132, ssa_1
>													vec1 32 ssa_2134 = fsqrt ssa_2133
>													vec1 32 ssa_2135 = fadd ssa_2129, -ssa_2134
>													vec1 32 ssa_2136 = fmul ssa_2135, ssa_2130
>													vec1 32 ssa_2137 = fadd ssa_2129, ssa_2134
>													vec1 32 ssa_2138 = fmul ssa_2137, ssa_2130
>													vec1 32 ssa_2139 = flt32 abs(ssa_2127), ssa_82
>													/* succs: block_363 block_364 */
>													if ssa_2139 {
>														block block_363:
>														/* preds: block_362 */
>														vec1 32 ssa_2140 = fmul ssa_37, ssa_2087
>														vec1 32 ssa_2141 = frcp ssa_2129
>														vec1 32 ssa_2142 = fmul ssa_2140, ssa_2141
>														/* succs: block_365 */
>													} else {
>														block block_364:
>														/* preds: block_362 */
>														/* succs: block_365 */
>													}
>													block block_365:
>													/* preds: block_363 block_364 */
>													vec1 32 ssa_2143 = phi block_363: ssa_2142, block_364: ssa_2138
>													vec1 32 ssa_2144 = phi block_363: ssa_2142, block_364: ssa_2136
>													vec1 32 ssa_2145 = fmul ssa_2128, ssa_33
>													vec1 32 ssa_2146 = ffma ssa_2126, ssa_2144, -ssa_2145
>													vec1 32 ssa_2147 = ffma ssa_2146, ssa_2144, ssa_2086
>													vec1 32 ssa_2148 = ffma ssa_2126, ssa_2143, -ssa_2145
>													vec1 32 ssa_2149 = ffma ssa_2148, ssa_2143, ssa_2086
>													vec1 32 ssa_2150 = fmul ssa_1947, ssa_2147
>													vec1 32 ssa_2151 = fmul ssa_1947, ssa_2149
>													vec1 32 ssa_2152 = iand ssa_2122, ssa_30
>													vec1 32 ssa_2153 = ine32 ssa_2152, ssa_1
>													/* succs: block_366 block_367 */
>													if ssa_2153 {
>														block block_366:
>														/* preds: block_365 */
>														vec1 32 ssa_2154 = ffma.sat ssa_2150, ssa_1970, ssa_37
>														vec1 32 ssa_2155 = fadd ssa_2079, ssa_2154
>														vec1 32 ssa_2156 = fmin ssa_2078, abs(ssa_2150)
>														/* succs: block_368 */
>													} else {
>														block block_367:
>														/* preds: block_365 */
>														/* succs: block_368 */
>													}
>													block block_368:
>													/* preds: block_366 block_367 */
>													vec1 32 ssa_2157 = phi block_366: ssa_2156, block_367: ssa_2078
>													vec1 32 ssa_2158 = phi block_366: ssa_2155, block_367: ssa_2079
>													vec1 32 ssa_2159 = ult32 ssa_30, ssa_2122
>													/* succs: block_369 block_370 */
>													if ssa_2159 {
>														block block_369:
>														/* preds: block_368 */
>														vec1 32 ssa_2160 = ffma.sat ssa_2151, ssa_1970, ssa_37
>														vec1 32 ssa_2161 = fadd ssa_2158, -ssa_2160
>														vec1 32 ssa_2162 = fmin ssa_2157, abs(ssa_2151)
>														/* succs: block_371 */
>													} else {
>														block block_370:
>														/* preds: block_368 */
>														/* succs: block_371 */
>													}
>													block block_371:
>													/* preds: block_369 block_370 */
>													vec1 32 ssa_2163 = phi block_369: ssa_2162, block_370: ssa_2157
>													vec1 32 ssa_2164 = phi block_369: ssa_2161, block_370: ssa_2158
>													/* succs: block_373 */
>												} else {
>													block block_372:
>													/* preds: block_361 */
>													/* succs: block_373 */
>												}
>												block block_373:
>												/* preds: block_371 block_372 */
>												vec1 32 ssa_2165 = phi block_371: ssa_2163, block_372: ssa_2078
>												vec1 32 ssa_2166 = phi block_371: ssa_2164, block_372: ssa_2079
>												vec1 32 ssa_2167 = iadd ssa_2077, ssa_32
>												vec1 32 ssa_2168 = iadd ssa_2080, ssa_30
>												/* succs: block_346 */
>											}
>											block block_374:
>											/* preds: block_347 block_353 block_359 */
>											vec1 32 ssa_2169 = fmov abs(ssa_2079)
>											/* succs: block_375 block_376 */
>											if ssa_1945 {
>												block block_375:
>												/* preds: block_374 */
>												vec1 32 ssa_2170 = fmul ssa_37, abs(ssa_1985)
>												vec1 32 ssa_2171 = fmul ssa_37, abs(ssa_2079)
>												vec1 32 ssa_2172 = ffract ssa_2170
>												vec1 32 ssa_2173 = ffract ssa_2171
>												vec1 32 ssa_2174 = fmul ssa_33, ssa_2172
>												vec1 32 ssa_2175 = fmul ssa_33, ssa_2173
>												/* succs: block_377 */
>											} else {
>												block block_376:
>												/* preds: block_374 */
>												/* succs: block_377 */
>											}
>											block block_377:
>											/* preds: block_375 block_376 */
>											vec1 32 ssa_2176 = phi block_375: ssa_2174, block_376: ssa_2075
>											vec1 32 ssa_2177 = phi block_375: ssa_2175, block_376: ssa_2169
>											vec1 32 ssa_2178 = fmin.sat abs(ssa_1984), ssa_37
>											vec1 32 ssa_2179 = fmin.sat abs(ssa_2078), ssa_37
>											vec1 32 ssa_2180 = ffma -ssa_33, ssa_2178, ssa_35
>											vec1 32 ssa_2181 = ffma -ssa_33, ssa_2179, ssa_35
>											vec1 32 ssa_2182 = fadd ssa_2180, ssa_2181
>											vec1 32 ssa_2183 = flt32 ssa_85, ssa_2182
>											/* succs: block_378 block_379 */
>											if ssa_2183 {
>												block block_378:
>												/* preds: block_377 */
>												vec1 32 ssa_2184 = fmul ssa_2177, ssa_2181
>												vec1 32 ssa_2185 = ffma ssa_2176, ssa_2180, ssa_2184
>												vec1 32 ssa_2186 = frcp ssa_2182
>												vec1 32 ssa_2187 = fmul ssa_2185, ssa_2186
>												/* succs: block_380 */
>											} else {
>												block block_379:
>												/* preds: block_377 */
>												vec1 32 ssa_2188 = fadd ssa_2176, ssa_2177
>												vec1 32 ssa_2189 = fmul ssa_37, ssa_2188
>												/* succs: block_380 */
>											}
>											block block_380:
>											/* preds: block_378 block_379 */
>											vec1 32 ssa_2190 = phi block_378: ssa_2187, block_379: ssa_2189
>											vec1 32 ssa_2191 = iand ssa_1942.x, ssa_33
>											vec1 32 ssa_2192 = ine32 ssa_2191, ssa_1
>											/* succs: block_381 block_382 */
>											if ssa_2192 {
>												block block_381:
>												/* preds: block_380 */
>												vec1 32 ssa_2193 = fadd ssa_35, -ssa_2190
>												/* succs: block_383 */
>											} else {
>												block block_382:
>												/* preds: block_380 */
>												/* succs: block_383 */
>											}
>											block block_383:
>											/* preds: block_381 block_382 */
>											vec1 32 ssa_2194 = phi block_381: ssa_2193, block_382: ssa_2190
>											/* succs: block_385 */
>										} else {
>											block block_384:
>											/* preds: block_315 */
>											/* succs: block_385 */
>										}
>										block block_385:
>										/* preds: block_383 block_384 */
>										vec1 32 ssa_2195 = phi block_383: ssa_2194, block_384: ssa_17
>										vec1 32 ssa_2196 = phi block_383: ssa_2194, block_384: ssa_16
>										vec1 32 ssa_2197 = phi block_383: ssa_2194, block_384: ssa_15
>										vec1 32 ssa_2198 = phi block_383: ssa_2194, block_384: ssa_14
>										/* succs: block_386 */
>									}
>									block block_386:
>									/* preds: block_314 block_385 */
>									vec1 32 ssa_2199 = phi block_314: ssa_1931, block_385: ssa_2195
>									vec1 32 ssa_2200 = phi block_314: ssa_1931, block_385: ssa_2196
>									vec1 32 ssa_2201 = phi block_314: ssa_1931, block_385: ssa_2197
>									vec1 32 ssa_2202 = phi block_314: ssa_1931, block_385: ssa_2198
>									/* succs: block_387 */
>								}
>								block block_387:
>								/* preds: block_194 block_386 */
>								vec1 32 ssa_2203 = phi block_194: ssa_1436, block_386: ssa_2199
>								vec1 32 ssa_2204 = phi block_194: ssa_1436, block_386: ssa_2200
>								vec1 32 ssa_2205 = phi block_194: ssa_1436, block_386: ssa_2201
>								vec1 32 ssa_2206 = phi block_194: ssa_1436, block_386: ssa_2202
>								/* succs: block_388 */
>							}
>							block block_388:
>							/* preds: block_168 block_387 */
>							vec1 32 ssa_2207 = phi block_168: ssa_1298, block_387: ssa_2203
>							vec1 32 ssa_2208 = phi block_168: ssa_1298, block_387: ssa_2204
>							vec1 32 ssa_2209 = phi block_168: ssa_1298, block_387: ssa_2205
>							vec1 32 ssa_2210 = phi block_168: ssa_1298, block_387: ssa_2206
>							/* succs: block_389 */
>						}
>						block block_389:
>						/* preds: block_142 block_388 */
>						vec1 32 ssa_2211 = phi block_142: ssa_1168, block_388: ssa_2207
>						vec1 32 ssa_2212 = phi block_142: ssa_1168, block_388: ssa_2208
>						vec1 32 ssa_2213 = phi block_142: ssa_1168, block_388: ssa_2209
>						vec1 32 ssa_2214 = phi block_142: ssa_1168, block_388: ssa_2210
>						/* succs: block_391 */
>					} else {
>						block block_390:
>						/* preds: block_140 */
>						/* succs: block_391 */
>					}
>					block block_391:
>					/* preds: block_389 block_390 */
>					vec1 32 ssa_2215 = phi block_390: ssa_35, block_389: ssa_2211
>					vec1 32 ssa_2216 = phi block_390: ssa_35, block_389: ssa_2212
>					vec1 32 ssa_2217 = phi block_390: ssa_35, block_389: ssa_2213
>					vec1 32 ssa_2218 = phi block_390: ssa_35, block_389: ssa_2214
>					/* succs: block_393 */
>				} else {
>					block block_392:
>					/* preds: block_139 */
>					/* succs: block_393 */
>				}
>				block block_393:
>				/* preds: block_391 block_392 */
>				vec1 32 ssa_2219 = phi block_392: ssa_35, block_391: ssa_2215
>				vec1 32 ssa_2220 = phi block_392: ssa_35, block_391: ssa_2216
>				vec1 32 ssa_2221 = phi block_392: ssa_35, block_391: ssa_2217
>				vec1 32 ssa_2222 = phi block_392: ssa_35, block_391: ssa_2218
>				/* succs: block_394 */
>			}
>			block block_394:
>			/* preds: block_138 block_393 */
>			vec1 32 ssa_2223 = phi block_138: ssa_1153, block_393: ssa_2219
>			vec1 32 ssa_2224 = phi block_138: ssa_1153, block_393: ssa_2220
>			vec1 32 ssa_2225 = phi block_138: ssa_1153, block_393: ssa_2221
>			vec1 32 ssa_2226 = phi block_138: ssa_1153, block_393: ssa_2222
>			/* succs: block_395 */
>		}
>		block block_395:
>		/* preds: block_136 block_394 */
>		vec1 32 ssa_2227 = phi block_136: ssa_1138, block_394: ssa_2223
>		vec1 32 ssa_2228 = phi block_136: ssa_1138, block_394: ssa_2224
>		vec1 32 ssa_2229 = phi block_136: ssa_1138, block_394: ssa_2225
>		vec1 32 ssa_2230 = phi block_136: ssa_1138, block_394: ssa_2226
>		vec1 32 ssa_2231 = fmul ssa_1119, ssa_2227
>		vec1 32 ssa_2232 = fmul ssa_1120, ssa_2228
>		vec1 32 ssa_2233 = fmul ssa_1121, ssa_2229
>		vec1 32 ssa_2234 = fmul ssa_1122, ssa_2230
>		/* succs: block_397 */
>	} else {
>		block block_396:
>		/* preds: block_0 */
>		/* succs: block_397 */
>	}
>	block block_397:
>	/* preds: block_395 block_396 */
>	vec1 32 ssa_2235 = phi block_395: ssa_2231, block_396: ssa_1
>	vec1 32 ssa_2236 = phi block_395: ssa_2232, block_396: ssa_1
>	vec1 32 ssa_2237 = phi block_395: ssa_2233, block_396: ssa_1
>	vec1 32 ssa_2238 = phi block_395: ssa_2234, block_396: ssa_1
>	vec1 32 ssa_2239 = intrinsic load_input (ssa_1) (32, 3) /* base=32 */ /* component=3 */	/* fastuidraw_uint_varying1 */
>	vec1 32 ssa_2240 = ine32 ssa_2239, ssa_30
>	/* succs: block_398 block_441 */
>	if ssa_2240 {
>		block block_398:
>		/* preds: block_397 */
>		vec1 32 ssa_2241 = ine32 ssa_2239, ssa_31
>		/* succs: block_399 block_439 */
>		if ssa_2241 {
>			block block_399:
>			/* preds: block_398 */
>			vec1 32 ssa_2242 = ine32 ssa_2239, ssa_32
>			/* succs: block_400 block_437 */
>			if ssa_2242 {
>				block block_400:
>				/* preds: block_399 */
>				vec1 32 ssa_2243 = ieq32 ssa_2239, ssa_80
>				/* succs: block_401 block_402 */
>				if ssa_2243 {
>					block block_401:
>					/* preds: block_400 */
>					vec1 32 ssa_2244 = fadd ssa_35, -ssa_2238
>					/* succs: block_436 */
>				} else {
>					block block_402:
>					/* preds: block_400 */
>					vec1 32 ssa_2245 = ine32 ssa_2239, ssa_86
>					/* succs: block_403 block_434 */
>					if ssa_2245 {
>						block block_403:
>						/* preds: block_402 */
>						vec1 32 ssa_2246 = ine32 ssa_2239, ssa_67
>						/* succs: block_404 block_432 */
>						if ssa_2246 {
>							block block_404:
>							/* preds: block_403 */
>							vec1 32 ssa_2247 = ine32 ssa_2239, ssa_87
>							/* succs: block_405 block_430 */
>							if ssa_2247 {
>								block block_405:
>								/* preds: block_404 */
>								vec1 32 ssa_2248 = ine32 ssa_2239, ssa_70
>								/* succs: block_406 block_428 */
>								if ssa_2248 {
>									block block_406:
>									/* preds: block_405 */
>									vec1 32 ssa_2249 = ieq32 ssa_2239, ssa_88
>									/* succs: block_407 block_408 */
>									if ssa_2249 {
>										block block_407:
>										/* preds: block_406 */
>										vec1 32 ssa_2250 = fadd ssa_35, -ssa_2238
>										/* succs: block_427 */
>									} else {
>										block block_408:
>										/* preds: block_406 */
>										vec1 32 ssa_2251 = ieq32 ssa_2239, ssa_52
>										/* succs: block_409 block_410 */
>										if ssa_2251 {
>											block block_409:
>											/* preds: block_408 */
>											vec1 32 ssa_2252 = fadd ssa_35, -ssa_2238
>											/* succs: block_426 */
>										} else {
>											block block_410:
>											/* preds: block_408 */
>											vec1 32 ssa_2253 = ine32 ssa_2239, ssa_89
>											/* succs: block_411 block_424 */
>											if ssa_2253 {
>												block block_411:
>												/* preds: block_410 */
>												vec1 32 ssa_2254 = ieq32 ssa_2239, ssa_90
>												/* succs: block_412 block_413 */
>												if ssa_2254 {
>													block block_412:
>													/* preds: block_411 */
>													vec1 32 ssa_2255 = fadd ssa_35, -ssa_2238
>													/* succs: block_423 */
>												} else {
>													block block_413:
>													/* preds: block_411 */
>													vec1 32 ssa_2256 = ine32 ssa_2239, ssa_91
>													/* succs: block_414 block_421 */
>													if ssa_2256 {
>														block block_414:
>														/* preds: block_413 */
>														vec1 32 ssa_2257 = ine32 ssa_2239, ssa_29
>														/* succs: block_415 block_419 */
>														if ssa_2257 {
>															block block_415:
>															/* preds: block_414 */
>															vec1 32 ssa_2258 = ieq32 ssa_2239, ssa_76
>															/* succs: block_416 block_417 */
>															if ssa_2258 {
>																block block_416:
>																/* preds: block_415 */
>																vec1 32 ssa_2259 = fadd ssa_35, -ssa_2235
>																vec1 32 ssa_2260 = fadd ssa_35, -ssa_2236
>																vec1 32 ssa_2261 = fadd ssa_35, -ssa_2237
>																vec1 32 ssa_2262 = fadd ssa_35, -ssa_2238
>																/* succs: block_418 */
>															} else {
>																block block_417:
>																/* preds: block_415 */
>																/* succs: block_418 */
>															}
>															block block_418:
>															/* preds: block_416 block_417 */
>															vec1 32 ssa_2263 = phi block_416: ssa_2259, block_417: ssa_13
>															vec1 32 ssa_2264 = phi block_416: ssa_2260, block_417: ssa_12
>															vec1 32 ssa_2265 = phi block_416: ssa_2261, block_417: ssa_11
>															vec1 32 ssa_2266 = phi block_416: ssa_2262, block_417: ssa_10
>															vec1 32 ssa_2267 = phi block_416: ssa_2235, block_417: ssa_9
>															vec1 32 ssa_2268 = phi block_416: ssa_2236, block_417: ssa_8
>															vec1 32 ssa_2269 = phi block_416: ssa_2237, block_417: ssa_7
>															vec1 32 ssa_2270 = phi block_416: ssa_2238, block_417: ssa_6
>															/* succs: block_420 */
>														} else {
>															block block_419:
>															/* preds: block_414 */
>															/* succs: block_420 */
>														}
>														block block_420:
>														/* preds: block_418 block_419 */
>														vec1 32 ssa_2271 = phi block_419: ssa_2235, block_418: ssa_2263
>														vec1 32 ssa_2272 = phi block_419: ssa_2236, block_418: ssa_2264
>														vec1 32 ssa_2273 = phi block_419: ssa_2237, block_418: ssa_2265
>														vec1 32 ssa_2274 = phi block_419: ssa_2238, block_418: ssa_2266
>														vec1 32 ssa_2275 = phi block_419: ssa_1, block_418: ssa_2267
>														vec1 32 ssa_2276 = phi block_419: ssa_1, block_418: ssa_2268
>														vec1 32 ssa_2277 = phi block_419: ssa_1, block_418: ssa_2269
>														vec1 32 ssa_2278 = phi block_419: ssa_1, block_418: ssa_2270
>														/* succs: block_422 */
>													} else {
>														block block_421:
>														/* preds: block_413 */
>														/* succs: block_422 */
>													}
>													block block_422:
>													/* preds: block_420 block_421 */
>													vec1 32 ssa_2279 = phi block_421: ssa_35, block_420: ssa_2271
>													vec1 32 ssa_2280 = phi block_421: ssa_35, block_420: ssa_2272
>													vec1 32 ssa_2281 = phi block_421: ssa_35, block_420: ssa_2273
>													vec1 32 ssa_2282 = phi block_421: ssa_35, block_420: ssa_2274
>													vec1 32 ssa_2283 = phi block_421: ssa_2235, block_420: ssa_2275
>													vec1 32 ssa_2284 = phi block_421: ssa_2236, block_420: ssa_2276
>													vec1 32 ssa_2285 = phi block_421: ssa_2237, block_420: ssa_2277
>													vec1 32 ssa_2286 = phi block_421: ssa_2238, block_420: ssa_2278
>													/* succs: block_423 */
>												}
>												block block_423:
>												/* preds: block_412 block_422 */
>												vec1 32 ssa_2287 = phi block_412: ssa_2255, block_422: ssa_2279
>												vec1 32 ssa_2288 = phi block_412: ssa_2255, block_422: ssa_2280
>												vec1 32 ssa_2289 = phi block_412: ssa_2255, block_422: ssa_2281
>												vec1 32 ssa_2290 = phi block_412: ssa_2255, block_422: ssa_2282
>												vec1 32 ssa_2291 = phi block_412: ssa_2235, block_422: ssa_2283
>												vec1 32 ssa_2292 = phi block_412: ssa_2236, block_422: ssa_2284
>												vec1 32 ssa_2293 = phi block_412: ssa_2237, block_422: ssa_2285
>												vec1 32 ssa_2294 = phi block_412: ssa_2238, block_422: ssa_2286
>												/* succs: block_425 */
>											} else {
>												block block_424:
>												/* preds: block_410 */
>												/* succs: block_425 */
>											}
>											block block_425:
>											/* preds: block_423 block_424 */
>											vec1 32 ssa_2295 = phi block_424: ssa_2238, block_423: ssa_2287
>											vec1 32 ssa_2296 = phi block_424: ssa_2238, block_423: ssa_2288
>											vec1 32 ssa_2297 = phi block_424: ssa_2238, block_423: ssa_2289
>											vec1 32 ssa_2298 = phi block_424: ssa_2238, block_423: ssa_2290
>											vec1 32 ssa_2299 = phi block_424: ssa_2235, block_423: ssa_2291
>											vec1 32 ssa_2300 = phi block_424: ssa_2236, block_423: ssa_2292
>											vec1 32 ssa_2301 = phi block_424: ssa_2237, block_423: ssa_2293
>											vec1 32 ssa_2302 = phi block_424: ssa_2238, block_423: ssa_2294
>											/* succs: block_426 */
>										}
>										block block_426:
>										/* preds: block_409 block_425 */
>										vec1 32 ssa_2303 = phi block_409: ssa_2252, block_425: ssa_2295
>										vec1 32 ssa_2304 = phi block_409: ssa_2252, block_425: ssa_2296
>										vec1 32 ssa_2305 = phi block_409: ssa_2252, block_425: ssa_2297
>										vec1 32 ssa_2306 = phi block_409: ssa_2252, block_425: ssa_2298
>										vec1 32 ssa_2307 = phi block_409: ssa_2235, block_425: ssa_2299
>										vec1 32 ssa_2308 = phi block_409: ssa_2236, block_425: ssa_2300
>										vec1 32 ssa_2309 = phi block_409: ssa_2237, block_425: ssa_2301
>										vec1 32 ssa_2310 = phi block_409: ssa_2238, block_425: ssa_2302
>										/* succs: block_427 */
>									}
>									block block_427:
>									/* preds: block_407 block_426 */
>									vec1 32 ssa_2311 = phi block_407: ssa_2250, block_426: ssa_2303
>									vec1 32 ssa_2312 = phi block_407: ssa_2250, block_426: ssa_2304
>									vec1 32 ssa_2313 = phi block_407: ssa_2250, block_426: ssa_2305
>									vec1 32 ssa_2314 = phi block_407: ssa_2250, block_426: ssa_2306
>									vec1 32 ssa_2315 = phi block_407: ssa_1, block_426: ssa_2307
>									vec1 32 ssa_2316 = phi block_407: ssa_1, block_426: ssa_2308
>									vec1 32 ssa_2317 = phi block_407: ssa_1, block_426: ssa_2309
>									vec1 32 ssa_2318 = phi block_407: ssa_1, block_426: ssa_2310
>									/* succs: block_429 */
>								} else {
>									block block_428:
>									/* preds: block_405 */
>									/* succs: block_429 */
>								}
>								block block_429:
>								/* preds: block_427 block_428 */
>								vec1 32 ssa_2319 = phi block_428: ssa_1, block_427: ssa_2311
>								vec1 32 ssa_2320 = phi block_428: ssa_1, block_427: ssa_2312
>								vec1 32 ssa_2321 = phi block_428: ssa_1, block_427: ssa_2313
>								vec1 32 ssa_2322 = phi block_428: ssa_1, block_427: ssa_2314
>								vec1 32 ssa_2323 = phi block_428: ssa_2235, block_427: ssa_2315
>								vec1 32 ssa_2324 = phi block_428: ssa_2236, block_427: ssa_2316
>								vec1 32 ssa_2325 = phi block_428: ssa_2237, block_427: ssa_2317
>								vec1 32 ssa_2326 = phi block_428: ssa_2238, block_427: ssa_2318
>								/* succs: block_431 */
>							} else {
>								block block_430:
>								/* preds: block_404 */
>								/* succs: block_431 */
>							}
>							block block_431:
>							/* preds: block_429 block_430 */
>							vec1 32 ssa_2327 = phi block_430: ssa_2238, block_429: ssa_2319
>							vec1 32 ssa_2328 = phi block_430: ssa_2238, block_429: ssa_2320
>							vec1 32 ssa_2329 = phi block_430: ssa_2238, block_429: ssa_2321
>							vec1 32 ssa_2330 = phi block_430: ssa_2238, block_429: ssa_2322
>							vec1 32 ssa_2331 = phi block_430: ssa_1, block_429: ssa_2323
>							vec1 32 ssa_2332 = phi block_430: ssa_1, block_429: ssa_2324
>							vec1 32 ssa_2333 = phi block_430: ssa_1, block_429: ssa_2325
>							vec1 32 ssa_2334 = phi block_430: ssa_1, block_429: ssa_2326
>							/* succs: block_433 */
>						} else {
>							block block_432:
>							/* preds: block_403 */
>							/* succs: block_433 */
>						}
>						block block_433:
>						/* preds: block_431 block_432 */
>						vec1 32 ssa_2335 = phi block_432: ssa_1, block_431: ssa_2327
>						vec1 32 ssa_2336 = phi block_432: ssa_1, block_431: ssa_2328
>						vec1 32 ssa_2337 = phi block_432: ssa_1, block_431: ssa_2329
>						vec1 32 ssa_2338 = phi block_432: ssa_1, block_431: ssa_2330
>						vec1 32 ssa_2339 = phi block_432: ssa_2235, block_431: ssa_2331
>						vec1 32 ssa_2340 = phi block_432: ssa_2236, block_431: ssa_2332
>						vec1 32 ssa_2341 = phi block_432: ssa_2237, block_431: ssa_2333
>						vec1 32 ssa_2342 = phi block_432: ssa_2238, block_431: ssa_2334
>						/* succs: block_435 */
>					} else {
>						block block_434:
>						/* preds: block_402 */
>						/* succs: block_435 */
>					}
>					block block_435:
>					/* preds: block_433 block_434 */
>					vec1 32 ssa_2343 = phi block_434: ssa_35, block_433: ssa_2335
>					vec1 32 ssa_2344 = phi block_434: ssa_35, block_433: ssa_2336
>					vec1 32 ssa_2345 = phi block_434: ssa_35, block_433: ssa_2337
>					vec1 32 ssa_2346 = phi block_434: ssa_35, block_433: ssa_2338
>					vec1 32 ssa_2347 = phi block_434: ssa_2235, block_433: ssa_2339
>					vec1 32 ssa_2348 = phi block_434: ssa_2236, block_433: ssa_2340
>					vec1 32 ssa_2349 = phi block_434: ssa_2237, block_433: ssa_2341
>					vec1 32 ssa_2350 = phi block_434: ssa_2238, block_433: ssa_2342
>					/* succs: block_436 */
>				}
>				block block_436:
>				/* preds: block_401 block_435 */
>				vec1 32 ssa_2351 = phi block_401: ssa_2244, block_435: ssa_2343
>				vec1 32 ssa_2352 = phi block_401: ssa_2244, block_435: ssa_2344
>				vec1 32 ssa_2353 = phi block_401: ssa_2244, block_435: ssa_2345
>				vec1 32 ssa_2354 = phi block_401: ssa_2244, block_435: ssa_2346
>				vec1 32 ssa_2355 = phi block_401: ssa_2235, block_435: ssa_2347
>				vec1 32 ssa_2356 = phi block_401: ssa_2236, block_435: ssa_2348
>				vec1 32 ssa_2357 = phi block_401: ssa_2237, block_435: ssa_2349
>				vec1 32 ssa_2358 = phi block_401: ssa_2238, block_435: ssa_2350
>				/* succs: block_438 */
>			} else {
>				block block_437:
>				/* preds: block_399 */
>				/* succs: block_438 */
>			}
>			block block_438:
>			/* preds: block_436 block_437 */
>			vec1 32 ssa_2359 = phi block_437: ssa_35, block_436: ssa_2351
>			vec1 32 ssa_2360 = phi block_437: ssa_35, block_436: ssa_2352
>			vec1 32 ssa_2361 = phi block_437: ssa_35, block_436: ssa_2353
>			vec1 32 ssa_2362 = phi block_437: ssa_35, block_436: ssa_2354
>			vec1 32 ssa_2363 = phi block_437: ssa_1, block_436: ssa_2355
>			vec1 32 ssa_2364 = phi block_437: ssa_1, block_436: ssa_2356
>			vec1 32 ssa_2365 = phi block_437: ssa_1, block_436: ssa_2357
>			vec1 32 ssa_2366 = phi block_437: ssa_1, block_436: ssa_2358
>			/* succs: block_440 */
>		} else {
>			block block_439:
>			/* preds: block_398 */
>			/* succs: block_440 */
>		}
>		block block_440:
>		/* preds: block_438 block_439 */
>		vec1 32 ssa_2367 = phi block_439: ssa_1, block_438: ssa_2359
>		vec1 32 ssa_2368 = phi block_439: ssa_1, block_438: ssa_2360
>		vec1 32 ssa_2369 = phi block_439: ssa_1, block_438: ssa_2361
>		vec1 32 ssa_2370 = phi block_439: ssa_1, block_438: ssa_2362
>		vec1 32 ssa_2371 = phi block_439: ssa_2235, block_438: ssa_2363
>		vec1 32 ssa_2372 = phi block_439: ssa_2236, block_438: ssa_2364
>		vec1 32 ssa_2373 = phi block_439: ssa_2237, block_438: ssa_2365
>		vec1 32 ssa_2374 = phi block_439: ssa_2238, block_438: ssa_2366
>		/* succs: block_442 */
>	} else {
>		block block_441:
>		/* preds: block_397 */
>		/* succs: block_442 */
>	}
>	block block_442:
>	/* preds: block_440 block_441 */
>	vec1 32 ssa_2375 = phi block_441: ssa_1, block_440: ssa_2367
>	vec1 32 ssa_2376 = phi block_441: ssa_1, block_440: ssa_2368
>	vec1 32 ssa_2377 = phi block_441: ssa_1, block_440: ssa_2369
>	vec1 32 ssa_2378 = phi block_441: ssa_1, block_440: ssa_2370
>	vec1 32 ssa_2379 = phi block_441: ssa_1, block_440: ssa_2371
>	vec1 32 ssa_2380 = phi block_441: ssa_1, block_440: ssa_2372
>	vec1 32 ssa_2381 = phi block_441: ssa_1, block_440: ssa_2373
>	vec1 32 ssa_2382 = phi block_441: ssa_1, block_440: ssa_2374
>	vec4 32 ssa_2383 = vec4 ssa_2379, ssa_2380, ssa_2381, ssa_2382
>	vec4 32 ssa_2384 = vec4 ssa_2375, ssa_2376, ssa_2377, ssa_2378
>	intrinsic store_output (ssa_2383, ssa_1) (8, 15, 0) /* base=8 */ /* wrmask=xyzw */ /* component=0 */	/* fastuidraw_final_color0 */
>	intrinsic store_output (ssa_2384, ssa_1) (9, 15, 0) /* base=9 */ /* wrmask=xyzw */ /* component=0 */	/* fastuidraw_final_color1 */
>	/* succs: block_443 */
>	block block_443:
>}
>
>NIR (final form) for fragment shader:
>shader: MESA_SHADER_FRAGMENT
>name: GLSL1
>inputs: 0
>outputs: 0
>uniforms: 16
>shared: 0
>decl_var ssbo INTERP_MODE_NONE restrict readonly uvec4[] fastuidraw_painterStore (0, 0, 0)
>decl_var ssbo INTERP_MODE_NONE restrict readonly uint[] fastuidraw_glyphDataStore_data (0, 0, 1)
>decl_var ubo INTERP_MODE_NONE vec4[2] fastuidraw_uniforms (0, 0, 0)
>decl_var uniform INTERP_MODE_NONE sampler1DArray fastuidraw_colorStopAtlas (3, 0, 0)
>decl_var uniform INTERP_MODE_NONE sampler2DArray fastuidraw_imageAtlasLinear (4, 0, 1)
>decl_var uniform INTERP_MODE_NONE sampler2DArray fastuidraw_imageAtlasNearest (5, 0, 2)
>decl_var uniform INTERP_MODE_NONE usampler2DArray fastuidraw_imageIndexAtlas (6, 0, 3)
>decl_var uniform INTERP_MODE_NONE sampler2D[8] fastuidraw_external_texture (7, 0, 4)
>decl_var uniform INTERP_MODE_NONE sampler2D fastuidraw_deferred_coverage_buffer (8, 0, 12)
>decl_var uniform INTERP_MODE_NONE vec4 gl_FbWposYTransform (0, 0, 0)
>decl_var shader_in INTERP_MODE_SMOOTH vec4 gl_FragCoord (VARYING_SLOT_POS, 0, 0)
>decl_var shader_in INTERP_MODE_SMOOTH float fastuidraw_float_smooth_varying2 (VARYING_SLOT_VAR5.x, 36, 0)
>decl_var shader_in INTERP_MODE_FLAT uint fastuidraw_uint_varying2 (VARYING_SLOT_VAR2.x, 33, 0)
>decl_var shader_in INTERP_MODE_FLAT uint fastuidraw_uint_varying2@0 (VARYING_SLOT_VAR2.y, 33, 0)
>decl_var shader_in INTERP_MODE_FLAT uint fastuidraw_uint_varying2@1 (VARYING_SLOT_VAR2.w, 33, 0)
>decl_var shader_in INTERP_MODE_FLAT float fastuidraw_float_flat_varying4 (VARYING_SLOT_VAR10.x, 41, 0)
>decl_var shader_in INTERP_MODE_FLAT float fastuidraw_float_flat_varying4@2 (VARYING_SLOT_VAR10.y, 41, 0)
>decl_var shader_in INTERP_MODE_FLAT float fastuidraw_float_flat_varying4@3 (VARYING_SLOT_VAR10.z, 41, 0)
>decl_var shader_in INTERP_MODE_FLAT float fastuidraw_float_flat_varying4@4 (VARYING_SLOT_VAR10.w, 41, 0)
>decl_var shader_in INTERP_MODE_FLAT float fastuidraw_float_flat_varying5 (VARYING_SLOT_VAR11.x, 42, 0)
>decl_var shader_in INTERP_MODE_FLAT float fastuidraw_float_flat_varying5@5 (VARYING_SLOT_VAR11.y, 42, 0)
>decl_var shader_in INTERP_MODE_FLAT float fastuidraw_float_flat_varying5@6 (VARYING_SLOT_VAR11.z, 42, 0)
>decl_var shader_in INTERP_MODE_SMOOTH float fastuidraw_float_smooth_varying1 (VARYING_SLOT_VAR4.w, 35, 0)
>decl_var shader_in INTERP_MODE_FLAT float fastuidraw_float_flat_varying0 (VARYING_SLOT_VAR6.x, 37, 0)
>decl_var shader_in INTERP_MODE_FLAT float fastuidraw_float_flat_varying0@7 (VARYING_SLOT_VAR6.y, 37, 0)
>decl_var shader_in INTERP_MODE_FLAT float fastuidraw_float_flat_varying0@8 (VARYING_SLOT_VAR6.z, 37, 0)
>decl_var shader_in INTERP_MODE_FLAT float fastuidraw_float_flat_varying0@9 (VARYING_SLOT_VAR6.w, 37, 0)
>decl_var shader_in INTERP_MODE_FLAT float fastuidraw_float_flat_varying1 (VARYING_SLOT_VAR7.x, 38, 0)
>decl_var shader_in INTERP_MODE_FLAT float fastuidraw_float_flat_varying1@10 (VARYING_SLOT_VAR7.y, 38, 0)
>decl_var shader_in INTERP_MODE_FLAT float fastuidraw_float_flat_varying1@11 (VARYING_SLOT_VAR7.z, 38, 0)
>decl_var shader_in INTERP_MODE_FLAT float fastuidraw_float_flat_varying1@12 (VARYING_SLOT_VAR7.w, 38, 0)
>decl_var shader_in INTERP_MODE_FLAT float fastuidraw_float_flat_varying2 (VARYING_SLOT_VAR8.x, 39, 0)
>decl_var shader_in INTERP_MODE_FLAT float fastuidraw_float_flat_varying2@13 (VARYING_SLOT_VAR8.y, 39, 0)
>decl_var shader_in INTERP_MODE_FLAT float fastuidraw_float_flat_varying2@14 (VARYING_SLOT_VAR8.z, 39, 0)
>decl_var shader_in INTERP_MODE_FLAT float fastuidraw_float_flat_varying2@15 (VARYING_SLOT_VAR8.w, 39, 0)
>decl_var shader_in INTERP_MODE_FLAT float fastuidraw_float_flat_varying3 (VARYING_SLOT_VAR9.x, 40, 0)
>decl_var shader_in INTERP_MODE_FLAT float fastuidraw_float_flat_varying3@16 (VARYING_SLOT_VAR9.y, 40, 0)
>decl_var shader_in INTERP_MODE_FLAT float fastuidraw_float_flat_varying3@17 (VARYING_SLOT_VAR9.z, 40, 0)
>decl_var shader_in INTERP_MODE_FLAT float fastuidraw_float_flat_varying3@18 (VARYING_SLOT_VAR9.w, 40, 0)
>decl_var shader_in INTERP_MODE_FLAT uint fastuidraw_uint_varying0 (VARYING_SLOT_VAR0.x, 31, 0)
>decl_var shader_in INTERP_MODE_FLAT uint fastuidraw_uint_varying0@19 (VARYING_SLOT_VAR0.y, 31, 0)
>decl_var shader_in INTERP_MODE_FLAT uint fastuidraw_uint_varying0@20 (VARYING_SLOT_VAR0.z, 31, 0)
>decl_var shader_in INTERP_MODE_FLAT uint fastuidraw_uint_varying0@21 (VARYING_SLOT_VAR0.w, 31, 0)
>decl_var shader_in INTERP_MODE_FLAT uint fastuidraw_uint_varying1 (VARYING_SLOT_VAR1.x, 32, 0)
>decl_var shader_in INTERP_MODE_FLAT uint fastuidraw_uint_varying1@22 (VARYING_SLOT_VAR1.y, 32, 0)
>decl_var shader_in INTERP_MODE_FLAT uint fastuidraw_uint_varying1@23 (VARYING_SLOT_VAR1.w, 32, 0)
>decl_var shader_in INTERP_MODE_SMOOTH float fastuidraw_float_smooth_varying0 (VARYING_SLOT_VAR3.x, 34, 0)
>decl_var shader_in INTERP_MODE_SMOOTH float fastuidraw_float_smooth_varying0@24 (VARYING_SLOT_VAR3.y, 34, 0)
>decl_var shader_in INTERP_MODE_SMOOTH float fastuidraw_float_smooth_varying0@25 (VARYING_SLOT_VAR3.z, 34, 0)
>decl_var shader_in INTERP_MODE_SMOOTH float fastuidraw_float_smooth_varying0@26 (VARYING_SLOT_VAR3.w, 34, 0)
>decl_var shader_in INTERP_MODE_FLAT uvec4 fastuidraw_uint_varying0@27 (VARYING_SLOT_VAR0, 31, 0)
>decl_var shader_in INTERP_MODE_FLAT uvec2 fastuidraw_uint_varying1@28 (VARYING_SLOT_VAR1.xy, 32, 0)
>decl_var shader_in INTERP_MODE_FLAT uvec2 fastuidraw_uint_varying2@29 (VARYING_SLOT_VAR2.xy, 33, 0)
>decl_var shader_in INTERP_MODE_SMOOTH vec4 fastuidraw_float_smooth_varying0@30 (VARYING_SLOT_VAR3, 34, 0)
>decl_var shader_in INTERP_MODE_FLAT vec4 fastuidraw_float_flat_varying0@31 (VARYING_SLOT_VAR6, 37, 0)
>decl_var shader_in INTERP_MODE_FLAT vec4 fastuidraw_float_flat_varying1@32 (VARYING_SLOT_VAR7, 38, 0)
>decl_var shader_in INTERP_MODE_FLAT vec4 fastuidraw_float_flat_varying2@33 (VARYING_SLOT_VAR8, 39, 0)
>decl_var shader_in INTERP_MODE_FLAT vec4 fastuidraw_float_flat_varying3@34 (VARYING_SLOT_VAR9, 40, 0)
>decl_var shader_in INTERP_MODE_FLAT vec4 fastuidraw_float_flat_varying4@35 (VARYING_SLOT_VAR10, 41, 0)
>decl_var shader_in INTERP_MODE_FLAT vec3 fastuidraw_float_flat_varying5@36 (VARYING_SLOT_VAR11.xyz, 42, 0)
>decl_var shader_out INTERP_MODE_NONE vec4 fastuidraw_final_color0 (FRAG_RESULT_DATA0, 8, 0)
>decl_var shader_out INTERP_MODE_NONE vec4 fastuidraw_final_color1 (FRAG_RESULT_DATA0, 9, 0)
>decl_function main (0 params)
>
>impl main {
>	decl_reg vec1 32 r0
>	decl_reg vec1 32 r1
>	decl_reg vec1 32 r2
>	decl_reg vec1 32 r3
>	decl_reg vec1 32 r4
>	decl_reg vec1 32 r5
>	decl_reg vec1 32 r6
>	decl_reg vec1 32 r7
>	decl_reg vec1 32 r8
>	decl_reg vec1 32 r9
>	decl_reg vec1 32 r10
>	decl_reg vec1 32 r11
>	decl_reg vec1 32 r12
>	decl_reg vec1 32 r13
>	decl_reg vec1 32 r14
>	decl_reg vec1 32 r15
>	decl_reg vec1 32 r16
>	decl_reg vec1 32 r17
>	decl_reg vec1 32 r18
>	decl_reg vec1 32 r19
>	decl_reg vec1 32 r20
>	decl_reg vec1 32 r21
>	decl_reg vec1 32 r22
>	decl_reg vec1 32 r23
>	decl_reg vec1 32 r24
>	decl_reg vec1 32 r25
>	decl_reg vec1 32 r26
>	decl_reg vec1 32 r27
>	decl_reg vec1 32 r28
>	decl_reg vec1 32 r29
>	decl_reg vec1 32 r30
>	decl_reg vec1 32 r31
>	decl_reg vec1 32 r32
>	decl_reg vec1 32 r33
>	decl_reg vec1 32 r34
>	decl_reg vec1 32 r35
>	decl_reg vec1 32 r36
>	decl_reg vec1 32 r37
>	decl_reg vec1 32 r38
>	decl_reg vec1 32 r39
>	decl_reg vec1 32 r40
>	decl_reg vec1 32 r41
>	decl_reg vec1 32 r42
>	decl_reg vec1 32 r43
>	decl_reg vec4 32 r44
>	decl_reg vec1 32 r45
>	decl_reg vec1 32 r46
>	decl_reg vec1 32 r47
>	decl_reg vec1 32 r48
>	decl_reg vec1 32 r49
>	decl_reg vec1 32 r50
>	decl_reg vec4 32 r51
>	decl_reg vec4 32 r52
>	decl_reg vec4 32 r53
>	decl_reg vec4 32 r54
>	decl_reg vec1 32 r55
>	decl_reg vec1 32 r56
>	decl_reg vec1 32 r57
>	decl_reg vec1 32 r58
>	decl_reg vec1 32 r59
>	decl_reg vec1 32 r60
>	decl_reg vec1 32 r61
>	decl_reg vec1 32 r62
>	decl_reg vec1 32 r63
>	decl_reg vec1 32 r64
>	decl_reg vec1 32 r65
>	decl_reg vec1 32 r66
>	decl_reg vec1 32 r67
>	decl_reg vec1 32 r68
>	decl_reg vec1 32 r69
>	decl_reg vec1 32 r70
>	decl_reg vec1 32 r71
>	decl_reg vec1 32 r72
>	decl_reg vec1 32 r73
>	decl_reg vec1 32 r74
>	decl_reg vec1 32 r75
>	decl_reg vec1 32 r76
>	decl_reg vec1 32 r77
>	decl_reg vec1 32 r78
>	decl_reg vec1 32 r79
>	decl_reg vec1 32 r80
>	decl_reg vec1 32 r81
>	decl_reg vec1 32 r82
>	decl_reg vec1 32 r83
>	decl_reg vec1 32 r84
>	decl_reg vec1 32 r85
>	decl_reg vec1 32 r86
>	decl_reg vec1 32 r87
>	decl_reg vec1 32 r88
>	decl_reg vec1 32 r89
>	decl_reg vec1 32 r90
>	decl_reg vec1 32 r91
>	decl_reg vec1 32 r92
>	decl_reg vec1 32 r93
>	decl_reg vec1 32 r94
>	decl_reg vec1 32 r95
>	decl_reg vec1 32 r96
>	decl_reg vec1 32 r97
>	decl_reg vec1 32 r98
>	decl_reg vec1 32 r99
>	decl_reg vec1 32 r100
>	decl_reg vec1 32 r101
>	decl_reg vec1 32 r102
>	decl_reg vec1 32 r103
>	decl_reg vec1 32 r104
>	decl_reg vec1 32 r105
>	decl_reg vec1 32 r106
>	decl_reg vec1 32 r107
>	decl_reg vec1 32 r108
>	decl_reg vec1 32 r109
>	decl_reg vec1 32 r110
>	decl_reg vec1 32 r111
>	decl_reg vec1 32 r112
>	decl_reg vec1 32 r113
>	decl_reg vec1 32 r114
>	decl_reg vec1 32 r115
>	decl_reg vec1 32 r116
>	decl_reg vec1 32 r117
>	decl_reg vec1 32 r118
>	decl_reg vec1 32 r119
>	decl_reg vec1 32 r120
>	decl_reg vec1 32 r121
>	decl_reg vec1 32 r122
>	decl_reg vec1 32 r123
>	decl_reg vec1 32 r124
>	decl_reg vec1 32 r125
>	decl_reg vec1 32 r126
>	decl_reg vec1 32 r127
>	decl_reg vec1 32 r128
>	decl_reg vec1 32 r129
>	decl_reg vec1 32 r130
>	decl_reg vec1 32 r131
>	decl_reg vec1 32 r132
>	decl_reg vec1 32 r133
>	decl_reg vec1 32 r134
>	decl_reg vec1 32 r135
>	decl_reg vec1 32 r136
>	decl_reg vec1 32 r137
>	decl_reg vec1 32 r138
>	decl_reg vec1 32 r139
>	decl_reg vec1 32 r140
>	decl_reg vec1 32 r141
>	decl_reg vec1 32 r142
>	decl_reg vec1 32 r143
>	decl_reg vec1 32 r144
>	decl_reg vec1 32 r145
>	decl_reg vec1 32 r146
>	decl_reg vec1 32 r147
>	block block_0:
>	/* preds: */
>	vec2 32 ssa_0 = intrinsic load_barycentric_pixel () (1) /* interp_mode=1 */
>	vec1 32 ssa_1 = load_const (0x00000000 /* 0.000000 */)
>	r0 = intrinsic load_interpolated_input (ssa_0, ssa_1) (35, 3) /* base=35 */ /* component=3 */	/* fastuidraw_float_smooth_varying1 */
>	r1 = intrinsic load_interpolated_input (ssa_0, ssa_1) (36, 0) /* base=36 */ /* component=0 */	/* fastuidraw_float_smooth_varying2 */
>	vec4 32 ssa_4 = intrinsic load_interpolated_input (ssa_0, ssa_1) (0, 0) /* base=0 */ /* component=0 */	/* gl_FragCoord */
>	vec4 32 ssa_5 = intrinsic load_interpolated_input (ssa_0, ssa_1) (34, 0) /* base=34 */ /* component=0 */	/* fastuidraw_float_smooth_varying0 */
>	vec1 32 ssa_23 = load_const (0x00000010 /* 0.000000 */)
>	vec1 32 ssa_24 = load_const (0xffff8000 /* -nan */)
>	vec1 32 ssa_25 = load_const (0xffffffff /* -nan */)
>	vec1 32 ssa_26 = load_const (0x80000000 /* -0.000000 */)
>	vec1 32 ssa_27 = load_const (0x00002000 /* 0.000000 */)
>	vec1 32 ssa_28 = load_const (0x0000001e /* 0.000000 */)
>	vec1 32 ssa_29 = load_const (0x0000000e /* 0.000000 */)
>	vec1 32 ssa_30 = load_const (0x00000001 /* 0.000000 */)
>	vec1 32 ssa_31 = load_const (0x00000002 /* 0.000000 */)
>	vec1 32 ssa_32 = load_const (0x00000003 /* 0.000000 */)
>	vec1 32 ssa_33 = load_const (0x40000000 /* 2.000000 */)
>	vec1 32 ssa_34 = load_const (0x00000015 /* 0.000000 */)
>	vec1 32 ssa_35 = load_const (0x3f800000 /* 1.000000 */)
>	vec1 32 ssa_36 = load_const (0x40800000 /* 4.000000 */)
>	vec1 32 ssa_37 = load_const (0x3f000000 /* 0.500000 */)
>	vec1 32 ssa_38 = load_const (0x5d5e0b6b /* 999999984306749440.000000 */)
>	vec1 32 ssa_39 = load_const (0x3e800000 /* 0.250000 */)
>	vec1 32 ssa_40 = load_const (0xbc46c6a5 /* -0.012132 */)
>	vec1 32 ssa_41 = load_const (0x3d5be101 /* 0.053681 */)
>	vec1 32 ssa_42 = load_const (0xbdf0555d /* -0.117350 */)
>	vec1 32 ssa_43 = load_const (0x3e468bc1 /* 0.193892 */)
>	vec1 32 ssa_44 = load_const (0xbeaa5476 /* -0.332676 */)
>	vec1 32 ssa_45 = load_const (0x3f7ffea5 /* 0.999979 */)
>	vec1 32 ssa_46 = load_const (0xc0000000 /* -2.000000 */)
>	vec1 32 ssa_47 = load_const (0x3fc90fdb /* 1.570796 */)
>	vec1 32 ssa_48 = load_const (0x40c90fdb /* 6.283185 */)
>	vec1 32 ssa_49 = load_const (0x3e22f983 /* 0.159155 */)
>	vec1 32 ssa_50 = load_const (0x00000013 /* 0.000000 */)
>	vec1 32 ssa_51 = load_const (0xbf800000 /* -1.000000 */)
>	vec1 32 ssa_52 = load_const (0x0000000a /* 0.000000 */)
>	vec1 32 ssa_53 = load_const (0x00000017 /* 0.000000 */)
>	vec1 32 ssa_54 = load_const (0x00000019 /* 0.000000 */)
>	vec1 32 ssa_55 = load_const (0x40900000 /* 4.500000 */)
>	vec1 32 ssa_56 = load_const (0x42000000 /* 32.000000 */)
>	vec1 32 ssa_57 = load_const (0x3d000000 /* 0.031250 */)
>	vec1 32 ssa_58 = load_const (0x41f80000 /* 31.000000 */)
>	vec1 32 ssa_59 = load_const (0x40400000 /* 3.000000 */)
>	vec1 32 ssa_60 = load_const (0x40c00000 /* 6.000000 */)
>	vec1 32 ssa_61 = load_const (0xbfc00000 /* -1.500000 */)
>	vec1 32 ssa_62 = load_const (0x40200000 /* 2.500000 */)
>	vec1 32 ssa_63 = load_const (0xbf000000 /* -0.500000 */)
>	vec1 32 ssa_64 = load_const (0x3fc00000 /* 1.500000 */)
>	vec1 32 ssa_65 = load_const (0x39000000 /* 0.000122 */)
>	vec1 32 ssa_66 = load_const (0x01000000 /* 0.000000 */)
>	vec1 32 ssa_67 = load_const (0x00000006 /* 0.000000 */)
>	vec1 32 ssa_68 = load_const (0x00000012 /* 0.000000 */)
>	vec1 32 ssa_69 = load_const (0x00000014 /* 0.000000 */)
>	vec1 32 ssa_70 = load_const (0x00000008 /* 0.000000 */)
>	vec1 32 ssa_71 = load_const (0x00000018 /* 0.000000 */)
>	vec1 32 ssa_72 = load_const (0x00000016 /* 0.000000 */)
>	vec1 32 ssa_73 = load_const (0x3fffffff /* 2.000000 */)
>	vec1 32 ssa_74 = load_const (0x0000001f /* 0.000000 */)
>	vec1 32 ssa_75 = load_const (0x00000011 /* 0.000000 */)
>	vec1 32 ssa_76 = load_const (0x0000000f /* 0.000000 */)
>	vec1 32 ssa_77 = load_const (0x42f00000 /* 120.000000 */)
>	vec1 32 ssa_78 = load_const (0x33d6bf95 /* 0.000000 */)
>	vec1 32 ssa_79 = load_const (0x00008000 /* 0.000000 */)
>	vec1 32 ssa_80 = load_const (0x00000004 /* 0.000000 */)
>	vec1 32 ssa_81 = load_const (0x00002e74 /* 0.000000 */)
>	vec1 32 ssa_82 = load_const (0x38d1b717 /* 0.000100 */)
>	vec1 32 ssa_83 = load_const (0x00000000 /* 0.000000 */)
>	vec1 32 ssa_84 = load_const (0x3c800000 /* 0.015625 */)
>	vec1 32 ssa_85 = load_const (0x3a83126f /* 0.001000 */)
>	vec1 32 ssa_86 = load_const (0x00000005 /* 0.000000 */)
>	vec1 32 ssa_87 = load_const (0x00000007 /* 0.000000 */)
>	vec1 32 ssa_88 = load_const (0x00000009 /* 0.000000 */)
>	vec1 32 ssa_89 = load_const (0x0000000b /* 0.000000 */)
>	vec1 32 ssa_90 = load_const (0x0000000c /* 0.000000 */)
>	vec1 32 ssa_91 = load_const (0x0000000d /* 0.000000 */)
>	vec2 32 ssa_92 = intrinsic load_input (ssa_1) (33, 0) /* base=33 */ /* component=0 */	/* fastuidraw_uint_varying2 */
>	vec1 32 ssa_93 = intrinsic load_input (ssa_1) (33, 3) /* base=33 */ /* component=3 */	/* fastuidraw_uint_varying2 */
>	vec1 32 ssa_94 = extract_u16 ssa_93, ssa_1
>	vec1 32 ssa_95 = extract_u16 ssa_93, ssa_30
>	vec1 32 ssa_96 = iadd ssa_94, ssa_24
>	vec1 32 ssa_97 = iadd ssa_95, ssa_24
>	vec1 32 ssa_98 = ine32 ssa_92.x, ssa_25
>	/* succs: block_1 block_396 */
>	if ssa_98 {
>		block block_1:
>		/* preds: block_0 */
>		vec1 32 ssa_99 = iand ssa_92.y, ssa_26
>		vec1 32 ssa_100 = ine32 ssa_99, ssa_1
>		/* succs: block_2 block_134 */
>		if ssa_100 {
>			block block_2:
>			/* preds: block_1 */
>			vec4 32 ssa_101 = intrinsic load_input (ssa_1) (41, 0) /* base=41 */ /* component=0 */	/* fastuidraw_float_flat_varying4 */
>			r19 = imov ssa_101.w
>			vec3 32 ssa_103 = intrinsic load_input (ssa_1) (42, 0) /* base=42 */ /* component=0 */	/* fastuidraw_float_flat_varying5 */
>			r20 = imov ssa_103.x
>			r21 = imov ssa_103.y
>			r14 = imov ssa_103.z
>			vec1 32 ssa_107 = fddx r0
>			vec1 32 ssa_108 = fddx r1
>			vec4 32 ssa_109 = intrinsic load_uniform (ssa_1) (0, 16) /* base=0 */ /* range=16 */	/* fastuidraw_painterStore */
>			vec1 32 ssa_110 = fmul r0, ssa_109.x
>			vec1 32 ssa_111 = fddy ssa_110
>			vec1 32 ssa_112 = fmul r1, ssa_109.x
>			vec1 32 ssa_113 = fddy ssa_112
>			vec1 32 ssa_114 = iand ssa_92.y, ssa_27
>			vec1 32 ssa_115 = ine32 ssa_114, ssa_1
>			/* succs: block_3 block_22 */
>			if ssa_115 {
>				block block_3:
>				/* preds: block_2 */
>				vec1 32 ssa_116 = ishl ssa_92.y, ssa_23
>				vec1 32 ssa_117 = ushr ssa_116, ssa_28
>				vec1 32 ssa_118 = ishl ssa_92.y, ssa_29
>				vec1 32 ssa_119 = ushr ssa_118, ssa_28
>				vec4 32 ssa_120 = intrinsic load_input (ssa_1) (37, 0) /* base=37 */ /* component=0 */	/* fastuidraw_float_flat_varying0 */
>				vec1 32 ssa_121 = fadd r0, -ssa_120.x
>				vec1 32 ssa_122 = fadd r1, -ssa_120.y
>				vec1 32 ssa_123 = ieq32 ssa_117, ssa_30
>				/* succs: block_4 block_5 */
>				if ssa_123 {
>					block block_4:
>					/* preds: block_3 */
>					vec1 32 ssa_124 = fmax abs(ssa_121), ssa_1
>					r22 = fmin ssa_124, ssa_120.z
>					/* succs: block_12 */
>				} else {
>					block block_5:
>					/* preds: block_3 */
>					vec1 32 ssa_126 = ieq32 ssa_117, ssa_31
>					/* succs: block_6 block_7 */
>					if ssa_126 {
>						block block_6:
>						/* preds: block_5 */
>						vec1 32 ssa_127 = frcp ssa_120.z
>						vec1 32 ssa_128 = fmul ssa_121, ssa_127
>						vec1 32 ssa_129 = ffloor ssa_128
>						r22 = ffma -ssa_120.z, ssa_129, ssa_121
>						/* succs: block_11 */
>					} else {
>						block block_7:
>						/* preds: block_5 */
>						vec1 32 ssa_131 = ieq32 ssa_117, ssa_32
>						/* succs: block_8 block_9 */
>						if ssa_131 {
>							block block_8:
>							/* preds: block_7 */
>							vec1 32 ssa_132 = fmul ssa_33, ssa_120.z
>							vec1 32 ssa_133 = frcp ssa_132
>							vec1 32 ssa_134 = fmul ssa_121, ssa_133
>							vec1 32 ssa_135 = ffloor ssa_134
>							vec1 32 ssa_136 = ffma -ssa_132, ssa_135, ssa_121
>							vec1 32 ssa_137 = fadd ssa_136, -ssa_120.z
>							r22 = fadd ssa_120.z, -abs(ssa_137)
>							/* succs: block_10 */
>						} else {
>							block block_9:
>							/* preds: block_7 */
>							vec1 32 ssa_139 = fmax ssa_121, ssa_1
>							r22 = fmin ssa_139, ssa_120.z
>							/* succs: block_10 */
>						}
>						block block_10:
>						/* preds: block_8 block_9 */
>						/* succs: block_11 */
>					}
>					block block_11:
>					/* preds: block_6 block_10 */
>					/* succs: block_12 */
>				}
>				block block_12:
>				/* preds: block_4 block_11 */
>				vec1 32 ssa_144 = ieq32 ssa_119, ssa_30
>				/* succs: block_13 block_14 */
>				if ssa_144 {
>					block block_13:
>					/* preds: block_12 */
>					vec1 32 ssa_145 = fmax abs(ssa_122), ssa_1
>					r23 = fmin ssa_145, ssa_120.w
>					/* succs: block_21 */
>				} else {
>					block block_14:
>					/* preds: block_12 */
>					vec1 32 ssa_147 = ieq32 ssa_119, ssa_31
>					/* succs: block_15 block_16 */
>					if ssa_147 {
>						block block_15:
>						/* preds: block_14 */
>						vec1 32 ssa_148 = frcp ssa_120.w
>						vec1 32 ssa_149 = fmul ssa_122, ssa_148
>						vec1 32 ssa_150 = ffloor ssa_149
>						r23 = ffma -ssa_120.w, ssa_150, ssa_122
>						/* succs: block_20 */
>					} else {
>						block block_16:
>						/* preds: block_14 */
>						vec1 32 ssa_152 = ieq32 ssa_119, ssa_32
>						/* succs: block_17 block_18 */
>						if ssa_152 {
>							block block_17:
>							/* preds: block_16 */
>							vec1 32 ssa_153 = fmul ssa_33, ssa_120.w
>							vec1 32 ssa_154 = frcp ssa_153
>							vec1 32 ssa_155 = fmul ssa_122, ssa_154
>							vec1 32 ssa_156 = ffloor ssa_155
>							vec1 32 ssa_157 = ffma -ssa_153, ssa_156, ssa_122
>							vec1 32 ssa_158 = fadd ssa_157, -ssa_120.w
>							r23 = fadd ssa_120.w, -abs(ssa_158)
>							/* succs: block_19 */
>						} else {
>							block block_18:
>							/* preds: block_16 */
>							vec1 32 ssa_160 = fmax ssa_122, ssa_1
>							r23 = fmin ssa_160, ssa_120.w
>							/* succs: block_19 */
>						}
>						block block_19:
>						/* preds: block_17 block_18 */
>						/* succs: block_20 */
>					}
>					block block_20:
>					/* preds: block_15 block_19 */
>					/* succs: block_21 */
>				}
>				block block_21:
>				/* preds: block_13 block_20 */
>				r0 = fadd r22, ssa_120.x
>				r1 = fadd r23, ssa_120.y
>				/* succs: block_23 */
>			} else {
>				block block_22:
>				/* preds: block_2 */
>				/* succs: block_23 */
>			}
>			block block_23:
>			/* preds: block_21 block_22 */
>			vec1 32 ssa_169 = ishl ssa_92.y, ssa_34
>			vec1 32 ssa_170 = ushr ssa_169, ssa_28
>			vec1 32 ssa_171 = ine32 ssa_170, ssa_1
>			/* succs: block_24 block_52 */
>			if ssa_171 {
>				block block_24:
>				/* preds: block_23 */
>				vec1 32 ssa_172 = ieq32 ssa_170, ssa_31
>				/* succs: block_25 block_32 */
>				if ssa_172 {
>					block block_25:
>					/* preds: block_24 */
>					vec4 32 ssa_173 = intrinsic load_input (ssa_1) (38, 0) /* base=38 */ /* component=0 */	/* fastuidraw_float_flat_varying1 */
>					vec1 32 ssa_174 = fadd r0, -ssa_173.x
>					vec1 32 ssa_175 = fadd r1, -ssa_173.y
>					vec1 32 ssa_176 = fadd ssa_173.z, -ssa_173.x
>					vec1 32 ssa_177 = fadd ssa_173.w, -ssa_173.y
>					vec4 32 ssa_178 = intrinsic load_input (ssa_1) (39, 0) /* base=39 */ /* component=0 */	/* fastuidraw_float_flat_varying2 */
>					vec1 32 ssa_179 = fadd ssa_178.y, -ssa_178.x
>					vec1 32 ssa_180 = fmul ssa_175, ssa_177
>					vec1 32 ssa_181 = ffma ssa_174, ssa_176, ssa_180
>					vec1 32 ssa_182 = ffma -ssa_178.x, ssa_179, ssa_181
>					vec1 32 ssa_183 = fmul ssa_33, ssa_182
>					vec1 32 ssa_184 = fmul ssa_177, ssa_177
>					vec1 32 ssa_185 = ffma ssa_176, ssa_176, ssa_184
>					vec1 32 ssa_186 = ffma -ssa_179, ssa_179, ssa_185
>					vec1 32 ssa_187 = fmul ssa_175, ssa_175
>					vec1 32 ssa_188 = ffma ssa_174, ssa_174, ssa_187
>					vec1 32 ssa_189 = ffma -ssa_178.x, ssa_178.x, ssa_188
>					vec1 32 ssa_190 = fmul ssa_186, ssa_36
>					vec1 32 ssa_191 = fmul ssa_190, ssa_189
>					vec1 32 ssa_192 = ffma ssa_183, ssa_183, -ssa_191
>					vec1 32 ssa_193 = fge32 ssa_192, ssa_1
>					/* succs: block_26 block_30 */
>					if ssa_193 {
>						block block_26:
>						/* preds: block_25 */
>						vec1 32 ssa_194 = fsqrt abs(ssa_192)
>						vec1 32 ssa_195 = frcp ssa_186
>						vec1 32 ssa_196 = fmul ssa_37, ssa_195
>						vec1 32 ssa_197 = fadd -ssa_183, ssa_194
>						vec1 32 ssa_198 = fmul ssa_197, ssa_196
>						vec1 32 ssa_199 = fadd -ssa_183, -ssa_194
>						vec1 32 ssa_200 = fmul ssa_199, ssa_196
>						vec1 32 ssa_201 = fge32 ssa_35, ssa_198
>						vec1 32 ssa_202 = fge32 ssa_198, ssa_1
>						vec1 32 ssa_203 = iand ssa_202, ssa_201
>						vec1 32 ssa_204 = b2f32 ssa_203
>						vec1 32 ssa_205 = fge32 ssa_35, ssa_200
>						vec1 32 ssa_206 = fge32 ssa_200, ssa_1
>						vec1 32 ssa_207 = iand ssa_206, ssa_205
>						vec1 32 ssa_208 = b2f32 ssa_207
>						vec1 32 ssa_209 = ieq32 ssa_203, ssa_207
>						/* succs: block_27 block_28 */
>						if ssa_209 {
>							block block_27:
>							/* preds: block_26 */
>							r24 = fmax ssa_198, ssa_200
>							/* succs: block_29 */
>						} else {
>							block block_28:
>							/* preds: block_26 */
>							vec1 32 ssa_211 = fmul ssa_208, ssa_200
>							r24 = ffma ssa_204, ssa_198, ssa_211
>							/* succs: block_29 */
>						}
>						block block_29:
>						/* preds: block_27 block_28 */
>						r18 = imov ssa_35
>						/* succs: block_31 */
>					} else {
>						block block_30:
>						/* preds: block_25 */
>						r18 = imov ssa_1
>						r24 = imov r18
>						/* succs: block_31 */
>					}
>					block block_31:
>					/* preds: block_29 block_30 */
>					/* succs: block_42 */
>				} else {
>					block block_32:
>					/* preds: block_24 */
>					vec1 32 ssa_216 = ieq32 ssa_170, ssa_30
>					/* succs: block_33 block_34 */
>					if ssa_216 {
>						block block_33:
>						/* preds: block_32 */
>						vec4 32 ssa_217 = intrinsic load_input (ssa_1) (38, 0) /* base=38 */ /* component=0 */	/* fastuidraw_float_flat_varying1 */
>						vec1 32 ssa_218 = fadd ssa_217.z, -ssa_217.x
>						vec1 32 ssa_219 = fadd ssa_217.w, -ssa_217.y
>						vec1 32 ssa_220 = fadd r0, -ssa_217.x
>						vec1 32 ssa_221 = fadd r1, -ssa_217.y
>						vec1 32 ssa_222 = fmul ssa_219, ssa_221
>						vec1 32 ssa_223 = ffma ssa_218, ssa_220, ssa_222
>						vec1 32 ssa_224 = fmul ssa_219, ssa_219
>						vec1 32 ssa_225 = ffma ssa_218, ssa_218, ssa_224
>						vec1 32 ssa_226 = frcp ssa_225
>						r24 = fmul ssa_223, ssa_226
>						r18 = imov ssa_35
>						/* succs: block_41 */
>					} else {
>						block block_34:
>						/* preds: block_32 */
>						vec1 32 ssa_228 = ieq32 ssa_170, ssa_32
>						/* succs: block_35 block_39 */
>						if ssa_228 {
>							block block_35:
>							/* preds: block_34 */
>							vec4 32 ssa_229 = intrinsic load_input (ssa_1) (38, 0) /* base=38 */ /* component=0 */	/* fastuidraw_float_flat_varying1 */
>							vec1 32 ssa_230 = fadd r0, -ssa_229.x
>							vec1 32 ssa_231 = fadd r1, -ssa_229.y
>							vec1 32 ssa_232 = fmov abs(ssa_230)
>							vec1 32 ssa_233 = fge32 ssa_1, ssa_230
>							vec1 32 ssa_234 = b32csel ssa_233, ssa_232, ssa_231
>							vec1 32 ssa_235 = b32csel ssa_233, ssa_231, ssa_232
>							vec1 32 ssa_236 = fge32 abs(ssa_235), ssa_38
>							vec1 32 ssa_237 = b32csel ssa_236, ssa_39, ssa_35
>							vec1 32 ssa_238 = fmul ssa_235, ssa_237
>							vec1 32 ssa_239 = frcp ssa_238
>							vec1 32 ssa_240 = fmul ssa_234, ssa_237
>							vec1 32 ssa_241 = fmul ssa_240, ssa_239
>							vec1 32 ssa_242 = fmov abs(ssa_241)
>							vec1 32 ssa_243 = feq32 abs(ssa_230), abs(ssa_231)
>							vec1 32 ssa_244 = b32csel ssa_243, ssa_35, ssa_242
>							vec1 32 ssa_245 = fmin abs(ssa_244), ssa_35
>							vec1 32 ssa_246 = fmax abs(ssa_244), ssa_35
>							vec1 32 ssa_247 = frcp ssa_246
>							vec1 32 ssa_248 = fmul ssa_245, ssa_247
>							vec1 32 ssa_249 = fmul ssa_248, ssa_248
>							vec1 32 ssa_250 = fmul ssa_40, ssa_249
>							vec1 32 ssa_251 = fadd ssa_250, ssa_41
>							vec1 32 ssa_252 = ffma ssa_251, ssa_249, ssa_42
>							vec1 32 ssa_253 = ffma ssa_252, ssa_249, ssa_43
>							vec1 32 ssa_254 = ffma ssa_253, ssa_249, ssa_44
>							vec1 32 ssa_255 = ffma ssa_254, ssa_249, ssa_45
>							vec1 32 ssa_256 = fmul ssa_255, ssa_248
>							vec1 32 ssa_257 = flt32 ssa_35, abs(ssa_244)
>							vec1 32 ssa_258 = b2f32 ssa_257
>							vec1 32 ssa_259 = ffma ssa_256, ssa_46, ssa_47
>							vec1 32 ssa_260 = ffma ssa_258, ssa_259, ssa_256
>							vec1 32 ssa_261 = fsign ssa_244
>							vec1 32 ssa_262 = b2f32 ssa_233
>							vec1 32 ssa_263 = fmul ssa_262, ssa_47
>							vec1 32 ssa_264 = ffma ssa_260, ssa_261, ssa_263
>							vec1 32 ssa_265 = fmin ssa_231, ssa_239
>							vec1 32 ssa_266 = fmov -ssa_264
>							vec1 32 ssa_267 = flt32 ssa_265, ssa_1
>							vec1 32 ssa_268 = b32csel ssa_267, ssa_266, ssa_264
>							vec1 32 ssa_269 = fadd ssa_268, ssa_48
>							vec1 32 ssa_270 = flt32 ssa_268, ssa_229.z
>							vec1 32 ssa_271 = b32csel ssa_270, ssa_269, ssa_268
>							vec1 32 ssa_272 = fadd ssa_271, -ssa_229.z
>							r25 = fmul ssa_272, ssa_49
>							vec1 32 ssa_274 = flt32 ssa_229.w, ssa_1
>							/* succs: block_36 block_37 */
>							if ssa_274 {
>								block block_36:
>								/* preds: block_35 */
>								r25 = fadd ssa_35, -r25
>								/* succs: block_38 */
>							} else {
>								block block_37:
>								/* preds: block_35 */
>								/* succs: block_38 */
>							}
>							block block_38:
>							/* preds: block_36 block_37 */
>							r24 = fmul r25, abs(ssa_229.w)
>							r18 = imov ssa_35
>							/* succs: block_40 */
>						} else {
>							block block_39:
>							/* preds: block_34 */
>							r24 = imov ssa_35
>							/* succs: block_40 */
>						}
>						block block_40:
>						/* preds: block_38 block_39 */
>						/* succs: block_41 */
>					}
>					block block_41:
>					/* preds: block_33 block_40 */
>					/* succs: block_42 */
>				}
>				block block_42:
>				/* preds: block_31 block_41 */
>				vec1 32 ssa_284 = ishl ssa_92.y, ssa_50
>				vec1 32 ssa_285 = ushr ssa_284, ssa_28
>				vec1 32 ssa_286 = ieq32 ssa_285, ssa_30
>				/* succs: block_43 block_44 */
>				if ssa_286 {
>					block block_43:
>					/* preds: block_42 */
>					r26 = fmov.sat abs(r24)
>					/* succs: block_51 */
>				} else {
>					block block_44:
>					/* preds: block_42 */
>					vec1 32 ssa_288 = ieq32 ssa_285, ssa_31
>					/* succs: block_45 block_46 */
>					if ssa_288 {
>						block block_45:
>						/* preds: block_44 */
>						r26 = ffract r24
>						/* succs: block_50 */
>					} else {
>						block block_46:
>						/* preds: block_44 */
>						vec1 32 ssa_290 = ieq32 ssa_285, ssa_32
>						/* succs: block_47 block_48 */
>						if ssa_290 {
>							block block_47:
>							/* preds: block_46 */
>							vec1 32 ssa_291 = fmul r24, ssa_37
>							vec1 32 ssa_292 = ffloor ssa_291
>							vec1 32 ssa_293 = fadd r24, ssa_51
>							vec1 32 ssa_294 = ffma -ssa_33, ssa_292, ssa_293
>							r26 = fadd ssa_35, -abs(ssa_294)
>							/* succs: block_49 */
>						} else {
>							block block_48:
>							/* preds: block_46 */
>							r26 = fmov.sat r24
>							/* succs: block_49 */
>						}
>						block block_49:
>						/* preds: block_47 block_48 */
>						/* succs: block_50 */
>					}
>					block block_50:
>					/* preds: block_45 block_49 */
>					/* succs: block_51 */
>				}
>				block block_51:
>				/* preds: block_43 block_50 */
>				vec1 32 ssa_300 = ffma r26, ssa_101.z, ssa_101.x
>				vec2 32 ssa_301 = vec2 ssa_300, ssa_101.y
>				vec4 32 ssa_302 = txl ssa_301 (coord), ssa_1 (lod), 0 (texture), 0 (sampler), 
>				vec1 32 ssa_303 = fmul r18, ssa_302.x
>				vec1 32 ssa_304 = fmul r18, ssa_302.y
>				vec1 32 ssa_305 = fmul r18, ssa_302.z
>				vec1 32 ssa_306 = fmul r18, ssa_302.w
>				r19 = fmul ssa_101.w, ssa_303
>				r20 = fmul ssa_103.x, ssa_304
>				r21 = fmul ssa_103.y, ssa_305
>				r14 = fmul ssa_103.z, ssa_306
>				/* succs: block_53 */
>			} else {
>				block block_52:
>				/* preds: block_23 */
>				/* succs: block_53 */
>			}
>			block block_53:
>			/* preds: block_51 block_52 */
>			r17 = fmul r19, r14
>			r16 = fmul r20, r14
>			r15 = fmul r21, r14
>			vec1 32 ssa_318 = iand ssa_92.y, ssa_32
>			vec1 32 ssa_319 = ine32 ssa_318, ssa_1
>			/* succs: block_54 block_132 */
>			if ssa_319 {
>				block block_54:
>				/* preds: block_53 */
>				vec1 32 ssa_320 = fmax r0, ssa_1
>				vec4 32 ssa_321 = intrinsic load_input (ssa_1) (40, 0) /* base=40 */ /* component=0 */	/* fastuidraw_float_flat_varying3 */
>				vec1 32 ssa_322 = fadd ssa_321.x, ssa_51
>				vec1 32 ssa_323 = fmin ssa_320, ssa_322
>				vec1 32 ssa_324 = fmax r1, ssa_1
>				vec1 32 ssa_325 = fadd ssa_321.y, ssa_51
>				vec1 32 ssa_326 = fmin ssa_324, ssa_325
>				vec1 32 ssa_327 = ishl ssa_92.y, ssa_52
>				vec1 32 ssa_328 = ushr ssa_327, ssa_28
>				vec1 32 ssa_329 = ishl ssa_92.y, ssa_28
>				vec1 32 ssa_330 = ushr ssa_329, ssa_28
>				vec1 32 ssa_331 = ishl ssa_92.y, ssa_53
>				vec1 32 ssa_332 = ushr ssa_331, ssa_54
>				vec1 32 ssa_333 = ult32 ssa_1, ssa_332
>				/* succs: block_55 block_56 */
>				if ssa_333 {
>					block block_55:
>					/* preds: block_54 */
>					vec1 32 ssa_334 = fmul ssa_108, ssa_108
>					vec1 32 ssa_335 = ffma ssa_107, ssa_107, ssa_334
>					vec1 32 ssa_336 = fmul ssa_113, ssa_113
>					vec1 32 ssa_337 = ffma ssa_111, ssa_111, ssa_336
>					vec1 32 ssa_338 = fadd ssa_335, ssa_337
>					vec1 32 ssa_339 = fmul ssa_338, ssa_37
>					vec1 32 ssa_340 = fmax ssa_35, ssa_339
>					vec1 32 ssa_341 = flog2 ssa_340
>					vec1 32 ssa_342 = fmul ssa_37, ssa_341
>					vec1 32 ssa_343 = u2f32 ssa_332
>					r27 = fmin ssa_343, ssa_342
>					/* succs: block_57 */
>				} else {
>					block block_56:
>					/* preds: block_54 */
>					r27 = imov ssa_1
>					/* succs: block_57 */
>				}
>				block block_57:
>				/* preds: block_55 block_56 */
>				vec1 32 ssa_346 = ieq32 ssa_328, ssa_1
>				/* succs: block_58 block_118 */
>				if ssa_346 {
>					block block_58:
>					/* preds: block_57 */
>					vec1 32 ssa_347 = fmin r27, ssa_55
>					vec1 32 ssa_348 = ieq32 ssa_330, ssa_30
>					/* succs: block_59 block_65 */
>					if ssa_348 {
>						block block_59:
>						/* preds: block_58 */
>						vec1 32 ssa_349 = fceil ssa_347
>						vec1 32 ssa_350 = fmax ssa_323, ssa_1
>						vec1 32 ssa_351 = fmax ssa_326, ssa_1
>						vec1 32 ssa_352 = fmin ssa_350, ssa_321.x
>						vec1 32 ssa_353 = fmin ssa_351, ssa_321.y
>						vec4 32 ssa_354 = intrinsic load_input (ssa_1) (39, 0) /* base=39 */ /* component=0 */	/* fastuidraw_float_flat_varying2 */
>						r28 = ffma ssa_352, ssa_321.z, ssa_354.z
>						r29 = ffma ssa_353, ssa_321.z, ssa_354.w
>						vec1 32 ssa_357 = f2i32 r28
>						vec1 32 ssa_358 = f2i32 r29
>						vec4 32 ssa_359 = intrinsic load_input (ssa_1) (31, 0) /* base=31 */ /* component=0 */	/* fastuidraw_uint_varying0 */
>						vec3 32 ssa_360 = vec3 ssa_357, ssa_358, ssa_359.w
>						vec4 32 ssa_361 = txf ssa_360 (coord), ssa_1 (lod), 3 (texture), 3 (sampler), 
>						vec1 32 ssa_362 = ishl ssa_361.w, ssa_70
>						r30 = iadd ssa_361.z, ssa_362
>						r31 = imov ssa_361.x
>						r32 = imov ssa_361.y
>						r33 = imov ssa_30
>						/* succs: block_60 */
>						loop {
>							block block_60:
>							/* preds: block_59 block_63 */
>							vec2 32 ssa_372 = intrinsic load_input (ssa_1) (32, 0) /* base=32 */ /* component=0 */	/* fastuidraw_uint_varying1 */
>							vec1 32 ssa_373 = uge32 r33, ssa_372.x
>							/* succs: block_61 block_62 */
>							if ssa_373 {
>								block block_61:
>								/* preds: block_60 */
>								break
>								/* succs: block_64 */
>							} else {
>								block block_62:
>								/* preds: block_60 */
>								/* succs: block_63 */
>							}
>							block block_63:
>							/* preds: block_62 */
>							vec1 32 ssa_374 = ffloor r28
>							vec1 32 ssa_375 = ffloor r29
>							vec1 32 ssa_376 = fadd r28, -ssa_374
>							vec1 32 ssa_377 = fadd r29, -ssa_375
>							vec1 32 ssa_378 = u2f32 r31
>							vec1 32 ssa_379 = u2f32 r32
>							vec1 32 ssa_380 = fadd ssa_376, ssa_378
>							r28 = fmul ssa_36, ssa_380
>							vec1 32 ssa_382 = fadd ssa_377, ssa_379
>							r29 = fmul ssa_36, ssa_382
>							vec1 32 ssa_384 = f2i32 r28
>							vec1 32 ssa_385 = f2i32 r29
>							vec3 32 ssa_386 = vec3 ssa_384, ssa_385, r30
>							vec4 32 ssa_387 = txf ssa_386 (coord), ssa_1 (lod), 3 (texture), 3 (sampler), 
>							vec1 32 ssa_388 = ishl ssa_387.w, ssa_70
>							r30 = iadd ssa_387.z, ssa_388
>							r33 = iadd r33, ssa_30
>							r31 = imov ssa_387.x
>							r32 = imov ssa_387.y
>							/* succs: block_60 */
>						}
>						block block_64:
>						/* preds: block_61 */
>						vec1 32 ssa_393 = ffloor r28
>						vec1 32 ssa_394 = ffloor r29
>						vec1 32 ssa_395 = fadd r28, -ssa_393
>						vec1 32 ssa_396 = fadd r29, -ssa_394
>						vec1 32 ssa_397 = u2f32 r31
>						vec1 32 ssa_398 = u2f32 r32
>						vec1 32 ssa_399 = fadd ssa_395, ssa_397
>						vec1 32 ssa_400 = fadd ssa_396, ssa_398
>						vec1 32 ssa_401 = load_const (0x3b800000 /* 0.003906 */)
>						vec1 32 ssa_402 = fmul ssa_401, ssa_399
>						vec1 32 ssa_403 = fmul ssa_401, ssa_400
>						vec1 32 ssa_404 = u2f32 r30
>						vec3 32 ssa_405 = vec3 ssa_402, ssa_403, ssa_404
>						vec4 32 ssa_406 = txl ssa_405 (coord), ssa_349 (lod), 2 (texture), 2 (sampler), 
>						r34 = imov ssa_406.x
>						r35 = imov ssa_406.y
>						r36 = imov ssa_406.z
>						r37 = imov ssa_406.w
>						/* succs: block_117 */
>					} else {
>						block block_65:
>						/* preds: block_58 */
>						vec1 32 ssa_411 = flt32 ssa_37, ssa_347
>						vec1 32 ssa_412 = ieq32 ssa_330, ssa_31
>						vec1 32 ssa_413 = ior ssa_412, ssa_411
>						/* succs: block_66 block_75 */
>						if ssa_413 {
>							block block_66:
>							/* preds: block_65 */
>							vec1 32 ssa_414 = fround_even ssa_347
>							vec1 32 ssa_415 = f2i32 ssa_414
>							vec1 32 ssa_416 = ishl ssa_30, ssa_415
>							vec1 32 ssa_417 = i2f32 ssa_416
>							vec1 32 ssa_418 = fmul ssa_37, ssa_417
>							vec1 32 ssa_419 = fmax ssa_323, ssa_418
>							vec1 32 ssa_420 = fmax ssa_326, ssa_418
>							vec1 32 ssa_421 = fadd ssa_321.x, -ssa_418
>							vec1 32 ssa_422 = fadd ssa_321.y, -ssa_418
>							vec1 32 ssa_423 = fmin ssa_419, ssa_421
>							vec1 32 ssa_424 = fmin ssa_420, ssa_422
>							vec4 32 ssa_425 = intrinsic load_input (ssa_1) (39, 0) /* base=39 */ /* component=0 */	/* fastuidraw_float_flat_varying2 */
>							r38 = ffma ssa_423, ssa_321.z, ssa_425.z
>							r39 = ffma ssa_424, ssa_321.z, ssa_425.w
>							vec1 32 ssa_428 = fmul ssa_39, r38
>							vec1 32 ssa_429 = fmul ssa_39, r39
>							vec1 32 ssa_430 = ffloor ssa_428
>							vec1 32 ssa_431 = ffloor ssa_429
>							vec1 32 ssa_432 = ffma -ssa_36, ssa_430, r38
>							vec1 32 ssa_433 = ffma -ssa_36, ssa_431, r39
>							vec1 32 ssa_434 = fmul ssa_432, ssa_321.w
>							vec1 32 ssa_435 = fmul ssa_433, ssa_321.w
>							vec1 32 ssa_436 = fmul ssa_434, ssa_57
>							vec1 32 ssa_437 = ffloor ssa_436
>							vec1 32 ssa_438 = ffma -ssa_56, ssa_437, ssa_434
>							vec1 32 ssa_439 = fmul ssa_435, ssa_57
>							vec1 32 ssa_440 = ffloor ssa_439
>							vec1 32 ssa_441 = ffma -ssa_56, ssa_440, ssa_435
>							vec1 32 ssa_442 = f2i32 r38
>							vec1 32 ssa_443 = f2i32 r39
>							vec4 32 ssa_444 = intrinsic load_input (ssa_1) (31, 0) /* base=31 */ /* component=0 */	/* fastuidraw_uint_varying0 */
>							vec3 32 ssa_445 = vec3 ssa_442, ssa_443, ssa_444.w
>							vec4 32 ssa_446 = txf ssa_445 (coord), ssa_1 (lod), 3 (texture), 3 (sampler), 
>							vec1 32 ssa_447 = ishl ssa_446.w, ssa_70
>							r40 = iadd ssa_446.z, ssa_447
>							r41 = imov ssa_446.x
>							r42 = imov ssa_446.y
>							r43 = imov ssa_30
>							/* succs: block_67 */
>							loop {
>								block block_67:
>								/* preds: block_66 block_70 */
>								vec2 32 ssa_457 = intrinsic load_input (ssa_1) (32, 0) /* base=32 */ /* component=0 */	/* fastuidraw_uint_varying1 */
>								vec1 32 ssa_458 = uge32 r43, ssa_457.x
>								/* succs: block_68 block_69 */
>								if ssa_458 {
>									block block_68:
>									/* preds: block_67 */
>									break
>									/* succs: block_71 */
>								} else {
>									block block_69:
>									/* preds: block_67 */
>									/* succs: block_70 */
>								}
>								block block_70:
>								/* preds: block_69 */
>								vec1 32 ssa_459 = ffloor r38
>								vec1 32 ssa_460 = ffloor r39
>								vec1 32 ssa_461 = fadd r38, -ssa_459
>								vec1 32 ssa_462 = fadd r39, -ssa_460
>								vec1 32 ssa_463 = u2f32 r41
>								vec1 32 ssa_464 = u2f32 r42
>								vec1 32 ssa_465 = fadd ssa_461, ssa_463
>								r38 = fmul ssa_36, ssa_465
>								vec1 32 ssa_467 = fadd ssa_462, ssa_464
>								r39 = fmul ssa_36, ssa_467
>								vec1 32 ssa_469 = f2i32 r38
>								vec1 32 ssa_470 = f2i32 r39
>								vec3 32 ssa_471 = vec3 ssa_469, ssa_470, r40
>								vec4 32 ssa_472 = txf ssa_471 (coord), ssa_1 (lod), 3 (texture), 3 (sampler), 
>								vec1 32 ssa_473 = ishl ssa_472.w, ssa_70
>								r40 = iadd ssa_472.z, ssa_473
>								r43 = iadd r43, ssa_30
>								r41 = imov ssa_472.x
>								r42 = imov ssa_472.y
>								/* succs: block_67 */
>							}
>							block block_71:
>							/* preds: block_68 */
>							vec1 32 ssa_478 = ffloor r38
>							vec1 32 ssa_479 = ffloor r39
>							vec1 32 ssa_480 = fadd r38, -ssa_478
>							vec1 32 ssa_481 = fadd r39, -ssa_479
>							vec1 32 ssa_482 = u2f32 r41
>							vec1 32 ssa_483 = u2f32 r42
>							vec1 32 ssa_484 = fadd ssa_480, ssa_482
>							vec1 32 ssa_485 = fadd ssa_481, ssa_483
>							vec1 32 ssa_486 = fmin -ssa_438, -ssa_441
>							vec1 32 ssa_487 = fadd ssa_58, ssa_486
>							vec1 32 ssa_488 = fge32 -ssa_418, -ssa_438
>							vec1 32 ssa_489 = fge32 ssa_487, ssa_418
>							vec1 32 ssa_490 = iand ssa_489, ssa_488
>							vec1 32 ssa_491 = fge32 -ssa_418, -ssa_441
>							vec1 32 ssa_492 = iand ssa_490, ssa_491
>							/* succs: block_72 block_73 */
>							if ssa_492 {
>								block block_72:
>								/* preds: block_71 */
>								vec1 32 ssa_493 = load_const (0x3b800000 /* 0.003906 */)
>								vec1 32 ssa_494 = fmul ssa_493, ssa_484
>								vec1 32 ssa_495 = fmul ssa_493, ssa_485
>								vec1 32 ssa_496 = u2f32 r40
>								vec3 32 ssa_497 = vec3 ssa_494, ssa_495, ssa_496
>								vec1 32 ssa_498 = i2f32 ssa_415
>								r44 = txl ssa_497 (coord), ssa_498 (lod), 1 (texture), 1 (sampler), 
>								/* succs: block_74 */
>							} else {
>								block block_73:
>								/* preds: block_71 */
>								vec1 32 ssa_500 = load_const (0x3b800000 /* 0.003906 */)
>								vec1 32 ssa_501 = fmul ssa_500, ssa_484
>								vec1 32 ssa_502 = fmul ssa_500, ssa_485
>								vec1 32 ssa_503 = u2f32 r40
>								vec3 32 ssa_504 = vec3 ssa_501, ssa_502, ssa_503
>								vec1 32 ssa_505 = i2f32 ssa_415
>								r44 = txl ssa_504 (coord), ssa_505 (lod), 2 (texture), 2 (sampler), 
>								/* succs: block_74 */
>							}
>							block block_74:
>							/* preds: block_72 block_73 */
>							r34 = imov r44.x
>							r35 = imov r44.y
>							r36 = imov r44.z
>							r37 = imov r44.w
>							/* succs: block_116 */
>						} else {
>							block block_75:
>							/* preds: block_65 */
>							vec1 32 ssa_512 = fmax ssa_323, ssa_33
>							vec1 32 ssa_513 = fmax ssa_326, ssa_33
>							vec1 32 ssa_514 = fadd ssa_321.x, ssa_46
>							vec1 32 ssa_515 = fadd ssa_321.y, ssa_46
>							vec1 32 ssa_516 = fmin ssa_512, ssa_514
>							vec1 32 ssa_517 = fmin ssa_513, ssa_515
>							vec4 32 ssa_518 = intrinsic load_input (ssa_1) (39, 0) /* base=39 */ /* component=0 */	/* fastuidraw_float_flat_varying2 */
>							vec1 32 ssa_519 = ffma ssa_516, ssa_321.z, ssa_518.z
>							vec1 32 ssa_520 = ffma ssa_517, ssa_321.z, ssa_518.w
>							r45 = ffma -ssa_37, ssa_321.z, ssa_519
>							r46 = ffma -ssa_37, ssa_321.z, ssa_520
>							vec1 32 ssa_523 = fadd r45, -ssa_518.z
>							vec1 32 ssa_524 = fadd r46, -ssa_518.w
>							vec1 32 ssa_525 = fmul ssa_523, ssa_321.w
>							vec1 32 ssa_526 = fmul ssa_524, ssa_321.w
>							vec1 32 ssa_527 = fmul ssa_525, ssa_57
>							vec1 32 ssa_528 = ffloor ssa_527
>							vec1 32 ssa_529 = ffma -ssa_56, ssa_528, ssa_525
>							vec1 32 ssa_530 = fadd ssa_58, -ssa_529
>							vec1 32 ssa_531 = fmul ssa_526, ssa_57
>							vec1 32 ssa_532 = ffloor ssa_531
>							vec1 32 ssa_533 = ffma -ssa_56, ssa_532, ssa_526
>							vec1 32 ssa_534 = fadd ssa_58, -ssa_533
>							vec1 32 ssa_535 = ffract ssa_525
>							vec1 32 ssa_536 = ffract ssa_526
>							vec1 32 ssa_537 = fmul ssa_535, ssa_535
>							vec1 32 ssa_538 = fmul ssa_537, ssa_535
>							vec1 32 ssa_539 = fadd ssa_35, -ssa_535
>							vec1 32 ssa_540 = fmul ssa_539, ssa_539
>							vec1 32 ssa_541 = fmul ssa_540, ssa_539
>							vec1 32 ssa_542 = fmul ssa_60, ssa_537
>							vec1 32 ssa_543 = ffma ssa_59, ssa_538, -ssa_542
>							vec1 32 ssa_544 = fadd ssa_543, ssa_36
>							vec1 32 ssa_545 = ffma ssa_59, ssa_541, ssa_36
>							vec1 32 ssa_546 = ffma -ssa_60, ssa_540, ssa_545
>							vec1 32 ssa_547 = load_const (0x3e2aaaab /* 0.166667 */)
>							vec1 32 ssa_548 = fmul ssa_544, ssa_547
>							vec1 32 ssa_549 = fmul ssa_538, ssa_547
>							vec1 32 ssa_550 = fmul ssa_536, ssa_536
>							vec1 32 ssa_551 = fmul ssa_550, ssa_536
>							vec1 32 ssa_552 = fadd ssa_35, -ssa_536
>							vec1 32 ssa_553 = fmul ssa_552, ssa_552
>							vec1 32 ssa_554 = fmul ssa_553, ssa_552
>							vec1 32 ssa_555 = fmul ssa_60, ssa_550
>							vec1 32 ssa_556 = ffma ssa_59, ssa_551, -ssa_555
>							vec1 32 ssa_557 = fadd ssa_556, ssa_36
>							vec1 32 ssa_558 = ffma ssa_59, ssa_554, ssa_36
>							vec1 32 ssa_559 = ffma -ssa_60, ssa_553, ssa_558
>							vec1 32 ssa_560 = fmul ssa_557, ssa_547
>							vec1 32 ssa_561 = fmul ssa_551, ssa_547
>							vec1 32 ssa_562 = fadd ssa_541, ssa_544
>							vec1 32 ssa_563 = fmul ssa_547, ssa_562
>							vec1 32 ssa_564 = fadd ssa_546, ssa_538
>							vec1 32 ssa_565 = fmul ssa_547, ssa_564
>							vec1 32 ssa_566 = fadd ssa_554, ssa_557
>							vec1 32 ssa_567 = fmul ssa_547, ssa_566
>							vec1 32 ssa_568 = fadd ssa_559, ssa_551
>							vec1 32 ssa_569 = fmul ssa_547, ssa_568
>							vec1 32 ssa_570 = frcp ssa_563
>							vec1 32 ssa_571 = frcp ssa_565
>							vec1 32 ssa_572 = frcp ssa_567
>							vec1 32 ssa_573 = frcp ssa_569
>							vec1 32 ssa_574 = fadd ssa_562, ssa_564
>							vec1 32 ssa_575 = fmul ssa_547, ssa_574
>							vec1 32 ssa_576 = frcp ssa_575
>							vec1 32 ssa_577 = fmul ssa_565, ssa_576
>							vec1 32 ssa_578 = fadd ssa_566, ssa_568
>							vec1 32 ssa_579 = fmul ssa_547, ssa_578
>							vec1 32 ssa_580 = frcp ssa_579
>							vec1 32 ssa_581 = fmul ssa_569, ssa_580
>							vec1 32 ssa_582 = fmax -ssa_529, -ssa_533
>							vec1 32 ssa_583 = fge32 ssa_530, ssa_62
>							vec1 32 ssa_584 = fge32 ssa_61, ssa_582
>							vec1 32 ssa_585 = iand ssa_584, ssa_583
>							vec1 32 ssa_586 = fge32 ssa_534, ssa_62
>							vec1 32 ssa_587 = iand ssa_585, ssa_586
>							/* succs: block_76 block_82 */
>							if ssa_587 {
>								block block_76:
>								/* preds: block_75 */
>								vec1 32 ssa_588 = f2i32 r45
>								vec1 32 ssa_589 = f2i32 r46
>								vec4 32 ssa_590 = intrinsic load_input (ssa_1) (31, 0) /* base=31 */ /* component=0 */	/* fastuidraw_uint_varying0 */
>								vec3 32 ssa_591 = vec3 ssa_588, ssa_589, ssa_590.w
>								vec4 32 ssa_592 = txf ssa_591 (coord), ssa_1 (lod), 3 (texture), 3 (sampler), 
>								vec1 32 ssa_593 = ishl ssa_592.w, ssa_70
>								r47 = iadd ssa_592.z, ssa_593
>								r48 = imov ssa_592.x
>								r49 = imov ssa_592.y
>								r50 = imov ssa_30
>								/* succs: block_77 */
>								loop {
>									block block_77:
>									/* preds: block_76 block_80 */
>									vec2 32 ssa_603 = intrinsic load_input (ssa_1) (32, 0) /* base=32 */ /* component=0 */	/* fastuidraw_uint_varying1 */
>									vec1 32 ssa_604 = uge32 r50, ssa_603.x
>									/* succs: block_78 block_79 */
>									if ssa_604 {
>										block block_78:
>										/* preds: block_77 */
>										break
>										/* succs: block_81 */
>									} else {
>										block block_79:
>										/* preds: block_77 */
>										/* succs: block_80 */
>									}
>									block block_80:
>									/* preds: block_79 */
>									vec1 32 ssa_605 = ffloor r45
>									vec1 32 ssa_606 = ffloor r46
>									vec1 32 ssa_607 = fadd r45, -ssa_605
>									vec1 32 ssa_608 = fadd r46, -ssa_606
>									vec1 32 ssa_609 = u2f32 r48
>									vec1 32 ssa_610 = u2f32 r49
>									vec1 32 ssa_611 = fadd ssa_607, ssa_609
>									r45 = fmul ssa_36, ssa_611
>									vec1 32 ssa_613 = fadd ssa_608, ssa_610
>									r46 = fmul ssa_36, ssa_613
>									vec1 32 ssa_615 = f2i32 r45
>									vec1 32 ssa_616 = f2i32 r46
>									vec3 32 ssa_617 = vec3 ssa_615, ssa_616, r47
>									vec4 32 ssa_618 = txf ssa_617 (coord), ssa_1 (lod), 3 (texture), 3 (sampler), 
>									vec1 32 ssa_619 = ishl ssa_618.w, ssa_70
>									r47 = iadd ssa_618.z, ssa_619
>									r50 = iadd r50, ssa_30
>									r48 = imov ssa_618.x
>									r49 = imov ssa_618.y
>									/* succs: block_77 */
>								}
>								block block_81:
>								/* preds: block_78 */
>								vec1 32 ssa_624 = ffloor r45
>								vec1 32 ssa_625 = ffloor r46
>								vec1 32 ssa_626 = fadd r45, -ssa_624
>								vec1 32 ssa_627 = fadd r46, -ssa_625
>								vec1 32 ssa_628 = u2f32 r48
>								vec1 32 ssa_629 = u2f32 r49
>								vec1 32 ssa_630 = fadd ssa_626, ssa_628
>								vec1 32 ssa_631 = fadd ssa_627, ssa_629
>								vec1 32 ssa_632 = ffma ssa_56, ssa_630, -ssa_535
>								vec1 32 ssa_633 = ffma ssa_56, ssa_631, -ssa_536
>								vec1 32 ssa_634 = fadd ssa_632, ssa_63
>								vec1 32 ssa_635 = ffma ssa_548, ssa_570, ssa_634
>								vec1 32 ssa_636 = fadd ssa_632, ssa_64
>								vec1 32 ssa_637 = ffma ssa_549, ssa_571, ssa_636
>								vec1 32 ssa_638 = fadd ssa_633, ssa_63
>								vec1 32 ssa_639 = ffma ssa_560, ssa_572, ssa_638
>								vec1 32 ssa_640 = fadd ssa_633, ssa_64
>								vec1 32 ssa_641 = ffma ssa_561, ssa_573, ssa_640
>								vec1 32 ssa_642 = fmul ssa_635, ssa_65
>								vec1 32 ssa_643 = fmul ssa_637, ssa_65
>								vec1 32 ssa_644 = fmul ssa_639, ssa_65
>								vec1 32 ssa_645 = fmul ssa_641, ssa_65
>								vec1 32 ssa_646 = u2f32 r47
>								vec3 32 ssa_647 = vec3 ssa_642, ssa_644, ssa_646
>								r51 = txl ssa_647 (coord), ssa_1 (lod), 1 (texture), 1 (sampler), 
>								vec3 32 ssa_649 = vec3 ssa_643, ssa_644, ssa_646
>								r52 = txl ssa_649 (coord), ssa_1 (lod), 1 (texture), 1 (sampler), 
>								vec3 32 ssa_651 = vec3 ssa_642, ssa_645, ssa_646
>								r53 = txl ssa_651 (coord), ssa_1 (lod), 1 (texture), 1 (sampler), 
>								vec3 32 ssa_653 = vec3 ssa_643, ssa_645, ssa_646
>								r54 = txl ssa_653 (coord), ssa_1 (lod), 1 (texture), 1 (sampler), 
>								/* succs: block_115 */
>							} else {
>								block block_82:
>								/* preds: block_75 */
>								vec1 32 ssa_655 = ffma -ssa_535, ssa_321.z, r45
>								vec1 32 ssa_656 = ffma -ssa_536, ssa_321.z, r46
>								vec1 32 ssa_657 = ffma -ssa_37, ssa_321.z, ssa_655
>								vec1 32 ssa_658 = ffma -ssa_37, ssa_321.z, ssa_656
>								vec1 32 ssa_659 = ffma ssa_64, ssa_321.z, ssa_655
>								vec1 32 ssa_660 = ffma ssa_64, ssa_321.z, ssa_656
>								vec1 32 ssa_661 = fmul ssa_548, ssa_570
>								vec1 32 ssa_662 = fmul ssa_549, ssa_571
>								vec1 32 ssa_663 = fmul ssa_560, ssa_572
>								vec1 32 ssa_664 = fmul ssa_561, ssa_573
>								r55 = ffma ssa_661, ssa_321.z, ssa_657
>								r56 = ffma ssa_662, ssa_321.z, ssa_659
>								r57 = ffma ssa_663, ssa_321.z, ssa_658
>								r58 = ffma ssa_664, ssa_321.z, ssa_660
>								vec1 32 ssa_669 = fmul ssa_39, r55
>								vec1 32 ssa_670 = fmul ssa_39, r57
>								vec1 32 ssa_671 = ffloor ssa_669
>								vec1 32 ssa_672 = ffloor ssa_670
>								vec1 32 ssa_673 = ffma -ssa_36, ssa_671, r55
>								vec1 32 ssa_674 = ffma -ssa_36, ssa_672, r57
>								vec1 32 ssa_675 = fmul ssa_673, ssa_321.w
>								vec1 32 ssa_676 = fmul ssa_674, ssa_321.w
>								vec1 32 ssa_677 = fmul ssa_675, ssa_57
>								vec1 32 ssa_678 = ffloor ssa_677
>								vec1 32 ssa_679 = ffma -ssa_56, ssa_678, ssa_675
>								vec1 32 ssa_680 = fadd ssa_58, -ssa_679
>								vec1 32 ssa_681 = fmul ssa_676, ssa_57
>								vec1 32 ssa_682 = ffloor ssa_681
>								vec1 32 ssa_683 = ffma -ssa_56, ssa_682, ssa_676
>								vec1 32 ssa_684 = fadd ssa_58, -ssa_683
>								vec1 32 ssa_685 = f2i32 r55
>								vec1 32 ssa_686 = f2i32 r57
>								vec4 32 ssa_687 = intrinsic load_input (ssa_1) (31, 0) /* base=31 */ /* component=0 */	/* fastuidraw_uint_varying0 */
>								vec3 32 ssa_688 = vec3 ssa_685, ssa_686, ssa_687.w
>								vec4 32 ssa_689 = txf ssa_688 (coord), ssa_1 (lod), 3 (texture), 3 (sampler), 
>								vec1 32 ssa_690 = ishl ssa_689.w, ssa_70
>								r59 = iadd ssa_689.z, ssa_690
>								r60 = imov ssa_689.x
>								r61 = imov ssa_689.y
>								r64 = imov ssa_30
>								r63 = imov r57
>								r62 = imov r55
>								/* succs: block_83 */
>								loop {
>									block block_83:
>									/* preds: block_82 block_86 */
>									vec2 32 ssa_700 = intrinsic load_input (ssa_1) (32, 0) /* base=32 */ /* component=0 */	/* fastuidraw_uint_varying1 */
>									vec1 32 ssa_701 = uge32 r64, ssa_700.x
>									/* succs: block_84 block_85 */
>									if ssa_701 {
>										block block_84:
>										/* preds: block_83 */
>										break
>										/* succs: block_87 */
>									} else {
>										block block_85:
>										/* preds: block_83 */
>										/* succs: block_86 */
>									}
>									block block_86:
>									/* preds: block_85 */
>									vec1 32 ssa_702 = ffloor r62
>									vec1 32 ssa_703 = ffloor r63
>									vec1 32 ssa_704 = fadd r62, -ssa_702
>									vec1 32 ssa_705 = fadd r63, -ssa_703
>									vec1 32 ssa_706 = u2f32 r60
>									vec1 32 ssa_707 = u2f32 r61
>									vec1 32 ssa_708 = fadd ssa_704, ssa_706
>									r62 = fmul ssa_36, ssa_708
>									vec1 32 ssa_710 = fadd ssa_705, ssa_707
>									r63 = fmul ssa_36, ssa_710
>									vec1 32 ssa_712 = f2i32 r62
>									vec1 32 ssa_713 = f2i32 r63
>									vec3 32 ssa_714 = vec3 ssa_712, ssa_713, r59
>									vec4 32 ssa_715 = txf ssa_714 (coord), ssa_1 (lod), 3 (texture), 3 (sampler), 
>									vec1 32 ssa_716 = ishl ssa_715.w, ssa_70
>									r59 = iadd ssa_715.z, ssa_716
>									r64 = iadd r64, ssa_30
>									r60 = imov ssa_715.x
>									r61 = imov ssa_715.y
>									/* succs: block_83 */
>								}
>								block block_87:
>								/* preds: block_84 */
>								vec1 32 ssa_721 = ffloor r62
>								vec1 32 ssa_722 = ffloor r63
>								vec1 32 ssa_723 = fadd r62, -ssa_721
>								vec1 32 ssa_724 = fadd r63, -ssa_722
>								vec1 32 ssa_725 = u2f32 r60
>								vec1 32 ssa_726 = u2f32 r61
>								vec1 32 ssa_727 = fadd ssa_723, ssa_725
>								vec1 32 ssa_728 = fadd ssa_724, ssa_726
>								vec1 32 ssa_729 = fge32 ssa_684, ssa_37
>								vec1 32 ssa_730 = fge32 ssa_680, ssa_37
>								vec1 32 ssa_731 = iand ssa_730, ssa_729
>								vec1 32 ssa_732 = fge32 ssa_63, -ssa_679
>								vec1 32 ssa_733 = iand ssa_731, ssa_732
>								vec1 32 ssa_734 = fge32 ssa_63, -ssa_683
>								vec1 32 ssa_735 = iand ssa_733, ssa_734
>								/* succs: block_88 block_89 */
>								if ssa_735 {
>									block block_88:
>									/* preds: block_87 */
>									vec1 32 ssa_736 = load_const (0x3b800000 /* 0.003906 */)
>									vec1 32 ssa_737 = fmul ssa_736, ssa_727
>									vec1 32 ssa_738 = fmul ssa_736, ssa_728
>									vec1 32 ssa_739 = u2f32 r59
>									vec3 32 ssa_740 = vec3 ssa_737, ssa_738, ssa_739
>									r51 = txl ssa_740 (coord), ssa_1 (lod), 1 (texture), 1 (sampler), 
>									/* succs: block_90 */
>								} else {
>									block block_89:
>									/* preds: block_87 */
>									vec1 32 ssa_742 = load_const (0x3b800000 /* 0.003906 */)
>									vec1 32 ssa_743 = fmul ssa_742, ssa_727
>									vec1 32 ssa_744 = fmul ssa_742, ssa_728
>									vec1 32 ssa_745 = u2f32 r59
>									vec3 32 ssa_746 = vec3 ssa_743, ssa_744, ssa_745
>									r51 = txl ssa_746 (coord), ssa_1 (lod), 2 (texture), 2 (sampler), 
>									/* succs: block_90 */
>								}
>								block block_90:
>								/* preds: block_88 block_89 */
>								vec1 32 ssa_749 = fmul ssa_39, r56
>								vec1 32 ssa_750 = ffloor ssa_749
>								vec1 32 ssa_751 = ffma -ssa_36, ssa_750, r56
>								vec1 32 ssa_752 = fmul ssa_751, ssa_321.w
>								vec1 32 ssa_753 = fmul ssa_752, ssa_57
>								vec1 32 ssa_754 = ffloor ssa_753
>								vec1 32 ssa_755 = ffma -ssa_56, ssa_754, ssa_752
>								vec1 32 ssa_756 = fadd ssa_58, -ssa_755
>								vec1 32 ssa_757 = f2i32 r56
>								vec3 32 ssa_758 = vec3 ssa_757, ssa_686, ssa_687.w
>								vec4 32 ssa_759 = txf ssa_758 (coord), ssa_1 (lod), 3 (texture), 3 (sampler), 
>								vec1 32 ssa_760 = ishl ssa_759.w, ssa_70
>								r65 = iadd ssa_759.z, ssa_760
>								r66 = imov ssa_759.x
>								r67 = imov ssa_759.y
>								r69 = imov ssa_30
>								r68 = imov r56
>								/* succs: block_91 */
>								loop {
>									block block_91:
>									/* preds: block_90 block_94 */
>									vec1 32 ssa_770 = uge32 r69, ssa_700.x
>									/* succs: block_92 block_93 */
>									if ssa_770 {
>										block block_92:
>										/* preds: block_91 */
>										break
>										/* succs: block_95 */
>									} else {
>										block block_93:
>										/* preds: block_91 */
>										/* succs: block_94 */
>									}
>									block block_94:
>									/* preds: block_93 */
>									vec1 32 ssa_771 = ffloor r68
>									vec1 32 ssa_772 = ffloor r57
>									vec1 32 ssa_773 = fadd r68, -ssa_771
>									vec1 32 ssa_774 = fadd r57, -ssa_772
>									vec1 32 ssa_775 = u2f32 r66
>									vec1 32 ssa_776 = u2f32 r67
>									vec1 32 ssa_777 = fadd ssa_773, ssa_775
>									r68 = fmul ssa_36, ssa_777
>									vec1 32 ssa_779 = fadd ssa_774, ssa_776
>									r57 = fmul ssa_36, ssa_779
>									vec1 32 ssa_781 = f2i32 r68
>									vec1 32 ssa_782 = f2i32 r57
>									vec3 32 ssa_783 = vec3 ssa_781, ssa_782, r65
>									vec4 32 ssa_784 = txf ssa_783 (coord), ssa_1 (lod), 3 (texture), 3 (sampler), 
>									vec1 32 ssa_785 = ishl ssa_784.w, ssa_70
>									r65 = iadd ssa_784.z, ssa_785
>									r69 = iadd r69, ssa_30
>									r66 = imov ssa_784.x
>									r67 = imov ssa_784.y
>									/* succs: block_91 */
>								}
>								block block_95:
>								/* preds: block_92 */
>								vec1 32 ssa_790 = ffloor r68
>								vec1 32 ssa_791 = ffloor r57
>								vec1 32 ssa_792 = fadd r68, -ssa_790
>								vec1 32 ssa_793 = fadd r57, -ssa_791
>								vec1 32 ssa_794 = u2f32 r66
>								vec1 32 ssa_795 = u2f32 r67
>								vec1 32 ssa_796 = fadd ssa_792, ssa_794
>								vec1 32 ssa_797 = fadd ssa_793, ssa_795
>								vec1 32 ssa_798 = fge32 ssa_756, ssa_37
>								vec1 32 ssa_799 = iand ssa_798, ssa_729
>								vec1 32 ssa_800 = fge32 ssa_63, -ssa_755
>								vec1 32 ssa_801 = iand ssa_799, ssa_800
>								vec1 32 ssa_802 = iand ssa_801, ssa_734
>								/* succs: block_96 block_97 */
>								if ssa_802 {
>									block block_96:
>									/* preds: block_95 */
>									vec1 32 ssa_803 = load_const (0x3b800000 /* 0.003906 */)
>									vec1 32 ssa_804 = fmul ssa_803, ssa_796
>									vec1 32 ssa_805 = fmul ssa_803, ssa_797
>									vec1 32 ssa_806 = u2f32 r65
>									vec3 32 ssa_807 = vec3 ssa_804, ssa_805, ssa_806
>									r52 = txl ssa_807 (coord), ssa_1 (lod), 1 (texture), 1 (sampler), 
>									/* succs: block_98 */
>								} else {
>									block block_97:
>									/* preds: block_95 */
>									vec1 32 ssa_809 = load_const (0x3b800000 /* 0.003906 */)
>									vec1 32 ssa_810 = fmul ssa_809, ssa_796
>									vec1 32 ssa_811 = fmul ssa_809, ssa_797
>									vec1 32 ssa_812 = u2f32 r65
>									vec3 32 ssa_813 = vec3 ssa_810, ssa_811, ssa_812
>									r52 = txl ssa_813 (coord), ssa_1 (lod), 2 (texture), 2 (sampler), 
>									/* succs: block_98 */
>								}
>								block block_98:
>								/* preds: block_96 block_97 */
>								vec1 32 ssa_816 = fmul ssa_39, r58
>								vec1 32 ssa_817 = ffloor ssa_816
>								vec1 32 ssa_818 = ffma -ssa_36, ssa_817, r58
>								vec1 32 ssa_819 = fmul ssa_818, ssa_321.w
>								vec1 32 ssa_820 = fmul ssa_819, ssa_57
>								vec1 32 ssa_821 = ffloor ssa_820
>								vec1 32 ssa_822 = ffma -ssa_56, ssa_821, ssa_819
>								vec1 32 ssa_823 = fadd ssa_58, -ssa_822
>								vec1 32 ssa_824 = f2i32 r58
>								vec3 32 ssa_825 = vec3 ssa_685, ssa_824, ssa_687.w
>								vec4 32 ssa_826 = txf ssa_825 (coord), ssa_1 (lod), 3 (texture), 3 (sampler), 
>								vec1 32 ssa_827 = ishl ssa_826.w, ssa_70
>								r70 = iadd ssa_826.z, ssa_827
>								r71 = imov ssa_826.x
>								r72 = imov ssa_826.y
>								r74 = imov ssa_30
>								r73 = imov r58
>								/* succs: block_99 */
>								loop {
>									block block_99:
>									/* preds: block_98 block_102 */
>									vec1 32 ssa_837 = uge32 r74, ssa_700.x
>									/* succs: block_100 block_101 */
>									if ssa_837 {
>										block block_100:
>										/* preds: block_99 */
>										break
>										/* succs: block_103 */
>									} else {
>										block block_101:
>										/* preds: block_99 */
>										/* succs: block_102 */
>									}
>									block block_102:
>									/* preds: block_101 */
>									vec1 32 ssa_838 = ffloor r55
>									vec1 32 ssa_839 = ffloor r73
>									vec1 32 ssa_840 = fadd r55, -ssa_838
>									vec1 32 ssa_841 = fadd r73, -ssa_839
>									vec1 32 ssa_842 = u2f32 r71
>									vec1 32 ssa_843 = u2f32 r72
>									vec1 32 ssa_844 = fadd ssa_840, ssa_842
>									r55 = fmul ssa_36, ssa_844
>									vec1 32 ssa_846 = fadd ssa_841, ssa_843
>									r73 = fmul ssa_36, ssa_846
>									vec1 32 ssa_848 = f2i32 r55
>									vec1 32 ssa_849 = f2i32 r73
>									vec3 32 ssa_850 = vec3 ssa_848, ssa_849, r70
>									vec4 32 ssa_851 = txf ssa_850 (coord), ssa_1 (lod), 3 (texture), 3 (sampler), 
>									vec1 32 ssa_852 = ishl ssa_851.w, ssa_70
>									r70 = iadd ssa_851.z, ssa_852
>									r74 = iadd r74, ssa_30
>									r71 = imov ssa_851.x
>									r72 = imov ssa_851.y
>									/* succs: block_99 */
>								}
>								block block_103:
>								/* preds: block_100 */
>								vec1 32 ssa_857 = ffloor r55
>								vec1 32 ssa_858 = ffloor r73
>								vec1 32 ssa_859 = fadd r55, -ssa_857
>								vec1 32 ssa_860 = fadd r73, -ssa_858
>								vec1 32 ssa_861 = u2f32 r71
>								vec1 32 ssa_862 = u2f32 r72
>								vec1 32 ssa_863 = fadd ssa_859, ssa_861
>								vec1 32 ssa_864 = fadd ssa_860, ssa_862
>								vec1 32 ssa_865 = fge32 ssa_823, ssa_37
>								vec1 32 ssa_866 = iand ssa_730, ssa_865
>								vec1 32 ssa_867 = iand ssa_866, ssa_732
>								vec1 32 ssa_868 = fge32 ssa_63, -ssa_822
>								vec1 32 ssa_869 = iand ssa_867, ssa_868
>								/* succs: block_104 block_105 */
>								if ssa_869 {
>									block block_104:
>									/* preds: block_103 */
>									vec1 32 ssa_870 = load_const (0x3b800000 /* 0.003906 */)
>									vec1 32 ssa_871 = fmul ssa_870, ssa_863
>									vec1 32 ssa_872 = fmul ssa_870, ssa_864
>									vec1 32 ssa_873 = u2f32 r70
>									vec3 32 ssa_874 = vec3 ssa_871, ssa_872, ssa_873
>									r53 = txl ssa_874 (coord), ssa_1 (lod), 1 (texture), 1 (sampler), 
>									/* succs: block_106 */
>								} else {
>									block block_105:
>									/* preds: block_103 */
>									vec1 32 ssa_876 = load_const (0x3b800000 /* 0.003906 */)
>									vec1 32 ssa_877 = fmul ssa_876, ssa_863
>									vec1 32 ssa_878 = fmul ssa_876, ssa_864
>									vec1 32 ssa_879 = u2f32 r70
>									vec3 32 ssa_880 = vec3 ssa_877, ssa_878, ssa_879
>									r53 = txl ssa_880 (coord), ssa_1 (lod), 2 (texture), 2 (sampler), 
>									/* succs: block_106 */
>								}
>								block block_106:
>								/* preds: block_104 block_105 */
>								vec3 32 ssa_883 = vec3 ssa_757, ssa_824, ssa_687.w
>								vec4 32 ssa_884 = txf ssa_883 (coord), ssa_1 (lod), 3 (texture), 3 (sampler), 
>								vec1 32 ssa_885 = ishl ssa_884.w, ssa_70
>								r75 = iadd ssa_884.z, ssa_885
>								r76 = imov ssa_884.x
>								r77 = imov ssa_884.y
>								r78 = imov ssa_30
>								/* succs: block_107 */
>								loop {
>									block block_107:
>									/* preds: block_106 block_110 */
>									vec1 32 ssa_895 = uge32 r78, ssa_700.x
>									/* succs: block_108 block_109 */
>									if ssa_895 {
>										block block_108:
>										/* preds: block_107 */
>										break
>										/* succs: block_111 */
>									} else {
>										block block_109:
>										/* preds: block_107 */
>										/* succs: block_110 */
>									}
>									block block_110:
>									/* preds: block_109 */
>									vec1 32 ssa_896 = ffloor r56
>									vec1 32 ssa_897 = ffloor r58
>									vec1 32 ssa_898 = fadd r56, -ssa_896
>									vec1 32 ssa_899 = fadd r58, -ssa_897
>									vec1 32 ssa_900 = u2f32 r76
>									vec1 32 ssa_901 = u2f32 r77
>									vec1 32 ssa_902 = fadd ssa_898, ssa_900
>									r56 = fmul ssa_36, ssa_902
>									vec1 32 ssa_904 = fadd ssa_899, ssa_901
>									r58 = fmul ssa_36, ssa_904
>									vec1 32 ssa_906 = f2i32 r56
>									vec1 32 ssa_907 = f2i32 r58
>									vec3 32 ssa_908 = vec3 ssa_906, ssa_907, r75
>									vec4 32 ssa_909 = txf ssa_908 (coord), ssa_1 (lod), 3 (texture), 3 (sampler), 
>									vec1 32 ssa_910 = ishl ssa_909.w, ssa_70
>									r75 = iadd ssa_909.z, ssa_910
>									r78 = iadd r78, ssa_30
>									r76 = imov ssa_909.x
>									r77 = imov ssa_909.y
>									/* succs: block_107 */
>								}
>								block block_111:
>								/* preds: block_108 */
>								vec1 32 ssa_915 = ffloor r56
>								vec1 32 ssa_916 = ffloor r58
>								vec1 32 ssa_917 = fadd r56, -ssa_915
>								vec1 32 ssa_918 = fadd r58, -ssa_916
>								vec1 32 ssa_919 = u2f32 r76
>								vec1 32 ssa_920 = u2f32 r77
>								vec1 32 ssa_921 = fadd ssa_917, ssa_919
>								vec1 32 ssa_922 = fadd ssa_918, ssa_920
>								vec1 32 ssa_923 = iand ssa_798, ssa_865
>								vec1 32 ssa_924 = iand ssa_923, ssa_800
>								vec1 32 ssa_925 = iand ssa_924, ssa_868
>								/* succs: block_112 block_113 */
>								if ssa_925 {
>									block block_112:
>									/* preds: block_111 */
>									vec1 32 ssa_926 = load_const (0x3b800000 /* 0.003906 */)
>									vec1 32 ssa_927 = fmul ssa_926, ssa_921
>									vec1 32 ssa_928 = fmul ssa_926, ssa_922
>									vec1 32 ssa_929 = u2f32 r75
>									vec3 32 ssa_930 = vec3 ssa_927, ssa_928, ssa_929
>									r54 = txl ssa_930 (coord), ssa_1 (lod), 1 (texture), 1 (sampler), 
>									/* succs: block_114 */
>								} else {
>									block block_113:
>									/* preds: block_111 */
>									vec1 32 ssa_932 = load_const (0x3b800000 /* 0.003906 */)
>									vec1 32 ssa_933 = fmul ssa_932, ssa_921
>									vec1 32 ssa_934 = fmul ssa_932, ssa_922
>									vec1 32 ssa_935 = u2f32 r75
>									vec3 32 ssa_936 = vec3 ssa_933, ssa_934, ssa_935
>									r54 = txl ssa_936 (coord), ssa_1 (lod), 2 (texture), 2 (sampler), 
>									/* succs: block_114 */
>								}
>								block block_114:
>								/* preds: block_112 block_113 */
>								/* succs: block_115 */
>							}
>							block block_115:
>							/* preds: block_81 block_114 */
>							vec1 32 ssa_943 = flrp r51.x, r52.x, ssa_577
>							vec1 32 ssa_944 = flrp r51.y, r52.y, ssa_577
>							vec1 32 ssa_945 = flrp r51.z, r52.z, ssa_577
>							vec1 32 ssa_946 = flrp r51.w, r52.w, ssa_577
>							vec1 32 ssa_947 = flrp r53.x, r54.x, ssa_577
>							vec1 32 ssa_948 = flrp r53.y, r54.y, ssa_577
>							vec1 32 ssa_949 = flrp r53.z, r54.z, ssa_577
>							vec1 32 ssa_950 = flrp r53.w, r54.w, ssa_577
>							r34 = flrp ssa_943, ssa_947, ssa_581
>							r35 = flrp ssa_944, ssa_948, ssa_581
>							r36 = flrp ssa_945, ssa_949, ssa_581
>							r37 = flrp ssa_946, ssa_950, ssa_581
>							/* succs: block_116 */
>						}
>						block block_116:
>						/* preds: block_74 block_115 */
>						/* succs: block_117 */
>					}
>					block block_117:
>					/* preds: block_64 block_116 */
>					/* succs: block_128 */
>				} else {
>					block block_118:
>					/* preds: block_57 */
>					vec1 32 ssa_963 = ine32 ssa_328, ssa_30
>					/* succs: block_119 block_126 */
>					if ssa_963 {
>						block block_119:
>						/* preds: block_118 */
>						vec4 32 ssa_964 = intrinsic load_input (ssa_1) (39, 0) /* base=39 */ /* component=0 */	/* fastuidraw_float_flat_varying2 */
>						vec1 32 ssa_965 = fadd ssa_323, ssa_964.z
>						vec1 32 ssa_966 = fadd ssa_326, ssa_964.w
>						vec1 32 ssa_967 = ieq32 ssa_330, ssa_30
>						/* succs: block_120 block_121 */
>						if ssa_967 {
>							block block_120:
>							/* preds: block_119 */
>							vec1 32 ssa_968 = fceil r27
>							vec1 32 ssa_969 = f2i32 ssa_968
>							vec1 32 ssa_970 = ishl ssa_30, ssa_969
>							vec1 32 ssa_971 = i2f32 ssa_970
>							vec1 32 ssa_972 = frcp ssa_971
>							vec1 32 ssa_973 = fmul ssa_965, ssa_972
>							vec1 32 ssa_974 = fmul ssa_966, ssa_972
>							vec1 32 ssa_975 = f2i32 ssa_973
>							vec1 32 ssa_976 = f2i32 ssa_974
>							vec2 32 ssa_977 = vec2 ssa_975, ssa_976
>							vec4 32 ssa_978 = txf ssa_977 (coord), ssa_969 (lod), 4 (texture), 4 (sampler), 
>							r34 = imov ssa_978.x
>							r35 = imov ssa_978.y
>							r36 = imov ssa_978.z
>							r37 = imov ssa_978.w
>							/* succs: block_125 */
>						} else {
>							block block_121:
>							/* preds: block_119 */
>							vec1 32 ssa_983 = flt32 ssa_37, r27
>							vec1 32 ssa_984 = ieq32 ssa_330, ssa_31
>							vec1 32 ssa_985 = ior ssa_984, ssa_983
>							/* succs: block_122 block_123 */
>							if ssa_985 {
>								block block_122:
>								/* preds: block_121 */
>								vec2 32 ssa_986 = txs ssa_1 (lod), 4 (texture), 4 (sampler), 
>								vec1 32 ssa_987 = i2f32 ssa_986.x
>								vec1 32 ssa_988 = i2f32 ssa_986.y
>								vec1 32 ssa_989 = frcp ssa_987
>								vec1 32 ssa_990 = frcp ssa_988
>								vec1 32 ssa_991 = fmul ssa_965, ssa_989
>								vec1 32 ssa_992 = fmul ssa_966, ssa_990
>								vec2 32 ssa_993 = vec2 ssa_991, ssa_992
>								vec4 32 ssa_994 = txl ssa_993 (coord), r27 (lod), 4 (texture), 4 (sampler), 
>								r34 = imov ssa_994.x
>								r35 = imov ssa_994.y
>								r36 = imov ssa_994.z
>								r37 = imov ssa_994.w
>								/* succs: block_124 */
>							} else {
>								block block_123:
>								/* preds: block_121 */
>								vec1 32 ssa_999 = fadd ssa_965, ssa_63
>								vec1 32 ssa_1000 = fadd ssa_966, ssa_63
>								vec1 32 ssa_1001 = ffract ssa_999
>								vec1 32 ssa_1002 = ffract ssa_1000
>								vec1 32 ssa_1003 = ffloor ssa_999
>								vec1 32 ssa_1004 = ffloor ssa_1000
>								vec1 32 ssa_1005 = fmul ssa_1001, ssa_1001
>								vec1 32 ssa_1006 = fmul ssa_1005, ssa_1001
>								vec1 32 ssa_1007 = fadd ssa_35, -ssa_1001
>								vec1 32 ssa_1008 = fmul ssa_1007, ssa_1007
>								vec1 32 ssa_1009 = fmul ssa_1008, ssa_1007
>								vec1 32 ssa_1010 = fmul ssa_60, ssa_1005
>								vec1 32 ssa_1011 = ffma ssa_59, ssa_1006, -ssa_1010
>								vec1 32 ssa_1012 = fadd ssa_1011, ssa_36
>								vec1 32 ssa_1013 = ffma ssa_59, ssa_1009, ssa_36
>								vec1 32 ssa_1014 = ffma -ssa_60, ssa_1008, ssa_1013
>								vec1 32 ssa_1015 = load_const (0x3e2aaaab /* 0.166667 */)
>								vec1 32 ssa_1016 = fmul ssa_1002, ssa_1002
>								vec1 32 ssa_1017 = fmul ssa_1016, ssa_1002
>								vec1 32 ssa_1018 = fadd ssa_35, -ssa_1002
>								vec1 32 ssa_1019 = fmul ssa_1018, ssa_1018
>								vec1 32 ssa_1020 = fmul ssa_1019, ssa_1018
>								vec1 32 ssa_1021 = fmul ssa_60, ssa_1016
>								vec1 32 ssa_1022 = ffma ssa_59, ssa_1017, -ssa_1021
>								vec1 32 ssa_1023 = fadd ssa_1022, ssa_36
>								vec1 32 ssa_1024 = ffma ssa_59, ssa_1020, ssa_36
>								vec1 32 ssa_1025 = ffma -ssa_60, ssa_1019, ssa_1024
>								vec1 32 ssa_1026 = fadd ssa_1009, ssa_1012
>								vec1 32 ssa_1027 = fmul ssa_1015, ssa_1026
>								vec1 32 ssa_1028 = fadd ssa_1014, ssa_1006
>								vec1 32 ssa_1029 = fmul ssa_1015, ssa_1028
>								vec1 32 ssa_1030 = fadd ssa_1020, ssa_1023
>								vec1 32 ssa_1031 = fmul ssa_1015, ssa_1030
>								vec1 32 ssa_1032 = fadd ssa_1025, ssa_1017
>								vec1 32 ssa_1033 = fmul ssa_1015, ssa_1032
>								vec1 32 ssa_1034 = frcp ssa_1027
>								vec1 32 ssa_1035 = frcp ssa_1029
>								vec1 32 ssa_1036 = frcp ssa_1031
>								vec1 32 ssa_1037 = frcp ssa_1033
>								vec1 32 ssa_1038 = fmul ssa_1012, ssa_1015
>								vec1 32 ssa_1039 = fmul ssa_1006, ssa_1015
>								vec1 32 ssa_1040 = fmul ssa_1023, ssa_1015
>								vec1 32 ssa_1041 = fmul ssa_1017, ssa_1015
>								vec1 32 ssa_1042 = fadd ssa_1003, ssa_63
>								vec1 32 ssa_1043 = ffma ssa_1038, ssa_1034, ssa_1042
>								vec1 32 ssa_1044 = fadd ssa_1003, ssa_64
>								vec1 32 ssa_1045 = ffma ssa_1039, ssa_1035, ssa_1044
>								vec1 32 ssa_1046 = fadd ssa_1004, ssa_63
>								vec1 32 ssa_1047 = ffma ssa_1040, ssa_1036, ssa_1046
>								vec1 32 ssa_1048 = fadd ssa_1004, ssa_64
>								vec1 32 ssa_1049 = ffma ssa_1041, ssa_1037, ssa_1048
>								vec2 32 ssa_1050 = txs ssa_1 (lod), 4 (texture), 4 (sampler), 
>								vec1 32 ssa_1051 = i2f32 ssa_1050.x
>								vec1 32 ssa_1052 = i2f32 ssa_1050.y
>								vec1 32 ssa_1053 = frcp ssa_1051
>								vec1 32 ssa_1054 = frcp ssa_1052
>								vec1 32 ssa_1055 = fmul ssa_1043, ssa_1053
>								vec1 32 ssa_1056 = fmul ssa_1045, ssa_1054
>								vec1 32 ssa_1057 = fmul ssa_1047, ssa_1053
>								vec1 32 ssa_1058 = fmul ssa_1049, ssa_1054
>								vec1 32 ssa_1059 = fadd ssa_1026, ssa_1028
>								vec1 32 ssa_1060 = fmul ssa_1015, ssa_1059
>								vec1 32 ssa_1061 = frcp ssa_1060
>								vec1 32 ssa_1062 = fmul ssa_1029, ssa_1061
>								vec1 32 ssa_1063 = fadd ssa_1030, ssa_1032
>								vec1 32 ssa_1064 = fmul ssa_1015, ssa_1063
>								vec1 32 ssa_1065 = frcp ssa_1064
>								vec1 32 ssa_1066 = fmul ssa_1033, ssa_1065
>								vec2 32 ssa_1067 = vec2 ssa_1055, ssa_1057
>								vec4 32 ssa_1068 = txl ssa_1067 (coord), ssa_1 (lod), 4 (texture), 4 (sampler), 
>								vec2 32 ssa_1069 = vec2 ssa_1056, ssa_1057
>								vec4 32 ssa_1070 = txl ssa_1069 (coord), ssa_1 (lod), 4 (texture), 4 (sampler), 
>								vec1 32 ssa_1071 = flrp ssa_1068.x, ssa_1070.x, ssa_1062
>								vec1 32 ssa_1072 = flrp ssa_1068.y, ssa_1070.y, ssa_1062
>								vec1 32 ssa_1073 = flrp ssa_1068.z, ssa_1070.z, ssa_1062
>								vec1 32 ssa_1074 = flrp ssa_1068.w, ssa_1070.w, ssa_1062
>								vec2 32 ssa_1075 = vec2 ssa_1055, ssa_1058
>								vec4 32 ssa_1076 = txl ssa_1075 (coord), ssa_1 (lod), 4 (texture), 4 (sampler), 
>								vec2 32 ssa_1077 = vec2 ssa_1056, ssa_1058
>								vec4 32 ssa_1078 = txl ssa_1077 (coord), ssa_1 (lod), 4 (texture), 4 (sampler), 
>								vec1 32 ssa_1079 = flrp ssa_1076.x, ssa_1078.x, ssa_1062
>								vec1 32 ssa_1080 = flrp ssa_1076.y, ssa_1078.y, ssa_1062
>								vec1 32 ssa_1081 = flrp ssa_1076.z, ssa_1078.z, ssa_1062
>								vec1 32 ssa_1082 = flrp ssa_1076.w, ssa_1078.w, ssa_1062
>								r34 = flrp ssa_1071, ssa_1079, ssa_1066
>								r35 = flrp ssa_1072, ssa_1080, ssa_1066
>								r36 = flrp ssa_1073, ssa_1081, ssa_1066
>								r37 = flrp ssa_1074, ssa_1082, ssa_1066
>								/* succs: block_124 */
>							}
>							block block_124:
>							/* preds: block_122 block_123 */
>							/* succs: block_125 */
>						}
>						block block_125:
>						/* preds: block_120 block_124 */
>						/* succs: block_127 */
>					} else {
>						block block_126:
>						/* preds: block_118 */
>						r37 = imov ssa_35
>						r36 = imov r37
>						r35 = imov r36
>						r34 = imov r35
>						/* succs: block_127 */
>					}
>					block block_127:
>					/* preds: block_125 block_126 */
>					/* succs: block_128 */
>				}
>				block block_128:
>				/* preds: block_117 block_127 */
>				vec1 32 ssa_1103 = iand ssa_92.y, ssa_66
>				vec1 32 ssa_1104 = ieq32 ssa_1103, ssa_1
>				/* succs: block_129 block_130 */
>				if ssa_1104 {
>					block block_129:
>					/* preds: block_128 */
>					r34 = fmul r34, r37
>					r35 = fmul r35, r37
>					r36 = fmul r36, r37
>					/* succs: block_131 */
>				} else {
>					block block_130:
>					/* preds: block_128 */
>					/* succs: block_131 */
>				}
>				block block_131:
>				/* preds: block_129 block_130 */
>				r17 = fmul r17, r34
>				r16 = fmul r16, r35
>				r15 = fmul r15, r36
>				r14 = fmul r14, r37
>				/* succs: block_133 */
>			} else {
>				block block_132:
>				/* preds: block_53 */
>				/* succs: block_133 */
>			}
>			block block_133:
>			/* preds: block_131 block_132 */
>			/* succs: block_135 */
>		} else {
>			block block_134:
>			/* preds: block_1 */
>			/* succs: block_135 */
>		}
>		block block_135:
>		/* preds: block_133 block_134 */
>		vec2 32 ssa_1123 = intrinsic load_input (ssa_1) (32, 0) /* base=32 */ /* component=0 */	/* fastuidraw_uint_varying1 */
>		vec1 32 ssa_1124 = ult32 ssa_1123.y, ssa_67
>		vec1 32 ssa_1125 = uge32 ssa_1123.y, ssa_31
>		vec1 32 ssa_1126 = iand ssa_1125, ssa_1124
>		/* succs: block_136 block_137 */
>		if ssa_1126 {
>			block block_136:
>			/* preds: block_135 */
>			vec4 32 ssa_1127 = intrinsic load_uniform (ssa_1) (0, 16) /* base=0 */ /* range=16 */	/* fastuidraw_painterStore */
>			vec4 32 ssa_1128 = load_const (0x3f000000 /* 0.500000 */, 0x3f000000 /* 0.500000 */, 0x00000000 /* 0.000000 */, 0x00000000 /* 0.000000 */)
>			vec1 32 ssa_1129 = fadd ssa_4.x, ssa_1128.x
>			vec1 32 ssa_1130 = fadd ssa_4.y, ssa_1128.y
>			vec1 32 ssa_1131 = ffma ssa_1130, ssa_1127.x, ssa_1127.y
>			vec1 32 ssa_1132 = f2i32 ssa_1129
>			vec1 32 ssa_1133 = f2i32 ssa_1131
>			vec1 32 ssa_1134 = iadd ssa_1132, ssa_96
>			vec1 32 ssa_1135 = iadd ssa_1133, ssa_97
>			vec2 32 ssa_1136 = vec2 ssa_1134, ssa_1135
>			vec4 32 ssa_1137 = txf ssa_1136 (coord), ssa_1 (lod), 12 (texture), 12 (sampler), 
>			r13 = imov ssa_1137.x
>			r10 = imov r13
>			r11 = imov r10
>			r12 = imov r11
>			/* succs: block_395 */
>		} else {
>			block block_137:
>			/* preds: block_135 */
>			vec1 32 ssa_1139 = ult32 ssa_1123.y, ssa_29
>			vec1 32 ssa_1140 = uge32 ssa_1123.y, ssa_52
>			vec1 32 ssa_1141 = iand ssa_1140, ssa_1139
>			/* succs: block_138 block_139 */
>			if ssa_1141 {
>				block block_138:
>				/* preds: block_137 */
>				vec4 32 ssa_1142 = intrinsic load_uniform (ssa_1) (0, 16) /* base=0 */ /* range=16 */	/* fastuidraw_painterStore */
>				vec4 32 ssa_1143 = load_const (0x3f000000 /* 0.500000 */, 0x3f000000 /* 0.500000 */, 0x00000000 /* 0.000000 */, 0x00000000 /* 0.000000 */)
>				vec1 32 ssa_1144 = fadd ssa_4.x, ssa_1143.x
>				vec1 32 ssa_1145 = fadd ssa_4.y, ssa_1143.y
>				vec1 32 ssa_1146 = ffma ssa_1145, ssa_1142.x, ssa_1142.y
>				vec1 32 ssa_1147 = f2i32 ssa_1144
>				vec1 32 ssa_1148 = f2i32 ssa_1146
>				vec1 32 ssa_1149 = iadd ssa_1147, ssa_96
>				vec1 32 ssa_1150 = iadd ssa_1148, ssa_97
>				vec2 32 ssa_1151 = vec2 ssa_1149, ssa_1150
>				vec4 32 ssa_1152 = txf ssa_1151 (coord), ssa_1 (lod), 12 (texture), 12 (sampler), 
>				r13 = imov ssa_1152.x
>				r10 = imov r13
>				r11 = imov r10
>				r12 = imov r11
>				/* succs: block_394 */
>			} else {
>				block block_139:
>				/* preds: block_137 */
>				vec1 32 ssa_1154 = ine32 ssa_1123.y, ssa_30
>				/* succs: block_140 block_392 */
>				if ssa_1154 {
>					block block_140:
>					/* preds: block_139 */
>					vec1 32 ssa_1155 = ine32 ssa_1123.y, ssa_68
>					/* succs: block_141 block_390 */
>					if ssa_1155 {
>						block block_141:
>						/* preds: block_140 */
>						vec1 32 ssa_1156 = ieq32 ssa_1123.y, ssa_50
>						/* succs: block_142 block_143 */
>						if ssa_1156 {
>							block block_142:
>							/* preds: block_141 */
>							vec4 32 ssa_1157 = intrinsic load_uniform (ssa_1) (0, 16) /* base=0 */ /* range=16 */	/* fastuidraw_painterStore */
>							vec4 32 ssa_1158 = load_const (0x3f000000 /* 0.500000 */, 0x3f000000 /* 0.500000 */, 0x00000000 /* 0.000000 */, 0x00000000 /* 0.000000 */)
>							vec1 32 ssa_1159 = fadd ssa_4.x, ssa_1158.x
>							vec1 32 ssa_1160 = fadd ssa_4.y, ssa_1158.y
>							vec1 32 ssa_1161 = ffma ssa_1160, ssa_1157.x, ssa_1157.y
>							vec1 32 ssa_1162 = f2i32 ssa_1159
>							vec1 32 ssa_1163 = f2i32 ssa_1161
>							vec1 32 ssa_1164 = iadd ssa_1162, ssa_96
>							vec1 32 ssa_1165 = iadd ssa_1163, ssa_97
>							vec2 32 ssa_1166 = vec2 ssa_1164, ssa_1165
>							vec4 32 ssa_1167 = txf ssa_1166 (coord), ssa_1 (lod), 12 (texture), 12 (sampler), 
>							r13 = imov ssa_1167.x
>							r10 = imov r13
>							r11 = imov r10
>							r12 = imov r11
>							/* succs: block_389 */
>						} else {
>							block block_143:
>							/* preds: block_141 */
>							vec1 32 ssa_1169 = ieq32 ssa_1123.y, ssa_69
>							/* succs: block_144 block_169 */
>							if ssa_1169 {
>								block block_144:
>								/* preds: block_143 */
>								vec1 32 ssa_1170 = f2u32 ssa_5.w
>								vec1 32 ssa_1171 = f2u32 ssa_5.z
>								vec1 32 ssa_1172 = fadd ssa_5.x, ssa_37
>								vec1 32 ssa_1173 = fadd ssa_5.y, ssa_37
>								vec1 32 ssa_1174 = f2i32 ssa_1172
>								vec1 32 ssa_1175 = f2i32 ssa_1173
>								vec1 32 ssa_1176 = iadd ssa_1174, ssa_25
>								vec1 32 ssa_1177 = iadd ssa_1175, ssa_25
>								vec1 32 ssa_1178 = i2f32 ssa_1174
>								vec1 32 ssa_1179 = i2f32 ssa_1175
>								vec1 32 ssa_1180 = fadd ssa_1172, -ssa_1178
>								vec1 32 ssa_1181 = fadd ssa_1173, -ssa_1179
>								vec1 32 ssa_1182 = imin ssa_1176, ssa_1177
>								vec1 32 ssa_1183 = ige32 ssa_1182, ssa_1
>								/* succs: block_145 block_149 */
>								if ssa_1183 {
>									block block_145:
>									/* preds: block_144 */
>									vec1 32 ssa_1184 = uge32 ssa_1177, ssa_1171
>									vec1 32 ssa_1185 = uge32 ssa_1176, ssa_1170
>									vec1 32 ssa_1186 = ior ssa_1185, ssa_1184
>									/* succs: block_146 block_147 */
>									if ssa_1186 {
>										block block_146:
>										/* preds: block_145 */
>										r79 = imov ssa_1
>										/* succs: block_148 */
>									} else {
>										block block_147:
>										/* preds: block_145 */
>										vec4 32 ssa_1187 = intrinsic load_input (ssa_1) (31, 0) /* base=31 */ /* component=0 */	/* fastuidraw_uint_varying0 */
>										vec1 32 ssa_1188 = ushr ssa_1176, ssa_30
>										vec1 32 ssa_1189 = iadd ssa_1187.x, ssa_1188
>										vec1 32 ssa_1190 = ushr ssa_1177, ssa_30
>										vec1 32 ssa_1191 = iadd ssa_1170, ssa_30
>										vec1 32 ssa_1192 = ushr ssa_1191, ssa_30
>										vec1 32 ssa_1193 = imul ssa_1190, ssa_1192
>										vec1 32 ssa_1194 = iadd ssa_1189, ssa_1193
>										vec1 32 ssa_1195 = ishl ssa_1194, ssa_31
>										vec1 32 ssa_1196 = intrinsic load_ssbo (ssa_30, ssa_1195) (0, 4, 0) /* access=0 */ /* align_mul=4 */ /* align_offset=0 */
>										vec1 32 ssa_1197 = iand ssa_1176, ssa_30
>										vec1 32 ssa_1198 = ine32 ssa_1197, ssa_1
>										vec1 32 ssa_1199 = b32csel ssa_1198, ssa_70, ssa_1
>										vec1 32 ssa_1200 = iand ssa_1177, ssa_30
>										vec1 32 ssa_1201 = ine32 ssa_1200, ssa_1
>										vec1 32 ssa_1202 = b32csel ssa_1201, ssa_23, ssa_1
>										vec1 32 ssa_1203 = iadd ssa_1199, ssa_1202
>										vec1 32 ssa_1204 = iadd ssa_71, -ssa_1203
>										vec1 32 ssa_1205 = ishl ssa_1196, ssa_1204
>										r79 = extract_u8 ssa_1205, ssa_32
>										/* succs: block_148 */
>									}
>									block block_148:
>									/* preds: block_146 block_147 */
>									/* succs: block_150 */
>								} else {
>									block block_149:
>									/* preds: block_144 */
>									r79 = imov ssa_1
>									/* succs: block_150 */
>								}
>								block block_150:
>								/* preds: block_148 block_149 */
>								vec1 32 ssa_1209 = imin ssa_1176, ssa_1175
>								vec1 32 ssa_1210 = ige32 ssa_1209, ssa_1
>								/* succs: block_151 block_155 */
>								if ssa_1210 {
>									block block_151:
>									/* preds: block_150 */
>									vec1 32 ssa_1211 = uge32 ssa_1175, ssa_1171
>									vec1 32 ssa_1212 = uge32 ssa_1176, ssa_1170
>									vec1 32 ssa_1213 = ior ssa_1212, ssa_1211
>									/* succs: block_152 block_153 */
>									if ssa_1213 {
>										block block_152:
>										/* preds: block_151 */
>										r80 = imov ssa_1
>										/* succs: block_154 */
>									} else {
>										block block_153:
>										/* preds: block_151 */
>										vec4 32 ssa_1214 = intrinsic load_input (ssa_1) (31, 0) /* base=31 */ /* component=0 */	/* fastuidraw_uint_varying0 */
>										vec1 32 ssa_1215 = ushr ssa_1176, ssa_30
>										vec1 32 ssa_1216 = iadd ssa_1214.x, ssa_1215
>										vec1 32 ssa_1217 = ushr ssa_1175, ssa_30
>										vec1 32 ssa_1218 = iadd ssa_1170, ssa_30
>										vec1 32 ssa_1219 = ushr ssa_1218, ssa_30
>										vec1 32 ssa_1220 = imul ssa_1217, ssa_1219
>										vec1 32 ssa_1221 = iadd ssa_1216, ssa_1220
>										vec1 32 ssa_1222 = ishl ssa_1221, ssa_31
>										vec1 32 ssa_1223 = intrinsic load_ssbo (ssa_30, ssa_1222) (0, 4, 0) /* access=0 */ /* align_mul=4 */ /* align_offset=0 */
>										vec1 32 ssa_1224 = iand ssa_1176, ssa_30
>										vec1 32 ssa_1225 = ine32 ssa_1224, ssa_1
>										vec1 32 ssa_1226 = b32csel ssa_1225, ssa_70, ssa_1
>										vec1 32 ssa_1227 = iand ssa_1175, ssa_30
>										vec1 32 ssa_1228 = ine32 ssa_1227, ssa_1
>										vec1 32 ssa_1229 = b32csel ssa_1228, ssa_23, ssa_1
>										vec1 32 ssa_1230 = iadd ssa_1226, ssa_1229
>										vec1 32 ssa_1231 = iadd ssa_71, -ssa_1230
>										vec1 32 ssa_1232 = ishl ssa_1223, ssa_1231
>										r80 = extract_u8 ssa_1232, ssa_32
>										/* succs: block_154 */
>									}
>									block block_154:
>									/* preds: block_152 block_153 */
>									/* succs: block_156 */
>								} else {
>									block block_155:
>									/* preds: block_150 */
>									r80 = imov ssa_1
>									/* succs: block_156 */
>								}
>								block block_156:
>								/* preds: block_154 block_155 */
>								vec1 32 ssa_1236 = imin ssa_1174, ssa_1177
>								vec1 32 ssa_1237 = ige32 ssa_1236, ssa_1
>								/* succs: block_157 block_161 */
>								if ssa_1237 {
>									block block_157:
>									/* preds: block_156 */
>									vec1 32 ssa_1238 = uge32 ssa_1177, ssa_1171
>									vec1 32 ssa_1239 = uge32 ssa_1174, ssa_1170
>									vec1 32 ssa_1240 = ior ssa_1239, ssa_1238
>									/* succs: block_158 block_159 */
>									if ssa_1240 {
>										block block_158:
>										/* preds: block_157 */
>										r81 = imov ssa_1
>										/* succs: block_160 */
>									} else {
>										block block_159:
>										/* preds: block_157 */
>										vec4 32 ssa_1241 = intrinsic load_input (ssa_1) (31, 0) /* base=31 */ /* component=0 */	/* fastuidraw_uint_varying0 */
>										vec1 32 ssa_1242 = ushr ssa_1174, ssa_30
>										vec1 32 ssa_1243 = iadd ssa_1241.x, ssa_1242
>										vec1 32 ssa_1244 = ushr ssa_1177, ssa_30
>										vec1 32 ssa_1245 = iadd ssa_1170, ssa_30
>										vec1 32 ssa_1246 = ushr ssa_1245, ssa_30
>										vec1 32 ssa_1247 = imul ssa_1244, ssa_1246
>										vec1 32 ssa_1248 = iadd ssa_1243, ssa_1247
>										vec1 32 ssa_1249 = ishl ssa_1248, ssa_31
>										vec1 32 ssa_1250 = intrinsic load_ssbo (ssa_30, ssa_1249) (0, 4, 0) /* access=0 */ /* align_mul=4 */ /* align_offset=0 */
>										vec1 32 ssa_1251 = iand ssa_1174, ssa_30
>										vec1 32 ssa_1252 = ine32 ssa_1251, ssa_1
>										vec1 32 ssa_1253 = b32csel ssa_1252, ssa_70, ssa_1
>										vec1 32 ssa_1254 = iand ssa_1177, ssa_30
>										vec1 32 ssa_1255 = ine32 ssa_1254, ssa_1
>										vec1 32 ssa_1256 = b32csel ssa_1255, ssa_23, ssa_1
>										vec1 32 ssa_1257 = iadd ssa_1253, ssa_1256
>										vec1 32 ssa_1258 = iadd ssa_71, -ssa_1257
>										vec1 32 ssa_1259 = ishl ssa_1250, ssa_1258
>										r81 = extract_u8 ssa_1259, ssa_32
>										/* succs: block_160 */
>									}
>									block block_160:
>									/* preds: block_158 block_159 */
>									/* succs: block_162 */
>								} else {
>									block block_161:
>									/* preds: block_156 */
>									r81 = imov ssa_1
>									/* succs: block_162 */
>								}
>								block block_162:
>								/* preds: block_160 block_161 */
>								vec1 32 ssa_1263 = imin ssa_1174, ssa_1175
>								vec1 32 ssa_1264 = ige32 ssa_1263, ssa_1
>								/* succs: block_163 block_167 */
>								if ssa_1264 {
>									block block_163:
>									/* preds: block_162 */
>									vec1 32 ssa_1265 = uge32 ssa_1175, ssa_1171
>									vec1 32 ssa_1266 = uge32 ssa_1174, ssa_1170
>									vec1 32 ssa_1267 = ior ssa_1266, ssa_1265
>									/* succs: block_164 block_165 */
>									if ssa_1267 {
>										block block_164:
>										/* preds: block_163 */
>										r82 = imov ssa_1
>										/* succs: block_166 */
>									} else {
>										block block_165:
>										/* preds: block_163 */
>										vec4 32 ssa_1268 = intrinsic load_input (ssa_1) (31, 0) /* base=31 */ /* component=0 */	/* fastuidraw_uint_varying0 */
>										vec1 32 ssa_1269 = ushr ssa_1174, ssa_30
>										vec1 32 ssa_1270 = iadd ssa_1268.x, ssa_1269
>										vec1 32 ssa_1271 = ushr ssa_1175, ssa_30
>										vec1 32 ssa_1272 = iadd ssa_1170, ssa_30
>										vec1 32 ssa_1273 = ushr ssa_1272, ssa_30
>										vec1 32 ssa_1274 = imul ssa_1271, ssa_1273
>										vec1 32 ssa_1275 = iadd ssa_1270, ssa_1274
>										vec1 32 ssa_1276 = ishl ssa_1275, ssa_31
>										vec1 32 ssa_1277 = intrinsic load_ssbo (ssa_30, ssa_1276) (0, 4, 0) /* access=0 */ /* align_mul=4 */ /* align_offset=0 */
>										vec1 32 ssa_1278 = iand ssa_1174, ssa_30
>										vec1 32 ssa_1279 = ine32 ssa_1278, ssa_1
>										vec1 32 ssa_1280 = b32csel ssa_1279, ssa_70, ssa_1
>										vec1 32 ssa_1281 = iand ssa_1175, ssa_30
>										vec1 32 ssa_1282 = ine32 ssa_1281, ssa_1
>										vec1 32 ssa_1283 = b32csel ssa_1282, ssa_23, ssa_1
>										vec1 32 ssa_1284 = iadd ssa_1280, ssa_1283
>										vec1 32 ssa_1285 = iadd ssa_71, -ssa_1284
>										vec1 32 ssa_1286 = ishl ssa_1277, ssa_1285
>										r82 = extract_u8 ssa_1286, ssa_32
>										/* succs: block_166 */
>									}
>									block block_166:
>									/* preds: block_164 block_165 */
>									/* succs: block_168 */
>								} else {
>									block block_167:
>									/* preds: block_162 */
>									r82 = imov ssa_1
>									/* succs: block_168 */
>								}
>								block block_168:
>								/* preds: block_166 block_167 */
>								vec1 32 ssa_1290 = u2f32 r79
>								vec1 32 ssa_1291 = u2f32 r80
>								vec1 32 ssa_1292 = flrp ssa_1290, ssa_1291, ssa_1181
>								vec1 32 ssa_1293 = u2f32 r81
>								vec1 32 ssa_1294 = u2f32 r82
>								vec1 32 ssa_1295 = flrp ssa_1293, ssa_1294, ssa_1181
>								vec1 32 ssa_1296 = flrp ssa_1292, ssa_1295, ssa_1180
>								vec1 32 ssa_1297 = load_const (0x3b808081 /* 0.003922 */)
>								r13 = fmul ssa_1296, ssa_1297
>								r10 = imov r13
>								r11 = imov r10
>								r12 = imov r11
>								/* succs: block_388 */
>							} else {
>								block block_169:
>								/* preds: block_143 */
>								vec1 32 ssa_1299 = ieq32 ssa_1123.y, ssa_34
>								/* succs: block_170 block_195 */
>								if ssa_1299 {
>									block block_170:
>									/* preds: block_169 */
>									vec1 32 ssa_1300 = f2u32 ssa_5.w
>									vec1 32 ssa_1301 = f2u32 ssa_5.z
>									vec1 32 ssa_1302 = fadd ssa_5.x, ssa_37
>									vec1 32 ssa_1303 = fadd ssa_5.y, ssa_37
>									vec1 32 ssa_1304 = f2i32 ssa_1302
>									vec1 32 ssa_1305 = f2i32 ssa_1303
>									vec1 32 ssa_1306 = iadd ssa_1304, ssa_25
>									vec1 32 ssa_1307 = iadd ssa_1305, ssa_25
>									vec1 32 ssa_1308 = i2f32 ssa_1304
>									vec1 32 ssa_1309 = i2f32 ssa_1305
>									vec1 32 ssa_1310 = fadd ssa_1302, -ssa_1308
>									vec1 32 ssa_1311 = fadd ssa_1303, -ssa_1309
>									vec1 32 ssa_1312 = imin ssa_1306, ssa_1307
>									vec1 32 ssa_1313 = ige32 ssa_1312, ssa_1
>									/* succs: block_171 block_175 */
>									if ssa_1313 {
>										block block_171:
>										/* preds: block_170 */
>										vec1 32 ssa_1314 = uge32 ssa_1307, ssa_1301
>										vec1 32 ssa_1315 = uge32 ssa_1306, ssa_1300
>										vec1 32 ssa_1316 = ior ssa_1315, ssa_1314
>										/* succs: block_172 block_173 */
>										if ssa_1316 {
>											block block_172:
>											/* preds: block_171 */
>											r83 = imov ssa_1
>											/* succs: block_174 */
>										} else {
>											block block_173:
>											/* preds: block_171 */
>											vec4 32 ssa_1317 = intrinsic load_input (ssa_1) (31, 0) /* base=31 */ /* component=0 */	/* fastuidraw_uint_varying0 */
>											vec1 32 ssa_1318 = ushr ssa_1306, ssa_30
>											vec1 32 ssa_1319 = iadd ssa_1317.x, ssa_1318
>											vec1 32 ssa_1320 = ushr ssa_1307, ssa_30
>											vec1 32 ssa_1321 = iadd ssa_1300, ssa_30
>											vec1 32 ssa_1322 = ushr ssa_1321, ssa_30
>											vec1 32 ssa_1323 = imul ssa_1320, ssa_1322
>											vec1 32 ssa_1324 = iadd ssa_1319, ssa_1323
>											vec1 32 ssa_1325 = ishl ssa_1324, ssa_31
>											vec1 32 ssa_1326 = intrinsic load_ssbo (ssa_30, ssa_1325) (0, 4, 0) /* access=0 */ /* align_mul=4 */ /* align_offset=0 */
>											vec1 32 ssa_1327 = iand ssa_1306, ssa_30
>											vec1 32 ssa_1328 = ine32 ssa_1327, ssa_1
>											vec1 32 ssa_1329 = b32csel ssa_1328, ssa_70, ssa_1
>											vec1 32 ssa_1330 = iand ssa_1307, ssa_30
>											vec1 32 ssa_1331 = ine32 ssa_1330, ssa_1
>											vec1 32 ssa_1332 = b32csel ssa_1331, ssa_23, ssa_1
>											vec1 32 ssa_1333 = iadd ssa_1329, ssa_1332
>											vec1 32 ssa_1334 = iadd ssa_71, -ssa_1333
>											vec1 32 ssa_1335 = ishl ssa_1326, ssa_1334
>											r83 = extract_u8 ssa_1335, ssa_32
>											/* succs: block_174 */
>										}
>										block block_174:
>										/* preds: block_172 block_173 */
>										/* succs: block_176 */
>									} else {
>										block block_175:
>										/* preds: block_170 */
>										r83 = imov ssa_1
>										/* succs: block_176 */
>									}
>									block block_176:
>									/* preds: block_174 block_175 */
>									vec1 32 ssa_1339 = imin ssa_1306, ssa_1305
>									vec1 32 ssa_1340 = ige32 ssa_1339, ssa_1
>									/* succs: block_177 block_181 */
>									if ssa_1340 {
>										block block_177:
>										/* preds: block_176 */
>										vec1 32 ssa_1341 = uge32 ssa_1305, ssa_1301
>										vec1 32 ssa_1342 = uge32 ssa_1306, ssa_1300
>										vec1 32 ssa_1343 = ior ssa_1342, ssa_1341
>										/* succs: block_178 block_179 */
>										if ssa_1343 {
>											block block_178:
>											/* preds: block_177 */
>											r84 = imov ssa_1
>											/* succs: block_180 */
>										} else {
>											block block_179:
>											/* preds: block_177 */
>											vec4 32 ssa_1344 = intrinsic load_input (ssa_1) (31, 0) /* base=31 */ /* component=0 */	/* fastuidraw_uint_varying0 */
>											vec1 32 ssa_1345 = ushr ssa_1306, ssa_30
>											vec1 32 ssa_1346 = iadd ssa_1344.x, ssa_1345
>											vec1 32 ssa_1347 = ushr ssa_1305, ssa_30
>											vec1 32 ssa_1348 = iadd ssa_1300, ssa_30
>											vec1 32 ssa_1349 = ushr ssa_1348, ssa_30
>											vec1 32 ssa_1350 = imul ssa_1347, ssa_1349
>											vec1 32 ssa_1351 = iadd ssa_1346, ssa_1350
>											vec1 32 ssa_1352 = ishl ssa_1351, ssa_31
>											vec1 32 ssa_1353 = intrinsic load_ssbo (ssa_30, ssa_1352) (0, 4, 0) /* access=0 */ /* align_mul=4 */ /* align_offset=0 */
>											vec1 32 ssa_1354 = iand ssa_1306, ssa_30
>											vec1 32 ssa_1355 = ine32 ssa_1354, ssa_1
>											vec1 32 ssa_1356 = b32csel ssa_1355, ssa_70, ssa_1
>											vec1 32 ssa_1357 = iand ssa_1305, ssa_30
>											vec1 32 ssa_1358 = ine32 ssa_1357, ssa_1
>											vec1 32 ssa_1359 = b32csel ssa_1358, ssa_23, ssa_1
>											vec1 32 ssa_1360 = iadd ssa_1356, ssa_1359
>											vec1 32 ssa_1361 = iadd ssa_71, -ssa_1360
>											vec1 32 ssa_1362 = ishl ssa_1353, ssa_1361
>											r84 = extract_u8 ssa_1362, ssa_32
>											/* succs: block_180 */
>										}
>										block block_180:
>										/* preds: block_178 block_179 */
>										/* succs: block_182 */
>									} else {
>										block block_181:
>										/* preds: block_176 */
>										r84 = imov ssa_1
>										/* succs: block_182 */
>									}
>									block block_182:
>									/* preds: block_180 block_181 */
>									vec1 32 ssa_1366 = imin ssa_1304, ssa_1307
>									vec1 32 ssa_1367 = ige32 ssa_1366, ssa_1
>									/* succs: block_183 block_187 */
>									if ssa_1367 {
>										block block_183:
>										/* preds: block_182 */
>										vec1 32 ssa_1368 = uge32 ssa_1307, ssa_1301
>										vec1 32 ssa_1369 = uge32 ssa_1304, ssa_1300
>										vec1 32 ssa_1370 = ior ssa_1369, ssa_1368
>										/* succs: block_184 block_185 */
>										if ssa_1370 {
>											block block_184:
>											/* preds: block_183 */
>											r85 = imov ssa_1
>											/* succs: block_186 */
>										} else {
>											block block_185:
>											/* preds: block_183 */
>											vec4 32 ssa_1371 = intrinsic load_input (ssa_1) (31, 0) /* base=31 */ /* component=0 */	/* fastuidraw_uint_varying0 */
>											vec1 32 ssa_1372 = ushr ssa_1304, ssa_30
>											vec1 32 ssa_1373 = iadd ssa_1371.x, ssa_1372
>											vec1 32 ssa_1374 = ushr ssa_1307, ssa_30
>											vec1 32 ssa_1375 = iadd ssa_1300, ssa_30
>											vec1 32 ssa_1376 = ushr ssa_1375, ssa_30
>											vec1 32 ssa_1377 = imul ssa_1374, ssa_1376
>											vec1 32 ssa_1378 = iadd ssa_1373, ssa_1377
>											vec1 32 ssa_1379 = ishl ssa_1378, ssa_31
>											vec1 32 ssa_1380 = intrinsic load_ssbo (ssa_30, ssa_1379) (0, 4, 0) /* access=0 */ /* align_mul=4 */ /* align_offset=0 */
>											vec1 32 ssa_1381 = iand ssa_1304, ssa_30
>											vec1 32 ssa_1382 = ine32 ssa_1381, ssa_1
>											vec1 32 ssa_1383 = b32csel ssa_1382, ssa_70, ssa_1
>											vec1 32 ssa_1384 = iand ssa_1307, ssa_30
>											vec1 32 ssa_1385 = ine32 ssa_1384, ssa_1
>											vec1 32 ssa_1386 = b32csel ssa_1385, ssa_23, ssa_1
>											vec1 32 ssa_1387 = iadd ssa_1383, ssa_1386
>											vec1 32 ssa_1388 = iadd ssa_71, -ssa_1387
>											vec1 32 ssa_1389 = ishl ssa_1380, ssa_1388
>											r85 = extract_u8 ssa_1389, ssa_32
>											/* succs: block_186 */
>										}
>										block block_186:
>										/* preds: block_184 block_185 */
>										/* succs: block_188 */
>									} else {
>										block block_187:
>										/* preds: block_182 */
>										r85 = imov ssa_1
>										/* succs: block_188 */
>									}
>									block block_188:
>									/* preds: block_186 block_187 */
>									vec1 32 ssa_1393 = imin ssa_1304, ssa_1305
>									vec1 32 ssa_1394 = ige32 ssa_1393, ssa_1
>									/* succs: block_189 block_193 */
>									if ssa_1394 {
>										block block_189:
>										/* preds: block_188 */
>										vec1 32 ssa_1395 = uge32 ssa_1305, ssa_1301
>										vec1 32 ssa_1396 = uge32 ssa_1304, ssa_1300
>										vec1 32 ssa_1397 = ior ssa_1396, ssa_1395
>										/* succs: block_190 block_191 */
>										if ssa_1397 {
>											block block_190:
>											/* preds: block_189 */
>											r86 = imov ssa_1
>											/* succs: block_192 */
>										} else {
>											block block_191:
>											/* preds: block_189 */
>											vec4 32 ssa_1398 = intrinsic load_input (ssa_1) (31, 0) /* base=31 */ /* component=0 */	/* fastuidraw_uint_varying0 */
>											vec1 32 ssa_1399 = ushr ssa_1304, ssa_30
>											vec1 32 ssa_1400 = iadd ssa_1398.x, ssa_1399
>											vec1 32 ssa_1401 = ushr ssa_1305, ssa_30
>											vec1 32 ssa_1402 = iadd ssa_1300, ssa_30
>											vec1 32 ssa_1403 = ushr ssa_1402, ssa_30
>											vec1 32 ssa_1404 = imul ssa_1401, ssa_1403
>											vec1 32 ssa_1405 = iadd ssa_1400, ssa_1404
>											vec1 32 ssa_1406 = ishl ssa_1405, ssa_31
>											vec1 32 ssa_1407 = intrinsic load_ssbo (ssa_30, ssa_1406) (0, 4, 0) /* access=0 */ /* align_mul=4 */ /* align_offset=0 */
>											vec1 32 ssa_1408 = iand ssa_1304, ssa_30
>											vec1 32 ssa_1409 = ine32 ssa_1408, ssa_1
>											vec1 32 ssa_1410 = b32csel ssa_1409, ssa_70, ssa_1
>											vec1 32 ssa_1411 = iand ssa_1305, ssa_30
>											vec1 32 ssa_1412 = ine32 ssa_1411, ssa_1
>											vec1 32 ssa_1413 = b32csel ssa_1412, ssa_23, ssa_1
>											vec1 32 ssa_1414 = iadd ssa_1410, ssa_1413
>											vec1 32 ssa_1415 = iadd ssa_71, -ssa_1414
>											vec1 32 ssa_1416 = ishl ssa_1407, ssa_1415
>											r86 = extract_u8 ssa_1416, ssa_32
>											/* succs: block_192 */
>										}
>										block block_192:
>										/* preds: block_190 block_191 */
>										/* succs: block_194 */
>									} else {
>										block block_193:
>										/* preds: block_188 */
>										r86 = imov ssa_1
>										/* succs: block_194 */
>									}
>									block block_194:
>									/* preds: block_192 block_193 */
>									vec1 32 ssa_1420 = u2f32 r83
>									vec1 32 ssa_1421 = u2f32 r84
>									vec1 32 ssa_1422 = flrp ssa_1420, ssa_1421, ssa_1311
>									vec1 32 ssa_1423 = u2f32 r85
>									vec1 32 ssa_1424 = u2f32 r86
>									vec1 32 ssa_1425 = flrp ssa_1423, ssa_1424, ssa_1311
>									vec1 32 ssa_1426 = flrp ssa_1422, ssa_1425, ssa_1310
>									vec1 32 ssa_1427 = load_const (0x3c008081 /* 0.007843 */)
>									vec1 32 ssa_1428 = ffma ssa_1427, ssa_1426, ssa_51
>									vec1 32 ssa_1429 = fddx ssa_1428
>									vec4 32 ssa_1430 = intrinsic load_uniform (ssa_1) (0, 16) /* base=0 */ /* range=16 */	/* fastuidraw_painterStore */
>									vec1 32 ssa_1431 = fmul ssa_1428, ssa_1430.x
>									vec1 32 ssa_1432 = fddy ssa_1431
>									vec1 32 ssa_1433 = fmul ssa_1432, ssa_1432
>									vec1 32 ssa_1434 = ffma ssa_1429, ssa_1429, ssa_1433
>									vec1 32 ssa_1435 = frsq ssa_1434
>									r13 = ffma.sat ssa_1428, ssa_1435, ssa_37
>									r10 = imov r13
>									r11 = imov r10
>									r12 = imov r11
>									/* succs: block_387 */
>								} else {
>									block block_195:
>									/* preds: block_169 */
>									vec1 32 ssa_1437 = ieq32 ssa_1123.y, ssa_72
>									/* succs: block_196 block_315 */
>									if ssa_1437 {
>										block block_196:
>										/* preds: block_195 */
>										vec4 32 ssa_1438 = intrinsic load_input (ssa_1) (31, 0) /* base=31 */ /* component=0 */	/* fastuidraw_uint_varying0 */
>										r87 = iand ssa_1438.x, ssa_73
>										vec1 32 ssa_1440 = fddx ssa_5.x
>										vec1 32 ssa_1441 = fddx ssa_5.y
>										vec4 32 ssa_1442 = intrinsic load_uniform (ssa_1) (0, 16) /* base=0 */ /* range=16 */	/* fastuidraw_painterStore */
>										vec1 32 ssa_1443 = fmul ssa_5.x, ssa_1442.x
>										vec1 32 ssa_1444 = fddy ssa_1443
>										vec1 32 ssa_1445 = fmul ssa_5.y, ssa_1442.x
>										vec1 32 ssa_1446 = fddy ssa_1445
>										vec1 32 ssa_1447 = iand ssa_1438.x, ssa_26
>										vec1 32 ssa_1448 = ine32 ssa_1447, ssa_1
>										vec1 32 ssa_1449 = ishl r87, ssa_31
>										r88 = intrinsic load_ssbo (ssa_30, ssa_1449) (0, 4, 0) /* access=0 */ /* align_mul=4 */ /* align_offset=0 */
>										vec1 32 ssa_1451 = load_const (0x45000000 /* 2048.000000 */)
>										vec1 32 ssa_1452 = load_const (0xc5000000 /* -2048.000000 */)
>										r93 = imov ssa_1452
>										r92 = imov r93
>										r91 = imov ssa_1451
>										r90 = imov r91
>										r89 = imov r87
>										/* succs: block_197 */
>										loop {
>											block block_197:
>											/* preds: block_196 block_203 */
>											vec1 32 ssa_1459 = iand r88, ssa_30
>											vec1 32 ssa_1460 = ieq32 ssa_1459, ssa_1
>											/* succs: block_198 block_199 */
>											if ssa_1460 {
>												block block_198:
>												/* preds: block_197 */
>												break
>												/* succs: block_204 */
>											} else {
>												block block_199:
>												/* preds: block_197 */
>												/* succs: block_200 */
>											}
>											block block_200:
>											/* preds: block_199 */
>											vec1 32 ssa_1461 = ishl r88, ssa_28
>											vec1 32 ssa_1462 = ushr ssa_1461, ssa_74
>											vec1 32 ssa_1463 = ieq32 ssa_1462, ssa_1
>											/* succs: block_201 block_202 */
>											if ssa_1463 {
>												block block_201:
>												/* preds: block_200 */
>												vec1 32 ssa_1464 = fadd r92, r90
>												vec1 32 ssa_1465 = fmul ssa_37, ssa_1464
>												r94 = flt32 ssa_1465, ssa_5.x
>												r92 = b32csel r94, ssa_1465, r92
>												r90 = b32csel r94, r90, ssa_1465
>												/* succs: block_203 */
>											} else {
>												block block_202:
>												/* preds: block_200 */
>												vec1 32 ssa_1469 = fadd r93, r91
>												vec1 32 ssa_1470 = fmul ssa_37, ssa_1469
>												r94 = flt32 ssa_1470, ssa_5.y
>												r93 = b32csel r94, ssa_1470, r93
>												r91 = b32csel r94, r91, ssa_1470
>												/* succs: block_203 */
>											}
>											block block_203:
>											/* preds: block_201 block_202 */
>											vec1 32 ssa_1479 = b32csel r94, ssa_75, ssa_31
>											vec1 32 ssa_1480 = iadd ssa_75, -ssa_1479
>											vec1 32 ssa_1481 = ishl r88, ssa_1480
>											vec1 32 ssa_1482 = ushr ssa_1481, ssa_75
>											r89 = iadd ssa_1482, r87
>											vec1 32 ssa_1484 = ishl r89, ssa_31
>											r88 = intrinsic load_ssbo (ssa_30, ssa_1484) (0, 4, 0) /* access=0 */ /* align_mul=4 */ /* align_offset=0 */
>											/* succs: block_197 */
>										}
>										block block_204:
>										/* preds: block_198 */
>										vec1 32 ssa_1486 = ishl r88, ssa_76
>										vec1 32 ssa_1487 = extract_u16 ssa_1486, ssa_30
>										vec1 32 ssa_1488 = ushr r88, ssa_75
>										vec1 32 ssa_1489 = iadd r89, ssa_30
>										vec1 32 ssa_1490 = ishl ssa_1489, ssa_31
>										vec1 32 ssa_1491 = intrinsic load_ssbo (ssa_30, ssa_1490) (0, 4, 0) /* access=0 */ /* align_mul=4 */ /* align_offset=0 */
>										vec1 32 ssa_1492 = extract_u8 ssa_1491, ssa_31
>										vec1 32 ssa_1493 = extract_u8 ssa_1491, ssa_32
>										vec1 32 ssa_1494 = u2f32 ssa_1492
>										vec1 32 ssa_1495 = u2f32 ssa_1493
>										vec1 32 ssa_1496 = load_const (0x3b800000 /* 0.003906 */)
>										vec1 32 ssa_1497 = fmul ssa_1494, ssa_1496
>										vec1 32 ssa_1498 = fmul ssa_1495, ssa_1496
>										vec1 32 ssa_1499 = extract_u16 ssa_1491, ssa_1
>										r95 = iadd ssa_1499, ssa_24
>										vec1 32 ssa_1501 = flrp r92, r90, ssa_1497
>										vec1 32 ssa_1502 = flrp r93, r91, ssa_1498
>										vec1 32 ssa_1503 = fadd ssa_1501, -ssa_5.x
>										vec1 32 ssa_1504 = fadd ssa_1502, -ssa_5.y
>										vec1 32 ssa_1505 = fmul ssa_1446, ssa_1446
>										vec1 32 ssa_1506 = ffma ssa_1441, ssa_1441, ssa_1505
>										vec1 32 ssa_1507 = fmul ssa_1444, ssa_1446
>										vec1 32 ssa_1508 = ffma ssa_1440, ssa_1441, ssa_1507
>										vec1 32 ssa_1509 = fmul ssa_1444, ssa_1444
>										vec1 32 ssa_1510 = ffma ssa_1440, ssa_1440, ssa_1509
>										vec1 32 ssa_1511 = fmul ssa_1508, ssa_1504
>										vec1 32 ssa_1512 = ffma -ssa_1506, ssa_1503, ssa_1511
>										vec1 32 ssa_1513 = fmul ssa_1510, ssa_1504
>										vec1 32 ssa_1514 = ffma ssa_1508, ssa_1503, -ssa_1513
>										vec1 32 ssa_1515 = fmul ssa_1514, ssa_1441
>										vec1 32 ssa_1516 = ffma ssa_1512, ssa_1440, ssa_1515
>										vec1 32 ssa_1517 = fmul ssa_1514, ssa_1446
>										vec1 32 ssa_1518 = ffma ssa_1512, ssa_1444, ssa_1517
>										vec1 32 ssa_1519 = fadd abs(ssa_1516), abs(ssa_1518)
>										vec1 32 ssa_1520 = fmul ssa_1503, ssa_1441
>										vec1 32 ssa_1521 = ffma -ssa_1504, ssa_1440, ssa_1520
>										vec1 32 ssa_1522 = fmul ssa_1503, ssa_1446
>										vec1 32 ssa_1523 = ffma -ssa_1504, ssa_1444, ssa_1522
>										vec1 32 ssa_1524 = fadd abs(ssa_1521), abs(ssa_1523)
>										vec1 32 ssa_1525 = fmax ssa_1519, ssa_78
>										vec1 32 ssa_1526 = fmax ssa_1524, ssa_78
>										vec1 32 ssa_1527 = frcp ssa_1525
>										vec1 32 ssa_1528 = fmul ssa_1512, ssa_1527
>										vec1 32 ssa_1529 = fmul ssa_1514, ssa_1527
>										vec1 32 ssa_1530 = frcp ssa_1526
>										vec1 32 ssa_1531 = fmul ssa_1504, ssa_1530
>										vec1 32 ssa_1532 = fmov -ssa_1531
>										vec1 32 ssa_1533 = fmul ssa_1503, ssa_1530
>										vec1 32 ssa_1534 = fmul ssa_1529, ssa_1504
>										vec1 32 ssa_1535 = ffma ssa_1528, ssa_1503, ssa_1534
>										vec1 32 ssa_1536 = fmov -ssa_1528
>										vec1 32 ssa_1537 = fmov -ssa_1529
>										vec1 32 ssa_1538 = fmov -ssa_1535
>										vec1 32 ssa_1539 = flt32 ssa_1535, ssa_1
>										vec1 32 ssa_1540 = b32csel ssa_1539, ssa_1538, ssa_1535
>										vec1 32 ssa_1541 = b32csel ssa_1539, ssa_1536, ssa_1528
>										vec1 32 ssa_1542 = b32csel ssa_1539, ssa_1537, ssa_1529
>										vec1 32 ssa_1543 = fmul ssa_1541, ssa_1533
>										vec1 32 ssa_1544 = fmul ssa_1531, ssa_1542
>										vec1 32 ssa_1545 = fmov -ssa_1533
>										vec1 32 ssa_1546 = flt32 ssa_1543, -ssa_1544
>										vec1 32 ssa_1547 = b32csel ssa_1546, ssa_1531, ssa_1532
>										vec1 32 ssa_1548 = b32csel ssa_1546, ssa_1545, ssa_1533
>										r96 = iadd ssa_1487, r87
>										r99 = imov ssa_77
>										r98 = imov r99
>										r97 = imov ssa_1
>										/* succs: block_205 */
>										loop {
>											block block_205:
>											/* preds: block_204 block_301 */
>											vec1 32 ssa_1555 = uge32 r97, ssa_1488
>											/* succs: block_206 block_207 */
>											if ssa_1555 {
>												block block_206:
>												/* preds: block_205 */
>												break
>												/* succs: block_302 */
>											} else {
>												block block_207:
>												/* preds: block_205 */
>												/* succs: block_208 */
>											}
>											block block_208:
>											/* preds: block_207 */
>											vec1 32 ssa_1556 = ishl r96, ssa_31
>											vec1 32 ssa_1557 = intrinsic load_ssbo (ssa_30, ssa_1556) (0, 4, 0) /* access=0 */ /* align_mul=4 */ /* align_offset=0 */
>											r96 = iadd r96, ssa_30
>											vec1 32 ssa_1559 = extract_u16 ssa_1557, ssa_1
>											vec1 32 ssa_1560 = ishl ssa_1559, ssa_75
>											vec1 32 ssa_1561 = ushr ssa_1560, ssa_75
>											vec1 32 ssa_1562 = iadd r87, ssa_1561
>											vec1 32 ssa_1563 = iand ssa_1559, ssa_79
>											vec1 32 ssa_1564 = ishl ssa_1562, ssa_31
>											vec1 32 ssa_1565 = intrinsic load_ssbo (ssa_30, ssa_1564) (0, 4, 0) /* access=0 */ /* align_mul=4 */ /* align_offset=0 */
>											vec1 32 ssa_1566 = unpack_half_2x16_split_x ssa_1565
>											vec1 32 ssa_1567 = unpack_half_2x16_split_y ssa_1565
>											vec1 32 ssa_1568 = iadd ssa_1562, ssa_30
>											vec1 32 ssa_1569 = ishl ssa_1568, ssa_31
>											vec1 32 ssa_1570 = intrinsic load_ssbo (ssa_30, ssa_1569) (0, 4, 0) /* access=0 */ /* align_mul=4 */ /* align_offset=0 */
>											r100 = unpack_half_2x16_split_x ssa_1570
>											r101 = unpack_half_2x16_split_y ssa_1570
>											vec1 32 ssa_1573 = ine32 ssa_1563, ssa_1
>											/* succs: block_209 block_210 */
>											if ssa_1573 {
>												block block_209:
>												/* preds: block_208 */
>												vec1 32 ssa_1574 = iadd ssa_1562, ssa_31
>												vec1 32 ssa_1575 = ishl ssa_1574, ssa_31
>												vec1 32 ssa_1576 = intrinsic load_ssbo (ssa_30, ssa_1575) (0, 4, 0) /* access=0 */ /* align_mul=4 */ /* align_offset=0 */
>												r102 = unpack_half_2x16_split_x ssa_1576
>												r103 = unpack_half_2x16_split_y ssa_1576
>												/* succs: block_211 */
>											} else {
>												block block_210:
>												/* preds: block_208 */
>												vec1 32 ssa_1579 = fadd ssa_1566, r100
>												vec1 32 ssa_1580 = fadd ssa_1567, r101
>												r104 = fmul ssa_37, ssa_1579
>												r105 = fmul ssa_37, ssa_1580
>												r103 = imov r101
>												r101 = imov r105
>												r102 = imov r100
>												r100 = imov r104
>												/* succs: block_211 */
>											}
>											block block_211:
>											/* preds: block_209 block_210 */
>											vec1 32 ssa_1587 = fadd ssa_1566, -ssa_5.x
>											vec1 32 ssa_1588 = fadd ssa_1567, -ssa_5.y
>											vec1 32 ssa_1589 = fmul ssa_1542, ssa_1588
>											vec1 32 ssa_1590 = ffma ssa_1541, ssa_1587, ssa_1589
>											vec1 32 ssa_1591 = fmul ssa_1548, ssa_1588
>											vec1 32 ssa_1592 = ffma ssa_1547, ssa_1587, ssa_1591
>											vec1 32 ssa_1593 = fadd r100, -ssa_5.x
>											vec1 32 ssa_1594 = fadd r101, -ssa_5.y
>											vec1 32 ssa_1595 = fmul ssa_1542, ssa_1594
>											vec1 32 ssa_1596 = ffma ssa_1541, ssa_1593, ssa_1595
>											vec1 32 ssa_1597 = fmul ssa_1548, ssa_1594
>											vec1 32 ssa_1598 = ffma ssa_1547, ssa_1593, ssa_1597
>											vec1 32 ssa_1599 = fadd r102, -ssa_5.x
>											vec1 32 ssa_1600 = fadd r103, -ssa_5.y
>											vec1 32 ssa_1601 = fmul ssa_1542, ssa_1600
>											vec1 32 ssa_1602 = ffma ssa_1541, ssa_1599, ssa_1601
>											vec1 32 ssa_1603 = fmul ssa_1548, ssa_1600
>											vec1 32 ssa_1604 = ffma ssa_1547, ssa_1599, ssa_1603
>											vec1 32 ssa_1605 = ffma -ssa_33, ssa_1596, ssa_1590
>											vec1 32 ssa_1606 = ffma -ssa_33, ssa_1598, ssa_1592
>											vec1 32 ssa_1607 = fadd ssa_1605, ssa_1602
>											vec1 32 ssa_1608 = fadd ssa_1606, ssa_1604
>											vec1 32 ssa_1609 = fadd ssa_1590, -ssa_1596
>											vec1 32 ssa_1610 = fadd ssa_1592, -ssa_1598
>											vec1 32 ssa_1611 = flt32 ssa_1, ssa_1590
>											vec1 32 ssa_1612 = b32csel ssa_1611, ssa_31, ssa_1
>											vec1 32 ssa_1613 = flt32 ssa_1, ssa_1596
>											vec1 32 ssa_1614 = b32csel ssa_1613, ssa_80, ssa_1
>											vec1 32 ssa_1615 = flt32 ssa_1, ssa_1602
>											vec1 32 ssa_1616 = b32csel ssa_1615, ssa_70, ssa_1
>											vec1 32 ssa_1617 = iadd ssa_1612, ssa_1614
>											vec1 32 ssa_1618 = iadd ssa_1617, ssa_1616
>											vec1 32 ssa_1619 = ushr ssa_81, ssa_1618
>											r106 = iand ssa_1619, ssa_32
>											vec1 32 ssa_1621 = flt32 ssa_1, ssa_1592
>											vec1 32 ssa_1622 = b32csel ssa_1621, ssa_31, ssa_1
>											vec1 32 ssa_1623 = flt32 ssa_1, ssa_1598
>											vec1 32 ssa_1624 = b32csel ssa_1623, ssa_80, ssa_1
>											vec1 32 ssa_1625 = flt32 ssa_1, ssa_1604
>											vec1 32 ssa_1626 = b32csel ssa_1625, ssa_70, ssa_1
>											vec1 32 ssa_1627 = iadd ssa_1622, ssa_1624
>											vec1 32 ssa_1628 = iadd ssa_1627, ssa_1626
>											vec1 32 ssa_1629 = ushr ssa_81, ssa_1628
>											r107 = iand ssa_1629, ssa_32
>											vec1 32 ssa_1631 = ine32 r107, ssa_1
>											/* succs: block_212 block_231 */
>											if ssa_1631 {
>												block block_212:
>												/* preds: block_211 */
>												/* succs: block_213 block_214 */
>												if ssa_1573 {
>													block block_213:
>													/* preds: block_212 */
>													r108 = flt32 ssa_82, abs(ssa_1608)
>													/* succs: block_215 */
>												} else {
>													block block_214:
>													/* preds: block_212 */
>													r108 = imov ssa_83
>													/* succs: block_215 */
>												}
>												block block_215:
>												/* preds: block_213 block_214 */
>												/* succs: block_216 block_217 */
>												if r108 {
>													block block_216:
>													/* preds: block_215 */
>													vec1 32 ssa_1634 = frcp ssa_1608
>													vec1 32 ssa_1635 = fmul ssa_1608, ssa_1592
>													vec1 32 ssa_1636 = ffma ssa_1610, ssa_1610, -ssa_1635
>													vec1 32 ssa_1637 = fmax ssa_1636, ssa_1
>													vec1 32 ssa_1638 = flt32 ssa_1636, ssa_1
>													r107 = b32csel ssa_1638, ssa_1, r107
>													vec1 32 ssa_1640 = fsqrt ssa_1637
>													vec1 32 ssa_1641 = fadd ssa_1610, -ssa_1640
>													r109 = fmul ssa_1641, ssa_1634
>													vec1 32 ssa_1643 = fadd ssa_1610, ssa_1640
>													r110 = fmul ssa_1643, ssa_1634
>													/* succs: block_218 */
>												} else {
>													block block_217:
>													/* preds: block_215 */
>													vec1 32 ssa_1645 = fmul ssa_37, ssa_1592
>													vec1 32 ssa_1646 = frcp ssa_1610
>													r110 = fmul ssa_1645, ssa_1646
>													r109 = imov r110
>													/* succs: block_218 */
>												}
>												block block_218:
>												/* preds: block_216 block_217 */
>												vec1 32 ssa_1651 = fmul ssa_1609, ssa_33
>												vec1 32 ssa_1652 = ffma ssa_1607, r109, -ssa_1651
>												vec1 32 ssa_1653 = ffma ssa_1652, r109, ssa_1590
>												vec1 32 ssa_1654 = ffma ssa_1607, r110, -ssa_1651
>												vec1 32 ssa_1655 = ffma ssa_1654, r110, ssa_1590
>												vec1 32 ssa_1656 = iand r107, ssa_30
>												vec1 32 ssa_1657 = ine32 ssa_1656, ssa_1
>												/* succs: block_219 block_223 */
>												if ssa_1657 {
>													block block_219:
>													/* preds: block_218 */
>													vec1 32 ssa_1658 = fge32 ssa_1653, ssa_1
>													vec1 32 ssa_1659 = fge32 ssa_1540, ssa_1653
>													vec1 32 ssa_1660 = iand ssa_1659, ssa_1658
>													r111 = b32csel ssa_1660, ssa_30, ssa_1
>													vec1 32 ssa_1662 = flt32 ssa_1653, ssa_1
>													/* succs: block_220 block_221 */
>													if ssa_1662 {
>														block block_220:
>														/* preds: block_219 */
>														r99 = fmin r99, abs(ssa_1653)
>														/* succs: block_222 */
>													} else {
>														block block_221:
>														/* preds: block_219 */
>														r98 = fmin r98, abs(ssa_1653)
>														/* succs: block_222 */
>													}
>													block block_222:
>													/* preds: block_220 block_221 */
>													/* succs: block_224 */
>												} else {
>													block block_223:
>													/* preds: block_218 */
>													r111 = imov ssa_1
>													/* succs: block_224 */
>												}
>												block block_224:
>												/* preds: block_222 block_223 */
>												vec1 32 ssa_1670 = ult32 ssa_30, r107
>												/* succs: block_225 block_229 */
>												if ssa_1670 {
>													block block_225:
>													/* preds: block_224 */
>													vec1 32 ssa_1671 = fge32 ssa_1655, ssa_1
>													vec1 32 ssa_1672 = fge32 ssa_1540, ssa_1655
>													vec1 32 ssa_1673 = iand ssa_1672, ssa_1671
>													vec1 32 ssa_1674 = iadd r111, ssa_25
>													r111 = b32csel ssa_1673, ssa_1674, r111
>													vec1 32 ssa_1676 = flt32 ssa_1, ssa_1655
>													/* succs: block_226 block_227 */
>													if ssa_1676 {
>														block block_226:
>														/* preds: block_225 */
>														r99 = fmin r99, abs(ssa_1655)
>														/* succs: block_228 */
>													} else {
>														block block_227:
>														/* preds: block_225 */
>														r98 = fmin r98, abs(ssa_1655)
>														/* succs: block_228 */
>													}
>													block block_228:
>													/* preds: block_226 block_227 */
>													/* succs: block_230 */
>												} else {
>													block block_229:
>													/* preds: block_224 */
>													/* succs: block_230 */
>												}
>												block block_230:
>												/* preds: block_228 block_229 */
>												/* succs: block_232 */
>											} else {
>												block block_231:
>												/* preds: block_211 */
>												r111 = imov ssa_1
>												/* succs: block_232 */
>											}
>											block block_232:
>											/* preds: block_230 block_231 */
>											vec1 32 ssa_1687 = ine32 r106, ssa_1
>											/* succs: block_233 block_252 */
>											if ssa_1687 {
>												block block_233:
>												/* preds: block_232 */
>												/* succs: block_234 block_235 */
>												if ssa_1573 {
>													block block_234:
>													/* preds: block_233 */
>													r112 = flt32 ssa_82, abs(ssa_1607)
>													/* succs: block_236 */
>												} else {
>													block block_235:
>													/* preds: block_233 */
>													r112 = imov ssa_83
>													/* succs: block_236 */
>												}
>												block block_236:
>												/* preds: block_234 block_235 */
>												/* succs: block_237 block_238 */
>												if r112 {
>													block block_237:
>													/* preds: block_236 */
>													vec1 32 ssa_1690 = frcp ssa_1607
>													vec1 32 ssa_1691 = fmul ssa_1607, ssa_1590
>													vec1 32 ssa_1692 = ffma ssa_1609, ssa_1609, -ssa_1691
>													vec1 32 ssa_1693 = fmax ssa_1692, ssa_1
>													vec1 32 ssa_1694 = flt32 ssa_1692, ssa_1
>													r106 = b32csel ssa_1694, ssa_1, r106
>													vec1 32 ssa_1696 = fsqrt ssa_1693
>													vec1 32 ssa_1697 = fadd ssa_1609, -ssa_1696
>													r113 = fmul ssa_1697, ssa_1690
>													vec1 32 ssa_1699 = fadd ssa_1609, ssa_1696
>													r114 = fmul ssa_1699, ssa_1690
>													/* succs: block_239 */
>												} else {
>													block block_238:
>													/* preds: block_236 */
>													vec1 32 ssa_1701 = fmul ssa_37, ssa_1590
>													vec1 32 ssa_1702 = frcp ssa_1609
>													r114 = fmul ssa_1701, ssa_1702
>													r113 = imov r114
>													/* succs: block_239 */
>												}
>												block block_239:
>												/* preds: block_237 block_238 */
>												vec1 32 ssa_1707 = fmul ssa_1610, ssa_33
>												vec1 32 ssa_1708 = ffma ssa_1608, r113, -ssa_1707
>												vec1 32 ssa_1709 = ffma ssa_1708, r113, ssa_1592
>												vec1 32 ssa_1710 = ffma ssa_1608, r114, -ssa_1707
>												vec1 32 ssa_1711 = ffma ssa_1710, r114, ssa_1592
>												vec1 32 ssa_1712 = iand r106, ssa_30
>												vec1 32 ssa_1713 = ine32 ssa_1712, ssa_1
>												/* succs: block_240 block_244 */
>												if ssa_1713 {
>													block block_240:
>													/* preds: block_239 */
>													vec1 32 ssa_1714 = flt32 ssa_1, ssa_1709
>													/* succs: block_241 block_242 */
>													if ssa_1714 {
>														block block_241:
>														/* preds: block_240 */
>														r99 = fmin r99, abs(ssa_1709)
>														/* succs: block_243 */
>													} else {
>														block block_242:
>														/* preds: block_240 */
>														r98 = fmin r98, abs(ssa_1709)
>														/* succs: block_243 */
>													}
>													block block_243:
>													/* preds: block_241 block_242 */
>													/* succs: block_245 */
>												} else {
>													block block_244:
>													/* preds: block_239 */
>													/* succs: block_245 */
>												}
>												block block_245:
>												/* preds: block_243 block_244 */
>												vec1 32 ssa_1721 = ult32 ssa_30, r106
>												/* succs: block_246 block_250 */
>												if ssa_1721 {
>													block block_246:
>													/* preds: block_245 */
>													vec1 32 ssa_1722 = flt32 ssa_1711, ssa_1
>													/* succs: block_247 block_248 */
>													if ssa_1722 {
>														block block_247:
>														/* preds: block_246 */
>														r99 = fmin r99, abs(ssa_1711)
>														/* succs: block_249 */
>													} else {
>														block block_248:
>														/* preds: block_246 */
>														r98 = fmin r98, abs(ssa_1711)
>														/* succs: block_249 */
>													}
>													block block_249:
>													/* preds: block_247 block_248 */
>													/* succs: block_251 */
>												} else {
>													block block_250:
>													/* preds: block_245 */
>													/* succs: block_251 */
>												}
>												block block_251:
>												/* preds: block_249 block_250 */
>												/* succs: block_253 */
>											} else {
>												block block_252:
>												/* preds: block_232 */
>												/* succs: block_253 */
>											}
>											block block_253:
>											/* preds: block_251 block_252 */
>											r95 = iadd r95, r111
>											vec1 32 ssa_1732 = iadd r97, ssa_30
>											vec1 32 ssa_1733 = ult32 ssa_1732, ssa_1488
>											/* succs: block_254 block_300 */
>											if ssa_1733 {
>												block block_254:
>												/* preds: block_253 */
>												vec1 32 ssa_1734 = extract_u16 ssa_1557, ssa_30
>												vec1 32 ssa_1735 = ishl ssa_1734, ssa_75
>												vec1 32 ssa_1736 = ushr ssa_1735, ssa_75
>												vec1 32 ssa_1737 = iadd r87, ssa_1736
>												vec1 32 ssa_1738 = iand ssa_1734, ssa_79
>												vec1 32 ssa_1739 = ishl ssa_1737, ssa_31
>												vec1 32 ssa_1740 = intrinsic load_ssbo (ssa_30, ssa_1739) (0, 4, 0) /* access=0 */ /* align_mul=4 */ /* align_offset=0 */
>												vec1 32 ssa_1741 = unpack_half_2x16_split_x ssa_1740
>												vec1 32 ssa_1742 = unpack_half_2x16_split_y ssa_1740
>												vec1 32 ssa_1743 = iadd ssa_1737, ssa_30
>												vec1 32 ssa_1744 = ishl ssa_1743, ssa_31
>												vec1 32 ssa_1745 = intrinsic load_ssbo (ssa_30, ssa_1744) (0, 4, 0) /* access=0 */ /* align_mul=4 */ /* align_offset=0 */
>												r115 = unpack_half_2x16_split_x ssa_1745
>												r116 = unpack_half_2x16_split_y ssa_1745
>												vec1 32 ssa_1748 = ine32 ssa_1738, ssa_1
>												/* succs: block_255 block_256 */
>												if ssa_1748 {
>													block block_255:
>													/* preds: block_254 */
>													vec1 32 ssa_1749 = iadd ssa_1737, ssa_31
>													vec1 32 ssa_1750 = ishl ssa_1749, ssa_31
>													vec1 32 ssa_1751 = intrinsic load_ssbo (ssa_30, ssa_1750) (0, 4, 0) /* access=0 */ /* align_mul=4 */ /* align_offset=0 */
>													r117 = unpack_half_2x16_split_x ssa_1751
>													r118 = unpack_half_2x16_split_y ssa_1751
>													/* succs: block_257 */
>												} else {
>													block block_256:
>													/* preds: block_254 */
>													vec1 32 ssa_1754 = fadd ssa_1741, r115
>													vec1 32 ssa_1755 = fadd ssa_1742, r116
>													r119 = fmul ssa_37, ssa_1754
>													r120 = fmul ssa_37, ssa_1755
>													r118 = imov r116
>													r116 = imov r120
>													r117 = imov r115
>													r115 = imov r119
>													/* succs: block_257 */
>												}
>												block block_257:
>												/* preds: block_255 block_256 */
>												vec1 32 ssa_1762 = fadd ssa_1741, -ssa_5.x
>												vec1 32 ssa_1763 = fadd ssa_1742, -ssa_5.y
>												vec1 32 ssa_1764 = fmul ssa_1542, ssa_1763
>												vec1 32 ssa_1765 = ffma ssa_1541, ssa_1762, ssa_1764
>												vec1 32 ssa_1766 = fmul ssa_1548, ssa_1763
>												vec1 32 ssa_1767 = ffma ssa_1547, ssa_1762, ssa_1766
>												vec1 32 ssa_1768 = fadd r115, -ssa_5.x
>												vec1 32 ssa_1769 = fadd r116, -ssa_5.y
>												vec1 32 ssa_1770 = fmul ssa_1542, ssa_1769
>												vec1 32 ssa_1771 = ffma ssa_1541, ssa_1768, ssa_1770
>												vec1 32 ssa_1772 = fmul ssa_1548, ssa_1769
>												vec1 32 ssa_1773 = ffma ssa_1547, ssa_1768, ssa_1772
>												vec1 32 ssa_1774 = fadd r117, -ssa_5.x
>												vec1 32 ssa_1775 = fadd r118, -ssa_5.y
>												vec1 32 ssa_1776 = fmul ssa_1542, ssa_1775
>												vec1 32 ssa_1777 = ffma ssa_1541, ssa_1774, ssa_1776
>												vec1 32 ssa_1778 = fmul ssa_1548, ssa_1775
>												vec1 32 ssa_1779 = ffma ssa_1547, ssa_1774, ssa_1778
>												vec1 32 ssa_1780 = ffma -ssa_33, ssa_1771, ssa_1765
>												vec1 32 ssa_1781 = ffma -ssa_33, ssa_1773, ssa_1767
>												vec1 32 ssa_1782 = fadd ssa_1780, ssa_1777
>												vec1 32 ssa_1783 = fadd ssa_1781, ssa_1779
>												vec1 32 ssa_1784 = fadd ssa_1765, -ssa_1771
>												vec1 32 ssa_1785 = fadd ssa_1767, -ssa_1773
>												vec1 32 ssa_1786 = flt32 ssa_1, ssa_1765
>												vec1 32 ssa_1787 = b32csel ssa_1786, ssa_31, ssa_1
>												vec1 32 ssa_1788 = flt32 ssa_1, ssa_1771
>												vec1 32 ssa_1789 = b32csel ssa_1788, ssa_80, ssa_1
>												vec1 32 ssa_1790 = flt32 ssa_1, ssa_1777
>												vec1 32 ssa_1791 = b32csel ssa_1790, ssa_70, ssa_1
>												vec1 32 ssa_1792 = iadd ssa_1787, ssa_1789
>												vec1 32 ssa_1793 = iadd ssa_1792, ssa_1791
>												vec1 32 ssa_1794 = ushr ssa_81, ssa_1793
>												r121 = iand ssa_1794, ssa_32
>												vec1 32 ssa_1796 = flt32 ssa_1, ssa_1767
>												vec1 32 ssa_1797 = b32csel ssa_1796, ssa_31, ssa_1
>												vec1 32 ssa_1798 = flt32 ssa_1, ssa_1773
>												vec1 32 ssa_1799 = b32csel ssa_1798, ssa_80, ssa_1
>												vec1 32 ssa_1800 = flt32 ssa_1, ssa_1779
>												vec1 32 ssa_1801 = b32csel ssa_1800, ssa_70, ssa_1
>												vec1 32 ssa_1802 = iadd ssa_1797, ssa_1799
>												vec1 32 ssa_1803 = iadd ssa_1802, ssa_1801
>												vec1 32 ssa_1804 = ushr ssa_81, ssa_1803
>												r122 = iand ssa_1804, ssa_32
>												vec1 32 ssa_1806 = ine32 r122, ssa_1
>												/* succs: block_258 block_277 */
>												if ssa_1806 {
>													block block_258:
>													/* preds: block_257 */
>													/* succs: block_259 block_260 */
>													if ssa_1748 {
>														block block_259:
>														/* preds: block_258 */
>														r123 = flt32 ssa_82, abs(ssa_1783)
>														/* succs: block_261 */
>													} else {
>														block block_260:
>														/* preds: block_258 */
>														r123 = imov ssa_83
>														/* succs: block_261 */
>													}
>													block block_261:
>													/* preds: block_259 block_260 */
>													/* succs: block_262 block_263 */
>													if r123 {
>														block block_262:
>														/* preds: block_261 */
>														vec1 32 ssa_1809 = frcp ssa_1783
>														vec1 32 ssa_1810 = fmul ssa_1783, ssa_1767
>														vec1 32 ssa_1811 = ffma ssa_1785, ssa_1785, -ssa_1810
>														vec1 32 ssa_1812 = fmax ssa_1811, ssa_1
>														vec1 32 ssa_1813 = flt32 ssa_1811, ssa_1
>														r122 = b32csel ssa_1813, ssa_1, r122
>														vec1 32 ssa_1815 = fsqrt ssa_1812
>														vec1 32 ssa_1816 = fadd ssa_1785, -ssa_1815
>														r124 = fmul ssa_1816, ssa_1809
>														vec1 32 ssa_1818 = fadd ssa_1785, ssa_1815
>														r125 = fmul ssa_1818, ssa_1809
>														/* succs: block_264 */
>													} else {
>														block block_263:
>														/* preds: block_261 */
>														vec1 32 ssa_1820 = fmul ssa_37, ssa_1767
>														vec1 32 ssa_1821 = frcp ssa_1785
>														r125 = fmul ssa_1820, ssa_1821
>														r124 = imov r125
>														/* succs: block_264 */
>													}
>													block block_264:
>													/* preds: block_262 block_263 */
>													vec1 32 ssa_1826 = fmul ssa_1784, ssa_33
>													vec1 32 ssa_1827 = ffma ssa_1782, r124, -ssa_1826
>													vec1 32 ssa_1828 = ffma ssa_1827, r124, ssa_1765
>													vec1 32 ssa_1829 = ffma ssa_1782, r125, -ssa_1826
>													vec1 32 ssa_1830 = ffma ssa_1829, r125, ssa_1765
>													vec1 32 ssa_1831 = iand r122, ssa_30
>													vec1 32 ssa_1832 = ine32 ssa_1831, ssa_1
>													/* succs: block_265 block_269 */
>													if ssa_1832 {
>														block block_265:
>														/* preds: block_264 */
>														vec1 32 ssa_1833 = fge32 ssa_1828, ssa_1
>														vec1 32 ssa_1834 = fge32 ssa_1540, ssa_1828
>														vec1 32 ssa_1835 = iand ssa_1834, ssa_1833
>														r126 = b32csel ssa_1835, ssa_30, ssa_1
>														vec1 32 ssa_1837 = flt32 ssa_1828, ssa_1
>														/* succs: block_266 block_267 */
>														if ssa_1837 {
>															block block_266:
>															/* preds: block_265 */
>															r99 = fmin r99, abs(ssa_1828)
>															/* succs: block_268 */
>														} else {
>															block block_267:
>															/* preds: block_265 */
>															r98 = fmin r98, abs(ssa_1828)
>															/* succs: block_268 */
>														}
>														block block_268:
>														/* preds: block_266 block_267 */
>														/* succs: block_270 */
>													} else {
>														block block_269:
>														/* preds: block_264 */
>														r126 = imov ssa_1
>														/* succs: block_270 */
>													}
>													block block_270:
>													/* preds: block_268 block_269 */
>													vec1 32 ssa_1845 = ult32 ssa_30, r122
>													/* succs: block_271 block_275 */
>													if ssa_1845 {
>														block block_271:
>														/* preds: block_270 */
>														vec1 32 ssa_1846 = fge32 ssa_1830, ssa_1
>														vec1 32 ssa_1847 = fge32 ssa_1540, ssa_1830
>														vec1 32 ssa_1848 = iand ssa_1847, ssa_1846
>														vec1 32 ssa_1849 = iadd r126, ssa_25
>														r126 = b32csel ssa_1848, ssa_1849, r126
>														vec1 32 ssa_1851 = flt32 ssa_1, ssa_1830
>														/* succs: block_272 block_273 */
>														if ssa_1851 {
>															block block_272:
>															/* preds: block_271 */
>															r99 = fmin r99, abs(ssa_1830)
>															/* succs: block_274 */
>														} else {
>															block block_273:
>															/* preds: block_271 */
>															r98 = fmin r98, abs(ssa_1830)
>															/* succs: block_274 */
>														}
>														block block_274:
>														/* preds: block_272 block_273 */
>														/* succs: block_276 */
>													} else {
>														block block_275:
>														/* preds: block_270 */
>														/* succs: block_276 */
>													}
>													block block_276:
>													/* preds: block_274 block_275 */
>													/* succs: block_278 */
>												} else {
>													block block_277:
>													/* preds: block_257 */
>													r126 = imov ssa_1
>													/* succs: block_278 */
>												}
>												block block_278:
>												/* preds: block_276 block_277 */
>												vec1 32 ssa_1862 = ine32 r121, ssa_1
>												/* succs: block_279 block_298 */
>												if ssa_1862 {
>													block block_279:
>													/* preds: block_278 */
>													/* succs: block_280 block_281 */
>													if ssa_1748 {
>														block block_280:
>														/* preds: block_279 */
>														r127 = flt32 ssa_82, abs(ssa_1782)
>														/* succs: block_282 */
>													} else {
>														block block_281:
>														/* preds: block_279 */
>														r127 = imov ssa_83
>														/* succs: block_282 */
>													}
>													block block_282:
>													/* preds: block_280 block_281 */
>													/* succs: block_283 block_284 */
>													if r127 {
>														block block_283:
>														/* preds: block_282 */
>														vec1 32 ssa_1865 = frcp ssa_1782
>														vec1 32 ssa_1866 = fmul ssa_1782, ssa_1765
>														vec1 32 ssa_1867 = ffma ssa_1784, ssa_1784, -ssa_1866
>														vec1 32 ssa_1868 = fmax ssa_1867, ssa_1
>														vec1 32 ssa_1869 = flt32 ssa_1867, ssa_1
>														r121 = b32csel ssa_1869, ssa_1, r121
>														vec1 32 ssa_1871 = fsqrt ssa_1868
>														vec1 32 ssa_1872 = fadd ssa_1784, -ssa_1871
>														r128 = fmul ssa_1872, ssa_1865
>														vec1 32 ssa_1874 = fadd ssa_1784, ssa_1871
>														r129 = fmul ssa_1874, ssa_1865
>														/* succs: block_285 */
>													} else {
>														block block_284:
>														/* preds: block_282 */
>														vec1 32 ssa_1876 = fmul ssa_37, ssa_1765
>														vec1 32 ssa_1877 = frcp ssa_1784
>														r129 = fmul ssa_1876, ssa_1877
>														r128 = imov r129
>														/* succs: block_285 */
>													}
>													block block_285:
>													/* preds: block_283 block_284 */
>													vec1 32 ssa_1882 = fmul ssa_1785, ssa_33
>													vec1 32 ssa_1883 = ffma ssa_1783, r128, -ssa_1882
>													vec1 32 ssa_1884 = ffma ssa_1883, r128, ssa_1767
>													vec1 32 ssa_1885 = ffma ssa_1783, r129, -ssa_1882
>													vec1 32 ssa_1886 = ffma ssa_1885, r129, ssa_1767
>													vec1 32 ssa_1887 = iand r121, ssa_30
>													vec1 32 ssa_1888 = ine32 ssa_1887, ssa_1
>													/* succs: block_286 block_290 */
>													if ssa_1888 {
>														block block_286:
>														/* preds: block_285 */
>														vec1 32 ssa_1889 = flt32 ssa_1, ssa_1884
>														/* succs: block_287 block_288 */
>														if ssa_1889 {
>															block block_287:
>															/* preds: block_286 */
>															r99 = fmin r99, abs(ssa_1884)
>															/* succs: block_289 */
>														} else {
>															block block_288:
>															/* preds: block_286 */
>															r98 = fmin r98, abs(ssa_1884)
>															/* succs: block_289 */
>														}
>														block block_289:
>														/* preds: block_287 block_288 */
>														/* succs: block_291 */
>													} else {
>														block block_290:
>														/* preds: block_285 */
>														/* succs: block_291 */
>													}
>													block block_291:
>													/* preds: block_289 block_290 */
>													vec1 32 ssa_1896 = ult32 ssa_30, r121
>													/* succs: block_292 block_296 */
>													if ssa_1896 {
>														block block_292:
>														/* preds: block_291 */
>														vec1 32 ssa_1897 = flt32 ssa_1886, ssa_1
>														/* succs: block_293 block_294 */
>														if ssa_1897 {
>															block block_293:
>															/* preds: block_292 */
>															r99 = fmin r99, abs(ssa_1886)
>															/* succs: block_295 */
>														} else {
>															block block_294:
>															/* preds: block_292 */
>															r98 = fmin r98, abs(ssa_1886)
>															/* succs: block_295 */
>														}
>														block block_295:
>														/* preds: block_293 block_294 */
>														/* succs: block_297 */
>													} else {
>														block block_296:
>														/* preds: block_291 */
>														/* succs: block_297 */
>													}
>													block block_297:
>													/* preds: block_295 block_296 */
>													/* succs: block_299 */
>												} else {
>													block block_298:
>													/* preds: block_278 */
>													/* succs: block_299 */
>												}
>												block block_299:
>												/* preds: block_297 block_298 */
>												r95 = iadd r95, r126
>												/* succs: block_301 */
>											} else {
>												block block_300:
>												/* preds: block_253 */
>												/* succs: block_301 */
>											}
>											block block_301:
>											/* preds: block_299 block_300 */
>											r97 = iadd r97, ssa_31
>											/* succs: block_205 */
>										}
>										block block_302:
>										/* preds: block_206 */
>										vec1 32 ssa_1911 = ieq32 r95, ssa_1
>										vec1 32 ssa_1912 = ior ssa_1911, ssa_1448
>										/* succs: block_303 block_304 */
>										if ssa_1912 {
>											block block_303:
>											/* preds: block_302 */
>											r99 = fmin r99, r98
>											/* succs: block_308 */
>										} else {
>											block block_304:
>											/* preds: block_302 */
>											vec1 32 ssa_1914 = ine32 r95, ssa_25
>											/* succs: block_305 block_306 */
>											if ssa_1914 {
>												block block_305:
>												/* preds: block_304 */
>												vec1 32 ssa_1915 = ieq32 r95, ssa_30
>												r99 = b32csel ssa_1915, r98, ssa_37
>												/* succs: block_307 */
>											} else {
>												block block_306:
>												/* preds: block_304 */
>												/* succs: block_307 */
>											}
>											block block_307:
>											/* preds: block_305 block_306 */
>											/* succs: block_308 */
>										}
>										block block_308:
>										/* preds: block_303 block_307 */
>										vec1 32 ssa_1919 = fmin r99, ssa_37
>										vec1 32 ssa_1920 = iand r95, ssa_30
>										vec1 32 ssa_1921 = ieq32 ssa_1920, ssa_1
>										vec1 32 ssa_1922 = iand ssa_1448, ssa_1921
>										vec1 32 ssa_1923 = b32csel ssa_1922, ssa_1, r95
>										vec1 32 ssa_1924 = ine32 ssa_1923, ssa_1
>										/* succs: block_309 block_310 */
>										if ssa_1924 {
>											block block_309:
>											/* preds: block_308 */
>											r13 = fadd ssa_37, ssa_1919
>											/* succs: block_311 */
>										} else {
>											block block_310:
>											/* preds: block_308 */
>											r13 = fadd ssa_37, -ssa_1919
>											/* succs: block_311 */
>										}
>										block block_311:
>										/* preds: block_309 block_310 */
>										vec1 32 ssa_1928 = iand ssa_1438.x, ssa_33
>										vec1 32 ssa_1929 = ine32 ssa_1928, ssa_1
>										/* succs: block_312 block_313 */
>										if ssa_1929 {
>											block block_312:
>											/* preds: block_311 */
>											r13 = fadd ssa_35, -r13
>											/* succs: block_314 */
>										} else {
>											block block_313:
>											/* preds: block_311 */
>											/* succs: block_314 */
>										}
>										block block_314:
>										/* preds: block_312 block_313 */
>										r10 = imov r13
>										r11 = imov r10
>										r12 = imov r11
>										/* succs: block_386 */
>									} else {
>										block block_315:
>										/* preds: block_195 */
>										vec1 32 ssa_1932 = ieq32 ssa_1123.y, ssa_53
>										/* succs: block_316 block_384 */
>										if ssa_1932 {
>											block block_316:
>											/* preds: block_315 */
>											vec1 32 ssa_1933 = fddx ssa_5.x
>											vec4 32 ssa_1934 = intrinsic load_uniform (ssa_1) (0, 16) /* base=0 */ /* range=16 */	/* fastuidraw_painterStore */
>											vec1 32 ssa_1935 = fmul ssa_5.x, ssa_1934.x
>											vec1 32 ssa_1936 = fddy ssa_1935
>											vec1 32 ssa_1937 = fadd abs(ssa_1933), abs(ssa_1936)
>											vec1 32 ssa_1938 = fddx ssa_5.y
>											vec1 32 ssa_1939 = fmul ssa_5.y, ssa_1934.x
>											vec1 32 ssa_1940 = fddy ssa_1939
>											vec1 32 ssa_1941 = fadd abs(ssa_1938), abs(ssa_1940)
>											vec4 32 ssa_1942 = intrinsic load_input (ssa_1) (31, 0) /* base=31 */ /* component=0 */	/* fastuidraw_uint_varying0 */
>											vec1 32 ssa_1943 = iand ssa_1942.x, ssa_73
>											vec1 32 ssa_1944 = iand ssa_1942.x, ssa_26
>											vec1 32 ssa_1945 = ine32 ssa_1944, ssa_1
>											vec1 32 ssa_1946 = frcp ssa_1937
>											vec1 32 ssa_1947 = frcp ssa_1941
>											vec1 32 ssa_1948 = u2f32 ssa_1942.z
>											vec1 32 ssa_1949 = u2f32 ssa_1942.y
>											vec1 32 ssa_1950 = iadd ssa_1942.z, ssa_25
>											vec1 32 ssa_1951 = fadd ssa_5.x, ssa_56
>											vec1 32 ssa_1952 = fmul ssa_1948, ssa_84
>											vec1 32 ssa_1953 = fmul ssa_1952, ssa_1951
>											vec1 32 ssa_1954 = f2u32 ssa_1953
>											vec1 32 ssa_1955 = umin ssa_1950, ssa_1954
>											vec1 32 ssa_1956 = iadd ssa_1942.y, ssa_25
>											vec1 32 ssa_1957 = fadd ssa_5.y, ssa_56
>											vec1 32 ssa_1958 = fmul ssa_1949, ssa_84
>											vec1 32 ssa_1959 = fmul ssa_1958, ssa_1957
>											vec1 32 ssa_1960 = f2u32 ssa_1959
>											vec1 32 ssa_1961 = umin ssa_1956, ssa_1960
>											vec1 32 ssa_1962 = iadd ssa_1961, ssa_1942.y
>											vec1 32 ssa_1963 = flt32 ssa_5.x, ssa_1
>											vec1 32 ssa_1964 = b32csel ssa_1963, ssa_51, ssa_35
>											vec1 32 ssa_1965 = b32csel ssa_1963, ssa_1962, ssa_1961
>											vec1 32 ssa_1966 = ishl ssa_1942.y, ssa_30
>											vec1 32 ssa_1967 = iadd ssa_1955, ssa_1966
>											vec1 32 ssa_1968 = iadd ssa_1967, ssa_1942.z
>											vec1 32 ssa_1969 = flt32 ssa_5.y, ssa_1
>											vec1 32 ssa_1970 = b32csel ssa_1969, ssa_51, ssa_35
>											vec1 32 ssa_1971 = b32csel ssa_1969, ssa_1968, ssa_1967
>											vec1 32 ssa_1972 = iadd ssa_1943, ssa_1965
>											vec1 32 ssa_1973 = ishl ssa_1972, ssa_31
>											vec1 32 ssa_1974 = intrinsic load_ssbo (ssa_30, ssa_1973) (0, 4, 0) /* access=0 */ /* align_mul=4 */ /* align_offset=0 */
>											vec1 32 ssa_1975 = extract_u8 ssa_1974, ssa_1
>											vec1 32 ssa_1976 = iadd ssa_1943, ssa_1971
>											vec1 32 ssa_1977 = ishl ssa_1976, ssa_31
>											vec1 32 ssa_1978 = intrinsic load_ssbo (ssa_30, ssa_1977) (0, 4, 0) /* access=0 */ /* align_mul=4 */ /* align_offset=0 */
>											vec1 32 ssa_1979 = extract_u8 ssa_1978, ssa_1
>											vec1 32 ssa_1980 = ushr ssa_1978, ssa_70
>											vec1 32 ssa_1981 = ushr ssa_1974, ssa_70
>											r130 = iadd ssa_1981, ssa_1943
>											r133 = imov ssa_1
>											r132 = imov r133
>											r131 = imov ssa_37
>											/* succs: block_317 */
>											loop {
>												block block_317:
>												/* preds: block_316 block_344 */
>												vec1 32 ssa_1987 = uge32 r133, ssa_1975
>												/* succs: block_318 block_319 */
>												if ssa_1987 {
>													block block_318:
>													/* preds: block_317 */
>													break
>													/* succs: block_345 */
>												} else {
>													block block_319:
>													/* preds: block_317 */
>													/* succs: block_320 */
>												}
>												block block_320:
>												/* preds: block_319 */
>												vec1 32 ssa_1988 = ishl r130, ssa_31
>												vec1 32 ssa_1989 = intrinsic load_ssbo (ssa_30, ssa_1988) (0, 4, 0) /* access=0 */ /* align_mul=4 */ /* align_offset=0 */
>												vec1 32 ssa_1990 = unpack_half_2x16_split_x ssa_1989
>												vec1 32 ssa_1991 = unpack_half_2x16_split_y ssa_1989
>												vec1 32 ssa_1992 = fadd ssa_1990, -ssa_5.x
>												vec1 32 ssa_1993 = fadd ssa_1991, -ssa_5.y
>												vec1 32 ssa_1994 = iadd r130, ssa_30
>												vec1 32 ssa_1995 = ishl ssa_1994, ssa_31
>												vec1 32 ssa_1996 = intrinsic load_ssbo (ssa_30, ssa_1995) (0, 4, 0) /* access=0 */ /* align_mul=4 */ /* align_offset=0 */
>												vec1 32 ssa_1997 = unpack_half_2x16_split_x ssa_1996
>												vec1 32 ssa_1998 = unpack_half_2x16_split_y ssa_1996
>												vec1 32 ssa_1999 = fadd ssa_1997, -ssa_5.x
>												vec1 32 ssa_2000 = fadd ssa_1998, -ssa_5.y
>												vec1 32 ssa_2001 = iadd r130, ssa_31
>												vec1 32 ssa_2002 = ishl ssa_2001, ssa_31
>												vec1 32 ssa_2003 = intrinsic load_ssbo (ssa_30, ssa_2002) (0, 4, 0) /* access=0 */ /* align_mul=4 */ /* align_offset=0 */
>												vec1 32 ssa_2004 = unpack_half_2x16_split_x ssa_2003
>												vec1 32 ssa_2005 = unpack_half_2x16_split_y ssa_2003
>												vec1 32 ssa_2006 = fadd ssa_2004, -ssa_5.x
>												vec1 32 ssa_2007 = fadd ssa_2005, -ssa_5.y
>												vec1 32 ssa_2008 = fge32 ssa_5.x, ssa_1
>												/* succs: block_321 block_322 */
>												if ssa_2008 {
>													block block_321:
>													/* preds: block_320 */
>													vec1 32 ssa_2009 = fmax ssa_1999, ssa_2006
>													vec1 32 ssa_2010 = fmax ssa_1992, ssa_2009
>													vec1 32 ssa_2011 = fmul ssa_2010, ssa_1946
>													r134 = flt32 ssa_2011, ssa_63
>													/* succs: block_323 */
>												} else {
>													block block_322:
>													/* preds: block_320 */
>													r134 = imov ssa_83
>													/* succs: block_323 */
>												}
>												block block_323:
>												/* preds: block_321 block_322 */
>												/* succs: block_324 block_325 */
>												if r134 {
>													block block_324:
>													/* preds: block_323 */
>													break
>													/* succs: block_345 */
>												} else {
>													block block_325:
>													/* preds: block_323 */
>													/* succs: block_326 */
>												}
>												block block_326:
>												/* preds: block_325 */
>												/* succs: block_327 block_328 */
>												if ssa_1963 {
>													block block_327:
>													/* preds: block_326 */
>													vec1 32 ssa_2014 = fmin ssa_1999, ssa_2006
>													vec1 32 ssa_2015 = fmin ssa_1992, ssa_2014
>													vec1 32 ssa_2016 = fmul ssa_2015, ssa_1946
>													r135 = flt32 ssa_37, ssa_2016
>													/* succs: block_329 */
>												} else {
>													block block_328:
>													/* preds: block_326 */
>													r135 = imov ssa_83
>													/* succs: block_329 */
>												}
>												block block_329:
>												/* preds: block_327 block_328 */
>												/* succs: block_330 block_331 */
>												if r135 {
>													block block_330:
>													/* preds: block_329 */
>													break
>													/* succs: block_345 */
>												} else {
>													block block_331:
>													/* preds: block_329 */
>													/* succs: block_332 */
>												}
>												block block_332:
>												/* preds: block_331 */
>												vec1 32 ssa_2019 = flt32 ssa_1, ssa_1993
>												vec1 32 ssa_2020 = b32csel ssa_2019, ssa_31, ssa_1
>												vec1 32 ssa_2021 = flt32 ssa_1, ssa_2000
>												vec1 32 ssa_2022 = b32csel ssa_2021, ssa_80, ssa_1
>												vec1 32 ssa_2023 = flt32 ssa_1, ssa_2007
>												vec1 32 ssa_2024 = b32csel ssa_2023, ssa_70, ssa_1
>												vec1 32 ssa_2025 = ior ssa_2020, ssa_2022
>												vec1 32 ssa_2026 = ior ssa_2025, ssa_2024
>												vec1 32 ssa_2027 = ushr ssa_81, ssa_2026
>												vec1 32 ssa_2028 = iand ssa_2027, ssa_32
>												vec1 32 ssa_2029 = ine32 ssa_2028, ssa_1
>												/* succs: block_333 block_343 */
>												if ssa_2029 {
>													block block_333:
>													/* preds: block_332 */
>													vec1 32 ssa_2030 = ffma -ssa_33, ssa_1999, ssa_1992
>													vec1 32 ssa_2031 = ffma -ssa_33, ssa_2000, ssa_1993
>													vec1 32 ssa_2032 = fadd ssa_2030, ssa_2006
>													vec1 32 ssa_2033 = fadd ssa_2031, ssa_2007
>													vec1 32 ssa_2034 = fadd ssa_1992, -ssa_1999
>													vec1 32 ssa_2035 = fadd ssa_1993, -ssa_2000
>													vec1 32 ssa_2036 = frcp ssa_2033
>													vec1 32 ssa_2037 = fmul ssa_2033, ssa_1993
>													vec1 32 ssa_2038 = ffma ssa_2035, ssa_2035, -ssa_2037
>													vec1 32 ssa_2039 = fmax ssa_2038, ssa_1
>													vec1 32 ssa_2040 = fsqrt ssa_2039
>													vec1 32 ssa_2041 = fadd ssa_2035, -ssa_2040
>													r136 = fmul ssa_2041, ssa_2036
>													vec1 32 ssa_2043 = fadd ssa_2035, ssa_2040
>													r137 = fmul ssa_2043, ssa_2036
>													vec1 32 ssa_2045 = flt32 abs(ssa_2033), ssa_82
>													/* succs: block_334 block_335 */
>													if ssa_2045 {
>														block block_334:
>														/* preds: block_333 */
>														vec1 32 ssa_2046 = fmul ssa_37, ssa_1993
>														vec1 32 ssa_2047 = frcp ssa_2035
>														r137 = fmul ssa_2046, ssa_2047
>														r136 = imov r137
>														/* succs: block_336 */
>													} else {
>														block block_335:
>														/* preds: block_333 */
>														/* succs: block_336 */
>													}
>													block block_336:
>													/* preds: block_334 block_335 */
>													vec1 32 ssa_2051 = fmul ssa_2034, ssa_33
>													vec1 32 ssa_2052 = ffma ssa_2032, r136, -ssa_2051
>													vec1 32 ssa_2053 = ffma ssa_2052, r136, ssa_1992
>													vec1 32 ssa_2054 = ffma ssa_2032, r137, -ssa_2051
>													vec1 32 ssa_2055 = ffma ssa_2054, r137, ssa_1992
>													vec1 32 ssa_2056 = fmul ssa_1946, ssa_2053
>													vec1 32 ssa_2057 = fmul ssa_1946, ssa_2055
>													vec1 32 ssa_2058 = iand ssa_2028, ssa_30
>													vec1 32 ssa_2059 = ine32 ssa_2058, ssa_1
>													/* succs: block_337 block_338 */
>													if ssa_2059 {
>														block block_337:
>														/* preds: block_336 */
>														vec1 32 ssa_2060 = ffma.sat ssa_2056, ssa_1964, ssa_37
>														r132 = fadd r132, ssa_2060
>														r131 = fmin r131, abs(ssa_2056)
>														/* succs: block_339 */
>													} else {
>														block block_338:
>														/* preds: block_336 */
>														/* succs: block_339 */
>													}
>													block block_339:
>													/* preds: block_337 block_338 */
>													vec1 32 ssa_2065 = ult32 ssa_30, ssa_2028
>													/* succs: block_340 block_341 */
>													if ssa_2065 {
>														block block_340:
>														/* preds: block_339 */
>														vec1 32 ssa_2066 = ffma.sat ssa_2057, ssa_1964, ssa_37
>														r132 = fadd r132, -ssa_2066
>														r131 = fmin r131, abs(ssa_2057)
>														/* succs: block_342 */
>													} else {
>														block block_341:
>														/* preds: block_339 */
>														/* succs: block_342 */
>													}
>													block block_342:
>													/* preds: block_340 block_341 */
>													/* succs: block_344 */
>												} else {
>													block block_343:
>													/* preds: block_332 */
>													/* succs: block_344 */
>												}
>												block block_344:
>												/* preds: block_342 block_343 */
>												r130 = iadd r130, ssa_32
>												r133 = iadd r133, ssa_30
>												/* succs: block_317 */
>											}
>											block block_345:
>											/* preds: block_318 block_324 block_330 */
>											r138 = fmov abs(r132)
>											r139 = iadd ssa_1980, ssa_1943
>											r142 = imov ssa_1
>											r141 = imov r142
>											r140 = imov ssa_37
>											/* succs: block_346 */
>											loop {
>												block block_346:
>												/* preds: block_345 block_373 */
>												vec1 32 ssa_2081 = uge32 r142, ssa_1979
>												/* succs: block_347 block_348 */
>												if ssa_2081 {
>													block block_347:
>													/* preds: block_346 */
>													break
>													/* succs: block_374 */
>												} else {
>													block block_348:
>													/* preds: block_346 */
>													/* succs: block_349 */
>												}
>												block block_349:
>												/* preds: block_348 */
>												vec1 32 ssa_2082 = ishl r139, ssa_31
>												vec1 32 ssa_2083 = intrinsic load_ssbo (ssa_30, ssa_2082) (0, 4, 0) /* access=0 */ /* align_mul=4 */ /* align_offset=0 */
>												vec1 32 ssa_2084 = unpack_half_2x16_split_x ssa_2083
>												vec1 32 ssa_2085 = unpack_half_2x16_split_y ssa_2083
>												vec1 32 ssa_2086 = fadd ssa_2084, -ssa_5.y
>												vec1 32 ssa_2087 = fadd ssa_2085, -ssa_5.x
>												vec1 32 ssa_2088 = iadd r139, ssa_30
>												vec1 32 ssa_2089 = ishl ssa_2088, ssa_31
>												vec1 32 ssa_2090 = intrinsic load_ssbo (ssa_30, ssa_2089) (0, 4, 0) /* access=0 */ /* align_mul=4 */ /* align_offset=0 */
>												vec1 32 ssa_2091 = unpack_half_2x16_split_x ssa_2090
>												vec1 32 ssa_2092 = unpack_half_2x16_split_y ssa_2090
>												vec1 32 ssa_2093 = fadd ssa_2091, -ssa_5.y
>												vec1 32 ssa_2094 = fadd ssa_2092, -ssa_5.x
>												vec1 32 ssa_2095 = iadd r139, ssa_31
>												vec1 32 ssa_2096 = ishl ssa_2095, ssa_31
>												vec1 32 ssa_2097 = intrinsic load_ssbo (ssa_30, ssa_2096) (0, 4, 0) /* access=0 */ /* align_mul=4 */ /* align_offset=0 */
>												vec1 32 ssa_2098 = unpack_half_2x16_split_x ssa_2097
>												vec1 32 ssa_2099 = unpack_half_2x16_split_y ssa_2097
>												vec1 32 ssa_2100 = fadd ssa_2098, -ssa_5.y
>												vec1 32 ssa_2101 = fadd ssa_2099, -ssa_5.x
>												vec1 32 ssa_2102 = fge32 ssa_5.y, ssa_1
>												/* succs: block_350 block_351 */
>												if ssa_2102 {
>													block block_350:
>													/* preds: block_349 */
>													vec1 32 ssa_2103 = fmax ssa_2093, ssa_2100
>													vec1 32 ssa_2104 = fmax ssa_2086, ssa_2103
>													vec1 32 ssa_2105 = fmul ssa_2104, ssa_1947
>													r143 = flt32 ssa_2105, ssa_63
>													/* succs: block_352 */
>												} else {
>													block block_351:
>													/* preds: block_349 */
>													r143 = imov ssa_83
>													/* succs: block_352 */
>												}
>												block block_352:
>												/* preds: block_350 block_351 */
>												/* succs: block_353 block_354 */
>												if r143 {
>													block block_353:
>													/* preds: block_352 */
>													break
>													/* succs: block_374 */
>												} else {
>													block block_354:
>													/* preds: block_352 */
>													/* succs: block_355 */
>												}
>												block block_355:
>												/* preds: block_354 */
>												/* succs: block_356 block_357 */
>												if ssa_1969 {
>													block block_356:
>													/* preds: block_355 */
>													vec1 32 ssa_2108 = fmin ssa_2093, ssa_2100
>													vec1 32 ssa_2109 = fmin ssa_2086, ssa_2108
>													vec1 32 ssa_2110 = fmul ssa_2109, ssa_1947
>													r144 = flt32 ssa_37, ssa_2110
>													/* succs: block_358 */
>												} else {
>													block block_357:
>													/* preds: block_355 */
>													r144 = imov ssa_83
>													/* succs: block_358 */
>												}
>												block block_358:
>												/* preds: block_356 block_357 */
>												/* succs: block_359 block_360 */
>												if r144 {
>													block block_359:
>													/* preds: block_358 */
>													break
>													/* succs: block_374 */
>												} else {
>													block block_360:
>													/* preds: block_358 */
>													/* succs: block_361 */
>												}
>												block block_361:
>												/* preds: block_360 */
>												vec1 32 ssa_2113 = flt32 ssa_1, ssa_2087
>												vec1 32 ssa_2114 = b32csel ssa_2113, ssa_31, ssa_1
>												vec1 32 ssa_2115 = flt32 ssa_1, ssa_2094
>												vec1 32 ssa_2116 = b32csel ssa_2115, ssa_80, ssa_1
>												vec1 32 ssa_2117 = flt32 ssa_1, ssa_2101
>												vec1 32 ssa_2118 = b32csel ssa_2117, ssa_70, ssa_1
>												vec1 32 ssa_2119 = ior ssa_2114, ssa_2116
>												vec1 32 ssa_2120 = ior ssa_2119, ssa_2118
>												vec1 32 ssa_2121 = ushr ssa_81, ssa_2120
>												vec1 32 ssa_2122 = iand ssa_2121, ssa_32
>												vec1 32 ssa_2123 = ine32 ssa_2122, ssa_1
>												/* succs: block_362 block_372 */
>												if ssa_2123 {
>													block block_362:
>													/* preds: block_361 */
>													vec1 32 ssa_2124 = ffma -ssa_33, ssa_2093, ssa_2086
>													vec1 32 ssa_2125 = ffma -ssa_33, ssa_2094, ssa_2087
>													vec1 32 ssa_2126 = fadd ssa_2124, ssa_2100
>													vec1 32 ssa_2127 = fadd ssa_2125, ssa_2101
>													vec1 32 ssa_2128 = fadd ssa_2086, -ssa_2093
>													vec1 32 ssa_2129 = fadd ssa_2087, -ssa_2094
>													vec1 32 ssa_2130 = frcp ssa_2127
>													vec1 32 ssa_2131 = fmul ssa_2127, ssa_2087
>													vec1 32 ssa_2132 = ffma ssa_2129, ssa_2129, -ssa_2131
>													vec1 32 ssa_2133 = fmax ssa_2132, ssa_1
>													vec1 32 ssa_2134 = fsqrt ssa_2133
>													vec1 32 ssa_2135 = fadd ssa_2129, -ssa_2134
>													r145 = fmul ssa_2135, ssa_2130
>													vec1 32 ssa_2137 = fadd ssa_2129, ssa_2134
>													r146 = fmul ssa_2137, ssa_2130
>													vec1 32 ssa_2139 = flt32 abs(ssa_2127), ssa_82
>													/* succs: block_363 block_364 */
>													if ssa_2139 {
>														block block_363:
>														/* preds: block_362 */
>														vec1 32 ssa_2140 = fmul ssa_37, ssa_2087
>														vec1 32 ssa_2141 = frcp ssa_2129
>														r146 = fmul ssa_2140, ssa_2141
>														r145 = imov r146
>														/* succs: block_365 */
>													} else {
>														block block_364:
>														/* preds: block_362 */
>														/* succs: block_365 */
>													}
>													block block_365:
>													/* preds: block_363 block_364 */
>													vec1 32 ssa_2145 = fmul ssa_2128, ssa_33
>													vec1 32 ssa_2146 = ffma ssa_2126, r145, -ssa_2145
>													vec1 32 ssa_2147 = ffma ssa_2146, r145, ssa_2086
>													vec1 32 ssa_2148 = ffma ssa_2126, r146, -ssa_2145
>													vec1 32 ssa_2149 = ffma ssa_2148, r146, ssa_2086
>													vec1 32 ssa_2150 = fmul ssa_1947, ssa_2147
>													vec1 32 ssa_2151 = fmul ssa_1947, ssa_2149
>													vec1 32 ssa_2152 = iand ssa_2122, ssa_30
>													vec1 32 ssa_2153 = ine32 ssa_2152, ssa_1
>													/* succs: block_366 block_367 */
>													if ssa_2153 {
>														block block_366:
>														/* preds: block_365 */
>														vec1 32 ssa_2154 = ffma.sat ssa_2150, ssa_1970, ssa_37
>														r141 = fadd r141, ssa_2154
>														r140 = fmin r140, abs(ssa_2150)
>														/* succs: block_368 */
>													} else {
>														block block_367:
>														/* preds: block_365 */
>														/* succs: block_368 */
>													}
>													block block_368:
>													/* preds: block_366 block_367 */
>													vec1 32 ssa_2159 = ult32 ssa_30, ssa_2122
>													/* succs: block_369 block_370 */
>													if ssa_2159 {
>														block block_369:
>														/* preds: block_368 */
>														vec1 32 ssa_2160 = ffma.sat ssa_2151, ssa_1970, ssa_37
>														r141 = fadd r141, -ssa_2160
>														r140 = fmin r140, abs(ssa_2151)
>														/* succs: block_371 */
>													} else {
>														block block_370:
>														/* preds: block_368 */
>														/* succs: block_371 */
>													}
>													block block_371:
>													/* preds: block_369 block_370 */
>													/* succs: block_373 */
>												} else {
>													block block_372:
>													/* preds: block_361 */
>													/* succs: block_373 */
>												}
>												block block_373:
>												/* preds: block_371 block_372 */
>												r139 = iadd r139, ssa_32
>												r142 = iadd r142, ssa_30
>												/* succs: block_346 */
>											}
>											block block_374:
>											/* preds: block_347 block_353 block_359 */
>											r147 = fmov abs(r141)
>											/* succs: block_375 block_376 */
>											if ssa_1945 {
>												block block_375:
>												/* preds: block_374 */
>												vec1 32 ssa_2170 = fmul ssa_37, abs(r132)
>												vec1 32 ssa_2171 = fmul ssa_37, abs(r141)
>												vec1 32 ssa_2172 = ffract ssa_2170
>												vec1 32 ssa_2173 = ffract ssa_2171
>												r138 = fmul ssa_33, ssa_2172
>												r147 = fmul ssa_33, ssa_2173
>												/* succs: block_377 */
>											} else {
>												block block_376:
>												/* preds: block_374 */
>												/* succs: block_377 */
>											}
>											block block_377:
>											/* preds: block_375 block_376 */
>											vec1 32 ssa_2178 = fmin.sat abs(r131), ssa_37
>											vec1 32 ssa_2179 = fmin.sat abs(r140), ssa_37
>											vec1 32 ssa_2180 = ffma -ssa_33, ssa_2178, ssa_35
>											vec1 32 ssa_2181 = ffma -ssa_33, ssa_2179, ssa_35
>											vec1 32 ssa_2182 = fadd ssa_2180, ssa_2181
>											vec1 32 ssa_2183 = flt32 ssa_85, ssa_2182
>											/* succs: block_378 block_379 */
>											if ssa_2183 {
>												block block_378:
>												/* preds: block_377 */
>												vec1 32 ssa_2184 = fmul r147, ssa_2181
>												vec1 32 ssa_2185 = ffma r138, ssa_2180, ssa_2184
>												vec1 32 ssa_2186 = frcp ssa_2182
>												r13 = fmul ssa_2185, ssa_2186
>												/* succs: block_380 */
>											} else {
>												block block_379:
>												/* preds: block_377 */
>												vec1 32 ssa_2188 = fadd r138, r147
>												r13 = fmul ssa_37, ssa_2188
>												/* succs: block_380 */
>											}
>											block block_380:
>											/* preds: block_378 block_379 */
>											vec1 32 ssa_2191 = iand ssa_1942.x, ssa_33
>											vec1 32 ssa_2192 = ine32 ssa_2191, ssa_1
>											/* succs: block_381 block_382 */
>											if ssa_2192 {
>												block block_381:
>												/* preds: block_380 */
>												r13 = fadd ssa_35, -r13
>												/* succs: block_383 */
>											} else {
>												block block_382:
>												/* preds: block_380 */
>												/* succs: block_383 */
>											}
>											block block_383:
>											/* preds: block_381 block_382 */
>											r10 = imov r13
>											r11 = imov r10
>											r12 = imov r11
>											/* succs: block_385 */
>										} else {
>											block block_384:
>											/* preds: block_315 */
>											/* succs: block_385 */
>										}
>										block block_385:
>										/* preds: block_383 block_384 */
>										/* succs: block_386 */
>									}
>									block block_386:
>									/* preds: block_314 block_385 */
>									/* succs: block_387 */
>								}
>								block block_387:
>								/* preds: block_194 block_386 */
>								/* succs: block_388 */
>							}
>							block block_388:
>							/* preds: block_168 block_387 */
>							/* succs: block_389 */
>						}
>						block block_389:
>						/* preds: block_142 block_388 */
>						/* succs: block_391 */
>					} else {
>						block block_390:
>						/* preds: block_140 */
>						r10 = imov ssa_35
>						r11 = imov r10
>						r12 = imov r11
>						r13 = imov r12
>						/* succs: block_391 */
>					}
>					block block_391:
>					/* preds: block_389 block_390 */
>					/* succs: block_393 */
>				} else {
>					block block_392:
>					/* preds: block_139 */
>					r10 = imov ssa_35
>					r11 = imov r10
>					r12 = imov r11
>					r13 = imov r12
>					/* succs: block_393 */
>				}
>				block block_393:
>				/* preds: block_391 block_392 */
>				/* succs: block_394 */
>			}
>			block block_394:
>			/* preds: block_138 block_393 */
>			/* succs: block_395 */
>		}
>		block block_395:
>		/* preds: block_136 block_394 */
>		r5 = fmul r17, r13
>		r4 = fmul r16, r12
>		r3 = fmul r15, r11
>		r2 = fmul r14, r10
>		/* succs: block_397 */
>	} else {
>		block block_396:
>		/* preds: block_0 */
>		r2 = imov ssa_1
>		r3 = imov r2
>		r4 = imov r3
>		r5 = imov r4
>		/* succs: block_397 */
>	}
>	block block_397:
>	/* preds: block_395 block_396 */
>	vec1 32 ssa_2239 = intrinsic load_input (ssa_1) (32, 3) /* base=32 */ /* component=3 */	/* fastuidraw_uint_varying1 */
>	vec1 32 ssa_2240 = ine32 ssa_2239, ssa_30
>	/* succs: block_398 block_441 */
>	if ssa_2240 {
>		block block_398:
>		/* preds: block_397 */
>		vec1 32 ssa_2241 = ine32 ssa_2239, ssa_31
>		/* succs: block_399 block_439 */
>		if ssa_2241 {
>			block block_399:
>			/* preds: block_398 */
>			vec1 32 ssa_2242 = ine32 ssa_2239, ssa_32
>			/* succs: block_400 block_437 */
>			if ssa_2242 {
>				block block_400:
>				/* preds: block_399 */
>				vec1 32 ssa_2243 = ieq32 ssa_2239, ssa_80
>				/* succs: block_401 block_402 */
>				if ssa_2243 {
>					block block_401:
>					/* preds: block_400 */
>					r9 = fadd ssa_35, -r2
>					r6 = imov r9
>					r7 = imov r6
>					r8 = imov r7
>					/* succs: block_436 */
>				} else {
>					block block_402:
>					/* preds: block_400 */
>					vec1 32 ssa_2245 = ine32 ssa_2239, ssa_86
>					/* succs: block_403 block_434 */
>					if ssa_2245 {
>						block block_403:
>						/* preds: block_402 */
>						vec1 32 ssa_2246 = ine32 ssa_2239, ssa_67
>						/* succs: block_404 block_432 */
>						if ssa_2246 {
>							block block_404:
>							/* preds: block_403 */
>							vec1 32 ssa_2247 = ine32 ssa_2239, ssa_87
>							/* succs: block_405 block_430 */
>							if ssa_2247 {
>								block block_405:
>								/* preds: block_404 */
>								vec1 32 ssa_2248 = ine32 ssa_2239, ssa_70
>								/* succs: block_406 block_428 */
>								if ssa_2248 {
>									block block_406:
>									/* preds: block_405 */
>									vec1 32 ssa_2249 = ieq32 ssa_2239, ssa_88
>									/* succs: block_407 block_408 */
>									if ssa_2249 {
>										block block_407:
>										/* preds: block_406 */
>										r9 = fadd ssa_35, -r2
>										r2 = imov ssa_1
>										r3 = imov r2
>										r4 = imov r3
>										r5 = imov r4
>										r6 = imov r9
>										r7 = imov r6
>										r8 = imov r7
>										/* succs: block_427 */
>									} else {
>										block block_408:
>										/* preds: block_406 */
>										vec1 32 ssa_2251 = ieq32 ssa_2239, ssa_52
>										/* succs: block_409 block_410 */
>										if ssa_2251 {
>											block block_409:
>											/* preds: block_408 */
>											r9 = fadd ssa_35, -r2
>											r6 = imov r9
>											r7 = imov r6
>											r8 = imov r7
>											/* succs: block_426 */
>										} else {
>											block block_410:
>											/* preds: block_408 */
>											vec1 32 ssa_2253 = ine32 ssa_2239, ssa_89
>											/* succs: block_411 block_424 */
>											if ssa_2253 {
>												block block_411:
>												/* preds: block_410 */
>												vec1 32 ssa_2254 = ieq32 ssa_2239, ssa_90
>												/* succs: block_412 block_413 */
>												if ssa_2254 {
>													block block_412:
>													/* preds: block_411 */
>													r9 = fadd ssa_35, -r2
>													r6 = imov r9
>													r7 = imov r6
>													r8 = imov r7
>													/* succs: block_423 */
>												} else {
>													block block_413:
>													/* preds: block_411 */
>													vec1 32 ssa_2256 = ine32 ssa_2239, ssa_91
>													/* succs: block_414 block_421 */
>													if ssa_2256 {
>														block block_414:
>														/* preds: block_413 */
>														vec1 32 ssa_2257 = ine32 ssa_2239, ssa_29
>														/* succs: block_415 block_419 */
>														if ssa_2257 {
>															block block_415:
>															/* preds: block_414 */
>															vec1 32 ssa_2258 = ieq32 ssa_2239, ssa_76
>															/* succs: block_416 block_417 */
>															if ssa_2258 {
>																block block_416:
>																/* preds: block_415 */
>																r9 = fadd ssa_35, -r5
>																r8 = fadd ssa_35, -r4
>																r7 = fadd ssa_35, -r3
>																r6 = fadd ssa_35, -r2
>																/* succs: block_418 */
>															} else {
>																block block_417:
>																/* preds: block_415 */
>																/* succs: block_418 */
>															}
>															block block_418:
>															/* preds: block_416 block_417 */
>															/* succs: block_420 */
>														} else {
>															block block_419:
>															/* preds: block_414 */
>															r6 = imov r2
>															r2 = imov ssa_1
>															r7 = imov r3
>															r3 = imov r2
>															r8 = imov r4
>															r4 = imov r3
>															r9 = imov r5
>															r5 = imov r4
>															/* succs: block_420 */
>														}
>														block block_420:
>														/* preds: block_418 block_419 */
>														/* succs: block_422 */
>													} else {
>														block block_421:
>														/* preds: block_413 */
>														r6 = imov ssa_35
>														r7 = imov r6
>														r8 = imov r7
>														r9 = imov r8
>														/* succs: block_422 */
>													}
>													block block_422:
>													/* preds: block_420 block_421 */
>													/* succs: block_423 */
>												}
>												block block_423:
>												/* preds: block_412 block_422 */
>												/* succs: block_425 */
>											} else {
>												block block_424:
>												/* preds: block_410 */
>												r6 = imov r2
>												r7 = imov r6
>												r8 = imov r7
>												r9 = imov r8
>												/* succs: block_425 */
>											}
>											block block_425:
>											/* preds: block_423 block_424 */
>											/* succs: block_426 */
>										}
>										block block_426:
>										/* preds: block_409 block_425 */
>										/* succs: block_427 */
>									}
>									block block_427:
>									/* preds: block_407 block_426 */
>									/* succs: block_429 */
>								} else {
>									block block_428:
>									/* preds: block_405 */
>									r6 = imov ssa_1
>									r7 = imov r6
>									r8 = imov r7
>									r9 = imov r8
>									/* succs: block_429 */
>								}
>								block block_429:
>								/* preds: block_427 block_428 */
>								/* succs: block_431 */
>							} else {
>								block block_430:
>								/* preds: block_404 */
>								r3 = imov ssa_1
>								r4 = imov r3
>								r5 = imov r4
>								r6 = imov r2
>								r2 = imov r5
>								r7 = imov r6
>								r8 = imov r7
>								r9 = imov r8
>								/* succs: block_431 */
>							}
>							block block_431:
>							/* preds: block_429 block_430 */
>							/* succs: block_433 */
>						} else {
>							block block_432:
>							/* preds: block_403 */
>							r6 = imov ssa_1
>							r7 = imov r6
>							r8 = imov r7
>							r9 = imov r8
>							/* succs: block_433 */
>						}
>						block block_433:
>						/* preds: block_431 block_432 */
>						/* succs: block_435 */
>					} else {
>						block block_434:
>						/* preds: block_402 */
>						r6 = imov ssa_35
>						r7 = imov r6
>						r8 = imov r7
>						r9 = imov r8
>						/* succs: block_435 */
>					}
>					block block_435:
>					/* preds: block_433 block_434 */
>					/* succs: block_436 */
>				}
>				block block_436:
>				/* preds: block_401 block_435 */
>				/* succs: block_438 */
>			} else {
>				block block_437:
>				/* preds: block_399 */
>				r2 = imov ssa_1
>				r3 = imov r2
>				r4 = imov r3
>				r5 = imov r4
>				r6 = imov ssa_35
>				r7 = imov r6
>				r8 = imov r7
>				r9 = imov r8
>				/* succs: block_438 */
>			}
>			block block_438:
>			/* preds: block_436 block_437 */
>			/* succs: block_440 */
>		} else {
>			block block_439:
>			/* preds: block_398 */
>			r6 = imov ssa_1
>			r7 = imov r6
>			r8 = imov r7
>			r9 = imov r8
>			/* succs: block_440 */
>		}
>		block block_440:
>		/* preds: block_438 block_439 */
>		/* succs: block_442 */
>	} else {
>		block block_441:
>		/* preds: block_397 */
>		r2 = imov ssa_1
>		r3 = imov r2
>		r4 = imov r3
>		r5 = imov r4
>		r6 = imov r5
>		r7 = imov r6
>		r8 = imov r7
>		r9 = imov r8
>		/* succs: block_442 */
>	}
>	block block_442:
>	/* preds: block_440 block_441 */
>	vec4 32 ssa_2383 = vec4 r5, r4, r3, r2
>	vec4 32 ssa_2384 = vec4 r9, r8, r7, r6
>	intrinsic store_output (ssa_2383, ssa_1) (8, 15, 0) /* base=8 */ /* wrmask=xyzw */ /* component=0 */	/* fastuidraw_final_color0 */
>	intrinsic store_output (ssa_2384, ssa_1) (9, 15, 0) /* base=9 */ /* wrmask=xyzw */ /* component=0 */	/* fastuidraw_final_color1 */
>	/* succs: block_443 */
>	block block_443:
>}
>
>FS compile failed: Failure to register allocate.  Reduce number of live scalar values to avoid this.
>Native code for unnamed fragment shader GLSL1
>SIMD8 shader: 2388 instructions. 11 loops. 120307 cycles. 0:0 spills:fills. Promoted 14 constants. Compacted 38208 to 27392 bytes (28%)
>   START B0 (64 cycles)
>add(16)         g4<1>UW         g1.4<1,4,0>UW   0x11001010V     { align1 WE_all 1H };
>mov(8)          g64<1>UD        0x00000000UD                    { align1 1Q compacted };
>pln(8)          g18<1>F         g16.4<0,1,0>F   g2<8,8,1>F      { align1 1Q compacted };
>pln(8)          g31<1>F         g17<0,1,0>F     g2<8,8,1>F      { align1 1Q compacted };
>pln(8)          g103<1>F        g13<0,1,0>F     g2<8,8,1>F      { align1 1Q compacted };
>pln(8)          g49<1>F         g13.4<0,1,0>F   g2<8,8,1>F      { align1 1Q compacted };
>pln(8)          g53<1>F         g14<0,1,0>F     g2<8,8,1>F      { align1 1Q compacted };
>pln(8)          g71<1>F         g14.4<0,1,0>F   g2<8,8,1>F      { align1 1Q compacted };
>mov(8)          g36<1>UD        0x00000001UD                    { align1 1Q compacted };
>mov(8)          g54<1>UD        0x00000002UD                    { align1 1Q compacted };
>mov(8)          g60<1>D         1065353216D                     { align1 1Q };
>mov(8)          g72<1>D         -1082130432D                    { align1 1Q };
>mov(8)          g74<1>D         11892D                          { align1 1Q };
>mov(8)          g98<1>F         g12.7<0,1,0>F                   { align1 1Q };
>mov(8)          g62<1>UD        g12.14<0,1,0>UW                 { align1 1Q };
>cmp.nz.f0.0(8)  null<1>D        g11.3<0,1,0>D   -1D             { align1 1Q compacted };
>mov(8)          g110<1>F        g4<8,4,1>UW                     { align1 1Q };
>mov(8)          g109<1>F        g4.4<8,4,1>UW                   { align1 1Q };
>mov(8)          g63<1>UD        g98.1<16,8,2>UW                 { align1 1Q };
>add(8)          g97<1>D         g62<8,8,1>D     -32768D         { align1 1Q };
>add(8)          g58<1>D         g63<8,8,1>D     -32768D         { align1 1Q };
>(+f0.0) if(8)   JIP: 25320      UIP: 25352                      { align1 1Q };
>   END B0 ->B1 ->B349
>   START B1 <-B0 (22 cycles)
>and.nz.f0.0(8)  null<1>UD       g11.7<0,1,0>UD  0x80000000UD    { align1 1Q };
>mov(1)          g59<1>F         0x3f000000F      /* 0.5F */     { align1 WE_all 1N };
>mov(1)          g59.1<1>F       0x40000000F      /* 2F */       { align1 WE_all 1N };
>(+f0.0) if(8)   JIP: 11640      UIP: 11640                      { align1 1Q };
>   END B1 ->B2 ->B122
>   START B2 <-B1 (34 cycles)
>mov(8)          g39<1>D         g28.7<0,1,0>D                   { align1 1Q };
>mov(8)          g40<1>D         g29.3<0,1,0>D                   { align1 1Q compacted };
>mov(8)          g41<1>D         g29.7<0,1,0>D                   { align1 1Q };
>mov(8)          g86<1>D         g30.3<0,1,0>D                   { align1 1Q compacted };
>add(8)          g68<1>F         g18.1<4,4,0>F   -g18<4,4,0>F    { align1 1Q compacted };
>add(8)          g69<1>F         g31.1<4,4,0>F   -g31<4,4,0>F    { align1 1Q compacted };
>mul(8)          g70<1>F         g18<8,8,1>F     g6<0,1,0>F      { align1 1Q compacted };
>mul(8)          g55<1>F         g31<8,8,1>F     g6<0,1,0>F      { align1 1Q compacted };
>and.nz.f0.0(8)  null<1>UD       g11.7<0,1,0>UD  0x00002000UD    { align1 1Q };
>add(8)          g52<1>F         -g70<4,4,0>F    g70.2<4,4,0>F   { align1 1Q compacted };
>add(8)          g73<1>F         -g55<4,4,0>F    g55.2<4,4,0>F   { align1 1Q compacted };
>(+f0.0) if(8)   JIP: 728        UIP: 728                        { align1 1Q };
>   END B2 ->B3 ->B22
>   START B3 <-B2 (50 cycles)
>shl(8)          g56<1>D         g11.7<0,1,0>D   0x00000010UD    { align1 1Q };
>shl(8)          g76<1>D         g11.7<0,1,0>D   0x0000000eUD    { align1 1Q };
>add(8)          g35<1>F         g18<8,8,1>F     -g19.3<0,1,0>F  { align1 1Q compacted };
>add(8)          g79<1>F         g31<8,8,1>F     -g19.7<0,1,0>F  { align1 1Q compacted };
>shr(8)          g75<1>UD        g56<8,8,1>UD    0x0000001eUD    { align1 1Q compacted };
>shr(8)          g77<1>UD        g76<8,8,1>UD    0x0000001eUD    { align1 1Q compacted };
>cmp.z.f0.0(8)   null<1>D        g75<8,8,1>D     1D              { align1 1Q compacted };
>(+f0.0) if(8)   JIP: 48         UIP: 288                        { align1 1Q };
>   END B3 ->B4 ->B5
>   START B4 <-B3 (20 cycles)
>sel.ge(8)       g80<1>F         (abs)g35<8,8,1>F 0x0F  /* 0F */ { align1 1Q compacted };
>sel.l(8)        g42<1>F         g80<8,8,1>F     g20.3<0,1,0>F   { align1 1Q compacted };
>else(8)         JIP: 256        UIP: 256                        { align1 1Q };
>   END B4 ->B12
>   START B5 <-B3 (18 cycles)
>cmp.z.f0.0(8)   null<1>D        g75<8,8,1>D     2D              { align1 1Q compacted };
>(+f0.0) if(8)   JIP: 72         UIP: 216                        { align1 1Q };
>   END B5 ->B6 ->B7
>   START B6 <-B5 (54 cycles)
>math inv(8)     g81<1>F         g20.3<0,1,0>F   null<8,8,1>F    { align1 1Q compacted };
>mul(8)          g82<1>F         g35<8,8,1>F     g81<8,8,1>F     { align1 1Q compacted };
>rndd(8)         g83<1>F         g82<8,8,1>F                     { align1 1Q compacted };
>mad(8)          g42<1>F         g35<4,4,1>F     g83<4,4,1>F     -g20.3<0,1,0>F { align16 1Q };
>else(8)         JIP: 160        UIP: 160                        { align1 1Q };
>   END B6 ->B11
>   START B7 <-B5 (18 cycles)
>cmp.z.f0.0(8)   null<1>D        g75<8,8,1>D     3D              { align1 1Q compacted };
>(+f0.0) if(8)   JIP: 104        UIP: 120                        { align1 1Q };
>   END B7 ->B8 ->B9
>   START B8 <-B7 (106 cycles)
>mul(8)          g84<1>F         g20.3<0,1,0>F   0x40000000F  /* 2F */ { align1 1Q };
>math inv(8)     g85<1>F         g84<8,8,1>F     null<8,8,1>F    { align1 1Q compacted };
>mul(8)          g48<1>F         g35<8,8,1>F     g85<8,8,1>F     { align1 1Q compacted };
>rndd(8)         g87<1>F         g48<8,8,1>F                     { align1 1Q compacted };
>mad(8)          g88<1>F         g35<4,4,1>F     g87<4,4,1>F     -g84<4,4,1>F { align16 1Q compacted };
>add(8)          g89<1>F         g88<8,8,1>F     -g20.3<0,1,0>F  { align1 1Q compacted };
>add(8)          g42<1>F         g20.3<0,1,0>F   -(abs)g89<8,8,1>F { align1 1Q };
>else(8)         JIP: 32         UIP: 32                         { align1 1Q };
>   END B8 ->B10
>   START B9 <-B7 (18 cycles)
>sel.ge(8)       g90<1>F         g35<8,8,1>F     0x0F  /* 0F */  { align1 1Q compacted };
>sel.l(8)        g42<1>F         g90<8,8,1>F     g20.3<0,1,0>F   { align1 1Q compacted };
>   END B9 ->B10
>   START B10 <-B9 <-B8 (2 cycles)
>endif(8)        JIP: 16                                         { align1 1Q };
>   END B10 ->B11
>   START B11 <-B10 <-B6 (2 cycles)
>endif(8)        JIP: 16                                         { align1 1Q };
>   END B11 ->B12
>   START B12 <-B11 <-B4 (20 cycles)
>endif(8)        JIP: 352                                        { align1 1Q };
>cmp.z.f0.0(8)   null<1>D        g77<8,8,1>D     1D              { align1 1Q compacted };
>(+f0.0) if(8)   JIP: 48         UIP: 296                        { align1 1Q };
>   END B12 ->B13 ->B14
>   START B13 <-B12 (20 cycles)
>sel.ge(8)       g91<1>F         (abs)g79<8,8,1>F 0x0F  /* 0F */ { align1 1Q compacted };
>sel.l(8)        g43<1>F         g91<8,8,1>F     g20.7<0,1,0>F   { align1 1Q compacted };
>else(8)         JIP: 264        UIP: 264                        { align1 1Q };
>   END B13 ->B21
>   START B14 <-B12 (18 cycles)
>cmp.z.f0.0(8)   null<1>D        g77<8,8,1>D     2D              { align1 1Q compacted };
>(+f0.0) if(8)   JIP: 80         UIP: 224                        { align1 1Q };
>   END B14 ->B15 ->B16
>   START B15 <-B14 (54 cycles)
>math inv(8)     g92<1>F         g20.7<0,1,0>F   null<8,8,1>F    { align1 1Q };
>mul(8)          g93<1>F         g79<8,8,1>F     g92<8,8,1>F     { align1 1Q compacted };
>rndd(8)         g94<1>F         g93<8,8,1>F                     { align1 1Q compacted };
>mad(8)          g43<1>F         g79<4,4,1>F     g94<4,4,1>F     -g20.7<0,1,0>F { align16 1Q };
>else(8)         JIP: 160        UIP: 160                        { align1 1Q };
>   END B15 ->B20
>   START B16 <-B14 (18 cycles)
>cmp.z.f0.0(8)   null<1>D        g77<8,8,1>D     3D              { align1 1Q compacted };
>(+f0.0) if(8)   JIP: 104        UIP: 120                        { align1 1Q };
>   END B16 ->B17 ->B18
>   START B17 <-B16 (106 cycles)
>mul(8)          g95<1>F         g20.7<0,1,0>F   0x40000000F  /* 2F */ { align1 1Q };
>math inv(8)     g96<1>F         g95<8,8,1>F     null<8,8,1>F    { align1 1Q compacted };
>mul(8)          g57<1>F         g79<8,8,1>F     g96<8,8,1>F     { align1 1Q compacted };
>rndd(8)         g61<1>F         g57<8,8,1>F                     { align1 1Q compacted };
>mad(8)          g99<1>F         g79<4,4,1>F     g61<4,4,1>F     -g95<4,4,1>F { align16 1Q compacted };
>add(8)          g100<1>F        g99<8,8,1>F     -g20.7<0,1,0>F  { align1 1Q compacted };
>add(8)          g43<1>F         g20.7<0,1,0>F   -(abs)g100<8,8,1>F { align1 1Q };
>else(8)         JIP: 32         UIP: 32                         { align1 1Q };
>   END B17 ->B19
>   START B18 <-B16 (18 cycles)
>sel.ge(8)       g101<1>F        g79<8,8,1>F     0x0F  /* 0F */  { align1 1Q compacted };
>sel.l(8)        g43<1>F         g101<8,8,1>F    g20.7<0,1,0>F   { align1 1Q compacted };
>   END B18 ->B19
>   START B19 <-B18 <-B17 (2 cycles)
>endif(8)        JIP: 16                                         { align1 1Q };
>   END B19 ->B20
>   START B20 <-B19 <-B15 (2 cycles)
>endif(8)        JIP: 16                                         { align1 1Q };
>   END B20 ->B21
>   START B21 <-B20 <-B13 (6 cycles)
>endif(8)        JIP: 32                                         { align1 1Q };
>add(8)          g18<1>F         g42<8,8,1>F     g19.3<0,1,0>F   { align1 1Q compacted };
>add(8)          g31<1>F         g43<8,8,1>F     g19.7<0,1,0>F   { align1 1Q compacted };
>   END B21 ->B22
>   START B22 <-B2 <-B21 (36 cycles)
>endif(8)        JIP: 10784                                      { align1 1Q };
>shl(8)          g102<1>D        g11.7<0,1,0>D   0x00000015UD    { align1 1Q };
>shr.nz.f0.0(8)  g5<1>UD         g102<8,8,1>UD   0x0000001eUD    { align1 1Q compacted };
>(+f0.0) if(8)   JIP: 1920       UIP: 1920                       { align1 1Q };
>   END B22 ->B23 ->B50
>   START B23 <-B22 (18 cycles)
>cmp.z.f0.0(8)   null<1>D        g5<8,8,1>D      2D              { align1 1Q compacted };
>(+f0.0) if(8)   JIP: 544        UIP: 1464                       { align1 1Q };
>   END B23 ->B24 ->B31
>   START B24 <-B23 (134 cycles)
>add(8)          g50<1>F         g18<8,8,1>F     -g21.3<0,1,0>F  { align1 1Q compacted };
>add(8)          g105<1>F        g31<8,8,1>F     -g21.7<0,1,0>F  { align1 1Q compacted };
>add(8)          g106<1>F        g22.3<0,1,0>F   -g21.3<0,1,0>F  { align1 1Q };
>add(8)          g107<1>F        g22.7<0,1,0>F   -g21.7<0,1,0>F  { align1 1Q };
>add(8)          g108<1>F        g23.7<0,1,0>F   -g23.3<0,1,0>F  { align1 1Q };
>mul(8)          g116<1>F        g105<8,8,1>F    g105<8,8,1>F    { align1 1Q compacted };
>mul(8)          g47<1>F         g105<8,8,1>F    g107<8,8,1>F    { align1 1Q compacted };
>mul(8)          g113<1>F        g107<8,8,1>F    g107<8,8,1>F    { align1 1Q compacted };
>mad(8)          g117<1>F        g116<4,4,1>F    g50<4,4,1>F     g50<4,4,1>F { align16 1Q compacted };
>mad(8)          g46<1>F         g47<4,4,1>F     g106<4,4,1>F    g50<4,4,1>F { align16 1Q compacted };
>mad(8)          g114<1>F        g113<4,4,1>F    g106<4,4,1>F    g106<4,4,1>F { align16 1Q compacted };
>mad(8)          g118<1>F        g117<4,4,1>F    g23.3<0,1,0>F   -g23.3<0,1,0>F { align16 1Q };
>mad(8)          g111<1>F        g46<4,4,1>F     g108<4,4,1>F    -g23.3<0,1,0>F { align16 1Q };
>mad(8)          g115<1>F        g114<4,4,1>F    g108<4,4,1>F    -g108<4,4,1>F { align16 1Q compacted };
>mul(8)          g112<1>F        g111<8,8,1>F    0x40000000F  /* 2F */ { align1 1Q };
>mul(8)          g119<1>F        g115<8,8,1>F    0x40800000F  /* 4F */ { align1 1Q };
>mul(8)          g120<1>F        g119<8,8,1>F    g118<8,8,1>F    { align1 1Q compacted };
>mad.ge.f0.0(8)  g121<1>F        -g120<4,4,1>F   g112<4,4,1>F    g112<4,4,1>F { align16 1Q };
>(+f0.0) if(8)   JIP: 272        UIP: 288                        { align1 1Q };
>   END B24 ->B25 ->B29
>   START B25 <-B24 (112 cycles)
>math sqrt(8)    g122<1>F        (abs)g121<8,8,1>F null<8,8,1>F  { align1 1Q compacted };
>math inv(8)     g123<1>F        g115<8,8,1>F    null<8,8,1>F    { align1 1Q compacted };
>add(8)          g125<1>F        -g112<8,8,1>F   g122<8,8,1>F    { align1 1Q compacted };
>add(8)          g127<1>F        -g112<8,8,1>F   -g122<8,8,1>F   { align1 1Q compacted };
>mul(8)          g124<1>F        g123<8,8,1>F    0x3f000000F  /* 0.5F */ { align1 1Q };
>mul(8)          g126<1>F        g125<8,8,1>F    g124<8,8,1>F    { align1 1Q compacted };
>mul(8)          g2<1>F          g127<8,8,1>F    g124<8,8,1>F    { align1 1Q compacted };
>cmp.le.f0.0(8)  g3<1>F          g126<8,8,1>F    0x3f800000F  /* 1F */ { align1 1Q };
>cmp.ge.f0.0(8)  g4<1>F          g126<8,8,1>F    0x0F  /* 0F */  { align1 1Q compacted };
>cmp.le.f0.0(8)  g14<1>F         g2<8,8,1>F      0x3f800000F  /* 1F */ { align1 1Q };
>cmp.ge.f0.0(8)  g15<1>F         g2<8,8,1>F      0x0F  /* 0F */  { align1 1Q compacted };
>and(8)          g12<1>UD        g4<8,8,1>UD     g3<8,8,1>UD     { align1 1Q compacted };
>and(8)          g16<1>UD        g15<8,8,1>UD    g14<8,8,1>UD    { align1 1Q compacted };
>mov(8)          g13<1>F         -g12<8,8,1>D                    { align1 1Q compacted };
>mov(8)          g17<1>F         -g16<8,8,1>D                    { align1 1Q compacted };
>cmp.z.f0.0(8)   null<1>D        g12<8,8,1>D     g16<8,8,1>D     { align1 1Q compacted };
>(+f0.0) if(8)   JIP: 40         UIP: 56                         { align1 1Q };
>   END B25 ->B26 ->B27
>   START B26 <-B25 (4 cycles)
>sel.ge(8)       g44<1>F         g126<8,8,1>F    g2<8,8,1>F      { align1 1Q compacted };
>else(8)         JIP: 32         UIP: 32                         { align1 1Q };
>   END B26 ->B28
>   START B27 <-B25 (18 cycles)
>mul(8)          g19<1>F         g17<8,8,1>F     g2<8,8,1>F      { align1 1Q compacted };
>mad(8)          g44<1>F         g19<4,4,1>F     g126<4,4,1>F    g13<4,4,1>F { align16 1Q compacted };
>   END B27 ->B28
>   START B28 <-B27 <-B26 (6 cycles)
>endif(8)        JIP: 32                                         { align1 1Q };
>mov(8)          g38<1>D         1065353216D                     { align1 1Q };
>else(8)         JIP: 32         UIP: 32                         { align1 1Q };
>   END B28 ->B30
>   START B29 <-B24 (4 cycles)
>mov(8)          g38<1>UD        0x00000000UD                    { align1 1Q compacted };
>mov(8)          g44<1>UD        0x00000000UD                    { align1 1Q compacted };
>   END B29 ->B30
>   START B30 <-B29 <-B28 (4 cycles)
>endif(8)        JIP: 16                                         { align1 1Q };
>else(8)         JIP: 936        UIP: 936                        { align1 1Q };
>   END B30 ->B40
>   START B31 <-B23 (18 cycles)
>cmp.z.f0.0(8)   null<1>D        g5<8,8,1>D      1D              { align1 1Q compacted };
>(+f0.0) if(8)   JIP: 144        UIP: 896                        { align1 1Q };
>   END B31 ->B32 ->B33
>   START B32 <-B31 (76 cycles)
>add(8)          g20<1>F         g22.3<0,1,0>F   -g21.3<0,1,0>F  { align1 1Q };
>add(8)          g23<1>F         g22.7<0,1,0>F   -g21.7<0,1,0>F  { align1 1Q };
>add(8)          g32<1>F         g18<8,8,1>F     -g21.3<0,1,0>F  { align1 1Q compacted };
>add(8)          g33<1>F         g31<8,8,1>F     -g21.7<0,1,0>F  { align1 1Q compacted };
>mov(8)          g38<1>D         1065353216D                     { align1 1Q };
>mul(8)          g42<1>F         g23<8,8,1>F     g23<8,8,1>F     { align1 1Q compacted };
>mul(8)          g34<1>F         g23<8,8,1>F     g33<8,8,1>F     { align1 1Q compacted };
>mad(8)          g43<1>F         g42<4,4,1>F     g20<4,4,1>F     g20<4,4,1>F { align16 1Q compacted };
>mad(8)          g37<1>F         g34<4,4,1>F     g32<4,4,1>F     g20<4,4,1>F { align16 1Q compacted };
>math inv(8)     g45<1>F         g43<8,8,1>F     null<8,8,1>F    { align1 1Q compacted };
>mul(8)          g44<1>F         g37<8,8,1>F     g45<8,8,1>F     { align1 1Q compacted };
>else(8)         JIP: 768        UIP: 768                        { align1 1Q };
>   END B32 ->B39
>   START B33 <-B31 (18 cycles)
>cmp.z.f0.0(8)   null<1>D        g5<8,8,1>D      3D              { align1 1Q compacted };
>(+f0.0) if(8)   JIP: 712        UIP: 728                        { align1 1Q };
>   END B33 ->B34 ->B37
>   START B34 <-B33 (460 cycles)
>add(8)          g78<1>F         g18<8,8,1>F     -g21.3<0,1,0>F  { align1 1Q compacted };
>add(8)          g104<1>F        g31<8,8,1>F     -g21.7<0,1,0>F  { align1 1Q compacted };
>mov(1)          g59.2<1>F       0x3df0555dF      /* 0.11735F */ { align1 WE_all 1N };
>cmp.le.f0.0(8)  g98<1>F         g78<8,8,1>F     0x0F  /* 0F */  { align1 1Q compacted };
>csel.le(8)      g62<1>F         (abs)g78<4,4,1>F g104<4,4,1>F   g78<4,4,1>F { align16 1Q };
>csel.le(8)      g63<1>F         g104<4,4,1>F    (abs)g78<4,4,1>F g78<4,4,1>F { align16 1Q };
>mov(8)          g91<1>F         -g98<8,8,1>D                    { align1 1Q compacted };
>cmp.ge.f0.0(8)  null<1>F        (abs)g63<8,8,1>F 0x5d5e0b6bF  /* 1e+18F */ { align1 1Q };
>mul(8)          g92<1>F         g91<8,8,1>F     0x3fc90fdbF  /* 1.5708F */ { align1 1Q };
>(-f0.0) sel(8)  g51<1>UD        g60<8,8,1>UD    0x3e800000UD    { align1 1Q };
>mul(8)          g65<1>F         g63<8,8,1>F     g51<8,8,1>F     { align1 1Q compacted };
>mul(8)          g67<1>F         g62<8,8,1>F     g51<8,8,1>F     { align1 1Q compacted };
>cmp.z.f0.0(8)   null<1>F        (abs)g78<8,8,1>F (abs)g104<8,8,1>F { align1 1Q compacted };
>math inv(8)     g66<1>F         g65<8,8,1>F     null<8,8,1>F    { align1 1Q compacted };
>mul(8)          g70<1>F         g67<8,8,1>F     g66<8,8,1>F     { align1 1Q compacted };
>sel.l(8)        g94<1>F         g104<8,8,1>F    g66<8,8,1>F     { align1 1Q compacted };
>(-f0.0) sel(8)  g55<1>F         (abs)g70<8,8,1>F 0x3f800000F  /* 1F */ { align1 1Q };
>sel.l(8)        g56<1>F         (abs)g55<8,8,1>F 0x3f800000F  /* 1F */ { align1 1Q };
>sel.ge(8)       g75<1>F         (abs)g55<8,8,1>F 0x3f800000F  /* 1F */ { align1 1Q };
>cmp.g.f0.0(8)   g48<1>F         (abs)g55<8,8,1>F 0x3f800000F  /* 1F */ { align1 1Q };
>and(8)          g90<1>UD        g55<8,8,1>UD    0x80000000UD    { align1 1Q };
>cmp.nz.f0.0(8)  null<1>F        g55<8,8,1>F     0x0F  /* 0F */  { align1 1Q compacted };
>math inv(8)     g76<1>F         g75<8,8,1>F     null<8,8,1>F    { align1 1Q compacted };
>mov(8)          g87<1>F         -g48<8,8,1>D                    { align1 1Q compacted };
>(+f0.0) or(8)   g90<1>UD        g90<8,8,1>UD    0x3f800000UD    { align1 1Q };
>mul(8)          g77<1>F         g56<8,8,1>F     g76<8,8,1>F     { align1 1Q compacted };
>mul(8)          g35<1>F         g77<8,8,1>F     g77<8,8,1>F     { align1 1Q compacted };
>mul(8)          g79<1>F         g35<8,8,1>F     0xbc46c6a5F  /* -0.0121323F */ { align1 1Q };
>add(8)          g80<1>F         g79<8,8,1>F     0x3d5be101F  /* 0.0536814F */ { align1 1Q };
>mad(8)          g81<1>F         -g59.2<0,1,0>F  g35<4,4,1>F     g80<4,4,1>F { align16 1Q };
>mov(1)          g59.3<1>F       0x3e468bc1F      /* 0.193892F */ { align1 WE_all 1N };
>mad(8)          g82<1>F         g59.3<0,1,0>F   g35<4,4,1>F     g81<4,4,1>F { align16 1Q };
>mov(1)          g59.4<1>F       0x3eaa5476F      /* 0.332676F */ { align1 WE_all 1N };
>mad(8)          g83<1>F         -g59.4<0,1,0>F  g35<4,4,1>F     g82<4,4,1>F { align16 1Q };
>mov(1)          g59.5<1>F       0x3f7ffea5F      /* 0.999979F */ { align1 WE_all 1N };
>mad(8)          g84<1>F         g59.5<0,1,0>F   g35<4,4,1>F     g83<4,4,1>F { align16 1Q };
>mov(1)          g59.6<1>F       0x3fc90fdbF      /* 1.5708F */  { align1 WE_all 1N };
>mul(8)          g85<1>F         g84<8,8,1>F     g77<8,8,1>F     { align1 1Q compacted };
>mad(8)          g88<1>F         g59.6<0,1,0>F   -g59.1<0,1,0>F  g85<4,4,1>F { align16 1Q };
>mad(8)          g89<1>F         g85<4,4,1>F     g88<4,4,1>F     g87<4,4,1>F { align16 1Q compacted };
>mad(8)          g93<1>F         g92<4,4,1>F     g90<4,4,1>F     g89<4,4,1>F { align16 1Q compacted };
>csel.l(8)       g95<1>F         -g93<4,4,1>F    g93<4,4,1>F     g94<4,4,1>F { align16 1Q };
>add(8)          g96<1>F         g95<8,8,1>F     0x40c90fdbF  /* 6.28319F */ { align1 1Q };
>cmp.l.f0.0(8)   null<1>F        g95<8,8,1>F     g22.3<0,1,0>F   { align1 1Q compacted };
>(+f0.0) sel(8)  g57<1>UD        g96<8,8,1>UD    g95<8,8,1>UD    { align1 1Q compacted };
>add(8)          g61<1>F         g57<8,8,1>F     -g22.3<0,1,0>F  { align1 1Q compacted };
>cmp.l.f0.0(8)   null<1>F        g22.7<0,1,0>F   0x0F  /* 0F */  { align1 1Q };
>mul(8)          g45<1>F         g61<8,8,1>F     0x3e22f983F  /* 0.159155F */ { align1 1Q };
>(+f0.0) if(8)   JIP: 32         UIP: 32                         { align1 1Q };
>   END B34 ->B35 ->B36
>   START B35 <-B34 (2 cycles)
>add(8)          g45<1>F         -g45<8,8,1>F    0x3f800000F  /* 1F */ { align1 1Q };
>   END B35 ->B36
>   START B36 <-B34 <-B35 (8 cycles)
>endif(8)        JIP: 48                                         { align1 1Q };
>mul(8)          g44<1>F         g45<8,8,1>F     (abs)g22.7<0,1,0>F { align1 1Q };
>mov(8)          g38<1>D         1065353216D                     { align1 1Q };
>else(8)         JIP: 32         UIP: 32                         { align1 1Q };
>   END B36 ->B38
>   START B37 <-B33 (2 cycles)
>mov(8)          g44<1>D         1065353216D                     { align1 1Q };
>   END B37 ->B38
>   START B38 <-B37 <-B36 (2 cycles)
>endif(8)        JIP: 16                                         { align1 1Q };
>   END B38 ->B39
>   START B39 <-B38 <-B32 (2 cycles)
>endif(8)        JIP: 16                                         { align1 1Q };
>   END B39 ->B40
>   START B40 <-B39 <-B30 (52 cycles)
>endif(8)        JIP: 432                                        { align1 1Q };
>shl(8)          g99<1>D         g11.7<0,1,0>D   0x00000013UD    { align1 1Q };
>shr(8)          g100<1>UD       g99<8,8,1>UD    0x0000001eUD    { align1 1Q compacted };
>cmp.z.f0.0(8)   null<1>D        g100<8,8,1>D    1D              { align1 1Q compacted };
>(+f0.0) if(8)   JIP: 40         UIP: 240                        { align1 1Q };
>   END B40 ->B41 ->B42
>   START B41 <-B40 (4 cycles)
>mov.sat(8)      g78<1>F         (abs)g44<8,8,1>F                { align1 1Q compacted };
>else(8)         JIP: 216        UIP: 216                        { align1 1Q };
>   END B41 ->B49
>   START B42 <-B40 (18 cycles)
>cmp.z.f0.0(8)   null<1>D        g100<8,8,1>D    2D              { align1 1Q compacted };
>(+f0.0) if(8)   JIP: 40         UIP: 176                        { align1 1Q };
>   END B42 ->B43 ->B44
>   START B43 <-B42 (4 cycles)
>frc(8)          g78<1>F         g44<8,8,1>F                     { align1 1Q compacted };
>else(8)         JIP: 152        UIP: 152                        { align1 1Q };
>   END B43 ->B48
>   START B44 <-B42 (18 cycles)
>cmp.z.f0.0(8)   null<1>D        g100<8,8,1>D    3D              { align1 1Q compacted };
>(+f0.0) if(8)   JIP: 104        UIP: 112                        { align1 1Q };
>   END B44 ->B45 ->B46
>   START B45 <-B44 (56 cycles)
>mul(8)          g101<1>F        g44<8,8,1>F     0x3f000000F  /* 0.5F */ { align1 1Q };
>add(8)          g5<1>F          g44<8,8,1>F     0xbf800000F  /* -1F */ { align1 1Q };
>rndd(8)         g102<1>F        g101<8,8,1>F                    { align1 1Q compacted };
>mad(8)          g50<1>F         g5<4,4,1>F      g102<4,4,1>F    -g59.1<0,1,0>F { align16 1Q };
>add(8)          g78<1>F         -(abs)g50<8,8,1>F 0x3f800000F  /* 1F */ { align1 1Q };
>else(8)         JIP: 24         UIP: 24                         { align1 1Q };
>   END B45 ->B47
>   START B46 <-B44 (2 cycles)
>mov.sat(8)      g78<1>F         g44<8,8,1>F                     { align1 1Q compacted };
>   END B46 ->B47
>   START B47 <-B46 <-B45 (2 cycles)
>endif(8)        JIP: 16                                         { align1 1Q };
>   END B47 ->B48
>   START B48 <-B47 <-B43 (2 cycles)
>endif(8)        JIP: 16                                         { align1 1Q };
>   END B48 ->B49
>   START B49 <-B48 <-B41 (248 cycles)
>endif(8)        JIP: 144                                        { align1 1Q };
>mad(8)          g2<1>F          g27.3<0,1,0>F   g28.3<0,1,0>F   g78<4,4,1>F { align16 1Q };
>mov(8)          g3<1>F          g27.7<0,1,0>F                   { align1 1Q };
>send(8)         g12<1>UW        g2<8,8,1>UD     0x04438001
>                            sampler MsgDesc: sample_lz SIMD8 Surface = 1 Sampler = 0 mlen 2 rlen 4 { align1 1Q };
>mul(8)          g106<1>F        g38<8,8,1>F     g12<8,8,1>F     { align1 1Q compacted };
>mul(8)          g107<1>F        g38<8,8,1>F     g13<8,8,1>F     { align1 1Q compacted };
>mul(8)          g108<1>F        g38<8,8,1>F     g14<8,8,1>F     { align1 1Q compacted };
>mul(8)          g47<1>F         g38<8,8,1>F     g15<8,8,1>F     { align1 1Q compacted };
>mul(8)          g39<1>F         g28.7<0,1,0>F   g106<8,8,1>F    { align1 1Q };
>mul(8)          g40<1>F         g29.3<0,1,0>F   g107<8,8,1>F    { align1 1Q compacted };
>mul(8)          g41<1>F         g29.7<0,1,0>F   g108<8,8,1>F    { align1 1Q };
>mul(8)          g86<1>F         g30.3<0,1,0>F   g47<8,8,1>F     { align1 1Q compacted };
>   END B49 ->B50
>   START B50 <-B22 <-B49 (26 cycles)
>endif(8)        JIP: 8824                                       { align1 1Q };
>mul(8)          g60<1>F         g39<8,8,1>F     g86<8,8,1>F     { align1 1Q compacted };
>mul(8)          g104<1>F        g40<8,8,1>F     g86<8,8,1>F     { align1 1Q compacted };
>mul(8)          g78<1>F         g41<8,8,1>F     g86<8,8,1>F     { align1 1Q compacted };
>and.nz.f0.0(8)  null<1>UD       g11.7<0,1,0>UD  0x00000003UD    { align1 1Q };
>(+f0.0) if(8)   JIP: 8752       UIP: 8752                       { align1 1Q };
>   END B50 ->B51 ->B121
>   START B51 <-B50 (46 cycles)
>sel.ge(8)       g46<1>F         g18<8,8,1>F     0x0F  /* 0F */  { align1 1Q compacted };
>add(8)          g111<1>F        g25.3<0,1,0>F   0xbf800000F  /* -1F */ { align1 1Q };
>sel.ge(8)       g112<1>F        g31<8,8,1>F     0x0F  /* 0F */  { align1 1Q compacted };
>add(8)          g113<1>F        g25.7<0,1,0>F   0xbf800000F  /* -1F */ { align1 1Q };
>shl(8)          g114<1>D        g11.7<0,1,0>D   0x0000000aUD    { align1 1Q };
>shl(8)          g115<1>D        g11.7<0,1,0>D   0x0000001eUD    { align1 1Q };
>shl(8)          g116<1>D        g11.7<0,1,0>D   0x00000017UD    { align1 1Q };
>sel.l(8)        g51<1>F         g46<8,8,1>F     g111<8,8,1>F    { align1 1Q compacted };
>sel.l(8)        g65<1>F         g112<8,8,1>F    g113<8,8,1>F    { align1 1Q compacted };
>shr(8)          g66<1>UD        g114<8,8,1>UD   0x0000001eUD    { align1 1Q compacted };
>shr(8)          g67<1>UD        g115<8,8,1>UD   0x0000001eUD    { align1 1Q compacted };
>shr.g.f0.0(8)   g117<1>UD       g116<8,8,1>UD   0x00000019UD    { align1 1Q compacted };
>(+f0.0) if(8)   JIP: 144        UIP: 152                        { align1 1Q };
>   END B51 ->B52 ->B53
>   START B52 <-B51 (124 cycles)
>mul(8)          g118<1>F        g69<8,8,1>F     g69<8,8,1>F     { align1 1Q compacted };
>mul(8)          g120<1>F        g73<8,8,1>F     g73<8,8,1>F     { align1 1Q compacted };
>mov(8)          g127<1>F        g117<8,8,1>UD                   { align1 1Q compacted };
>mad(8)          g119<1>F        g118<4,4,1>F    g68<4,4,1>F     g68<4,4,1>F { align16 1Q compacted };
>mad(8)          g121<1>F        g120<4,4,1>F    g52<4,4,1>F     g52<4,4,1>F { align16 1Q compacted };
>add(8)          g122<1>F        g119<8,8,1>F    g121<8,8,1>F    { align1 1Q compacted };
>mul(8)          g123<1>F        g122<8,8,1>F    0x3f000000F  /* 0.5F */ { align1 1Q };
>sel.ge(8)       g124<1>F        g123<8,8,1>F    0x3f800000F  /* 1F */ { align1 1Q };
>math log(8)     g125<1>F        g124<8,8,1>F    null<8,8,1>F    { align1 1Q compacted };
>mul(8)          g126<1>F        g125<8,8,1>F    0x3f000000F  /* 0.5F */ { align1 1Q };
>sel.l(8)        g2<1>F          g127<8,8,1>F    g126<8,8,1>F    { align1 1Q compacted };
>else(8)         JIP: 24         UIP: 24                         { align1 1Q };
>   END B52 ->B54
>   START B53 <-B51 (2 cycles)
>mov(8)          g2<1>UD         0x00000000UD                    { align1 1Q compacted };
>   END B53 ->B54
>   START B54 <-B53 <-B52 (26 cycles)
>endif(8)        JIP: 8448                                       { align1 1Q };
>cmp.z.f0.0(8)   null<1>D        g66<8,8,1>D     0D              { align1 1Q compacted };
>mov(1)          g59.7<1>F       0x40800000F      /* 4F */       { align1 WE_all 1N };
>mov(1)          g68<1>F         0x40400000F      /* 3F */       { align1 WE_all 1N };
>mov(1)          g68.1<1>F       0x40c00000F      /* 6F */       { align1 WE_all 1N };
>(+f0.0) if(8)   JIP: 6768       UIP: 8256                       { align1 1Q };
>   END B54 ->B55 ->B108
>   START B55 <-B54 (20 cycles)
>sel.l(8)        g19<1>F         g2<8,8,1>F      0x40900000F  /* 4.5F */ { align1 1Q };
>cmp.z.f0.0(8)   null<1>D        g67<8,8,1>D     1D              { align1 1Q compacted };
>(+f0.0) if(8)   JIP: 576        UIP: 6696                       { align1 1Q };
>   END B55 ->B56 ->B61
>   START B56 <-B55 (292 cycles)
>rndd(8)         g20<1>F         -g19<8,8,1>F                    { align1 1Q compacted };
>sel.ge(8)       g21<1>F         g51<8,8,1>F     0x0F  /* 0F */  { align1 1Q compacted };
>sel.ge(8)       g22<1>F         g65<8,8,1>F     0x0F  /* 0F */  { align1 1Q compacted };
>mov(8)          g14<1>F         g8.7<0,1,0>F                    { align1 1Q };
>mov(8)          g70<1>UD        0x00000001UD                    { align1 1Q compacted };
>sel.l(8)        g23<1>F         g21<8,8,1>F     g25.3<0,1,0>F   { align1 1Q compacted };
>sel.l(8)        g27<1>F         g22<8,8,1>F     g25.7<0,1,0>F   { align1 1Q compacted };
>mad(8)          g98<1>F         g24.3<0,1,0>F   g26.3<0,1,0>F   g23<4,4,1>F { align16 1Q };
>mad(8)          g62<1>F         g24.7<0,1,0>F   g26.3<0,1,0>F   g27<4,4,1>F { align16 1Q };
>mov(8)          g12<1>D         g98<8,8,1>F                     { align1 1Q compacted };
>mov(8)          g13<1>D         g62<8,8,1>F                     { align1 1Q compacted };
>send(8)         g12<1>UW        g12<8,8,1>UD    0x0643a304
>                            sampler MsgDesc: ld_lz SIMD8 Surface = 4 Sampler = 3 mlen 3 rlen 4 { align1 1Q };
>shl(8)          g29<1>D         g15<8,8,1>D     0x00000008UD    { align1 1Q };
>mov(8)          g63<1>D         g12<8,8,1>D                     { align1 1Q compacted };
>mov(8)          g69<1>D         g13<8,8,1>D                     { align1 1Q compacted };
>add(8)          g18<1>D         g14<8,8,1>D     g29<8,8,1>D     { align1 1Q compacted };
>   END B56 ->B57
>   START B58 <-B57 <-B59 (18 cycles)
>cmp.ge.f0.0(8)  null<1>UD       g70<8,8,1>UD    g9.3<0,1,0>UD   { align1 1Q compacted };
>   END B57 ->B58 ->B60
>(+f0.0) break(8) JIP: 192       UIP: 192                        { align1 1Q };
>   END B58 ->B57 ->B59
>   START B59 <-B58 (304 cycles)
>rndd(8)         g30<1>F         g98<8,8,1>F                     { align1 1Q compacted };
>rndd(8)         g31<1>F         g62<8,8,1>F                     { align1 1Q compacted };
>mov(8)          g34<1>F         g63<8,8,1>UD                    { align1 1Q compacted };
>mov(8)          g37<1>F         g69<8,8,1>UD                    { align1 1Q compacted };
>add(8)          g70<1>D         g70<8,8,1>D     1D              { align1 1Q compacted };
>add(8)          g32<1>F         g98<8,8,1>F     -g30<8,8,1>F    { align1 1Q compacted };
>add(8)          g33<1>F         g62<8,8,1>F     -g31<8,8,1>F    { align1 1Q compacted };
>add(8)          g38<1>F         g32<8,8,1>F     g34<8,8,1>F     { align1 1Q compacted };
>add(8)          g39<1>F         g33<8,8,1>F     g37<8,8,1>F     { align1 1Q compacted };
>mul(8)          g98<1>F         g38<8,8,1>F     0x40800000F  /* 4F */ { align1 1Q };
>mul(8)          g62<1>F         g39<8,8,1>F     0x40800000F  /* 4F */ { align1 1Q };
>mov(8)          g16<1>D         g98<8,8,1>F                     { align1 1Q compacted };
>mov(8)          g17<1>D         g62<8,8,1>F                     { align1 1Q compacted };
>send(8)         g12<1>UW        g16<8,8,1>UD    0x0643a304
>                            sampler MsgDesc: ld_lz SIMD8 Surface = 4 Sampler = 3 mlen 3 rlen 4 { align1 1Q };
>shl(8)          g40<1>D         g15<8,8,1>D     0x00000008UD    { align1 1Q };
>mov(8)          g63<1>D         g12<8,8,1>D                     { align1 1Q compacted };
>mov(8)          g69<1>D         g13<8,8,1>D                     { align1 1Q compacted };
>add(8)          g18<1>D         g14<8,8,1>D     g40<8,8,1>D     { align1 1Q compacted };
>while(8)        JIP: -200                                       { align1 1Q };
>   END B59 ->B58
>   START B60 <-B57 (278 cycles)
>rndd(8)         g41<1>F         g98<8,8,1>F                     { align1 1Q compacted };
>rndd(8)         g42<1>F         g62<8,8,1>F                     { align1 1Q compacted };
>mov(8)          g45<1>F         g63<8,8,1>UD                    { align1 1Q compacted };
>mov(8)          g15<1>F         g18<8,8,1>UD                    { align1 1Q compacted };
>mov(8)          g12<1>F         -g20<8,8,1>F                    { align1 1Q compacted };
>mov(8)          g63<1>F         g69<8,8,1>UD                    { align1 1Q compacted };
>add(8)          g43<1>F         g98<8,8,1>F     -g41<8,8,1>F    { align1 1Q compacted };
>add(8)          g44<1>F         g62<8,8,1>F     -g42<8,8,1>F    { align1 1Q compacted };
>add(8)          g69<1>F         g43<8,8,1>F     g45<8,8,1>F     { align1 1Q compacted };
>add(8)          g70<1>F         g44<8,8,1>F     g63<8,8,1>F     { align1 1Q compacted };
>mul(8)          g13<1>F         g69<8,8,1>F     0x3b800000F  /* 0.00390625F */ { align1 1Q };
>mul(8)          g14<1>F         g70<8,8,1>F     0x3b800000F  /* 0.00390625F */ { align1 1Q };
>send(8)         g12<1>UW        g12<8,8,1>UD    0x08422203
>                            sampler MsgDesc: sample_l SIMD8 Surface = 3 Sampler = 2 mlen 4 rlen 4 { align1 1Q };
>mov(8)          g98<1>D         g12<8,8,1>D                     { align1 1Q compacted };
>mov(8)          g62<1>D         g13<8,8,1>D                     { align1 1Q compacted };
>mov(8)          g63<1>D         g14<8,8,1>D                     { align1 1Q compacted };
>mov(8)          g69<1>D         g15<8,8,1>D                     { align1 1Q compacted };
>else(8)         JIP: 6136       UIP: 6136                       { align1 1Q };
>   END B60 ->B107
>   START B61 <-B55 (38 cycles)
>cmp.g.f0.0(8)   g55<1>F         g19<8,8,1>F     0x3f000000F  /* 0.5F */ { align1 1Q };
>mov(1)          g68.2<1>F       0x42000000F      /* 32F */      { align1 WE_all 1N };
>cmp.z.f0.0(8)   g73<1>D         g67<8,8,1>D     2D              { align1 1Q compacted };
>or.nz.f0.0(8)   null<1>UD       g73<8,8,1>UD    g55<8,8,1>UD    { align1 1Q compacted };
>(+f0.0) if(8)   JIP: 1032       UIP: 6056                       { align1 1Q };
>   END B61 ->B62 ->B70
>   START B62 <-B61 (378 cycles)
>rnde(8)         g56<1>F         g19<8,8,1>F                     { align1 1Q compacted };
>mov(8)          g75<1>UD        0x00000001UD                    { align1 1Q compacted };
>mov(8)          g19<1>F         g8.7<0,1,0>F                    { align1 1Q };
>mov(8)          g76<1>D         g56<8,8,1>F                     { align1 1Q compacted };
>shl(8)          g77<1>D         g36<8,8,1>D     g76<8,8,1>UD    { align1 1Q };
>mov(8)          g35<1>F         g77<8,8,1>D                     { align1 1Q compacted };
>mul(8)          g79<1>F         g35<8,8,1>F     0x3f000000F  /* 0.5F */ { align1 1Q };
>sel.ge(8)       g80<1>F         g51<8,8,1>F     g79<8,8,1>F     { align1 1Q compacted };
>sel.ge(8)       g81<1>F         g65<8,8,1>F     g79<8,8,1>F     { align1 1Q compacted };
>add(8)          g82<1>F         g25.3<0,1,0>F   -g79<8,8,1>F    { align1 1Q compacted };
>add(8)          g83<1>F         g25.7<0,1,0>F   -g79<8,8,1>F    { align1 1Q };
>sel.l(8)        g84<1>F         g80<8,8,1>F     g82<8,8,1>F     { align1 1Q compacted };
>sel.l(8)        g85<1>F         g81<8,8,1>F     g83<8,8,1>F     { align1 1Q compacted };
>mad(8)          g52<1>F         g24.3<0,1,0>F   g26.3<0,1,0>F   g84<4,4,1>F { align16 1Q };
>mad(8)          g55<1>F         g24.7<0,1,0>F   g26.3<0,1,0>F   g85<4,4,1>F { align16 1Q };
>mul(8)          g48<1>F         g52<8,8,1>F     0x3e800000F  /* 0.25F */ { align1 1Q };
>mov(8)          g17<1>D         g52<8,8,1>F                     { align1 1Q compacted };
>mul(8)          g87<1>F         g55<8,8,1>F     0x3e800000F  /* 0.25F */ { align1 1Q };
>mov(8)          g18<1>D         g55<8,8,1>F                     { align1 1Q compacted };
>rndd(8)         g88<1>F         g48<8,8,1>F                     { align1 1Q compacted };
>rndd(8)         g89<1>F         g87<8,8,1>F                     { align1 1Q compacted };
>send(8)         g12<1>UW        g17<8,8,1>UD    0x0643a304
>                            sampler MsgDesc: ld_lz SIMD8 Surface = 4 Sampler = 3 mlen 3 rlen 4 { align1 1Q };
>mad(8)          g90<1>F         g52<4,4,1>F     g88<4,4,1>F     -g59.7<0,1,0>F { align16 1Q };
>mad(8)          g91<1>F         g55<4,4,1>F     g89<4,4,1>F     -g59.7<0,1,0>F { align16 1Q };
>mul(8)          g92<1>F         g90<8,8,1>F     g26.7<0,1,0>F   { align1 1Q compacted };
>mul(8)          g93<1>F         g91<8,8,1>F     g26.7<0,1,0>F   { align1 1Q compacted };
>mul(8)          g94<1>F         g92<8,8,1>F     0x3d000000F  /* 0.03125F */ { align1 1Q };
>mul(8)          g57<1>F         g93<8,8,1>F     0x3d000000F  /* 0.03125F */ { align1 1Q };
>rndd(8)         g95<1>F         g94<8,8,1>F                     { align1 1Q compacted };
>rndd(8)         g61<1>F         g57<8,8,1>F                     { align1 1Q compacted };
>mad(8)          g96<1>F         g92<4,4,1>F     g95<4,4,1>F     -g68.2<0,1,0>F { align16 1Q };
>mad(8)          g99<1>F         g93<4,4,1>F     g61<4,4,1>F     -g68.2<0,1,0>F { align16 1Q };
>shl(8)          g101<1>D        g15<8,8,1>D     0x00000008UD    { align1 1Q };
>mov(8)          g73<1>D         g12<8,8,1>D                     { align1 1Q compacted };
>mov(8)          g56<1>D         g13<8,8,1>D                     { align1 1Q compacted };
>add(8)          g22<1>D         g14<8,8,1>D     g101<8,8,1>D    { align1 1Q compacted };
>   END B62 ->B63
>   START B64 <-B63 <-B65 (18 cycles)
>cmp.ge.f0.0(8)  null<1>UD       g75<8,8,1>UD    g9.3<0,1,0>UD   { align1 1Q compacted };
>   END B63 ->B64 ->B66
>(+f0.0) break(8) JIP: 192       UIP: 192                        { align1 1Q };
>   END B64 ->B63 ->B65
>   START B65 <-B64 (304 cycles)
>rndd(8)         g102<1>F        g52<8,8,1>F                     { align1 1Q compacted };
>rndd(8)         g5<1>F          g55<8,8,1>F                     { align1 1Q compacted };
>mov(8)          g106<1>F        g73<8,8,1>UD                    { align1 1Q compacted };
>mov(8)          g107<1>F        g56<8,8,1>UD                    { align1 1Q compacted };
>add(8)          g75<1>D         g75<8,8,1>D     1D              { align1 1Q compacted };
>add(8)          g50<1>F         g52<8,8,1>F     -g102<8,8,1>F   { align1 1Q compacted };
>add(8)          g105<1>F        g55<8,8,1>F     -g5<8,8,1>F     { align1 1Q compacted };
>add(8)          g108<1>F        g50<8,8,1>F     g106<8,8,1>F    { align1 1Q compacted };
>add(8)          g47<1>F         g105<8,8,1>F    g107<8,8,1>F    { align1 1Q compacted };
>mul(8)          g52<1>F         g108<8,8,1>F    0x40800000F  /* 4F */ { align1 1Q };
>mul(8)          g55<1>F         g47<8,8,1>F     0x40800000F  /* 4F */ { align1 1Q };
>mov(8)          g20<1>D         g52<8,8,1>F                     { align1 1Q compacted };
>mov(8)          g21<1>D         g55<8,8,1>F                     { align1 1Q compacted };
>send(8)         g12<1>UW        g20<8,8,1>UD    0x0643a304
>                            sampler MsgDesc: ld_lz SIMD8 Surface = 4 Sampler = 3 mlen 3 rlen 4 { align1 1Q };
>shl(8)          g46<1>D         g15<8,8,1>D     0x00000008UD    { align1 1Q };
>mov(8)          g73<1>D         g12<8,8,1>D                     { align1 1Q compacted };
>mov(8)          g56<1>D         g13<8,8,1>D                     { align1 1Q compacted };
>add(8)          g22<1>D         g14<8,8,1>D     g46<8,8,1>D     { align1 1Q compacted };
>while(8)        JIP: -200                                       { align1 1Q };
>   END B65 ->B64
>   START B66 <-B63 (90 cycles)
>rndd(8)         g111<1>F        g52<8,8,1>F                     { align1 1Q compacted };
>rndd(8)         g112<1>F        g55<8,8,1>F                     { align1 1Q compacted };
>mov(8)          g115<1>F        g73<8,8,1>UD                    { align1 1Q compacted };
>mov(8)          g116<1>F        g56<8,8,1>UD                    { align1 1Q compacted };
>sel.l(8)        g119<1>F        -g96<8,8,1>F    -g99<8,8,1>F    { align1 1Q compacted };
>cmp.ge.f0.0(8)  g121<1>F        -g79<8,8,1>F    -g96<8,8,1>F    { align1 1Q compacted };
>add(8)          g113<1>F        g52<8,8,1>F     -g111<8,8,1>F   { align1 1Q compacted };
>add(8)          g114<1>F        g55<8,8,1>F     -g112<8,8,1>F   { align1 1Q compacted };
>add(8)          g120<1>F        g119<8,8,1>F    0x41f80000F  /* 31F */ { align1 1Q };
>add(8)          g117<1>F        g113<8,8,1>F    g115<8,8,1>F    { align1 1Q compacted };
>add(8)          g118<1>F        g114<8,8,1>F    g116<8,8,1>F    { align1 1Q compacted };
>cmp.ge.f0.0(8)  g122<1>F        g120<8,8,1>F    g79<8,8,1>F     { align1 1Q compacted };
>cmp.ge.f0.0(8)  g124<1>F        -g79<8,8,1>F    -g99<8,8,1>F    { align1 1Q compacted };
>and(8)          g123<1>UD       g122<8,8,1>UD   g121<8,8,1>UD   { align1 1Q compacted };
>and.nz.f0.0(8)  null<1>UD       g123<8,8,1>UD   g124<8,8,1>UD   { align1 1Q compacted };
>(+f0.0) if(8)   JIP: 96         UIP: 192                        { align1 1Q };
>   END B66 ->B67 ->B68
>   START B67 <-B66 (26 cycles)
>mul(8)          g13<1>F         g117<8,8,1>F    0x3b800000F  /* 0.00390625F */ { align1 1Q };
>mul(8)          g14<1>F         g118<8,8,1>F    0x3b800000F  /* 0.00390625F */ { align1 1Q };
>mov(8)          g15<1>F         g22<8,8,1>UD                    { align1 1Q compacted };
>mov(8)          g12<1>F         g76<8,8,1>D                     { align1 1Q compacted };
>send(8)         g12<1>UW        g12<8,8,1>UD    0x08422102
>                            sampler MsgDesc: sample_l SIMD8 Surface = 2 Sampler = 1 mlen 4 rlen 4 { align1 1Q };
>else(8)         JIP: 112        UIP: 112                        { align1 1Q };
>   END B67 ->B69
>   START B68 <-B66 (232 cycles)
>mul(8)          g17<1>F         g117<8,8,1>F    0x3b800000F  /* 0.00390625F */ { align1 1Q };
>mul(8)          g18<1>F         g118<8,8,1>F    0x3b800000F  /* 0.00390625F */ { align1 1Q };
>mov(8)          g19<1>F         g22<8,8,1>UD                    { align1 1Q compacted };
>mov(8)          g16<1>F         g76<8,8,1>D                     { align1 1Q compacted };
>send(8)         g16<1>UW        g16<8,8,1>UD    0x08422203
>                            sampler MsgDesc: sample_l SIMD8 Surface = 3 Sampler = 2 mlen 4 rlen 4 { align1 1Q };
>mov(8)          g12<1>F         g16<8,8,1>F                     { align1 1Q compacted };
>mov(8)          g13<1>F         g17<8,8,1>F                     { align1 1Q compacted };
>mov(8)          g14<1>F         g18<8,8,1>F                     { align1 1Q compacted };
>mov(8)          g15<1>F         g19<8,8,1>F                     { align1 1Q compacted };
>   END B68 ->B69
>   START B69 <-B68 <-B67 (12 cycles)
>endif(8)        JIP: 48                                         { align1 1Q };
>mov(8)          g98<1>D         g12<8,8,1>D                     { align1 1Q compacted };
>mov(8)          g62<1>D         g13<8,8,1>D                     { align1 1Q compacted };
>mov(8)          g63<1>D         g14<8,8,1>D                     { align1 1Q compacted };
>mov(8)          g69<1>D         g15<8,8,1>D                     { align1 1Q compacted };
>else(8)         JIP: 5040       UIP: 5040                       { align1 1Q };
>   END B69 ->B106
>   START B70 <-B61 (306 cycles)
>sel.ge(8)       g127<1>F        g51<8,8,1>F     0x40000000F  /* 2F */ { align1 1Q };
>sel.ge(8)       g12<1>F         g65<8,8,1>F     0x40000000F  /* 2F */ { align1 1Q };
>add(8)          g13<1>F         g25.3<0,1,0>F   0xc0000000F  /* -2F */ { align1 1Q };
>add(8)          g14<1>F         g25.7<0,1,0>F   0xc0000000F  /* -2F */ { align1 1Q };
>sel.l(8)        g15<1>F         g127<8,8,1>F    g13<8,8,1>F     { align1 1Q compacted };
>sel.l(8)        g16<1>F         g12<8,8,1>F     g14<8,8,1>F     { align1 1Q compacted };
>mad(8)          g17<1>F         g24.3<0,1,0>F   g26.3<0,1,0>F   g15<4,4,1>F { align16 1Q };
>mad(8)          g18<1>F         g24.7<0,1,0>F   g26.3<0,1,0>F   g16<4,4,1>F { align16 1Q };
>mad(8)          g76<1>F         g17<4,4,1>F     g26.3<0,1,0>F   -g59.0<0,1,0>F { align16 1Q };
>mad(8)          g77<1>F         g18<4,4,1>F     g26.3<0,1,0>F   -g59.0<0,1,0>F { align16 1Q };
>add(8)          g19<1>F         g76<8,8,1>F     -g24.3<0,1,0>F  { align1 1Q compacted };
>add(8)          g20<1>F         g77<8,8,1>F     -g24.7<0,1,0>F  { align1 1Q compacted };
>mul(8)          g21<1>F         g19<8,8,1>F     g26.7<0,1,0>F   { align1 1Q compacted };
>mul(8)          g22<1>F         g20<8,8,1>F     g26.7<0,1,0>F   { align1 1Q compacted };
>mul(8)          g23<1>F         g21<8,8,1>F     0x3d000000F  /* 0.03125F */ { align1 1Q };
>frc(8)          g33<1>F         g21<8,8,1>F                     { align1 1Q compacted };
>mul(8)          g29<1>F         g22<8,8,1>F     0x3d000000F  /* 0.03125F */ { align1 1Q };
>frc(8)          g34<1>F         g22<8,8,1>F                     { align1 1Q compacted };
>rndd(8)         g25<1>F         g23<8,8,1>F                     { align1 1Q compacted };
>mul(8)          g37<1>F         g33<8,8,1>F     g33<8,8,1>F     { align1 1Q compacted };
>add(8)          g39<1>F         -g33<8,8,1>F    0x3f800000F  /* 1F */ { align1 1Q };
>rndd(8)         g30<1>F         g29<8,8,1>F                     { align1 1Q compacted };
>mul(8)          g73<1>F         g34<8,8,1>F     g34<8,8,1>F     { align1 1Q compacted };
>add(8)          g75<1>F         -g34<8,8,1>F    0x3f800000F  /* 1F */ { align1 1Q };
>mad(8)          g27<1>F         g21<4,4,1>F     g25<4,4,1>F     -g68.2<0,1,0>F { align16 1Q };
>mul(8)          g38<1>F         g37<8,8,1>F     g33<8,8,1>F     { align1 1Q compacted };
>mul(8)          g42<1>F         g37<8,8,1>F     0x40c00000F  /* 6F */ { align1 1Q };
>mul(8)          g40<1>F         g39<8,8,1>F     g39<8,8,1>F     { align1 1Q compacted };
>mad(8)          g31<1>F         g22<4,4,1>F     g30<4,4,1>F     -g68.2<0,1,0>F { align16 1Q };
>mul(8)          g56<1>F         g73<8,8,1>F     g34<8,8,1>F     { align1 1Q compacted };
>mul(8)          g80<1>F         g73<8,8,1>F     0x40c00000F  /* 6F */ { align1 1Q };
>mul(8)          g35<1>F         g75<8,8,1>F     g75<8,8,1>F     { align1 1Q compacted };
>mul(8)          g55<1>F         g38<8,8,1>F     0x3e2aaaabF  /* 0.166667F */ { align1 1Q };
>mad(8)          g43<1>F         -g42<4,4,1>F    g38<4,4,1>F     g68.0<0,1,0>F { align16 1Q };
>add(8)          g28<1>F         -g27<8,8,1>F    0x41f80000F  /* 31F */ { align1 1Q };
>mul(8)          g41<1>F         g40<8,8,1>F     g39<8,8,1>F     { align1 1Q compacted };
>mul(8)          g48<1>F         g56<8,8,1>F     0x3e2aaaabF  /* 0.166667F */ { align1 1Q };
>mad(8)          g81<1>F         -g80<4,4,1>F    g56<4,4,1>F     g68.0<0,1,0>F { align16 1Q };
>add(8)          g32<1>F         -g31<8,8,1>F    0x41f80000F  /* 31F */ { align1 1Q };
>sel.ge(8)       g105<1>F        -g27<8,8,1>F    -g31<8,8,1>F    { align1 1Q compacted };
>mul(8)          g79<1>F         g35<8,8,1>F     g75<8,8,1>F     { align1 1Q compacted };
>cmp.ge.f0.0(8)  g106<1>F        g28<8,8,1>F     0x40200000F  /* 2.5F */ { align1 1Q };
>mad(8)          g45<1>F         g59.7<0,1,0>F   g41<4,4,1>F     g68.0<0,1,0>F { align16 1Q };
>add(8)          g44<1>F         g43<8,8,1>F     0x40800000F  /* 4F */ { align1 1Q };
>cmp.le.f0.0(8)  g107<1>F        g105<8,8,1>F    0xbfc00000F  /* -1.5F */ { align1 1Q };
>add(8)          g82<1>F         g81<8,8,1>F     0x40800000F  /* 4F */ { align1 1Q };
>cmp.ge.f0.0(8)  g47<1>F         g32<8,8,1>F     0x40200000F  /* 2.5F */ { align1 1Q };
>mad(8)          g83<1>F         g59.7<0,1,0>F   g79<4,4,1>F     g68.0<0,1,0>F { align16 1Q };
>mul(8)          g52<1>F         g44<8,8,1>F     0x3e2aaaabF  /* 0.166667F */ { align1 1Q };
>add(8)          g87<1>F         g41<8,8,1>F     g44<8,8,1>F     { align1 1Q compacted };
>mad(8)          g70<1>F         g45<4,4,1>F     g40<4,4,1>F     -g68.1<0,1,0>F { align16 1Q };
>and(8)          g108<1>UD       g107<8,8,1>UD   g106<8,8,1>UD   { align1 1Q compacted };
>mul(8)          g85<1>F         g82<8,8,1>F     0x3e2aaaabF  /* 0.166667F */ { align1 1Q };
>add(8)          g91<1>F         g79<8,8,1>F     g82<8,8,1>F     { align1 1Q compacted };
>mad(8)          g84<1>F         g83<4,4,1>F     g35<4,4,1>F     -g68.1<0,1,0>F { align16 1Q };
>mul(8)          g88<1>F         g87<8,8,1>F     0x3e2aaaabF  /* 0.166667F */ { align1 1Q };
>and.nz.f0.0(8)  null<1>UD       g108<8,8,1>UD   g47<8,8,1>UD    { align1 1Q compacted };
>add(8)          g89<1>F         g70<8,8,1>F     g38<8,8,1>F     { align1 1Q compacted };
>mul(8)          g92<1>F         g91<8,8,1>F     0x3e2aaaabF  /* 0.166667F */ { align1 1Q };
>math inv(8)     g95<1>F         g88<8,8,1>F     null<8,8,1>F    { align1 1Q compacted };
>add(8)          g93<1>F         g84<8,8,1>F     g56<8,8,1>F     { align1 1Q compacted };
>mul(8)          g90<1>F         g89<8,8,1>F     0x3e2aaaabF  /* 0.166667F */ { align1 1Q };
>add(8)          g99<1>F         g87<8,8,1>F     g89<8,8,1>F     { align1 1Q compacted };
>math inv(8)     g57<1>F         g92<8,8,1>F     null<8,8,1>F    { align1 1Q compacted };
>mul(8)          g94<1>F         g93<8,8,1>F     0x3e2aaaabF  /* 0.166667F */ { align1 1Q };
>add(8)          g102<1>F        g91<8,8,1>F     g93<8,8,1>F     { align1 1Q compacted };
>math inv(8)     g96<1>F         g90<8,8,1>F     null<8,8,1>F    { align1 1Q compacted };
>mul(8)          g100<1>F        g99<8,8,1>F     0x3e2aaaabF  /* 0.166667F */ { align1 1Q };
>math inv(8)     g61<1>F         g94<8,8,1>F     null<8,8,1>F    { align1 1Q compacted };
>mul(8)          g5<1>F          g102<8,8,1>F    0x3e2aaaabF  /* 0.166667F */ { align1 1Q };
>math inv(8)     g101<1>F        g100<8,8,1>F    null<8,8,1>F    { align1 1Q compacted };
>math inv(8)     g50<1>F         g5<8,8,1>F      null<8,8,1>F    { align1 1Q compacted };
>mul(8)          g25<1>F         g90<8,8,1>F     g101<8,8,1>F    { align1 1Q compacted };
>mul(8)          g70<1>F         g94<8,8,1>F     g50<8,8,1>F     { align1 1Q compacted };
>(+f0.0) if(8)   JIP: 728        UIP: 4008                       { align1 1Q };
>   END B70 ->B71 ->B76
>   START B71 <-B70 (240 cycles)
>mov(8)          g18<1>D         g76<8,8,1>F                     { align1 1Q compacted };
>mov(8)          g19<1>D         g77<8,8,1>F                     { align1 1Q compacted };
>mov(8)          g20<1>F         g8.7<0,1,0>F                    { align1 1Q };
>mov(8)          g80<1>UD        0x00000001UD                    { align1 1Q compacted };
>send(8)         g12<1>UW        g18<8,8,1>UD    0x0643a304
>                            sampler MsgDesc: ld_lz SIMD8 Surface = 4 Sampler = 3 mlen 3 rlen 4 { align1 1Q };
>shl(8)          g111<1>D        g15<8,8,1>D     0x00000008UD    { align1 1Q };
>mov(8)          g35<1>D         g12<8,8,1>D                     { align1 1Q compacted };
>mov(8)          g79<1>D         g13<8,8,1>D                     { align1 1Q compacted };
>add(8)          g18<1>D         g14<8,8,1>D     g111<8,8,1>D    { align1 1Q compacted };
>   END B71 ->B72
>   START B73 <-B72 <-B74 (18 cycles)
>cmp.ge.f0.0(8)  null<1>UD       g80<8,8,1>UD    g9.3<0,1,0>UD   { align1 1Q compacted };
>   END B72 ->B73 ->B75
>(+f0.0) break(8) JIP: 192       UIP: 192                        { align1 1Q };
>   END B73 ->B72 ->B74
>   START B74 <-B73 (304 cycles)
>rndd(8)         g112<1>F        g76<8,8,1>F                     { align1 1Q compacted };
>rndd(8)         g113<1>F        g77<8,8,1>F                     { align1 1Q compacted };
>mov(8)          g116<1>F        g35<8,8,1>UD                    { align1 1Q compacted };
>mov(8)          g117<1>F        g79<8,8,1>UD                    { align1 1Q compacted };
>add(8)          g80<1>D         g80<8,8,1>D     1D              { align1 1Q compacted };
>add(8)          g114<1>F        g76<8,8,1>F     -g112<8,8,1>F   { align1 1Q compacted };
>add(8)          g115<1>F        g77<8,8,1>F     -g113<8,8,1>F   { align1 1Q compacted };
>add(8)          g118<1>F        g114<8,8,1>F    g116<8,8,1>F    { align1 1Q compacted };
>add(8)          g119<1>F        g115<8,8,1>F    g117<8,8,1>F    { align1 1Q compacted };
>mul(8)          g76<1>F         g118<8,8,1>F    0x40800000F  /* 4F */ { align1 1Q };
>mul(8)          g77<1>F         g119<8,8,1>F    0x40800000F  /* 4F */ { align1 1Q };
>mov(8)          g16<1>D         g76<8,8,1>F                     { align1 1Q compacted };
>mov(8)          g17<1>D         g77<8,8,1>F                     { align1 1Q compacted };
>send(8)         g12<1>UW        g16<8,8,1>UD    0x0643a304
>                            sampler MsgDesc: ld_lz SIMD8 Surface = 4 Sampler = 3 mlen 3 rlen 4 { align1 1Q };
>shl(8)          g120<1>D        g15<8,8,1>D     0x00000008UD    { align1 1Q };
>mov(8)          g35<1>D         g12<8,8,1>D                     { align1 1Q compacted };
>mov(8)          g79<1>D         g13<8,8,1>D                     { align1 1Q compacted };
>add(8)          g18<1>D         g14<8,8,1>D     g120<8,8,1>D    { align1 1Q compacted };
>while(8)        JIP: -200                                       { align1 1Q };
>   END B74 ->B73
>   START B75 <-B72 (148 cycles)
>rndd(8)         g121<1>F        g76<8,8,1>F                     { align1 1Q compacted };
>rndd(8)         g122<1>F        g77<8,8,1>F                     { align1 1Q compacted };
>mov(8)          g125<1>F        g35<8,8,1>UD                    { align1 1Q compacted };
>mov(8)          g126<1>F        g79<8,8,1>UD                    { align1 1Q compacted };
>mov(8)          g21<1>F         g18<8,8,1>UD                    { align1 1Q compacted };
>add(8)          g123<1>F        g76<8,8,1>F     -g121<8,8,1>F   { align1 1Q compacted };
>add(8)          g124<1>F        g77<8,8,1>F     -g122<8,8,1>F   { align1 1Q compacted };
>mov(8)          g18<1>F         g21<8,8,1>F                     { align1 1Q compacted };
>mov(8)          g32<1>F         g21<8,8,1>F                     { align1 1Q compacted };
>mov(8)          g29<1>F         g21<8,8,1>F                     { align1 1Q compacted };
>add(8)          g127<1>F        g123<8,8,1>F    g125<8,8,1>F    { align1 1Q compacted };
>add(8)          g12<1>F         g124<8,8,1>F    g126<8,8,1>F    { align1 1Q compacted };
>mad(8)          g13<1>F         -g33<4,4,1>F    g127<4,4,1>F    g68.2<0,1,0>F { align16 1Q };
>mad(8)          g14<1>F         -g34<4,4,1>F    g12<4,4,1>F     g68.2<0,1,0>F { align16 1Q };
>add(8)          g15<1>F         g13<8,8,1>F     0xbf000000F  /* -0.5F */ { align1 1Q };
>add(8)          g23<1>F         g13<8,8,1>F     0x3fc00000F  /* 1.5F */ { align1 1Q };
>add(8)          g38<1>F         g14<8,8,1>F     0xbf000000F  /* -0.5F */ { align1 1Q };
>add(8)          g40<1>F         g14<8,8,1>F     0x3fc00000F  /* 1.5F */ { align1 1Q };
>mad(8)          g22<1>F         g15<4,4,1>F     g95<4,4,1>F     g52<4,4,1>F { align16 1Q compacted };
>mad(8)          g37<1>F         g23<4,4,1>F     g96<4,4,1>F     g55<4,4,1>F { align16 1Q compacted };
>mad(8)          g39<1>F         g38<4,4,1>F     g57<4,4,1>F     g85<4,4,1>F { align16 1Q compacted };
>mad(8)          g41<1>F         g40<4,4,1>F     g61<4,4,1>F     g48<4,4,1>F { align16 1Q compacted };
>mul(8)          g19<1>F         g22<8,8,1>F     0x39000000F  /* 0.00012207F */ { align1 1Q };
>mul(8)          g16<1>F         g37<8,8,1>F     0x39000000F  /* 0.00012207F */ { align1 1Q };
>mul(8)          g20<1>F         g39<8,8,1>F     0x39000000F  /* 0.00012207F */ { align1 1Q };
>mul(8)          g31<1>F         g41<8,8,1>F     0x39000000F  /* 0.00012207F */ { align1 1Q };
>mov(8)          g30<1>F         g19<8,8,1>F                     { align1 1Q compacted };
>mov(8)          g27<1>F         g16<8,8,1>F                     { align1 1Q compacted };
>send(8)         g12<1>UW        g19<8,8,1>UD    0x06438102
>                            sampler MsgDesc: sample_lz SIMD8 Surface = 2 Sampler = 1 mlen 3 rlen 4 { align1 1Q };
>mov(8)          g17<1>F         g20<8,8,1>F                     { align1 1Q compacted };
>mov(8)          g28<1>F         g31<8,8,1>F                     { align1 1Q compacted };
>send(8)         g20<1>UW        g30<8,8,1>UD    0x06438102
>                            sampler MsgDesc: sample_lz SIMD8 Surface = 2 Sampler = 1 mlen 3 rlen 4 { align1 1Q };
>send(8)         g16<1>UW        g16<8,8,1>UD    0x06438102
>                            sampler MsgDesc: sample_lz SIMD8 Surface = 2 Sampler = 1 mlen 3 rlen 4 { align1 1Q };
>send(8)         g27<1>UW        g27<8,8,1>UD    0x06438102
>                            sampler MsgDesc: sample_lz SIMD8 Surface = 2 Sampler = 1 mlen 3 rlen 4 { align1 1Q };
>else(8)         JIP: 3296       UIP: 3296                       { align1 1Q };
>   END B75 ->B105
>   START B76 <-B70 (306 cycles)
>mad(8)          g44<1>F         g76<4,4,1>F     g26.3<0,1,0>F   -g33<4,4,1>F { align16 1Q };
>mad(8)          g45<1>F         g77<4,4,1>F     g26.3<0,1,0>F   -g34<4,4,1>F { align16 1Q };
>mov(1)          g68.3<1>F       0x3fc00000F      /* 1.5F */     { align1 WE_all 1N };
>mul(8)          g35<1>F         g85<8,8,1>F     g57<8,8,1>F     { align1 1Q compacted };
>mul(8)          g79<1>F         g48<8,8,1>F     g61<8,8,1>F     { align1 1Q compacted };
>mov(8)          g39<1>F         g8.7<0,1,0>F                    { align1 1Q };
>mul(8)          g76<1>F         g52<8,8,1>F     g95<8,8,1>F     { align1 1Q compacted };
>mul(8)          g77<1>F         g55<8,8,1>F     g96<8,8,1>F     { align1 1Q compacted };
>mov(8)          g48<1>UD        0x00000001UD                    { align1 1Q compacted };
>mad(8)          g52<1>F         g44<4,4,1>F     g26.3<0,1,0>F   -g59.0<0,1,0>F { align16 1Q };
>mad(8)          g56<1>F         g44<4,4,1>F     g26.3<0,1,0>F   g68.3<0,1,0>F { align16 1Q };
>mad(8)          g55<1>F         g45<4,4,1>F     g26.3<0,1,0>F   -g59.0<0,1,0>F { align16 1Q };
>mad(8)          g75<1>F         g45<4,4,1>F     g26.3<0,1,0>F   g68.3<0,1,0>F { align16 1Q };
>mad(8)          g73<1>F         g52<4,4,1>F     g26.3<0,1,0>F   g76<4,4,1>F { align16 1Q };
>mad(8)          g52<1>F         g56<4,4,1>F     g26.3<0,1,0>F   g77<4,4,1>F { align16 1Q };
>mad(8)          g81<1>F         g55<4,4,1>F     g26.3<0,1,0>F   g35<4,4,1>F { align16 1Q };
>mad(8)          g55<1>F         g75<4,4,1>F     g26.3<0,1,0>F   g79<4,4,1>F { align16 1Q };
>mul(8)          g80<1>F         g73<8,8,1>F     0x3e800000F  /* 0.25F */ { align1 1Q };
>mov(8)          g37<1>D         g73<8,8,1>F                     { align1 1Q compacted };
>mov(8)          g84<1>D         g73<8,8,1>D                     { align1 1Q compacted };
>mul(8)          g82<1>F         g81<8,8,1>F     0x3e800000F  /* 0.25F */ { align1 1Q };
>mov(8)          g38<1>D         g81<8,8,1>F                     { align1 1Q compacted };
>mov(8)          g85<1>D         g81<8,8,1>D                     { align1 1Q compacted };
>rndd(8)         g83<1>F         g80<8,8,1>F                     { align1 1Q compacted };
>rndd(8)         g87<1>F         g82<8,8,1>F                     { align1 1Q compacted };
>send(8)         g31<1>UW        g37<8,8,1>UD    0x0643a304
>                            sampler MsgDesc: ld_lz SIMD8 Surface = 4 Sampler = 3 mlen 3 rlen 4 { align1 1Q };
>mad(8)          g88<1>F         g73<4,4,1>F     g83<4,4,1>F     -g59.7<0,1,0>F { align16 1Q };
>mad(8)          g89<1>F         g81<4,4,1>F     g87<4,4,1>F     -g59.7<0,1,0>F { align16 1Q };
>mul(8)          g90<1>F         g88<8,8,1>F     g26.7<0,1,0>F   { align1 1Q compacted };
>mul(8)          g91<1>F         g89<8,8,1>F     g26.7<0,1,0>F   { align1 1Q compacted };
>mul(8)          g92<1>F         g90<8,8,1>F     0x3d000000F  /* 0.03125F */ { align1 1Q };
>mul(8)          g96<1>F         g91<8,8,1>F     0x3d000000F  /* 0.03125F */ { align1 1Q };
>rndd(8)         g93<1>F         g92<8,8,1>F                     { align1 1Q compacted };
>rndd(8)         g57<1>F         g96<8,8,1>F                     { align1 1Q compacted };
>mad(8)          g94<1>F         g90<4,4,1>F     g93<4,4,1>F     -g68.2<0,1,0>F { align16 1Q };
>mad(8)          g61<1>F         g91<4,4,1>F     g57<4,4,1>F     -g68.2<0,1,0>F { align16 1Q };
>add(8)          g95<1>F         -g94<8,8,1>F    0x41f80000F  /* 31F */ { align1 1Q };
>add(8)          g99<1>F         -g61<8,8,1>F    0x41f80000F  /* 31F */ { align1 1Q };
>mov(8)          g83<1>D         g32<8,8,1>D                     { align1 1Q compacted };
>shl(8)          g101<1>D        g34<8,8,1>D     0x00000008UD    { align1 1Q };
>mov(8)          g82<1>D         g31<8,8,1>D                     { align1 1Q compacted };
>add(8)          g42<1>D         g33<8,8,1>D     g101<8,8,1>D    { align1 1Q compacted };
>   END B76 ->B77
>   START B78 <-B77 <-B79 (18 cycles)
>cmp.ge.f0.0(8)  null<1>UD       g48<8,8,1>UD    g9.3<0,1,0>UD   { align1 1Q compacted };
>   END B77 ->B78 ->B80
>(+f0.0) break(8) JIP: 192       UIP: 192                        { align1 1Q };
>   END B78 ->B77 ->B79
>   START B79 <-B78 (304 cycles)
>rndd(8)         g102<1>F        g84<8,8,1>F                     { align1 1Q compacted };
>rndd(8)         g5<1>F          g85<8,8,1>F                     { align1 1Q compacted };
>mov(8)          g106<1>F        g82<8,8,1>UD                    { align1 1Q compacted };
>mov(8)          g107<1>F        g83<8,8,1>UD                    { align1 1Q compacted };
>add(8)          g48<1>D         g48<8,8,1>D     1D              { align1 1Q compacted };
>add(8)          g50<1>F         g84<8,8,1>F     -g102<8,8,1>F   { align1 1Q compacted };
>add(8)          g105<1>F        g85<8,8,1>F     -g5<8,8,1>F     { align1 1Q compacted };
>add(8)          g108<1>F        g50<8,8,1>F     g106<8,8,1>F    { align1 1Q compacted };
>add(8)          g47<1>F         g105<8,8,1>F    g107<8,8,1>F    { align1 1Q compacted };
>mul(8)          g84<1>F         g108<8,8,1>F    0x40800000F  /* 4F */ { align1 1Q };
>mul(8)          g85<1>F         g47<8,8,1>F     0x40800000F  /* 4F */ { align1 1Q };
>mov(8)          g40<1>D         g84<8,8,1>F                     { align1 1Q compacted };
>mov(8)          g41<1>D         g85<8,8,1>F                     { align1 1Q compacted };
>send(8)         g31<1>UW        g40<8,8,1>UD    0x0643a304
>                            sampler MsgDesc: ld_lz SIMD8 Surface = 4 Sampler = 3 mlen 3 rlen 4 { align1 1Q };
>shl(8)          g46<1>D         g34<8,8,1>D     0x00000008UD    { align1 1Q };
>mov(8)          g82<1>D         g31<8,8,1>D                     { align1 1Q compacted };
>mov(8)          g83<1>D         g32<8,8,1>D                     { align1 1Q compacted };
>add(8)          g42<1>D         g33<8,8,1>D     g46<8,8,1>D     { align1 1Q compacted };
>while(8)        JIP: -200                                       { align1 1Q };
>   END B79 ->B78
>   START B80 <-B77 (76 cycles)
>rndd(8)         g111<1>F        g84<8,8,1>F                     { align1 1Q compacted };
>rndd(8)         g112<1>F        g85<8,8,1>F                     { align1 1Q compacted };
>mov(8)          g115<1>F        g82<8,8,1>UD                    { align1 1Q compacted };
>mov(8)          g116<1>F        g83<8,8,1>UD                    { align1 1Q compacted };
>cmp.ge.f0.0(8)  g119<1>F        g99<8,8,1>F     0x3f000000F  /* 0.5F */ { align1 1Q };
>cmp.ge.f0.0(8)  g76<1>F         g95<8,8,1>F     0x3f000000F  /* 0.5F */ { align1 1Q };
>cmp.le.f0.0(8)  g77<1>F         -g94<8,8,1>F    0xbf000000F  /* -0.5F */ { align1 1Q };
>cmp.le.f0.0(8)  g122<1>F        -g61<8,8,1>F    0xbf000000F  /* -0.5F */ { align1 1Q };
>add(8)          g113<1>F        g84<8,8,1>F     -g111<8,8,1>F   { align1 1Q compacted };
>add(8)          g114<1>F        g85<8,8,1>F     -g112<8,8,1>F   { align1 1Q compacted };
>and(8)          g120<1>UD       g76<8,8,1>UD    g119<8,8,1>UD   { align1 1Q compacted };
>add(8)          g117<1>F        g113<8,8,1>F    g115<8,8,1>F    { align1 1Q compacted };
>add(8)          g118<1>F        g114<8,8,1>F    g116<8,8,1>F    { align1 1Q compacted };
>and(8)          g121<1>UD       g120<8,8,1>UD   g77<8,8,1>UD    { align1 1Q compacted };
>and.nz.f0.0(8)  null<1>UD       g121<8,8,1>UD   g122<8,8,1>UD   { align1 1Q compacted };
>(+f0.0) if(8)   JIP: 120        UIP: 208                        { align1 1Q };
>   END B80 ->B81 ->B82
>   START B81 <-B80 (232 cycles)
>mul(8)          g31<1>F         g117<8,8,1>F    0x3b800000F  /* 0.00390625F */ { align1 1Q };
>mul(8)          g32<1>F         g118<8,8,1>F    0x3b800000F  /* 0.00390625F */ { align1 1Q };
>mov(8)          g33<1>F         g42<8,8,1>UD                    { align1 1Q compacted };
>send(8)         g31<1>UW        g31<8,8,1>UD    0x06438102
>                            sampler MsgDesc: sample_lz SIMD8 Surface = 2 Sampler = 1 mlen 3 rlen 4 { align1 1Q };
>mov(8)          g12<1>F         g31<8,8,1>F                     { align1 1Q compacted };
>mov(8)          g13<1>F         g32<8,8,1>F                     { align1 1Q compacted };
>mov(8)          g14<1>F         g33<8,8,1>F                     { align1 1Q compacted };
>mov(8)          g15<1>F         g34<8,8,1>F                     { align1 1Q compacted };
>else(8)         JIP: 104        UIP: 104                        { align1 1Q };
>   END B81 ->B83
>   START B82 <-B80 (230 cycles)
>mul(8)          g31<1>F         g117<8,8,1>F    0x3b800000F  /* 0.00390625F */ { align1 1Q };
>mul(8)          g32<1>F         g118<8,8,1>F    0x3b800000F  /* 0.00390625F */ { align1 1Q };
>mov(8)          g33<1>F         g42<8,8,1>UD                    { align1 1Q compacted };
>send(8)         g31<1>UW        g31<8,8,1>UD    0x06438203
>                            sampler MsgDesc: sample_lz SIMD8 Surface = 3 Sampler = 2 mlen 3 rlen 4 { align1 1Q };
>mov(8)          g12<1>F         g31<8,8,1>F                     { align1 1Q compacted };
>mov(8)          g13<1>F         g32<8,8,1>F                     { align1 1Q compacted };
>mov(8)          g14<1>F         g33<8,8,1>F                     { align1 1Q compacted };
>mov(8)          g15<1>F         g34<8,8,1>F                     { align1 1Q compacted };
>   END B82 ->B83
>   START B83 <-B82 <-B81 (270 cycles)
>endif(8)        JIP: 2176                                       { align1 1Q };
>mul(8)          g123<1>F        g52<8,8,1>F     0x3e800000F  /* 0.25F */ { align1 1Q };
>mov(8)          g40<1>D         g52<8,8,1>F                     { align1 1Q compacted };
>mov(8)          g41<1>F         g38<8,8,1>F                     { align1 1Q compacted };
>mov(8)          g42<1>F         g8.7<0,1,0>F                    { align1 1Q };
>mov(8)          g90<1>UD        0x00000001UD                    { align1 1Q compacted };
>mov(8)          g89<1>D         g52<8,8,1>D                     { align1 1Q compacted };
>rndd(8)         g124<1>F        g123<8,8,1>F                    { align1 1Q compacted };
>send(8)         g31<1>UW        g40<8,8,1>UD    0x0643a304
>                            sampler MsgDesc: ld_lz SIMD8 Surface = 4 Sampler = 3 mlen 3 rlen 4 { align1 1Q };
>mad(8)          g125<1>F        g52<4,4,1>F     g124<4,4,1>F    -g59.7<0,1,0>F { align16 1Q };
>mul(8)          g126<1>F        g125<8,8,1>F    g26.7<0,1,0>F   { align1 1Q compacted };
>mul(8)          g127<1>F        g126<8,8,1>F    0x3d000000F  /* 0.03125F */ { align1 1Q };
>shl(8)          g80<1>D         g34<8,8,1>D     0x00000008UD    { align1 1Q };
>mov(8)          g87<1>D         g31<8,8,1>D                     { align1 1Q compacted };
>mov(8)          g88<1>D         g32<8,8,1>D                     { align1 1Q compacted };
>rndd(8)         g31<1>F         g127<8,8,1>F                    { align1 1Q compacted };
>add(8)          g45<1>D         g33<8,8,1>D     g80<8,8,1>D     { align1 1Q compacted };
>mad(8)          g75<1>F         g126<4,4,1>F    g31<4,4,1>F     -g68.2<0,1,0>F { align16 1Q };
>add(8)          g35<1>F         -g75<8,8,1>F    0x41f80000F  /* 31F */ { align1 1Q };
>   END B83 ->B84
>   START B85 <-B84 <-B86 (18 cycles)
>cmp.ge.f0.0(8)  null<1>UD       g90<8,8,1>UD    g9.3<0,1,0>UD   { align1 1Q compacted };
>   END B84 ->B85 ->B87
>(+f0.0) break(8) JIP: 192       UIP: 192                        { align1 1Q };
>   END B85 ->B84 ->B86
>   START B86 <-B85 (304 cycles)
>rndd(8)         g82<1>F         g89<8,8,1>F                     { align1 1Q compacted };
>rndd(8)         g83<1>F         g81<8,8,1>F                     { align1 1Q compacted };
>mov(8)          g48<1>F         g87<8,8,1>UD                    { align1 1Q compacted };
>mov(8)          g91<1>F         g88<8,8,1>UD                    { align1 1Q compacted };
>add(8)          g90<1>D         g90<8,8,1>D     1D              { align1 1Q compacted };
>add(8)          g84<1>F         g89<8,8,1>F     -g82<8,8,1>F    { align1 1Q compacted };
>add(8)          g85<1>F         g81<8,8,1>F     -g83<8,8,1>F    { align1 1Q compacted };
>add(8)          g92<1>F         g84<8,8,1>F     g48<8,8,1>F     { align1 1Q compacted };
>add(8)          g93<1>F         g85<8,8,1>F     g91<8,8,1>F     { align1 1Q compacted };
>mul(8)          g89<1>F         g92<8,8,1>F     0x40800000F  /* 4F */ { align1 1Q };
>mul(8)          g81<1>F         g93<8,8,1>F     0x40800000F  /* 4F */ { align1 1Q };
>mov(8)          g43<1>D         g89<8,8,1>F                     { align1 1Q compacted };
>mov(8)          g44<1>D         g81<8,8,1>F                     { align1 1Q compacted };
>send(8)         g31<1>UW        g43<8,8,1>UD    0x0643a304
>                            sampler MsgDesc: ld_lz SIMD8 Surface = 4 Sampler = 3 mlen 3 rlen 4 { align1 1Q };
>shl(8)          g94<1>D         g34<8,8,1>D     0x00000008UD    { align1 1Q };
>mov(8)          g87<1>D         g31<8,8,1>D                     { align1 1Q compacted };
>mov(8)          g88<1>D         g32<8,8,1>D                     { align1 1Q compacted };
>add(8)          g45<1>D         g33<8,8,1>D     g94<8,8,1>D     { align1 1Q compacted };
>while(8)        JIP: -200                                       { align1 1Q };
>   END B86 ->B85
>   START B87 <-B84 (74 cycles)
>rndd(8)         g95<1>F         g89<8,8,1>F                     { align1 1Q compacted };
>rndd(8)         g96<1>F         g81<8,8,1>F                     { align1 1Q compacted };
>mov(8)          g99<1>F         g87<8,8,1>UD                    { align1 1Q compacted };
>mov(8)          g100<1>F        g88<8,8,1>UD                    { align1 1Q compacted };
>cmp.ge.f0.0(8)  g56<1>F         g35<8,8,1>F     0x3f000000F  /* 0.5F */ { align1 1Q };
>cmp.le.f0.0(8)  g75<1>F         -g75<8,8,1>F    0xbf000000F  /* -0.5F */ { align1 1Q };
>add(8)          g57<1>F         g89<8,8,1>F     -g95<8,8,1>F    { align1 1Q compacted };
>add(8)          g61<1>F         g81<8,8,1>F     -g96<8,8,1>F    { align1 1Q compacted };
>and(8)          g5<1>UD         g56<8,8,1>UD    g119<8,8,1>UD   { align1 1Q compacted };
>add(8)          g101<1>F        g57<8,8,1>F     g99<8,8,1>F     { align1 1Q compacted };
>add(8)          g102<1>F        g61<8,8,1>F     g100<8,8,1>F    { align1 1Q compacted };
>and(8)          g50<1>UD        g5<8,8,1>UD     g75<8,8,1>UD    { align1 1Q compacted };
>and.nz.f0.0(8)  null<1>UD       g50<8,8,1>UD    g122<8,8,1>UD   { align1 1Q compacted };
>(+f0.0) if(8)   JIP: 120        UIP: 208                        { align1 1Q };
>   END B87 ->B88 ->B89
>   START B88 <-B87 (232 cycles)
>mul(8)          g31<1>F         g101<8,8,1>F    0x3b800000F  /* 0.00390625F */ { align1 1Q };
>mul(8)          g32<1>F         g102<8,8,1>F    0x3b800000F  /* 0.00390625F */ { align1 1Q };
>mov(8)          g33<1>F         g45<8,8,1>UD                    { align1 1Q compacted };
>send(8)         g31<1>UW        g31<8,8,1>UD    0x06438102
>                            sampler MsgDesc: sample_lz SIMD8 Surface = 2 Sampler = 1 mlen 3 rlen 4 { align1 1Q };
>mov(8)          g16<1>F         g31<8,8,1>F                     { align1 1Q compacted };
>mov(8)          g17<1>F         g32<8,8,1>F                     { align1 1Q compacted };
>mov(8)          g18<1>F         g33<8,8,1>F                     { align1 1Q compacted };
>mov(8)          g19<1>F         g34<8,8,1>F                     { align1 1Q compacted };
>else(8)         JIP: 104        UIP: 104                        { align1 1Q };
>   END B88 ->B90
>   START B89 <-B87 (230 cycles)
>mul(8)          g31<1>F         g101<8,8,1>F    0x3b800000F  /* 0.00390625F */ { align1 1Q };
>mul(8)          g32<1>F         g102<8,8,1>F    0x3b800000F  /* 0.00390625F */ { align1 1Q };
>mov(8)          g33<1>F         g45<8,8,1>UD                    { align1 1Q compacted };
>send(8)         g31<1>UW        g31<8,8,1>UD    0x06438203
>                            sampler MsgDesc: sample_lz SIMD8 Surface = 3 Sampler = 2 mlen 3 rlen 4 { align1 1Q };
>mov(8)          g16<1>F         g31<8,8,1>F                     { align1 1Q compacted };
>mov(8)          g17<1>F         g32<8,8,1>F                     { align1 1Q compacted };
>mov(8)          g18<1>F         g33<8,8,1>F                     { align1 1Q compacted };
>mov(8)          g19<1>F         g34<8,8,1>F                     { align1 1Q compacted };
>   END B89 ->B90
>   START B90 <-B89 <-B88 (244 cycles)
>endif(8)        JIP: 1408                                       { align1 1Q };
>mul(8)          g105<1>F        g55<8,8,1>F     0x3e800000F  /* 0.25F */ { align1 1Q };
>mov(8)          g44<1>D         g55<8,8,1>F                     { align1 1Q compacted };
>mov(8)          g43<1>F         g37<8,8,1>F                     { align1 1Q compacted };
>mov(8)          g45<1>F         g8.7<0,1,0>F                    { align1 1Q };
>mov(8)          g94<1>UD        0x00000001UD                    { align1 1Q compacted };
>mov(8)          g93<1>D         g55<8,8,1>D                     { align1 1Q compacted };
>rndd(8)         g106<1>F        g105<8,8,1>F                    { align1 1Q compacted };
>send(8)         g31<1>UW        g43<8,8,1>UD    0x0643a304
>                            sampler MsgDesc: ld_lz SIMD8 Surface = 4 Sampler = 3 mlen 3 rlen 4 { align1 1Q };
>mad(8)          g107<1>F        g55<4,4,1>F     g106<4,4,1>F    -g59.7<0,1,0>F { align16 1Q };
>mul(8)          g108<1>F        g107<8,8,1>F    g26.7<0,1,0>F   { align1 1Q compacted };
>mul(8)          g47<1>F         g108<8,8,1>F    0x3d000000F  /* 0.03125F */ { align1 1Q };
>rndd(8)         g46<1>F         g47<8,8,1>F                     { align1 1Q compacted };
>mad(8)          g111<1>F        g108<4,4,1>F    g46<4,4,1>F     -g68.2<0,1,0>F { align16 1Q };
>add(8)          g112<1>F        -g111<8,8,1>F   0x41f80000F  /* 31F */ { align1 1Q };
>shl(8)          g114<1>D        g34<8,8,1>D     0x00000008UD    { align1 1Q };
>mov(8)          g91<1>D         g31<8,8,1>D                     { align1 1Q compacted };
>mov(8)          g92<1>D         g32<8,8,1>D                     { align1 1Q compacted };
>add(8)          g39<1>D         g33<8,8,1>D     g114<8,8,1>D    { align1 1Q compacted };
>   END B90 ->B91
>   START B92 <-B91 <-B93 (18 cycles)
>cmp.ge.f0.0(8)  null<1>UD       g94<8,8,1>UD    g9.3<0,1,0>UD   { align1 1Q compacted };
>   END B91 ->B92 ->B94
>(+f0.0) break(8) JIP: 192       UIP: 192                        { align1 1Q };
>   END B92 ->B91 ->B93
>   START B93 <-B92 (304 cycles)
>rndd(8)         g115<1>F        g73<8,8,1>F                     { align1 1Q compacted };
>rndd(8)         g116<1>F        g93<8,8,1>F                     { align1 1Q compacted };
>mov(8)          g119<1>F        g91<8,8,1>UD                    { align1 1Q compacted };
>mov(8)          g120<1>F        g92<8,8,1>UD                    { align1 1Q compacted };
>add(8)          g94<1>D         g94<8,8,1>D     1D              { align1 1Q compacted };
>add(8)          g117<1>F        g73<8,8,1>F     -g115<8,8,1>F   { align1 1Q compacted };
>add(8)          g118<1>F        g93<8,8,1>F     -g116<8,8,1>F   { align1 1Q compacted };
>add(8)          g121<1>F        g117<8,8,1>F    g119<8,8,1>F    { align1 1Q compacted };
>add(8)          g122<1>F        g118<8,8,1>F    g120<8,8,1>F    { align1 1Q compacted };
>mul(8)          g73<1>F         g121<8,8,1>F    0x40800000F  /* 4F */ { align1 1Q };
>mul(8)          g93<1>F         g122<8,8,1>F    0x40800000F  /* 4F */ { align1 1Q };
>mov(8)          g37<1>D         g73<8,8,1>F                     { align1 1Q compacted };
>mov(8)          g38<1>D         g93<8,8,1>F                     { align1 1Q compacted };
>send(8)         g31<1>UW        g37<8,8,1>UD    0x0643a304
>                            sampler MsgDesc: ld_lz SIMD8 Surface = 4 Sampler = 3 mlen 3 rlen 4 { align1 1Q };
>shl(8)          g123<1>D        g34<8,8,1>D     0x00000008UD    { align1 1Q };
>mov(8)          g91<1>D         g31<8,8,1>D                     { align1 1Q compacted };
>mov(8)          g92<1>D         g32<8,8,1>D                     { align1 1Q compacted };
>add(8)          g39<1>D         g33<8,8,1>D     g123<8,8,1>D    { align1 1Q compacted };
>while(8)        JIP: -200                                       { align1 1Q };
>   END B93 ->B92
>   START B94 <-B91 (74 cycles)
>rndd(8)         g124<1>F        g73<8,8,1>F                     { align1 1Q compacted };
>rndd(8)         g125<1>F        g93<8,8,1>F                     { align1 1Q compacted };
>mov(8)          g26<1>F         g91<8,8,1>UD                    { align1 1Q compacted };
>mov(8)          g31<1>F         g92<8,8,1>UD                    { align1 1Q compacted };
>cmp.ge.f0.0(8)  g35<1>F         g112<8,8,1>F    0x3f000000F  /* 0.5F */ { align1 1Q };
>cmp.le.f0.0(8)  g81<1>F         -g111<8,8,1>F   0xbf000000F  /* -0.5F */ { align1 1Q };
>add(8)          g126<1>F        g73<8,8,1>F     -g124<8,8,1>F   { align1 1Q compacted };
>add(8)          g127<1>F        g93<8,8,1>F     -g125<8,8,1>F   { align1 1Q compacted };
>and(8)          g79<1>UD        g76<8,8,1>UD    g35<8,8,1>UD    { align1 1Q compacted };
>add(8)          g73<1>F         g126<8,8,1>F    g26<8,8,1>F     { align1 1Q compacted };
>add(8)          g76<1>F         g127<8,8,1>F    g31<8,8,1>F     { align1 1Q compacted };
>and(8)          g80<1>UD        g79<8,8,1>UD    g77<8,8,1>UD    { align1 1Q compacted };
>and.nz.f0.0(8)  null<1>UD       g80<8,8,1>UD    g81<8,8,1>UD    { align1 1Q compacted };
>(+f0.0) if(8)   JIP: 120        UIP: 208                        { align1 1Q };
>   END B94 ->B95 ->B96
>   START B95 <-B94 (232 cycles)
>mul(8)          g31<1>F         g73<8,8,1>F     0x3b800000F  /* 0.00390625F */ { align1 1Q };
>mul(8)          g32<1>F         g76<8,8,1>F     0x3b800000F  /* 0.00390625F */ { align1 1Q };
>mov(8)          g33<1>F         g39<8,8,1>UD                    { align1 1Q compacted };
>send(8)         g31<1>UW        g31<8,8,1>UD    0x06438102
>                            sampler MsgDesc: sample_lz SIMD8 Surface = 2 Sampler = 1 mlen 3 rlen 4 { align1 1Q };
>mov(8)          g20<1>F         g31<8,8,1>F                     { align1 1Q compacted };
>mov(8)          g21<1>F         g32<8,8,1>F                     { align1 1Q compacted };
>mov(8)          g22<1>F         g33<8,8,1>F                     { align1 1Q compacted };
>mov(8)          g23<1>F         g34<8,8,1>F                     { align1 1Q compacted };
>else(8)         JIP: 104        UIP: 104                        { align1 1Q };
>   END B95 ->B97
>   START B96 <-B94 (230 cycles)
>mul(8)          g31<1>F         g73<8,8,1>F     0x3b800000F  /* 0.00390625F */ { align1 1Q };
>mul(8)          g32<1>F         g76<8,8,1>F     0x3b800000F  /* 0.00390625F */ { align1 1Q };
>mov(8)          g33<1>F         g39<8,8,1>UD                    { align1 1Q compacted };
>send(8)         g31<1>UW        g31<8,8,1>UD    0x06438203
>                            sampler MsgDesc: sample_lz SIMD8 Surface = 3 Sampler = 2 mlen 3 rlen 4 { align1 1Q };
>mov(8)          g20<1>F         g31<8,8,1>F                     { align1 1Q compacted };
>mov(8)          g21<1>F         g32<8,8,1>F                     { align1 1Q compacted };
>mov(8)          g22<1>F         g33<8,8,1>F                     { align1 1Q compacted };
>mov(8)          g23<1>F         g34<8,8,1>F                     { align1 1Q compacted };
>   END B96 ->B97
>   START B97 <-B96 <-B95 (242 cycles)
>endif(8)        JIP: 640                                        { align1 1Q };
>mov(8)          g31<1>F         g40<8,8,1>F                     { align1 1Q compacted };
>mov(8)          g32<1>F         g44<8,8,1>F                     { align1 1Q compacted };
>mov(8)          g33<1>F         g8.7<0,1,0>F                    { align1 1Q };
>mov(8)          g57<1>UD        0x00000001UD                    { align1 1Q compacted };
>send(8)         g31<1>UW        g31<8,8,1>UD    0x0643a304
>                            sampler MsgDesc: ld_lz SIMD8 Surface = 4 Sampler = 3 mlen 3 rlen 4 { align1 1Q };
>shl(8)          g82<1>D         g34<8,8,1>D     0x00000008UD    { align1 1Q };
>mov(8)          g95<1>D         g31<8,8,1>D                     { align1 1Q compacted };
>mov(8)          g96<1>D         g32<8,8,1>D                     { align1 1Q compacted };
>add(8)          g39<1>D         g33<8,8,1>D     g82<8,8,1>D     { align1 1Q compacted };
>   END B97 ->B98
>   START B99 <-B98 <-B100 (18 cycles)
>cmp.ge.f0.0(8)  null<1>UD       g57<8,8,1>UD    g9.3<0,1,0>UD   { align1 1Q compacted };
>   END B98 ->B99 ->B101
>(+f0.0) break(8) JIP: 192       UIP: 192                        { align1 1Q };
>   END B99 ->B98 ->B100
>   START B100 <-B99 (304 cycles)
>rndd(8)         g83<1>F         g52<8,8,1>F                     { align1 1Q compacted };
>rndd(8)         g84<1>F         g55<8,8,1>F                     { align1 1Q compacted };
>mov(8)          g87<1>F         g95<8,8,1>UD                    { align1 1Q compacted };
>mov(8)          g88<1>F         g96<8,8,1>UD                    { align1 1Q compacted };
>add(8)          g57<1>D         g57<8,8,1>D     1D              { align1 1Q compacted };
>add(8)          g85<1>F         g52<8,8,1>F     -g83<8,8,1>F    { align1 1Q compacted };
>add(8)          g48<1>F         g55<8,8,1>F     -g84<8,8,1>F    { align1 1Q compacted };
>add(8)          g89<1>F         g85<8,8,1>F     g87<8,8,1>F     { align1 1Q compacted };
>add(8)          g90<1>F         g48<8,8,1>F     g88<8,8,1>F     { align1 1Q compacted };
>mul(8)          g52<1>F         g89<8,8,1>F     0x40800000F  /* 4F */ { align1 1Q };
>mul(8)          g55<1>F         g90<8,8,1>F     0x40800000F  /* 4F */ { align1 1Q };
>mov(8)          g37<1>D         g52<8,8,1>F                     { align1 1Q compacted };
>mov(8)          g38<1>D         g55<8,8,1>F                     { align1 1Q compacted };
>send(8)         g31<1>UW        g37<8,8,1>UD    0x0643a304
>                            sampler MsgDesc: ld_lz SIMD8 Surface = 4 Sampler = 3 mlen 3 rlen 4 { align1 1Q };
>shl(8)          g91<1>D         g34<8,8,1>D     0x00000008UD    { align1 1Q };
>mov(8)          g95<1>D         g31<8,8,1>D                     { align1 1Q compacted };
>mov(8)          g96<1>D         g32<8,8,1>D                     { align1 1Q compacted };
>add(8)          g39<1>D         g33<8,8,1>D     g91<8,8,1>D     { align1 1Q compacted };
>while(8)        JIP: -200                                       { align1 1Q };
>   END B100 ->B99
>   START B101 <-B98 (58 cycles)
>rndd(8)         g92<1>F         g52<8,8,1>F                     { align1 1Q compacted };
>rndd(8)         g93<1>F         g55<8,8,1>F                     { align1 1Q compacted };
>mov(8)          g57<1>F         g95<8,8,1>UD                    { align1 1Q compacted };
>mov(8)          g61<1>F         g96<8,8,1>UD                    { align1 1Q compacted };
>and(8)          g101<1>UD       g56<8,8,1>UD    g35<8,8,1>UD    { align1 1Q compacted };
>add(8)          g94<1>F         g52<8,8,1>F     -g92<8,8,1>F    { align1 1Q compacted };
>add(8)          g95<1>F         g55<8,8,1>F     -g93<8,8,1>F    { align1 1Q compacted };
>and(8)          g102<1>UD       g101<8,8,1>UD   g75<8,8,1>UD    { align1 1Q compacted };
>add(8)          g99<1>F         g94<8,8,1>F     g57<8,8,1>F     { align1 1Q compacted };
>add(8)          g100<1>F        g95<8,8,1>F     g61<8,8,1>F     { align1 1Q compacted };
>and.nz.f0.0(8)  null<1>UD       g102<8,8,1>UD   g81<8,8,1>UD    { align1 1Q compacted };
>(+f0.0) if(8)   JIP: 120        UIP: 208                        { align1 1Q };
>   END B101 ->B102 ->B103
>   START B102 <-B101 (232 cycles)
>mul(8)          g31<1>F         g99<8,8,1>F     0x3b800000F  /* 0.00390625F */ { align1 1Q };
>mul(8)          g32<1>F         g100<8,8,1>F    0x3b800000F  /* 0.00390625F */ { align1 1Q };
>mov(8)          g33<1>F         g39<8,8,1>UD                    { align1 1Q compacted };
>send(8)         g31<1>UW        g31<8,8,1>UD    0x06438102
>                            sampler MsgDesc: sample_lz SIMD8 Surface = 2 Sampler = 1 mlen 3 rlen 4 { align1 1Q };
>mov(8)          g27<1>F         g31<8,8,1>F                     { align1 1Q compacted };
>mov(8)          g28<1>F         g32<8,8,1>F                     { align1 1Q compacted };
>mov(8)          g29<1>F         g33<8,8,1>F                     { align1 1Q compacted };
>mov(8)          g30<1>F         g34<8,8,1>F                     { align1 1Q compacted };
>else(8)         JIP: 104        UIP: 104                        { align1 1Q };
>   END B102 ->B104
>   START B103 <-B101 (230 cycles)
>mul(8)          g31<1>F         g99<8,8,1>F     0x3b800000F  /* 0.00390625F */ { align1 1Q };
>mul(8)          g32<1>F         g100<8,8,1>F    0x3b800000F  /* 0.00390625F */ { align1 1Q };
>mov(8)          g33<1>F         g39<8,8,1>UD                    { align1 1Q compacted };
>send(8)         g31<1>UW        g31<8,8,1>UD    0x06438203
>                            sampler MsgDesc: sample_lz SIMD8 Surface = 3 Sampler = 2 mlen 3 rlen 4 { align1 1Q };
>mov(8)          g27<1>F         g31<8,8,1>F                     { align1 1Q compacted };
>mov(8)          g28<1>F         g32<8,8,1>F                     { align1 1Q compacted };
>mov(8)          g29<1>F         g33<8,8,1>F                     { align1 1Q compacted };
>mov(8)          g30<1>F         g34<8,8,1>F                     { align1 1Q compacted };
>   END B103 ->B104
>   START B104 <-B103 <-B102 (2 cycles)
>endif(8)        JIP: 16                                         { align1 1Q };
>   END B104 ->B105
>   START B105 <-B104 <-B75 (38 cycles)
>endif(8)        JIP: 112                                        { align1 1Q };
>lrp(8)          g5<1>F          g25<4,4,1>F     g16<4,4,1>F     g12<4,4,1>F { align16 1Q compacted };
>lrp(8)          g50<1>F         g25<4,4,1>F     g17<4,4,1>F     g13<4,4,1>F { align16 1Q compacted };
>lrp(8)          g105<1>F        g25<4,4,1>F     g18<4,4,1>F     g14<4,4,1>F { align16 1Q compacted };
>lrp(8)          g106<1>F        g25<4,4,1>F     g19<4,4,1>F     g15<4,4,1>F { align16 1Q compacted };
>lrp(8)          g107<1>F        g25<4,4,1>F     g27<4,4,1>F     g20<4,4,1>F { align16 1Q compacted };
>lrp(8)          g108<1>F        g25<4,4,1>F     g28<4,4,1>F     g21<4,4,1>F { align16 1Q compacted };
>lrp(8)          g47<1>F         g25<4,4,1>F     g29<4,4,1>F     g22<4,4,1>F { align16 1Q compacted };
>lrp(8)          g46<1>F         g25<4,4,1>F     g30<4,4,1>F     g23<4,4,1>F { align16 1Q compacted };
>lrp(8)          g98<1>F         g70<4,4,1>F     g107<4,4,1>F    g5<4,4,1>F { align16 1Q compacted };
>lrp(8)          g62<1>F         g70<4,4,1>F     g108<4,4,1>F    g50<4,4,1>F { align16 1Q compacted };
>lrp(8)          g63<1>F         g70<4,4,1>F     g47<4,4,1>F     g105<4,4,1>F { align16 1Q compacted };
>lrp(8)          g69<1>F         g70<4,4,1>F     g46<4,4,1>F     g106<4,4,1>F { align16 1Q compacted };
>   END B105 ->B106
>   START B106 <-B105 <-B69 (2 cycles)
>endif(8)        JIP: 16                                         { align1 1Q };
>   END B106 ->B107
>   START B107 <-B106 <-B60 (4 cycles)
>endif(8)        JIP: 16                                         { align1 1Q };
>else(8)         JIP: 1504       UIP: 1504                       { align1 1Q };
>   END B107 ->B118
>   START B108 <-B54 (18 cycles)
>cmp.nz.f0.0(8)  null<1>D        g66<8,8,1>D     1D              { align1 1Q compacted };
>(+f0.0) if(8)   JIP: 1400       UIP: 1464                       { align1 1Q };
>   END B108 ->B109 ->B116
>   START B109 <-B108 (22 cycles)
>add(8)          g111<1>F        g51<8,8,1>F     g24.3<0,1,0>F   { align1 1Q compacted };
>add(8)          g112<1>F        g65<8,8,1>F     g24.7<0,1,0>F   { align1 1Q compacted };
>cmp.z.f0.0(8)   null<1>D        g67<8,8,1>D     1D              { align1 1Q compacted };
>(+f0.0) if(8)   JIP: 160        UIP: 1328                       { align1 1Q };
>   END B109 ->B110 ->B111
>   START B110 <-B109 (328 cycles)
>rndd(8)         g113<1>F        -g2<8,8,1>F                     { align1 1Q compacted };
>mov(8)          g14<1>D         -g113<8,8,1>F                   { align1 1Q compacted };
>shl(8)          g114<1>D        g36<8,8,1>D     g14<8,8,1>UD    { align1 1Q };
>mov(8)          g115<1>F        g114<8,8,1>D                    { align1 1Q compacted };
>math inv(8)     g116<1>F        g115<8,8,1>F    null<8,8,1>F    { align1 1Q compacted };
>mul(8)          g117<1>F        g111<8,8,1>F    g116<8,8,1>F    { align1 1Q compacted };
>mul(8)          g118<1>F        g112<8,8,1>F    g116<8,8,1>F    { align1 1Q compacted };
>mov(8)          g12<1>D         g117<8,8,1>F                    { align1 1Q compacted };
>mov(8)          g13<1>D         g118<8,8,1>F                    { align1 1Q compacted };
>send(8)         g12<1>UW        g12<8,8,1>UD    0x06427405
>                            sampler MsgDesc: ld SIMD8 Surface = 5 Sampler = 4 mlen 3 rlen 4 { align1 1Q };
>mov(8)          g98<1>D         g12<8,8,1>D                     { align1 1Q compacted };
>mov(8)          g62<1>D         g13<8,8,1>D                     { align1 1Q compacted };
>mov(8)          g63<1>D         g14<8,8,1>D                     { align1 1Q compacted };
>mov(8)          g69<1>D         g15<8,8,1>D                     { align1 1Q compacted };
>else(8)         JIP: 1184       UIP: 1184                       { align1 1Q };
>   END B110 ->B115
>   START B111 <-B109 (36 cycles)
>cmp.g.f0.0(8)   g120<1>F        g2<8,8,1>F      0x3f000000F  /* 0.5F */ { align1 1Q };
>cmp.z.f0.0(8)   g121<1>D        g67<8,8,1>D     2D              { align1 1Q compacted };
>or.nz.f0.0(8)   null<1>UD       g121<8,8,1>UD   g120<8,8,1>UD   { align1 1Q compacted };
>(+f0.0) if(8)   JIP: 152        UIP: 1120                       { align1 1Q };
>   END B111 ->B112 ->B113
>   START B112 <-B111 (382 cycles)
>mov(8)          g12<1>F         0x0VF           /* [0F, 0F, 0F, 0F]VF */ { align1 1Q compacted };
>send(8)         g12<1>UW        g12<8,8,1>UD    0x0222a405
>                            sampler MsgDesc: resinfo SIMD8 Surface = 5 Sampler = 4 mlen 1 rlen 2 { align1 1Q };
>mov(8)          g122<1>F        g12<8,8,1>D                     { align1 1Q compacted };
>mov(8)          g123<1>F        g13<8,8,1>D                     { align1 1Q compacted };
>math inv(8)     g124<1>F        g122<8,8,1>F    null<8,8,1>F    { align1 1Q compacted };
>math inv(8)     g125<1>F        g123<8,8,1>F    null<8,8,1>F    { align1 1Q compacted };
>mul(8)          g3<1>F          g111<8,8,1>F    g124<8,8,1>F    { align1 1Q compacted };
>mul(8)          g4<1>F          g112<8,8,1>F    g125<8,8,1>F    { align1 1Q compacted };
>send(8)         g12<1>UW        g2<8,8,1>UD     0x06422405
>                            sampler MsgDesc: sample_l SIMD8 Surface = 5 Sampler = 4 mlen 3 rlen 4 { align1 1Q };
>mov(8)          g98<1>D         g12<8,8,1>D                     { align1 1Q compacted };
>mov(8)          g62<1>D         g13<8,8,1>D                     { align1 1Q compacted };
>mov(8)          g63<1>D         g14<8,8,1>D                     { align1 1Q compacted };
>mov(8)          g69<1>D         g15<8,8,1>D                     { align1 1Q compacted };
>else(8)         JIP: 984        UIP: 984                        { align1 1Q };
>   END B112 ->B114
>   START B113 <-B111 (740 cycles)
>add(8)          g127<1>F        g111<8,8,1>F    0xbf000000F  /* -0.5F */ { align1 1Q };
>add(8)          g2<1>F          g112<8,8,1>F    0xbf000000F  /* -0.5F */ { align1 1Q };
>mov(8)          g14<1>F         0x0VF           /* [0F, 0F, 0F, 0F]VF */ { align1 1Q compacted };
>frc(8)          g3<1>F          g127<8,8,1>F                    { align1 1Q compacted };
>rndd(8)         g12<1>F         g127<8,8,1>F                    { align1 1Q compacted };
>frc(8)          g4<1>F          g2<8,8,1>F                      { align1 1Q compacted };
>rndd(8)         g13<1>F         g2<8,8,1>F                      { align1 1Q compacted };
>send(8)         g17<1>UW        g14<8,8,1>UD    0x0222a405
>                            sampler MsgDesc: resinfo SIMD8 Surface = 5 Sampler = 4 mlen 1 rlen 2 { align1 1Q };
>mul(8)          g14<1>F         g3<8,8,1>F      g3<8,8,1>F      { align1 1Q compacted };
>add(8)          g16<1>F         -g3<8,8,1>F     0x3f800000F  /* 1F */ { align1 1Q };
>add(8)          g52<1>F         g12<8,8,1>F     0xbf000000F  /* -0.5F */ { align1 1Q };
>add(8)          g73<1>F         g12<8,8,1>F     0x3fc00000F  /* 1.5F */ { align1 1Q };
>mul(8)          g24<1>F         g4<8,8,1>F      g4<8,8,1>F      { align1 1Q compacted };
>add(8)          g26<1>F         -g4<8,8,1>F     0x3f800000F  /* 1F */ { align1 1Q };
>add(8)          g75<1>F         g13<8,8,1>F     0xbf000000F  /* -0.5F */ { align1 1Q };
>add(8)          g77<1>F         g13<8,8,1>F     0x3fc00000F  /* 1.5F */ { align1 1Q };
>mul(8)          g15<1>F         g14<8,8,1>F     g3<8,8,1>F      { align1 1Q compacted };
>mul(8)          g19<1>F         g14<8,8,1>F     0x40c00000F  /* 6F */ { align1 1Q };
>mul(8)          g25<1>F         g24<8,8,1>F     g4<8,8,1>F      { align1 1Q compacted };
>mul(8)          g29<1>F         g24<8,8,1>F     0x40c00000F  /* 6F */ { align1 1Q };
>mul(8)          g27<1>F         g26<8,8,1>F     g26<8,8,1>F     { align1 1Q compacted };
>mul(8)          g66<1>F         g15<8,8,1>F     0x3e2aaaabF  /* 0.166667F */ { align1 1Q };
>mad(8)          g20<1>F         -g19<4,4,1>F    g15<4,4,1>F     g68.0<0,1,0>F { align16 1Q };
>mul(8)          g70<1>F         g25<8,8,1>F     0x3e2aaaabF  /* 0.166667F */ { align1 1Q };
>mad(8)          g30<1>F         -g29<4,4,1>F    g25<4,4,1>F     g68.0<0,1,0>F { align16 1Q };
>mul(8)          g28<1>F         g27<8,8,1>F     g26<8,8,1>F     { align1 1Q compacted };
>add(8)          g21<1>F         g20<8,8,1>F     0x40800000F  /* 4F */ { align1 1Q };
>mad(8)          g32<1>F         g59.7<0,1,0>F   g28<4,4,1>F     g68.0<0,1,0>F { align16 1Q };
>add(8)          g31<1>F         g30<8,8,1>F     0x40800000F  /* 4F */ { align1 1Q };
>mul(8)          g65<1>F         g21<8,8,1>F     0x3e2aaaabF  /* 0.166667F */ { align1 1Q };
>add(8)          g40<1>F         g28<8,8,1>F     g31<8,8,1>F     { align1 1Q compacted };
>mul(8)          g67<1>F         g31<8,8,1>F     0x3e2aaaabF  /* 0.166667F */ { align1 1Q };
>mad(8)          g33<1>F         g32<4,4,1>F     g27<4,4,1>F     -g68.1<0,1,0>F { align16 1Q };
>mul(8)          g41<1>F         g40<8,8,1>F     0x3e2aaaabF  /* 0.166667F */ { align1 1Q };
>mov(8)          g79<1>F         g17<8,8,1>D                     { align1 1Q compacted };
>mov(8)          g80<1>F         g18<8,8,1>D                     { align1 1Q compacted };
>mul(8)          g17<1>F         g16<8,8,1>F     g16<8,8,1>F     { align1 1Q compacted };
>add(8)          g42<1>F         g33<8,8,1>F     g25<8,8,1>F     { align1 1Q compacted };
>math inv(8)     g36<1>F         g41<8,8,1>F     null<8,8,1>F    { align1 1Q compacted };
>math inv(8)     g81<1>F         g79<8,8,1>F     null<8,8,1>F    { align1 1Q compacted };
>math inv(8)     g82<1>F         g80<8,8,1>F     null<8,8,1>F    { align1 1Q compacted };
>mul(8)          g18<1>F         g17<8,8,1>F     g16<8,8,1>F     { align1 1Q compacted };
>mul(8)          g43<1>F         g42<8,8,1>F     0x3e2aaaabF  /* 0.166667F */ { align1 1Q };
>add(8)          g87<1>F         g40<8,8,1>F     g42<8,8,1>F     { align1 1Q compacted };
>mad(8)          g76<1>F         g75<4,4,1>F     g36<4,4,1>F     g67<4,4,1>F { align16 1Q compacted };
>mad(8)          g22<1>F         g59.7<0,1,0>F   g18<4,4,1>F     g68.0<0,1,0>F { align16 1Q };
>add(8)          g34<1>F         g18<8,8,1>F     g21<8,8,1>F     { align1 1Q compacted };
>math inv(8)     g51<1>F         g43<8,8,1>F     null<8,8,1>F    { align1 1Q compacted };
>mul(8)          g88<1>F         g87<8,8,1>F     0x3e2aaaabF  /* 0.166667F */ { align1 1Q };
>mul(8)          g3<1>F          g76<8,8,1>F     g81<8,8,1>F     { align1 1Q compacted };
>mul(8)          g37<1>F         g34<8,8,1>F     0x3e2aaaabF  /* 0.166667F */ { align1 1Q };
>mad(8)          g23<1>F         g22<4,4,1>F     g17<4,4,1>F     -g68.1<0,1,0>F { align16 1Q };
>math inv(8)     g89<1>F         g88<8,8,1>F     null<8,8,1>F    { align1 1Q compacted };
>mad(8)          g35<1>F         g77<4,4,1>F     g51<4,4,1>F     g70<4,4,1>F { align16 1Q compacted };
>mov(8)          g17<1>F         g3<8,8,1>F                      { align1 1Q compacted };
>math inv(8)     g44<1>F         g37<8,8,1>F     null<8,8,1>F    { align1 1Q compacted };
>mul(8)          g90<1>F         g43<8,8,1>F     g89<8,8,1>F     { align1 1Q compacted };
>add(8)          g38<1>F         g23<8,8,1>F     g15<8,8,1>F     { align1 1Q compacted };
>mul(8)          g25<1>F         g35<8,8,1>F     g82<8,8,1>F     { align1 1Q compacted };
>mad(8)          g55<1>F         g52<4,4,1>F     g44<4,4,1>F     g65<4,4,1>F { align16 1Q compacted };
>mul(8)          g39<1>F         g38<8,8,1>F     0x3e2aaaabF  /* 0.166667F */ { align1 1Q };
>add(8)          g83<1>F         g34<8,8,1>F     g38<8,8,1>F     { align1 1Q compacted };
>mov(8)          g27<1>F         g25<8,8,1>F                     { align1 1Q compacted };
>mul(8)          g2<1>F          g55<8,8,1>F     g81<8,8,1>F     { align1 1Q compacted };
>math inv(8)     g45<1>F         g39<8,8,1>F     null<8,8,1>F    { align1 1Q compacted };
>mul(8)          g84<1>F         g83<8,8,1>F     0x3e2aaaabF  /* 0.166667F */ { align1 1Q };
>mov(8)          g24<1>F         g2<8,8,1>F                      { align1 1Q compacted };
>send(8)         g12<1>UW        g2<8,8,1>UD     0x04438405
>                            sampler MsgDesc: sample_lz SIMD8 Surface = 5 Sampler = 4 mlen 2 rlen 4 { align1 1Q };
>math inv(8)     g85<1>F         g84<8,8,1>F     null<8,8,1>F    { align1 1Q compacted };
>mad(8)          g56<1>F         g73<4,4,1>F     g45<4,4,1>F     g66<4,4,1>F { align16 1Q compacted };
>send(8)         g20<1>UW        g24<8,8,1>UD    0x04438405
>                            sampler MsgDesc: sample_lz SIMD8 Surface = 5 Sampler = 4 mlen 2 rlen 4 { align1 1Q };
>mul(8)          g48<1>F         g39<8,8,1>F     g85<8,8,1>F     { align1 1Q compacted };
>mul(8)          g16<1>F         g56<8,8,1>F     g82<8,8,1>F     { align1 1Q compacted };
>mov(8)          g26<1>F         g16<8,8,1>F                     { align1 1Q compacted };
>send(8)         g16<1>UW        g16<8,8,1>UD    0x04438405
>                            sampler MsgDesc: sample_lz SIMD8 Surface = 5 Sampler = 4 mlen 2 rlen 4 { align1 1Q };
>lrp(8)          g92<1>F         g48<4,4,1>F     g16<4,4,1>F     g12<4,4,1>F { align16 1Q compacted };
>lrp(8)          g93<1>F         g48<4,4,1>F     g17<4,4,1>F     g13<4,4,1>F { align16 1Q compacted };
>lrp(8)          g94<1>F         g48<4,4,1>F     g18<4,4,1>F     g14<4,4,1>F { align16 1Q compacted };
>lrp(8)          g95<1>F         g48<4,4,1>F     g19<4,4,1>F     g15<4,4,1>F { align16 1Q compacted };
>send(8)         g12<1>UW        g26<8,8,1>UD    0x04438405
>                            sampler MsgDesc: sample_lz SIMD8 Surface = 5 Sampler = 4 mlen 2 rlen 4 { align1 1Q };
>lrp(8)          g57<1>F         g48<4,4,1>F     g12<4,4,1>F     g20<4,4,1>F { align16 1Q compacted };
>lrp(8)          g61<1>F         g48<4,4,1>F     g13<4,4,1>F     g21<4,4,1>F { align16 1Q compacted };
>lrp(8)          g99<1>F         g48<4,4,1>F     g14<4,4,1>F     g22<4,4,1>F { align16 1Q compacted };
>lrp(8)          g100<1>F        g48<4,4,1>F     g15<4,4,1>F     g23<4,4,1>F { align16 1Q compacted };
>lrp(8)          g98<1>F         g90<4,4,1>F     g57<4,4,1>F     g92<4,4,1>F { align16 1Q compacted };
>lrp(8)          g62<1>F         g90<4,4,1>F     g61<4,4,1>F     g93<4,4,1>F { align16 1Q compacted };
>lrp(8)          g63<1>F         g90<4,4,1>F     g99<4,4,1>F     g94<4,4,1>F { align16 1Q compacted };
>lrp(8)          g69<1>F         g90<4,4,1>F     g100<4,4,1>F    g95<4,4,1>F { align16 1Q compacted };
>   END B113 ->B114
>   START B114 <-B113 <-B112 (2 cycles)
>endif(8)        JIP: 16                                         { align1 1Q };
>   END B114 ->B115
>   START B115 <-B114 <-B110 (4 cycles)
>endif(8)        JIP: 16                                         { align1 1Q };
>else(8)         JIP: 80         UIP: 80                         { align1 1Q };
>   END B115 ->B117
>   START B116 <-B108 (8 cycles)
>mov(8)          g69<1>D         1065353216D                     { align1 1Q };
>mov(8)          g63<1>D         1065353216D                     { align1 1Q };
>mov(8)          g62<1>D         1065353216D                     { align1 1Q };
>mov(8)          g98<1>D         1065353216D                     { align1 1Q };
>   END B116 ->B117
>   START B117 <-B116 <-B115 (2 cycles)
>endif(8)        JIP: 16                                         { align1 1Q };
>   END B117 ->B118
>   START B118 <-B117 <-B107 (20 cycles)
>endif(8)        JIP: 120                                        { align1 1Q };
>and.z.f0.0(8)   null<1>UD       g11.7<0,1,0>UD  0x01000000UD    { align1 1Q };
>(+f0.0) if(8)   JIP: 40         UIP: 40                         { align1 1Q };
>   END B118 ->B119 ->B120
>   START B119 <-B118 (6 cycles)
>mul(8)          g98<1>F         g98<8,8,1>F     g69<8,8,1>F     { align1 1Q compacted };
>mul(8)          g62<1>F         g62<8,8,1>F     g69<8,8,1>F     { align1 1Q compacted };
>mul(8)          g63<1>F         g63<8,8,1>F     g69<8,8,1>F     { align1 1Q compacted };
>   END B119 ->B120
>   START B120 <-B118 <-B119 (10 cycles)
>endif(8)        JIP: 48                                         { align1 1Q };
>mul(8)          g60<1>F         g60<8,8,1>F     g98<8,8,1>F     { align1 1Q compacted };
>mul(8)          g104<1>F        g104<8,8,1>F    g62<8,8,1>F     { align1 1Q compacted };
>mul(8)          g78<1>F         g78<8,8,1>F     g63<8,8,1>F     { align1 1Q compacted };
>mul(8)          g86<1>F         g86<8,8,1>F     g69<8,8,1>F     { align1 1Q compacted };
>   END B120 ->B121
>   START B121 <-B50 <-B120 (2 cycles)
>endif(8)        JIP: 16                                         { align1 1Q };
>   END B121 ->B122
>   START B122 <-B1 <-B121 (38 cycles)
>endif(8)        JIP: 13600                                      { align1 1Q };
>cmp.l.f0.0(8)   g101<1>UD       g9.7<0,1,0>UD   0x00000006UD    { align1 1Q };
>cmp.ge.f0.0(8)  g102<1>UD       g9.7<0,1,0>UD   0x00000002UD    { align1 1Q };
>and.nz.f0.0(8)  null<1>UD       g102<8,8,1>UD   g101<8,8,1>UD   { align1 1Q compacted };
>(+f0.0) if(8)   JIP: 152        UIP: 13496                      { align1 1Q };
>   END B122 ->B123 ->B124
>   START B123 <-B122 (280 cycles)
>add(8)          g5<1>F          g110<8,8,1>F    0x3f000000F  /* 0.5F */ { align1 1Q };
>add(8)          g50<1>F         g109<8,8,1>F    0x3f000000F  /* 0.5F */ { align1 1Q };
>mov(8)          g106<1>D        g5<8,8,1>F                      { align1 1Q compacted };
>mad(8)          g105<1>F        g6.1<0,1,0>F    g6.0<0,1,0>F    g50<4,4,1>F { align16 1Q };
>add(8)          g27<1>D         g106<8,8,1>D    g97<8,8,1>D     { align1 1Q compacted };
>mov(8)          g107<1>D        g105<8,8,1>F                    { align1 1Q compacted };
>add(8)          g28<1>D         g107<8,8,1>D    g58<8,8,1>D     { align1 1Q compacted };
>send(8)         g34<1>UW        g27<8,8,1>UD    0x0413ac0d
>                            sampler MsgDesc: ld_lz SIMD8 Surface = 13 Sampler = 12 mlen 2 rlen 1 { align1 1Q };
>mov(8)          g37<1>D         g34<8,8,1>D                     { align1 1Q compacted };
>mov(8)          g32<1>D         g34<8,8,1>D                     { align1 1Q compacted };
>mov(8)          g33<1>D         g34<8,8,1>D                     { align1 1Q compacted };
>else(8)         JIP: 13360      UIP: 13360                      { align1 1Q };
>   END B123 ->B348
>   START B124 <-B122 (36 cycles)
>cmp.l.f0.0(8)   g108<1>UD       g9.7<0,1,0>UD   0x0000000eUD    { align1 1Q };
>cmp.ge.f0.0(8)  g47<1>UD        g9.7<0,1,0>UD   0x0000000aUD    { align1 1Q };
>and.nz.f0.0(8)  null<1>UD       g47<8,8,1>UD    g108<8,8,1>UD   { align1 1Q compacted };
>(+f0.0) if(8)   JIP: 160        UIP: 13288                      { align1 1Q };
>   END B124 ->B125 ->B126
>   START B125 <-B124 (282 cycles)
>add(8)          g46<1>F         g110<8,8,1>F    0x3f000000F  /* 0.5F */ { align1 1Q };
>add(8)          g111<1>F        g109<8,8,1>F    0x3f000000F  /* 0.5F */ { align1 1Q };
>mov(8)          g113<1>D        g46<8,8,1>F                     { align1 1Q compacted };
>mad(8)          g112<1>F        g6.1<0,1,0>F    g6.0<0,1,0>F    g111<4,4,1>F { align16 1Q };
>add(8)          g28<1>D         g113<8,8,1>D    g97<8,8,1>D     { align1 1Q compacted };
>mov(8)          g114<1>D        g112<8,8,1>F                    { align1 1Q compacted };
>add(8)          g29<1>D         g114<8,8,1>D    g58<8,8,1>D     { align1 1Q compacted };
>send(8)         g2<1>UW         g28<8,8,1>UD    0x0413ac0d
>                            sampler MsgDesc: ld_lz SIMD8 Surface = 13 Sampler = 12 mlen 2 rlen 1 { align1 1Q };
>mov(8)          g37<1>D         g2<8,8,1>D                      { align1 1Q compacted };
>mov(8)          g32<1>D         g2<8,8,1>D                      { align1 1Q compacted };
>mov(8)          g33<1>D         g2<8,8,1>D                      { align1 1Q compacted };
>mov(8)          g34<1>D         g2<8,8,1>D                      { align1 1Q compacted };
>else(8)         JIP: 13144      UIP: 13144                      { align1 1Q };
>   END B125 ->B347
>   START B126 <-B124 (18 cycles)
>cmp.nz.f0.0(8)  null<1>D        g9.7<0,1,0>D    1D              { align1 1Q };
>(+f0.0) if(8)   JIP: 13032      UIP: 13096                      { align1 1Q };
>   END B126 ->B127 ->B345
>   START B127 <-B126 (18 cycles)
>cmp.nz.f0.0(8)  null<1>D        g9.7<0,1,0>D    18D             { align1 1Q };
>(+f0.0) if(8)   JIP: 12904      UIP: 12968                      { align1 1Q };
>   END B127 ->B128 ->B343
>   START B128 <-B127 (18 cycles)
>cmp.z.f0.0(8)   null<1>D        g9.7<0,1,0>D    19D             { align1 1Q };
>(+f0.0) if(8)   JIP: 160        UIP: 12840                      { align1 1Q };
>   END B128 ->B129 ->B130
>   START B129 <-B128 (282 cycles)
>add(8)          g115<1>F        g110<8,8,1>F    0x3f000000F  /* 0.5F */ { align1 1Q };
>add(8)          g116<1>F        g109<8,8,1>F    0x3f000000F  /* 0.5F */ { align1 1Q };
>mov(8)          g118<1>D        g115<8,8,1>F                    { align1 1Q compacted };
>mad(8)          g117<1>F        g6.1<0,1,0>F    g6.0<0,1,0>F    g116<4,4,1>F { align16 1Q };
>add(8)          g29<1>D         g118<8,8,1>D    g97<8,8,1>D     { align1 1Q compacted };
>mov(8)          g119<1>D        g117<8,8,1>F                    { align1 1Q compacted };
>add(8)          g30<1>D         g119<8,8,1>D    g58<8,8,1>D     { align1 1Q compacted };
>send(8)         g3<1>UW         g29<8,8,1>UD    0x0413ac0d
>                            sampler MsgDesc: ld_lz SIMD8 Surface = 13 Sampler = 12 mlen 2 rlen 1 { align1 1Q };
>mov(8)          g37<1>D         g3<8,8,1>D                      { align1 1Q compacted };
>mov(8)          g32<1>D         g3<8,8,1>D                      { align1 1Q compacted };
>mov(8)          g33<1>D         g3<8,8,1>D                      { align1 1Q compacted };
>mov(8)          g34<1>D         g3<8,8,1>D                      { align1 1Q compacted };
>else(8)         JIP: 12696      UIP: 12696                      { align1 1Q };
>   END B129 ->B342
>   START B130 <-B128 (18 cycles)
>cmp.z.f0.0(8)   null<1>D        g9.7<0,1,0>D    20D             { align1 1Q };
>(+f0.0) if(8)   JIP: 1584       UIP: 12648                      { align1 1Q };
>   END B130 ->B131 ->B156
>   START B131 <-B130 (90 cycles)
>mov(8)          g120<1>UD       g71<8,8,1>F                     { align1 1Q compacted };
>mov(8)          g121<1>UD       g53<8,8,1>F                     { align1 1Q compacted };
>add(8)          g122<1>F        g103<8,8,1>F    0x3f000000F  /* 0.5F */ { align1 1Q };
>add(8)          g123<1>F        g49<8,8,1>F     0x3f000000F  /* 0.5F */ { align1 1Q };
>mov(8)          g124<1>D        g122<8,8,1>F                    { align1 1Q compacted };
>mov(8)          g125<1>D        g123<8,8,1>F                    { align1 1Q compacted };
>add(8)          g126<1>D        g124<8,8,1>D    -1D             { align1 1Q compacted };
>mov(8)          g2<1>F          g124<8,8,1>D                    { align1 1Q compacted };
>add(8)          g127<1>D        g125<8,8,1>D    -1D             { align1 1Q compacted };
>mov(8)          g3<1>F          g125<8,8,1>D                    { align1 1Q compacted };
>add(8)          g4<1>F          g122<8,8,1>F    -g2<8,8,1>F     { align1 1Q compacted };
>sel.l(8)        g12<1>D         g126<8,8,1>D    g127<8,8,1>D    { align1 1Q compacted };
>add(8)          g11<1>F         g123<8,8,1>F    -g3<8,8,1>F     { align1 1Q compacted };
>cmp.ge.f0.0(8)  null<1>D        g12<8,8,1>D     0D              { align1 1Q compacted };
>(+f0.0) if(8)   JIP: 296        UIP: 304                        { align1 1Q };
>   END B131 ->B132 ->B136
>   START B132 <-B131 (36 cycles)
>cmp.ge.f0.0(8)  g13<1>UD        g127<8,8,1>UD   g121<8,8,1>UD   { align1 1Q compacted };
>cmp.ge.f0.0(8)  g14<1>UD        g126<8,8,1>UD   g120<8,8,1>UD   { align1 1Q compacted };
>or.nz.f0.0(8)   null<1>UD       g14<8,8,1>UD    g13<8,8,1>UD    { align1 1Q compacted };
>(+f0.0) if(8)   JIP: 40         UIP: 224                        { align1 1Q };
>   END B132 ->B133 ->B134
>   START B133 <-B132 (4 cycles)
>mov(8)          g61<1>UD        0x00000000UD                    { align1 1Q compacted };
>else(8)         JIP: 200        UIP: 200                        { align1 1Q };
>   END B133 ->B135
>   START B134 <-B132 (404 cycles)
>shr(8)          g15<1>UD        g126<8,8,1>UD   0x00000001UD    { align1 1Q compacted };
>shr(8)          g17<1>UD        g127<8,8,1>UD   0x00000001UD    { align1 1Q compacted };
>add(8)          g18<1>D         g120<8,8,1>D    1D              { align1 1Q compacted };
>add(8)          g16<1>D         g7.3<0,1,0>D    g15<8,8,1>D     { align1 1Q compacted };
>shr(8)          g19<1>UD        g18<8,8,1>UD    0x00000001UD    { align1 1Q compacted };
>mul(8)          g20<1>D         g17<8,8,1>D     g19<8,8,1>D     { align1 1Q compacted };
>add(8)          g21<1>D         g16<8,8,1>D     g20<8,8,1>D     { align1 1Q compacted };
>shl(8)          g2<1>D          g21<8,8,1>D     0x00000002UD    { align1 1Q };
>send(8)         g22<1>UW        g2<8,8,1>UD     0x02106e10
>                            dp data 1 MsgDesc: ( untyped surface read, Surface = 16, SIMD8, Mask = 0xe) mlen 1 rlen 1 { align1 1Q };
>and.nz.f0.0(8)  null<1>UD       g126<8,8,1>UD   0x00000001UD    { align1 1Q compacted };
>(-f0.0) sel(8)  g23<1>UD        g64<8,8,1>UD    0x00000008UD    { align1 1Q };
>and.nz.f0.0(8)  null<1>UD       g127<8,8,1>UD   0x00000001UD    { align1 1Q compacted };
>(-f0.0) sel(8)  g24<1>UD        g64<8,8,1>UD    0x00000010UD    { align1 1Q };
>add(8)          g25<1>D         g23<8,8,1>D     g24<8,8,1>D     { align1 1Q compacted };
>add(8)          g26<1>D         -g25<8,8,1>D    24D             { align1 1Q compacted };
>shl(8)          g27<1>D         g22<8,8,1>D     g26<8,8,1>UD    { align1 1Q };
>mov(8)          g61<1>UD        g27.3<32,8,4>UB                 { align1 1Q };
>   END B134 ->B135
>   START B135 <-B134 <-B133 (4 cycles)
>endif(8)        JIP: 16                                         { align1 1Q };
>else(8)         JIP: 24         UIP: 24                         { align1 1Q };
>   END B135 ->B137
>   START B136 <-B131 (2 cycles)
>mov(8)          g61<1>UD        0x00000000UD                    { align1 1Q compacted };
>   END B136 ->B137
>   START B137 <-B136 <-B135 (36 cycles)
>endif(8)        JIP: 1120                                       { align1 1Q };
>sel.l(8)        g28<1>D         g126<8,8,1>D    g125<8,8,1>D    { align1 1Q compacted };
>cmp.ge.f0.0(8)  null<1>D        g28<8,8,1>D     0D              { align1 1Q compacted };
>(+f0.0) if(8)   JIP: 296        UIP: 304                        { align1 1Q };
>   END B137 ->B138 ->B142
>   START B138 <-B137 (36 cycles)
>cmp.ge.f0.0(8)  g29<1>UD        g125<8,8,1>UD   g121<8,8,1>UD   { align1 1Q compacted };
>cmp.ge.f0.0(8)  g30<1>UD        g126<8,8,1>UD   g120<8,8,1>UD   { align1 1Q compacted };
>or.nz.f0.0(8)   null<1>UD       g30<8,8,1>UD    g29<8,8,1>UD    { align1 1Q compacted };
>(+f0.0) if(8)   JIP: 40         UIP: 224                        { align1 1Q };
>   END B138 ->B139 ->B140
>   START B139 <-B138 (4 cycles)
>mov(8)          g99<1>UD        0x00000000UD                    { align1 1Q compacted };
>else(8)         JIP: 200        UIP: 200                        { align1 1Q };
>   END B139 ->B141
>   START B140 <-B138 (404 cycles)
>shr(8)          g31<1>UD        g126<8,8,1>UD   0x00000001UD    { align1 1Q compacted };
>shr(8)          g39<1>UD        g125<8,8,1>UD   0x00000001UD    { align1 1Q compacted };
>add(8)          g40<1>D         g120<8,8,1>D    1D              { align1 1Q compacted };
>add(8)          g38<1>D         g7.3<0,1,0>D    g31<8,8,1>D     { align1 1Q compacted };
>shr(8)          g41<1>UD        g40<8,8,1>UD    0x00000001UD    { align1 1Q compacted };
>mul(8)          g42<1>D         g39<8,8,1>D     g41<8,8,1>D     { align1 1Q compacted };
>add(8)          g43<1>D         g38<8,8,1>D     g42<8,8,1>D     { align1 1Q compacted };
>shl(8)          g3<1>D          g43<8,8,1>D     0x00000002UD    { align1 1Q };
>send(8)         g44<1>UW        g3<8,8,1>UD     0x02106e10
>                            dp data 1 MsgDesc: ( untyped surface read, Surface = 16, SIMD8, Mask = 0xe) mlen 1 rlen 1 { align1 1Q };
>and.nz.f0.0(8)  null<1>UD       g126<8,8,1>UD   0x00000001UD    { align1 1Q compacted };
>(-f0.0) sel(8)  g45<1>UD        g64<8,8,1>UD    0x00000008UD    { align1 1Q };
>and.nz.f0.0(8)  null<1>UD       g125<8,8,1>UD   0x00000001UD    { align1 1Q compacted };
>(-f0.0) sel(8)  g110<1>UD       g64<8,8,1>UD    0x00000010UD    { align1 1Q };
>add(8)          g109<1>D        g45<8,8,1>D     g110<8,8,1>D    { align1 1Q compacted };
>add(8)          g36<1>D         -g109<8,8,1>D   24D             { align1 1Q compacted };
>shl(8)          g97<1>D         g44<8,8,1>D     g36<8,8,1>UD    { align1 1Q };
>mov(8)          g99<1>UD        g97.3<32,8,4>UB                 { align1 1Q };
>   END B140 ->B141
>   START B141 <-B140 <-B139 (4 cycles)
>endif(8)        JIP: 16                                         { align1 1Q };
>else(8)         JIP: 24         UIP: 24                         { align1 1Q };
>   END B141 ->B143
>   START B142 <-B137 (2 cycles)
>mov(8)          g99<1>UD        0x00000000UD                    { align1 1Q compacted };
>   END B142 ->B143
>   START B143 <-B142 <-B141 (36 cycles)
>endif(8)        JIP: 784                                        { align1 1Q };
>sel.l(8)        g58<1>D         g124<8,8,1>D    g127<8,8,1>D    { align1 1Q compacted };
>cmp.ge.f0.0(8)  null<1>D        g58<8,8,1>D     0D              { align1 1Q compacted };
>(+f0.0) if(8)   JIP: 296        UIP: 304                        { align1 1Q };
>   END B143 ->B144 ->B148
>   START B144 <-B143 (36 cycles)
>cmp.ge.f0.0(8)  g98<1>UD        g127<8,8,1>UD   g121<8,8,1>UD   { align1 1Q compacted };
>cmp.ge.f0.0(8)  g62<1>UD        g124<8,8,1>UD   g120<8,8,1>UD   { align1 1Q compacted };
>or.nz.f0.0(8)   null<1>UD       g62<8,8,1>UD    g98<8,8,1>UD    { align1 1Q compacted };
>(+f0.0) if(8)   JIP: 40         UIP: 224                        { align1 1Q };
>   END B144 ->B145 ->B146
>   START B145 <-B144 (4 cycles)
>mov(8)          g100<1>UD       0x00000000UD                    { align1 1Q compacted };
>else(8)         JIP: 200        UIP: 200                        { align1 1Q };
>   END B145 ->B147
>   START B146 <-B144 (404 cycles)
>shr(8)          g63<1>UD        g124<8,8,1>UD   0x00000001UD    { align1 1Q compacted };
>shr(8)          g65<1>UD        g127<8,8,1>UD   0x00000001UD    { align1 1Q compacted };
>add(8)          g66<1>D         g120<8,8,1>D    1D              { align1 1Q compacted };
>add(8)          g51<1>D         g7.3<0,1,0>D    g63<8,8,1>D     { align1 1Q compacted };
>shr(8)          g67<1>UD        g66<8,8,1>UD    0x00000001UD    { align1 1Q compacted };
>mul(8)          g69<1>D         g65<8,8,1>D     g67<8,8,1>D     { align1 1Q compacted };
>add(8)          g70<1>D         g51<8,8,1>D     g69<8,8,1>D     { align1 1Q compacted };
>shl(8)          g12<1>D         g70<8,8,1>D     0x00000002UD    { align1 1Q };
>send(8)         g52<1>UW        g12<8,8,1>UD    0x02106e10
>                            dp data 1 MsgDesc: ( untyped surface read, Surface = 16, SIMD8, Mask = 0xe) mlen 1 rlen 1 { align1 1Q };
>and.nz.f0.0(8)  null<1>UD       g124<8,8,1>UD   0x00000001UD    { align1 1Q compacted };
>(-f0.0) sel(8)  g55<1>UD        g64<8,8,1>UD    0x00000008UD    { align1 1Q };
>and.nz.f0.0(8)  null<1>UD       g127<8,8,1>UD   0x00000001UD    { align1 1Q compacted };
>(-f0.0) sel(8)  g73<1>UD        g64<8,8,1>UD    0x00000010UD    { align1 1Q };
>add(8)          g56<1>D         g55<8,8,1>D     g73<8,8,1>D     { align1 1Q compacted };
>add(8)          g75<1>D         -g56<8,8,1>D    24D             { align1 1Q compacted };
>shl(8)          g76<1>D         g52<8,8,1>D     g75<8,8,1>UD    { align1 1Q };
>mov(8)          g100<1>UD       g76.3<32,8,4>UB                 { align1 1Q };
>   END B146 ->B147
>   START B147 <-B146 <-B145 (4 cycles)
>endif(8)        JIP: 16                                         { align1 1Q };
>else(8)         JIP: 24         UIP: 24                         { align1 1Q };
>   END B147 ->B149
>   START B148 <-B143 (2 cycles)
>mov(8)          g100<1>UD       0x00000000UD                    { align1 1Q compacted };
>   END B148 ->B149
>   START B149 <-B148 <-B147 (36 cycles)
>endif(8)        JIP: 448                                        { align1 1Q };
>sel.l(8)        g77<1>D         g124<8,8,1>D    g125<8,8,1>D    { align1 1Q compacted };
>cmp.ge.f0.0(8)  null<1>D        g77<8,8,1>D     0D              { align1 1Q compacted };
>(+f0.0) if(8)   JIP: 296        UIP: 304                        { align1 1Q };
>   END B149 ->B150 ->B154
>   START B150 <-B149 (36 cycles)
>cmp.ge.f0.0(8)  g35<1>UD        g125<8,8,1>UD   g121<8,8,1>UD   { align1 1Q compacted };
>cmp.ge.f0.0(8)  g79<1>UD        g124<8,8,1>UD   g120<8,8,1>UD   { align1 1Q compacted };
>or.nz.f0.0(8)   null<1>UD       g79<8,8,1>UD    g35<8,8,1>UD    { align1 1Q compacted };
>(+f0.0) if(8)   JIP: 40         UIP: 224                        { align1 1Q };
>   END B150 ->B151 ->B152
>   START B151 <-B150 (4 cycles)
>mov(8)          g101<1>UD       0x00000000UD                    { align1 1Q compacted };
>else(8)         JIP: 200        UIP: 200                        { align1 1Q };
>   END B151 ->B153
>   START B152 <-B150 (404 cycles)
>shr(8)          g80<1>UD        g124<8,8,1>UD   0x00000001UD    { align1 1Q compacted };
>shr(8)          g82<1>UD        g125<8,8,1>UD   0x00000001UD    { align1 1Q compacted };
>add(8)          g83<1>D         g120<8,8,1>D    1D              { align1 1Q compacted };
>add(8)          g81<1>D         g7.3<0,1,0>D    g80<8,8,1>D     { align1 1Q compacted };
>shr(8)          g84<1>UD        g83<8,8,1>UD    0x00000001UD    { align1 1Q compacted };
>mul(8)          g85<1>D         g82<8,8,1>D     g84<8,8,1>D     { align1 1Q compacted };
>add(8)          g48<1>D         g81<8,8,1>D     g85<8,8,1>D     { align1 1Q compacted };
>shl(8)          g13<1>D         g48<8,8,1>D     0x00000002UD    { align1 1Q };
>send(8)         g87<1>UW        g13<8,8,1>UD    0x02106e10
>                            dp data 1 MsgDesc: ( untyped surface read, Surface = 16, SIMD8, Mask = 0xe) mlen 1 rlen 1 { align1 1Q };
>and.nz.f0.0(8)  null<1>UD       g124<8,8,1>UD   0x00000001UD    { align1 1Q compacted };
>(-f0.0) sel(8)  g88<1>UD        g64<8,8,1>UD    0x00000008UD    { align1 1Q };
>and.nz.f0.0(8)  null<1>UD       g125<8,8,1>UD   0x00000001UD    { align1 1Q compacted };
>(-f0.0) sel(8)  g89<1>UD        g64<8,8,1>UD    0x00000010UD    { align1 1Q };
>add(8)          g90<1>D         g88<8,8,1>D     g89<8,8,1>D     { align1 1Q compacted };
>add(8)          g91<1>D         -g90<8,8,1>D    24D             { align1 1Q compacted };
>shl(8)          g92<1>D         g87<8,8,1>D     g91<8,8,1>UD    { align1 1Q };
>mov(8)          g101<1>UD       g92.3<32,8,4>UB                 { align1 1Q };
>   END B152 ->B153
>   START B153 <-B152 <-B151 (4 cycles)
>endif(8)        JIP: 16                                         { align1 1Q };
>else(8)         JIP: 24         UIP: 24                         { align1 1Q };
>   END B153 ->B155
>   START B154 <-B149 (2 cycles)
>mov(8)          g101<1>UD       0x00000000UD                    { align1 1Q compacted };
>   END B154 ->B155
>   START B155 <-B154 <-B153 (80 cycles)
>endif(8)        JIP: 112                                        { align1 1Q };
>mov(8)          g93<1>F         g61<8,8,1>UD                    { align1 1Q compacted };
>mov(8)          g94<1>F         g99<8,8,1>UD                    { align1 1Q compacted };
>mov(8)          g96<1>F         g100<8,8,1>UD                   { align1 1Q compacted };
>mov(8)          g57<1>F         g101<8,8,1>UD                   { align1 1Q compacted };
>lrp(8)          g95<1>F         g11<4,4,1>F     g94<4,4,1>F     g93<4,4,1>F { align16 1Q compacted };
>lrp(8)          g61<1>F         g11<4,4,1>F     g57<4,4,1>F     g96<4,4,1>F { align16 1Q compacted };
>lrp(8)          g99<1>F         g4<4,4,1>F      g61<4,4,1>F     g95<4,4,1>F { align16 1Q compacted };
>mul(8)          g37<1>F         g99<8,8,1>F     0x3b808081F  /* 0.00392157F */ { align1 1Q };
>mov(8)          g32<1>D         g37<8,8,1>D                     { align1 1Q compacted };
>mov(8)          g33<1>D         g37<8,8,1>D                     { align1 1Q compacted };
>mov(8)          g34<1>D         g37<8,8,1>D                     { align1 1Q compacted };
>else(8)         JIP: 11080      UIP: 11080                      { align1 1Q };
>   END B155 ->B341
>   START B156 <-B130 (18 cycles)
>cmp.z.f0.0(8)   null<1>D        g9.7<0,1,0>D    21D             { align1 1Q };
>mov(1)          g68.4<1>F       0x3f800000F      /* 1F */       { align1 WE_all 1N };
>(+f0.0) if(8)   JIP: 1664       UIP: 11016                      { align1 1Q };
>   END B156 ->B157 ->B182
>   START B157 <-B156 (90 cycles)
>mov(8)          g100<1>UD       g71<8,8,1>F                     { align1 1Q compacted };
>mov(8)          g101<1>UD       g53<8,8,1>F                     { align1 1Q compacted };
>add(8)          g102<1>F        g103<8,8,1>F    0x3f000000F  /* 0.5F */ { align1 1Q };
>add(8)          g5<1>F          g49<8,8,1>F     0x3f000000F  /* 0.5F */ { align1 1Q };
>mov(8)          g106<1>D        g102<8,8,1>F                    { align1 1Q compacted };
>mov(8)          g107<1>D        g5<8,8,1>F                      { align1 1Q compacted };
>add(8)          g108<1>D        g106<8,8,1>D    -1D             { align1 1Q compacted };
>mov(8)          g46<1>F         g106<8,8,1>D                    { align1 1Q compacted };
>add(8)          g47<1>D         g107<8,8,1>D    -1D             { align1 1Q compacted };
>mov(8)          g111<1>F        g107<8,8,1>D                    { align1 1Q compacted };
>add(8)          g112<1>F        g102<8,8,1>F    -g46<8,8,1>F    { align1 1Q compacted };
>sel.l(8)        g114<1>D        g108<8,8,1>D    g47<8,8,1>D     { align1 1Q compacted };
>add(8)          g113<1>F        g5<8,8,1>F      -g111<8,8,1>F   { align1 1Q compacted };
>cmp.ge.f0.0(8)  null<1>D        g114<8,8,1>D    0D              { align1 1Q compacted };
>(+f0.0) if(8)   JIP: 296        UIP: 304                        { align1 1Q };
>   END B157 ->B158 ->B162
>   START B158 <-B157 (36 cycles)
>cmp.ge.f0.0(8)  g115<1>UD       g47<8,8,1>UD    g101<8,8,1>UD   { align1 1Q compacted };
>cmp.ge.f0.0(8)  g116<1>UD       g108<8,8,1>UD   g100<8,8,1>UD   { align1 1Q compacted };
>or.nz.f0.0(8)   null<1>UD       g116<8,8,1>UD   g115<8,8,1>UD   { align1 1Q compacted };
>(+f0.0) if(8)   JIP: 40         UIP: 224                        { align1 1Q };
>   END B158 ->B159 ->B160
>   START B159 <-B158 (4 cycles)
>mov(8)          g102<1>UD       0x00000000UD                    { align1 1Q compacted };
>else(8)         JIP: 200        UIP: 200                        { align1 1Q };
>   END B159 ->B161
>   START B160 <-B158 (404 cycles)
>shr(8)          g117<1>UD       g108<8,8,1>UD   0x00000001UD    { align1 1Q compacted };
>shr(8)          g119<1>UD       g47<8,8,1>UD    0x00000001UD    { align1 1Q compacted };
>add(8)          g120<1>D        g100<8,8,1>D    1D              { align1 1Q compacted };
>add(8)          g118<1>D        g7.3<0,1,0>D    g117<8,8,1>D    { align1 1Q compacted };
>shr(8)          g121<1>UD       g120<8,8,1>UD   0x00000001UD    { align1 1Q compacted };
>mul(8)          g122<1>D        g119<8,8,1>D    g121<8,8,1>D    { align1 1Q compacted };
>add(8)          g123<1>D        g118<8,8,1>D    g122<8,8,1>D    { align1 1Q compacted };
>shl(8)          g14<1>D         g123<8,8,1>D    0x00000002UD    { align1 1Q };
>send(8)         g124<1>UW       g14<8,8,1>UD    0x02106e10
>                            dp data 1 MsgDesc: ( untyped surface read, Surface = 16, SIMD8, Mask = 0xe) mlen 1 rlen 1 { align1 1Q };
>and.nz.f0.0(8)  null<1>UD       g108<8,8,1>UD   0x00000001UD    { align1 1Q compacted };
>(-f0.0) sel(8)  g125<1>UD       g64<8,8,1>UD    0x00000008UD    { align1 1Q };
>and.nz.f0.0(8)  null<1>UD       g47<8,8,1>UD    0x00000001UD    { align1 1Q compacted };
>(-f0.0) sel(8)  g126<1>UD       g64<8,8,1>UD    0x00000010UD    { align1 1Q };
>add(8)          g127<1>D        g125<8,8,1>D    g126<8,8,1>D    { align1 1Q compacted };
>add(8)          g2<1>D          -g127<8,8,1>D   24D             { align1 1Q compacted };
>shl(8)          g3<1>D          g124<8,8,1>D    g2<8,8,1>UD     { align1 1Q };
>mov(8)          g102<1>UD       g3.3<32,8,4>UB                  { align1 1Q };
>   END B160 ->B161
>   START B161 <-B160 <-B159 (4 cycles)
>endif(8)        JIP: 16                                         { align1 1Q };
>else(8)         JIP: 24         UIP: 24                         { align1 1Q };
>   END B161 ->B163
>   START B162 <-B157 (2 cycles)
>mov(8)          g102<1>UD       0x00000000UD                    { align1 1Q compacted };
>   END B162 ->B163
>   START B163 <-B162 <-B161 (36 cycles)
>endif(8)        JIP: 1200                                       { align1 1Q };
>sel.l(8)        g4<1>D          g108<8,8,1>D    g107<8,8,1>D    { align1 1Q compacted };
>cmp.ge.f0.0(8)  null<1>D        g4<8,8,1>D      0D              { align1 1Q compacted };
>(+f0.0) if(8)   JIP: 296        UIP: 304                        { align1 1Q };
>   END B163 ->B164 ->B168
>   START B164 <-B163 (36 cycles)
>cmp.ge.f0.0(8)  g11<1>UD        g107<8,8,1>UD   g101<8,8,1>UD   { align1 1Q compacted };
>cmp.ge.f0.0(8)  g12<1>UD        g108<8,8,1>UD   g100<8,8,1>UD   { align1 1Q compacted };
>or.nz.f0.0(8)   null<1>UD       g12<8,8,1>UD    g11<8,8,1>UD    { align1 1Q compacted };
>(+f0.0) if(8)   JIP: 40         UIP: 224                        { align1 1Q };
>   END B164 ->B165 ->B166
>   START B165 <-B164 (4 cycles)
>mov(8)          g5<1>UD         0x00000000UD                    { align1 1Q compacted };
>else(8)         JIP: 200        UIP: 200                        { align1 1Q };
>   END B165 ->B167
>   START B166 <-B164 (404 cycles)
>shr(8)          g13<1>UD        g108<8,8,1>UD   0x00000001UD    { align1 1Q compacted };
>shr(8)          g15<1>UD        g107<8,8,1>UD   0x00000001UD    { align1 1Q compacted };
>add(8)          g16<1>D         g100<8,8,1>D    1D              { align1 1Q compacted };
>add(8)          g14<1>D         g7.3<0,1,0>D    g13<8,8,1>D     { align1 1Q compacted };
>shr(8)          g17<1>UD        g16<8,8,1>UD    0x00000001UD    { align1 1Q compacted };
>mul(8)          g18<1>D         g15<8,8,1>D     g17<8,8,1>D     { align1 1Q compacted };
>add(8)          g19<1>D         g14<8,8,1>D     g18<8,8,1>D     { align1 1Q compacted };
>shl(8)          g15<1>D         g19<8,8,1>D     0x00000002UD    { align1 1Q };
>send(8)         g20<1>UW        g15<8,8,1>UD    0x02106e10
>                            dp data 1 MsgDesc: ( untyped surface read, Surface = 16, SIMD8, Mask = 0xe) mlen 1 rlen 1 { align1 1Q };
>and.nz.f0.0(8)  null<1>UD       g108<8,8,1>UD   0x00000001UD    { align1 1Q compacted };
>(-f0.0) sel(8)  g21<1>UD        g64<8,8,1>UD    0x00000008UD    { align1 1Q };
>and.nz.f0.0(8)  null<1>UD       g107<8,8,1>UD   0x00000001UD    { align1 1Q compacted };
>(-f0.0) sel(8)  g22<1>UD        g64<8,8,1>UD    0x00000010UD    { align1 1Q };
>add(8)          g23<1>D         g21<8,8,1>D     g22<8,8,1>D     { align1 1Q compacted };
>add(8)          g24<1>D         -g23<8,8,1>D    24D             { align1 1Q compacted };
>shl(8)          g25<1>D         g20<8,8,1>D     g24<8,8,1>UD    { align1 1Q };
>mov(8)          g5<1>UD         g25.3<32,8,4>UB                 { align1 1Q };
>   END B166 ->B167
>   START B167 <-B166 <-B165 (4 cycles)
>endif(8)        JIP: 16                                         { align1 1Q };
>else(8)         JIP: 24         UIP: 24                         { align1 1Q };
>   END B167 ->B169
>   START B168 <-B163 (2 cycles)
>mov(8)          g5<1>UD         0x00000000UD                    { align1 1Q compacted };
>   END B168 ->B169
>   START B169 <-B168 <-B167 (36 cycles)
>endif(8)        JIP: 864                                        { align1 1Q };
>sel.l(8)        g26<1>D         g106<8,8,1>D    g47<8,8,1>D     { align1 1Q compacted };
>cmp.ge.f0.0(8)  null<1>D        g26<8,8,1>D     0D              { align1 1Q compacted };
>(+f0.0) if(8)   JIP: 296        UIP: 304                        { align1 1Q };
>   END B169 ->B170 ->B174
>   START B170 <-B169 (36 cycles)
>cmp.ge.f0.0(8)  g27<1>UD        g47<8,8,1>UD    g101<8,8,1>UD   { align1 1Q compacted };
>cmp.ge.f0.0(8)  g28<1>UD        g106<8,8,1>UD   g100<8,8,1>UD   { align1 1Q compacted };
>or.nz.f0.0(8)   null<1>UD       g28<8,8,1>UD    g27<8,8,1>UD    { align1 1Q compacted };
>(+f0.0) if(8)   JIP: 40         UIP: 224                        { align1 1Q };
>   END B170 ->B171 ->B172
>   START B171 <-B170 (4 cycles)
>mov(8)          g50<1>UD        0x00000000UD                    { align1 1Q compacted };
>else(8)         JIP: 200        UIP: 200                        { align1 1Q };
>   END B171 ->B173
>   START B172 <-B170 (404 cycles)
>shr(8)          g29<1>UD        g106<8,8,1>UD   0x00000001UD    { align1 1Q compacted };
>shr(8)          g31<1>UD        g47<8,8,1>UD    0x00000001UD    { align1 1Q compacted };
>add(8)          g53<1>D         g100<8,8,1>D    1D              { align1 1Q compacted };
>add(8)          g30<1>D         g7.3<0,1,0>D    g29<8,8,1>D     { align1 1Q compacted };
>shr(8)          g38<1>UD        g53<8,8,1>UD    0x00000001UD    { align1 1Q compacted };
>mul(8)          g39<1>D         g31<8,8,1>D     g38<8,8,1>D     { align1 1Q compacted };
>add(8)          g40<1>D         g30<8,8,1>D     g39<8,8,1>D     { align1 1Q compacted };
>shl(8)          g16<1>D         g40<8,8,1>D     0x00000002UD    { align1 1Q };
>send(8)         g41<1>UW        g16<8,8,1>UD    0x02106e10
>                            dp data 1 MsgDesc: ( untyped surface read, Surface = 16, SIMD8, Mask = 0xe) mlen 1 rlen 1 { align1 1Q };
>and.nz.f0.0(8)  null<1>UD       g106<8,8,1>UD   0x00000001UD    { align1 1Q compacted };
>(-f0.0) sel(8)  g42<1>UD        g64<8,8,1>UD    0x00000008UD    { align1 1Q };
>and.nz.f0.0(8)  null<1>UD       g47<8,8,1>UD    0x00000001UD    { align1 1Q compacted };
>(-f0.0) sel(8)  g43<1>UD        g64<8,8,1>UD    0x00000010UD    { align1 1Q };
>add(8)          g44<1>D         g42<8,8,1>D     g43<8,8,1>D     { align1 1Q compacted };
>add(8)          g45<1>D         -g44<8,8,1>D    24D             { align1 1Q compacted };
>shl(8)          g110<1>D        g41<8,8,1>D     g45<8,8,1>UD    { align1 1Q };
>mov(8)          g50<1>UD        g110.3<32,8,4>UB                { align1 1Q };
>   END B172 ->B173
>   START B173 <-B172 <-B171 (4 cycles)
>endif(8)        JIP: 16                                         { align1 1Q };
>else(8)         JIP: 24         UIP: 24                         { align1 1Q };
>   END B173 ->B175
>   START B174 <-B169 (2 cycles)
>mov(8)          g50<1>UD        0x00000000UD                    { align1 1Q compacted };
>   END B174 ->B175
>   START B175 <-B174 <-B173 (36 cycles)
>endif(8)        JIP: 528                                        { align1 1Q };
>sel.l(8)        g109<1>D        g106<8,8,1>D    g107<8,8,1>D    { align1 1Q compacted };
>cmp.ge.f0.0(8)  null<1>D        g109<8,8,1>D    0D              { align1 1Q compacted };
>(+f0.0) if(8)   JIP: 296        UIP: 304                        { align1 1Q };
>   END B175 ->B176 ->B180
>   START B176 <-B175 (36 cycles)
>cmp.ge.f0.0(8)  g71<1>UD        g107<8,8,1>UD   g101<8,8,1>UD   { align1 1Q compacted };
>cmp.ge.f0.0(8)  g36<1>UD        g106<8,8,1>UD   g100<8,8,1>UD   { align1 1Q compacted };
>or.nz.f0.0(8)   null<1>UD       g36<8,8,1>UD    g71<8,8,1>UD    { align1 1Q compacted };
>(+f0.0) if(8)   JIP: 40         UIP: 224                        { align1 1Q };
>   END B176 ->B177 ->B178
>   START B177 <-B176 (4 cycles)
>mov(8)          g105<1>UD       0x00000000UD                    { align1 1Q compacted };
>else(8)         JIP: 200        UIP: 200                        { align1 1Q };
>   END B177 ->B179
>   START B178 <-B176 (404 cycles)
>shr(8)          g97<1>UD        g106<8,8,1>UD   0x00000001UD    { align1 1Q compacted };
>shr(8)          g98<1>UD        g107<8,8,1>UD   0x00000001UD    { align1 1Q compacted };
>add(8)          g62<1>D         g100<8,8,1>D    1D              { align1 1Q compacted };
>add(8)          g58<1>D         g7.3<0,1,0>D    g97<8,8,1>D     { align1 1Q compacted };
>shr(8)          g63<1>UD        g62<8,8,1>UD    0x00000001UD    { align1 1Q compacted };
>mul(8)          g51<1>D         g98<8,8,1>D     g63<8,8,1>D     { align1 1Q compacted };
>add(8)          g65<1>D         g58<8,8,1>D     g51<8,8,1>D     { align1 1Q compacted };
>shl(8)          g17<1>D         g65<8,8,1>D     0x00000002UD    { align1 1Q };
>send(8)         g66<1>UW        g17<8,8,1>UD    0x02106e10
>                            dp data 1 MsgDesc: ( untyped surface read, Surface = 16, SIMD8, Mask = 0xe) mlen 1 rlen 1 { align1 1Q };
>and.nz.f0.0(8)  null<1>UD       g106<8,8,1>UD   0x00000001UD    { align1 1Q compacted };
>(-f0.0) sel(8)  g67<1>UD        g64<8,8,1>UD    0x00000008UD    { align1 1Q };
>and.nz.f0.0(8)  null<1>UD       g107<8,8,1>UD   0x00000001UD    { align1 1Q compacted };
>(-f0.0) sel(8)  g69<1>UD        g64<8,8,1>UD    0x00000010UD    { align1 1Q };
>add(8)          g70<1>D         g67<8,8,1>D     g69<8,8,1>D     { align1 1Q compacted };
>add(8)          g52<1>D         -g70<8,8,1>D    24D             { align1 1Q compacted };
>shl(8)          g55<1>D         g66<8,8,1>D     g52<8,8,1>UD    { align1 1Q };
>mov(8)          g105<1>UD       g55.3<32,8,4>UB                 { align1 1Q };
>   END B178 ->B179
>   START B179 <-B178 <-B177 (4 cycles)
>endif(8)        JIP: 16                                         { align1 1Q };
>else(8)         JIP: 24         UIP: 24                         { align1 1Q };
>   END B179 ->B181
>   START B180 <-B175 (2 cycles)
>mov(8)          g105<1>UD       0x00000000UD                    { align1 1Q compacted };
>   END B180 ->B181
>   START B181 <-B180 <-B179 (192 cycles)
>endif(8)        JIP: 192                                        { align1 1Q };
>mov(8)          g73<1>F         g102<8,8,1>UD                   { align1 1Q compacted };
>mov(8)          g56<1>F         g5<8,8,1>UD                     { align1 1Q compacted };
>mov(8)          g76<1>F         g50<8,8,1>UD                    { align1 1Q compacted };
>mov(8)          g77<1>F         g105<8,8,1>UD                   { align1 1Q compacted };
>mov(1)          g68.5<1>F       0x3c008081F      /* 0.00784314F */ { align1 WE_all 1N };
>lrp(8)          g75<1>F         g113<4,4,1>F    g56<4,4,1>F     g73<4,4,1>F { align16 1Q compacted };
>lrp(8)          g35<1>F         g113<4,4,1>F    g77<4,4,1>F     g76<4,4,1>F { align16 1Q compacted };
>lrp(8)          g79<1>F         g112<4,4,1>F    g35<4,4,1>F     g75<4,4,1>F { align16 1Q compacted };
>mad(8)          g80<1>F         -g68.4<0,1,0>F  g79<4,4,1>F     g68.5<0,1,0>F { align16 1Q };
>add(8)          g81<1>F         g80.1<4,4,0>F   -g80<4,4,0>F    { align1 1Q compacted };
>mul(8)          g82<1>F         g80<8,8,1>F     g6<0,1,0>F      { align1 1Q compacted };
>add(8)          g83<1>F         -g82<4,4,0>F    g82.2<4,4,0>F   { align1 1Q compacted };
>mul(8)          g84<1>F         g83<8,8,1>F     g83<8,8,1>F     { align1 1Q compacted };
>mad(8)          g85<1>F         g84<4,4,1>F     g81<4,4,1>F     g81<4,4,1>F { align16 1Q compacted };
>math rsq(8)     g48<1>F         g85<8,8,1>F     null<8,8,1>F    { align1 1Q compacted };
>mad.sat(8)      g37<1>F         g59.0<0,1,0>F   g48<4,4,1>F     g80<4,4,1>F { align16 1Q };
>mov(8)          g32<1>D         g37<8,8,1>D                     { align1 1Q compacted };
>mov(8)          g33<1>D         g37<8,8,1>D                     { align1 1Q compacted };
>mov(8)          g34<1>D         g37<8,8,1>D                     { align1 1Q compacted };
>else(8)         JIP: 9368       UIP: 9368                       { align1 1Q };
>   END B181 ->B340
>   START B182 <-B156 (18 cycles)
>cmp.z.f0.0(8)   null<1>D        g9.7<0,1,0>D    22D             { align1 1Q };
>(+f0.0) if(8)   JIP: 5920       UIP: 9320                       { align1 1Q };
>   END B182 ->B183 ->B289
>   START B183 <-B182 (44 cycles)
>and(8)          g106<1>UD       g7.3<0,1,0>UD   0x3fffffffUD    { align1 1Q };
>add(8)          g87<1>F         g103.1<4,4,0>F  -g103<4,4,0>F   { align1 1Q compacted };
>add(8)          g88<1>F         g49.1<4,4,0>F   -g49<4,4,0>F    { align1 1Q compacted };
>mul(8)          g89<1>F         g103<8,8,1>F    g6<0,1,0>F      { align1 1Q compacted };
>mul(8)          g91<1>F         g49<8,8,1>F     g6<0,1,0>F      { align1 1Q compacted };
>and(8)          g93<1>UD        g7.3<0,1,0>UD   0x80000000UD    { align1 1Q };
>shl(8)          g18<1>D         g106<8,8,1>D    0x00000002UD    { align1 1Q };
>add(8)          g90<1>F         -g89<4,4,0>F    g89.2<4,4,0>F   { align1 1Q compacted };
>add(8)          g92<1>F         -g91<4,4,0>F    g91.2<4,4,0>F   { align1 1Q compacted };
>cmp.nz.f0.0(8)  g94<1>D         g93<8,8,1>D     0D              { align1 1Q compacted };
>send(8)         g107<1>UW       g18<8,8,1>UD    0x02106e10
>                            dp data 1 MsgDesc: ( untyped surface read, Surface = 16, SIMD8, Mask = 0xe) mlen 1 rlen 1 { align1 1Q };
>mov(8)          g112<1>D        -989855744D                     { align1 1Q };
>mov(8)          g111<1>D        -989855744D                     { align1 1Q };
>mov(8)          g46<1>D         1157627904D                     { align1 1Q };
>mov(8)          g47<1>D         1157627904D                     { align1 1Q };
>mov(8)          g108<1>D        g106<8,8,1>D                    { align1 1Q compacted };
>   END B183 ->B184
>   START B185 <-B184 <-B189 (18 cycles)
>and.z.f0.0(8)   null<1>UD       g107<8,8,1>UD   0x00000001UD    { align1 1Q compacted };
>   END B184 ->B185 ->B190
>(+f0.0) break(8) JIP: 280       UIP: 280                        { align1 1Q };
>   END B185 ->B184 ->B186
>   START B186 <-B185 (34 cycles)
>shl(8)          g95<1>D         g107<8,8,1>D    0x0000001eUD    { align1 1Q };
>shr.z.f0.0(8)   null<1>UD       g95<8,8,1>UD    0x0000001fUD    { align1 1Q compacted };
>(+f0.0) if(8)   JIP: 80         UIP: 128                        { align1 1Q };
>   END B186 ->B187 ->B188
>   START B187 <-B186 (54 cycles)
>add(8)          g96<1>F         g111<8,8,1>F    g47<8,8,1>F     { align1 1Q compacted };
>mul(8)          g57<1>F         g96<8,8,1>F     0x3f000000F  /* 0.5F */ { align1 1Q };
>cmp.l.f0.0(8)   g113<1>F        g57<8,8,1>F     g103<8,8,1>F    { align1 1Q compacted };
>(+f0.0) sel(8)  g111<1>UD       g57<8,8,1>UD    g111<8,8,1>UD   { align1 1Q compacted };
>(+f0.0) sel(8)  g47<1>UD        g47<8,8,1>UD    g57<8,8,1>UD    { align1 1Q compacted };
>else(8)         JIP: 64         UIP: 64                         { align1 1Q };
>   END B187 ->B189
>   START B188 <-B186 (52 cycles)
>add(8)          g61<1>F         g112<8,8,1>F    g46<8,8,1>F     { align1 1Q compacted };
>mul(8)          g99<1>F         g61<8,8,1>F     0x3f000000F  /* 0.5F */ { align1 1Q };
>cmp.l.f0.0(8)   g113<1>F        g99<8,8,1>F     g49<8,8,1>F     { align1 1Q compacted };
>(+f0.0) sel(8)  g112<1>UD       g99<8,8,1>UD    g112<8,8,1>UD   { align1 1Q compacted };
>(+f0.0) sel(8)  g46<1>UD        g46<8,8,1>UD    g99<8,8,1>UD    { align1 1Q compacted };
>   END B188 ->B189
>   START B189 <-B188 <-B187 (118 cycles)
>endif(8)        JIP: 112                                        { align1 1Q };
>cmp.nz.f0.0(8)  null<1>D        g113<8,8,1>D    0D              { align1 1Q compacted };
>(-f0.0) sel(8)  g100<1>UD       g54<8,8,1>UD    0x00000011UD    { align1 1Q };
>add(8)          g101<1>D        -g100<8,8,1>D   17D             { align1 1Q compacted };
>shl(8)          g102<1>D        g107<8,8,1>D    g101<8,8,1>UD   { align1 1Q };
>shr(8)          g5<1>UD         g102<8,8,1>UD   0x00000011UD    { align1 1Q compacted };
>add(8)          g108<1>D        g5<8,8,1>D      g106<8,8,1>D    { align1 1Q compacted };
>shl(8)          g19<1>D         g108<8,8,1>D    0x00000002UD    { align1 1Q };
>send(8)         g107<1>UW       g19<8,8,1>UD    0x02106e10
>                            dp data 1 MsgDesc: ( untyped surface read, Surface = 16, SIMD8, Mask = 0xe) mlen 1 rlen 1 { align1 1Q };
>while(8)        JIP: -288                                       { align1 1Q };
>   END B189 ->B185
>   START B190 <-B184 (641 cycles)
>shl(8)          g50<1>D         g107<8,8,1>D    0x0000000fUD    { align1 1Q };
>add(8)          g108<1>D        g108<8,8,1>D    1D              { align1 1Q compacted };
>shr(8)          g107<1>UD       g107<8,8,1>UD   0x00000011UD    { align1 1Q compacted };
>mov(8)          g105<1>UD       g50.1<16,8,2>UW                 { align1 1Q };
>shl(8)          g20<1>D         g108<8,8,1>D    0x00000002UD    { align1 1Q };
>send(8)         g113<1>UW       g20<8,8,1>UD    0x02106e10
>                            dp data 1 MsgDesc: ( untyped surface read, Surface = 16, SIMD8, Mask = 0xe) mlen 1 rlen 1 { align1 1Q };
>mul(8)          g127<1>F        g92<8,8,1>F     g92<8,8,1>F     { align1 1Q compacted };
>mul(8)          g3<1>F          g90<8,8,1>F     g92<8,8,1>F     { align1 1Q compacted };
>mul(8)          g11<1>F         g90<8,8,1>F     g90<8,8,1>F     { align1 1Q compacted };
>add(8)          g115<1>D        g105<8,8,1>D    g106<8,8,1>D    { align1 1Q compacted };
>mov(8)          g118<1>D        1123024896D                     { align1 1Q };
>mov(8)          g117<1>D        1123024896D                     { align1 1Q };
>mov(8)          g116<1>UD       0x00000000UD                    { align1 1Q compacted };
>mad(8)          g2<1>F          g127<4,4,1>F    g88<4,4,1>F     g88<4,4,1>F { align16 1Q compacted };
>mad(8)          g4<1>F          g3<4,4,1>F      g88<4,4,1>F     g87<4,4,1>F { align16 1Q compacted };
>mad(8)          g12<1>F         g11<4,4,1>F     g87<4,4,1>F     g87<4,4,1>F { align16 1Q compacted };
>mov(8)          g114<1>F        g113.2<32,8,4>UB                { align1 1Q };
>mov(8)          g119<1>F        g113.3<32,8,4>UB                { align1 1Q };
>mov(8)          g122<1>UD       g113<16,8,2>UW                  { align1 1Q };
>mul(8)          g120<1>F        g114<8,8,1>F    0x3b800000F  /* 0.00390625F */ { align1 1Q };
>mul(8)          g121<1>F        g119<8,8,1>F    0x3b800000F  /* 0.00390625F */ { align1 1Q };
>add(8)          g114<1>D        g122<8,8,1>D    -32768D         { align1 1Q };
>lrp(8)          g123<1>F        g120<4,4,1>F    g47<4,4,1>F     g111<4,4,1>F { align16 1Q compacted };
>lrp(8)          g124<1>F        g121<4,4,1>F    g46<4,4,1>F     g112<4,4,1>F { align16 1Q compacted };
>add(8)          g125<1>F        g123<8,8,1>F    -g103<8,8,1>F   { align1 1Q compacted };
>add(8)          g126<1>F        g124<8,8,1>F    -g49<8,8,1>F    { align1 1Q compacted };
>mul(8)          g22<1>F         g125<8,8,1>F    g88<8,8,1>F     { align1 1Q compacted };
>mul(8)          g24<1>F         g125<8,8,1>F    g92<8,8,1>F     { align1 1Q compacted };
>mul(8)          g13<1>F         g4<8,8,1>F      g126<8,8,1>F    { align1 1Q compacted };
>mul(8)          g15<1>F         g12<8,8,1>F     g126<8,8,1>F    { align1 1Q compacted };
>mad(8)          g23<1>F         g22<4,4,1>F     g87<4,4,1>F     -g126<4,4,1>F { align16 1Q compacted };
>mad(8)          g25<1>F         g24<4,4,1>F     g90<4,4,1>F     -g126<4,4,1>F { align16 1Q compacted };
>mad(8)          g14<1>F         g13<4,4,1>F     g125<4,4,1>F    -g2<4,4,1>F { align16 1Q compacted };
>mad(8)          g16<1>F         -g15<4,4,1>F    g125<4,4,1>F    g4<4,4,1>F { align16 1Q compacted };
>add(8)          g26<1>F         (abs)g23<8,8,1>F (abs)g25<8,8,1>F { align1 1Q compacted };
>mul(8)          g17<1>F         g16<8,8,1>F     g88<8,8,1>F     { align1 1Q compacted };
>mul(8)          g19<1>F         g16<8,8,1>F     g92<8,8,1>F     { align1 1Q compacted };
>sel.ge(8)       g28<1>F         g26<8,8,1>F     0x33d6bf95F  /* 1e-07F */ { align1 1Q };
>mad(8)          g18<1>F         g17<4,4,1>F     g87<4,4,1>F     g14<4,4,1>F { align16 1Q compacted };
>mad(8)          g20<1>F         g19<4,4,1>F     g90<4,4,1>F     g14<4,4,1>F { align16 1Q compacted };
>math inv(8)     g53<1>F         g28<8,8,1>F     null<8,8,1>F    { align1 1Q compacted };
>add(8)          g21<1>F         (abs)g18<8,8,1>F (abs)g20<8,8,1>F { align1 1Q compacted };
>mul(8)          g38<1>F         g126<8,8,1>F    g53<8,8,1>F     { align1 1Q compacted };
>mul(8)          g39<1>F         g125<8,8,1>F    g53<8,8,1>F     { align1 1Q compacted };
>sel.ge(8)       g27<1>F         g21<8,8,1>F     0x33d6bf95F  /* 1e-07F */ { align1 1Q };
>math inv(8)     g29<1>F         g27<8,8,1>F     null<8,8,1>F    { align1 1Q compacted };
>mul(8)          g30<1>F         g14<8,8,1>F     g29<8,8,1>F     { align1 1Q compacted };
>mul(8)          g31<1>F         g16<8,8,1>F     g29<8,8,1>F     { align1 1Q compacted };
>mul(8)          g40<1>F         g31<8,8,1>F     g126<8,8,1>F    { align1 1Q compacted };
>mad.l.f0.0(8)   g41<1>F         g40<4,4,1>F     g125<4,4,1>F    g30<4,4,1>F { align16 1Q };
>(+f0.0) sel(8)  g42<1>F         -g41<8,8,1>F    g41<8,8,1>F     { align1 1Q compacted };
>(+f0.0) sel(8)  g43<1>F         -g30<8,8,1>F    g30<8,8,1>F     { align1 1Q compacted };
>(+f0.0) sel(8)  g44<1>F         -g31<8,8,1>F    g31<8,8,1>F     { align1 1Q compacted };
>mul(8)          g45<1>F         g43<8,8,1>F     g39<8,8,1>F     { align1 1Q compacted };
>mul(8)          g110<1>F        g38<8,8,1>F     g44<8,8,1>F     { align1 1Q compacted };
>cmp.l.f0.0(8)   null<1>F        g45<8,8,1>F     -g110<8,8,1>F   { align1 1Q compacted };
>(+f0.0) sel(8)  g109<1>F        g38<8,8,1>F     -g38<8,8,1>F    { align1 1Q compacted };
>(+f0.0) sel(8)  g71<1>F         -g39<8,8,1>F    g39<8,8,1>F     { align1 1Q compacted };
>   END B190 ->B191
>   START B192 <-B191 <-B277 (18 cycles)
>cmp.ge.f0.0(8)  null<1>UD       g116<8,8,1>UD   g107<8,8,1>UD   { align1 1Q compacted };
>   END B191 ->B192 ->B278
>(+f0.0) break(8) JIP: 4416      UIP: 4416                       { align1 1Q };
>   END B192 ->B191 ->B193
>   START B193 <-B192 (1012 cycles)
>shl(8)          g21<1>D         g115<8,8,1>D    0x00000002UD    { align1 1Q };
>send(8)         g36<1>UW        g21<8,8,1>UD    0x02106e10
>                            dp data 1 MsgDesc: ( untyped surface read, Surface = 16, SIMD8, Mask = 0xe) mlen 1 rlen 1 { align1 1Q };
>add(8)          g115<1>D        g115<8,8,1>D    1D              { align1 1Q compacted };
>mov(8)          g54<1>UD        g36<16,8,2>UW                   { align1 1Q };
>shl(8)          g97<1>D         g54<8,8,1>D     0x00000011UD    { align1 1Q };
>and(8)          g62<1>UD        g54<8,8,1>UD    0x00008000UD    { align1 1Q };
>shr(8)          g58<1>UD        g97<8,8,1>UD    0x00000011UD    { align1 1Q compacted };
>add(8)          g98<1>D         g106<8,8,1>D    g58<8,8,1>D     { align1 1Q compacted };
>shl(8)          g22<1>D         g98<8,8,1>D     0x00000002UD    { align1 1Q };
>send(8)         g63<1>UW        g22<8,8,1>UD    0x02106e10
>                            dp data 1 MsgDesc: ( untyped surface read, Surface = 16, SIMD8, Mask = 0xe) mlen 1 rlen 1 { align1 1Q };
>add(8)          g66<1>D         g98<8,8,1>D     1D              { align1 1Q compacted };
>shl(8)          g23<1>D         g66<8,8,1>D     0x00000002UD    { align1 1Q };
>mov(8)          g51<1>F         g63<16,8,2>HF                   { align1 1Q };
>mov(8)          g65<1>F         g63.1<16,8,2>HF                 { align1 1Q };
>send(8)         g67<1>UW        g23<8,8,1>UD    0x02106e10
>                            dp data 1 MsgDesc: ( untyped surface read, Surface = 16, SIMD8, Mask = 0xe) mlen 1 rlen 1 { align1 1Q };
>cmp.nz.f0.0(8)  g69<1>D         g62<8,8,1>D     0D              { align1 1Q compacted };
>mov(8)          g119<1>F        g67<16,8,2>HF                   { align1 1Q };
>mov(8)          g120<1>F        g67.1<16,8,2>HF                 { align1 1Q };
>(+f0.0) if(8)   JIP: 104        UIP: 184                        { align1 1Q };
>   END B193 ->B194 ->B195
>   START B194 <-B193 (340 cycles)
>add(8)          g70<1>D         g98<8,8,1>D     2D              { align1 1Q compacted };
>shl(8)          g24<1>D         g70<8,8,1>D     0x00000002UD    { align1 1Q };
>send(8)         g52<1>UW        g24<8,8,1>UD    0x02106e10
>                            dp data 1 MsgDesc: ( untyped surface read, Surface = 16, SIMD8, Mask = 0xe) mlen 1 rlen 1 { align1 1Q };
>mov(8)          g121<1>F        g52<16,8,2>HF                   { align1 1Q };
>mov(8)          g122<1>F        g52.1<16,8,2>HF                 { align1 1Q };
>else(8)         JIP: 96         UIP: 96                         { align1 1Q };
>   END B194 ->B196
>   START B195 <-B193 (36 cycles)
>add(8)          g55<1>F         g51<8,8,1>F     g119<8,8,1>F    { align1 1Q compacted };
>add(8)          g73<1>F         g65<8,8,1>F     g120<8,8,1>F    { align1 1Q compacted };
>mov(8)          g122<1>D        g120<8,8,1>D                    { align1 1Q compacted };
>mov(8)          g121<1>D        g119<8,8,1>D                    { align1 1Q compacted };
>mul(8)          g123<1>F        g55<8,8,1>F     0x3f000000F  /* 0.5F */ { align1 1Q };
>mul(8)          g124<1>F        g73<8,8,1>F     0x3f000000F  /* 0.5F */ { align1 1Q };
>mov(8)          g119<1>D        g123<8,8,1>D                    { align1 1Q compacted };
>mov(8)          g120<1>D        g124<8,8,1>D                    { align1 1Q compacted };
>   END B195 ->B196
>   START B196 <-B195 <-B194 (288 cycles)
>endif(8)        JIP: 3968                                       { align1 1Q };
>add(8)          g56<1>F         g51<8,8,1>F     -g103<8,8,1>F   { align1 1Q compacted };
>add(8)          g75<1>F         g65<8,8,1>F     -g49<8,8,1>F    { align1 1Q compacted };
>add(8)          g80<1>F         g119<8,8,1>F    -g103<8,8,1>F   { align1 1Q compacted };
>add(8)          g81<1>F         g120<8,8,1>F    -g49<8,8,1>F    { align1 1Q compacted };
>add(8)          g48<1>F         g121<8,8,1>F    -g103<8,8,1>F   { align1 1Q compacted };
>add(8)          g87<1>F         g122<8,8,1>F    -g49<8,8,1>F    { align1 1Q compacted };
>mul(8)          g76<1>F         g44<8,8,1>F     g75<8,8,1>F     { align1 1Q compacted };
>mul(8)          g35<1>F         g71<8,8,1>F     g75<8,8,1>F     { align1 1Q compacted };
>mul(8)          g82<1>F         g44<8,8,1>F     g81<8,8,1>F     { align1 1Q compacted };
>mul(8)          g84<1>F         g71<8,8,1>F     g81<8,8,1>F     { align1 1Q compacted };
>mul(8)          g88<1>F         g44<8,8,1>F     g87<8,8,1>F     { align1 1Q compacted };
>mul(8)          g90<1>F         g71<8,8,1>F     g87<8,8,1>F     { align1 1Q compacted };
>mad.g.f0.0(8)   g77<1>F         g76<4,4,1>F     g56<4,4,1>F     g43<4,4,1>F { align16 1Q };
>mad(8)          g79<1>F         g35<4,4,1>F     g56<4,4,1>F     g109<4,4,1>F { align16 1Q compacted };
>mad(8)          g83<1>F         g82<4,4,1>F     g80<4,4,1>F     g43<4,4,1>F { align16 1Q compacted };
>mad(8)          g85<1>F         g84<4,4,1>F     g80<4,4,1>F     g109<4,4,1>F { align16 1Q compacted };
>mad(8)          g89<1>F         g88<4,4,1>F     g48<4,4,1>F     g43<4,4,1>F { align16 1Q compacted };
>mad(8)          g91<1>F         g90<4,4,1>F     g48<4,4,1>F     g109<4,4,1>F { align16 1Q compacted };
>(-f0.0) sel(8)  g99<1>UD        g64<8,8,1>UD    0x00000002UD    { align1 1Q };
>mad(8)          g92<1>F         g77<4,4,1>F     g83<4,4,1>F     -g59.1<0,1,0>F { align16 1Q };
>add(8)          g57<1>F         g77<8,8,1>F     -g83<8,8,1>F    { align1 1Q compacted };
>mad(8)          g93<1>F         g79<4,4,1>F     g85<4,4,1>F     -g59.1<0,1,0>F { align16 1Q };
>add(8)          g61<1>F         g79<8,8,1>F     -g85<8,8,1>F    { align1 1Q compacted };
>cmp.g.f0.0(8)   null<1>F        g83<8,8,1>F     0x0F  /* 0F */  { align1 1Q compacted };
>add(8)          g95<1>F         g92<8,8,1>F     g89<8,8,1>F     { align1 1Q compacted };
>add(8)          g96<1>F         g93<8,8,1>F     g91<8,8,1>F     { align1 1Q compacted };
>(-f0.0) sel(8)  g100<1>UD       g64<8,8,1>UD    0x00000004UD    { align1 1Q };
>add(8)          g102<1>D        g99<8,8,1>D     g100<8,8,1>D    { align1 1Q compacted };
>cmp.g.f0.0(8)   null<1>F        g89<8,8,1>F     0x0F  /* 0F */  { align1 1Q compacted };
>(-f0.0) sel(8)  g101<1>UD       g64<8,8,1>UD    0x00000008UD    { align1 1Q };
>add(8)          g5<1>D          g102<8,8,1>D    g101<8,8,1>D    { align1 1Q compacted };
>cmp.g.f0.0(8)   null<1>F        g79<8,8,1>F     0x0F  /* 0F */  { align1 1Q compacted };
>shr(8)          g50<1>UD        g74<8,8,1>UD    g5<8,8,1>UD     { align1 1Q compacted };
>(-f0.0) sel(8)  g105<1>UD       g64<8,8,1>UD    0x00000002UD    { align1 1Q };
>and(8)          g125<1>UD       g50<8,8,1>UD    0x00000003UD    { align1 1Q compacted };
>cmp.g.f0.0(8)   null<1>F        g85<8,8,1>F     0x0F  /* 0F */  { align1 1Q compacted };
>(-f0.0) sel(8)  g108<1>UD       g64<8,8,1>UD    0x00000004UD    { align1 1Q };
>add(8)          g46<1>D         g105<8,8,1>D    g108<8,8,1>D    { align1 1Q compacted };
>cmp.g.f0.0(8)   null<1>F        g91<8,8,1>F     0x0F  /* 0F */  { align1 1Q compacted };
>(-f0.0) sel(8)  g47<1>UD        g64<8,8,1>UD    0x00000008UD    { align1 1Q };
>add(8)          g111<1>D        g46<8,8,1>D     g47<8,8,1>D     { align1 1Q compacted };
>shr(8)          g112<1>UD       g74<8,8,1>UD    g111<8,8,1>UD   { align1 1Q compacted };
>and.nz.f0.0(8)  g126<1>UD       g112<8,8,1>UD   0x00000003UD    { align1 1Q compacted };
>(+f0.0) if(8)   JIP: 696        UIP: 704                        { align1 1Q };
>   END B196 ->B197 ->B215
>   START B197 <-B196 (18 cycles)
>mov.nz.f0.0(8)  null<1>D        g69<8,8,1>D                     { align1 1Q };
>(+f0.0) if(8)   JIP: 48         UIP: 56                         { align1 1Q };
>   END B197 ->B198 ->B199
>   START B198 <-B197 (4 cycles)
>cmp.g.f0.0(8)   g127<1>F        (abs)g96<8,8,1>F 0x38d1b717F  /* 0.0001F */ { align1 1Q };
>else(8)         JIP: 24         UIP: 24                         { align1 1Q };
>   END B198 ->B200
>   START B199 <-B197 (2 cycles)
>mov(8)          g127<1>UD       0x00000000UD                    { align1 1Q compacted };
>   END B199 ->B200
>   START B200 <-B199 <-B198 (20 cycles)
>endif(8)        JIP: 592                                        { align1 1Q };
>mov.nz.f0.0(8)  null<1>D        g127<8,8,1>D                    { align1 1Q };
>(+f0.0) if(8)   JIP: 128        UIP: 168                        { align1 1Q };
>   END B200 ->B201 ->B202
>   START B201 <-B200 (94 cycles)
>math inv(8)     g113<1>F        g96<8,8,1>F     null<8,8,1>F    { align1 1Q compacted };
>mul(8)          g119<1>F        g96<8,8,1>F     g79<8,8,1>F     { align1 1Q compacted };
>mad.l.f0.0(8)   g120<1>F        -g119<4,4,1>F   g61<4,4,1>F     g61<4,4,1>F { align16 1Q };
>sel.ge(8)       g121<1>F        g120<8,8,1>F    0x0F  /* 0F */  { align1 1Q compacted };
>(-f0.0) sel(8)  g126<1>UD       g126<8,8,1>UD   0x00000000UD    { align1 1Q };
>math sqrt(8)    g122<1>F        g121<8,8,1>F    null<8,8,1>F    { align1 1Q compacted };
>add(8)          g123<1>F        g61<8,8,1>F     -g122<8,8,1>F   { align1 1Q compacted };
>add(8)          g124<1>F        g61<8,8,1>F     g122<8,8,1>F    { align1 1Q compacted };
>mul(8)          g2<1>F          g123<8,8,1>F    g113<8,8,1>F    { align1 1Q compacted };
>mul(8)          g3<1>F          g124<8,8,1>F    g113<8,8,1>F    { align1 1Q compacted };
>else(8)         JIP: 56         UIP: 56                         { align1 1Q };
>   END B201 ->B203
>   START B202 <-B200 (38 cycles)
>mul(8)          g127<1>F        g79<8,8,1>F     0x3f000000F  /* 0.5F */ { align1 1Q };
>math inv(8)     g4<1>F          g61<8,8,1>F     null<8,8,1>F    { align1 1Q compacted };
>mul(8)          g3<1>F          g127<8,8,1>F    g4<8,8,1>F      { align1 1Q compacted };
>mov(8)          g2<1>D          g3<8,8,1>D                      { align1 1Q compacted };
>   END B202 ->B203
>   START B203 <-B202 <-B201 (45 cycles)
>endif(8)        JIP: 392                                        { align1 1Q };
>mul(8)          g11<1>F         g57<8,8,1>F     0x40000000F  /* 2F */ { align1 1Q };
>and.nz.f0.0(8)  null<1>UD       g126<8,8,1>UD   0x00000001UD    { align1 1Q compacted };
>mad(8)          g12<1>F         -g11<4,4,1>F    g2<4,4,1>F      g95<4,4,1>F { align16 1Q compacted };
>mad(8)          g14<1>F         -g11<4,4,1>F    g3<4,4,1>F      g95<4,4,1>F { align16 1Q compacted };
>mad(8)          g13<1>F         g77<4,4,1>F     g2<4,4,1>F      g12<4,4,1>F { align16 1Q compacted };
>mad(8)          g15<1>F         g77<4,4,1>F     g3<4,4,1>F      g14<4,4,1>F { align16 1Q compacted };
>(+f0.0) if(8)   JIP: 144        UIP: 152                        { align1 1Q };
>   END B203 ->B204 ->B208
>   START B204 <-B203 (68 cycles)
>cmp.ge.f0.0(8)  g16<1>F         g13<8,8,1>F     0x0F  /* 0F */  { align1 1Q compacted };
>cmp.ge.f0.0(8)  g17<1>F         g42<8,8,1>F     g13<8,8,1>F     { align1 1Q compacted };
>and.nz.f0.0(8)  null<1>UD       g17<8,8,1>UD    g16<8,8,1>UD    { align1 1Q compacted };
>(-f0.0) sel(8)  g4<1>UD         g64<8,8,1>UD    0x00000001UD    { align1 1Q };
>cmp.l.f0.0(8)   null<1>F        g13<8,8,1>F     0x0F  /* 0F */  { align1 1Q compacted };
>(+f0.0) if(8)   JIP: 40         UIP: 48                         { align1 1Q };
>   END B204 ->B205 ->B206
>   START B205 <-B204 (4 cycles)
>sel.l(8)        g118<1>F        g118<8,8,1>F    (abs)g13<8,8,1>F { align1 1Q compacted };
>else(8)         JIP: 24         UIP: 24                         { align1 1Q };
>   END B205 ->B207
>   START B206 <-B204 (2 cycles)
>sel.l(8)        g117<1>F        g117<8,8,1>F    (abs)g13<8,8,1>F { align1 1Q compacted };
>   END B206 ->B207
>   START B207 <-B206 <-B205 (4 cycles)
>endif(8)        JIP: 16                                         { align1 1Q };
>else(8)         JIP: 24         UIP: 24                         { align1 1Q };
>   END B207 ->B209
>   START B208 <-B203 (2 cycles)
>mov(8)          g4<1>UD         0x00000000UD                    { align1 1Q compacted };
>   END B208 ->B209
>   START B209 <-B208 <-B207 (20 cycles)
>endif(8)        JIP: 168                                        { align1 1Q };
>cmp.g.f0.0(8)   null<1>UD       g126<8,8,1>UD   0x00000001UD    { align1 1Q compacted };
>(+f0.0) if(8)   JIP: 128        UIP: 128                        { align1 1Q };
>   END B209 ->B210 ->B214
>   START B210 <-B209 (70 cycles)
>cmp.ge.f0.0(8)  g18<1>F         g15<8,8,1>F     0x0F  /* 0F */  { align1 1Q compacted };
>add(8)          g20<1>D         g4<8,8,1>D      -1D             { align1 1Q compacted };
>cmp.ge.f0.0(8)  g19<1>F         g42<8,8,1>F     g15<8,8,1>F     { align1 1Q compacted };
>and.nz.f0.0(8)  null<1>UD       g19<8,8,1>UD    g18<8,8,1>UD    { align1 1Q compacted };
>(+f0.0) sel(8)  g4<1>UD         g20<8,8,1>UD    g4<8,8,1>UD     { align1 1Q compacted };
>cmp.g.f0.0(8)   null<1>F        g15<8,8,1>F     0x0F  /* 0F */  { align1 1Q compacted };
>(+f0.0) if(8)   JIP: 40         UIP: 48                         { align1 1Q };
>   END B210 ->B211 ->B212
>   START B211 <-B210 (4 cycles)
>sel.l(8)        g118<1>F        g118<8,8,1>F    (abs)g15<8,8,1>F { align1 1Q compacted };
>else(8)         JIP: 24         UIP: 24                         { align1 1Q };
>   END B211 ->B213
>   START B212 <-B210 (2 cycles)
>sel.l(8)        g117<1>F        g117<8,8,1>F    (abs)g15<8,8,1>F { align1 1Q compacted };
>   END B212 ->B213
>   START B213 <-B212 <-B211 (2 cycles)
>endif(8)        JIP: 16                                         { align1 1Q };
>   END B213 ->B214
>   START B214 <-B209 <-B213 (4 cycles)
>endif(8)        JIP: 16                                         { align1 1Q };
>else(8)         JIP: 24         UIP: 24                         { align1 1Q };
>   END B214 ->B216
>   START B215 <-B196 (2 cycles)
>mov(8)          g4<1>UD         0x00000000UD                    { align1 1Q compacted };
>   END B215 ->B216
>   START B216 <-B215 <-B214 (20 cycles)
>endif(8)        JIP: 2832                                       { align1 1Q };
>cmp.nz.f0.0(8)  null<1>D        g125<8,8,1>D    0D              { align1 1Q compacted };
>(+f0.0) if(8)   JIP: 576        UIP: 576                        { align1 1Q };
>   END B216 ->B217 ->B234
>   START B217 <-B216 (18 cycles)
>mov.nz.f0.0(8)  null<1>D        g69<8,8,1>D                     { align1 1Q };
>(+f0.0) if(8)   JIP: 48         UIP: 56                         { align1 1Q };
>   END B217 ->B218 ->B219
>   START B218 <-B217 (4 cycles)
>cmp.g.f0.0(8)   g11<1>F         (abs)g95<8,8,1>F 0x38d1b717F  /* 0.0001F */ { align1 1Q };
>else(8)         JIP: 24         UIP: 24                         { align1 1Q };
>   END B218 ->B220
>   START B219 <-B217 (2 cycles)
>mov(8)          g11<1>UD        0x00000000UD                    { align1 1Q compacted };
>   END B219 ->B220
>   START B220 <-B219 <-B218 (20 cycles)
>endif(8)        JIP: 488                                        { align1 1Q };
>mov.nz.f0.0(8)  null<1>D        g11<8,8,1>D                     { align1 1Q };
>(+f0.0) if(8)   JIP: 128        UIP: 168                        { align1 1Q };
>   END B220 ->B221 ->B222
>   START B221 <-B220 (94 cycles)
>math inv(8)     g21<1>F         g95<8,8,1>F     null<8,8,1>F    { align1 1Q compacted };
>mul(8)          g22<1>F         g95<8,8,1>F     g77<8,8,1>F     { align1 1Q compacted };
>mad.l.f0.0(8)   g23<1>F         -g22<4,4,1>F    g57<4,4,1>F     g57<4,4,1>F { align16 1Q };
>sel.ge(8)       g24<1>F         g23<8,8,1>F     0x0F  /* 0F */  { align1 1Q compacted };
>(-f0.0) sel(8)  g125<1>UD       g125<8,8,1>UD   0x00000000UD    { align1 1Q };
>math sqrt(8)    g25<1>F         g24<8,8,1>F     null<8,8,1>F    { align1 1Q compacted };
>add(8)          g26<1>F         g57<8,8,1>F     -g25<8,8,1>F    { align1 1Q compacted };
>add(8)          g27<1>F         g57<8,8,1>F     g25<8,8,1>F     { align1 1Q compacted };
>mul(8)          g12<1>F         g26<8,8,1>F     g21<8,8,1>F     { align1 1Q compacted };
>mul(8)          g13<1>F         g27<8,8,1>F     g21<8,8,1>F     { align1 1Q compacted };
>else(8)         JIP: 56         UIP: 56                         { align1 1Q };
>   END B221 ->B223
>   START B222 <-B220 (38 cycles)
>mul(8)          g28<1>F         g77<8,8,1>F     0x3f000000F  /* 0.5F */ { align1 1Q };
>math inv(8)     g29<1>F         g57<8,8,1>F     null<8,8,1>F    { align1 1Q compacted };
>mul(8)          g13<1>F         g28<8,8,1>F     g29<8,8,1>F     { align1 1Q compacted };
>mov(8)          g12<1>D         g13<8,8,1>D                     { align1 1Q compacted };
>   END B222 ->B223
>   START B223 <-B222 <-B221 (44 cycles)
>endif(8)        JIP: 288                                        { align1 1Q };
>mul(8)          g30<1>F         g61<8,8,1>F     0x40000000F  /* 2F */ { align1 1Q };
>and.nz.f0.0(8)  null<1>UD       g125<8,8,1>UD   0x00000001UD    { align1 1Q compacted };
>mad(8)          g31<1>F         -g30<4,4,1>F    g12<4,4,1>F     g96<4,4,1>F { align16 1Q compacted };
>mad(8)          g38<1>F         -g30<4,4,1>F    g13<4,4,1>F     g96<4,4,1>F { align16 1Q compacted };
>mad(8)          g53<1>F         g79<4,4,1>F     g12<4,4,1>F     g31<4,4,1>F { align16 1Q compacted };
>mad(8)          g39<1>F         g79<4,4,1>F     g13<4,4,1>F     g38<4,4,1>F { align16 1Q compacted };
>(+f0.0) if(8)   JIP: 88         UIP: 88                         { align1 1Q };
>   END B223 ->B224 ->B228
>   START B224 <-B223 (18 cycles)
>cmp.g.f0.0(8)   null<1>F        g53<8,8,1>F     0x0F  /* 0F */  { align1 1Q compacted };
>(+f0.0) if(8)   JIP: 40         UIP: 48                         { align1 1Q };
>   END B224 ->B225 ->B226
>   START B225 <-B224 (4 cycles)
>sel.l(8)        g118<1>F        g118<8,8,1>F    (abs)g53<8,8,1>F { align1 1Q compacted };
>else(8)         JIP: 24         UIP: 24                         { align1 1Q };
>   END B225 ->B227
>   START B226 <-B224 (2 cycles)
>sel.l(8)        g117<1>F        g117<8,8,1>F    (abs)g53<8,8,1>F { align1 1Q compacted };
>   END B226 ->B227
>   START B227 <-B226 <-B225 (2 cycles)
>endif(8)        JIP: 16                                         { align1 1Q };
>   END B227 ->B228
>   START B228 <-B223 <-B227 (20 cycles)
>endif(8)        JIP: 128                                        { align1 1Q };
>cmp.g.f0.0(8)   null<1>UD       g125<8,8,1>UD   0x00000001UD    { align1 1Q compacted };
>(+f0.0) if(8)   JIP: 88         UIP: 88                         { align1 1Q };
>   END B228 ->B229 ->B233
>   START B229 <-B228 (18 cycles)
>cmp.l.f0.0(8)   null<1>F        g39<8,8,1>F     0x0F  /* 0F */  { align1 1Q compacted };
>(+f0.0) if(8)   JIP: 40         UIP: 48                         { align1 1Q };
>   END B229 ->B230 ->B231
>   START B230 <-B229 (4 cycles)
>sel.l(8)        g118<1>F        g118<8,8,1>F    (abs)g39<8,8,1>F { align1 1Q compacted };
>else(8)         JIP: 24         UIP: 24                         { align1 1Q };
>   END B230 ->B232
>   START B231 <-B229 (2 cycles)
>sel.l(8)        g117<1>F        g117<8,8,1>F    (abs)g39<8,8,1>F { align1 1Q compacted };
>   END B231 ->B232
>   START B232 <-B231 <-B230 (2 cycles)
>endif(8)        JIP: 16                                         { align1 1Q };
>   END B232 ->B233
>   START B233 <-B228 <-B232 (2 cycles)
>endif(8)        JIP: 16                                         { align1 1Q };
>   END B233 ->B234
>   START B234 <-B216 <-B233 (38 cycles)
>endif(8)        JIP: 2232                                       { align1 1Q };
>add(8)          g114<1>D        g114<8,8,1>D    g4<8,8,1>D      { align1 1Q compacted };
>add(8)          g40<1>D         g116<8,8,1>D    1D              { align1 1Q compacted };
>cmp.l.f0.0(8)   null<1>UD       g40<8,8,1>UD    g107<8,8,1>UD   { align1 1Q compacted };
>(+f0.0) if(8)   JIP: 2168       UIP: 2168                       { align1 1Q };
>   END B234 ->B235 ->B277
>   START B235 <-B234 (694 cycles)
>mov(8)          g41<1>UD        g36.1<16,8,2>UW                 { align1 1Q };
>shl(8)          g45<1>D         g41<8,8,1>D     0x00000011UD    { align1 1Q };
>and(8)          g54<1>UD        g41<8,8,1>UD    0x00008000UD    { align1 1Q };
>shr(8)          g110<1>UD       g45<8,8,1>UD    0x00000011UD    { align1 1Q compacted };
>add(8)          g36<1>D         g106<8,8,1>D    g110<8,8,1>D    { align1 1Q compacted };
>shl(8)          g25<1>D         g36<8,8,1>D     0x00000002UD    { align1 1Q };
>send(8)         g97<1>UW        g25<8,8,1>UD    0x02106e10
>                            dp data 1 MsgDesc: ( untyped surface read, Surface = 16, SIMD8, Mask = 0xe) mlen 1 rlen 1 { align1 1Q };
>add(8)          g62<1>D         g36<8,8,1>D     1D              { align1 1Q compacted };
>shl(8)          g26<1>D         g62<8,8,1>D     0x00000002UD    { align1 1Q };
>mov(8)          g58<1>F         g97<16,8,2>HF                   { align1 1Q };
>mov(8)          g98<1>F         g97.1<16,8,2>HF                 { align1 1Q };
>send(8)         g63<1>UW        g26<8,8,1>UD    0x02106e10
>                            dp data 1 MsgDesc: ( untyped surface read, Surface = 16, SIMD8, Mask = 0xe) mlen 1 rlen 1 { align1 1Q };
>cmp.nz.f0.0(8)  g51<1>D         g54<8,8,1>D     0D              { align1 1Q compacted };
>mov(8)          g14<1>F         g63<16,8,2>HF                   { align1 1Q };
>mov(8)          g15<1>F         g63.1<16,8,2>HF                 { align1 1Q };
>(+f0.0) if(8)   JIP: 104        UIP: 184                        { align1 1Q };
>   END B235 ->B236 ->B237
>   START B236 <-B235 (340 cycles)
>add(8)          g65<1>D         g36<8,8,1>D     2D              { align1 1Q compacted };
>shl(8)          g27<1>D         g65<8,8,1>D     0x00000002UD    { align1 1Q };
>send(8)         g66<1>UW        g27<8,8,1>UD    0x02106e10
>                            dp data 1 MsgDesc: ( untyped surface read, Surface = 16, SIMD8, Mask = 0xe) mlen 1 rlen 1 { align1 1Q };
>mov(8)          g16<1>F         g66<16,8,2>HF                   { align1 1Q };
>mov(8)          g17<1>F         g66.1<16,8,2>HF                 { align1 1Q };
>else(8)         JIP: 96         UIP: 96                         { align1 1Q };
>   END B236 ->B238
>   START B237 <-B235 (36 cycles)
>add(8)          g67<1>F         g58<8,8,1>F     g14<8,8,1>F     { align1 1Q compacted };
>add(8)          g69<1>F         g98<8,8,1>F     g15<8,8,1>F     { align1 1Q compacted };
>mov(8)          g17<1>D         g15<8,8,1>D                     { align1 1Q compacted };
>mov(8)          g16<1>D         g14<8,8,1>D                     { align1 1Q compacted };
>mul(8)          g18<1>F         g67<8,8,1>F     0x3f000000F  /* 0.5F */ { align1 1Q };
>mul(8)          g19<1>F         g69<8,8,1>F     0x3f000000F  /* 0.5F */ { align1 1Q };
>mov(8)          g14<1>D         g18<8,8,1>D                     { align1 1Q compacted };
>mov(8)          g15<1>D         g19<8,8,1>D                     { align1 1Q compacted };
>   END B237 ->B238
>   START B238 <-B237 <-B236 (288 cycles)
>endif(8)        JIP: 1760                                       { align1 1Q };
>add(8)          g70<1>F         g58<8,8,1>F     -g103<8,8,1>F   { align1 1Q compacted };
>add(8)          g52<1>F         g98<8,8,1>F     -g49<8,8,1>F    { align1 1Q compacted };
>add(8)          g76<1>F         g14<8,8,1>F     -g103<8,8,1>F   { align1 1Q compacted };
>add(8)          g77<1>F         g15<8,8,1>F     -g49<8,8,1>F    { align1 1Q compacted };
>add(8)          g82<1>F         g16<8,8,1>F     -g103<8,8,1>F   { align1 1Q compacted };
>add(8)          g83<1>F         g17<8,8,1>F     -g49<8,8,1>F    { align1 1Q compacted };
>mul(8)          g55<1>F         g44<8,8,1>F     g52<8,8,1>F     { align1 1Q compacted };
>mul(8)          g56<1>F         g71<8,8,1>F     g52<8,8,1>F     { align1 1Q compacted };
>mul(8)          g35<1>F         g44<8,8,1>F     g77<8,8,1>F     { align1 1Q compacted };
>mul(8)          g80<1>F         g71<8,8,1>F     g77<8,8,1>F     { align1 1Q compacted };
>mul(8)          g84<1>F         g44<8,8,1>F     g83<8,8,1>F     { align1 1Q compacted };
>mul(8)          g48<1>F         g71<8,8,1>F     g83<8,8,1>F     { align1 1Q compacted };
>mad.g.f0.0(8)   g73<1>F         g55<4,4,1>F     g70<4,4,1>F     g43<4,4,1>F { align16 1Q };
>mad(8)          g75<1>F         g56<4,4,1>F     g70<4,4,1>F     g109<4,4,1>F { align16 1Q compacted };
>mad(8)          g79<1>F         g35<4,4,1>F     g76<4,4,1>F     g43<4,4,1>F { align16 1Q compacted };
>mad(8)          g81<1>F         g80<4,4,1>F     g76<4,4,1>F     g109<4,4,1>F { align16 1Q compacted };
>mad(8)          g85<1>F         g84<4,4,1>F     g82<4,4,1>F     g43<4,4,1>F { align16 1Q compacted };
>mad(8)          g87<1>F         g48<4,4,1>F     g82<4,4,1>F     g109<4,4,1>F { align16 1Q compacted };
>(-f0.0) sel(8)  g95<1>UD        g64<8,8,1>UD    0x00000002UD    { align1 1Q };
>mad(8)          g88<1>F         g73<4,4,1>F     g79<4,4,1>F     -g59.1<0,1,0>F { align16 1Q };
>add(8)          g92<1>F         g73<8,8,1>F     -g79<8,8,1>F    { align1 1Q compacted };
>mad(8)          g89<1>F         g75<4,4,1>F     g81<4,4,1>F     -g59.1<0,1,0>F { align16 1Q };
>add(8)          g93<1>F         g75<8,8,1>F     -g81<8,8,1>F    { align1 1Q compacted };
>cmp.g.f0.0(8)   null<1>F        g79<8,8,1>F     0x0F  /* 0F */  { align1 1Q compacted };
>add(8)          g90<1>F         g88<8,8,1>F     g85<8,8,1>F     { align1 1Q compacted };
>add(8)          g91<1>F         g89<8,8,1>F     g87<8,8,1>F     { align1 1Q compacted };
>(-f0.0) sel(8)  g96<1>UD        g64<8,8,1>UD    0x00000004UD    { align1 1Q };
>add(8)          g61<1>D         g95<8,8,1>D     g96<8,8,1>D     { align1 1Q compacted };
>cmp.g.f0.0(8)   null<1>F        g85<8,8,1>F     0x0F  /* 0F */  { align1 1Q compacted };
>(-f0.0) sel(8)  g57<1>UD        g64<8,8,1>UD    0x00000008UD    { align1 1Q };
>add(8)          g99<1>D         g61<8,8,1>D     g57<8,8,1>D     { align1 1Q compacted };
>cmp.g.f0.0(8)   null<1>F        g75<8,8,1>F     0x0F  /* 0F */  { align1 1Q compacted };
>shr(8)          g100<1>UD       g74<8,8,1>UD    g99<8,8,1>UD    { align1 1Q compacted };
>(-f0.0) sel(8)  g101<1>UD       g64<8,8,1>UD    0x00000002UD    { align1 1Q };
>and(8)          g20<1>UD        g100<8,8,1>UD   0x00000003UD    { align1 1Q compacted };
>cmp.g.f0.0(8)   null<1>F        g81<8,8,1>F     0x0F  /* 0F */  { align1 1Q compacted };
>(-f0.0) sel(8)  g102<1>UD       g64<8,8,1>UD    0x00000004UD    { align1 1Q };
>add(8)          g50<1>D         g101<8,8,1>D    g102<8,8,1>D    { align1 1Q compacted };
>cmp.g.f0.0(8)   null<1>F        g87<8,8,1>F     0x0F  /* 0F */  { align1 1Q compacted };
>(-f0.0) sel(8)  g5<1>UD         g64<8,8,1>UD    0x00000008UD    { align1 1Q };
>add(8)          g105<1>D        g50<8,8,1>D     g5<8,8,1>D      { align1 1Q compacted };
>shr(8)          g108<1>UD       g74<8,8,1>UD    g105<8,8,1>UD   { align1 1Q compacted };
>and.nz.f0.0(8)  g21<1>UD        g108<8,8,1>UD   0x00000003UD    { align1 1Q compacted };
>(+f0.0) if(8)   JIP: 696        UIP: 704                        { align1 1Q };
>   END B238 ->B239 ->B257
>   START B239 <-B238 (18 cycles)
>mov.nz.f0.0(8)  null<1>D        g51<8,8,1>D                     { align1 1Q };
>(+f0.0) if(8)   JIP: 48         UIP: 56                         { align1 1Q };
>   END B239 ->B240 ->B241
>   START B240 <-B239 (4 cycles)
>cmp.g.f0.0(8)   g22<1>F         (abs)g91<8,8,1>F 0x38d1b717F  /* 0.0001F */ { align1 1Q };
>else(8)         JIP: 24         UIP: 24                         { align1 1Q };
>   END B240 ->B242
>   START B241 <-B239 (2 cycles)
>mov(8)          g22<1>UD        0x00000000UD                    { align1 1Q compacted };
>   END B241 ->B242
>   START B242 <-B241 <-B240 (20 cycles)
>endif(8)        JIP: 592                                        { align1 1Q };
>mov.nz.f0.0(8)  null<1>D        g22<8,8,1>D                     { align1 1Q };
>(+f0.0) if(8)   JIP: 128        UIP: 168                        { align1 1Q };
>   END B242 ->B243 ->B244
>   START B243 <-B242 (94 cycles)
>math inv(8)     g47<1>F         g91<8,8,1>F     null<8,8,1>F    { align1 1Q compacted };
>mul(8)          g46<1>F         g91<8,8,1>F     g75<8,8,1>F     { align1 1Q compacted };
>mad.l.f0.0(8)   g111<1>F        -g46<4,4,1>F    g93<4,4,1>F     g93<4,4,1>F { align16 1Q };
>sel.ge(8)       g112<1>F        g111<8,8,1>F    0x0F  /* 0F */  { align1 1Q compacted };
>(-f0.0) sel(8)  g21<1>UD        g21<8,8,1>UD    0x00000000UD    { align1 1Q };
>math sqrt(8)    g113<1>F        g112<8,8,1>F    null<8,8,1>F    { align1 1Q compacted };
>add(8)          g119<1>F        g93<8,8,1>F     -g113<8,8,1>F   { align1 1Q compacted };
>add(8)          g120<1>F        g93<8,8,1>F     g113<8,8,1>F    { align1 1Q compacted };
>mul(8)          g23<1>F         g119<8,8,1>F    g47<8,8,1>F     { align1 1Q compacted };
>mul(8)          g24<1>F         g120<8,8,1>F    g47<8,8,1>F     { align1 1Q compacted };
>else(8)         JIP: 56         UIP: 56                         { align1 1Q };
>   END B243 ->B245
>   START B244 <-B242 (38 cycles)
>mul(8)          g121<1>F        g75<8,8,1>F     0x3f000000F  /* 0.5F */ { align1 1Q };
>math inv(8)     g122<1>F        g93<8,8,1>F     null<8,8,1>F    { align1 1Q compacted };
>mul(8)          g24<1>F         g121<8,8,1>F    g122<8,8,1>F    { align1 1Q compacted };
>mov(8)          g23<1>D         g24<8,8,1>D                     { align1 1Q compacted };
>   END B244 ->B245
>   START B245 <-B244 <-B243 (44 cycles)
>endif(8)        JIP: 392                                        { align1 1Q };
>mul(8)          g123<1>F        g92<8,8,1>F     0x40000000F  /* 2F */ { align1 1Q };
>and.nz.f0.0(8)  null<1>UD       g21<8,8,1>UD    0x00000001UD    { align1 1Q compacted };
>mad(8)          g124<1>F        -g123<4,4,1>F   g23<4,4,1>F     g90<4,4,1>F { align16 1Q compacted };
>mad(8)          g126<1>F        -g123<4,4,1>F   g24<4,4,1>F     g90<4,4,1>F { align16 1Q compacted };
>mad(8)          g125<1>F        g73<4,4,1>F     g23<4,4,1>F     g124<4,4,1>F { align16 1Q compacted };
>mad(8)          g127<1>F        g73<4,4,1>F     g24<4,4,1>F     g126<4,4,1>F { align16 1Q compacted };
>(+f0.0) if(8)   JIP: 144        UIP: 152                        { align1 1Q };
>   END B245 ->B246 ->B250
>   START B246 <-B245 (68 cycles)
>cmp.ge.f0.0(8)  g2<1>F          g125<8,8,1>F    0x0F  /* 0F */  { align1 1Q compacted };
>cmp.ge.f0.0(8)  g3<1>F          g42<8,8,1>F     g125<8,8,1>F    { align1 1Q compacted };
>and.nz.f0.0(8)  null<1>UD       g3<8,8,1>UD     g2<8,8,1>UD     { align1 1Q compacted };
>(-f0.0) sel(8)  g25<1>UD        g64<8,8,1>UD    0x00000001UD    { align1 1Q };
>cmp.l.f0.0(8)   null<1>F        g125<8,8,1>F    0x0F  /* 0F */  { align1 1Q compacted };
>(+f0.0) if(8)   JIP: 40         UIP: 48                         { align1 1Q };
>   END B246 ->B247 ->B248
>   START B247 <-B246 (4 cycles)
>sel.l(8)        g118<1>F        g118<8,8,1>F    (abs)g125<8,8,1>F { align1 1Q compacted };
>else(8)         JIP: 24         UIP: 24                         { align1 1Q };
>   END B247 ->B249
>   START B248 <-B246 (2 cycles)
>sel.l(8)        g117<1>F        g117<8,8,1>F    (abs)g125<8,8,1>F { align1 1Q compacted };
>   END B248 ->B249
>   START B249 <-B248 <-B247 (4 cycles)
>endif(8)        JIP: 16                                         { align1 1Q };
>else(8)         JIP: 24         UIP: 24                         { align1 1Q };
>   END B249 ->B251
>   START B250 <-B245 (2 cycles)
>mov(8)          g25<1>UD        0x00000000UD                    { align1 1Q compacted };
>   END B250 ->B251
>   START B251 <-B250 <-B249 (20 cycles)
>endif(8)        JIP: 168                                        { align1 1Q };
>cmp.g.f0.0(8)   null<1>UD       g21<8,8,1>UD    0x00000001UD    { align1 1Q compacted };
>(+f0.0) if(8)   JIP: 128        UIP: 128                        { align1 1Q };
>   END B251 ->B252 ->B256
>   START B252 <-B251 (70 cycles)
>cmp.ge.f0.0(8)  g4<1>F          g127<8,8,1>F    0x0F  /* 0F */  { align1 1Q compacted };
>add(8)          g12<1>D         g25<8,8,1>D     -1D             { align1 1Q compacted };
>cmp.ge.f0.0(8)  g11<1>F         g42<8,8,1>F     g127<8,8,1>F    { align1 1Q compacted };
>and.nz.f0.0(8)  null<1>UD       g11<8,8,1>UD    g4<8,8,1>UD     { align1 1Q compacted };
>(+f0.0) sel(8)  g25<1>UD        g12<8,8,1>UD    g25<8,8,1>UD    { align1 1Q compacted };
>cmp.g.f0.0(8)   null<1>F        g127<8,8,1>F    0x0F  /* 0F */  { align1 1Q compacted };
>(+f0.0) if(8)   JIP: 40         UIP: 48                         { align1 1Q };
>   END B252 ->B253 ->B254
>   START B253 <-B252 (4 cycles)
>sel.l(8)        g118<1>F        g118<8,8,1>F    (abs)g127<8,8,1>F { align1 1Q compacted };
>else(8)         JIP: 24         UIP: 24                         { align1 1Q };
>   END B253 ->B255
>   START B254 <-B252 (2 cycles)
>sel.l(8)        g117<1>F        g117<8,8,1>F    (abs)g127<8,8,1>F { align1 1Q compacted };
>   END B254 ->B255
>   START B255 <-B254 <-B253 (2 cycles)
>endif(8)        JIP: 16                                         { align1 1Q };
>   END B255 ->B256
>   START B256 <-B251 <-B255 (4 cycles)
>endif(8)        JIP: 16                                         { align1 1Q };
>else(8)         JIP: 24         UIP: 24                         { align1 1Q };
>   END B256 ->B258
>   START B257 <-B238 (2 cycles)
>mov(8)          g25<1>UD        0x00000000UD                    { align1 1Q compacted };
>   END B257 ->B258
>   START B258 <-B257 <-B256 (20 cycles)
>endif(8)        JIP: 624                                        { align1 1Q };
>cmp.nz.f0.0(8)  null<1>D        g20<8,8,1>D     0D              { align1 1Q compacted };
>(+f0.0) if(8)   JIP: 576        UIP: 576                        { align1 1Q };
>   END B258 ->B259 ->B276
>   START B259 <-B258 (18 cycles)
>mov.nz.f0.0(8)  null<1>D        g51<8,8,1>D                     { align1 1Q };
>(+f0.0) if(8)   JIP: 48         UIP: 56                         { align1 1Q };
>   END B259 ->B260 ->B261
>   START B260 <-B259 (4 cycles)
>cmp.g.f0.0(8)   g26<1>F         (abs)g90<8,8,1>F 0x38d1b717F  /* 0.0001F */ { align1 1Q };
>else(8)         JIP: 24         UIP: 24                         { align1 1Q };
>   END B260 ->B262
>   START B261 <-B259 (2 cycles)
>mov(8)          g26<1>UD        0x00000000UD                    { align1 1Q compacted };
>   END B261 ->B262
>   START B262 <-B261 <-B260 (20 cycles)
>endif(8)        JIP: 488                                        { align1 1Q };
>mov.nz.f0.0(8)  null<1>D        g26<8,8,1>D                     { align1 1Q };
>(+f0.0) if(8)   JIP: 128        UIP: 168                        { align1 1Q };
>   END B262 ->B263 ->B264
>   START B263 <-B262 (94 cycles)
>math inv(8)     g13<1>F         g90<8,8,1>F     null<8,8,1>F    { align1 1Q compacted };
>mul(8)          g14<1>F         g90<8,8,1>F     g73<8,8,1>F     { align1 1Q compacted };
>mad.l.f0.0(8)   g15<1>F         -g14<4,4,1>F    g92<4,4,1>F     g92<4,4,1>F { align16 1Q };
>sel.ge(8)       g16<1>F         g15<8,8,1>F     0x0F  /* 0F */  { align1 1Q compacted };
>(-f0.0) sel(8)  g20<1>UD        g20<8,8,1>UD    0x00000000UD    { align1 1Q };
>math sqrt(8)    g17<1>F         g16<8,8,1>F     null<8,8,1>F    { align1 1Q compacted };
>add(8)          g18<1>F         g92<8,8,1>F     -g17<8,8,1>F    { align1 1Q compacted };
>add(8)          g19<1>F         g92<8,8,1>F     g17<8,8,1>F     { align1 1Q compacted };
>mul(8)          g27<1>F         g18<8,8,1>F     g13<8,8,1>F     { align1 1Q compacted };
>mul(8)          g28<1>F         g19<8,8,1>F     g13<8,8,1>F     { align1 1Q compacted };
>else(8)         JIP: 56         UIP: 56                         { align1 1Q };
>   END B263 ->B265
>   START B264 <-B262 (38 cycles)
>mul(8)          g21<1>F         g73<8,8,1>F     0x3f000000F  /* 0.5F */ { align1 1Q };
>math inv(8)     g22<1>F         g92<8,8,1>F     null<8,8,1>F    { align1 1Q compacted };
>mul(8)          g28<1>F         g21<8,8,1>F     g22<8,8,1>F     { align1 1Q compacted };
>mov(8)          g27<1>D         g28<8,8,1>D                     { align1 1Q compacted };
>   END B264 ->B265
>   START B265 <-B264 <-B263 (44 cycles)
>endif(8)        JIP: 288                                        { align1 1Q };
>mul(8)          g23<1>F         g93<8,8,1>F     0x40000000F  /* 2F */ { align1 1Q };
>and.nz.f0.0(8)  null<1>UD       g20<8,8,1>UD    0x00000001UD    { align1 1Q compacted };
>mad(8)          g24<1>F         -g23<4,4,1>F    g27<4,4,1>F     g91<4,4,1>F { align16 1Q compacted };
>mad(8)          g29<1>F         -g23<4,4,1>F    g28<4,4,1>F     g91<4,4,1>F { align16 1Q compacted };
>mad(8)          g26<1>F         g75<4,4,1>F     g27<4,4,1>F     g24<4,4,1>F { align16 1Q compacted };
>mad(8)          g30<1>F         g75<4,4,1>F     g28<4,4,1>F     g29<4,4,1>F { align16 1Q compacted };
>(+f0.0) if(8)   JIP: 88         UIP: 88                         { align1 1Q };
>   END B265 ->B266 ->B270
>   START B266 <-B265 (18 cycles)
>cmp.g.f0.0(8)   null<1>F        g26<8,8,1>F     0x0F  /* 0F */  { align1 1Q compacted };
>(+f0.0) if(8)   JIP: 40         UIP: 48                         { align1 1Q };
>   END B266 ->B267 ->B268
>   START B267 <-B266 (4 cycles)
>sel.l(8)        g118<1>F        g118<8,8,1>F    (abs)g26<8,8,1>F { align1 1Q compacted };
>else(8)         JIP: 24         UIP: 24                         { align1 1Q };
>   END B267 ->B269
>   START B268 <-B266 (2 cycles)
>sel.l(8)        g117<1>F        g117<8,8,1>F    (abs)g26<8,8,1>F { align1 1Q compacted };
>   END B268 ->B269
>   START B269 <-B268 <-B267 (2 cycles)
>endif(8)        JIP: 16                                         { align1 1Q };
>   END B269 ->B270
>   START B270 <-B265 <-B269 (20 cycles)
>endif(8)        JIP: 128                                        { align1 1Q };
>cmp.g.f0.0(8)   null<1>UD       g20<8,8,1>UD    0x00000001UD    { align1 1Q compacted };
>(+f0.0) if(8)   JIP: 88         UIP: 88                         { align1 1Q };
>   END B270 ->B271 ->B275
>   START B271 <-B270 (18 cycles)
>cmp.l.f0.0(8)   null<1>F        g30<8,8,1>F     0x0F  /* 0F */  { align1 1Q compacted };
>(+f0.0) if(8)   JIP: 40         UIP: 48                         { align1 1Q };
>   END B271 ->B272 ->B273
>   START B272 <-B271 (4 cycles)
>sel.l(8)        g118<1>F        g118<8,8,1>F    (abs)g30<8,8,1>F { align1 1Q compacted };
>else(8)         JIP: 24         UIP: 24                         { align1 1Q };
>   END B272 ->B274
>   START B273 <-B271 (2 cycles)
>sel.l(8)        g117<1>F        g117<8,8,1>F    (abs)g30<8,8,1>F { align1 1Q compacted };
>   END B273 ->B274
>   START B274 <-B273 <-B272 (2 cycles)
>endif(8)        JIP: 16                                         { align1 1Q };
>   END B274 ->B275
>   START B275 <-B270 <-B274 (2 cycles)
>endif(8)        JIP: 16                                         { align1 1Q };
>   END B275 ->B276
>   START B276 <-B258 <-B275 (4 cycles)
>endif(8)        JIP: 24                                         { align1 1Q };
>add(8)          g114<1>D        g114<8,8,1>D    g25<8,8,1>D     { align1 1Q compacted };
>   END B276 ->B277
>   START B277 <-B234 <-B276 (6 cycles)
>endif(8)        JIP: 24                                         { align1 1Q };
>add(8)          g116<1>D        g116<8,8,1>D    2D              { align1 1Q compacted };
>while(8)        JIP: -4424                                      { align1 1Q };
>   END B277 ->B192
>   START B278 <-B191 (34 cycles)
>cmp.z.f0.0(8)   g31<1>D         g114<8,8,1>D    0D              { align1 1Q compacted };
>or.nz.f0.0(8)   null<1>UD       g31<8,8,1>UD    g94<8,8,1>UD    { align1 1Q compacted };
>(+f0.0) if(8)   JIP: 40         UIP: 104                        { align1 1Q };
>   END B278 ->B279 ->B280
>   START B279 <-B278 (4 cycles)
>sel.l(8)        g118<1>F        g118<8,8,1>F    g117<8,8,1>F    { align1 1Q compacted };
>else(8)         JIP: 80         UIP: 80                         { align1 1Q };
>   END B279 ->B283
>   START B280 <-B278 (18 cycles)
>cmp.nz.f0.0(8)  null<1>D        g114<8,8,1>D    -1D             { align1 1Q compacted };
>(+f0.0) if(8)   JIP: 40         UIP: 40                         { align1 1Q };
>   END B280 ->B281 ->B282
>   START B281 <-B280 (18 cycles)
>cmp.z.f0.0(8)   null<1>D        g114<8,8,1>D    1D              { align1 1Q compacted };
>(+f0.0) sel(8)  g118<1>UD       g117<8,8,1>UD   0x3f000000UD    { align1 1Q };
>   END B281 ->B282
>   START B282 <-B280 <-B281 (2 cycles)
>endif(8)        JIP: 16                                         { align1 1Q };
>   END B282 ->B283
>   START B283 <-B282 <-B279 (86 cycles)
>endif(8)        JIP: 248                                        { align1 1Q };
>sel.l(8)        g53<1>F         g118<8,8,1>F    0x3f000000F  /* 0.5F */ { align1 1Q };
>and(8)          g38<1>UD        g114<8,8,1>UD   0x00000001UD    { align1 1Q compacted };
>cmp.z.f0.0(8)   g39<1>D         g38<8,8,1>D     0D              { align1 1Q compacted };
>and.nz.f0.0(8)  null<1>UD       g94<8,8,1>UD    g39<8,8,1>UD    { align1 1Q compacted };
>(-f0.0) sel(8)  g40<1>UD        g114<8,8,1>UD   0x00000000UD    { align1 1Q };
>cmp.nz.f0.0(8)  null<1>D        g40<8,8,1>D     0D              { align1 1Q compacted };
>(+f0.0) if(8)   JIP: 48         UIP: 64                         { align1 1Q };
>   END B283 ->B284 ->B285
>   START B284 <-B283 (4 cycles)
>add(8)          g37<1>F         g53<8,8,1>F     0x3f000000F  /* 0.5F */ { align1 1Q };
>else(8)         JIP: 32         UIP: 32                         { align1 1Q };
>   END B284 ->B286
>   START B285 <-B283 (2 cycles)
>add(8)          g37<1>F         -g53<8,8,1>F    0x3f000000F  /* 0.5F */ { align1 1Q };
>   END B285 ->B286
>   START B286 <-B285 <-B284 (20 cycles)
>endif(8)        JIP: 104                                        { align1 1Q };
>and.nz.f0.0(8)  null<1>UD       g7.3<0,1,0>UD   0x40000000UD    { align1 1Q };
>(+f0.0) if(8)   JIP: 32         UIP: 32                         { align1 1Q };
>   END B286 ->B287 ->B288
>   START B287 <-B286 (2 cycles)
>add(8)          g37<1>F         -g37<8,8,1>F    0x3f800000F  /* 1F */ { align1 1Q };
>   END B287 ->B288
>   START B288 <-B286 <-B287 (10 cycles)
>endif(8)        JIP: 40                                         { align1 1Q };
>mov(8)          g32<1>D         g37<8,8,1>D                     { align1 1Q compacted };
>mov(8)          g33<1>D         g37<8,8,1>D                     { align1 1Q compacted };
>mov(8)          g34<1>D         g37<8,8,1>D                     { align1 1Q compacted };
>else(8)         JIP: 3416       UIP: 3416                       { align1 1Q };
>   END B288 ->B339
>   START B289 <-B182 (18 cycles)
>cmp.z.f0.0(8)   null<1>D        g9.7<0,1,0>D    23D             { align1 1Q };
>(+f0.0) if(8)   JIP: 3368       UIP: 3368                       { align1 1Q };
>   END B289 ->B290 ->B338
>   START B290 <-B289 (772 cycles)
>add(8)          g41<1>F         g103.1<4,4,0>F  -g103<4,4,0>F   { align1 1Q compacted };
>mul(8)          g42<1>F         g103<8,8,1>F    g6<0,1,0>F      { align1 1Q compacted };
>add(8)          g45<1>F         g49.1<4,4,0>F   -g49<4,4,0>F    { align1 1Q compacted };
>mul(8)          g110<1>F        g49<8,8,1>F     g6<0,1,0>F      { align1 1Q compacted };
>and(8)          g36<1>UD        g7.3<0,1,0>UD   0x3fffffffUD    { align1 1Q };
>and(8)          g54<1>UD        g7.3<0,1,0>UD   0x80000000UD    { align1 1Q };
>mov(8)          g62<1>F         g8.3<0,1,0>UD                   { align1 1Q compacted };
>mov(8)          g63<1>F         g7.7<0,1,0>UD                   { align1 1Q };
>add(8)          g51<1>D         g8.3<0,1,0>D    -1D             { align1 1Q compacted };
>add(8)          g65<1>F         g103<8,8,1>F    0x42000000F  /* 32F */ { align1 1Q };
>add(8)          g52<1>D         g7.7<0,1,0>D    -1D             { align1 1Q };
>add(8)          g55<1>F         g49<8,8,1>F     0x42000000F  /* 32F */ { align1 1Q };
>shl(8)          g81<1>D         g7.7<0,1,0>D    0x00000001UD    { align1 1Q };
>add(8)          g43<1>F         -g42<4,4,0>F    g42.2<4,4,0>F   { align1 1Q compacted };
>add(8)          g109<1>F        -g110<4,4,0>F   g110.2<4,4,0>F  { align1 1Q compacted };
>cmp.nz.f0.0(8)  g97<1>D         g54<8,8,1>D     0D              { align1 1Q compacted };
>mul(8)          g66<1>F         g62<8,8,1>F     0x3c800000F  /* 0.015625F */ { align1 1Q };
>mul(8)          g73<1>F         g63<8,8,1>F     0x3c800000F  /* 0.015625F */ { align1 1Q };
>cmp.l.f0.0(8)   g35<1>F         g103<8,8,1>F    0x0F  /* 0F */  { align1 1Q compacted };
>add(8)          g44<1>F         (abs)g41<8,8,1>F (abs)g43<8,8,1>F { align1 1Q compacted };
>add(8)          g71<1>F         (abs)g45<8,8,1>F (abs)g109<8,8,1>F { align1 1Q compacted };
>mul(8)          g67<1>F         g66<8,8,1>F     g65<8,8,1>F     { align1 1Q compacted };
>mul(8)          g56<1>F         g73<8,8,1>F     g55<8,8,1>F     { align1 1Q compacted };
>(+f0.0) sel(8)  g79<1>UD        g72<8,8,1>UD    0x3f800000UD    { align1 1Q };
>math inv(8)     g58<1>F         g44<8,8,1>F     null<8,8,1>F    { align1 1Q compacted };
>math inv(8)     g98<1>F         g71<8,8,1>F     null<8,8,1>F    { align1 1Q compacted };
>mov(8)          g69<1>UD        g67<8,8,1>F                     { align1 1Q compacted };
>mov(8)          g75<1>UD        g56<8,8,1>F                     { align1 1Q compacted };
>cmp.l.f0.0(8)   g84<1>F         g49<8,8,1>F     0x0F  /* 0F */  { align1 1Q compacted };
>sel.l(8)        g70<1>UD        g51<8,8,1>UD    g69<8,8,1>UD    { align1 1Q compacted };
>sel.l(8)        g76<1>UD        g52<8,8,1>UD    g75<8,8,1>UD    { align1 1Q compacted };
>(+f0.0) sel(8)  g85<1>UD        g72<8,8,1>UD    0x3f800000UD    { align1 1Q };
>add(8)          g82<1>D         g70<8,8,1>D     g81<8,8,1>D     { align1 1Q compacted };
>add(8)          g77<1>D         g76<8,8,1>D     g7.7<0,1,0>D    { align1 1Q compacted };
>add(8)          g83<1>D         g82<8,8,1>D     g8.3<0,1,0>D    { align1 1Q compacted };
>csel.l(8)       g80<1>F         g77<4,4,1>F     g76<4,4,1>F     g103<4,4,1>F { align16 1Q };
>csel.l(8)       g48<1>F         g83<4,4,1>F     g82<4,4,1>F     g49<4,4,1>F { align16 1Q };
>add(8)          g87<1>D         g36<8,8,1>D     g80<8,8,1>D     { align1 1Q compacted };
>shl(8)          g28<1>D         g87<8,8,1>D     0x00000002UD    { align1 1Q };
>send(8)         g88<1>UW        g28<8,8,1>UD    0x02106e10
>                            dp data 1 MsgDesc: ( untyped surface read, Surface = 16, SIMD8, Mask = 0xe) mlen 1 rlen 1 { align1 1Q };
>add(8)          g90<1>D         g36<8,8,1>D     g48<8,8,1>D     { align1 1Q compacted };
>shl(8)          g29<1>D         g90<8,8,1>D     0x00000002UD    { align1 1Q };
>mov(8)          g89<1>UD        g88<32,8,4>UB                   { align1 1Q };
>send(8)         g91<1>UW        g29<8,8,1>UD    0x02106e10
>                            dp data 1 MsgDesc: ( untyped surface read, Surface = 16, SIMD8, Mask = 0xe) mlen 1 rlen 1 { align1 1Q };
>shr(8)          g94<1>UD        g88<8,8,1>UD    0x00000008UD    { align1 1Q compacted };
>mov(8)          g53<1>UD        0x00000000UD                    { align1 1Q compacted };
>mov(8)          g31<1>UD        0x00000000UD                    { align1 1Q compacted };
>mov(8)          g30<1>D         1056964608D                     { align1 1Q };
>add(8)          g29<1>D         g94<8,8,1>D     g36<8,8,1>D     { align1 1Q compacted };
>mov(8)          g92<1>UD        g91<32,8,4>UB                   { align1 1Q };
>shr(8)          g93<1>UD        g91<8,8,1>UD    0x00000008UD    { align1 1Q compacted };
>   END B290 ->B291
>   START B292 <-B291 <-B309 (18 cycles)
>cmp.ge.f0.0(8)  null<1>UD       g53<8,8,1>UD    g89<8,8,1>UD    { align1 1Q compacted };
>   END B291 ->B292 ->B310
>(+f0.0) break(8) JIP: 1136      UIP: 1136                       { align1 1Q };
>   END B292 ->B291 ->B293
>   START B293 <-B292 (984 cycles)
>shl(8)          g38<1>D         g29<8,8,1>D     0x00000002UD    { align1 1Q };
>send(8)         g95<1>UW        g38<8,8,1>UD    0x02106e10
>                            dp data 1 MsgDesc: ( untyped surface read, Surface = 16, SIMD8, Mask = 0xe) mlen 1 rlen 1 { align1 1Q };
>add(8)          g100<1>D        g29<8,8,1>D     1D              { align1 1Q compacted };
>shl(8)          g39<1>D         g100<8,8,1>D    0x00000002UD    { align1 1Q };
>mov(8)          g96<1>F         g95<16,8,2>HF                   { align1 1Q };
>mov(8)          g57<1>F         g95.1<16,8,2>HF                 { align1 1Q };
>add(8)          g61<1>F         g96<8,8,1>F     -g103<8,8,1>F   { align1 1Q compacted };
>add(8)          g99<1>F         g57<8,8,1>F     -g49<8,8,1>F    { align1 1Q compacted };
>send(8)         g101<1>UW       g39<8,8,1>UD    0x02106e10
>                            dp data 1 MsgDesc: ( untyped surface read, Surface = 16, SIMD8, Mask = 0xe) mlen 1 rlen 1 { align1 1Q };
>add(8)          g106<1>D        g29<8,8,1>D     2D              { align1 1Q compacted };
>shl(8)          g40<1>D         g106<8,8,1>D    0x00000002UD    { align1 1Q };
>mov(8)          g102<1>F        g101<16,8,2>HF                  { align1 1Q };
>mov(8)          g5<1>F          g101.1<16,8,2>HF                { align1 1Q };
>add(8)          g50<1>F         g102<8,8,1>F    -g103<8,8,1>F   { align1 1Q compacted };
>add(8)          g105<1>F        g5<8,8,1>F      -g49<8,8,1>F    { align1 1Q compacted };
>send(8)         g107<1>UW       g40<8,8,1>UD    0x02106e10
>                            dp data 1 MsgDesc: ( untyped surface read, Surface = 16, SIMD8, Mask = 0xe) mlen 1 rlen 1 { align1 1Q };
>cmp.ge.f0.0(8)  null<1>F        g103<8,8,1>F    0x0F  /* 0F */  { align1 1Q compacted };
>mov(8)          g108<1>F        g107<16,8,2>HF                  { align1 1Q };
>mov(8)          g47<1>F         g107.1<16,8,2>HF                { align1 1Q };
>add(8)          g46<1>F         g108<8,8,1>F    -g103<8,8,1>F   { align1 1Q compacted };
>add(8)          g111<1>F        g47<8,8,1>F     -g49<8,8,1>F    { align1 1Q compacted };
>(+f0.0) if(8)   JIP: 72         UIP: 80                         { align1 1Q };
>   END B293 ->B294 ->B295
>   START B294 <-B293 (52 cycles)
>sel.ge(8)       g112<1>F        g50<8,8,1>F     g46<8,8,1>F     { align1 1Q compacted };
>sel.ge(8)       g113<1>F        g61<8,8,1>F     g112<8,8,1>F    { align1 1Q compacted };
>mul(8)          g114<1>F        g113<8,8,1>F    g58<8,8,1>F     { align1 1Q compacted };
>cmp.l.f0.0(8)   g38<1>F         g114<8,8,1>F    0xbf000000F  /* -0.5F */ { align1 1Q };
>else(8)         JIP: 24         UIP: 24                         { align1 1Q };
>   END B294 ->B296
>   START B295 <-B293 (2 cycles)
>mov(8)          g38<1>UD        0x00000000UD                    { align1 1Q compacted };
>   END B295 ->B296
>   START B296 <-B295 <-B294 (20 cycles)
>endif(8)        JIP: 776                                        { align1 1Q };
>mov.nz.f0.0(8)  null<1>D        g38<8,8,1>D                     { align1 1Q };
>(+f0.0) break(8) JIP: 744       UIP: 744                        { align1 1Q };
>   END B296 ->B291 ->B297
>   START B297 <-B296 (18 cycles)
>mov.nz.f0.0(8)  null<1>D        g35<8,8,1>D                     { align1 1Q };
>(+f0.0) if(8)   JIP: 72         UIP: 80                         { align1 1Q };
>   END B297 ->B298 ->B299
>   START B298 <-B297 (52 cycles)
>sel.l(8)        g115<1>F        g50<8,8,1>F     g46<8,8,1>F     { align1 1Q compacted };
>sel.l(8)        g116<1>F        g61<8,8,1>F     g115<8,8,1>F    { align1 1Q compacted };
>mul(8)          g117<1>F        g116<8,8,1>F    g58<8,8,1>F     { align1 1Q compacted };
>cmp.g.f0.0(8)   g39<1>F         g117<8,8,1>F    0x3f000000F  /* 0.5F */ { align1 1Q };
>else(8)         JIP: 24         UIP: 24                         { align1 1Q };
>   END B298 ->B300
>   START B299 <-B297 (2 cycles)
>mov(8)          g39<1>UD        0x00000000UD                    { align1 1Q compacted };
>   END B299 ->B300
>   START B300 <-B299 <-B298 (20 cycles)
>endif(8)        JIP: 632                                        { align1 1Q };
>mov.nz.f0.0(8)  null<1>D        g39<8,8,1>D                     { align1 1Q };
>(+f0.0) break(8) JIP: 600       UIP: 600                        { align1 1Q };
>   END B300 ->B291 ->B301
>   START B301 <-B300 (148 cycles)
>cmp.g.f0.0(8)   null<1>F        g99<8,8,1>F     0x0F  /* 0F */  { align1 1Q compacted };
>(-f0.0) sel(8)  g118<1>UD       g64<8,8,1>UD    0x00000002UD    { align1 1Q };
>cmp.g.f0.0(8)   null<1>F        g105<8,8,1>F    0x0F  /* 0F */  { align1 1Q compacted };
>(-f0.0) sel(8)  g119<1>UD       g64<8,8,1>UD    0x00000004UD    { align1 1Q };
>or(8)           g121<1>UD       g118<8,8,1>UD   g119<8,8,1>UD   { align1 1Q compacted };
>cmp.g.f0.0(8)   null<1>F        g111<8,8,1>F    0x0F  /* 0F */  { align1 1Q compacted };
>(-f0.0) sel(8)  g120<1>UD       g64<8,8,1>UD    0x00000008UD    { align1 1Q };
>or(8)           g122<1>UD       g121<8,8,1>UD   g120<8,8,1>UD   { align1 1Q compacted };
>shr(8)          g123<1>UD       g74<8,8,1>UD    g122<8,8,1>UD   { align1 1Q compacted };
>and.nz.f0.0(8)  g124<1>UD       g123<8,8,1>UD   0x00000003UD    { align1 1Q compacted };
>(+f0.0) if(8)   JIP: 448        UIP: 448                        { align1 1Q };
>   END B301 ->B302 ->B309
>   START B302 <-B301 (132 cycles)
>mad(8)          g125<1>F        g61<4,4,1>F     g50<4,4,1>F     -g59.1<0,1,0>F { align16 1Q };
>mad(8)          g126<1>F        g99<4,4,1>F     g105<4,4,1>F    -g59.1<0,1,0>F { align16 1Q };
>add(8)          g3<1>F          g61<8,8,1>F     -g50<8,8,1>F    { align1 1Q compacted };
>add(8)          g4<1>F          g99<8,8,1>F     -g105<8,8,1>F   { align1 1Q compacted };
>add(8)          g127<1>F        g125<8,8,1>F    g46<8,8,1>F     { align1 1Q compacted };
>add(8)          g2<1>F          g126<8,8,1>F    g111<8,8,1>F    { align1 1Q compacted };
>math inv(8)     g6<1>F          g2<8,8,1>F      null<8,8,1>F    { align1 1Q compacted };
>mul(8)          g8<1>F          g2<8,8,1>F      g99<8,8,1>F     { align1 1Q compacted };
>cmp.l.f0.0(8)   null<1>F        (abs)g2<8,8,1>F 0x38d1b717F  /* 0.0001F */ { align1 1Q };
>mad(8)          g9<1>F          -g8<4,4,1>F     g4<4,4,1>F      g4<4,4,1>F { align16 1Q compacted };
>sel.ge(8)       g11<1>F         g9<8,8,1>F      0x0F  /* 0F */  { align1 1Q compacted };
>math sqrt(8)    g12<1>F         g11<8,8,1>F     null<8,8,1>F    { align1 1Q compacted };
>add(8)          g13<1>F         g4<8,8,1>F      -g12<8,8,1>F    { align1 1Q compacted };
>add(8)          g14<1>F         g4<8,8,1>F      g12<8,8,1>F     { align1 1Q compacted };
>mul(8)          g40<1>F         g13<8,8,1>F     g6<8,8,1>F      { align1 1Q compacted };
>mul(8)          g41<1>F         g14<8,8,1>F     g6<8,8,1>F      { align1 1Q compacted };
>(+f0.0) if(8)   JIP: 56         UIP: 56                         { align1 1Q };
>   END B302 ->B303 ->B304
>   START B303 <-B302 (38 cycles)
>mul(8)          g15<1>F         g99<8,8,1>F     0x3f000000F  /* 0.5F */ { align1 1Q };
>math inv(8)     g16<1>F         g4<8,8,1>F      null<8,8,1>F    { align1 1Q compacted };
>mul(8)          g41<1>F         g15<8,8,1>F     g16<8,8,1>F     { align1 1Q compacted };
>mov(8)          g40<1>D         g41<8,8,1>D                     { align1 1Q compacted };
>   END B303 ->B304
>   START B304 <-B302 <-B303 (65 cycles)
>endif(8)        JIP: 224                                        { align1 1Q };
>mul(8)          g17<1>F         g3<8,8,1>F      0x40000000F  /* 2F */ { align1 1Q };
>and.nz.f0.0(8)  null<1>UD       g124<8,8,1>UD   0x00000001UD    { align1 1Q compacted };
>mad(8)          g18<1>F         -g17<4,4,1>F    g40<4,4,1>F     g127<4,4,1>F { align16 1Q compacted };
>mad(8)          g20<1>F         -g17<4,4,1>F    g41<4,4,1>F     g127<4,4,1>F { align16 1Q compacted };
>mad(8)          g19<1>F         g61<4,4,1>F     g40<4,4,1>F     g18<4,4,1>F { align16 1Q compacted };
>mad(8)          g21<1>F         g61<4,4,1>F     g41<4,4,1>F     g20<4,4,1>F { align16 1Q compacted };
>mul(8)          g22<1>F         g58<8,8,1>F     g19<8,8,1>F     { align1 1Q compacted };
>mul(8)          g23<1>F         g58<8,8,1>F     g21<8,8,1>F     { align1 1Q compacted };
>(+f0.0) if(8)   JIP: 48         UIP: 48                         { align1 1Q };
>   END B304 ->B305 ->B306
>   START B305 <-B304 (22 cycles)
>mad.sat(8)      g24<1>F         g59.0<0,1,0>F   g79<4,4,1>F     g22<4,4,1>F { align16 1Q };
>sel.l(8)        g30<1>F         g30<8,8,1>F     (abs)g22<8,8,1>F { align1 1Q compacted };
>add(8)          g31<1>F         g31<8,8,1>F     g24<8,8,1>F     { align1 1Q compacted };
>   END B305 ->B306
>   START B306 <-B304 <-B305 (20 cycles)
>endif(8)        JIP: 88                                         { align1 1Q };
>cmp.g.f0.0(8)   null<1>UD       g124<8,8,1>UD   0x00000001UD    { align1 1Q compacted };
>(+f0.0) if(8)   JIP: 48         UIP: 48                         { align1 1Q };
>   END B306 ->B307 ->B308
>   START B307 <-B306 (22 cycles)
>mad.sat(8)      g25<1>F         g59.0<0,1,0>F   g79<4,4,1>F     g23<4,4,1>F { align16 1Q };
>sel.l(8)        g30<1>F         g30<8,8,1>F     (abs)g23<8,8,1>F { align1 1Q compacted };
>add(8)          g31<1>F         g31<8,8,1>F     -g25<8,8,1>F    { align1 1Q compacted };
>   END B307 ->B308
>   START B308 <-B306 <-B307 (2 cycles)
>endif(8)        JIP: 16                                         { align1 1Q };
>   END B308 ->B309
>   START B309 <-B301 <-B308 (8 cycles)
>endif(8)        JIP: 32                                         { align1 1Q };
>add(8)          g29<1>D         g29<8,8,1>D     3D              { align1 1Q compacted };
>add(8)          g53<1>D         g53<8,8,1>D     1D              { align1 1Q compacted };
>while(8)        JIP: -1144                                      { align1 1Q };
>   END B309 ->B292
>   START B310 <-B291 (10 cycles)
>mov(8)          g42<1>F         (abs)g31<8,8,1>F                { align1 1Q compacted };
>add(8)          g43<1>D         g93<8,8,1>D     g36<8,8,1>D     { align1 1Q compacted };
>mov(8)          g110<1>UD       0x00000000UD                    { align1 1Q compacted };
>mov(8)          g45<1>UD        0x00000000UD                    { align1 1Q compacted };
>mov(8)          g44<1>D         1056964608D                     { align1 1Q };
>   END B310 ->B311
>   START B312 <-B311 <-B329 (18 cycles)
>cmp.ge.f0.0(8)  null<1>UD       g110<8,8,1>UD   g92<8,8,1>UD    { align1 1Q compacted };
>   END B311 ->B312 ->B330
>(+f0.0) break(8) JIP: 1136      UIP: 1136                       { align1 1Q };
>   END B312 ->B311 ->B313
>   START B313 <-B312 (984 cycles)
>shl(8)          g41<1>D         g43<8,8,1>D     0x00000002UD    { align1 1Q };
>send(8)         g26<1>UW        g41<8,8,1>UD    0x02106e10
>                            dp data 1 MsgDesc: ( untyped surface read, Surface = 16, SIMD8, Mask = 0xe) mlen 1 rlen 1 { align1 1Q };
>add(8)          g38<1>D         g43<8,8,1>D     1D              { align1 1Q compacted };
>shl(8)          g109<1>D        g38<8,8,1>D     0x00000002UD    { align1 1Q };
>mov(8)          g27<1>F         g26<16,8,2>HF                   { align1 1Q };
>mov(8)          g28<1>F         g26.1<16,8,2>HF                 { align1 1Q };
>add(8)          g29<1>F         g27<8,8,1>F     -g49<8,8,1>F    { align1 1Q compacted };
>add(8)          g53<1>F         g28<8,8,1>F     -g103<8,8,1>F   { align1 1Q compacted };
>send(8)         g39<1>UW        g109<8,8,1>UD   0x02106e10
>                            dp data 1 MsgDesc: ( untyped surface read, Surface = 16, SIMD8, Mask = 0xe) mlen 1 rlen 1 { align1 1Q };
>add(8)          g72<1>D         g43<8,8,1>D     2D              { align1 1Q compacted };
>shl(8)          g71<1>D         g72<8,8,1>D     0x00000002UD    { align1 1Q };
>mov(8)          g40<1>F         g39<16,8,2>HF                   { align1 1Q };
>mov(8)          g41<1>F         g39.1<16,8,2>HF                 { align1 1Q };
>add(8)          g36<1>F         g40<8,8,1>F     -g49<8,8,1>F    { align1 1Q compacted };
>add(8)          g54<1>F         g41<8,8,1>F     -g103<8,8,1>F   { align1 1Q compacted };
>send(8)         g58<1>UW        g71<8,8,1>UD    0x02106e10
>                            dp data 1 MsgDesc: ( untyped surface read, Surface = 16, SIMD8, Mask = 0xe) mlen 1 rlen 1 { align1 1Q };
>cmp.ge.f0.0(8)  null<1>F        g49<8,8,1>F     0x0F  /* 0F */  { align1 1Q compacted };
>mov(8)          g62<1>F         g58<16,8,2>HF                   { align1 1Q };
>mov(8)          g63<1>F         g58.1<16,8,2>HF                 { align1 1Q };
>add(8)          g51<1>F         g62<8,8,1>F     -g49<8,8,1>F    { align1 1Q compacted };
>add(8)          g65<1>F         g63<8,8,1>F     -g103<8,8,1>F   { align1 1Q compacted };
>(+f0.0) if(8)   JIP: 72         UIP: 80                         { align1 1Q };
>   END B313 ->B314 ->B315
>   START B314 <-B313 (52 cycles)
>sel.ge(8)       g66<1>F         g36<8,8,1>F     g51<8,8,1>F     { align1 1Q compacted };
>sel.ge(8)       g67<1>F         g29<8,8,1>F     g66<8,8,1>F     { align1 1Q compacted };
>mul(8)          g69<1>F         g67<8,8,1>F     g98<8,8,1>F     { align1 1Q compacted };
>cmp.l.f0.0(8)   g109<1>F        g69<8,8,1>F     0xbf000000F  /* -0.5F */ { align1 1Q };
>else(8)         JIP: 24         UIP: 24                         { align1 1Q };
>   END B314 ->B316
>   START B315 <-B313 (2 cycles)
>mov(8)          g109<1>UD       0x00000000UD                    { align1 1Q compacted };
>   END B315 ->B316
>   START B316 <-B315 <-B314 (20 cycles)
>endif(8)        JIP: 776                                        { align1 1Q };
>mov.nz.f0.0(8)  null<1>D        g109<8,8,1>D                    { align1 1Q };
>(+f0.0) break(8) JIP: 744       UIP: 744                        { align1 1Q };
>   END B316 ->B311 ->B317
>   START B317 <-B316 (18 cycles)
>mov.nz.f0.0(8)  null<1>D        g84<8,8,1>D                     { align1 1Q };
>(+f0.0) if(8)   JIP: 72         UIP: 80                         { align1 1Q };
>   END B317 ->B318 ->B319
>   START B318 <-B317 (52 cycles)
>sel.l(8)        g70<1>F         g36<8,8,1>F     g51<8,8,1>F     { align1 1Q compacted };
>sel.l(8)        g52<1>F         g29<8,8,1>F     g70<8,8,1>F     { align1 1Q compacted };
>mul(8)          g55<1>F         g52<8,8,1>F     g98<8,8,1>F     { align1 1Q compacted };
>cmp.g.f0.0(8)   g71<1>F         g55<8,8,1>F     0x3f000000F  /* 0.5F */ { align1 1Q };
>else(8)         JIP: 24         UIP: 24                         { align1 1Q };
>   END B318 ->B320
>   START B319 <-B317 (2 cycles)
>mov(8)          g71<1>UD        0x00000000UD                    { align1 1Q compacted };
>   END B319 ->B320
>   START B320 <-B319 <-B318 (20 cycles)
>endif(8)        JIP: 632                                        { align1 1Q };
>mov.nz.f0.0(8)  null<1>D        g71<8,8,1>D                     { align1 1Q };
>(+f0.0) break(8) JIP: 600       UIP: 600                        { align1 1Q };
>   END B320 ->B311 ->B321
>   START B321 <-B320 (148 cycles)
>cmp.g.f0.0(8)   null<1>F        g53<8,8,1>F     0x0F  /* 0F */  { align1 1Q compacted };
>(-f0.0) sel(8)  g73<1>UD        g64<8,8,1>UD    0x00000002UD    { align1 1Q };
>cmp.g.f0.0(8)   null<1>F        g54<8,8,1>F     0x0F  /* 0F */  { align1 1Q compacted };
>(-f0.0) sel(8)  g56<1>UD        g64<8,8,1>UD    0x00000004UD    { align1 1Q };
>or(8)           g76<1>UD        g73<8,8,1>UD    g56<8,8,1>UD    { align1 1Q compacted };
>cmp.g.f0.0(8)   null<1>F        g65<8,8,1>F     0x0F  /* 0F */  { align1 1Q compacted };
>(-f0.0) sel(8)  g75<1>UD        g64<8,8,1>UD    0x00000008UD    { align1 1Q };
>or(8)           g77<1>UD        g76<8,8,1>UD    g75<8,8,1>UD    { align1 1Q compacted };
>shr(8)          g35<1>UD        g74<8,8,1>UD    g77<8,8,1>UD    { align1 1Q compacted };
>and.nz.f0.0(8)  g79<1>UD        g35<8,8,1>UD    0x00000003UD    { align1 1Q compacted };
>(+f0.0) if(8)   JIP: 448        UIP: 448                        { align1 1Q };
>   END B321 ->B322 ->B329
>   START B322 <-B321 (132 cycles)
>mad(8)          g80<1>F         g29<4,4,1>F     g36<4,4,1>F     -g59.1<0,1,0>F { align16 1Q };
>mad(8)          g81<1>F         g53<4,4,1>F     g54<4,4,1>F     -g59.1<0,1,0>F { align16 1Q };
>add(8)          g48<1>F         g29<8,8,1>F     -g36<8,8,1>F    { align1 1Q compacted };
>add(8)          g87<1>F         g53<8,8,1>F     -g54<8,8,1>F    { align1 1Q compacted };
>add(8)          g82<1>F         g80<8,8,1>F     g51<8,8,1>F     { align1 1Q compacted };
>add(8)          g83<1>F         g81<8,8,1>F     g65<8,8,1>F     { align1 1Q compacted };
>math inv(8)     g88<1>F         g83<8,8,1>F     null<8,8,1>F    { align1 1Q compacted };
>mul(8)          g89<1>F         g83<8,8,1>F     g53<8,8,1>F     { align1 1Q compacted };
>cmp.l.f0.0(8)   null<1>F        (abs)g83<8,8,1>F 0x38d1b717F  /* 0.0001F */ { align1 1Q };
>mad(8)          g90<1>F         -g89<4,4,1>F    g87<4,4,1>F     g87<4,4,1>F { align16 1Q compacted };
>sel.ge(8)       g91<1>F         g90<8,8,1>F     0x0F  /* 0F */  { align1 1Q compacted };
>math sqrt(8)    g93<1>F         g91<8,8,1>F     null<8,8,1>F    { align1 1Q compacted };
>add(8)          g94<1>F         g87<8,8,1>F     -g93<8,8,1>F    { align1 1Q compacted };
>add(8)          g95<1>F         g87<8,8,1>F     g93<8,8,1>F     { align1 1Q compacted };
>mul(8)          g36<1>F         g94<8,8,1>F     g88<8,8,1>F     { align1 1Q compacted };
>mul(8)          g54<1>F         g95<8,8,1>F     g88<8,8,1>F     { align1 1Q compacted };
>(+f0.0) if(8)   JIP: 56         UIP: 56                         { align1 1Q };
>   END B322 ->B323 ->B324
>   START B323 <-B322 (38 cycles)
>mul(8)          g96<1>F         g53<8,8,1>F     0x3f000000F  /* 0.5F */ { align1 1Q };
>math inv(8)     g57<1>F         g87<8,8,1>F     null<8,8,1>F    { align1 1Q compacted };
>mul(8)          g54<1>F         g96<8,8,1>F     g57<8,8,1>F     { align1 1Q compacted };
>mov(8)          g36<1>D         g54<8,8,1>D                     { align1 1Q compacted };
>   END B323 ->B324
>   START B324 <-B322 <-B323 (64 cycles)
>endif(8)        JIP: 224                                        { align1 1Q };
>mul(8)          g61<1>F         g48<8,8,1>F     0x40000000F  /* 2F */ { align1 1Q };
>and.nz.f0.0(8)  null<1>UD       g79<8,8,1>UD    0x00000001UD    { align1 1Q compacted };
>mad(8)          g99<1>F         -g61<4,4,1>F    g36<4,4,1>F     g82<4,4,1>F { align16 1Q compacted };
>mad(8)          g101<1>F        -g61<4,4,1>F    g54<4,4,1>F     g82<4,4,1>F { align16 1Q compacted };
>mad(8)          g100<1>F        g29<4,4,1>F     g36<4,4,1>F     g99<4,4,1>F { align16 1Q compacted };
>mad(8)          g102<1>F        g29<4,4,1>F     g54<4,4,1>F     g101<4,4,1>F { align16 1Q compacted };
>mul(8)          g5<1>F          g98<8,8,1>F     g100<8,8,1>F    { align1 1Q compacted };
>mul(8)          g50<1>F         g98<8,8,1>F     g102<8,8,1>F    { align1 1Q compacted };
>(+f0.0) if(8)   JIP: 48         UIP: 48                         { align1 1Q };
>   END B324 ->B325 ->B326
>   START B325 <-B324 (22 cycles)
>mad.sat(8)      g105<1>F        g59.0<0,1,0>F   g85<4,4,1>F     g5<4,4,1>F { align16 1Q };
>sel.l(8)        g44<1>F         g44<8,8,1>F     (abs)g5<8,8,1>F { align1 1Q compacted };
>add(8)          g45<1>F         g45<8,8,1>F     g105<8,8,1>F    { align1 1Q compacted };
>   END B325 ->B326
>   START B326 <-B324 <-B325 (20 cycles)
>endif(8)        JIP: 88                                         { align1 1Q };
>cmp.g.f0.0(8)   null<1>UD       g79<8,8,1>UD    0x00000001UD    { align1 1Q compacted };
>(+f0.0) if(8)   JIP: 48         UIP: 48                         { align1 1Q };
>   END B326 ->B327 ->B328
>   START B327 <-B326 (22 cycles)
>mad.sat(8)      g106<1>F        g59.0<0,1,0>F   g85<4,4,1>F     g50<4,4,1>F { align16 1Q };
>sel.l(8)        g44<1>F         g44<8,8,1>F     (abs)g50<8,8,1>F { align1 1Q compacted };
>add(8)          g45<1>F         g45<8,8,1>F     -g106<8,8,1>F   { align1 1Q compacted };
>   END B327 ->B328
>   START B328 <-B326 <-B327 (2 cycles)
>endif(8)        JIP: 16                                         { align1 1Q };
>   END B328 ->B329
>   START B329 <-B321 <-B328 (8 cycles)
>endif(8)        JIP: 32                                         { align1 1Q };
>add(8)          g43<1>D         g43<8,8,1>D     3D              { align1 1Q compacted };
>add(8)          g110<1>D        g110<8,8,1>D    1D              { align1 1Q compacted };
>while(8)        JIP: -1144                                      { align1 1Q };
>   END B329 ->B312
>   START B330 <-B311 (20 cycles)
>mov(8)          g72<1>F         (abs)g45<8,8,1>F                { align1 1Q compacted };
>mov.nz.f0.0(8)  null<1>D        g97<8,8,1>D                     { align1 1Q };
>(+f0.0) if(8)   JIP: 96         UIP: 96                         { align1 1Q };
>   END B330 ->B331 ->B332
>   START B331 <-B330 (36 cycles)
>mul(8)          g107<1>F        (abs)g31<8,8,1>F 0x3f000000F  /* 0.5F */ { align1 1Q };
>mul(8)          g108<1>F        (abs)g45<8,8,1>F 0x3f000000F  /* 0.5F */ { align1 1Q };
>frc(8)          g47<1>F         g107<8,8,1>F                    { align1 1Q compacted };
>frc(8)          g46<1>F         g108<8,8,1>F                    { align1 1Q compacted };
>mul(8)          g42<1>F         g47<8,8,1>F     0x40000000F  /* 2F */ { align1 1Q };
>mul(8)          g72<1>F         g46<8,8,1>F     0x40000000F  /* 2F */ { align1 1Q };
>   END B331 ->B332
>   START B332 <-B330 <-B331 (74 cycles)
>endif(8)        JIP: 296                                        { align1 1Q };
>sel.sat.l(8)    g111<1>F        (abs)g30<8,8,1>F 0x3f000000F  /* 0.5F */ { align1 1Q };
>sel.sat.l(8)    g112<1>F        (abs)g44<8,8,1>F 0x3f000000F  /* 0.5F */ { align1 1Q };
>mad(8)          g113<1>F        g68.4<0,1,0>F   g111<4,4,1>F    -g59.1<0,1,0>F { align16 1Q };
>mad(8)          g114<1>F        g68.4<0,1,0>F   g112<4,4,1>F    -g59.1<0,1,0>F { align16 1Q };
>add(8)          g115<1>F        g113<8,8,1>F    g114<8,8,1>F    { align1 1Q compacted };
>cmp.g.f0.0(8)   null<1>F        g115<8,8,1>F    0x3a83126fF  /* 0.001F */ { align1 1Q };
>(+f0.0) if(8)   JIP: 64         UIP: 88                         { align1 1Q };
>   END B332 ->B333 ->B334
>   START B333 <-B332 (40 cycles)
>mul(8)          g116<1>F        g72<8,8,1>F     g114<8,8,1>F    { align1 1Q compacted };
>math inv(8)     g118<1>F        g115<8,8,1>F    null<8,8,1>F    { align1 1Q compacted };
>mad(8)          g117<1>F        g116<4,4,1>F    g113<4,4,1>F    g42<4,4,1>F { align16 1Q compacted };
>mul(8)          g37<1>F         g117<8,8,1>F    g118<8,8,1>F    { align1 1Q compacted };
>else(8)         JIP: 40         UIP: 40                         { align1 1Q };
>   END B333 ->B335
>   START B334 <-B332 (18 cycles)
>add(8)          g119<1>F        g42<8,8,1>F     g72<8,8,1>F     { align1 1Q compacted };
>mul(8)          g37<1>F         g119<8,8,1>F    0x3f000000F  /* 0.5F */ { align1 1Q };
>   END B334 ->B335
>   START B335 <-B334 <-B333 (20 cycles)
>endif(8)        JIP: 104                                        { align1 1Q };
>and.nz.f0.0(8)  null<1>UD       g7.3<0,1,0>UD   0x40000000UD    { align1 1Q };
>(+f0.0) if(8)   JIP: 32         UIP: 32                         { align1 1Q };
>   END B335 ->B336 ->B337
>   START B336 <-B335 (2 cycles)
>add(8)          g37<1>F         -g37<8,8,1>F    0x3f800000F  /* 1F */ { align1 1Q };
>   END B336 ->B337
>   START B337 <-B335 <-B336 (8 cycles)
>endif(8)        JIP: 40                                         { align1 1Q };
>mov(8)          g32<1>D         g37<8,8,1>D                     { align1 1Q compacted };
>mov(8)          g33<1>D         g37<8,8,1>D                     { align1 1Q compacted };
>mov(8)          g34<1>D         g37<8,8,1>D                     { align1 1Q compacted };
>   END B337 ->B338
>   START B338 <-B289 <-B337 (2 cycles)
>endif(8)        JIP: 16                                         { align1 1Q };
>   END B338 ->B339
>   START B339 <-B338 <-B288 (2 cycles)
>endif(8)        JIP: 16                                         { align1 1Q };
>   END B339 ->B340
>   START B340 <-B339 <-B181 (2 cycles)
>endif(8)        JIP: 16                                         { align1 1Q };
>   END B340 ->B341
>   START B341 <-B340 <-B155 (2 cycles)
>endif(8)        JIP: 16                                         { align1 1Q };
>   END B341 ->B342
>   START B342 <-B341 <-B129 (4 cycles)
>endif(8)        JIP: 16                                         { align1 1Q };
>else(8)         JIP: 80         UIP: 80                         { align1 1Q };
>   END B342 ->B344
>   START B343 <-B127 (8 cycles)
>mov(8)          g32<1>D         1065353216D                     { align1 1Q };
>mov(8)          g33<1>D         1065353216D                     { align1 1Q };
>mov(8)          g34<1>D         1065353216D                     { align1 1Q };
>mov(8)          g37<1>D         1065353216D                     { align1 1Q };
>   END B343 ->B344
>   START B344 <-B343 <-B342 (4 cycles)
>endif(8)        JIP: 16                                         { align1 1Q };
>else(8)         JIP: 80         UIP: 80                         { align1 1Q };
>   END B344 ->B346
>   START B345 <-B126 (8 cycles)
>mov(8)          g32<1>D         1065353216D                     { align1 1Q };
>mov(8)          g33<1>D         1065353216D                     { align1 1Q };
>mov(8)          g34<1>D         1065353216D                     { align1 1Q };
>mov(8)          g37<1>D         1065353216D                     { align1 1Q };
>   END B345 ->B346
>   START B346 <-B345 <-B344 (2 cycles)
>endif(8)        JIP: 16                                         { align1 1Q };
>   END B346 ->B347
>   START B347 <-B346 <-B125 (2 cycles)
>endif(8)        JIP: 16                                         { align1 1Q };
>   END B347 ->B348
>   START B348 <-B347 <-B123 (12 cycles)
>endif(8)        JIP: 48                                         { align1 1Q };
>mul(8)          g120<1>F        g60<8,8,1>F     g37<8,8,1>F     { align1 1Q compacted };
>mul(8)          g121<1>F        g104<8,8,1>F    g34<8,8,1>F     { align1 1Q compacted };
>mul(8)          g122<1>F        g78<8,8,1>F     g33<8,8,1>F     { align1 1Q compacted };
>mul(8)          g123<1>F        g86<8,8,1>F     g32<8,8,1>F     { align1 1Q compacted };
>else(8)         JIP: 48         UIP: 48                         { align1 1Q };
>   END B348 ->B350
>   START B349 <-B0 (8 cycles)
>mov(8)          g123<1>UD       0x00000000UD                    { align1 1Q compacted };
>mov(8)          g122<1>UD       0x00000000UD                    { align1 1Q compacted };
>mov(8)          g121<1>UD       0x00000000UD                    { align1 1Q compacted };
>mov(8)          g120<1>UD       0x00000000UD                    { align1 1Q compacted };
>   END B349 ->B350
>   START B350 <-B349 <-B348 (20 cycles)
>endif(8)        JIP: 16                                         { align1 1Q };
>cmp.nz.f0.0(8)  null<1>D        g10.7<0,1,0>D   1D              { align1 1Q };
>(+f0.0) if(8)   JIP: 1648       UIP: 1712                       { align1 1Q };
>   END B350 ->B351 ->B393
>   START B351 <-B350 (18 cycles)
>cmp.nz.f0.0(8)  null<1>D        g10.7<0,1,0>D   2D              { align1 1Q };
>(+f0.0) if(8)   JIP: 1552       UIP: 1584                       { align1 1Q };
>   END B351 ->B352 ->B391
>   START B352 <-B351 (18 cycles)
>cmp.nz.f0.0(8)  null<1>D        g10.7<0,1,0>D   3D              { align1 1Q };
>(+f0.0) if(8)   JIP: 1392       UIP: 1488                       { align1 1Q };
>   END B352 ->B353 ->B389
>   START B353 <-B352 (18 cycles)
>cmp.z.f0.0(8)   null<1>D        g10.7<0,1,0>D   4D              { align1 1Q };
>(+f0.0) if(8)   JIP: 72         UIP: 1328                       { align1 1Q };
>   END B353 ->B354 ->B355
>   START B354 <-B353 (24 cycles)
>add(8)          g124<1>F        -g123<8,8,1>F   0x3f800000F  /* 1F */ { align1 1Q };
>mov(8)          g127<1>D        g124<8,8,1>D                    { align1 1Q compacted };
>mov(8)          g126<1>D        g124<8,8,1>D                    { align1 1Q compacted };
>mov(8)          g125<1>D        g124<8,8,1>D                    { align1 1Q compacted };
>else(8)         JIP: 1272       UIP: 1272                       { align1 1Q };
>   END B354 ->B388
>   START B355 <-B353 (18 cycles)
>cmp.nz.f0.0(8)  null<1>D        g10.7<0,1,0>D   5D              { align1 1Q };
>(+f0.0) if(8)   JIP: 1160       UIP: 1224                       { align1 1Q };
>   END B355 ->B356 ->B386
>   START B356 <-B355 (18 cycles)
>cmp.nz.f0.0(8)  null<1>D        g10.7<0,1,0>D   6D              { align1 1Q };
>(+f0.0) if(8)   JIP: 1064       UIP: 1096                       { align1 1Q };
>   END B356 ->B357 ->B384
>   START B357 <-B356 (18 cycles)
>cmp.nz.f0.0(8)  null<1>D        g10.7<0,1,0>D   7D              { align1 1Q };
>(+f0.0) if(8)   JIP: 936        UIP: 1000                       { align1 1Q };
>   END B357 ->B358 ->B382
>   START B358 <-B357 (18 cycles)
>cmp.nz.f0.0(8)  null<1>D        g10.7<0,1,0>D   8D              { align1 1Q };
>(+f0.0) if(8)   JIP: 840        UIP: 872                        { align1 1Q };
>   END B358 ->B359 ->B380
>   START B359 <-B358 (18 cycles)
>cmp.z.f0.0(8)   null<1>D        g10.7<0,1,0>D   9D              { align1 1Q };
>(+f0.0) if(8)   JIP: 104        UIP: 776                        { align1 1Q };
>   END B359 ->B360 ->B361
>   START B360 <-B359 (24 cycles)
>add(8)          g124<1>F        -g123<8,8,1>F   0x3f800000F  /* 1F */ { align1 1Q };
>mov(8)          g122<1>UD       0x00000000UD                    { align1 1Q compacted };
>mov(8)          g121<1>UD       0x00000000UD                    { align1 1Q compacted };
>mov(8)          g120<1>UD       0x00000000UD                    { align1 1Q compacted };
>mov(8)          g123<1>UD       0x00000000UD                    { align1 1Q compacted };
>mov(8)          g127<1>D        g124<8,8,1>D                    { align1 1Q compacted };
>mov(8)          g126<1>D        g124<8,8,1>D                    { align1 1Q compacted };
>mov(8)          g125<1>D        g124<8,8,1>D                    { align1 1Q compacted };
>else(8)         JIP: 688        UIP: 688                        { align1 1Q };
>   END B360 ->B379
>   START B361 <-B359 (18 cycles)
>cmp.z.f0.0(8)   null<1>D        g10.7<0,1,0>D   10D             { align1 1Q };
>(+f0.0) if(8)   JIP: 72         UIP: 640                        { align1 1Q };
>   END B361 ->B362 ->B363
>   START B362 <-B361 (24 cycles)
>add(8)          g124<1>F        -g123<8,8,1>F   0x3f800000F  /* 1F */ { align1 1Q };
>mov(8)          g127<1>D        g124<8,8,1>D                    { align1 1Q compacted };
>mov(8)          g126<1>D        g124<8,8,1>D                    { align1 1Q compacted };
>mov(8)          g125<1>D        g124<8,8,1>D                    { align1 1Q compacted };
>else(8)         JIP: 584        UIP: 584                        { align1 1Q };
>   END B362 ->B378
>   START B363 <-B361 (18 cycles)
>cmp.nz.f0.0(8)  null<1>D        g10.7<0,1,0>D   11D             { align1 1Q };
>(+f0.0) if(8)   JIP: 504        UIP: 536                        { align1 1Q };
>   END B363 ->B364 ->B376
>   START B364 <-B363 (18 cycles)
>cmp.z.f0.0(8)   null<1>D        g10.7<0,1,0>D   12D             { align1 1Q };
>(+f0.0) if(8)   JIP: 72         UIP: 440                        { align1 1Q };
>   END B364 ->B365 ->B366
>   START B365 <-B364 (24 cycles)
>add(8)          g124<1>F        -g123<8,8,1>F   0x3f800000F  /* 1F */ { align1 1Q };
>mov(8)          g127<1>D        g124<8,8,1>D                    { align1 1Q compacted };
>mov(8)          g126<1>D        g124<8,8,1>D                    { align1 1Q compacted };
>mov(8)          g125<1>D        g124<8,8,1>D                    { align1 1Q compacted };
>else(8)         JIP: 384        UIP: 384                        { align1 1Q };
>   END B365 ->B375
>   START B366 <-B364 (18 cycles)
>cmp.nz.f0.0(8)  null<1>D        g10.7<0,1,0>D   13D             { align1 1Q };
>(+f0.0) if(8)   JIP: 272        UIP: 336                        { align1 1Q };
>   END B366 ->B367 ->B373
>   START B367 <-B366 (18 cycles)
>cmp.nz.f0.0(8)  null<1>D        g10.7<0,1,0>D   14D             { align1 1Q };
>(+f0.0) if(8)   JIP: 144        UIP: 208                        { align1 1Q };
>   END B367 ->B368 ->B371
>   START B368 <-B367 (18 cycles)
>cmp.z.f0.0(8)   null<1>D        g10.7<0,1,0>D   15D             { align1 1Q };
>(+f0.0) if(8)   JIP: 80         UIP: 80                         { align1 1Q };
>   END B368 ->B369 ->B370
>   START B369 <-B368 (8 cycles)
>add(8)          g124<1>F        -g120<8,8,1>F   0x3f800000F  /* 1F */ { align1 1Q };
>add(8)          g125<1>F        -g121<8,8,1>F   0x3f800000F  /* 1F */ { align1 1Q };
>add(8)          g126<1>F        -g122<8,8,1>F   0x3f800000F  /* 1F */ { align1 1Q };
>add(8)          g127<1>F        -g123<8,8,1>F   0x3f800000F  /* 1F */ { align1 1Q };
>   END B369 ->B370
>   START B370 <-B368 <-B369 (4 cycles)
>endif(8)        JIP: 16                                         { align1 1Q };
>else(8)         JIP: 80         UIP: 80                         { align1 1Q };
>   END B370 ->B372
>   START B371 <-B367 (16 cycles)
>mov(8)          g127<1>D        g123<8,8,1>D                    { align1 1Q compacted };
>mov(8)          g126<1>D        g122<8,8,1>D                    { align1 1Q compacted };
>mov(8)          g125<1>D        g121<8,8,1>D                    { align1 1Q compacted };
>mov(8)          g124<1>D        g120<8,8,1>D                    { align1 1Q compacted };
>mov(8)          g123<1>UD       0x00000000UD                    { align1 1Q compacted };
>mov(8)          g122<1>UD       0x00000000UD                    { align1 1Q compacted };
>mov(8)          g121<1>UD       0x00000000UD                    { align1 1Q compacted };
>mov(8)          g120<1>UD       0x00000000UD                    { align1 1Q compacted };
>   END B371 ->B372
>   START B372 <-B371 <-B370 (4 cycles)
>endif(8)        JIP: 16                                         { align1 1Q };
>else(8)         JIP: 80         UIP: 80                         { align1 1Q };
>   END B372 ->B374
>   START B373 <-B366 (8 cycles)
>mov(8)          g127<1>D        1065353216D                     { align1 1Q };
>mov(8)          g126<1>D        1065353216D                     { align1 1Q };
>mov(8)          g125<1>D        1065353216D                     { align1 1Q };
>mov(8)          g124<1>D        1065353216D                     { align1 1Q };
>   END B373 ->B374
>   START B374 <-B373 <-B372 (2 cycles)
>endif(8)        JIP: 16                                         { align1 1Q };
>   END B374 ->B375
>   START B375 <-B374 <-B365 (4 cycles)
>endif(8)        JIP: 16                                         { align1 1Q };
>else(8)         JIP: 48         UIP: 48                         { align1 1Q };
>   END B375 ->B377
>   START B376 <-B363 (8 cycles)
>mov(8)          g127<1>D        g123<8,8,1>D                    { align1 1Q compacted };
>mov(8)          g126<1>D        g123<8,8,1>D                    { align1 1Q compacted };
>mov(8)          g125<1>D        g123<8,8,1>D                    { align1 1Q compacted };
>mov(8)          g124<1>D        g123<8,8,1>D                    { align1 1Q compacted };
>   END B376 ->B377
>   START B377 <-B376 <-B375 (2 cycles)
>endif(8)        JIP: 16                                         { align1 1Q };
>   END B377 ->B378
>   START B378 <-B377 <-B362 (2 cycles)
>endif(8)        JIP: 16                                         { align1 1Q };
>   END B378 ->B379
>   START B379 <-B378 <-B360 (4 cycles)
>endif(8)        JIP: 16                                         { align1 1Q };
>else(8)         JIP: 48         UIP: 48                         { align1 1Q };
>   END B379 ->B381
>   START B380 <-B358 (8 cycles)
>mov(8)          g127<1>UD       0x00000000UD                    { align1 1Q compacted };
>mov(8)          g126<1>UD       0x00000000UD                    { align1 1Q compacted };
>mov(8)          g125<1>UD       0x00000000UD                    { align1 1Q compacted };
>mov(8)          g124<1>UD       0x00000000UD                    { align1 1Q compacted };
>   END B380 ->B381
>   START B381 <-B380 <-B379 (4 cycles)
>endif(8)        JIP: 16                                         { align1 1Q };
>else(8)         JIP: 80         UIP: 80                         { align1 1Q };
>   END B381 ->B383
>   START B382 <-B357 (28 cycles)
>mov(8)          g122<1>UD       0x00000000UD                    { align1 1Q compacted };
>mov(8)          g121<1>UD       0x00000000UD                    { align1 1Q compacted };
>mov(8)          g120<1>UD       0x00000000UD                    { align1 1Q compacted };
>mov(8)          g127<1>D        g123<8,8,1>D                    { align1 1Q compacted };
>mov(8)          g123<1>UD       0x00000000UD                    { align1 1Q compacted };
>mov(8)          g126<1>D        g127<8,8,1>D                    { align1 1Q compacted };
>mov(8)          g125<1>D        g127<8,8,1>D                    { align1 1Q compacted };
>mov(8)          g124<1>D        g127<8,8,1>D                    { align1 1Q compacted };
>   END B382 ->B383
>   START B383 <-B382 <-B381 (4 cycles)
>endif(8)        JIP: 16                                         { align1 1Q };
>else(8)         JIP: 48         UIP: 48                         { align1 1Q };
>   END B383 ->B385
>   START B384 <-B356 (8 cycles)
>mov(8)          g127<1>UD       0x00000000UD                    { align1 1Q compacted };
>mov(8)          g126<1>UD       0x00000000UD                    { align1 1Q compacted };
>mov(8)          g125<1>UD       0x00000000UD                    { align1 1Q compacted };
>mov(8)          g124<1>UD       0x00000000UD                    { align1 1Q compacted };
>   END B384 ->B385
>   START B385 <-B384 <-B383 (4 cycles)
>endif(8)        JIP: 16                                         { align1 1Q };
>else(8)         JIP: 80         UIP: 80                         { align1 1Q };
>   END B385 ->B387
>   START B386 <-B355 (8 cycles)
>mov(8)          g127<1>D        1065353216D                     { align1 1Q };
>mov(8)          g126<1>D        1065353216D                     { align1 1Q };
>mov(8)          g125<1>D        1065353216D                     { align1 1Q };
>mov(8)          g124<1>D        1065353216D                     { align1 1Q };
>   END B386 ->B387
>   START B387 <-B386 <-B385 (2 cycles)
>endif(8)        JIP: 16                                         { align1 1Q };
>   END B387 ->B388
>   START B388 <-B387 <-B354 (4 cycles)
>endif(8)        JIP: 16                                         { align1 1Q };
>else(8)         JIP: 112        UIP: 112                        { align1 1Q };
>   END B388 ->B390
>   START B389 <-B352 (16 cycles)
>mov(8)          g123<1>UD       0x00000000UD                    { align1 1Q compacted };
>mov(8)          g122<1>UD       0x00000000UD                    { align1 1Q compacted };
>mov(8)          g121<1>UD       0x00000000UD                    { align1 1Q compacted };
>mov(8)          g120<1>UD       0x00000000UD                    { align1 1Q compacted };
>mov(8)          g127<1>D        1065353216D                     { align1 1Q };
>mov(8)          g126<1>D        1065353216D                     { align1 1Q };
>mov(8)          g125<1>D        1065353216D                     { align1 1Q };
>mov(8)          g124<1>D        1065353216D                     { align1 1Q };
>   END B389 ->B390
>   START B390 <-B389 <-B388 (4 cycles)
>endif(8)        JIP: 16                                         { align1 1Q };
>else(8)         JIP: 48         UIP: 48                         { align1 1Q };
>   END B390 ->B392
>   START B391 <-B351 (8 cycles)
>mov(8)          g127<1>UD       0x00000000UD                    { align1 1Q compacted };
>mov(8)          g126<1>UD       0x00000000UD                    { align1 1Q compacted };
>mov(8)          g125<1>UD       0x00000000UD                    { align1 1Q compacted };
>mov(8)          g124<1>UD       0x00000000UD                    { align1 1Q compacted };
>   END B391 ->B392
>   START B392 <-B391 <-B390 (4 cycles)
>endif(8)        JIP: 16                                         { align1 1Q };
>else(8)         JIP: 80         UIP: 80                         { align1 1Q };
>   END B392 ->B394
>   START B393 <-B350 (16 cycles)
>mov(8)          g123<1>UD       0x00000000UD                    { align1 1Q compacted };
>mov(8)          g122<1>UD       0x00000000UD                    { align1 1Q compacted };
>mov(8)          g121<1>UD       0x00000000UD                    { align1 1Q compacted };
>mov(8)          g120<1>UD       0x00000000UD                    { align1 1Q compacted };
>mov(8)          g127<1>UD       0x00000000UD                    { align1 1Q compacted };
>mov(8)          g126<1>UD       0x00000000UD                    { align1 1Q compacted };
>mov(8)          g125<1>UD       0x00000000UD                    { align1 1Q compacted };
>mov(8)          g124<1>UD       0x00000000UD                    { align1 1Q compacted };
>   END B393 ->B394
>   START B394 <-B393 <-B392 (22 cycles)
>endif(8)        JIP: 16                                         { align1 1Q };
>mov(16)         g118<1>UD       g0<8,8,1>UD                     { align1 WE_all 1H compacted };
>sendc(8)        null<1>UW       g118<0,1,0>F    0x940b1200
>                            render MsgDesc: RT write SIMD8/DualSrcLow LastRT Surface = 0 mlen 10 rlen 0 { align1 1Q EOT };
>   END B394
>
>NIR (SSA form) for fragment shader:
>shader: MESA_SHADER_FRAGMENT
>name: BLORP-blit
>inputs: 0
>outputs: 0
>uniforms: 0
>shared: 0
>decl_var shader_in INTERP_MODE_FLAT vec4 coord_transform (VARYING_SLOT_VAR3, 34, 0)
>decl_var shader_in INTERP_MODE_FLAT uint src_z (VARYING_SLOT_VAR5.z, 36, 0)
>decl_var shader_in INTERP_MODE_SMOOTH vec4 gl_FragCoord (VARYING_SLOT_POS, 0, 0)
>decl_var shader_out INTERP_MODE_NONE vec4 gl_FragColor (FRAG_RESULT_COLOR, 4, 0)
>decl_function main (0 params)
>
>impl main {
>	block block_0:
>	/* preds: */
>	vec2 32 ssa_0 = intrinsic load_barycentric_pixel () (1) /* interp_mode=1 */
>	vec1 32 ssa_1 = load_const (0x00000000 /* 0.000000 */)
>	vec4 32 ssa_2 = intrinsic load_interpolated_input (ssa_0, ssa_1) (0, 0) /* base=0 */ /* component=0 */	/* gl_FragCoord */
>	vec1 32 ssa_3 = f2i32 ssa_2.x
>	vec1 32 ssa_4 = f2i32 ssa_2.y
>	vec1 32 ssa_5 = i2f32 ssa_3
>	vec1 32 ssa_6 = i2f32 ssa_4
>	vec4 32 ssa_7 = intrinsic load_input (ssa_1) (34, 0) /* base=34 */ /* component=0 */	/* coord_transform */
>	vec1 32 ssa_8 = ffma ssa_5, ssa_7.x, ssa_7.y
>	vec1 32 ssa_9 = ffma ssa_6, ssa_7.z, ssa_7.w
>	vec1 32 ssa_10 = f2i32 ssa_8
>	vec1 32 ssa_11 = f2i32 ssa_9
>	vec1 32 ssa_12 = intrinsic load_input (ssa_1) (36, 2) /* base=36 */ /* component=2 */	/* src_z */
>	vec3 32 ssa_13 = vec3 ssa_10, ssa_11, ssa_12
>	vec4 32 ssa_14 = txf ssa_13 (coord), ssa_1 (lod), 0 (texture), 0 (sampler), 
>	intrinsic store_output (ssa_14, ssa_1) (4, 15, 0) /* base=4 */ /* wrmask=xyzw */ /* component=0 */	/* gl_FragColor */
>	/* succs: block_1 */
>	block block_1:
>}
>
>NIR (final form) for fragment shader:
>shader: MESA_SHADER_FRAGMENT
>name: BLORP-blit
>inputs: 0
>outputs: 0
>uniforms: 0
>shared: 0
>decl_var shader_in INTERP_MODE_FLAT vec4 coord_transform (VARYING_SLOT_VAR3, 34, 0)
>decl_var shader_in INTERP_MODE_FLAT uint src_z (VARYING_SLOT_VAR5.z, 36, 0)
>decl_var shader_in INTERP_MODE_SMOOTH vec4 gl_FragCoord (VARYING_SLOT_POS, 0, 0)
>decl_var shader_out INTERP_MODE_NONE vec4 gl_FragColor (FRAG_RESULT_COLOR, 4, 0)
>decl_function main (0 params)
>
>impl main {
>	block block_0:
>	/* preds: */
>	vec2 32 ssa_0 = intrinsic load_barycentric_pixel () (1) /* interp_mode=1 */
>	vec1 32 ssa_1 = load_const (0x00000000 /* 0.000000 */)
>	vec4 32 ssa_2 = intrinsic load_interpolated_input (ssa_0, ssa_1) (0, 0) /* base=0 */ /* component=0 */	/* gl_FragCoord */
>	vec1 32 ssa_3 = f2i32 ssa_2.x
>	vec1 32 ssa_4 = f2i32 ssa_2.y
>	vec1 32 ssa_5 = i2f32 ssa_3
>	vec1 32 ssa_6 = i2f32 ssa_4
>	vec4 32 ssa_7 = intrinsic load_input (ssa_1) (34, 0) /* base=34 */ /* component=0 */	/* coord_transform */
>	vec1 32 ssa_8 = ffma ssa_5, ssa_7.x, ssa_7.y
>	vec1 32 ssa_9 = ffma ssa_6, ssa_7.z, ssa_7.w
>	vec1 32 ssa_10 = f2i32 ssa_8
>	vec1 32 ssa_11 = f2i32 ssa_9
>	vec1 32 ssa_12 = intrinsic load_input (ssa_1) (36, 2) /* base=36 */ /* component=2 */	/* src_z */
>	vec3 32 ssa_13 = vec3 ssa_10, ssa_11, ssa_12
>	vec4 32 ssa_14 = txf ssa_13 (coord), ssa_1 (lod), 0 (texture), 0 (sampler), 
>	intrinsic store_output (ssa_14, ssa_1) (4, 15, 0) /* base=4 */ /* wrmask=xyzw */ /* component=0 */	/* gl_FragColor */
>	/* succs: block_1 */
>	block block_1:
>}
>
>Native code for unnamed fragment shader BLORP-blit
>SIMD8 shader: 14 instructions. 0 loops. 308 cycles. 0:0 spills:fills. Promoted 0 constants. Compacted 224 to 176 bytes (21%)
>   START B0 (308 cycles)
>add(16)         g6<1>UW         g1.4<1,4,0>UW   0x11001010V     { align1 WE_all 1H };
>mov(8)          g15<1>F         g7.3<0,1,0>F                    { align1 1Q compacted };
>mov(8)          g2<1>F          g6<8,4,1>UW                     { align1 1Q };
>mov(8)          g3<1>F          g6.4<8,4,1>UW                   { align1 1Q };
>mov(8)          g7<1>D          g2<8,8,1>F                      { align1 1Q compacted };
>mov(8)          g8<1>D          g3<8,8,1>F                      { align1 1Q compacted };
>mov(8)          g9<1>F          g7<8,8,1>D                      { align1 1Q compacted };
>mov(8)          g10<1>F         g8<8,8,1>D                      { align1 1Q compacted };
>mad(8)          g11<1>F         g4.7<0,1,0>F    g4.3<0,1,0>F    g9<4,4,1>F { align16 1Q };
>mad(8)          g12<1>F         g5.7<0,1,0>F    g5.3<0,1,0>F    g10<4,4,1>F { align16 1Q };
>mov(8)          g13<1>D         g11<8,8,1>F                     { align1 1Q compacted };
>mov(8)          g14<1>D         g12<8,8,1>F                     { align1 1Q compacted };
>send(8)         g124<1>UW       g13<8,8,1>UD    0x0643a001
>                            sampler MsgDesc: ld_lz SIMD8 Surface = 1 Sampler = 0 mlen 3 rlen 4 { align1 1Q };
>sendc(8)        null<1>UW       g124<0,1,0>F    0x88031400
>                            render MsgDesc: RT write SIMD8 LastRT Surface = 0 mlen 4 rlen 0 { align1 1Q EOT };
>   END B0
>
>Native code for unnamed fragment shader BLORP-blit
>SIMD16 shader: 14 instructions. 0 loops. 322 cycles. 0:0 spills:fills. Promoted 0 constants. Compacted 224 to 176 bytes (21%)
>   START B0 (322 cycles)
>add(32)         g10<1>UW        g1.4<1,4,0>UW   0x11001010V     { align1 WE_all };
>mov(16)         g27<1>F         g9.3<0,1,0>F                    { align1 1H compacted };
>mov(16)         g2<1>F          g10<8,4,1>UW                    { align1 1H };
>mov(16)         g4<1>F          g10.4<8,4,1>UW                  { align1 1H };
>mov(16)         g11<1>D         g2<8,8,1>F                      { align1 1H compacted };
>mov(16)         g13<1>D         g4<8,8,1>F                      { align1 1H compacted };
>mov(16)         g15<1>F         g11<8,8,1>D                     { align1 1H compacted };
>mov(16)         g17<1>F         g13<8,8,1>D                     { align1 1H compacted };
>mad(16)         g19<1>F         g6.7<0,1,0>F    g6.3<0,1,0>F    g15<4,4,1>F { align16 1H };
>mad(16)         g21<1>F         g7.7<0,1,0>F    g7.3<0,1,0>F    g17<4,4,1>F { align16 1H };
>mov(16)         g23<1>D         g19<8,8,1>F                     { align1 1H compacted };
>mov(16)         g25<1>D         g21<8,8,1>F                     { align1 1H compacted };
>send(16)        g120<1>UW       g23<8,8,1>UD    0x0c85a001
>                            sampler MsgDesc: ld_lz SIMD16 Surface = 1 Sampler = 0 mlen 6 rlen 8 { align1 1H };
>sendc(16)       null<1>UW       g120<0,1,0>F    0x90031000
>                            render MsgDesc: RT write SIMD16 LastRT Surface = 0 mlen 8 rlen 0 { align1 1H EOT };
>   END B0
>
>NIR (SSA form) for fragment shader:
>shader: MESA_SHADER_FRAGMENT
>name: BLORP-blit
>inputs: 0
>outputs: 0
>uniforms: 0
>shared: 0
>decl_var shader_in INTERP_MODE_FLAT vec4 coord_transform (VARYING_SLOT_VAR3, 34, 0)
>decl_var shader_in INTERP_MODE_FLAT uint src_z (VARYING_SLOT_VAR5.z, 36, 0)
>decl_var shader_in INTERP_MODE_SMOOTH vec4 gl_FragCoord (VARYING_SLOT_POS, 0, 0)
>decl_var shader_out INTERP_MODE_NONE vec4 gl_FragColor (FRAG_RESULT_COLOR, 4, 0)
>decl_function main (0 params)
>
>impl main {
>	block block_0:
>	/* preds: */
>	vec2 32 ssa_0 = intrinsic load_barycentric_pixel () (1) /* interp_mode=1 */
>	vec1 32 ssa_1 = load_const (0x00000000 /* 0.000000 */)
>	vec4 32 ssa_2 = intrinsic load_interpolated_input (ssa_0, ssa_1) (0, 0) /* base=0 */ /* component=0 */	/* gl_FragCoord */
>	vec1 32 ssa_3 = f2i32 ssa_2.x
>	vec1 32 ssa_4 = f2i32 ssa_2.y
>	vec1 32 ssa_5 = i2f32 ssa_3
>	vec1 32 ssa_6 = i2f32 ssa_4
>	vec4 32 ssa_7 = intrinsic load_input (ssa_1) (34, 0) /* base=34 */ /* component=0 */	/* coord_transform */
>	vec1 32 ssa_8 = ffma ssa_5, ssa_7.x, ssa_7.y
>	vec1 32 ssa_9 = ffma ssa_6, ssa_7.z, ssa_7.w
>	vec1 32 ssa_10 = f2i32 ssa_8
>	vec1 32 ssa_11 = f2i32 ssa_9
>	vec1 32 ssa_12 = intrinsic load_input (ssa_1) (36, 2) /* base=36 */ /* component=2 */	/* src_z */
>	vec3 32 ssa_13 = vec3 ssa_10, ssa_11, ssa_12
>	vec4 32 ssa_14 = txf ssa_13 (coord), ssa_1 (lod), 0 (texture), 0 (sampler), 
>	intrinsic store_output (ssa_14, ssa_1) (4, 15, 0) /* base=4 */ /* wrmask=xyzw */ /* component=0 */	/* gl_FragColor */
>	/* succs: block_1 */
>	block block_1:
>}
>
>NIR (final form) for fragment shader:
>shader: MESA_SHADER_FRAGMENT
>name: BLORP-blit
>inputs: 0
>outputs: 0
>uniforms: 0
>shared: 0
>decl_var shader_in INTERP_MODE_FLAT vec4 coord_transform (VARYING_SLOT_VAR3, 34, 0)
>decl_var shader_in INTERP_MODE_FLAT uint src_z (VARYING_SLOT_VAR5.z, 36, 0)
>decl_var shader_in INTERP_MODE_SMOOTH vec4 gl_FragCoord (VARYING_SLOT_POS, 0, 0)
>decl_var shader_out INTERP_MODE_NONE vec4 gl_FragColor (FRAG_RESULT_COLOR, 4, 0)
>decl_function main (0 params)
>
>impl main {
>	block block_0:
>	/* preds: */
>	vec2 32 ssa_0 = intrinsic load_barycentric_pixel () (1) /* interp_mode=1 */
>	vec1 32 ssa_1 = load_const (0x00000000 /* 0.000000 */)
>	vec4 32 ssa_2 = intrinsic load_interpolated_input (ssa_0, ssa_1) (0, 0) /* base=0 */ /* component=0 */	/* gl_FragCoord */
>	vec1 32 ssa_3 = f2i32 ssa_2.x
>	vec1 32 ssa_4 = f2i32 ssa_2.y
>	vec1 32 ssa_5 = i2f32 ssa_3
>	vec1 32 ssa_6 = i2f32 ssa_4
>	vec4 32 ssa_7 = intrinsic load_input (ssa_1) (34, 0) /* base=34 */ /* component=0 */	/* coord_transform */
>	vec1 32 ssa_8 = ffma ssa_5, ssa_7.x, ssa_7.y
>	vec1 32 ssa_9 = ffma ssa_6, ssa_7.z, ssa_7.w
>	vec1 32 ssa_10 = f2i32 ssa_8
>	vec1 32 ssa_11 = f2i32 ssa_9
>	vec1 32 ssa_12 = intrinsic load_input (ssa_1) (36, 2) /* base=36 */ /* component=2 */	/* src_z */
>	vec3 32 ssa_13 = vec3 ssa_10, ssa_11, ssa_12
>	vec4 32 ssa_14 = txf ssa_13 (coord), ssa_1 (lod), 0 (texture), 0 (sampler), 
>	intrinsic store_output (ssa_14, ssa_1) (4, 15, 0) /* base=4 */ /* wrmask=xyzw */ /* component=0 */	/* gl_FragColor */
>	/* succs: block_1 */
>	block block_1:
>}
>
>Native code for unnamed fragment shader BLORP-blit
>SIMD8 shader: 14 instructions. 0 loops. 106 cycles. 0:0 spills:fills. Promoted 0 constants. Compacted 224 to 160 bytes (29%)
>   START B0 (106 cycles)
>add(16)         g6<1>UW         g1.4<1,4,0>UW   0x11001010V     { align1 WE_all 1H };
>mov(8)          g124<1>UD       g0<8,8,1>UD                     { align1 WE_all 1Q compacted };
>mov(8)          g127<1>F        g7.3<0,1,0>F                    { align1 1Q compacted };
>mov(8)          g2<1>F          g6<8,4,1>UW                     { align1 1Q };
>mov(8)          g3<1>F          g6.4<8,4,1>UW                   { align1 1Q };
>mov(8)          g7<1>D          g2<8,8,1>F                      { align1 1Q compacted };
>mov(8)          g8<1>D          g3<8,8,1>F                      { align1 1Q compacted };
>mov(8)          g9<1>F          g7<8,8,1>D                      { align1 1Q compacted };
>mov(8)          g10<1>F         g8<8,8,1>D                      { align1 1Q compacted };
>mad(8)          g11<1>F         g4.7<0,1,0>F    g4.3<0,1,0>F    g9<4,4,1>F { align16 1Q };
>mad(8)          g12<1>F         g5.7<0,1,0>F    g5.3<0,1,0>F    g10<4,4,1>F { align16 1Q };
>mov(8)          g125<1>D        g11<8,8,1>F                     { align1 1Q compacted };
>mov(8)          g126<1>D        g12<8,8,1>F                     { align1 1Q compacted };
>sendc(8)        null<1>UW       g124<8,8,1>UD   0x880ba001
>                            sampler MsgDesc: ld_lz SIMD8 Surface = 1 Sampler = 0 mlen 4 rlen 0 { align1 1Q EOT };
>   END B0
>
>Native code for unnamed fragment shader BLORP-blit
>SIMD16 shader: 14 instructions. 0 loops. 118 cycles. 0:0 spills:fills. Promoted 0 constants. Compacted 224 to 160 bytes (29%)
>   START B0 (118 cycles)
>add(32)         g10<1>UW        g1.4<1,4,0>UW   0x11001010V     { align1 WE_all };
>mov(8)          g121<1>UD       g0<8,8,1>UD                     { align1 WE_all 1Q compacted };
>mov(16)         g126<1>F        g9.3<0,1,0>F                    { align1 1H compacted };
>mov(16)         g2<1>F          g10<8,4,1>UW                    { align1 1H };
>mov(16)         g4<1>F          g10.4<8,4,1>UW                  { align1 1H };
>mov(16)         g11<1>D         g2<8,8,1>F                      { align1 1H compacted };
>mov(16)         g13<1>D         g4<8,8,1>F                      { align1 1H compacted };
>mov(16)         g15<1>F         g11<8,8,1>D                     { align1 1H compacted };
>mov(16)         g17<1>F         g13<8,8,1>D                     { align1 1H compacted };
>mad(16)         g19<1>F         g6.7<0,1,0>F    g6.3<0,1,0>F    g15<4,4,1>F { align16 1H };
>mad(16)         g21<1>F         g7.7<0,1,0>F    g7.3<0,1,0>F    g17<4,4,1>F { align16 1H };
>mov(16)         g122<1>D        g19<8,8,1>F                     { align1 1H compacted };
>mov(16)         g124<1>D        g21<8,8,1>F                     { align1 1H compacted };
>sendc(16)       null<1>UW       g121<8,8,1>UD   0x8e0da001
>                            sampler MsgDesc: ld_lz SIMD16 Surface = 1 Sampler = 0 mlen 7 rlen 0 { align1 1H EOT };
>   END B0
>

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Attachments on bug 110412: 143948 | 143949

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