Attachment 145226 Details for Bug 111273 – possible fix

[patch] possible fix

0001-drm-amdgpu-Check-for-valid-number-of-registers-to-re.patch (text/plain), 1.17 KB, created by Trek on 2019-08-31 23:21:54 UTC

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Creator: Trek

Created: 2019-08-31 23:21:54 UTC

Size: 1.17 KB

patch

obsolete

>From 751db70debadb00a4cc104aa72a023860b32509f Mon Sep 17 00:00:00 2001
>From: Trek <trek00@inbox.ru>
>Date: Sat, 31 Aug 2019 21:25:36 +0200
>Subject: [PATCH] drm/amdgpu: Check for valid number of registers to read
>
>Do not try to allocate any amount of memory requested by the user.
>Instead limit it to 65536 registers. Actually the longest series of
>consecutive allowed registers are 48 (0x2644-0x2673) for the VI family,
>while the PCI BAR size for memory mapped registers is 256K, at least
>on my KAVERI, thus 65K registers.
>---
> drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 3 +++
> 1 file changed, 3 insertions(+)
>
>diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
>index 0cf7e8606..6bfc0e908 100644
>--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
>+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
>@@ -662,6 +662,9 @@ static int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file
> 		if (sh_num == AMDGPU_INFO_MMR_SH_INDEX_MASK)
> 			sh_num = 0xffffffff;
> 
>+		if (info->read_mmr_reg.count > 65536)
>+			return -EINVAL;
>+
> 		regs = kmalloc_array(info->read_mmr_reg.count, sizeof(*regs), GFP_KERNEL);
> 		if (!regs)
> 			return -ENOMEM;
>-- 
>2.20.1
>

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