Attachment 15527 Details for Bug 14430 – log file taken for working X session after freeze. (Sorry, I forgot to preserve the one for the freeze).

log file taken for working X session after freeze. (Sorry, I forgot to preserve the one for the freeze).

Xorg.0.log (text/plain), 94.74 KB, created by Alan W. Irwin on 2008-03-27 17:56:16 UTC

(hide)

Description:

Filename:

MIME Type:

Creator: Alan W. Irwin

Created: 2008-03-27 17:56:16 UTC

Size: 94.74 KB

patch

obsolete

>
>This is a pre-release version of the X server from The X.Org Foundation.
>It is not supported in any way.
>Bugs may be filed in the bugzilla at http://bugs.freedesktop.org/.
>Select the "xorg" product for bugs you find in this release.
>Before reporting bugs in pre-release versions please check the
>latest version in the X.Org Foundation git repository.
>See http://wiki.x.org/wiki/GitPage for git access instructions.
>
>X.Org X Server 1.4.0.90
>Release Date: 5 September 2007
>X Protocol Version 11, Revision 0
>Build Operating System: Linux Debian (xorg-server 2:1.4.1~git20080131-2)
>Current Operating System: Linux raven 2.6.24-1-amd64 #1 SMP Mon Feb 11 13:47:43 UTC 2008 x86_64
>Build Date: 14 March 2008  03:21:16PM
> 
>	Before reporting problems, check http://wiki.x.org
>	to make sure that you have the latest version.
>Module Loader present
>Markers: (--) probed, (**) from config file, (==) default setting,
>	(++) from command line, (!!) notice, (II) informational,
>	(WW) warning, (EE) error, (NI) not implemented, (??) unknown.
>(==) Log file: "/var/log/Xorg.0.log", Time: Thu Mar 27 17:19:02 2008
>(==) Using config file: "/etc/X11/xorg.conf"
>(==) ServerLayout "Default Layout"
>(**) |-->Screen "Default Screen" (0)
>(**) |   |-->Monitor "Sony Multiscan G200"
>(**) |   |-->Device "g33/X3000"
>(**) |-->Input Device "Generic Keyboard"
>(**) |-->Input Device "Configured Mouse"
>(==) Automatically adding devices
>(==) Automatically enabling devices
>(WW) The directory "/usr/share/fonts/X11/cyrillic" does not exist.
>	Entry deleted from font path.
>(WW) The directory "/var/lib/defoma/x-ttcidfont-conf.d/dirs/TrueType" does not exist.
>	Entry deleted from font path.
>(==) FontPath set to:
>	/usr/share/fonts/X11/misc,
>	/usr/share/fonts/X11/100dpi/:unscaled,
>	/usr/share/fonts/X11/75dpi/:unscaled,
>	/usr/share/fonts/X11/Type1,
>	/usr/share/fonts/X11/100dpi,
>	/usr/share/fonts/X11/75dpi
>(==) RgbPath set to "/etc/X11/rgb"
>(==) ModulePath set to "/usr/lib/xorg/modules"
>(II) Open ACPI successful (/var/run/acpid.socket)
>(II) Loader magic: 0x7b2660
>(II) Module ABI versions:
>	X.Org ANSI C Emulation: 0.3
>	X.Org Video Driver: 2.0
>	X.Org XInput driver : 2.0
>	X.Org Server Extension : 0.3
>	X.Org Font Renderer : 0.5
>(II) Loader running on linux
>(II) LoadModule: "pcidata"
>(II) Loading /usr/lib/xorg/modules//libpcidata.so
>(II) Module pcidata: vendor="X.Org Foundation"
>	compiled for 1.4.0.90, module version = 1.0.0
>	ABI class: X.Org Video Driver, version 2.0
>(--) using VT number 7
>
>(II) PCI: PCI scan (all values are in hex)
>(II) PCI: 00:00:0: chip 8086,29c0 card 1043,8276 rev 02 class 06,00,00 hdr 00
>(II) PCI: 00:02:0: chip 8086,29c2 card 1043,8276 rev 02 class 03,00,00 hdr 80
>(II) PCI: 00:02:1: chip 8086,29c3 card 1043,8276 rev 02 class 03,80,00 hdr 80
>(II) PCI: 00:1a:0: chip 8086,2937 card 1043,8277 rev 02 class 0c,03,00 hdr 80
>(II) PCI: 00:1a:1: chip 8086,2938 card 1043,8277 rev 02 class 0c,03,00 hdr 00
>(II) PCI: 00:1a:2: chip 8086,2939 card 1043,8277 rev 02 class 0c,03,00 hdr 00
>(II) PCI: 00:1a:7: chip 8086,293c card 1043,8277 rev 02 class 0c,03,20 hdr 00
>(II) PCI: 00:1b:0: chip 8086,293e card 1043,829f rev 02 class 04,03,00 hdr 00
>(II) PCI: 00:1c:0: chip 8086,2940 card 0000,0000 rev 02 class 06,04,00 hdr 81
>(II) PCI: 00:1c:4: chip 8086,2948 card 0000,0000 rev 02 class 06,04,00 hdr 81
>(II) PCI: 00:1c:5: chip 8086,294a card 0000,0000 rev 02 class 06,04,00 hdr 81
>(II) PCI: 00:1d:0: chip 8086,2934 card 1043,8277 rev 02 class 0c,03,00 hdr 80
>(II) PCI: 00:1d:1: chip 8086,2935 card 1043,8277 rev 02 class 0c,03,00 hdr 00
>(II) PCI: 00:1d:2: chip 8086,2936 card 1043,8277 rev 02 class 0c,03,00 hdr 00
>(II) PCI: 00:1d:7: chip 8086,293a card 1043,8277 rev 02 class 0c,03,20 hdr 00
>(II) PCI: 00:1e:0: chip 8086,244e card 0000,0000 rev 92 class 06,04,01 hdr 01
>(II) PCI: 00:1f:0: chip 8086,2918 card 1043,8277 rev 02 class 06,01,00 hdr 80
>(II) PCI: 00:1f:2: chip 8086,2921 card 1043,8277 rev 02 class 01,01,8f hdr 00
>(II) PCI: 00:1f:3: chip 8086,2930 card 1043,8277 rev 02 class 0c,05,00 hdr 00
>(II) PCI: 00:1f:5: chip 8086,2926 card 1043,8277 rev 02 class 01,01,85 hdr 00
>(II) PCI: 01:00:0: chip 1969,1048 card 1043,8226 rev b0 class 02,00,00 hdr 00
>(II) PCI: 02:00:0: chip 197b,2363 card 1043,824f rev 03 class 01,06,01 hdr 80
>(II) PCI: 02:00:1: chip 197b,2363 card 1043,824f rev 03 class 01,01,85 hdr 00
>(II) PCI: 04:00:0: chip 109e,036e card 0070,13eb rev 11 class 04,00,00 hdr 80
>(II) PCI: 04:00:1: chip 109e,0878 card 0070,13eb rev 11 class 04,80,00 hdr 80
>(II) PCI: 04:02:0: chip 1106,3043 card 1186,1400 rev 06 class 02,00,00 hdr 00
>(II) PCI: 04:03:0: chip 1106,3044 card 1043,81fe rev c0 class 0c,00,10 hdr 00
>(II) PCI: End of PCI scan
>(II) Intel Bridge workaround enabled
>(II) Host-to-PCI bridge:
>(II) Bus 0: bridge is at (0:0:0), (0,0,4), BCTRL: 0x0008 (VGA_EN is set)
>(II) Bus 0 I/O range:
>	[0] -1	0	0x00000000 - 0x0000ffff (0x10000) IX[B]
>(II) Bus 0 non-prefetchable memory range:
>	[0] -1	0	0x00000000 - 0xffffffff (0x100000000) MX[B]
>(II) Bus 0 prefetchable memory range:
>	[0] -1	0	0x00000000 - 0xffffffff (0x100000000) MX[B]
>(II) PCI-to-PCI bridge:
>(II) Bus 3: bridge is at (0:28:0), (0,3,3), BCTRL: 0x0002 (VGA_EN is cleared)
>(II) Bus 3 prefetchable memory range:
>	[0] -1	0	0xfde00000 - 0xfdefffff (0x100000) MX[B]
>(II) PCI-to-PCI bridge:
>(II) Bus 2: bridge is at (0:28:4), (0,2,2), BCTRL: 0x0002 (VGA_EN is cleared)
>(II) Bus 2 I/O range:
>	[0] -1	0	0x0000d000 - 0x0000dfff (0x1000) IX[B]
>(II) Bus 2 non-prefetchable memory range:
>	[0] -1	0	0xfea00000 - 0xfeafffff (0x100000) MX[B]
>(II) PCI-to-PCI bridge:
>(II) Bus 1: bridge is at (0:28:5), (0,1,1), BCTRL: 0x0002 (VGA_EN is cleared)
>(II) Bus 1 non-prefetchable memory range:
>	[0] -1	0	0xfe900000 - 0xfe9fffff (0x100000) MX[B]
>(II) Subtractive PCI-to-PCI bridge:
>(II) Bus 4: bridge is at (0:30:0), (0,4,4), BCTRL: 0x0002 (VGA_EN is cleared)
>(II) Bus 4 I/O range:
>	[0] -1	0	0x0000e000 - 0x0000efff (0x1000) IX[B]
>(II) Bus 4 non-prefetchable memory range:
>	[0] -1	0	0xfeb00000 - 0xfebfffff (0x100000) MX[B]
>(II) Bus 4 prefetchable memory range:
>	[0] -1	0	0xfdf00000 - 0xfdffffff (0x100000) MX[B]
>(II) PCI-to-ISA bridge:
>(II) Bus -1: bridge is at (0:31:0), (0,-1,-1), BCTRL: 0x0008 (VGA_EN is set)
>(--) PCI:*(0:2:0) Intel Corporation 82G33/G31 Express Integrated Graphics Controller rev 2, Mem @ 0xfe800000/19, 0xd0000000/28, 0xfe700000/20, I/O @ 0xcc00/3
>(--) PCI: (0:2:1) Intel Corporation 82G33/G31 Express Integrated Graphics Controller rev 2, Mem @ 0xfe880000/19
>(--) PCI: (4:0:0) Brooktree Corporation Bt878 Video Capture rev 17, Mem @ 0xfdffe000/12
>(II) Addressable bus resource ranges are
>	[0] -1	0	0x00000000 - 0xffffffff (0x100000000) MX[B]
>	[1] -1	0	0x00000000 - 0x0000ffff (0x10000) IX[B]
>(II) OS-reported resource ranges:
>	[0] -1	0	0x00100000 - 0x3fffffff (0x3ff00000) MX[B]E(B)
>	[1] -1	0	0x000f0000 - 0x000fffff (0x10000) MX[B]
>	[2] -1	0	0x000c0000 - 0x000effff (0x30000) MX[B]
>	[3] -1	0	0x00000000 - 0x0009ffff (0xa0000) MX[B]
>	[4] -1	0	0x0000ffff - 0x0000ffff (0x1) IX[B]
>	[5] -1	0	0x00000000 - 0x000000ff (0x100) IX[B]
>(II) Active PCI resource ranges:
>	[0] -1	0	0xfebff000 - 0xfebff7ff (0x800) MX[B]
>	[1] -1	0	0xfebffc00 - 0xfebffc7f (0x80) MX[B]
>	[2] -1	0	0xfdfff000 - 0xfdffffff (0x1000) MX[B]
>	[3] -1	0	0xfeafe000 - 0xfeafffff (0x2000) MX[B]
>	[4] -1	0	0xfe9c0000 - 0xfe9fffff (0x40000) MX[B]
>	[5] -1	0	0xfe6fb400 - 0xfe6fb4ff (0x100) MX[B]
>	[6] -1	0	0xfe6fb800 - 0xfe6fbbff (0x400) MX[B]
>	[7] -1	0	0xfe6f4000 - 0xfe6f7fff (0x4000) MX[B]
>	[8] -1	0	0xfe6fbc00 - 0xfe6fbfff (0x400) MX[B]
>	[9] -1	0	0xfdffe000 - 0xfdffefff (0x1000) MX[B](B)
>	[10] -1	0	0xfe880000 - 0xfe8fffff (0x80000) MX[B](B)
>	[11] -1	0	0xfe700000 - 0xfe7fffff (0x100000) MX[B](B)
>	[12] -1	0	0xd0000000 - 0xdfffffff (0x10000000) MX[B](B)
>	[13] -1	0	0xfe800000 - 0xfe87ffff (0x80000) MX[B](B)
>	[14] -1	0	0x0000e880 - 0x0000e8ff (0x80) IX[B]
>	[15] -1	0	0x0000ec00 - 0x0000ec7f (0x80) IX[B]
>	[16] -1	0	0x0000d400 - 0x0000d40f (0x10) IX[B]
>	[17] -1	0	0x0000d480 - 0x0000d483 (0x4) IX[B]
>	[18] -1	0	0x0000d800 - 0x0000d807 (0x8) IX[B]
>	[19] -1	0	0x0000d880 - 0x0000d883 (0x4) IX[B]
>	[20] -1	0	0x0000dc00 - 0x0000dc07 (0x8) IX[B]
>	[21] -1	0	0x0000b080 - 0x0000b08f (0x10) IX[B]
>	[22] -1	0	0x0000b400 - 0x0000b40f (0x10) IX[B]
>	[23] -1	0	0x0000b480 - 0x0000b483 (0x4) IX[B]
>	[24] -1	0	0x0000b800 - 0x0000b807 (0x8) IX[B]
>	[25] -1	0	0x0000b880 - 0x0000b883 (0x4) IX[B]
>	[26] -1	0	0x0000bc00 - 0x0000bc07 (0x8) IX[B]
>	[27] -1	0	0x00000400 - 0x0000041f (0x20) IX[B]
>	[28] -1	0	0x0000a080 - 0x0000a08f (0x10) IX[B]
>	[29] -1	0	0x0000a400 - 0x0000a40f (0x10) IX[B]
>	[30] -1	0	0x0000a480 - 0x0000a483 (0x4) IX[B]
>	[31] -1	0	0x0000a800 - 0x0000a807 (0x8) IX[B]
>	[32] -1	0	0x0000a880 - 0x0000a883 (0x4) IX[B]
>	[33] -1	0	0x0000ac00 - 0x0000ac07 (0x8) IX[B]
>	[34] -1	0	0x0000c400 - 0x0000c41f (0x20) IX[B]
>	[35] -1	0	0x0000c080 - 0x0000c09f (0x20) IX[B]
>	[36] -1	0	0x0000c000 - 0x0000c01f (0x20) IX[B]
>	[37] -1	0	0x0000c880 - 0x0000c89f (0x20) IX[B]
>	[38] -1	0	0x0000c800 - 0x0000c81f (0x20) IX[B]
>	[39] -1	0	0x0000c480 - 0x0000c49f (0x20) IX[B]
>	[40] -1	0	0x0000cc00 - 0x0000cc07 (0x8) IX[B](B)
>(II) Active PCI resource ranges after removing overlaps:
>	[0] -1	0	0xfebff000 - 0xfebff7ff (0x800) MX[B]
>	[1] -1	0	0xfebffc00 - 0xfebffc7f (0x80) MX[B]
>	[2] -1	0	0xfdfff000 - 0xfdffffff (0x1000) MX[B]
>	[3] -1	0	0xfeafe000 - 0xfeafffff (0x2000) MX[B]
>	[4] -1	0	0xfe9c0000 - 0xfe9fffff (0x40000) MX[B]
>	[5] -1	0	0xfe6fb400 - 0xfe6fb4ff (0x100) MX[B]
>	[6] -1	0	0xfe6fb800 - 0xfe6fbbff (0x400) MX[B]
>	[7] -1	0	0xfe6f4000 - 0xfe6f7fff (0x4000) MX[B]
>	[8] -1	0	0xfe6fbc00 - 0xfe6fbfff (0x400) MX[B]
>	[9] -1	0	0xfdffe000 - 0xfdffefff (0x1000) MX[B](B)
>	[10] -1	0	0xfe880000 - 0xfe8fffff (0x80000) MX[B](B)
>	[11] -1	0	0xfe700000 - 0xfe7fffff (0x100000) MX[B](B)
>	[12] -1	0	0xd0000000 - 0xdfffffff (0x10000000) MX[B](B)
>	[13] -1	0	0xfe800000 - 0xfe87ffff (0x80000) MX[B](B)
>	[14] -1	0	0x0000e880 - 0x0000e8ff (0x80) IX[B]
>	[15] -1	0	0x0000ec00 - 0x0000ec7f (0x80) IX[B]
>	[16] -1	0	0x0000d400 - 0x0000d40f (0x10) IX[B]
>	[17] -1	0	0x0000d480 - 0x0000d483 (0x4) IX[B]
>	[18] -1	0	0x0000d800 - 0x0000d807 (0x8) IX[B]
>	[19] -1	0	0x0000d880 - 0x0000d883 (0x4) IX[B]
>	[20] -1	0	0x0000dc00 - 0x0000dc07 (0x8) IX[B]
>	[21] -1	0	0x0000b080 - 0x0000b08f (0x10) IX[B]
>	[22] -1	0	0x0000b400 - 0x0000b40f (0x10) IX[B]
>	[23] -1	0	0x0000b480 - 0x0000b483 (0x4) IX[B]
>	[24] -1	0	0x0000b800 - 0x0000b807 (0x8) IX[B]
>	[25] -1	0	0x0000b880 - 0x0000b883 (0x4) IX[B]
>	[26] -1	0	0x0000bc00 - 0x0000bc07 (0x8) IX[B]
>	[27] -1	0	0x00000400 - 0x0000041f (0x20) IX[B]
>	[28] -1	0	0x0000a080 - 0x0000a08f (0x10) IX[B]
>	[29] -1	0	0x0000a400 - 0x0000a40f (0x10) IX[B]
>	[30] -1	0	0x0000a480 - 0x0000a483 (0x4) IX[B]
>	[31] -1	0	0x0000a800 - 0x0000a807 (0x8) IX[B]
>	[32] -1	0	0x0000a880 - 0x0000a883 (0x4) IX[B]
>	[33] -1	0	0x0000ac00 - 0x0000ac07 (0x8) IX[B]
>	[34] -1	0	0x0000c400 - 0x0000c41f (0x20) IX[B]
>	[35] -1	0	0x0000c080 - 0x0000c09f (0x20) IX[B]
>	[36] -1	0	0x0000c000 - 0x0000c01f (0x20) IX[B]
>	[37] -1	0	0x0000c880 - 0x0000c89f (0x20) IX[B]
>	[38] -1	0	0x0000c800 - 0x0000c81f (0x20) IX[B]
>	[39] -1	0	0x0000c480 - 0x0000c49f (0x20) IX[B]
>	[40] -1	0	0x0000cc00 - 0x0000cc07 (0x8) IX[B](B)
>(II) OS-reported resource ranges after removing overlaps with PCI:
>	[0] -1	0	0x00100000 - 0x3fffffff (0x3ff00000) MX[B]E(B)
>	[1] -1	0	0x000f0000 - 0x000fffff (0x10000) MX[B]
>	[2] -1	0	0x000c0000 - 0x000effff (0x30000) MX[B]
>	[3] -1	0	0x00000000 - 0x0009ffff (0xa0000) MX[B]
>	[4] -1	0	0x0000ffff - 0x0000ffff (0x1) IX[B]
>	[5] -1	0	0x00000000 - 0x000000ff (0x100) IX[B]
>(II) All system resource ranges:
>	[0] -1	0	0x00100000 - 0x3fffffff (0x3ff00000) MX[B]E(B)
>	[1] -1	0	0x000f0000 - 0x000fffff (0x10000) MX[B]
>	[2] -1	0	0x000c0000 - 0x000effff (0x30000) MX[B]
>	[3] -1	0	0x00000000 - 0x0009ffff (0xa0000) MX[B]
>	[4] -1	0	0xfebff000 - 0xfebff7ff (0x800) MX[B]
>	[5] -1	0	0xfebffc00 - 0xfebffc7f (0x80) MX[B]
>	[6] -1	0	0xfdfff000 - 0xfdffffff (0x1000) MX[B]
>	[7] -1	0	0xfeafe000 - 0xfeafffff (0x2000) MX[B]
>	[8] -1	0	0xfe9c0000 - 0xfe9fffff (0x40000) MX[B]
>	[9] -1	0	0xfe6fb400 - 0xfe6fb4ff (0x100) MX[B]
>	[10] -1	0	0xfe6fb800 - 0xfe6fbbff (0x400) MX[B]
>	[11] -1	0	0xfe6f4000 - 0xfe6f7fff (0x4000) MX[B]
>	[12] -1	0	0xfe6fbc00 - 0xfe6fbfff (0x400) MX[B]
>	[13] -1	0	0xfdffe000 - 0xfdffefff (0x1000) MX[B](B)
>	[14] -1	0	0xfe880000 - 0xfe8fffff (0x80000) MX[B](B)
>	[15] -1	0	0xfe700000 - 0xfe7fffff (0x100000) MX[B](B)
>	[16] -1	0	0xd0000000 - 0xdfffffff (0x10000000) MX[B](B)
>	[17] -1	0	0xfe800000 - 0xfe87ffff (0x80000) MX[B](B)
>	[18] -1	0	0x0000ffff - 0x0000ffff (0x1) IX[B]
>	[19] -1	0	0x00000000 - 0x000000ff (0x100) IX[B]
>	[20] -1	0	0x0000e880 - 0x0000e8ff (0x80) IX[B]
>	[21] -1	0	0x0000ec00 - 0x0000ec7f (0x80) IX[B]
>	[22] -1	0	0x0000d400 - 0x0000d40f (0x10) IX[B]
>	[23] -1	0	0x0000d480 - 0x0000d483 (0x4) IX[B]
>	[24] -1	0	0x0000d800 - 0x0000d807 (0x8) IX[B]
>	[25] -1	0	0x0000d880 - 0x0000d883 (0x4) IX[B]
>	[26] -1	0	0x0000dc00 - 0x0000dc07 (0x8) IX[B]
>	[27] -1	0	0x0000b080 - 0x0000b08f (0x10) IX[B]
>	[28] -1	0	0x0000b400 - 0x0000b40f (0x10) IX[B]
>	[29] -1	0	0x0000b480 - 0x0000b483 (0x4) IX[B]
>	[30] -1	0	0x0000b800 - 0x0000b807 (0x8) IX[B]
>	[31] -1	0	0x0000b880 - 0x0000b883 (0x4) IX[B]
>	[32] -1	0	0x0000bc00 - 0x0000bc07 (0x8) IX[B]
>	[33] -1	0	0x00000400 - 0x0000041f (0x20) IX[B]
>	[34] -1	0	0x0000a080 - 0x0000a08f (0x10) IX[B]
>	[35] -1	0	0x0000a400 - 0x0000a40f (0x10) IX[B]
>	[36] -1	0	0x0000a480 - 0x0000a483 (0x4) IX[B]
>	[37] -1	0	0x0000a800 - 0x0000a807 (0x8) IX[B]
>	[38] -1	0	0x0000a880 - 0x0000a883 (0x4) IX[B]
>	[39] -1	0	0x0000ac00 - 0x0000ac07 (0x8) IX[B]
>	[40] -1	0	0x0000c400 - 0x0000c41f (0x20) IX[B]
>	[41] -1	0	0x0000c080 - 0x0000c09f (0x20) IX[B]
>	[42] -1	0	0x0000c000 - 0x0000c01f (0x20) IX[B]
>	[43] -1	0	0x0000c880 - 0x0000c89f (0x20) IX[B]
>	[44] -1	0	0x0000c800 - 0x0000c81f (0x20) IX[B]
>	[45] -1	0	0x0000c480 - 0x0000c49f (0x20) IX[B]
>	[46] -1	0	0x0000cc00 - 0x0000cc07 (0x8) IX[B](B)
>(II) LoadModule: "extmod"
>(II) Loading /usr/lib/xorg/modules/extensions//libextmod.so
>(II) Module extmod: vendor="X.Org Foundation"
>	compiled for 1.4.0.90, module version = 1.0.0
>	Module class: X.Org Server Extension
>	ABI class: X.Org Server Extension, version 0.3
>(II) Loading extension SHAPE
>(II) Loading extension MIT-SUNDRY-NONSTANDARD
>(II) Loading extension BIG-REQUESTS
>(II) Loading extension SYNC
>(II) Loading extension MIT-SCREEN-SAVER
>(II) Loading extension XC-MISC
>(II) Loading extension XFree86-VidModeExtension
>(II) Loading extension XFree86-Misc
>(II) Loading extension XFree86-DGA
>(II) Loading extension DPMS
>(II) Loading extension TOG-CUP
>(II) Loading extension Extended-Visual-Information
>(II) Loading extension XVideo
>(II) Loading extension XVideo-MotionCompensation
>(II) Loading extension X-Resource
>(II) LoadModule: "dbe"
>(II) Loading /usr/lib/xorg/modules/extensions//libdbe.so
>(II) Module dbe: vendor="X.Org Foundation"
>	compiled for 1.4.0.90, module version = 1.0.0
>	Module class: X.Org Server Extension
>	ABI class: X.Org Server Extension, version 0.3
>(II) Loading extension DOUBLE-BUFFER
>(II) LoadModule: "glx"
>(II) Loading /usr/lib/xorg/modules/extensions//libglx.so
>(II) Module glx: vendor="X.Org Foundation"
>	compiled for 1.4.0.90, module version = 1.0.0
>	ABI class: X.Org Server Extension, version 0.3
>(==) AIGLX enabled
>(II) Loading extension GLX
>(II) LoadModule: "freetype"
>(II) Loading /usr/lib/xorg/modules//fonts/libfreetype.so
>(II) Module freetype: vendor="X.Org Foundation & the After X-TT Project"
>	compiled for 1.4.0.90, module version = 2.1.0
>	Module class: X.Org Font Renderer
>	ABI class: X.Org Font Renderer, version 0.5
>(II) Loading font FreeType
>(II) LoadModule: "record"
>(II) Loading /usr/lib/xorg/modules/extensions//librecord.so
>(II) Module record: vendor="X.Org Foundation"
>	compiled for 1.4.0.90, module version = 1.13.0
>	Module class: X.Org Server Extension
>	ABI class: X.Org Server Extension, version 0.3
>(II) Loading extension RECORD
>(II) LoadModule: "dri"
>(II) Loading /usr/lib/xorg/modules/extensions//libdri.so
>(II) Module dri: vendor="X.Org Foundation"
>	compiled for 1.4.0.90, module version = 1.0.0
>	ABI class: X.Org Server Extension, version 0.3
>(II) Loading extension XFree86-DRI
>(II) LoadModule: "intel"
>(II) Loading /usr/lib/xorg/modules/drivers//intel_drv.so
>(II) Module intel: vendor="X.Org Foundation"
>	compiled for 1.4.0.90, module version = 2.2.99
>	Module class: X.Org Video Driver
>	ABI class: X.Org Video Driver, version 2.0
>(II) LoadModule: "kbd"
>(II) Loading /usr/lib/xorg/modules/input//kbd_drv.so
>(II) Module kbd: vendor="X.Org Foundation"
>	compiled for 1.4.0, module version = 1.2.2
>	Module class: X.Org XInput Driver
>	ABI class: X.Org XInput driver, version 2.0
>(II) LoadModule: "mouse"
>(II) Loading /usr/lib/xorg/modules/input//mouse_drv.so
>(II) Module mouse: vendor="X.Org Foundation"
>	compiled for 1.4.0, module version = 1.2.3
>	Module class: X.Org XInput Driver
>	ABI class: X.Org XInput driver, version 2.0
>(II) intel: Driver for Intel Integrated Graphics Chipsets: i810,
>	i810-dc100, i810e, i815, i830M, 845G, 852GM/855GM, 865G, 915G,
>	E7221 (i915), 915GM, 945G, 945GM, 945GME, 965G, G35, 965Q, 946GZ,
>	965GM, 965GME/GLE, G33, Q35, Q33, Intel Integrated Graphics Device
>(II) Primary Device is: PCI 00:02:0
>(WW) intel: No matching Device section for instance (BusID PCI:0:2:1) found
>(--) Chipset G33 found
>(II) resource ranges after xf86ClaimFixedResources() call:
>	[0] -1	0	0x00100000 - 0x3fffffff (0x3ff00000) MX[B]E(B)
>	[1] -1	0	0x000f0000 - 0x000fffff (0x10000) MX[B]
>	[2] -1	0	0x000c0000 - 0x000effff (0x30000) MX[B]
>	[3] -1	0	0x00000000 - 0x0009ffff (0xa0000) MX[B]
>	[4] -1	0	0xfebff000 - 0xfebff7ff (0x800) MX[B]
>	[5] -1	0	0xfebffc00 - 0xfebffc7f (0x80) MX[B]
>	[6] -1	0	0xfdfff000 - 0xfdffffff (0x1000) MX[B]
>	[7] -1	0	0xfeafe000 - 0xfeafffff (0x2000) MX[B]
>	[8] -1	0	0xfe9c0000 - 0xfe9fffff (0x40000) MX[B]
>	[9] -1	0	0xfe6fb400 - 0xfe6fb4ff (0x100) MX[B]
>	[10] -1	0	0xfe6fb800 - 0xfe6fbbff (0x400) MX[B]
>	[11] -1	0	0xfe6f4000 - 0xfe6f7fff (0x4000) MX[B]
>	[12] -1	0	0xfe6fbc00 - 0xfe6fbfff (0x400) MX[B]
>	[13] -1	0	0xfdffe000 - 0xfdffefff (0x1000) MX[B](B)
>	[14] -1	0	0xfe880000 - 0xfe8fffff (0x80000) MX[B](B)
>	[15] -1	0	0xfe700000 - 0xfe7fffff (0x100000) MX[B](B)
>	[16] -1	0	0xd0000000 - 0xdfffffff (0x10000000) MX[B](B)
>	[17] -1	0	0xfe800000 - 0xfe87ffff (0x80000) MX[B](B)
>	[18] -1	0	0x0000ffff - 0x0000ffff (0x1) IX[B]
>	[19] -1	0	0x00000000 - 0x000000ff (0x100) IX[B]
>	[20] -1	0	0x0000e880 - 0x0000e8ff (0x80) IX[B]
>	[21] -1	0	0x0000ec00 - 0x0000ec7f (0x80) IX[B]
>	[22] -1	0	0x0000d400 - 0x0000d40f (0x10) IX[B]
>	[23] -1	0	0x0000d480 - 0x0000d483 (0x4) IX[B]
>	[24] -1	0	0x0000d800 - 0x0000d807 (0x8) IX[B]
>	[25] -1	0	0x0000d880 - 0x0000d883 (0x4) IX[B]
>	[26] -1	0	0x0000dc00 - 0x0000dc07 (0x8) IX[B]
>	[27] -1	0	0x0000b080 - 0x0000b08f (0x10) IX[B]
>	[28] -1	0	0x0000b400 - 0x0000b40f (0x10) IX[B]
>	[29] -1	0	0x0000b480 - 0x0000b483 (0x4) IX[B]
>	[30] -1	0	0x0000b800 - 0x0000b807 (0x8) IX[B]
>	[31] -1	0	0x0000b880 - 0x0000b883 (0x4) IX[B]
>	[32] -1	0	0x0000bc00 - 0x0000bc07 (0x8) IX[B]
>	[33] -1	0	0x00000400 - 0x0000041f (0x20) IX[B]
>	[34] -1	0	0x0000a080 - 0x0000a08f (0x10) IX[B]
>	[35] -1	0	0x0000a400 - 0x0000a40f (0x10) IX[B]
>	[36] -1	0	0x0000a480 - 0x0000a483 (0x4) IX[B]
>	[37] -1	0	0x0000a800 - 0x0000a807 (0x8) IX[B]
>	[38] -1	0	0x0000a880 - 0x0000a883 (0x4) IX[B]
>	[39] -1	0	0x0000ac00 - 0x0000ac07 (0x8) IX[B]
>	[40] -1	0	0x0000c400 - 0x0000c41f (0x20) IX[B]
>	[41] -1	0	0x0000c080 - 0x0000c09f (0x20) IX[B]
>	[42] -1	0	0x0000c000 - 0x0000c01f (0x20) IX[B]
>	[43] -1	0	0x0000c880 - 0x0000c89f (0x20) IX[B]
>	[44] -1	0	0x0000c800 - 0x0000c81f (0x20) IX[B]
>	[45] -1	0	0x0000c480 - 0x0000c49f (0x20) IX[B]
>	[46] -1	0	0x0000cc00 - 0x0000cc07 (0x8) IX[B](B)
>(II) resource ranges after probing:
>	[0] -1	0	0x00100000 - 0x3fffffff (0x3ff00000) MX[B]E(B)
>	[1] -1	0	0x000f0000 - 0x000fffff (0x10000) MX[B]
>	[2] -1	0	0x000c0000 - 0x000effff (0x30000) MX[B]
>	[3] -1	0	0x00000000 - 0x0009ffff (0xa0000) MX[B]
>	[4] -1	0	0xfebff000 - 0xfebff7ff (0x800) MX[B]
>	[5] -1	0	0xfebffc00 - 0xfebffc7f (0x80) MX[B]
>	[6] -1	0	0xfdfff000 - 0xfdffffff (0x1000) MX[B]
>	[7] -1	0	0xfeafe000 - 0xfeafffff (0x2000) MX[B]
>	[8] -1	0	0xfe9c0000 - 0xfe9fffff (0x40000) MX[B]
>	[9] -1	0	0xfe6fb400 - 0xfe6fb4ff (0x100) MX[B]
>	[10] -1	0	0xfe6fb800 - 0xfe6fbbff (0x400) MX[B]
>	[11] -1	0	0xfe6f4000 - 0xfe6f7fff (0x4000) MX[B]
>	[12] -1	0	0xfe6fbc00 - 0xfe6fbfff (0x400) MX[B]
>	[13] -1	0	0xfdffe000 - 0xfdffefff (0x1000) MX[B](B)
>	[14] -1	0	0xfe880000 - 0xfe8fffff (0x80000) MX[B](B)
>	[15] -1	0	0xfe700000 - 0xfe7fffff (0x100000) MX[B](B)
>	[16] -1	0	0xd0000000 - 0xdfffffff (0x10000000) MX[B](B)
>	[17] -1	0	0xfe800000 - 0xfe87ffff (0x80000) MX[B](B)
>	[18] 0	0	0x000a0000 - 0x000affff (0x10000) MS[B]
>	[19] 0	0	0x000b0000 - 0x000b7fff (0x8000) MS[B]
>	[20] 0	0	0x000b8000 - 0x000bffff (0x8000) MS[B]
>	[21] -1	0	0x0000ffff - 0x0000ffff (0x1) IX[B]
>	[22] -1	0	0x00000000 - 0x000000ff (0x100) IX[B]
>	[23] -1	0	0x0000e880 - 0x0000e8ff (0x80) IX[B]
>	[24] -1	0	0x0000ec00 - 0x0000ec7f (0x80) IX[B]
>	[25] -1	0	0x0000d400 - 0x0000d40f (0x10) IX[B]
>	[26] -1	0	0x0000d480 - 0x0000d483 (0x4) IX[B]
>	[27] -1	0	0x0000d800 - 0x0000d807 (0x8) IX[B]
>	[28] -1	0	0x0000d880 - 0x0000d883 (0x4) IX[B]
>	[29] -1	0	0x0000dc00 - 0x0000dc07 (0x8) IX[B]
>	[30] -1	0	0x0000b080 - 0x0000b08f (0x10) IX[B]
>	[31] -1	0	0x0000b400 - 0x0000b40f (0x10) IX[B]
>	[32] -1	0	0x0000b480 - 0x0000b483 (0x4) IX[B]
>	[33] -1	0	0x0000b800 - 0x0000b807 (0x8) IX[B]
>	[34] -1	0	0x0000b880 - 0x0000b883 (0x4) IX[B]
>	[35] -1	0	0x0000bc00 - 0x0000bc07 (0x8) IX[B]
>	[36] -1	0	0x00000400 - 0x0000041f (0x20) IX[B]
>	[37] -1	0	0x0000a080 - 0x0000a08f (0x10) IX[B]
>	[38] -1	0	0x0000a400 - 0x0000a40f (0x10) IX[B]
>	[39] -1	0	0x0000a480 - 0x0000a483 (0x4) IX[B]
>	[40] -1	0	0x0000a800 - 0x0000a807 (0x8) IX[B]
>	[41] -1	0	0x0000a880 - 0x0000a883 (0x4) IX[B]
>	[42] -1	0	0x0000ac00 - 0x0000ac07 (0x8) IX[B]
>	[43] -1	0	0x0000c400 - 0x0000c41f (0x20) IX[B]
>	[44] -1	0	0x0000c080 - 0x0000c09f (0x20) IX[B]
>	[45] -1	0	0x0000c000 - 0x0000c01f (0x20) IX[B]
>	[46] -1	0	0x0000c880 - 0x0000c89f (0x20) IX[B]
>	[47] -1	0	0x0000c800 - 0x0000c81f (0x20) IX[B]
>	[48] -1	0	0x0000c480 - 0x0000c49f (0x20) IX[B]
>	[49] -1	0	0x0000cc00 - 0x0000cc07 (0x8) IX[B](B)
>	[50] 0	0	0x000003b0 - 0x000003bb (0xc) IS[B]
>	[51] 0	0	0x000003c0 - 0x000003df (0x20) IS[B]
>(II) Setting vga for screen 0.
>(II) Loading sub module "int10"
>(II) LoadModule: "int10"
>(II) Loading /usr/lib/xorg/modules//libint10.so
>(II) Module int10: vendor="X.Org Foundation"
>	compiled for 1.4.0.90, module version = 1.0.0
>	ABI class: X.Org Video Driver, version 2.0
>(II) Loading sub module "vbe"
>(II) LoadModule: "vbe"
>(II) Loading /usr/lib/xorg/modules//libvbe.so
>(II) Module vbe: vendor="X.Org Foundation"
>	compiled for 1.4.0.90, module version = 1.1.0
>	ABI class: X.Org Video Driver, version 2.0
>(II) Loading sub module "vgahw"
>(II) LoadModule: "vgahw"
>(II) Loading /usr/lib/xorg/modules//libvgahw.so
>(II) Module vgahw: vendor="X.Org Foundation"
>	compiled for 1.4.0.90, module version = 0.1.0
>	ABI class: X.Org Video Driver, version 2.0
>(**) intel(0): Depth 16, (--) framebuffer bpp 16
>(==) intel(0): RGB weight 565
>(==) intel(0): Default visual is TrueColor
>(**) intel(0): Option "ModeDebug" "on"
>(II) intel(0): Integrated Graphics Chipset: Intel(R) G33
>(--) intel(0): Chipset: "G33"
>(--) intel(0): Linear framebuffer at 0xD0000000
>(--) intel(0): IO registers at addr 0xFE800000
>(II) intel(0): Hardware state on X startup:
>(II) intel(0): DumpRegsBegin
>(II) intel(0):    VCLK_DIVISOR_VGA0: 0x00031108 (n = 3, m1 = 17, m2 = 8)
>(II) intel(0):    VCLK_DIVISOR_VGA1: 0x00031406 (n = 3, m1 = 20, m2 = 6)
>(II) intel(0):        VCLK_POST_DIV: 0x00020002 (vga0 p1 = 4, p2 = 2, vga1 p1 = 2, p2 = 2)
>(II) intel(0):            DPLL_TEST: 0x00010001 ()
>(II) intel(0):         CACHE_MODE_0: 0x00006820
>(II) intel(0):              D_STATE: 0x00000000
>(II) intel(0):        DSPCLK_GATE_D: 0x00000000 (clock gates disabled:)
>(II) intel(0):       RENCLK_GATE_D1: 0x00000000
>(II) intel(0):       RENCLK_GATE_D2: 0x00000000
>(II) intel(0):                SDVOB: 0x80300084 (enabled, pipe A, stall disabled, detected)
>(II) intel(0):                SDVOC: 0x00300000 (disabled, pipe A, stall disabled, not detected)
>(II) intel(0):              SDVOUDI: 0x00000000
>(II) intel(0):               DSPARB: 0x00001d9c
>(II) intel(0):               DSPFW1: 0x00000000
>(II) intel(0):               DSPFW2: 0x00000000
>(II) intel(0):               DSPFW3: 0x00000000
>(II) intel(0):                 ADPA: 0x00008c18 (disabled, pipe A, +hsync, +vsync)
>(II) intel(0):                 LVDS: 0x00000000 (disabled, pipe A, 18 bit, 1 channel)
>(II) intel(0):                 DVOA: 0x00000000 (disabled, pipe A, no stall, -hsync, -vsync)
>(II) intel(0):                 DVOB: 0x80300084 (enabled, pipe A, no stall, -hsync, -vsync)
>(II) intel(0):                 DVOC: 0x00300000 (disabled, pipe A, no stall, -hsync, -vsync)
>(II) intel(0):          DVOA_SRCDIM: 0x00000000
>(II) intel(0):          DVOB_SRCDIM: 0x00000000
>(II) intel(0):          DVOC_SRCDIM: 0x00000000
>(II) intel(0):           PP_CONTROL: 0x00000000 (power target: off)
>(II) intel(0):            PP_STATUS: 0x00000000 (off, not ready, sequencing idle)
>(II) intel(0):         PFIT_CONTROL: 0x00000000
>(II) intel(0):      PFIT_PGM_RATIOS: 0x00000000
>(II) intel(0):      PORT_HOTPLUG_EN: 0x00000020
>(II) intel(0):    PORT_HOTPLUG_STAT: 0x00000000
>(II) intel(0):             DSPACNTR: 0x48000000 (disabled, pipe A)
>(II) intel(0):           DSPASTRIDE: 0x00000280 (640 bytes)
>(II) intel(0):              DSPAPOS: 0x00000000 (0, 0)
>(II) intel(0):             DSPASIZE: 0x018f02cf (720, 400)
>(II) intel(0):             DSPABASE: 0x00000000
>(II) intel(0):             DSPASURF: 0x00000000
>(II) intel(0):          DSPATILEOFF: 0x00000000
>(II) intel(0):            PIPEACONF: 0x80000000 (enabled, single-wide)
>(II) intel(0):             PIPEASRC: 0x02cf018f (720, 400)
>(II) intel(0):            PIPEASTAT: 0x00020203 (status: VBLANK_INT_ENABLE VSYNC_INT_STATUS VBLANK_INT_STATUS OREG_UPDATE_STATUS)
>(II) intel(0):         FBC_CFB_BASE: 0xffffffff
>(II) intel(0):          FBC_LL_BASE: 0xffffffff
>(II) intel(0):          FBC_CONTROL: 0xffffffff
>(II) intel(0):          FBC_COMMAND: 0xffffffff
>(II) intel(0):           FBC_STATUS: 0xffffffff
>(II) intel(0):         FBC_CONTROL2: 0xffffffff
>(II) intel(0):        FBC_FENCE_OFF: 0xffffffff
>(II) intel(0):          FBC_MOD_NUM: 0xffffffff
>(II) intel(0):                 FPA0: 0x00031406 (n = 3, m1 = 20, m2 = 6)
>(II) intel(0):                 FPA1: 0x00031108 (n = 3, m1 = 17, m2 = 8)
>(II) intel(0):               DPLL_A: 0xc4020033 (enabled, dvo, VGA, default clock, DAC/serial mode, p1 = 2, p2 = 10, SDVO mult 4)
>(II) intel(0):            DPLL_A_MD: 0x00000000
>(II) intel(0):             HTOTAL_A: 0x038302cf (720 active, 900 total)
>(II) intel(0):             HBLANK_A: 0x038302cf (720 start, 900 end)
>(II) intel(0):              HSYNC_A: 0x036802fc (765 start, 873 end)
>(II) intel(0):             VTOTAL_A: 0x01c0018f (400 active, 449 total)
>(II) intel(0):             VBLANK_A: 0x01c0018f (400 start, 449 end)
>(II) intel(0):              VSYNC_A: 0x019d019b (412 start, 414 end)
>(II) intel(0):            BCLRPAT_A: 0x00000000
>(II) intel(0):         VSYNCSHIFT_A: 0x00000000
>(II) intel(0):             DSPBCNTR: 0x01000000 (disabled, pipe B)
>(II) intel(0):           DSPBSTRIDE: 0x00000000 (0 bytes)
>(II) intel(0):              DSPBPOS: 0x00000000 (0, 0)
>(II) intel(0):             DSPBSIZE: 0x00000000 (1, 1)
>(II) intel(0):             DSPBBASE: 0x00000000
>(II) intel(0):             DSPBSURF: 0x00000000
>(II) intel(0):          DSPBTILEOFF: 0x00000000
>(II) intel(0):            PIPEBCONF: 0x00000000 (disabled, single-wide)
>(II) intel(0):             PIPEBSRC: 0x027f01df (640, 480)
>(II) intel(0):            PIPEBSTAT: 0x00020000 (status: VBLANK_INT_ENABLE)
>(II) intel(0):                 FPB0: 0x00031108 (n = 3, m1 = 17, m2 = 8)
>(II) intel(0):                 FPB1: 0x00031108 (n = 3, m1 = 17, m2 = 8)
>(II) intel(0):               DPLL_B: 0x04800003 (disabled, non-dvo, VGA, default clock, DAC/serial mode, p1 = 8, p2 = 10, SDVO mult 1)
>(II) intel(0):            DPLL_B_MD: 0x00000000
>(II) intel(0):             HTOTAL_B: 0x031f027f (640 active, 800 total)
>(II) intel(0):             HBLANK_B: 0x03170287 (648 start, 792 end)
>(II) intel(0):              HSYNC_B: 0x02ef028f (656 start, 752 end)
>(II) intel(0):             VTOTAL_B: 0x020c01df (480 active, 525 total)
>(II) intel(0):             VBLANK_B: 0x020401e7 (488 start, 517 end)
>(II) intel(0):              VSYNC_B: 0x01eb01e9 (490 start, 492 end)
>(II) intel(0):            BCLRPAT_B: 0x00000000
>(II) intel(0):         VSYNCSHIFT_B: 0x00000000
>(II) intel(0):    VCLK_DIVISOR_VGA0: 0x00031108
>(II) intel(0):    VCLK_DIVISOR_VGA1: 0x00031406
>(II) intel(0):        VCLK_POST_DIV: 0x00020002
>(II) intel(0):             VGACNTRL: 0x0020008e (enabled)
>(II) intel(0):               TV_CTL: 0x00000000
>(II) intel(0):               TV_DAC: 0x00000000
>(II) intel(0):             TV_CSC_Y: 0x00000000
>(II) intel(0):            TV_CSC_Y2: 0x00000000
>(II) intel(0):             TV_CSC_U: 0x00000000
>(II) intel(0):            TV_CSC_U2: 0x00000000
>(II) intel(0):             TV_CSC_V: 0x00000000
>(II) intel(0):            TV_CSC_V2: 0x00000000
>(II) intel(0):         TV_CLR_KNOBS: 0x00000000
>(II) intel(0):         TV_CLR_LEVEL: 0x00000000
>(II) intel(0):           TV_H_CTL_1: 0x00000000
>(II) intel(0):           TV_H_CTL_2: 0x00000000
>(II) intel(0):           TV_H_CTL_3: 0x00000000
>(II) intel(0):           TV_V_CTL_1: 0x00000000
>(II) intel(0):           TV_V_CTL_2: 0x00000000
>(II) intel(0):           TV_V_CTL_3: 0x00000000
>(II) intel(0):           TV_V_CTL_4: 0x00000000
>(II) intel(0):           TV_V_CTL_5: 0x00000000
>(II) intel(0):           TV_V_CTL_6: 0x00000000
>(II) intel(0):           TV_V_CTL_7: 0x00000000
>(II) intel(0):          TV_SC_CTL_1: 0x00000000
>(II) intel(0):          TV_SC_CTL_2: 0x00000000
>(II) intel(0):          TV_SC_CTL_3: 0x00000000
>(II) intel(0):           TV_WIN_POS: 0x00000000
>(II) intel(0):          TV_WIN_SIZE: 0x00000000
>(II) intel(0):      TV_FILTER_CTL_1: 0x00000000
>(II) intel(0):      TV_FILTER_CTL_2: 0x00000000
>(II) intel(0):      TV_FILTER_CTL_3: 0x00000000
>(II) intel(0):        TV_CC_CONTROL: 0x00000000
>(II) intel(0):           TV_CC_DATA: 0x00000000
>(II) intel(0):          TV_H_LUMA_0: 0x00000000
>(II) intel(0):         TV_H_LUMA_59: 0x00000000
>(II) intel(0):        TV_H_CHROMA_0: 0x00000000
>(II) intel(0):       TV_H_CHROMA_59: 0x00000000
>(II) intel(0):              MI_MODE: 0x00000200
>(II) intel(0):         MI_ARB_STATE: 0x00000040
>(II) intel(0):       MI_RDRET_STATE: 0x00000000
>(II) intel(0):              ECOSKPD: 0x00000307
>(II) intel(0):                 SR00: 0x03
>(II) intel(0):                 SR01: 0x00
>(II) intel(0):                 SR02: 0x03
>(II) intel(0):                 SR03: 0x00
>(II) intel(0):                 SR04: 0x02
>(II) intel(0):                 SR05: 0x00
>(II) intel(0):                 SR06: 0x00
>(II) intel(0):                 SR07: 0x00
>(II) intel(0):                  MSR: 0x67
>(II) intel(0):                  ARX: 0x30
>(II) intel(0):                 AR00: 0x00
>(II) intel(0):                 AR01: 0x01
>(II) intel(0):                 AR02: 0x02
>(II) intel(0):                 AR03: 0x03
>(II) intel(0):                 AR04: 0x04
>(II) intel(0):                 AR05: 0x05
>(II) intel(0):                 AR06: 0x06
>(II) intel(0):                 AR07: 0x07
>(II) intel(0):                 AR08: 0x08
>(II) intel(0):                 AR09: 0x09
>(II) intel(0):                 AR0a: 0x0a
>(II) intel(0):                 AR0b: 0x0b
>(II) intel(0):                 AR0c: 0x0c
>(II) intel(0):                 AR0d: 0x0d
>(II) intel(0):                 AR0e: 0x0e
>(II) intel(0):                 AR0f: 0x0f
>(II) intel(0):                 AR10: 0x0c
>(II) intel(0):                 AR11: 0x00
>(II) intel(0):                 AR12: 0x0f
>(II) intel(0):                 AR13: 0x08
>(II) intel(0):                 AR14: 0x00
>(II) intel(0):                 CR00: 0x5f
>(II) intel(0):                 CR01: 0x4f
>(II) intel(0):                 CR02: 0x50
>(II) intel(0):                 CR03: 0x82
>(II) intel(0):                 CR04: 0x55
>(II) intel(0):                 CR05: 0x81
>(II) intel(0):                 CR06: 0xbf
>(II) intel(0):                 CR07: 0x1f
>(II) intel(0):                 CR08: 0x00
>(II) intel(0):                 CR09: 0x4f
>(II) intel(0):                 CR0a: 0x0d
>(II) intel(0):                 CR0b: 0x0e
>(II) intel(0):                 CR0c: 0x00
>(II) intel(0):                 CR0d: 0x00
>(II) intel(0):                 CR0e: 0x00
>(II) intel(0):                 CR0f: 0x00
>(II) intel(0):                 CR10: 0x9c
>(II) intel(0):                 CR11: 0x8e
>(II) intel(0):                 CR12: 0x8f
>(II) intel(0):                 CR13: 0x28
>(II) intel(0):                 CR14: 0x1f
>(II) intel(0):                 CR15: 0x96
>(II) intel(0):                 CR16: 0xb9
>(II) intel(0):                 CR17: 0xa3
>(II) intel(0):                 CR18: 0xff
>(II) intel(0):                 CR19: 0x00
>(II) intel(0):                 CR1a: 0x00
>(II) intel(0):                 CR1b: 0x00
>(II) intel(0):                 CR1c: 0x00
>(II) intel(0):                 CR1d: 0x00
>(II) intel(0):                 CR1e: 0x00
>(II) intel(0):                 CR1f: 0x00
>(II) intel(0):                 CR20: 0x00
>(II) intel(0):                 CR21: 0x00
>(II) intel(0):                 CR22: 0x20
>(II) intel(0):                 CR23: 0x00
>(II) intel(0):                 CR24: 0x00
>(II) intel(0): pipe A dot 113280 n 3 m1 20 m2 6 p1 2 p2 10
>(II) intel(0): pipe B dot 25200 n 3 m1 17 m2 8 p1 8 p2 10
>(II) intel(0): DumpRegsEnd
>(II) intel(0): 2 display pipes available.
>(==) intel(0): Using EXA for acceleration
>(II) Loading sub module "ddc"
>(II) LoadModule: "ddc"(II) Module "ddc" already built-in
>(II) Loading sub module "i2c"
>(II) LoadModule: "i2c"(II) Module "i2c" already built-in
>(II) intel(0): Output VGA using monitor section Sony Multiscan G200
>(**) intel(0): Option "PreferredMode" "1024x768_85.00"
>(II) intel(0): I2C bus "CRTDDC_A" initialized.
>(II) intel(0): I2C bus "SDVOCTRL_E for SDVOB" initialized.
>(II) intel(0): I2C device "SDVOCTRL_E for SDVOB:SDVO Controller B" registered at address 0x70.
>(II) intel(0): I2C bus "SDVOB DDC Bus" initialized.
>(II) intel(0): SDVO: W: 02                         (SDVO_CMD_GET_DEVICE_CAPS)
>(II) intel(0): SDVO: R: 05 41 31 02 01 01 02 00 (Success)
>(II) intel(0): Output VGA-1 using monitor section Sony Multiscan G200
>(II) intel(0): SDVO: W: 10 00                      (SDVO_CMD_SET_TARGET_INPUT)
>(II) intel(0): SDVO: R:                         (Success)
>(II) intel(0): SDVO: W: 1D                         (SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE)
>(II) intel(0): SDVO: R: C4 09 74 40             (Success)
>(II) intel(0): SDVO device VID/DID: 05:41.31, clock range 25.0MHz - 165.0MHz, input 1: Y, input 2: N, output 1: Y, output 2: N
>(II) intel(0): I2C bus "SDVOCTRL_E for SDVOC" initialized.
>(II) intel(0): I2C device "SDVOCTRL_E for SDVOC:SDVO Controller C" registered at address 0x72.
>(II) intel(0): No SDVO device found on SDVOC
>(II) intel(0): I2C device "SDVOCTRL_E for SDVOC:SDVO Controller C" removed.
>(II) intel(0): I2C bus "SDVOCTRL_E for SDVOC" removed.
>(II) intel(0): SDVO: W: 20                         (SDVO_CMD_GET_CLOCK_RATE_MULT)
>(II) intel(0): SDVO: R: 08                      (Success)
>(II) intel(0): Current clock rate multiplier: 8
>(II) intel(0): SDVO: W: 04                         (SDVO_CMD_GET_ACTIVE_OUTPUTS)
>(II) intel(0): SDVO: R: 02 00                   (Success)
>(II) intel(0): SDVO: W: 10 00                      (SDVO_CMD_SET_TARGET_INPUT)
>(II) intel(0): SDVO: R:                         (Success)
>(II) intel(0): SDVO: W: 12                         (SDVO_CMD_GET_INPUT_TIMINGS_PART1)
>(II) intel(0): SDVO: R: 10 0B D0 B4 20 90 31 10 (Success)
>(II) intel(0): SDVO: W: 13                         (SDVO_CMD_GET_INPUT_TIMINGS_PART2)
>(II) intel(0): SDVO: R: 2D 6C C2 00 1C 00 00 00 (Success)
>(II) intel(0): SDVO: W: 11 02 00                   (SDVO_CMD_SET_TARGET_OUTPUT)
>(II) intel(0): SDVO: R:                         (Success)
>(II) intel(0): SDVO: W: 18                         (SDVO_CMD_GET_OUTPUT_TIMINGS_PART1)
>(II) intel(0): SDVO: R: 10 0B D0 B4 20 90 31 10 (Success)
>(II) intel(0): SDVO: W: 19                         (SDVO_CMD_GET_OUTPUT_TIMINGS_PART2)
>(II) intel(0): SDVO: R: 2D 6C C2 00 1C 00 00 00 (Success)
>(II) intel(0): Mode for pipe A:
>(II) intel(0): Modeline "640x480"x0.0   31.50  640 664 704 832  480 489 491 520 -hsync -vsync (37.9 kHz)
>chosen: dotclock 31500 vco 2520000 ((m 105, m1 17, m2 8), n 2, (p 80, p1 8, p2 10))
>(II) intel(0): SDVO: W: 05 00 00                   (SDVO_CMD_SET_ACTIVE_OUTPUTS)
>(II) intel(0): SDVO: R:                         (Success)
>(II) intel(0): EDID for output VGA
>(II) intel(0): SDVO: W: 0B                         (SDVO_CMD_GET_ATTACHED_DISPLAYS)
>(II) intel(0): SDVO: R: 02 00                   (Success)
>(II) intel(0): I2C device "SDVOB DDC Bus:ddc2" registered at address 0xA0.
>(II) intel(0): SDVO: W: 7A 02                      (SDVO_CMD_SET_CONTROL_BUS_SWITCH)
>(II) intel(0): SDVO: W: 7A 02                      (SDVO_CMD_SET_CONTROL_BUS_SWITCH)
>(II) intel(0): SDVO: W: 7A 02                      (SDVO_CMD_SET_CONTROL_BUS_SWITCH)
>(II) intel(0): SDVO: W: 7A 02                      (SDVO_CMD_SET_CONTROL_BUS_SWITCH)
>(II) intel(0): SDVO: W: 7A 02                      (SDVO_CMD_SET_CONTROL_BUS_SWITCH)
>(II) intel(0): SDVO: W: 7A 02                      (SDVO_CMD_SET_CONTROL_BUS_SWITCH)
>(II) intel(0): SDVO: W: 7A 02                      (SDVO_CMD_SET_CONTROL_BUS_SWITCH)
>(II) intel(0): SDVO: W: 7A 02                      (SDVO_CMD_SET_CONTROL_BUS_SWITCH)
>(II) intel(0): I2C device "SDVOB DDC Bus:ddc2" removed.
>(II) intel(0): EDID for output VGA-1
>(II) intel(0): Mode for pipe A:
>(II) intel(0): Modeline "640x480"x0.0   31.50  640 664 704 832  480 489 491 520 -hsync -vsync (37.9 kHz)
>chosen: dotclock 31500 vco 2520000 ((m 105, m1 17, m2 8), n 2, (p 80, p1 8, p2 10))
>(II) intel(0): SDVO: W: 05 00 00                   (SDVO_CMD_SET_ACTIVE_OUTPUTS)
>(II) intel(0): SDVO: R:                         (Success)
>(II) intel(0): I2C device "CRTDDC_A:ddc2" registered at address 0xA0.
>(II) intel(0): I2C device "CRTDDC_A:ddc2" removed.
>(II) intel(0): Not using default mode "1600x1200" (mode clock too high)
>(II) intel(0): Not using default mode "1600x1200" (mode clock too high)
>(II) intel(0): Not using default mode "1600x1200" (mode clock too high)
>(II) intel(0): Not using default mode "1600x1200" (hsync out of range)
>(II) intel(0): Not using default mode "1792x1344" (mode clock too high)
>(II) intel(0): Not using default mode "1792x1344" (hsync out of range)
>(II) intel(0): Not using default mode "1856x1392" (mode clock too high)
>(II) intel(0): Not using default mode "1856x1392" (hsync out of range)
>(II) intel(0): Not using default mode "1920x1440" (mode clock too high)
>(II) intel(0): Not using default mode "1920x1440" (hsync out of range)
>(II) intel(0): Not using default mode "1400x1050" (mode clock too high)
>(II) intel(0): Not using default mode "1920x1200" (mode clock too high)
>(II) intel(0): Not using default mode "1920x1200" (mode clock too high)
>(II) intel(0): Not using default mode "1920x1440" (hsync out of range)
>(II) intel(0): Not using default mode "2048x1536" (mode clock too high)
>(II) intel(0): Not using default mode "2048x1536" (hsync out of range)
>(II) intel(0): Not using default mode "2048x1536" (hsync out of range)
>(II) intel(0): Printing probed modes for output VGA-1
>(II) intel(0): Modeline "1024x768_85.00"x85.0   94.39  1024 1088 1200 1376  768 769 772 807 -hsync +vsync (68.6 kHz)
>(II) intel(0): Modeline "1600x1200"x60.0  162.00  1600 1664 1856 2160  1200 1201 1204 1250 +hsync +vsync (75.0 kHz)
>(II) intel(0): Modeline "1680x1050"x60.0  147.14  1680 1784 1968 2256  1050 1051 1054 1087 (65.2 kHz)
>(II) intel(0): Modeline "1600x1024"x60.0  106.91  1600 1620 1640 1670  1024 1027 1030 1067 -hsync -vsync (64.0 kHz)
>(II) intel(0): Modeline "1400x1050"x74.8  155.80  1400 1464 1784 1912  1050 1052 1064 1090 +hsync +vsync (81.5 kHz)
>(II) intel(0): Modeline "1400x1050"x70.0  151.00  1400 1464 1656 1960  1050 1051 1054 1100 +hsync +vsync (77.0 kHz)
>(II) intel(0): Modeline "1400x1050"x60.0  122.00  1400 1488 1640 1880  1050 1052 1064 1082 +hsync +vsync (64.9 kHz)
>(II) intel(0): Modeline "1280x1024"x85.0  157.50  1280 1344 1504 1728  1024 1025 1028 1072 +hsync +vsync (91.1 kHz)
>(II) intel(0): Modeline "1280x1024"x75.0  135.00  1280 1296 1440 1688  1024 1025 1028 1066 +hsync +vsync (80.0 kHz)
>(II) intel(0): Modeline "1280x1024"x60.0  108.00  1280 1328 1440 1688  1024 1025 1028 1066 +hsync +vsync (64.0 kHz)
>(II) intel(0): Modeline "1440x900"x60.2  108.84  1440 1472 1880 1912  900 918 927 946 +hsync +vsync (56.9 kHz)
>(II) intel(0): Modeline "1280x960"x85.0  148.50  1280 1344 1504 1728  960 961 964 1011 +hsync +vsync (85.9 kHz)
>(II) intel(0): Modeline "1280x960"x60.0  108.00  1280 1376 1488 1800  960 961 964 1000 +hsync +vsync (60.0 kHz)
>(II) intel(0): Modeline "1280x800"x60.0   83.46  1280 1344 1480 1680  800 801 804 828 (49.7 kHz)
>(II) intel(0): Modeline "1152x864"x85.1  121.50  1152 1216 1344 1568  864 865 868 911 +hsync -vsync (77.5 kHz)
>(II) intel(0): Modeline "1152x864"x75.0  108.00  1152 1216 1344 1600  864 865 868 900 +hsync +vsync (67.5 kHz)
>(II) intel(0): Modeline "1280x768"x60.0   80.14  1280 1344 1480 1680  768 769 772 795 (47.7 kHz)
>(II) intel(0): Modeline "1152x768"x54.8   65.00  1152 1178 1314 1472  768 771 777 806 +hsync +vsync (44.2 kHz)
>(II) intel(0): Modeline "1024x768"x85.0   94.50  1024 1072 1168 1376  768 769 772 808 +hsync +vsync (68.7 kHz)
>(II) intel(0): Modeline "1024x768"x75.0   78.75  1024 1040 1136 1312  768 769 772 800 +hsync +vsync (60.0 kHz)
>(II) intel(0): Modeline "1024x768"x70.1   75.00  1024 1048 1184 1328  768 771 777 806 -hsync -vsync (56.5 kHz)
>(II) intel(0): Modeline "1024x768"x60.0   65.00  1024 1048 1184 1344  768 771 777 806 -hsync -vsync (48.4 kHz)
>(II) intel(0): Modeline "832x624"x74.6   57.28  832 864 928 1152  624 625 628 667 -hsync -vsync (49.7 kHz)
>(II) intel(0): Modeline "800x600"x85.1   56.30  800 832 896 1048  600 601 604 631 +hsync +vsync (53.7 kHz)
>(II) intel(0): Modeline "800x600"x72.2   50.00  800 856 976 1040  600 637 643 666 +hsync +vsync (48.1 kHz)
>(II) intel(0): Modeline "800x600"x75.0   49.50  800 816 896 1056  600 601 604 625 +hsync +vsync (46.9 kHz)
>(II) intel(0): Modeline "800x600"x60.3   40.00  800 840 968 1056  600 601 605 628 +hsync +vsync (37.9 kHz)
>(II) intel(0): Modeline "800x600"x56.2   36.00  800 824 896 1024  600 601 603 625 +hsync +vsync (35.2 kHz)
>(II) intel(0): Modeline "640x480"x85.0   36.00  640 696 752 832  480 481 484 509 -hsync -vsync (43.3 kHz)
>(II) intel(0): Modeline "640x480"x72.8   31.50  640 664 704 832  480 489 492 520 -hsync -vsync (37.9 kHz)
>(II) intel(0): Modeline "640x480"x75.0   31.50  640 656 720 840  480 481 484 500 -hsync -vsync (37.5 kHz)
>(II) intel(0): Modeline "640x480"x59.9   25.18  640 656 752 800  480 490 492 525 -hsync -vsync (31.5 kHz)
>(II) intel(0): Modeline "720x400"x85.0   35.50  720 756 828 936  400 401 404 446 -hsync +vsync (37.9 kHz)
>(II) intel(0): Modeline "640x400"x85.1   31.50  640 672 736 832  400 401 404 445 -hsync +vsync (37.9 kHz)
>(II) intel(0): Modeline "640x350"x85.1   31.50  640 672 736 832  350 382 385 445 +hsync -vsync (37.9 kHz)
>(II) intel(0): Output VGA disconnected
>(II) intel(0): Output VGA-1 connected
>(II) intel(0): Output VGA-1 using initial mode 1024x768_85.00
>(II) intel(0): SDVO: W: 05 00 00                   (SDVO_CMD_SET_ACTIVE_OUTPUTS)
>(II) intel(0): SDVO: R:                         (Success)
>(II) intel(0): SDVO: W: 05 00 00                   (SDVO_CMD_SET_ACTIVE_OUTPUTS)
>(II) intel(0): SDVO: R:                         (Success)
>(II) intel(0): SDVO: W: 11 02 00                   (SDVO_CMD_SET_TARGET_OUTPUT)
>(II) intel(0): SDVO: R:                         (Success)
>(II) intel(0): SDVO: W: 16 10 0B D0 B4 20 90 31 10 (SDVO_CMD_SET_OUTPUT_TIMINGS_PART1)
>(II) intel(0): SDVO: R:                         (Not supported)
>(II) intel(0): SDVO: W: 10 00                      (SDVO_CMD_SET_TARGET_INPUT)
>(II) intel(0): SDVO: R:                         (Success)
>(II) intel(0): SDVO: W: 14 10 0B D0 B4 20 90 31 10 (SDVO_CMD_SET_INPUT_TIMINGS_PART1)
>(II) intel(0): SDVO: R:                         (Success)
>(II) intel(0): SDVO: W: 15 2D 6C C2 00 1C 00 00 00 (SDVO_CMD_SET_INPUT_TIMINGS_PART2)
>(II) intel(0): SDVO: R:                         (Success)
>(II) intel(0): SDVO: W: 21 08                      (SDVO_CMD_SET_CLOCK_RATE_MULT)
>(II) intel(0): SDVO: R:                         (Success)
>(II) intel(0): SDVO: W: 03                         (SDVO_CMD_GET_TRAINED_INPUTS)
>(II) intel(0): SDVO: R: 01                      (Success)
>(II) intel(0): SDVO: W: 05 02 00                   (SDVO_CMD_SET_ACTIVE_OUTPUTS)
>(II) intel(0): SDVO: R:                         (Success)
>(II) intel(0): detected 1024 kB GTT.
>(II) intel(0): detected 7164 kB stolen memory.
>(==) intel(0): video overlay key set to 0x83e
>(==) intel(0): Will not try to enable page flipping
>(==) intel(0): Triple buffering disabled
>(==) intel(0): Intel XvMC decoder disabled
>(==) intel(0): Using gamma correction (1.0, 1.0, 1.0)
>(==) intel(0): DPI set to (96, 96)
>(II) Loading sub module "fb"
>(II) LoadModule: "fb"
>(II) Loading /usr/lib/xorg/modules//libfb.so
>(II) Module fb: vendor="X.Org Foundation"
>	compiled for 1.4.0.90, module version = 1.0.0
>	ABI class: X.Org ANSI C Emulation, version 0.3
>(II) Loading sub module "exa"
>(II) LoadModule: "exa"
>(II) Loading /usr/lib/xorg/modules//libexa.so
>(II) Module exa: vendor="X.Org Foundation"
>	compiled for 1.4.0.90, module version = 2.2.0
>	ABI class: X.Org Video Driver, version 2.0
>(II) Loading sub module "ramdac"
>(II) LoadModule: "ramdac"(II) Module "ramdac" already built-in
>(II) intel(0): Comparing regs from server start up to After PreInit
>(WW) intel(0): Register 0x70024 (PIPEASTAT) changed from 0x00020203 to 0x80020203
>(WW) intel(0): PIPEASTAT before: status: VBLANK_INT_ENABLE VSYNC_INT_STATUS VBLANK_INT_STATUS OREG_UPDATE_STATUS
>(WW) intel(0): PIPEASTAT after: status: FIFO_UNDERRUN VBLANK_INT_ENABLE VSYNC_INT_STATUS VBLANK_INT_STATUS OREG_UPDATE_STATUS
>(II) do I need RAC?  No, I don't.
>(II) resource ranges after preInit:
>	[0] 0	0	0xfe700000 - 0xfe7fffff (0x100000) MS[B]
>	[1] 0	0	0xd0000000 - 0xdfffffff (0x10000000) MS[B]
>	[2] 0	0	0xfe800000 - 0xfe87ffff (0x80000) MS[B]
>	[3] -1	0	0x00100000 - 0x3fffffff (0x3ff00000) MX[B]E(B)
>	[4] -1	0	0x000f0000 - 0x000fffff (0x10000) MX[B]
>	[5] -1	0	0x000c0000 - 0x000effff (0x30000) MX[B]
>	[6] -1	0	0x00000000 - 0x0009ffff (0xa0000) MX[B]
>	[7] -1	0	0xfebff000 - 0xfebff7ff (0x800) MX[B]
>	[8] -1	0	0xfebffc00 - 0xfebffc7f (0x80) MX[B]
>	[9] -1	0	0xfdfff000 - 0xfdffffff (0x1000) MX[B]
>	[10] -1	0	0xfeafe000 - 0xfeafffff (0x2000) MX[B]
>	[11] -1	0	0xfe9c0000 - 0xfe9fffff (0x40000) MX[B]
>	[12] -1	0	0xfe6fb400 - 0xfe6fb4ff (0x100) MX[B]
>	[13] -1	0	0xfe6fb800 - 0xfe6fbbff (0x400) MX[B]
>	[14] -1	0	0xfe6f4000 - 0xfe6f7fff (0x4000) MX[B]
>	[15] -1	0	0xfe6fbc00 - 0xfe6fbfff (0x400) MX[B]
>	[16] -1	0	0xfdffe000 - 0xfdffefff (0x1000) MX[B](B)
>	[17] -1	0	0xfe880000 - 0xfe8fffff (0x80000) MX[B](B)
>	[18] -1	0	0xfe700000 - 0xfe7fffff (0x100000) MX[B](B)
>	[19] -1	0	0xd0000000 - 0xdfffffff (0x10000000) MX[B](B)
>	[20] -1	0	0xfe800000 - 0xfe87ffff (0x80000) MX[B](B)
>	[21] 0	0	0x000a0000 - 0x000affff (0x10000) MS[B](OprD)
>	[22] 0	0	0x000b0000 - 0x000b7fff (0x8000) MS[B](OprD)
>	[23] 0	0	0x000b8000 - 0x000bffff (0x8000) MS[B](OprD)
>	[24] 0	0	0x0000cc00 - 0x0000cc07 (0x8) IS[B]
>	[25] -1	0	0x0000ffff - 0x0000ffff (0x1) IX[B]
>	[26] -1	0	0x00000000 - 0x000000ff (0x100) IX[B]
>	[27] -1	0	0x0000e880 - 0x0000e8ff (0x80) IX[B]
>	[28] -1	0	0x0000ec00 - 0x0000ec7f (0x80) IX[B]
>	[29] -1	0	0x0000d400 - 0x0000d40f (0x10) IX[B]
>	[30] -1	0	0x0000d480 - 0x0000d483 (0x4) IX[B]
>	[31] -1	0	0x0000d800 - 0x0000d807 (0x8) IX[B]
>	[32] -1	0	0x0000d880 - 0x0000d883 (0x4) IX[B]
>	[33] -1	0	0x0000dc00 - 0x0000dc07 (0x8) IX[B]
>	[34] -1	0	0x0000b080 - 0x0000b08f (0x10) IX[B]
>	[35] -1	0	0x0000b400 - 0x0000b40f (0x10) IX[B]
>	[36] -1	0	0x0000b480 - 0x0000b483 (0x4) IX[B]
>	[37] -1	0	0x0000b800 - 0x0000b807 (0x8) IX[B]
>	[38] -1	0	0x0000b880 - 0x0000b883 (0x4) IX[B]
>	[39] -1	0	0x0000bc00 - 0x0000bc07 (0x8) IX[B]
>	[40] -1	0	0x00000400 - 0x0000041f (0x20) IX[B]
>	[41] -1	0	0x0000a080 - 0x0000a08f (0x10) IX[B]
>	[42] -1	0	0x0000a400 - 0x0000a40f (0x10) IX[B]
>	[43] -1	0	0x0000a480 - 0x0000a483 (0x4) IX[B]
>	[44] -1	0	0x0000a800 - 0x0000a807 (0x8) IX[B]
>	[45] -1	0	0x0000a880 - 0x0000a883 (0x4) IX[B]
>	[46] -1	0	0x0000ac00 - 0x0000ac07 (0x8) IX[B]
>	[47] -1	0	0x0000c400 - 0x0000c41f (0x20) IX[B]
>	[48] -1	0	0x0000c080 - 0x0000c09f (0x20) IX[B]
>	[49] -1	0	0x0000c000 - 0x0000c01f (0x20) IX[B]
>	[50] -1	0	0x0000c880 - 0x0000c89f (0x20) IX[B]
>	[51] -1	0	0x0000c800 - 0x0000c81f (0x20) IX[B]
>	[52] -1	0	0x0000c480 - 0x0000c49f (0x20) IX[B]
>	[53] -1	0	0x0000cc00 - 0x0000cc07 (0x8) IX[B](B)
>	[54] 0	0	0x000003b0 - 0x000003bb (0xc) IS[B](OprU)
>	[55] 0	0	0x000003c0 - 0x000003df (0x20) IS[B](OprU)
>(II) intel(0): Kernel reported 488960 total, 1 used
>(II) intel(0): I830CheckAvailableMemory: 1955836 kB available
>drmOpenDevice: node name is /dev/dri/card0
>drmOpenDevice: open result is 9, (OK)
>drmOpenDevice: node name is /dev/dri/card0
>drmOpenDevice: open result is 9, (OK)
>drmOpenByBusid: Searching for BusID pci:0000:00:02.0
>drmOpenDevice: node name is /dev/dri/card0
>drmOpenDevice: open result is 9, (OK)
>drmOpenByBusid: drmOpenMinor returns 9
>drmOpenByBusid: drmGetBusid reports pci:0000:00:02.0
>(II) [drm] DRM interface version 1.3
>(II) [drm] DRM open master succeeded.
>(II) intel(0): [drm] Using the DRM lock SAREA also for drawables.
>(II) intel(0): [drm] framebuffer mapped by ddx driver
>(II) intel(0): [drm] added 1 reserved context for kernel
>(II) intel(0): X context handle = 0x1
>(II) intel(0): [drm] installed DRM signal handler
>(**) intel(0): Framebuffer compression disabled
>(**) intel(0): Tiling enabled
>(==) intel(0): VideoRam: 262144 KB
>(II) intel(0): Attempting memory allocation with tiled buffers.
>(II) intel(0): Tiled allocation successful.
>(II) intel(0): [drm] Registers = 0xfe800000
>(II) intel(0): [drm] ring buffer = 0xd0000000
>(II) intel(0): [drm] mapped front buffer at 0xd0800000, handle = 0xd0800000
>(II) intel(0): [drm] mapped back buffer at 0xd2800000, handle = 0xd2800000
>(II) intel(0): [drm] mapped depth buffer at 0xd3000000, handle = 0xd3000000
>(II) intel(0): [drm] mapped classic textures at 0xd3800000, handle = 0xd3800000
>(II) intel(0): [drm] Initialized kernel agp heap manager, 33554432
>(II) intel(0): [dri] visual configs initialized
>(II) intel(0): Page Flipping disabled
>(==) intel(0): Write-combining range (0xd0000000,0x10000000)
>(II) intel(0): vgaHWGetIOBase: hwp->IOBase is 0x03d0, hwp->PIOOffset is 0x0000
>(II) EXA(0): Offscreen pixmap area of 20643840 bytes
>(II) EXA(0): Driver registered support for the following operations:
>(II)         Solid
>(II)         Copy
>(II)         Composite (RENDER acceleration)
>(==) intel(0): Backing store disabled
>(==) intel(0): Silken mouse enabled
>(II) intel(0): Initializing HW Cursor
>(II) intel(0): [DRI] installation complete
>(II) intel(0): SDVO: W: 20                         (SDVO_CMD_GET_CLOCK_RATE_MULT)
>(II) intel(0): SDVO: R: 08                      (Success)
>(II) intel(0): Current clock rate multiplier: 8
>(II) intel(0): SDVO: W: 04                         (SDVO_CMD_GET_ACTIVE_OUTPUTS)
>(II) intel(0): SDVO: R: 02 00                   (Success)
>(II) intel(0): SDVO: W: 10 00                      (SDVO_CMD_SET_TARGET_INPUT)
>(II) intel(0): SDVO: R:                         (Success)
>(II) intel(0): SDVO: W: 12                         (SDVO_CMD_GET_INPUT_TIMINGS_PART1)
>(II) intel(0): SDVO: R: 10 0B D0 B4 20 90 31 10 (Success)
>(II) intel(0): SDVO: W: 13                         (SDVO_CMD_GET_INPUT_TIMINGS_PART2)
>(II) intel(0): SDVO: R: 2D 6C C2 00 1C 00 00 00 (Success)
>(II) intel(0): SDVO: W: 11 02 00                   (SDVO_CMD_SET_TARGET_OUTPUT)
>(II) intel(0): SDVO: R:                         (Success)
>(II) intel(0): SDVO: W: 18                         (SDVO_CMD_GET_OUTPUT_TIMINGS_PART1)
>(II) intel(0): SDVO: R: 10 0B D0 B4 20 90 31 10 (Success)
>(II) intel(0): SDVO: W: 19                         (SDVO_CMD_GET_OUTPUT_TIMINGS_PART2)
>(II) intel(0): SDVO: R: 2D 6C C2 00 1C 00 00 00 (Success)
>(II) intel(0): xf86BindGARTMemory: bind key 0 at 0x00800000 (pgoffset 2048)
>(II) intel(0): xf86BindGARTMemory: bind key 1 at 0x01000000 (pgoffset 4096)
>(II) intel(0): xf86BindGARTMemory: bind key 2 at 0x02800000 (pgoffset 10240)
>(II) intel(0): xf86BindGARTMemory: bind key 3 at 0x03000000 (pgoffset 12288)
>(II) intel(0): xf86BindGARTMemory: bind key 4 at 0x03800000 (pgoffset 14336)
>(II) intel(0): Fixed memory allocation layout:
>(II) intel(0): 0x00000000-0x0001ffff: ring buffer (128 kB)
>(II) intel(0): 0x00020000-0x00029fff: HW cursors (40 kB)
>(II) intel(0): 0x0002a000-0x00031fff: logical 3D context (32 kB)
>(II) intel(0): 0x00032000-0x00032fff: overlay registers (4 kB)
>(II) intel(0): 0x00033000-0x00033fff: HW status (4 kB)
>(II) intel(0): 0x006ff000:            end of stolen memory
>(II) intel(0): 0x00800000-0x00ffffff: front buffer (6720 kB) X tiled
>(II) intel(0): 0x01000000-0x023affff: exa offscreen (20160 kB)
>(II) intel(0): 0x02800000-0x02ffffff: back buffer (6720 kB) X tiled
>(II) intel(0): 0x03000000-0x037fffff: depth buffer (6720 kB) X tiled
>(II) intel(0): 0x03800000-0x057fffff: classic textures (32768 kB)
>(II) intel(0): 0x10000000:            end of aperture
>(II) intel(0): SDVO: W: 05 00 00                   (SDVO_CMD_SET_ACTIVE_OUTPUTS)
>(II) intel(0): SDVO: R:                         (Success)
>(II) intel(0): SDVO: W: 05 00 00                   (SDVO_CMD_SET_ACTIVE_OUTPUTS)
>(II) intel(0): SDVO: R:                         (Success)
>(II) intel(0): Mode for pipe A:
>(II) intel(0): Modeline "1024x768_85.00"x85.0   94.39  1024 1088 1200 1376  768 769 772 807 -hsync +vsync (68.6 kHz)
>(II) intel(0): Adjusted mode for pipe A:
>(II) intel(0): Modeline "1024x768_85.00"x85.0  188.78  1024 1088 1200 1376  768 769 772 807 -hsync +vsync (137.2 kHz)
>chosen: dotclock 188800 vco 1888000 ((m 118, m1 20, m2 6), n 4, (p 10, p1 1, p2 10))
>(II) intel(0): SDVO: W: 11 02 00                   (SDVO_CMD_SET_TARGET_OUTPUT)
>(II) intel(0): SDVO: R:                         (Success)
>(II) intel(0): SDVO: W: 16 DF 24 00 60 41 00 27 30 (SDVO_CMD_SET_OUTPUT_TIMINGS_PART1)
>(II) intel(0): SDVO: R:                         (Not supported)
>(II) intel(0): SDVO: W: 10 00                      (SDVO_CMD_SET_TARGET_INPUT)
>(II) intel(0): SDVO: R:                         (Success)
>(II) intel(0): SDVO: W: 14 DF 24 00 60 41 00 27 30 (SDVO_CMD_SET_INPUT_TIMINGS_PART1)
>(II) intel(0): SDVO: R:                         (Success)
>(II) intel(0): SDVO: W: 15 40 70 13 00 1C 00 00 00 (SDVO_CMD_SET_INPUT_TIMINGS_PART2)
>(II) intel(0): SDVO: R:                         (Success)
>(II) intel(0): SDVO: W: 21 02                      (SDVO_CMD_SET_CLOCK_RATE_MULT)
>(II) intel(0): SDVO: R:                         (Success)
>(II) intel(0): SDVO: W: 03                         (SDVO_CMD_GET_TRAINED_INPUTS)
>(II) intel(0): SDVO: R: 01                      (Success)
>(II) intel(0): SDVO: W: 05 02 00                   (SDVO_CMD_SET_ACTIVE_OUTPUTS)
>(II) intel(0): SDVO: R:                         (Success)
>(II) intel(0): Hardware state at EnterVT:
>(II) intel(0): DumpRegsBegin
>(II) intel(0):    VCLK_DIVISOR_VGA0: 0x00031108 (n = 3, m1 = 17, m2 = 8)
>(II) intel(0):    VCLK_DIVISOR_VGA1: 0x00031406 (n = 3, m1 = 20, m2 = 6)
>(II) intel(0):        VCLK_POST_DIV: 0x00020002 (vga0 p1 = 4, p2 = 2, vga1 p1 = 2, p2 = 2)
>(II) intel(0):            DPLL_TEST: 0x00010001 ()
>(II) intel(0):         CACHE_MODE_0: 0x00006820
>(II) intel(0):              D_STATE: 0x00000000
>(II) intel(0):        DSPCLK_GATE_D: 0x00000000 (clock gates disabled:)
>(II) intel(0):       RENCLK_GATE_D1: 0x00000000
>(II) intel(0):       RENCLK_GATE_D2: 0x00000000
>(II) intel(0):                SDVOB: 0x80480084 (enabled, pipe A, stall disabled, detected)
>(II) intel(0):                SDVOC: 0x00300000 (disabled, pipe A, stall disabled, not detected)
>(II) intel(0):              SDVOUDI: 0x00000000
>(II) intel(0):               DSPARB: 0x00001d9c
>(II) intel(0):               DSPFW1: 0x00000000
>(II) intel(0):               DSPFW2: 0x00000000
>(II) intel(0):               DSPFW3: 0x00000000
>(II) intel(0):                 ADPA: 0x00008c18 (disabled, pipe A, +hsync, +vsync)
>(II) intel(0):                 LVDS: 0x00000000 (disabled, pipe A, 18 bit, 1 channel)
>(II) intel(0):                 DVOA: 0x00000000 (disabled, pipe A, no stall, -hsync, -vsync)
>(II) intel(0):                 DVOB: 0x80480084 (enabled, pipe A, no stall, -hsync, -vsync)
>(II) intel(0):                 DVOC: 0x00300000 (disabled, pipe A, no stall, -hsync, -vsync)
>(II) intel(0):          DVOA_SRCDIM: 0x00000000
>(II) intel(0):          DVOB_SRCDIM: 0x00000000
>(II) intel(0):          DVOC_SRCDIM: 0x00000000
>(II) intel(0):           PP_CONTROL: 0x00000000 (power target: off)
>(II) intel(0):            PP_STATUS: 0x00000000 (off, not ready, sequencing idle)
>(II) intel(0):         PFIT_CONTROL: 0x00000000
>(II) intel(0):      PFIT_PGM_RATIOS: 0x00000000
>(II) intel(0):      PORT_HOTPLUG_EN: 0x00000020
>(II) intel(0):    PORT_HOTPLUG_STAT: 0x00000000
>(II) intel(0):             DSPACNTR: 0xd4000000 (enabled, pipe A)
>(II) intel(0):           DSPASTRIDE: 0x00001000 (4096 bytes)
>(II) intel(0):              DSPAPOS: 0x00000000 (0, 0)
>(II) intel(0):             DSPASIZE: 0x02ff03ff (1024, 768)
>(II) intel(0):             DSPABASE: 0x00800000
>(II) intel(0):             DSPASURF: 0x00000000
>(II) intel(0):          DSPATILEOFF: 0x00000000
>(II) intel(0):            PIPEACONF: 0x80000000 (enabled, single-wide)
>(II) intel(0):             PIPEASRC: 0x03ff02ff (1024, 768)
>(II) intel(0):            PIPEASTAT: 0x80020203 (status: FIFO_UNDERRUN VBLANK_INT_ENABLE VSYNC_INT_STATUS VBLANK_INT_STATUS OREG_UPDATE_STATUS)
>(II) intel(0):         FBC_CFB_BASE: 0xffffffff
>(II) intel(0):          FBC_LL_BASE: 0xffffffff
>(II) intel(0):          FBC_CONTROL: 0xffffffff
>(II) intel(0):          FBC_COMMAND: 0xffffffff
>(II) intel(0):           FBC_STATUS: 0xffffffff
>(II) intel(0):         FBC_CONTROL2: 0xffffffff
>(II) intel(0):        FBC_FENCE_OFF: 0xffffffff
>(II) intel(0):          FBC_MOD_NUM: 0xffffffff
>(II) intel(0):                 FPA0: 0x00041406 (n = 4, m1 = 20, m2 = 6)
>(II) intel(0):                 FPA1: 0x00031108 (n = 3, m1 = 17, m2 = 8)
>(II) intel(0):               DPLL_A: 0xd4010010 (enabled, dvo, default clock, DAC/serial mode, p1 = 1, p2 = 10, SDVO mult 2)
>(II) intel(0):            DPLL_A_MD: 0x00000000
>(II) intel(0):             HTOTAL_A: 0x055f03ff (1024 active, 1376 total)
>(II) intel(0):             HBLANK_A: 0x055f03ff (1024 start, 1376 end)
>(II) intel(0):              HSYNC_A: 0x04af043f (1088 start, 1200 end)
>(II) intel(0):             VTOTAL_A: 0x032602ff (768 active, 807 total)
>(II) intel(0):             VBLANK_A: 0x032602ff (768 start, 807 end)
>(II) intel(0):              VSYNC_A: 0x03030300 (769 start, 772 end)
>(II) intel(0):            BCLRPAT_A: 0x00000000
>(II) intel(0):         VSYNCSHIFT_A: 0x00000000
>(II) intel(0):             DSPBCNTR: 0x01000000 (disabled, pipe B)
>(II) intel(0):           DSPBSTRIDE: 0x00000000 (0 bytes)
>(II) intel(0):              DSPBPOS: 0x00000000 (0, 0)
>(II) intel(0):             DSPBSIZE: 0x00000000 (1, 1)
>(II) intel(0):             DSPBBASE: 0x00000000
>(II) intel(0):             DSPBSURF: 0x00000000
>(II) intel(0):          DSPBTILEOFF: 0x00000000
>(II) intel(0):            PIPEBCONF: 0x00000000 (disabled, single-wide)
>(II) intel(0):             PIPEBSRC: 0x027f01df (640, 480)
>(II) intel(0):            PIPEBSTAT: 0x00020000 (status: VBLANK_INT_ENABLE)
>(II) intel(0):                 FPB0: 0x00031108 (n = 3, m1 = 17, m2 = 8)
>(II) intel(0):                 FPB1: 0x00031108 (n = 3, m1 = 17, m2 = 8)
>(II) intel(0):               DPLL_B: 0x04800003 (disabled, non-dvo, VGA, default clock, DAC/serial mode, p1 = 8, p2 = 10, SDVO mult 1)
>(II) intel(0):            DPLL_B_MD: 0x00000000
>(II) intel(0):             HTOTAL_B: 0x031f027f (640 active, 800 total)
>(II) intel(0):             HBLANK_B: 0x03170287 (648 start, 792 end)
>(II) intel(0):              HSYNC_B: 0x02ef028f (656 start, 752 end)
>(II) intel(0):             VTOTAL_B: 0x020c01df (480 active, 525 total)
>(II) intel(0):             VBLANK_B: 0x020401e7 (488 start, 517 end)
>(II) intel(0):              VSYNC_B: 0x01eb01e9 (490 start, 492 end)
>(II) intel(0):            BCLRPAT_B: 0x00000000
>(II) intel(0):         VSYNCSHIFT_B: 0x00000000
>(II) intel(0):    VCLK_DIVISOR_VGA0: 0x00031108
>(II) intel(0):    VCLK_DIVISOR_VGA1: 0x00031406
>(II) intel(0):        VCLK_POST_DIV: 0x00020002
>(II) intel(0):             VGACNTRL: 0x80000000 (disabled)
>(II) intel(0):               TV_CTL: 0x00000000
>(II) intel(0):               TV_DAC: 0x00000000
>(II) intel(0):             TV_CSC_Y: 0x00000000
>(II) intel(0):            TV_CSC_Y2: 0x00000000
>(II) intel(0):             TV_CSC_U: 0x00000000
>(II) intel(0):            TV_CSC_U2: 0x00000000
>(II) intel(0):             TV_CSC_V: 0x00000000
>(II) intel(0):            TV_CSC_V2: 0x00000000
>(II) intel(0):         TV_CLR_KNOBS: 0x00000000
>(II) intel(0):         TV_CLR_LEVEL: 0x00000000
>(II) intel(0):           TV_H_CTL_1: 0x00000000
>(II) intel(0):           TV_H_CTL_2: 0x00000000
>(II) intel(0):           TV_H_CTL_3: 0x00000000
>(II) intel(0):           TV_V_CTL_1: 0x00000000
>(II) intel(0):           TV_V_CTL_2: 0x00000000
>(II) intel(0):           TV_V_CTL_3: 0x00000000
>(II) intel(0):           TV_V_CTL_4: 0x00000000
>(II) intel(0):           TV_V_CTL_5: 0x00000000
>(II) intel(0):           TV_V_CTL_6: 0x00000000
>(II) intel(0):           TV_V_CTL_7: 0x00000000
>(II) intel(0):          TV_SC_CTL_1: 0x00000000
>(II) intel(0):          TV_SC_CTL_2: 0x00000000
>(II) intel(0):          TV_SC_CTL_3: 0x00000000
>(II) intel(0):           TV_WIN_POS: 0x00000000
>(II) intel(0):          TV_WIN_SIZE: 0x00000000
>(II) intel(0):      TV_FILTER_CTL_1: 0x00000000
>(II) intel(0):      TV_FILTER_CTL_2: 0x00000000
>(II) intel(0):      TV_FILTER_CTL_3: 0x00000000
>(II) intel(0):        TV_CC_CONTROL: 0x00000000
>(II) intel(0):           TV_CC_DATA: 0x00000000
>(II) intel(0):          TV_H_LUMA_0: 0x00000000
>(II) intel(0):         TV_H_LUMA_59: 0x00000000
>(II) intel(0):        TV_H_CHROMA_0: 0x00000000
>(II) intel(0):       TV_H_CHROMA_59: 0x00000000
>(II) intel(0):              MI_MODE: 0x00000200
>(II) intel(0):         MI_ARB_STATE: 0x00000040
>(II) intel(0):       MI_RDRET_STATE: 0x00000000
>(II) intel(0):              ECOSKPD: 0x00000307
>(II) intel(0):                 SR00: 0x03
>(II) intel(0):                 SR01: 0x00
>(II) intel(0):                 SR02: 0x03
>(II) intel(0):                 SR03: 0x00
>(II) intel(0):                 SR04: 0x02
>(II) intel(0):                 SR05: 0x00
>(II) intel(0):                 SR06: 0x00
>(II) intel(0):                 SR07: 0x00
>(II) intel(0):                  MSR: 0x67
>(II) intel(0):                  ARX: 0x30
>(II) intel(0):                 AR00: 0x00
>(II) intel(0):                 AR01: 0x01
>(II) intel(0):                 AR02: 0x02
>(II) intel(0):                 AR03: 0x03
>(II) intel(0):                 AR04: 0x04
>(II) intel(0):                 AR05: 0x05
>(II) intel(0):                 AR06: 0x06
>(II) intel(0):                 AR07: 0x07
>(II) intel(0):                 AR08: 0x08
>(II) intel(0):                 AR09: 0x09
>(II) intel(0):                 AR0a: 0x0a
>(II) intel(0):                 AR0b: 0x0b
>(II) intel(0):                 AR0c: 0x0c
>(II) intel(0):                 AR0d: 0x0d
>(II) intel(0):                 AR0e: 0x0e
>(II) intel(0):                 AR0f: 0x0f
>(II) intel(0):                 AR10: 0x0c
>(II) intel(0):                 AR11: 0x00
>(II) intel(0):                 AR12: 0x0f
>(II) intel(0):                 AR13: 0x08
>(II) intel(0):                 AR14: 0x00
>(II) intel(0):                 CR00: 0x5f
>(II) intel(0):                 CR01: 0x4f
>(II) intel(0):                 CR02: 0x50
>(II) intel(0):                 CR03: 0x82
>(II) intel(0):                 CR04: 0x55
>(II) intel(0):                 CR05: 0x81
>(II) intel(0):                 CR06: 0xbf
>(II) intel(0):                 CR07: 0x1f
>(II) intel(0):                 CR08: 0x00
>(II) intel(0):                 CR09: 0x4f
>(II) intel(0):                 CR0a: 0x0d
>(II) intel(0):                 CR0b: 0x0e
>(II) intel(0):                 CR0c: 0x00
>(II) intel(0):                 CR0d: 0x00
>(II) intel(0):                 CR0e: 0x00
>(II) intel(0):                 CR0f: 0x00
>(II) intel(0):                 CR10: 0x9c
>(II) intel(0):                 CR11: 0x0e
>(II) intel(0):                 CR12: 0x8f
>(II) intel(0):                 CR13: 0x28
>(II) intel(0):                 CR14: 0x1f
>(II) intel(0):                 CR15: 0x96
>(II) intel(0):                 CR16: 0xb9
>(II) intel(0):                 CR17: 0xa3
>(II) intel(0):                 CR18: 0xff
>(II) intel(0):                 CR19: 0x00
>(II) intel(0):                 CR1a: 0x00
>(II) intel(0):                 CR1b: 0x00
>(II) intel(0):                 CR1c: 0x00
>(II) intel(0):                 CR1d: 0x00
>(II) intel(0):                 CR1e: 0x00
>(II) intel(0):                 CR1f: 0x00
>(II) intel(0):                 CR20: 0x00
>(II) intel(0):                 CR21: 0x00
>(II) intel(0):                 CR22: 0x00
>(II) intel(0):                 CR23: 0x00
>(II) intel(0):                 CR24: 0x00
>(II) intel(0): pipe A dot 188800 n 4 m1 20 m2 6 p1 1 p2 10
>(II) intel(0): pipe B dot 25200 n 3 m1 17 m2 8 p1 8 p2 10
>(II) intel(0): DumpRegsEnd
>(II) intel(0): Output configuration:
>(II) intel(0):   Pipe A is on
>(II) intel(0):   Display plane A is now enabled and connected to pipe A.
>(II) intel(0):   Pipe B is off
>(II) intel(0):   Display plane B is now disabled and connected to pipe B.
>(II) intel(0):   Output VGA is connected to pipe none
>(II) intel(0):   Output VGA-1 is connected to pipe A
>(II) intel(0): [drm] dma control initialized, using IRQ 16
>(II) intel(0): RandR 1.2 enabled, ignore the following RandR disabled message.
>(**) Option "dpms"
>(**) intel(0): DPMS enabled
>(II) intel(0): Set up textured video
>(II) intel(0): Set up overlay video
>(II) intel(0): direct rendering: Enabled
>(WW) intel(0): Option "PreferredMode" is not used
>(--) RandR disabled
>(II) Initializing built-in extension MIT-SHM
>(II) Initializing built-in extension XInputExtension
>(II) Initializing built-in extension XTEST
>(II) Initializing built-in extension XKEYBOARD
>(II) Initializing built-in extension XC-APPGROUP
>(II) Initializing built-in extension XAccessControlExtension
>(II) Initializing built-in extension SECURITY
>(II) Initializing built-in extension XINERAMA
>(II) Initializing built-in extension XFIXES
>(II) Initializing built-in extension XFree86-Bigfont
>(II) Initializing built-in extension RENDER
>(II) Initializing built-in extension RANDR
>(II) Initializing built-in extension COMPOSITE
>(II) Initializing built-in extension DAMAGE
>(II) Initializing built-in extension XEVIE
>drmOpenDevice: node name is /dev/dri/card0
>drmOpenDevice: open result is 10, (OK)
>drmOpenByBusid: Searching for BusID pci:0000:00:02.0
>drmOpenDevice: node name is /dev/dri/card0
>drmOpenDevice: open result is 10, (OK)
>drmOpenByBusid: drmOpenMinor returns 10
>drmOpenByBusid: drmGetBusid reports pci:0000:00:02.0
>(WW) AIGLX: 3D driver claims to not support visual 0x23
>(WW) AIGLX: 3D driver claims to not support visual 0x24
>(WW) AIGLX: 3D driver claims to not support visual 0x25
>(WW) AIGLX: 3D driver claims to not support visual 0x26
>(WW) AIGLX: 3D driver claims to not support visual 0x27
>(WW) AIGLX: 3D driver claims to not support visual 0x28
>(WW) AIGLX: 3D driver claims to not support visual 0x29
>(WW) AIGLX: 3D driver claims to not support visual 0x2a
>(WW) AIGLX: 3D driver claims to not support visual 0x2b
>(WW) AIGLX: 3D driver claims to not support visual 0x2c
>(WW) AIGLX: 3D driver claims to not support visual 0x2d
>(WW) AIGLX: 3D driver claims to not support visual 0x2e
>(WW) AIGLX: 3D driver claims to not support visual 0x2f
>(WW) AIGLX: 3D driver claims to not support visual 0x30
>(WW) AIGLX: 3D driver claims to not support visual 0x31
>(WW) AIGLX: 3D driver claims to not support visual 0x32
>(II) AIGLX: Loaded and initialized /usr/lib/dri/i915_dri.so
>(II) GLX: Initialized DRI GL provider for screen 0
>(II) intel(0): Setting screen physical size to 270 x 203
>(**) Option "CoreKeyboard"
>(**) Generic Keyboard: always reports core events
>(**) Option "Protocol" "standard"
>(**) Generic Keyboard: Protocol: standard
>(**) Option "AutoRepeat" "500 30"
>(**) Option "XkbRules" "xorg"
>(**) Generic Keyboard: XkbRules: "xorg"
>(**) Option "XkbModel" "pc101"
>(**) Generic Keyboard: XkbModel: "pc101"
>(**) Option "XkbLayout" "us"
>(**) Generic Keyboard: XkbLayout: "us"
>(**) Option "CustomKeycodes" "off"
>(**) Generic Keyboard: CustomKeycodes disabled
>(**) Option "Protocol" "ExplorerPS/2"
>(**) Configured Mouse: Device: "/dev/input/mice"
>(**) Configured Mouse: Protocol: "ExplorerPS/2"
>(**) Option "CorePointer"
>(**) Configured Mouse: always reports core events
>(**) Option "Device" "/dev/input/mice"
>(**) Option "Buttons" "3"
>(**) Option "Emulate3Buttons" "off"
>(**) Option "ZAxisMapping" "8 9"
>(**) Configured Mouse: ZAxisMapping: buttons 8 and 9
>(**) Configured Mouse: Buttons: 13
>(**) Configured Mouse: Sensitivity: 1
>(II) evaluating device (Configured Mouse)
>(II) XINPUT: Adding extended input device "Configured Mouse" (type: MOUSE)
>(II) evaluating device (Generic Keyboard)
>(II) XINPUT: Adding extended input device "Generic Keyboard" (type: KEYBOARD)
>(II) Configured Mouse: ps2EnableDataReporting: succeeded
>(II) intel(0): SDVO: W: 03                         (SDVO_CMD_GET_TRAINED_INPUTS)
>(II) intel(0): SDVO: R: 01                      (Success)
>(II) intel(0): SDVO: W: 05 02 00                   (SDVO_CMD_SET_ACTIVE_OUTPUTS)
>(II) intel(0): SDVO: R:                         (Success)
>(II) intel(0): SDVO: W: 03                         (SDVO_CMD_GET_TRAINED_INPUTS)
>(II) intel(0): SDVO: R: 01                      (Success)
>(II) intel(0): SDVO: W: 05 02 00                   (SDVO_CMD_SET_ACTIVE_OUTPUTS)
>(II) intel(0): SDVO: R:                         (Success)
>(II) AIGLX: Suspending AIGLX clients for VT switch
>(II) intel(0): SDVO: W: 05 00 00                   (SDVO_CMD_SET_ACTIVE_OUTPUTS)
>(II) intel(0): SDVO: R:                         (Success)
>(II) intel(0): SDVO: W: 05 00 00                   (SDVO_CMD_SET_ACTIVE_OUTPUTS)
>(II) intel(0): SDVO: R:                         (Success)
>(II) intel(0): SDVO: W: 11 02 00                   (SDVO_CMD_SET_TARGET_OUTPUT)
>(II) intel(0): SDVO: R:                         (Success)
>(II) intel(0): SDVO: W: 16 10 0B D0 B4 20 90 31 10 (SDVO_CMD_SET_OUTPUT_TIMINGS_PART1)
>(II) intel(0): SDVO: R:                         (Not supported)
>(II) intel(0): SDVO: W: 10 00                      (SDVO_CMD_SET_TARGET_INPUT)
>(II) intel(0): SDVO: R:                         (Success)
>(II) intel(0): SDVO: W: 14 10 0B D0 B4 20 90 31 10 (SDVO_CMD_SET_INPUT_TIMINGS_PART1)
>(II) intel(0): SDVO: R:                         (Success)
>(II) intel(0): SDVO: W: 15 2D 6C C2 00 1C 00 00 00 (SDVO_CMD_SET_INPUT_TIMINGS_PART2)
>(II) intel(0): SDVO: R:                         (Success)
>(II) intel(0): SDVO: W: 21 08                      (SDVO_CMD_SET_CLOCK_RATE_MULT)
>(II) intel(0): SDVO: R:                         (Success)
>(II) intel(0): SDVO: W: 03                         (SDVO_CMD_GET_TRAINED_INPUTS)
>(II) intel(0): SDVO: R: 01                      (Success)
>(II) intel(0): SDVO: W: 05 02 00                   (SDVO_CMD_SET_ACTIVE_OUTPUTS)
>(II) intel(0): SDVO: R:                         (Success)
>(II) intel(0): Comparing regs from server start up to After LeaveVT
>(WW) intel(0): Register 0x70024 (PIPEASTAT) changed from 0x00020203 to 0x80020203
>(WW) intel(0): PIPEASTAT before: status: VBLANK_INT_ENABLE VSYNC_INT_STATUS VBLANK_INT_STATUS OREG_UPDATE_STATUS
>(WW) intel(0): PIPEASTAT after: status: FIFO_UNDERRUN VBLANK_INT_ENABLE VSYNC_INT_STATUS VBLANK_INT_STATUS OREG_UPDATE_STATUS
>(II) intel(0): DumpRegsBegin
>(II) intel(0):    VCLK_DIVISOR_VGA0: 0x00031108 (n = 3, m1 = 17, m2 = 8)
>(II) intel(0):    VCLK_DIVISOR_VGA1: 0x00031406 (n = 3, m1 = 20, m2 = 6)
>(II) intel(0):        VCLK_POST_DIV: 0x00020002 (vga0 p1 = 4, p2 = 2, vga1 p1 = 2, p2 = 2)
>(II) intel(0):            DPLL_TEST: 0x00010001 ()
>(II) intel(0):         CACHE_MODE_0: 0x00006820
>(II) intel(0):              D_STATE: 0x00000000
>(II) intel(0):        DSPCLK_GATE_D: 0x00000000 (clock gates disabled:)
>(II) intel(0):       RENCLK_GATE_D1: 0x00000000
>(II) intel(0):       RENCLK_GATE_D2: 0x00000000
>(II) intel(0):                SDVOB: 0x80300084 (enabled, pipe A, stall disabled, detected)
>(II) intel(0):                SDVOC: 0x00300000 (disabled, pipe A, stall disabled, not detected)
>(II) intel(0):              SDVOUDI: 0x00000000
>(II) intel(0):               DSPARB: 0x00001d9c
>(II) intel(0):               DSPFW1: 0x00000000
>(II) intel(0):               DSPFW2: 0x00000000
>(II) intel(0):               DSPFW3: 0x00000000
>(II) intel(0):                 ADPA: 0x00008c18 (disabled, pipe A, +hsync, +vsync)
>(II) intel(0):                 LVDS: 0x00000000 (disabled, pipe A, 18 bit, 1 channel)
>(II) intel(0):                 DVOA: 0x00000000 (disabled, pipe A, no stall, -hsync, -vsync)
>(II) intel(0):                 DVOB: 0x80300084 (enabled, pipe A, no stall, -hsync, -vsync)
>(II) intel(0):                 DVOC: 0x00300000 (disabled, pipe A, no stall, -hsync, -vsync)
>(II) intel(0):          DVOA_SRCDIM: 0x00000000
>(II) intel(0):          DVOB_SRCDIM: 0x00000000
>(II) intel(0):          DVOC_SRCDIM: 0x00000000
>(II) intel(0):           PP_CONTROL: 0x00000000 (power target: off)
>(II) intel(0):            PP_STATUS: 0x00000000 (off, not ready, sequencing idle)
>(II) intel(0):         PFIT_CONTROL: 0x00000000
>(II) intel(0):      PFIT_PGM_RATIOS: 0x00000000
>(II) intel(0):      PORT_HOTPLUG_EN: 0x00000020
>(II) intel(0):    PORT_HOTPLUG_STAT: 0x00000000
>(II) intel(0):             DSPACNTR: 0x48000000 (disabled, pipe A)
>(II) intel(0):           DSPASTRIDE: 0x00000280 (640 bytes)
>(II) intel(0):              DSPAPOS: 0x00000000 (0, 0)
>(II) intel(0):             DSPASIZE: 0x018f02cf (720, 400)
>(II) intel(0):             DSPABASE: 0x00000000
>(II) intel(0):             DSPASURF: 0x00000000
>(II) intel(0):          DSPATILEOFF: 0x00000000
>(II) intel(0):            PIPEACONF: 0x80000000 (enabled, single-wide)
>(II) intel(0):             PIPEASRC: 0x02cf018f (720, 400)
>(II) intel(0):            PIPEASTAT: 0x80020203 (status: FIFO_UNDERRUN VBLANK_INT_ENABLE VSYNC_INT_STATUS VBLANK_INT_STATUS OREG_UPDATE_STATUS)
>(II) intel(0):         FBC_CFB_BASE: 0xffffffff
>(II) intel(0):          FBC_LL_BASE: 0xffffffff
>(II) intel(0):          FBC_CONTROL: 0xffffffff
>(II) intel(0):          FBC_COMMAND: 0xffffffff
>(II) intel(0):           FBC_STATUS: 0xffffffff
>(II) intel(0):         FBC_CONTROL2: 0xffffffff
>(II) intel(0):        FBC_FENCE_OFF: 0xffffffff
>(II) intel(0):          FBC_MOD_NUM: 0xffffffff
>(II) intel(0):                 FPA0: 0x00031406 (n = 3, m1 = 20, m2 = 6)
>(II) intel(0):                 FPA1: 0x00031108 (n = 3, m1 = 17, m2 = 8)
>(II) intel(0):               DPLL_A: 0xc4020033 (enabled, dvo, VGA, default clock, DAC/serial mode, p1 = 2, p2 = 10, SDVO mult 4)
>(II) intel(0):            DPLL_A_MD: 0x00000000
>(II) intel(0):             HTOTAL_A: 0x038302cf (720 active, 900 total)
>(II) intel(0):             HBLANK_A: 0x038302cf (720 start, 900 end)
>(II) intel(0):              HSYNC_A: 0x036802fc (765 start, 873 end)
>(II) intel(0):             VTOTAL_A: 0x01c0018f (400 active, 449 total)
>(II) intel(0):             VBLANK_A: 0x01c0018f (400 start, 449 end)
>(II) intel(0):              VSYNC_A: 0x019d019b (412 start, 414 end)
>(II) intel(0):            BCLRPAT_A: 0x00000000
>(II) intel(0):         VSYNCSHIFT_A: 0x00000000
>(II) intel(0):             DSPBCNTR: 0x01000000 (disabled, pipe B)
>(II) intel(0):           DSPBSTRIDE: 0x00000000 (0 bytes)
>(II) intel(0):              DSPBPOS: 0x00000000 (0, 0)
>(II) intel(0):             DSPBSIZE: 0x00000000 (1, 1)
>(II) intel(0):             DSPBBASE: 0x00000000
>(II) intel(0):             DSPBSURF: 0x00000000
>(II) intel(0):          DSPBTILEOFF: 0x00000000
>(II) intel(0):            PIPEBCONF: 0x00000000 (disabled, single-wide)
>(II) intel(0):             PIPEBSRC: 0x027f01df (640, 480)
>(II) intel(0):            PIPEBSTAT: 0x00020000 (status: VBLANK_INT_ENABLE)
>(II) intel(0):                 FPB0: 0x00031108 (n = 3, m1 = 17, m2 = 8)
>(II) intel(0):                 FPB1: 0x00031108 (n = 3, m1 = 17, m2 = 8)
>(II) intel(0):               DPLL_B: 0x04800003 (disabled, non-dvo, VGA, default clock, DAC/serial mode, p1 = 8, p2 = 10, SDVO mult 1)
>(II) intel(0):            DPLL_B_MD: 0x00000000
>(II) intel(0):             HTOTAL_B: 0x031f027f (640 active, 800 total)
>(II) intel(0):             HBLANK_B: 0x03170287 (648 start, 792 end)
>(II) intel(0):              HSYNC_B: 0x02ef028f (656 start, 752 end)
>(II) intel(0):             VTOTAL_B: 0x020c01df (480 active, 525 total)
>(II) intel(0):             VBLANK_B: 0x020401e7 (488 start, 517 end)
>(II) intel(0):              VSYNC_B: 0x01eb01e9 (490 start, 492 end)
>(II) intel(0):            BCLRPAT_B: 0x00000000
>(II) intel(0):         VSYNCSHIFT_B: 0x00000000
>(II) intel(0):    VCLK_DIVISOR_VGA0: 0x00031108
>(II) intel(0):    VCLK_DIVISOR_VGA1: 0x00031406
>(II) intel(0):        VCLK_POST_DIV: 0x00020002
>(II) intel(0):             VGACNTRL: 0x0020008e (enabled)
>(II) intel(0):               TV_CTL: 0x00000000
>(II) intel(0):               TV_DAC: 0x00000000
>(II) intel(0):             TV_CSC_Y: 0x00000000
>(II) intel(0):            TV_CSC_Y2: 0x00000000
>(II) intel(0):             TV_CSC_U: 0x00000000
>(II) intel(0):            TV_CSC_U2: 0x00000000
>(II) intel(0):             TV_CSC_V: 0x00000000
>(II) intel(0):            TV_CSC_V2: 0x00000000
>(II) intel(0):         TV_CLR_KNOBS: 0x00000000
>(II) intel(0):         TV_CLR_LEVEL: 0x00000000
>(II) intel(0):           TV_H_CTL_1: 0x00000000
>(II) intel(0):           TV_H_CTL_2: 0x00000000
>(II) intel(0):           TV_H_CTL_3: 0x00000000
>(II) intel(0):           TV_V_CTL_1: 0x00000000
>(II) intel(0):           TV_V_CTL_2: 0x00000000
>(II) intel(0):           TV_V_CTL_3: 0x00000000
>(II) intel(0):           TV_V_CTL_4: 0x00000000
>(II) intel(0):           TV_V_CTL_5: 0x00000000
>(II) intel(0):           TV_V_CTL_6: 0x00000000
>(II) intel(0):           TV_V_CTL_7: 0x00000000
>(II) intel(0):          TV_SC_CTL_1: 0x00000000
>(II) intel(0):          TV_SC_CTL_2: 0x00000000
>(II) intel(0):          TV_SC_CTL_3: 0x00000000
>(II) intel(0):           TV_WIN_POS: 0x00000000
>(II) intel(0):          TV_WIN_SIZE: 0x00000000
>(II) intel(0):      TV_FILTER_CTL_1: 0x00000000
>(II) intel(0):      TV_FILTER_CTL_2: 0x00000000
>(II) intel(0):      TV_FILTER_CTL_3: 0x00000000
>(II) intel(0):        TV_CC_CONTROL: 0x00000000
>(II) intel(0):           TV_CC_DATA: 0x00000000
>(II) intel(0):          TV_H_LUMA_0: 0x00000000
>(II) intel(0):         TV_H_LUMA_59: 0x00000000
>(II) intel(0):        TV_H_CHROMA_0: 0x00000000
>(II) intel(0):       TV_H_CHROMA_59: 0x00000000
>(II) intel(0):              MI_MODE: 0x00000200
>(II) intel(0):         MI_ARB_STATE: 0x00000040
>(II) intel(0):       MI_RDRET_STATE: 0x00000000
>(II) intel(0):              ECOSKPD: 0x00000307
>(II) intel(0):                 SR00: 0x03
>(II) intel(0):                 SR01: 0x00
>(II) intel(0):                 SR02: 0x03
>(II) intel(0):                 SR03: 0x00
>(II) intel(0):                 SR04: 0x02
>(II) intel(0):                 SR05: 0x00
>(II) intel(0):                 SR06: 0x00
>(II) intel(0):                 SR07: 0x00
>(II) intel(0):                  MSR: 0x67
>(II) intel(0):                  ARX: 0x30
>(II) intel(0):                 AR00: 0x00
>(II) intel(0):                 AR01: 0x01
>(II) intel(0):                 AR02: 0x02
>(II) intel(0):                 AR03: 0x03
>(II) intel(0):                 AR04: 0x04
>(II) intel(0):                 AR05: 0x05
>(II) intel(0):                 AR06: 0x06
>(II) intel(0):                 AR07: 0x07
>(II) intel(0):                 AR08: 0x08
>(II) intel(0):                 AR09: 0x09
>(II) intel(0):                 AR0a: 0x0a
>(II) intel(0):                 AR0b: 0x0b
>(II) intel(0):                 AR0c: 0x0c
>(II) intel(0):                 AR0d: 0x0d
>(II) intel(0):                 AR0e: 0x0e
>(II) intel(0):                 AR0f: 0x0f
>(II) intel(0):                 AR10: 0x0c
>(II) intel(0):                 AR11: 0x00
>(II) intel(0):                 AR12: 0x0f
>(II) intel(0):                 AR13: 0x08
>(II) intel(0):                 AR14: 0x00
>(II) intel(0):                 CR00: 0x5f
>(II) intel(0):                 CR01: 0x4f
>(II) intel(0):                 CR02: 0x50
>(II) intel(0):                 CR03: 0x82
>(II) intel(0):                 CR04: 0x55
>(II) intel(0):                 CR05: 0x81
>(II) intel(0):                 CR06: 0xbf
>(II) intel(0):                 CR07: 0x1f
>(II) intel(0):                 CR08: 0x00
>(II) intel(0):                 CR09: 0x4f
>(II) intel(0):                 CR0a: 0x0d
>(II) intel(0):                 CR0b: 0x0e
>(II) intel(0):                 CR0c: 0x00
>(II) intel(0):                 CR0d: 0x00
>(II) intel(0):                 CR0e: 0x00
>(II) intel(0):                 CR0f: 0x00
>(II) intel(0):                 CR10: 0x9c
>(II) intel(0):                 CR11: 0x8e
>(II) intel(0):                 CR12: 0x8f
>(II) intel(0):                 CR13: 0x28
>(II) intel(0):                 CR14: 0x1f
>(II) intel(0):                 CR15: 0x96
>(II) intel(0):                 CR16: 0xb9
>(II) intel(0):                 CR17: 0xa3
>(II) intel(0):                 CR18: 0xff
>(II) intel(0):                 CR19: 0x00
>(II) intel(0):                 CR1a: 0x00
>(II) intel(0):                 CR1b: 0x00
>(II) intel(0):                 CR1c: 0x00
>(II) intel(0):                 CR1d: 0x00
>(II) intel(0):                 CR1e: 0x00
>(II) intel(0):                 CR1f: 0x00
>(II) intel(0):                 CR20: 0x00
>(II) intel(0):                 CR21: 0x00
>(II) intel(0):                 CR22: 0x00
>(II) intel(0):                 CR23: 0x00
>(II) intel(0):                 CR24: 0x00
>(II) intel(0): pipe A dot 113280 n 3 m1 20 m2 6 p1 2 p2 10
>(II) intel(0): pipe B dot 25200 n 3 m1 17 m2 8 p1 8 p2 10
>(II) intel(0): DumpRegsEnd
>(II) intel(0): xf86UnbindGARTMemory: unbind key 0
>(II) intel(0): xf86UnbindGARTMemory: unbind key 1
>(II) intel(0): xf86UnbindGARTMemory: unbind key 2
>(II) intel(0): xf86UnbindGARTMemory: unbind key 3
>(II) intel(0): xf86UnbindGARTMemory: unbind key 4
>(II) Open ACPI successful (/var/run/acpid.socket)
>(II) AIGLX: Resuming AIGLX clients after VT switch
>(II) intel(0): xf86BindGARTMemory: bind key 0 at 0x00800000 (pgoffset 2048)
>(II) intel(0): xf86BindGARTMemory: bind key 1 at 0x01000000 (pgoffset 4096)
>(II) intel(0): xf86BindGARTMemory: bind key 2 at 0x02800000 (pgoffset 10240)
>(II) intel(0): xf86BindGARTMemory: bind key 3 at 0x03000000 (pgoffset 12288)
>(II) intel(0): xf86BindGARTMemory: bind key 4 at 0x03800000 (pgoffset 14336)
>(II) intel(0): Fixed memory allocation layout:
>(II) intel(0): 0x00000000-0x0001ffff: ring buffer (128 kB)
>(II) intel(0): 0x00020000-0x00029fff: HW cursors (40 kB)
>(II) intel(0): 0x0002a000-0x00031fff: logical 3D context (32 kB)
>(II) intel(0): 0x00032000-0x00032fff: overlay registers (4 kB)
>(II) intel(0): 0x00033000-0x00033fff: HW status (4 kB)
>(II) intel(0): 0x006ff000:            end of stolen memory
>(II) intel(0): 0x00800000-0x00ffffff: front buffer (6720 kB) X tiled
>(II) intel(0): 0x01000000-0x023affff: exa offscreen (20160 kB)
>(II) intel(0): 0x02800000-0x02ffffff: back buffer (6720 kB) X tiled
>(II) intel(0): 0x03000000-0x037fffff: depth buffer (6720 kB) X tiled
>(II) intel(0): 0x03800000-0x057fffff: classic textures (32768 kB)
>(II) intel(0): 0x10000000:            end of aperture
>(II) intel(0): SDVO: W: 05 00 00                   (SDVO_CMD_SET_ACTIVE_OUTPUTS)
>(II) intel(0): SDVO: R:                         (Success)
>(II) intel(0): SDVO: W: 05 00 00                   (SDVO_CMD_SET_ACTIVE_OUTPUTS)
>(II) intel(0): SDVO: R:                         (Success)
>(II) intel(0): Mode for pipe A:
>(II) intel(0): Modeline "1024x768_85.00"x85.0   94.39  1024 1088 1200 1376  768 769 772 807 -hsync +vsync (68.6 kHz)
>(II) intel(0): Adjusted mode for pipe A:
>(II) intel(0): Modeline "1024x768_85.00"x85.0  188.78  1024 1088 1200 1376  768 769 772 807 -hsync +vsync (137.2 kHz)
>chosen: dotclock 188800 vco 1888000 ((m 118, m1 20, m2 6), n 4, (p 10, p1 1, p2 10))
>(II) intel(0): SDVO: W: 11 02 00                   (SDVO_CMD_SET_TARGET_OUTPUT)
>(II) intel(0): SDVO: R:                         (Success)
>(II) intel(0): SDVO: W: 16 DF 24 00 60 41 00 27 30 (SDVO_CMD_SET_OUTPUT_TIMINGS_PART1)
>(II) intel(0): SDVO: R:                         (Not supported)
>(II) intel(0): SDVO: W: 10 00                      (SDVO_CMD_SET_TARGET_INPUT)
>(II) intel(0): SDVO: R:                         (Success)
>(II) intel(0): SDVO: W: 14 DF 24 00 60 41 00 27 30 (SDVO_CMD_SET_INPUT_TIMINGS_PART1)
>(II) intel(0): SDVO: R:                         (Success)
>(II) intel(0): SDVO: W: 15 40 70 13 00 1C 00 00 00 (SDVO_CMD_SET_INPUT_TIMINGS_PART2)
>(II) intel(0): SDVO: R:                         (Success)
>(II) intel(0): SDVO: W: 21 02                      (SDVO_CMD_SET_CLOCK_RATE_MULT)
>(II) intel(0): SDVO: R:                         (Success)
>(II) intel(0): SDVO: W: 03                         (SDVO_CMD_GET_TRAINED_INPUTS)
>(II) intel(0): SDVO: R: 01                      (Success)
>(II) intel(0): SDVO: W: 05 02 00                   (SDVO_CMD_SET_ACTIVE_OUTPUTS)
>(II) intel(0): SDVO: R:                         (Success)
>(II) intel(0): Hardware state at EnterVT:
>(II) intel(0): DumpRegsBegin
>(II) intel(0):    VCLK_DIVISOR_VGA0: 0x00031108 (n = 3, m1 = 17, m2 = 8)
>(II) intel(0):    VCLK_DIVISOR_VGA1: 0x00031406 (n = 3, m1 = 20, m2 = 6)
>(II) intel(0):        VCLK_POST_DIV: 0x00020002 (vga0 p1 = 4, p2 = 2, vga1 p1 = 2, p2 = 2)
>(II) intel(0):            DPLL_TEST: 0x00010001 ()
>(II) intel(0):         CACHE_MODE_0: 0x00006820
>(II) intel(0):              D_STATE: 0x00000000
>(II) intel(0):        DSPCLK_GATE_D: 0x00000000 (clock gates disabled:)
>(II) intel(0):       RENCLK_GATE_D1: 0x00000000
>(II) intel(0):       RENCLK_GATE_D2: 0x00000000
>(II) intel(0):                SDVOB: 0x80480084 (enabled, pipe A, stall disabled, detected)
>(II) intel(0):                SDVOC: 0x00300000 (disabled, pipe A, stall disabled, not detected)
>(II) intel(0):              SDVOUDI: 0x00000000
>(II) intel(0):               DSPARB: 0x00001d9c
>(II) intel(0):               DSPFW1: 0x00000000
>(II) intel(0):               DSPFW2: 0x00000000
>(II) intel(0):               DSPFW3: 0x00000000
>(II) intel(0):                 ADPA: 0x00008c18 (disabled, pipe A, +hsync, +vsync)
>(II) intel(0):                 LVDS: 0x00000000 (disabled, pipe A, 18 bit, 1 channel)
>(II) intel(0):                 DVOA: 0x00000000 (disabled, pipe A, no stall, -hsync, -vsync)
>(II) intel(0):                 DVOB: 0x80480084 (enabled, pipe A, no stall, -hsync, -vsync)
>(II) intel(0):                 DVOC: 0x00300000 (disabled, pipe A, no stall, -hsync, -vsync)
>(II) intel(0):          DVOA_SRCDIM: 0x00000000
>(II) intel(0):          DVOB_SRCDIM: 0x00000000
>(II) intel(0):          DVOC_SRCDIM: 0x00000000
>(II) intel(0):           PP_CONTROL: 0x00000000 (power target: off)
>(II) intel(0):            PP_STATUS: 0x00000000 (off, not ready, sequencing idle)
>(II) intel(0):         PFIT_CONTROL: 0x00000000
>(II) intel(0):      PFIT_PGM_RATIOS: 0x00000000
>(II) intel(0):      PORT_HOTPLUG_EN: 0x00000020
>(II) intel(0):    PORT_HOTPLUG_STAT: 0x00000000
>(II) intel(0):             DSPACNTR: 0xd4000000 (enabled, pipe A)
>(II) intel(0):           DSPASTRIDE: 0x00001000 (4096 bytes)
>(II) intel(0):              DSPAPOS: 0x00000000 (0, 0)
>(II) intel(0):             DSPASIZE: 0x02ff03ff (1024, 768)
>(II) intel(0):             DSPABASE: 0x00800000
>(II) intel(0):             DSPASURF: 0x00000000
>(II) intel(0):          DSPATILEOFF: 0x00000000
>(II) intel(0):            PIPEACONF: 0x80000000 (enabled, single-wide)
>(II) intel(0):             PIPEASRC: 0x03ff02ff (1024, 768)
>(II) intel(0):            PIPEASTAT: 0x80020203 (status: FIFO_UNDERRUN VBLANK_INT_ENABLE VSYNC_INT_STATUS VBLANK_INT_STATUS OREG_UPDATE_STATUS)
>(II) intel(0):         FBC_CFB_BASE: 0xffffffff
>(II) intel(0):          FBC_LL_BASE: 0xffffffff
>(II) intel(0):          FBC_CONTROL: 0xffffffff
>(II) intel(0):          FBC_COMMAND: 0xffffffff
>(II) intel(0):           FBC_STATUS: 0xffffffff
>(II) intel(0):         FBC_CONTROL2: 0xffffffff
>(II) intel(0):        FBC_FENCE_OFF: 0xffffffff
>(II) intel(0):          FBC_MOD_NUM: 0xffffffff
>(II) intel(0):                 FPA0: 0x00041406 (n = 4, m1 = 20, m2 = 6)
>(II) intel(0):                 FPA1: 0x00031108 (n = 3, m1 = 17, m2 = 8)
>(II) intel(0):               DPLL_A: 0xd4010010 (enabled, dvo, default clock, DAC/serial mode, p1 = 1, p2 = 10, SDVO mult 2)
>(II) intel(0):            DPLL_A_MD: 0x00000000
>(II) intel(0):             HTOTAL_A: 0x055f03ff (1024 active, 1376 total)
>(II) intel(0):             HBLANK_A: 0x055f03ff (1024 start, 1376 end)
>(II) intel(0):              HSYNC_A: 0x04af043f (1088 start, 1200 end)
>(II) intel(0):             VTOTAL_A: 0x032602ff (768 active, 807 total)
>(II) intel(0):             VBLANK_A: 0x032602ff (768 start, 807 end)
>(II) intel(0):              VSYNC_A: 0x03030300 (769 start, 772 end)
>(II) intel(0):            BCLRPAT_A: 0x00000000
>(II) intel(0):         VSYNCSHIFT_A: 0x00000000
>(II) intel(0):             DSPBCNTR: 0x01000000 (disabled, pipe B)
>(II) intel(0):           DSPBSTRIDE: 0x00000000 (0 bytes)
>(II) intel(0):              DSPBPOS: 0x00000000 (0, 0)
>(II) intel(0):             DSPBSIZE: 0x00000000 (1, 1)
>(II) intel(0):             DSPBBASE: 0x00000000
>(II) intel(0):             DSPBSURF: 0x00000000
>(II) intel(0):          DSPBTILEOFF: 0x00000000
>(II) intel(0):            PIPEBCONF: 0x00000000 (disabled, single-wide)
>(II) intel(0):             PIPEBSRC: 0x027f01df (640, 480)
>(II) intel(0):            PIPEBSTAT: 0x00020000 (status: VBLANK_INT_ENABLE)
>(II) intel(0):                 FPB0: 0x00031108 (n = 3, m1 = 17, m2 = 8)
>(II) intel(0):                 FPB1: 0x00031108 (n = 3, m1 = 17, m2 = 8)
>(II) intel(0):               DPLL_B: 0x04800003 (disabled, non-dvo, VGA, default clock, DAC/serial mode, p1 = 8, p2 = 10, SDVO mult 1)
>(II) intel(0):            DPLL_B_MD: 0x00000000
>(II) intel(0):             HTOTAL_B: 0x031f027f (640 active, 800 total)
>(II) intel(0):             HBLANK_B: 0x03170287 (648 start, 792 end)
>(II) intel(0):              HSYNC_B: 0x02ef028f (656 start, 752 end)
>(II) intel(0):             VTOTAL_B: 0x020c01df (480 active, 525 total)
>(II) intel(0):             VBLANK_B: 0x020401e7 (488 start, 517 end)
>(II) intel(0):              VSYNC_B: 0x01eb01e9 (490 start, 492 end)
>(II) intel(0):            BCLRPAT_B: 0x00000000
>(II) intel(0):         VSYNCSHIFT_B: 0x00000000
>(II) intel(0):    VCLK_DIVISOR_VGA0: 0x00031108
>(II) intel(0):    VCLK_DIVISOR_VGA1: 0x00031406
>(II) intel(0):        VCLK_POST_DIV: 0x00020002
>(II) intel(0):             VGACNTRL: 0x80000000 (disabled)
>(II) intel(0):               TV_CTL: 0x00000000
>(II) intel(0):               TV_DAC: 0x00000000
>(II) intel(0):             TV_CSC_Y: 0x00000000
>(II) intel(0):            TV_CSC_Y2: 0x00000000
>(II) intel(0):             TV_CSC_U: 0x00000000
>(II) intel(0):            TV_CSC_U2: 0x00000000
>(II) intel(0):             TV_CSC_V: 0x00000000
>(II) intel(0):            TV_CSC_V2: 0x00000000
>(II) intel(0):         TV_CLR_KNOBS: 0x00000000
>(II) intel(0):         TV_CLR_LEVEL: 0x00000000
>(II) intel(0):           TV_H_CTL_1: 0x00000000
>(II) intel(0):           TV_H_CTL_2: 0x00000000
>(II) intel(0):           TV_H_CTL_3: 0x00000000
>(II) intel(0):           TV_V_CTL_1: 0x00000000
>(II) intel(0):           TV_V_CTL_2: 0x00000000
>(II) intel(0):           TV_V_CTL_3: 0x00000000
>(II) intel(0):           TV_V_CTL_4: 0x00000000
>(II) intel(0):           TV_V_CTL_5: 0x00000000
>(II) intel(0):           TV_V_CTL_6: 0x00000000
>(II) intel(0):           TV_V_CTL_7: 0x00000000
>(II) intel(0):          TV_SC_CTL_1: 0x00000000
>(II) intel(0):          TV_SC_CTL_2: 0x00000000
>(II) intel(0):          TV_SC_CTL_3: 0x00000000
>(II) intel(0):           TV_WIN_POS: 0x00000000
>(II) intel(0):          TV_WIN_SIZE: 0x00000000
>(II) intel(0):      TV_FILTER_CTL_1: 0x00000000
>(II) intel(0):      TV_FILTER_CTL_2: 0x00000000
>(II) intel(0):      TV_FILTER_CTL_3: 0x00000000
>(II) intel(0):        TV_CC_CONTROL: 0x00000000
>(II) intel(0):           TV_CC_DATA: 0x00000000
>(II) intel(0):          TV_H_LUMA_0: 0x00000000
>(II) intel(0):         TV_H_LUMA_59: 0x00000000
>(II) intel(0):        TV_H_CHROMA_0: 0x00000000
>(II) intel(0):       TV_H_CHROMA_59: 0x00000000
>(II) intel(0):              MI_MODE: 0x00000200
>(II) intel(0):         MI_ARB_STATE: 0x00000040
>(II) intel(0):       MI_RDRET_STATE: 0x00000000
>(II) intel(0):              ECOSKPD: 0x00000307
>(II) intel(0):                 SR00: 0x03
>(II) intel(0):                 SR01: 0x00
>(II) intel(0):                 SR02: 0x03
>(II) intel(0):                 SR03: 0x00
>(II) intel(0):                 SR04: 0x02
>(II) intel(0):                 SR05: 0x00
>(II) intel(0):                 SR06: 0x00
>(II) intel(0):                 SR07: 0x00
>(II) intel(0):                  MSR: 0x67
>(II) intel(0):                  ARX: 0x30
>(II) intel(0):                 AR00: 0x00
>(II) intel(0):                 AR01: 0x01
>(II) intel(0):                 AR02: 0x02
>(II) intel(0):                 AR03: 0x03
>(II) intel(0):                 AR04: 0x04
>(II) intel(0):                 AR05: 0x05
>(II) intel(0):                 AR06: 0x06
>(II) intel(0):                 AR07: 0x07
>(II) intel(0):                 AR08: 0x08
>(II) intel(0):                 AR09: 0x09
>(II) intel(0):                 AR0a: 0x0a
>(II) intel(0):                 AR0b: 0x0b
>(II) intel(0):                 AR0c: 0x0c
>(II) intel(0):                 AR0d: 0x0d
>(II) intel(0):                 AR0e: 0x0e
>(II) intel(0):                 AR0f: 0x0f
>(II) intel(0):                 AR10: 0x0c
>(II) intel(0):                 AR11: 0x00
>(II) intel(0):                 AR12: 0x0f
>(II) intel(0):                 AR13: 0x08
>(II) intel(0):                 AR14: 0x00
>(II) intel(0):                 CR00: 0x5f
>(II) intel(0):                 CR01: 0x4f
>(II) intel(0):                 CR02: 0x50
>(II) intel(0):                 CR03: 0x82
>(II) intel(0):                 CR04: 0x55
>(II) intel(0):                 CR05: 0x81
>(II) intel(0):                 CR06: 0xbf
>(II) intel(0):                 CR07: 0x1f
>(II) intel(0):                 CR08: 0x00
>(II) intel(0):                 CR09: 0x4f
>(II) intel(0):                 CR0a: 0x1f
>(II) intel(0):                 CR0b: 0x1e
>(II) intel(0):                 CR0c: 0x00
>(II) intel(0):                 CR0d: 0x00
>(II) intel(0):                 CR0e: 0x07
>(II) intel(0):                 CR0f: 0x8d
>(II) intel(0):                 CR10: 0x9c
>(II) intel(0):                 CR11: 0x8e
>(II) intel(0):                 CR12: 0x8f
>(II) intel(0):                 CR13: 0x28
>(II) intel(0):                 CR14: 0x1f
>(II) intel(0):                 CR15: 0x96
>(II) intel(0):                 CR16: 0xb9
>(II) intel(0):                 CR17: 0xa3
>(II) intel(0):                 CR18: 0xff
>(II) intel(0):                 CR19: 0x00
>(II) intel(0):                 CR1a: 0x00
>(II) intel(0):                 CR1b: 0x00
>(II) intel(0):                 CR1c: 0x00
>(II) intel(0):                 CR1d: 0x00
>(II) intel(0):                 CR1e: 0x00
>(II) intel(0):                 CR1f: 0x00
>(II) intel(0):                 CR20: 0x00
>(II) intel(0):                 CR21: 0x00
>(II) intel(0):                 CR22: 0x20
>(II) intel(0):                 CR23: 0x00
>(II) intel(0):                 CR24: 0x00
>(II) intel(0): pipe A dot 188800 n 4 m1 20 m2 6 p1 1 p2 10
>(II) intel(0): pipe B dot 25200 n 3 m1 17 m2 8 p1 8 p2 10
>(II) intel(0): DumpRegsEnd
>(II) intel(0): Output configuration:
>(II) intel(0):   Pipe A is on
>(II) intel(0):   Display plane A is now enabled and connected to pipe A.
>(II) intel(0):   Pipe B is off
>(II) intel(0):   Display plane B is now disabled and connected to pipe B.
>(II) intel(0):   Output VGA is connected to pipe none
>(II) intel(0):   Output VGA-1 is connected to pipe A
>(II) intel(0): [drm] mapped front buffer at 0xd0800000, handle = 0x2fff9000
>(II) intel(0): [drm] dma control initialized, using IRQ 16
>(II) intel(0): SDVO: W: 03                         (SDVO_CMD_GET_TRAINED_INPUTS)
>(II) intel(0): SDVO: R: 01                      (Success)
>(II) intel(0): SDVO: W: 05 02 00                   (SDVO_CMD_SET_ACTIVE_OUTPUTS)
>(II) intel(0): SDVO: R:                         (Success)
>(II) Configured Mouse: ps2EnableDataReporting: succeeded
>(II) intel(0): SDVO: W: 03                         (SDVO_CMD_GET_TRAINED_INPUTS)
>(II) intel(0): SDVO: R: 01                      (Success)
>(II) intel(0): SDVO: W: 05 02 00                   (SDVO_CMD_SET_ACTIVE_OUTPUTS)
>(II) intel(0): SDVO: R:                         (Success)

Actions: View

Attachments on bug 14430: 14221 | 14222 | 14269 | 14270 | 15524 | 15525 | 15526 | 15527

Use of freedesktop.org services, including Bugzilla, is subject to our Code of Conduct. How we collect and use information is described in our Privacy Policy.