Attachment 1643 Details for Bug 2241 – drm_radeon_cube_20050108.diff.txt

[patch] drm_radeon_cube_20050108.diff.txt

drm_radeon_cube_20050108.diff.txt (text/plain), 10.66 KB, created by Andreas Stenglein on 2005-01-08 16:46:57 UTC

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Creator: Andreas Stenglein

Created: 2005-01-08 16:46:57 UTC

Size: 10.66 KB

patch

obsolete

>Index: drm/shared/drm_pciids.txt
>===================================================================
>RCS file: /cvs/dri/drm/shared/drm_pciids.txt,v
>retrieving revision 1.10
>diff -u -r1.10 drm_pciids.txt
>--- drm/shared/drm_pciids.txt	6 Jan 2005 17:51:32 -0000	1.10
>+++ drm/shared/drm_pciids.txt	8 Jan 2005 20:33:41 -0000
>@@ -13,7 +13,7 @@
> 0x1002 0x4156 CHIP_RV350 "ATI FireGL AV T2"
> 0x1002 0x4237 CHIP_RS250|CHIP_IS_IGP "ATI Radeon RS250 IGP"
> 0x1002 0x4242 CHIP_R200 "ATI Radeon BB R200 AIW 8500DV"
>-0x1002 0x4242 CHIP_R200 "ATI Radeon BC R200"
>+0x1002 0x4243 CHIP_R200 "ATI Radeon BC R200"
> 0x1002 0x4336 CHIP_RS100|CHIP_IS_IGP|CHIP_IS_MOBILITY "ATI Radeon RS100 Mobility U1"
> 0x1002 0x4337 CHIP_RS200|CHIP_IS_IGP|CHIP_IS_MOBILITY "ATI Radeon RS200 Mobility IGP 340M"
> 0x1002 0x4437 CHIP_RS250|CHIP_IS_IGP|CHIP_IS_MOBILITY "ATI Radeon RS250 Mobility IGP"
>Index: drm/shared/radeon.h
>===================================================================
>RCS file: /cvs/dri/drm/shared/radeon.h,v
>retrieving revision 1.34
>diff -u -r1.34 radeon.h
>--- drm/shared/radeon.h	8 Dec 2004 16:43:00 -0000	1.34
>+++ drm/shared/radeon.h	8 Jan 2005 20:33:41 -0000
>@@ -42,10 +42,10 @@
> 
> #define DRIVER_NAME		"radeon"
> #define DRIVER_DESC		"ATI Radeon"
>-#define DRIVER_DATE		"20041207"
>+#define DRIVER_DATE		"20050108"
> 
> #define DRIVER_MAJOR		1
>-#define DRIVER_MINOR		13
>+#define DRIVER_MINOR		14
> #define DRIVER_PATCHLEVEL	0
> 
> /* Interface history:
>@@ -84,6 +84,7 @@
>  *       (No 3D support yet - just microcode loading).
>  * 1.13- Add packet R200_EMIT_TCL_POINT_SPRITE_CNTL for ARB_point_parameters
>  *     - Add hyperz support, add hyperz flags to clear ioctl.
>+ * 1.14- Add support for cube map registers on r100
>  */
> #define DRIVER_IOCTLS							     \
>  [DRM_IOCTL_NR(DRM_IOCTL_DMA)]               = { radeon_cp_buffers,  1, 0 }, \
>Index: drm/shared/radeon_drm.h
>===================================================================
>RCS file: /cvs/dri/drm/shared/radeon_drm.h,v
>retrieving revision 1.25
>diff -u -r1.25 radeon_drm.h
>--- drm/shared/radeon_drm.h	8 Dec 2004 16:43:00 -0000	1.25
>+++ drm/shared/radeon_drm.h	8 Jan 2005 20:33:42 -0000
>@@ -146,7 +146,13 @@
> #define RADEON_EMIT_PP_TEX_SIZE_2                   75
> #define R200_EMIT_RB3D_BLENDCOLOR                   76
> #define R200_EMIT_TCL_POINT_SPRITE_CNTL             77
>-#define RADEON_MAX_STATE_PACKETS                    78
>+#define RADEON_EMIT_PP_CUBIC_FACES_0                78
>+#define RADEON_EMIT_PP_CUBIC_OFFSETS_T0             79
>+#define RADEON_EMIT_PP_CUBIC_FACES_1                80
>+#define RADEON_EMIT_PP_CUBIC_OFFSETS_T1             81
>+#define RADEON_EMIT_PP_CUBIC_FACES_2                82
>+#define RADEON_EMIT_PP_CUBIC_OFFSETS_T2             83
>+#define RADEON_MAX_STATE_PACKETS                    84
> 
> 
> /* Commands understood by cmd_buffer ioctl.  More can be added but
>Index: drm/shared/radeon_drv.h
>===================================================================
>RCS file: /cvs/dri/drm/shared/radeon_drv.h,v
>retrieving revision 1.38
>diff -u -r1.38 radeon_drv.h
>--- drm/shared/radeon_drv.h	8 Dec 2004 16:43:00 -0000	1.38
>+++ drm/shared/radeon_drv.h	8 Jan 2005 20:33:43 -0000
>@@ -741,6 +741,12 @@
> #define RADEON_PP_TEX_SIZE_1                0x1d0c
> #define RADEON_PP_TEX_SIZE_2                0x1d14
> 
>+#define RADEON_PP_CUBIC_FACES_0             0x1d24
>+#define RADEON_PP_CUBIC_FACES_1             0x1d28
>+#define RADEON_PP_CUBIC_FACES_2             0x1d2c
>+#define RADEON_PP_CUBIC_OFFSET_T0_0         0x1dd0  /* bits [31:5] */
>+#define RADEON_PP_CUBIC_OFFSET_T1_0         0x1e00
>+#define RADEON_PP_CUBIC_OFFSET_T2_0         0x1e14
> 
> #define SE_VAP_CNTL__TCL_ENA_MASK                          0x00000001
> #define SE_VAP_CNTL__FORCE_W_TO_ONE_MASK                   0x00010000
>Index: drm/shared/radeon_state.c
>===================================================================
>RCS file: /cvs/dri/drm/shared/radeon_state.c,v
>retrieving revision 1.40
>diff -u -r1.40 radeon_state.c
>--- drm/shared/radeon_state.c	8 Dec 2004 16:43:00 -0000	1.40
>+++ drm/shared/radeon_state.c	8 Jan 2005 20:33:45 -0000
>@@ -145,6 +145,21 @@
> 		break;
> 	}
> 
>+	case RADEON_EMIT_PP_CUBIC_OFFSETS_T0:
>+	case RADEON_EMIT_PP_CUBIC_OFFSETS_T1:
>+	case RADEON_EMIT_PP_CUBIC_OFFSETS_T2: {
>+		int i;
>+		for ( i = 0; i < 5; i++ ) {
>+			if ( radeon_check_and_fixup_offset_user( dev_priv,
>+								 filp_priv,
>+								 &data[i] ) ) {
>+				DRM_ERROR( "Invalid R100 cubic texture offset\n" );
>+				return DRM_ERR( EINVAL );
>+			}
>+		}
>+		break;
>+	}
>+
> 	case RADEON_EMIT_RB3D_COLORPITCH:
> 	case RADEON_EMIT_RE_LINE_PATTERN:
> 	case RADEON_EMIT_SE_LINE_WIDTH:
>@@ -206,6 +221,9 @@
> 	case RADEON_EMIT_PP_TEX_SIZE_2:
> 	case R200_EMIT_RB3D_BLENDCOLOR:
> 	case R200_EMIT_TCL_POINT_SPRITE_CNTL:
>+	case RADEON_EMIT_PP_CUBIC_FACES_0:
>+	case RADEON_EMIT_PP_CUBIC_FACES_1:
>+	case RADEON_EMIT_PP_CUBIC_FACES_2:
> 		/* These packets don't contain memory offsets */
> 		break;
> 
>@@ -571,6 +589,12 @@
> 	{ RADEON_PP_TEX_SIZE_2, 2, "RADEON_PP_TEX_SIZE_2" },
> 	{ R200_RB3D_BLENDCOLOR, 3, "R200_RB3D_BLENDCOLOR" },
> 	{ R200_SE_TCL_POINT_SPRITE_CNTL, 1, "R200_SE_TCL_POINT_SPRITE_CNTL"},
>+	{ RADEON_PP_CUBIC_FACES_0, 1, "RADEON_PP_CUBIC_FACES_0" },
>+	{ RADEON_PP_CUBIC_OFFSET_T0_0, 5, "RADEON_PP_CUBIC_OFFSET_T0_0" },
>+	{ RADEON_PP_CUBIC_FACES_1, 1, "RADEON_PP_CUBIC_FACES_1" },
>+	{ RADEON_PP_CUBIC_OFFSET_T1_0, 5, "RADEON_PP_CUBIC_OFFSET_T1_0" },
>+	{ RADEON_PP_CUBIC_FACES_2, 1, "RADEON_PP_CUBIC_FACES_2" },
>+	{ RADEON_PP_CUBIC_OFFSET_T2_0, 5, "RADEON_PP_CUBIC_OFFSET_T2_0" },
> };
> 
> 
>Index: drm/shared-core/drm_pciids.txt
>===================================================================
>RCS file: /cvs/dri/drm/shared-core/drm_pciids.txt,v
>retrieving revision 1.12
>diff -u -r1.12 drm_pciids.txt
>--- drm/shared-core/drm_pciids.txt	6 Jan 2005 17:51:32 -0000	1.12
>+++ drm/shared-core/drm_pciids.txt	8 Jan 2005 20:33:46 -0000
>@@ -13,7 +13,7 @@
> 0x1002 0x4156 CHIP_RV350 "ATI FireGL AV T2"
> 0x1002 0x4237 CHIP_RS250|CHIP_IS_IGP "ATI Radeon RS250 IGP"
> 0x1002 0x4242 CHIP_R200 "ATI Radeon BB R200 AIW 8500DV"
>-0x1002 0x4242 CHIP_R200 "ATI Radeon BC R200"
>+0x1002 0x4243 CHIP_R200 "ATI Radeon BC R200"
> 0x1002 0x4336 CHIP_RS100|CHIP_IS_IGP|CHIP_IS_MOBILITY "ATI Radeon RS100 Mobility U1"
> 0x1002 0x4337 CHIP_RS200|CHIP_IS_IGP|CHIP_IS_MOBILITY "ATI Radeon RS200 Mobility IGP 340M"
> 0x1002 0x4437 CHIP_RS250|CHIP_IS_IGP|CHIP_IS_MOBILITY "ATI Radeon RS250 Mobility IGP"
>Index: drm/shared-core/radeon_drm.h
>===================================================================
>RCS file: /cvs/dri/drm/shared-core/radeon_drm.h,v
>retrieving revision 1.26
>diff -u -r1.26 radeon_drm.h
>--- drm/shared-core/radeon_drm.h	8 Dec 2004 16:43:00 -0000	1.26
>+++ drm/shared-core/radeon_drm.h	8 Jan 2005 20:33:46 -0000
>@@ -145,7 +145,13 @@
> #define RADEON_EMIT_PP_TEX_SIZE_2                   75
> #define R200_EMIT_RB3D_BLENDCOLOR                   76
> #define R200_EMIT_TCL_POINT_SPRITE_CNTL             77
>-#define RADEON_MAX_STATE_PACKETS                    78
>+#define RADEON_EMIT_PP_CUBIC_FACES_0                78
>+#define RADEON_EMIT_PP_CUBIC_OFFSETS_T0             79
>+#define RADEON_EMIT_PP_CUBIC_FACES_1                80
>+#define RADEON_EMIT_PP_CUBIC_OFFSETS_T1             81
>+#define RADEON_EMIT_PP_CUBIC_FACES_2                82
>+#define RADEON_EMIT_PP_CUBIC_OFFSETS_T2             83
>+#define RADEON_MAX_STATE_PACKETS                    84
> 
> /* Commands understood by cmd_buffer ioctl.  More can be added but
>  * obviously these can't be removed or changed:
>Index: drm/shared-core/radeon_drv.h
>===================================================================
>RCS file: /cvs/dri/drm/shared-core/radeon_drv.h,v
>retrieving revision 1.39
>diff -u -r1.39 radeon_drv.h
>--- drm/shared-core/radeon_drv.h	8 Dec 2004 16:43:00 -0000	1.39
>+++ drm/shared-core/radeon_drv.h	8 Jan 2005 20:33:47 -0000
>@@ -42,7 +42,7 @@
> 
> #define DRIVER_NAME		"radeon"
> #define DRIVER_DESC		"ATI Radeon"
>-#define DRIVER_DATE		"20041207"
>+#define DRIVER_DATE		"20050108"
> 
> /* Interface history:
>  *
>@@ -80,10 +80,11 @@
>  *       (No 3D support yet - just microcode loading).
>  * 1.13- Add packet R200_EMIT_TCL_POINT_SPRITE_CNTL for ARB_point_parameters
>  *     - Add hyperz support, add hyperz flags to clear ioctl.
>+ * 1.14- Add support for cube map registers on r100:
>  */
> 
> #define DRIVER_MAJOR		1
>-#define DRIVER_MINOR		13
>+#define DRIVER_MINOR		14
> #define DRIVER_PATCHLEVEL	0
> 
> enum radeon_family {
>@@ -797,6 +798,13 @@
> #define RADEON_PP_TEX_SIZE_1                0x1d0c
> #define RADEON_PP_TEX_SIZE_2                0x1d14
> 
>+#define RADEON_PP_CUBIC_FACES_0             0x1d24
>+#define RADEON_PP_CUBIC_FACES_1             0x1d28
>+#define RADEON_PP_CUBIC_FACES_2             0x1d2c
>+#define RADEON_PP_CUBIC_OFFSET_T0_0         0x1dd0	/* bits [31:5] */
>+#define RADEON_PP_CUBIC_OFFSET_T1_0         0x1e00
>+#define RADEON_PP_CUBIC_OFFSET_T2_0         0x1e14
>+
> #define SE_VAP_CNTL__TCL_ENA_MASK                          0x00000001
> #define SE_VAP_CNTL__FORCE_W_TO_ONE_MASK                   0x00010000
> #define SE_VAP_CNTL__VF_MAX_VTX_NUM__SHIFT                 0x00000012
>Index: drm/shared-core/radeon_state.c
>===================================================================
>RCS file: /cvs/dri/drm/shared-core/radeon_state.c,v
>retrieving revision 1.41
>diff -u -r1.41 radeon_state.c
>--- drm/shared-core/radeon_state.c	8 Dec 2004 16:43:00 -0000	1.41
>+++ drm/shared-core/radeon_state.c	8 Jan 2005 20:33:50 -0000
>@@ -211,6 +211,23 @@
> 			break;
> 		}
> 
>+	case RADEON_EMIT_PP_CUBIC_OFFSETS_T0:
>+	case RADEON_EMIT_PP_CUBIC_OFFSETS_T1:
>+	case RADEON_EMIT_PP_CUBIC_OFFSETS_T2:{
>+			int i;
>+			for (i = 0; i < 5; i++) {
>+				if (radeon_check_and_fixup_offset_user(dev_priv,
>+								       filp_priv,
>+								       &data
>+								       [i])) {
>+					DRM_ERROR
>+					    ("Invalid R100 cubic texture offset\n");
>+					return DRM_ERR(EINVAL);
>+				}
>+			}
>+		}
>+		break;
>+
> 	case RADEON_EMIT_RB3D_COLORPITCH:
> 	case RADEON_EMIT_RE_LINE_PATTERN:
> 	case RADEON_EMIT_SE_LINE_WIDTH:
>@@ -272,6 +289,9 @@
> 	case RADEON_EMIT_PP_TEX_SIZE_2:
> 	case R200_EMIT_RB3D_BLENDCOLOR:
> 	case R200_EMIT_TCL_POINT_SPRITE_CNTL:
>+	case RADEON_EMIT_PP_CUBIC_FACES_0:
>+	case RADEON_EMIT_PP_CUBIC_FACES_1:
>+	case RADEON_EMIT_PP_CUBIC_FACES_2:
> 		/* These packets don't contain memory offsets */
> 		break;
> 
>@@ -649,6 +669,13 @@
> 	RADEON_PP_TEX_SIZE_2, 2, "RADEON_PP_TEX_SIZE_2"}, {
> 	R200_RB3D_BLENDCOLOR, 3, "R200_RB3D_BLENDCOLOR"}, {
> 	R200_SE_TCL_POINT_SPRITE_CNTL, 1, "R200_SE_TCL_POINT_SPRITE_CNTL"},
>+	{
>+	RADEON_PP_CUBIC_FACES_0, 1, "RADEON_PP_CUBIC_FACES_0"}, {
>+	RADEON_PP_CUBIC_OFFSET_T0_0, 5, "RADEON_PP_CUBIC_OFFSET_T0_0"}, {
>+	RADEON_PP_CUBIC_FACES_1, 1, "RADEON_PP_CUBIC_FACES_1"}, {
>+	RADEON_PP_CUBIC_OFFSET_T1_0, 5, "RADEON_PP_CUBIC_OFFSET_T1_0"}, {
>+	RADEON_PP_CUBIC_FACES_2, 1, "RADEON_PP_CUBIC_FACES_2"}, {
>+	RADEON_PP_CUBIC_OFFSET_T2_0, 5, "RADEON_PP_CUBIC_OFFSET_T2_0"},
> };
> 
> /* ================================================================

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