Attachment 18004 Details for Bug 16833 – Log with the patch in attachment 18003 applied

Log with the patch in attachment 18003 applied

X.log.jesse-no-DSPARB (text/plain), 74.04 KB, created by Simon Farnsworth on 2008-07-30 08:51:49 UTC

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Creator: Simon Farnsworth

Created: 2008-07-30 08:51:49 UTC

Size: 74.04 KB

patch

obsolete

>
>X Window System Version 1.3.0
>Release Date: 19 April 2007
>X Protocol Version 11, Revision 0, Release 1.3
>Build Operating System: Fedora Core 7 Red Hat, Inc.
>Current Operating System: Linux localhost 2.6.24.3-50.fc8 #1 SMP Thu Mar 20 14:47:10 EDT 2008 i686
>Build Date: 18 March 2008
>Build ID: xorg-x11-server 1.3.0.0-91 
>	Before reporting problems, check http://wiki.x.org
>	to make sure that you have the latest version.
>Module Loader present
>Markers: (--) probed, (**) from config file, (==) default setting,
>	(++) from command line, (!!) notice, (II) informational,
>	(WW) warning, (EE) error, (NI) not implemented, (??) unknown.
>(++) Log file: "/data/data/logs/screen-server.log", Time: Wed Jul 30 16:46:59 2008
>(++) Using config file: "/etc/onelan/ntb/x.conf"
>(==) ServerLayout "ONELAN Configured"
>(**) |-->Screen "Screen0" (0)
>(**) |   |-->Monitor "Monitor-VGA"
>(**) |   |-->Device "Card0"
>(**) |-->Input Device "Mouse0"
>(**) |-->Input Device "Keyboard0"
>(WW) No FontPath specified.  Using compiled-in default.
>(==) FontPath set to:
>	catalogue:/etc/X11/fontpath.d,
>	built-ins
>(==) RgbPath set to "/usr/share/X11/rgb"
>(==) ModulePath set to "/usr/lib/xorg/modules"
>(II) Open ACPI successful (/var/run/acpid.socket)
>(II) Loader magic: 0x820c3e0
>(II) Module ABI versions:
>	X.Org ANSI C Emulation: 0.3
>	X.Org Video Driver: 1.2
>	X.Org XInput driver : 0.7
>	X.Org Server Extension : 0.3
>	X.Org Font Renderer : 0.5
>(II) Loader running on linux
>(II) LoadModule: "pcidata"
>(II) Loading /usr/lib/xorg/modules//libpcidata.so
>(II) Module pcidata: vendor="X.Org Foundation"
>	compiled for 1.3.0, module version = 1.0.0
>	ABI class: X.Org Video Driver, version 1.2
>(++) using VT number 7
>
>(II) PCI: PCI scan (all values are in hex)
>(II) PCI: 00:00:0: chip 8086,2a10 card 8086,2a10 rev 03 class 06,00,00 hdr 00
>(II) PCI: 00:02:0: chip 8086,2a12 card 8086,2a12 rev 03 class 03,00,00 hdr 80
>(II) PCI: 00:02:1: chip 8086,2a13 card 8086,2a12 rev 03 class 03,80,00 hdr 80
>(II) PCI: 00:1a:0: chip 8086,2834 card 8086,2834 rev 03 class 0c,03,00 hdr 80
>(II) PCI: 00:1a:1: chip 8086,2835 card 8086,2835 rev 03 class 0c,03,00 hdr 00
>(II) PCI: 00:1a:7: chip 8086,283a card 8086,283a rev 03 class 0c,03,20 hdr 00
>(II) PCI: 00:1b:0: chip 8086,284b card 8086,284b rev 03 class 04,03,00 hdr 00
>(II) PCI: 00:1c:0: chip 8086,283f card 0000,0000 rev 03 class 06,04,00 hdr 81
>(II) PCI: 00:1c:3: chip 8086,2845 card 0000,0000 rev 03 class 06,04,00 hdr 81
>(II) PCI: 00:1d:0: chip 8086,2830 card 8086,2830 rev 03 class 0c,03,00 hdr 80
>(II) PCI: 00:1d:1: chip 8086,2831 card 8086,2831 rev 03 class 0c,03,00 hdr 00
>(II) PCI: 00:1d:2: chip 8086,2832 card 8086,2832 rev 03 class 0c,03,00 hdr 00
>(II) PCI: 00:1d:7: chip 8086,2836 card 8086,2836 rev 03 class 0c,03,20 hdr 00
>(II) PCI: 00:1e:0: chip 8086,2448 card 0000,0000 rev f3 class 06,04,01 hdr 01
>(II) PCI: 00:1f:0: chip 8086,2815 card 8086,2815 rev 03 class 06,01,00 hdr 80
>(II) PCI: 00:1f:1: chip 8086,2850 card 8086,2850 rev 03 class 01,01,8a hdr 00
>(II) PCI: 00:1f:2: chip 8086,2828 card 8086,2828 rev 03 class 01,01,8f hdr 00
>(II) PCI: 00:1f:3: chip 8086,283e card 8086,283e rev 03 class 0c,05,00 hdr 00
>(II) PCI: 01:0f:0: chip 1131,7133 card 0070,6701 rev d1 class 04,80,00 hdr 00
>(II) PCI: 03:00:0: chip 10ec,8168 card 10ec,8168 rev 01 class 02,00,00 hdr 00
>(II) PCI: End of PCI scan
>(II) Intel Bridge workaround enabled
>(II) Host-to-PCI bridge:
>(II) Bus 0: bridge is at (0:0:0), (0,0,3), BCTRL: 0x0008 (VGA_EN is set)
>(II) Bus 0 I/O range:
>	[0] -1	0	0x00000000 - 0x0000ffff (0x10000) IX[B]
>(II) Bus 0 non-prefetchable memory range:
>	[0] -1	0	0x00000000 - 0xffffffff (0x0) MX[B]
>(II) Bus 0 prefetchable memory range:
>	[0] -1	0	0x00000000 - 0xffffffff (0x0) MX[B]
>(II) PCI-to-PCI bridge:
>(II) Bus 2: bridge is at (0:28:0), (0,2,2), BCTRL: 0x0002 (VGA_EN is cleared)
>(II) PCI-to-PCI bridge:
>(II) Bus 3: bridge is at (0:28:3), (0,3,3), BCTRL: 0x0002 (VGA_EN is cleared)
>(II) Bus 3 I/O range:
>	[0] -1	0	0x0000e000 - 0x0000efff (0x1000) IX[B]
>(II) Bus 3 non-prefetchable memory range:
>	[0] -1	0	0xfeb00000 - 0xfebfffff (0x100000) MX[B]
>(II) Bus 3 prefetchable memory range:
>	[0] -1	0	0x40000000 - 0x400fffff (0x100000) MX[B]
>(II) Subtractive PCI-to-PCI bridge:
>(II) Bus 1: bridge is at (0:30:0), (0,1,1), BCTRL: 0x0002 (VGA_EN is cleared)
>(II) Bus 1 non-prefetchable memory range:
>	[0] -1	0	0xfea00000 - 0xfeafffff (0x100000) MX[B]
>(II) PCI-to-ISA bridge:
>(II) Bus -1: bridge is at (0:31:0), (0,-1,-1), BCTRL: 0x0008 (VGA_EN is set)
>(--) PCI:*(0:2:0) Intel Corporation unknown chipset (0x2a12) rev 3, Mem @ 0xfe800000/20, 0xd0000000/28, I/O @ 0xc080/3
>(--) PCI: (0:2:1) Intel Corporation unknown chipset (0x2a13) rev 3, Mem @ 0xfe700000/20
>(II) Addressable bus resource ranges are
>	[0] -1	0	0x00000000 - 0xffffffff (0x0) MX[B]
>	[1] -1	0	0x00000000 - 0x0000ffff (0x10000) IX[B]
>(II) OS-reported resource ranges:
>	[0] -1	0	0x00100000 - 0x3fffffff (0x3ff00000) MX[B]E(B)
>	[1] -1	0	0x000f0000 - 0x000fffff (0x10000) MX[B]
>	[2] -1	0	0x000c0000 - 0x000effff (0x30000) MX[B]
>	[3] -1	0	0x00000000 - 0x0009ffff (0xa0000) MX[B]
>	[4] -1	0	0x0000ffff - 0x0000ffff (0x1) IX[B]
>	[5] -1	0	0x00000000 - 0x000000ff (0x100) IX[B]
>(II) Active PCI resource ranges:
>	[0] -1	0	0xfebff000 - 0xfebfffff (0x1000) MX[B]
>	[1] -1	0	0xfeaff800 - 0xfeafffff (0x800) MX[B]
>	[2] -1	0	0xfe9ffc00 - 0xfe9ffcff (0x100) MX[B]
>	[3] -1	0	0xfe9ff800 - 0xfe9ffbff (0x400) MX[B]
>	[4] -1	0	0xfe9f8000 - 0xfe9fbfff (0x4000) MX[B]
>	[5] -1	0	0xfe9ff400 - 0xfe9ff7ff (0x400) MX[B]
>	[6] -1	0	0xfe700000 - 0xfe7fffff (0x100000) MX[B](B)
>	[7] -1	0	0xd0000000 - 0xdfffffff (0x10000000) MX[B](B)
>	[8] -1	0	0xfe800000 - 0xfe8fffff (0x100000) MX[B](B)
>	[9] -1	0	0x0000e800 - 0x0000e8ff (0x100) IX[B]
>	[10] -1	0	0x00000400 - 0x0000041f (0x20) IX[B]
>	[11] -1	0	0x0000d080 - 0x0000d08f (0x10) IX[B]
>	[12] -1	0	0x0000d400 - 0x0000d40f (0x10) IX[B]
>	[13] -1	0	0x0000d480 - 0x0000d483 (0x4) IX[B]
>	[14] -1	0	0x0000d800 - 0x0000d807 (0x8) IX[B]
>	[15] -1	0	0x0000d880 - 0x0000d883 (0x4) IX[B]
>	[16] -1	0	0x0000dc00 - 0x0000dc07 (0x8) IX[B]
>	[17] -1	0	0x0000ffa0 - 0x0000ffaf (0x10) IX[B]
>	[18] -1	0	0x00000374 - 0x00000374 (0x1) IX[B]
>	[19] -1	0	0x00000170 - 0x00000177 (0x8) IX[B]
>	[20] -1	0	0x000001f0 - 0x000001f0 (0x1) IX[B]
>	[21] -1	0	0x000001f0 - 0x000001f7 (0x8) IX[B]
>	[22] -1	0	0x0000c800 - 0x0000c81f (0x20) IX[B]
>	[23] -1	0	0x0000c880 - 0x0000c89f (0x20) IX[B]
>	[24] -1	0	0x0000cc00 - 0x0000cc1f (0x20) IX[B]
>	[25] -1	0	0x0000c400 - 0x0000c41f (0x20) IX[B]
>	[26] -1	0	0x0000c480 - 0x0000c49f (0x20) IX[B]
>	[27] -1	0	0x0000c080 - 0x0000c087 (0x8) IX[B](B)
>(II) Active PCI resource ranges after removing overlaps:
>	[0] -1	0	0xfebff000 - 0xfebfffff (0x1000) MX[B]
>	[1] -1	0	0xfeaff800 - 0xfeafffff (0x800) MX[B]
>	[2] -1	0	0xfe9ffc00 - 0xfe9ffcff (0x100) MX[B]
>	[3] -1	0	0xfe9ff800 - 0xfe9ffbff (0x400) MX[B]
>	[4] -1	0	0xfe9f8000 - 0xfe9fbfff (0x4000) MX[B]
>	[5] -1	0	0xfe9ff400 - 0xfe9ff7ff (0x400) MX[B]
>	[6] -1	0	0xfe700000 - 0xfe7fffff (0x100000) MX[B](B)
>	[7] -1	0	0xd0000000 - 0xdfffffff (0x10000000) MX[B](B)
>	[8] -1	0	0xfe800000 - 0xfe8fffff (0x100000) MX[B](B)
>	[9] -1	0	0x0000e800 - 0x0000e8ff (0x100) IX[B]
>	[10] -1	0	0x00000400 - 0x0000041f (0x20) IX[B]
>	[11] -1	0	0x0000d080 - 0x0000d08f (0x10) IX[B]
>	[12] -1	0	0x0000d400 - 0x0000d40f (0x10) IX[B]
>	[13] -1	0	0x0000d480 - 0x0000d483 (0x4) IX[B]
>	[14] -1	0	0x0000d800 - 0x0000d807 (0x8) IX[B]
>	[15] -1	0	0x0000d880 - 0x0000d883 (0x4) IX[B]
>	[16] -1	0	0x0000dc00 - 0x0000dc07 (0x8) IX[B]
>	[17] -1	0	0x0000ffa0 - 0x0000ffaf (0x10) IX[B]
>	[18] -1	0	0x00000374 - 0x00000374 (0x1) IX[B]
>	[19] -1	0	0x00000170 - 0x00000177 (0x8) IX[B]
>	[20] -1	0	0x000001f0 - 0x000001f0 (0x1) IX[B]
>	[21] -1	0	0x000001f0 - 0x000001f7 (0x8) IX[B]
>	[22] -1	0	0x0000c800 - 0x0000c81f (0x20) IX[B]
>	[23] -1	0	0x0000c880 - 0x0000c89f (0x20) IX[B]
>	[24] -1	0	0x0000cc00 - 0x0000cc1f (0x20) IX[B]
>	[25] -1	0	0x0000c400 - 0x0000c41f (0x20) IX[B]
>	[26] -1	0	0x0000c480 - 0x0000c49f (0x20) IX[B]
>	[27] -1	0	0x0000c080 - 0x0000c087 (0x8) IX[B](B)
>(II) OS-reported resource ranges after removing overlaps with PCI:
>	[0] -1	0	0x00100000 - 0x3fffffff (0x3ff00000) MX[B]E(B)
>	[1] -1	0	0x000f0000 - 0x000fffff (0x10000) MX[B]
>	[2] -1	0	0x000c0000 - 0x000effff (0x30000) MX[B]
>	[3] -1	0	0x00000000 - 0x0009ffff (0xa0000) MX[B]
>	[4] -1	0	0x0000ffff - 0x0000ffff (0x1) IX[B]
>	[5] -1	0	0x00000000 - 0x000000ff (0x100) IX[B]
>(II) All system resource ranges:
>	[0] -1	0	0x00100000 - 0x3fffffff (0x3ff00000) MX[B]E(B)
>	[1] -1	0	0x000f0000 - 0x000fffff (0x10000) MX[B]
>	[2] -1	0	0x000c0000 - 0x000effff (0x30000) MX[B]
>	[3] -1	0	0x00000000 - 0x0009ffff (0xa0000) MX[B]
>	[4] -1	0	0xfebff000 - 0xfebfffff (0x1000) MX[B]
>	[5] -1	0	0xfeaff800 - 0xfeafffff (0x800) MX[B]
>	[6] -1	0	0xfe9ffc00 - 0xfe9ffcff (0x100) MX[B]
>	[7] -1	0	0xfe9ff800 - 0xfe9ffbff (0x400) MX[B]
>	[8] -1	0	0xfe9f8000 - 0xfe9fbfff (0x4000) MX[B]
>	[9] -1	0	0xfe9ff400 - 0xfe9ff7ff (0x400) MX[B]
>	[10] -1	0	0xfe700000 - 0xfe7fffff (0x100000) MX[B](B)
>	[11] -1	0	0xd0000000 - 0xdfffffff (0x10000000) MX[B](B)
>	[12] -1	0	0xfe800000 - 0xfe8fffff (0x100000) MX[B](B)
>	[13] -1	0	0x0000ffff - 0x0000ffff (0x1) IX[B]
>	[14] -1	0	0x00000000 - 0x000000ff (0x100) IX[B]
>	[15] -1	0	0x0000e800 - 0x0000e8ff (0x100) IX[B]
>	[16] -1	0	0x00000400 - 0x0000041f (0x20) IX[B]
>	[17] -1	0	0x0000d080 - 0x0000d08f (0x10) IX[B]
>	[18] -1	0	0x0000d400 - 0x0000d40f (0x10) IX[B]
>	[19] -1	0	0x0000d480 - 0x0000d483 (0x4) IX[B]
>	[20] -1	0	0x0000d800 - 0x0000d807 (0x8) IX[B]
>	[21] -1	0	0x0000d880 - 0x0000d883 (0x4) IX[B]
>	[22] -1	0	0x0000dc00 - 0x0000dc07 (0x8) IX[B]
>	[23] -1	0	0x0000ffa0 - 0x0000ffaf (0x10) IX[B]
>	[24] -1	0	0x00000374 - 0x00000374 (0x1) IX[B]
>	[25] -1	0	0x00000170 - 0x00000177 (0x8) IX[B]
>	[26] -1	0	0x000001f0 - 0x000001f0 (0x1) IX[B]
>	[27] -1	0	0x000001f0 - 0x000001f7 (0x8) IX[B]
>	[28] -1	0	0x0000c800 - 0x0000c81f (0x20) IX[B]
>	[29] -1	0	0x0000c880 - 0x0000c89f (0x20) IX[B]
>	[30] -1	0	0x0000cc00 - 0x0000cc1f (0x20) IX[B]
>	[31] -1	0	0x0000c400 - 0x0000c41f (0x20) IX[B]
>	[32] -1	0	0x0000c480 - 0x0000c49f (0x20) IX[B]
>	[33] -1	0	0x0000c080 - 0x0000c087 (0x8) IX[B](B)
>(II) LoadModule: "extmod"
>(II) Loading /usr/lib/xorg/modules/extensions//libextmod.so
>(II) Module extmod: vendor="X.Org Foundation"
>	compiled for 1.3.0, module version = 1.0.0
>	Module class: X.Org Server Extension
>	ABI class: X.Org Server Extension, version 0.3
>(II) Loading extension SHAPE
>(II) Loading extension MIT-SUNDRY-NONSTANDARD
>(II) Loading extension BIG-REQUESTS
>(II) Loading extension SYNC
>(II) Loading extension MIT-SCREEN-SAVER
>(II) Loading extension XC-MISC
>(II) Loading extension XFree86-VidModeExtension
>(II) Loading extension XFree86-Misc
>(II) Loading extension XFree86-DGA
>(II) Loading extension DPMS
>(II) Loading extension TOG-CUP
>(II) Loading extension Extended-Visual-Information
>(II) Loading extension XVideo
>(II) Loading extension XVideo-MotionCompensation
>(II) Loading extension X-Resource
>(II) LoadModule: "dbe"
>(II) Loading /usr/lib/xorg/modules/extensions//libdbe.so
>(II) Module dbe: vendor="X.Org Foundation"
>	compiled for 1.3.0, module version = 1.0.0
>	Module class: X.Org Server Extension
>	ABI class: X.Org Server Extension, version 0.3
>(II) Loading extension DOUBLE-BUFFER
>(II) LoadModule: "glx"
>(II) Loading /usr/lib/xorg/modules/extensions//libglx.so
>(II) Module glx: vendor="X.Org Foundation"
>	compiled for 1.3.0, module version = 1.0.0
>	ABI class: X.Org Server Extension, version 0.3
>(==) AIGLX enabled
>(II) Loading extension GLX
>(II) LoadModule: "freetype"
>(II) Loading /usr/lib/xorg/modules/fonts//libfreetype.so
>(II) Module freetype: vendor="X.Org Foundation & the After X-TT Project"
>	compiled for 1.3.0, module version = 2.1.0
>	Module class: X.Org Font Renderer
>	ABI class: X.Org Font Renderer, version 0.5
>(II) Loading font FreeType
>(II) LoadModule: "type1"
>(II) Loading /usr/lib/xorg/modules/fonts//libtype1.so
>(II) Module type1: vendor="X.Org Foundation"
>	compiled for 1.3.0, module version = 1.0.2
>	Module class: X.Org Font Renderer
>	ABI class: X.Org Font Renderer, version 0.5
>(II) Loading font Type1
>(II) LoadModule: "record"
>(II) Loading /usr/lib/xorg/modules/extensions//librecord.so
>(II) Module record: vendor="X.Org Foundation"
>	compiled for 1.3.0, module version = 1.13.0
>	Module class: X.Org Server Extension
>	ABI class: X.Org Server Extension, version 0.3
>(II) Loading extension RECORD
>(II) LoadModule: "dri"
>(II) Loading /usr/lib/xorg/modules/extensions//libdri.so
>(II) Module dri: vendor="X.Org Foundation"
>	compiled for 1.3.0, module version = 1.0.0
>	ABI class: X.Org Server Extension, version 0.3
>(II) Loading extension XFree86-DRI
>(II) LoadModule: "intel"
>(II) Loading /usr/lib/xorg/modules/drivers//intel_drv.so
>(II) Module intel: vendor="X.Org Foundation"
>	compiled for 1.3.0, module version = 2.4.0
>	Module class: X.Org Video Driver
>	ABI class: X.Org Video Driver, version 1.2
>(II) LoadModule: "mouse"
>(II) Loading /usr/lib/xorg/modules/input//mouse_drv.so
>(II) Module mouse: vendor="X.Org Foundation"
>	compiled for 1.3.0, module version = 1.2.3
>	Module class: X.Org XInput Driver
>	ABI class: X.Org XInput driver, version 0.7
>(II) LoadModule: "kbd"
>(II) Loading /usr/lib/xorg/modules/input//kbd_drv.so
>(II) Module kbd: vendor="X.Org Foundation"
>	compiled for 1.3.0, module version = 1.2.2
>	Module class: X.Org XInput Driver
>	ABI class: X.Org XInput driver, version 0.7
>(II) intel: Driver for Intel Integrated Graphics Chipsets: i810,
>	i810-dc100, i810e, i815, i830M, 845G, 852GM/855GM, 865G, 915G,
>	E7221 (i915), 915GM, 945G, 945GM, 945GME, 965G, G35, 965Q, 946GZ,
>	965GM, 965GME/GLE, G33, Q35, Q33,
>	Mobile IntelÂ® GM45 Express Chipset,
>	Intel Integrated Graphics Device, G45/G43, Q45/Q43
>(II) Primary Device is: PCI 00:02:0
>(WW) intel: No matching Device section for instance (BusID PCI:0:2:1) found
>(--) Chipset 965GME/GLE found
>(II) resource ranges after xf86ClaimFixedResources() call:
>	[0] -1	0	0x00100000 - 0x3fffffff (0x3ff00000) MX[B]E(B)
>	[1] -1	0	0x000f0000 - 0x000fffff (0x10000) MX[B]
>	[2] -1	0	0x000c0000 - 0x000effff (0x30000) MX[B]
>	[3] -1	0	0x00000000 - 0x0009ffff (0xa0000) MX[B]
>	[4] -1	0	0xfebff000 - 0xfebfffff (0x1000) MX[B]
>	[5] -1	0	0xfeaff800 - 0xfeafffff (0x800) MX[B]
>	[6] -1	0	0xfe9ffc00 - 0xfe9ffcff (0x100) MX[B]
>	[7] -1	0	0xfe9ff800 - 0xfe9ffbff (0x400) MX[B]
>	[8] -1	0	0xfe9f8000 - 0xfe9fbfff (0x4000) MX[B]
>	[9] -1	0	0xfe9ff400 - 0xfe9ff7ff (0x400) MX[B]
>	[10] -1	0	0xfe700000 - 0xfe7fffff (0x100000) MX[B](B)
>	[11] -1	0	0xd0000000 - 0xdfffffff (0x10000000) MX[B](B)
>	[12] -1	0	0xfe800000 - 0xfe8fffff (0x100000) MX[B](B)
>	[13] -1	0	0x0000ffff - 0x0000ffff (0x1) IX[B]
>	[14] -1	0	0x00000000 - 0x000000ff (0x100) IX[B]
>	[15] -1	0	0x0000e800 - 0x0000e8ff (0x100) IX[B]
>	[16] -1	0	0x00000400 - 0x0000041f (0x20) IX[B]
>	[17] -1	0	0x0000d080 - 0x0000d08f (0x10) IX[B]
>	[18] -1	0	0x0000d400 - 0x0000d40f (0x10) IX[B]
>	[19] -1	0	0x0000d480 - 0x0000d483 (0x4) IX[B]
>	[20] -1	0	0x0000d800 - 0x0000d807 (0x8) IX[B]
>	[21] -1	0	0x0000d880 - 0x0000d883 (0x4) IX[B]
>	[22] -1	0	0x0000dc00 - 0x0000dc07 (0x8) IX[B]
>	[23] -1	0	0x0000ffa0 - 0x0000ffaf (0x10) IX[B]
>	[24] -1	0	0x00000374 - 0x00000374 (0x1) IX[B]
>	[25] -1	0	0x00000170 - 0x00000177 (0x8) IX[B]
>	[26] -1	0	0x000001f0 - 0x000001f0 (0x1) IX[B]
>	[27] -1	0	0x000001f0 - 0x000001f7 (0x8) IX[B]
>	[28] -1	0	0x0000c800 - 0x0000c81f (0x20) IX[B]
>	[29] -1	0	0x0000c880 - 0x0000c89f (0x20) IX[B]
>	[30] -1	0	0x0000cc00 - 0x0000cc1f (0x20) IX[B]
>	[31] -1	0	0x0000c400 - 0x0000c41f (0x20) IX[B]
>	[32] -1	0	0x0000c480 - 0x0000c49f (0x20) IX[B]
>	[33] -1	0	0x0000c080 - 0x0000c087 (0x8) IX[B](B)
>(II) resource ranges after probing:
>	[0] -1	0	0x00100000 - 0x3fffffff (0x3ff00000) MX[B]E(B)
>	[1] -1	0	0x000f0000 - 0x000fffff (0x10000) MX[B]
>	[2] -1	0	0x000c0000 - 0x000effff (0x30000) MX[B]
>	[3] -1	0	0x00000000 - 0x0009ffff (0xa0000) MX[B]
>	[4] -1	0	0xfebff000 - 0xfebfffff (0x1000) MX[B]
>	[5] -1	0	0xfeaff800 - 0xfeafffff (0x800) MX[B]
>	[6] -1	0	0xfe9ffc00 - 0xfe9ffcff (0x100) MX[B]
>	[7] -1	0	0xfe9ff800 - 0xfe9ffbff (0x400) MX[B]
>	[8] -1	0	0xfe9f8000 - 0xfe9fbfff (0x4000) MX[B]
>	[9] -1	0	0xfe9ff400 - 0xfe9ff7ff (0x400) MX[B]
>	[10] -1	0	0xfe700000 - 0xfe7fffff (0x100000) MX[B](B)
>	[11] -1	0	0xd0000000 - 0xdfffffff (0x10000000) MX[B](B)
>	[12] -1	0	0xfe800000 - 0xfe8fffff (0x100000) MX[B](B)
>	[13] 0	0	0x000a0000 - 0x000affff (0x10000) MS[B]
>	[14] 0	0	0x000b0000 - 0x000b7fff (0x8000) MS[B]
>	[15] 0	0	0x000b8000 - 0x000bffff (0x8000) MS[B]
>	[16] -1	0	0x0000ffff - 0x0000ffff (0x1) IX[B]
>	[17] -1	0	0x00000000 - 0x000000ff (0x100) IX[B]
>	[18] -1	0	0x0000e800 - 0x0000e8ff (0x100) IX[B]
>	[19] -1	0	0x00000400 - 0x0000041f (0x20) IX[B]
>	[20] -1	0	0x0000d080 - 0x0000d08f (0x10) IX[B]
>	[21] -1	0	0x0000d400 - 0x0000d40f (0x10) IX[B]
>	[22] -1	0	0x0000d480 - 0x0000d483 (0x4) IX[B]
>	[23] -1	0	0x0000d800 - 0x0000d807 (0x8) IX[B]
>	[24] -1	0	0x0000d880 - 0x0000d883 (0x4) IX[B]
>	[25] -1	0	0x0000dc00 - 0x0000dc07 (0x8) IX[B]
>	[26] -1	0	0x0000ffa0 - 0x0000ffaf (0x10) IX[B]
>	[27] -1	0	0x00000374 - 0x00000374 (0x1) IX[B]
>	[28] -1	0	0x00000170 - 0x00000177 (0x8) IX[B]
>	[29] -1	0	0x000001f0 - 0x000001f0 (0x1) IX[B]
>	[30] -1	0	0x000001f0 - 0x000001f7 (0x8) IX[B]
>	[31] -1	0	0x0000c800 - 0x0000c81f (0x20) IX[B]
>	[32] -1	0	0x0000c880 - 0x0000c89f (0x20) IX[B]
>	[33] -1	0	0x0000cc00 - 0x0000cc1f (0x20) IX[B]
>	[34] -1	0	0x0000c400 - 0x0000c41f (0x20) IX[B]
>	[35] -1	0	0x0000c480 - 0x0000c49f (0x20) IX[B]
>	[36] -1	0	0x0000c080 - 0x0000c087 (0x8) IX[B](B)
>	[37] 0	0	0x000003b0 - 0x000003bb (0xc) IS[B]
>	[38] 0	0	0x000003c0 - 0x000003df (0x20) IS[B]
>(II) Setting vga for screen 0.
>(II) Enabling PCI device
>(II) Loading sub module "int10"
>(II) LoadModule: "int10"
>(II) Loading /usr/lib/xorg/modules//libint10.so
>(II) Module int10: vendor="X.Org Foundation"
>	compiled for 1.3.0, module version = 1.0.0
>	ABI class: X.Org Video Driver, version 1.2
>(II) Loading sub module "vbe"
>(II) LoadModule: "vbe"
>(II) Loading /usr/lib/xorg/modules//libvbe.so
>(II) Module vbe: vendor="X.Org Foundation"
>	compiled for 1.3.0, module version = 1.1.0
>	ABI class: X.Org Video Driver, version 1.2
>(II) Loading sub module "vgahw"
>(II) LoadModule: "vgahw"
>(II) Loading /usr/lib/xorg/modules//libvgahw.so
>(II) Module vgahw: vendor="X.Org Foundation"
>	compiled for 1.3.0, module version = 0.1.0
>	ABI class: X.Org Video Driver, version 1.2
>(**) intel(0): Depth 24, (--) framebuffer bpp 32
>(==) intel(0): RGB weight 888
>(==) intel(0): Default visual is TrueColor
>(**) intel(0): Option "AccelMethod" "EXA"
>(**) intel(0): Option "ModeDebug" "1"
>(II) intel(0): Integrated Graphics Chipset: Intel(R) 965GME/GLE
>(--) intel(0): Chipset: "965GME/GLE"
>(--) intel(0): Linear framebuffer at 0xD0000000
>(--) intel(0): IO registers at addr 0xFE800000
>(II) intel(0): Hardware state on X startup:
>(II) intel(0): DumpRegsBegin
>(II) intel(0):    VCLK_DIVISOR_VGA0: 0x00031108 (n = 3, m1 = 17, m2 = 8)
>(II) intel(0):    VCLK_DIVISOR_VGA1: 0x00031406 (n = 3, m1 = 20, m2 = 6)
>(II) intel(0):        VCLK_POST_DIV: 0x00020002 (vga0 p1 = 4, p2 = 2, vga1 p1 = 2, p2 = 2)
>(II) intel(0):            DPLL_TEST: 0x00010001 ()
>(II) intel(0):         CACHE_MODE_0: 0x00006800
>(II) intel(0):              D_STATE: 0x00000000
>(II) intel(0):        DSPCLK_GATE_D: 0x00001000 (clock gates disabled: DPLUNIT)
>(II) intel(0):       RENCLK_GATE_D1: 0x00000000
>(II) intel(0):       RENCLK_GATE_D2: 0x00000000
>(II) intel(0):                SDVOB: 0x0008001c (disabled, pipe A, stall disabled, detected)
>(II) intel(0):                SDVOC: 0x00080018 (disabled, pipe A, stall disabled, not detected)
>(II) intel(0):              SDVOUDI: 0x00000000
>(II) intel(0):               DSPARB: 0x00001d9c
>(II) intel(0):               DSPFW1: 0x3f880808
>(II) intel(0):               DSPFW2: 0x00000808
>(II) intel(0):               DSPFW3: 0x00000000
>(II) intel(0):                 ADPA: 0x80008000 (enabled, pipe A, -hsync, -vsync)
>(II) intel(0):                 LVDS: 0x42000300 (disabled, pipe B, 18 bit, 1 channel)
>(II) intel(0):                 DVOA: 0x00000000 (disabled, pipe A, no stall, -hsync, -vsync)
>(II) intel(0):                 DVOB: 0x0008001c (disabled, pipe A, no stall, +hsync, +vsync)
>(II) intel(0):                 DVOC: 0x00080018 (disabled, pipe A, no stall, +hsync, +vsync)
>(II) intel(0):          DVOA_SRCDIM: 0x00000000
>(II) intel(0):          DVOB_SRCDIM: 0x00000000
>(II) intel(0):          DVOC_SRCDIM: 0x00000000
>(II) intel(0):           PP_CONTROL: 0x00000002 (power target: off)
>(II) intel(0):            PP_STATUS: 0x00000000 (off, not ready, sequencing idle)
>(II) intel(0):         PFIT_CONTROL: 0x00000000
>(II) intel(0):      PFIT_PGM_RATIOS: 0x00000000
>(II) intel(0):      PORT_HOTPLUG_EN: 0x00000020
>(II) intel(0):    PORT_HOTPLUG_STAT: 0x00000b00
>(II) intel(0):             DSPACNTR: 0x48000000 (disabled, pipe A)
>(II) intel(0):           DSPASTRIDE: 0x00000280 (640 bytes)
>(II) intel(0):              DSPAPOS: 0x00000000 (0, 0)
>(II) intel(0):             DSPASIZE: 0x00000000 (1, 1)
>(II) intel(0):             DSPABASE: 0x00000000
>(II) intel(0):             DSPASURF: 0x00000000
>(II) intel(0):          DSPATILEOFF: 0x00000000
>(II) intel(0):            PIPEACONF: 0xc0000000 (enabled, active)
>(II) intel(0):             PIPEASRC: 0x027f01df (640, 480)
>(II) intel(0):            PIPEASTAT: 0x00020000 (status: VBLANK_INT_ENABLE)
>(II) intel(0):                 FPA0: 0x00031108 (n = 3, m1 = 17, m2 = 8)
>(II) intel(0):                 FPA1: 0x00031108 (n = 3, m1 = 17, m2 = 8)
>(II) intel(0):               DPLL_A: 0x84801a00 (enabled, non-dvo, VGA, default clock, DAC/serial mode, p1 = 8, p2 = 10)
>(II) intel(0):            DPLL_A_MD: 0x00000003
>(II) intel(0):             HTOTAL_A: 0x031f027f (640 active, 800 total)
>(II) intel(0):             HBLANK_A: 0x03170287 (648 start, 792 end)
>(II) intel(0):              HSYNC_A: 0x02ef028f (656 start, 752 end)
>(II) intel(0):             VTOTAL_A: 0x020c01df (480 active, 525 total)
>(II) intel(0):             VBLANK_A: 0x020401e7 (488 start, 517 end)
>(II) intel(0):              VSYNC_A: 0x01eb01e9 (490 start, 492 end)
>(II) intel(0):            BCLRPAT_A: 0x00000000
>(II) intel(0):         VSYNCSHIFT_A: 0x00000000
>(II) intel(0):             DSPBCNTR: 0x01000000 (disabled, pipe B)
>(II) intel(0):           DSPBSTRIDE: 0x00000000 (0 bytes)
>(II) intel(0):              DSPBPOS: 0x00000000 (0, 0)
>(II) intel(0):             DSPBSIZE: 0x00000000 (1, 1)
>(II) intel(0):             DSPBBASE: 0x00000000
>(II) intel(0):             DSPBSURF: 0x00000000
>(II) intel(0):          DSPBTILEOFF: 0x00000000
>(II) intel(0):            PIPEBCONF: 0x00000000 (disabled, inactive)
>(II) intel(0):             PIPEBSRC: 0x027f01df (640, 480)
>(II) intel(0):            PIPEBSTAT: 0x00020000 (status: VBLANK_INT_ENABLE)
>(II) intel(0):                 FPB0: 0x00031108 (n = 3, m1 = 17, m2 = 8)
>(II) intel(0):                 FPB1: 0x00031108 (n = 3, m1 = 17, m2 = 8)
>(II) intel(0):               DPLL_B: 0x04800c00 (disabled, non-dvo, VGA, default clock, DAC/serial mode, p1 = 8, p2 = 10)
>(II) intel(0):            DPLL_B_MD: 0x00000303
>(II) intel(0):             HTOTAL_B: 0x031f027f (640 active, 800 total)
>(II) intel(0):             HBLANK_B: 0x03170287 (648 start, 792 end)
>(II) intel(0):              HSYNC_B: 0x02ef028f (656 start, 752 end)
>(II) intel(0):             VTOTAL_B: 0x020c01df (480 active, 525 total)
>(II) intel(0):             VBLANK_B: 0x020401e7 (488 start, 517 end)
>(II) intel(0):              VSYNC_B: 0x01eb01e9 (490 start, 492 end)
>(II) intel(0):            BCLRPAT_B: 0x00000000
>(II) intel(0):         VSYNCSHIFT_B: 0x00000000
>(II) intel(0):    VCLK_DIVISOR_VGA0: 0x00031108
>(II) intel(0):    VCLK_DIVISOR_VGA1: 0x00031406
>(II) intel(0):        VCLK_POST_DIV: 0x00020002
>(II) intel(0):             VGACNTRL: 0x0020008e (enabled)
>(II) intel(0):               TV_CTL: 0x00000010
>(II) intel(0):               TV_DAC: 0x70000000
>(II) intel(0):             TV_CSC_Y: 0x00000000
>(II) intel(0):            TV_CSC_Y2: 0x00000000
>(II) intel(0):             TV_CSC_U: 0x00000000
>(II) intel(0):            TV_CSC_U2: 0x00000000
>(II) intel(0):             TV_CSC_V: 0x00000000
>(II) intel(0):            TV_CSC_V2: 0x00000000
>(II) intel(0):         TV_CLR_KNOBS: 0x00000000
>(II) intel(0):         TV_CLR_LEVEL: 0x00000000
>(II) intel(0):           TV_H_CTL_1: 0x00000000
>(II) intel(0):           TV_H_CTL_2: 0x00000000
>(II) intel(0):           TV_H_CTL_3: 0x00000000
>(II) intel(0):           TV_V_CTL_1: 0x00000000
>(II) intel(0):           TV_V_CTL_2: 0x00000000
>(II) intel(0):           TV_V_CTL_3: 0x00000000
>(II) intel(0):           TV_V_CTL_4: 0x00000000
>(II) intel(0):           TV_V_CTL_5: 0x00000000
>(II) intel(0):           TV_V_CTL_6: 0x00000000
>(II) intel(0):           TV_V_CTL_7: 0x00000000
>(II) intel(0):          TV_SC_CTL_1: 0x00000000
>(II) intel(0):          TV_SC_CTL_2: 0x00000000
>(II) intel(0):          TV_SC_CTL_3: 0x00000000
>(II) intel(0):           TV_WIN_POS: 0x00000000
>(II) intel(0):          TV_WIN_SIZE: 0x00000000
>(II) intel(0):      TV_FILTER_CTL_1: 0x00000000
>(II) intel(0):      TV_FILTER_CTL_2: 0x00000000
>(II) intel(0):      TV_FILTER_CTL_3: 0x00000000
>(II) intel(0):        TV_CC_CONTROL: 0x00000000
>(II) intel(0):           TV_CC_DATA: 0x00000000
>(II) intel(0):          TV_H_LUMA_0: 0x00000000
>(II) intel(0):         TV_H_LUMA_59: 0x00000000
>(II) intel(0):        TV_H_CHROMA_0: 0x00000000
>(II) intel(0):       TV_H_CHROMA_59: 0x00000000
>(II) intel(0):         FBC_CFB_BASE: 0x00000000
>(II) intel(0):          FBC_LL_BASE: 0x00000000
>(II) intel(0):          FBC_CONTROL: 0x00000000
>(II) intel(0):          FBC_COMMAND: 0x00000000
>(II) intel(0):           FBC_STATUS: 0x20000000
>(II) intel(0):         FBC_CONTROL2: 0x00000000
>(II) intel(0):        FBC_FENCE_OFF: 0x00000000
>(II) intel(0):          FBC_MOD_NUM: 0x00000000
>(II) intel(0):              MI_MODE: 0x00000200
>(II) intel(0):         MI_ARB_STATE: 0x00000044
>(II) intel(0):       MI_RDRET_STATE: 0x00000000
>(II) intel(0):              ECOSKPD: 0x00000307
>(II) intel(0):                 DP_B: 0x00000000
>(II) intel(0):       DPB_AUX_CH_CTL: 0x00000000
>(II) intel(0):     DPB_AUX_CH_DATA1: 0x00000000
>(II) intel(0):     DPB_AUX_CH_DATA2: 0x00000000
>(II) intel(0):     DPB_AUX_CH_DATA3: 0x00000000
>(II) intel(0):     DPB_AUX_CH_DATA4: 0x00000000
>(II) intel(0):     DPB_AUX_CH_DATA5: 0x00000000
>(II) intel(0):                 DP_C: 0x00000000
>(II) intel(0):       DPC_AUX_CH_CTL: 0x00000000
>(II) intel(0):     DPC_AUX_CH_DATA1: 0x00000000
>(II) intel(0):     DPC_AUX_CH_DATA2: 0x00000000
>(II) intel(0):     DPC_AUX_CH_DATA3: 0x00000000
>(II) intel(0):     DPC_AUX_CH_DATA4: 0x00000000
>(II) intel(0):     DPC_AUX_CH_DATA5: 0x00000000
>(II) intel(0):                 DP_D: 0x00000000
>(II) intel(0):       DPD_AUX_CH_CTL: 0x00000000
>(II) intel(0):     DPD_AUX_CH_DATA1: 0x00000000
>(II) intel(0):     DPD_AUX_CH_DATA2: 0x00000000
>(II) intel(0):     DPD_AUX_CH_DATA3: 0x00000000
>(II) intel(0):     DPD_AUX_CH_DATA4: 0x00000000
>(II) intel(0):     DPD_AUX_CH_DATA5: 0x00000000
>(II) intel(0): SDVO phase shift 13 out of range -- probobly not an issue.
>(II) intel(0): pipe A dot 25200 n 3 m1 17 m2 8 p1 8 p2 10
>(II) intel(0): pipe B dot 25200 n 3 m1 17 m2 8 p1 8 p2 10
>(II) intel(0): DumpRegsEnd
>(II) intel(0): 2 display pipes available.
>(**) intel(0): Using EXA for acceleration
>(II) Loading sub module "ddc"
>(II) LoadModule: "ddc"(II) Module already built-in
>(II) Loading sub module "i2c"
>(II) LoadModule: "i2c"(II) Module already built-in
>(II) intel(0): Output VGA using monitor section Monitor-VGA
>(**) intel(0): Option "PreferredMode" "640x480"
>(**) intel(0): Option "Enable" "YES"
>(II) intel(0): I2C bus "CRTDDC_A" initialized.
>(II) intel(0): Output LVDS using monitor section Monitor-LVDS
>(**) intel(0): Option "Ignore" "Yes"
>(II) intel(0): I2C bus "SDVOCTRL_E for SDVOB" initialized.
>(II) intel(0): I2C device "SDVOCTRL_E for SDVOB:SDVO Controller B" registered at address 0x70.
>(II) intel(0): I2C bus "SDVOB DDC Bus" initialized.
>(II) intel(0): SDVOB: W: 02                         (SDVO_CMD_GET_DEVICE_CAPS)
>(II) intel(0): SDVOB: R: 02 3C 06 01 01 01 01 00 (Success)
>(II) intel(0): SDVOB: W: 9D                         (SDVO_CMD_GET_SUPP_ENCODE)
>(II) intel(0): SDVOB: R: 00 00                   (Not supported)
>(II) intel(0): Output TMDS-1 has no monitor section
>(II) intel(0): SDVOB: W: 10 00                      (SDVO_CMD_SET_TARGET_INPUT)
>(II) intel(0): SDVOB: R:                         (Success)
>(II) intel(0): SDVOB: W: 1D                         (SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE)
>(II) intel(0): SDVOB: R: C4 09 20 4E             (Success)
>(II) intel(0): SDVOB: device VID/DID: 02:3C.06, clock range 25.0MHz - 200.0MHz
>(II) intel(0): SDVOB: 1 input channel
>(II) intel(0): SDVOB: TMDS0 output reported
>(II) Loading sub module "int10"
>(II) LoadModule: "int10"
>(II) Reloading /usr/lib/xorg/modules//libint10.so
>(II) intel(0): initializing int10
>(WW) intel(0): Bad V_BIOS checksum
>(II) intel(0): Primary V_BIOS segment is: 0xc000
>(II) intel(0): VESA BIOS detected
>(II) intel(0): VESA VBE Version 3.0
>(II) intel(0): VESA VBE Total Mem: 7616 kB
>(II) intel(0): VESA VBE OEM: Intel(r)GM965/PM965/GL960 Graphics Chip Accelerated VGA BIOS
>(II) intel(0): VESA VBE OEM Software Rev: 1.0
>(II) intel(0): VESA VBE OEM Vendor: Intel Corporation
>(II) intel(0): VESA VBE OEM Product: Intel(r)GM965/PM965/GL960 Graphics Controller
>(II) intel(0): VESA VBE OEM Product Rev: Hardware Version 0.0
>(II) intel(0): SDVOB: W: 20                         (SDVO_CMD_GET_CLOCK_RATE_MULT)
>(II) intel(0): SDVOB: R: 01                      (Success)
>(II) intel(0): Current clock rate multiplier: 1
>(II) intel(0): SDVOB: W: 04                         (SDVO_CMD_GET_ACTIVE_OUTPUTS)
>(II) intel(0): SDVOB: R: 00 00                   (Success)
>(II) intel(0): SDVOB: W: 10 00                      (SDVO_CMD_SET_TARGET_INPUT)
>(II) intel(0): SDVOB: R:                         (Success)
>(II) intel(0): SDVOB: W: 12                         (SDVO_CMD_GET_INPUT_TIMINGS_PART1)
>(II) intel(0): SDVOB: R: 64 19 00 40 41 00 26 30 (Success)
>(II) intel(0): SDVOB: W: 13                         (SDVO_CMD_GET_INPUT_TIMINGS_PART2)
>(II) intel(0): SDVOB: R: 18 88 36 00 18 00 00 00 (Success)
>(II) intel(0): SDVOB: W: 11 01 00                   (SDVO_CMD_SET_TARGET_OUTPUT)
>(II) intel(0): SDVOB: R:                         (Success)
>(II) intel(0): SDVOB: W: 18                         (SDVO_CMD_GET_OUTPUT_TIMINGS_PART1)
>(II) intel(0): SDVOB: R: 64 19 00 40 41 00 26 30 (Success)
>(II) intel(0): SDVOB: W: 19                         (SDVO_CMD_GET_OUTPUT_TIMINGS_PART2)
>(II) intel(0): SDVOB: R: 18 88 36 00 18 00 00 00 (Success)
>(II) intel(0): Mode for pipe A:
>(II) intel(0): Modeline "640x480"x0.0   31.50  640 664 704 832  480 489 491 520 -hsync -vsync (37.9 kHz)
>(II) intel(0): chosen: dotclock 31500 vco 2520000 ((m 105, m1 17, m2 8), n 2, (p 80, p1 8, p2 10))
>(II) intel(0): SDVOB: W: 05 00 00                   (SDVO_CMD_SET_ACTIVE_OUTPUTS)
>(II) intel(0): SDVOB: R:                         (Success)
>(**) intel(0): Option "ddc" "0"
>(II) intel(0): EDID for output VGA
>(II) intel(0): Not using default mode "640x350" (vrefresh out of range)
>(II) intel(0): Not using default mode "640x400" (vrefresh out of range)
>(II) intel(0): Not using default mode "720x400" (width too large for virtual size)
>(II) intel(0): Not using default mode "640x480" (vrefresh out of range)
>(II) intel(0): Not using default mode "640x480" (vrefresh out of range)
>(II) intel(0): Not using default mode "640x480" (vrefresh out of range)
>(II) intel(0): Not using default mode "800x600" (height too large for virtual size)
>(II) intel(0): Not using default mode "800x600" (height too large for virtual size)
>(II) intel(0): Not using default mode "800x600" (height too large for virtual size)
>(II) intel(0): Not using default mode "800x600" (height too large for virtual size)
>(II) intel(0): Not using default mode "800x600" (height too large for virtual size)
>(II) intel(0): Not using default mode "1024x768" (height too large for virtual size)
>(II) intel(0): Not using default mode "1024x768" (height too large for virtual size)
>(II) intel(0): Not using default mode "1024x768" (height too large for virtual size)
>(II) intel(0): Not using default mode "1024x768" (height too large for virtual size)
>(II) intel(0): Not using default mode "1152x864" (height too large for virtual size)
>(II) intel(0): Not using default mode "1280x960" (height too large for virtual size)
>(II) intel(0): Not using default mode "1280x960" (height too large for virtual size)
>(II) intel(0): Not using default mode "1280x1024" (height too large for virtual size)
>(II) intel(0): Not using default mode "1280x1024" (height too large for virtual size)
>(II) intel(0): Not using default mode "1280x1024" (height too large for virtual size)
>(II) intel(0): Not using default mode "1600x1200" (height too large for virtual size)
>(II) intel(0): Not using default mode "1600x1200" (height too large for virtual size)
>(II) intel(0): Not using default mode "1600x1200" (height too large for virtual size)
>(II) intel(0): Not using default mode "1600x1200" (height too large for virtual size)
>(II) intel(0): Not using default mode "1600x1200" (height too large for virtual size)
>(II) intel(0): Not using default mode "1792x1344" (height too large for virtual size)
>(II) intel(0): Not using default mode "1792x1344" (height too large for virtual size)
>(II) intel(0): Not using default mode "1856x1392" (height too large for virtual size)
>(II) intel(0): Not using default mode "1856x1392" (height too large for virtual size)
>(II) intel(0): Not using default mode "1920x1440" (height too large for virtual size)
>(II) intel(0): Not using default mode "1920x1440" (height too large for virtual size)
>(II) intel(0): Not using default mode "832x624" (height too large for virtual size)
>(II) intel(0): Not using default mode "1152x768" (height too large for virtual size)
>(II) intel(0): Not using default mode "1152x864" (height too large for virtual size)
>(II) intel(0): Not using default mode "1152x864" (height too large for virtual size)
>(II) intel(0): Not using default mode "1152x864" (height too large for virtual size)
>(II) intel(0): Not using default mode "1152x864" (height too large for virtual size)
>(II) intel(0): Not using default mode "1152x864" (height too large for virtual size)
>(II) intel(0): Not using default mode "1152x864" (height too large for virtual size)
>(II) intel(0): Not using default mode "1280x720" (height too large for virtual size)
>(II) intel(0): Not using default mode "1280x720" (height too large for virtual size)
>(II) intel(0): Not using default mode "1280x720" (height too large for virtual size)
>(II) intel(0): Not using default mode "1280x720" (height too large for virtual size)
>(II) intel(0): Not using default mode "1280x800" (height too large for virtual size)
>(II) intel(0): Not using default mode "1280x800" (height too large for virtual size)
>(II) intel(0): Not using default mode "1280x800" (height too large for virtual size)
>(II) intel(0): Not using default mode "1280x800" (height too large for virtual size)
>(II) intel(0): Not using default mode "1280x768" (height too large for virtual size)
>(II) intel(0): Not using default mode "1280x768" (height too large for virtual size)
>(II) intel(0): Not using default mode "1280x768" (height too large for virtual size)
>(II) intel(0): Not using default mode "1280x768" (height too large for virtual size)
>(II) intel(0): Not using default mode "1360x768" (height too large for virtual size)
>(II) intel(0): Not using default mode "1360x768" (height too large for virtual size)
>(II) intel(0): Not using default mode "1400x1050" (height too large for virtual size)
>(II) intel(0): Not using default mode "1400x1050" (height too large for virtual size)
>(II) intel(0): Not using default mode "1400x1050" (height too large for virtual size)
>(II) intel(0): Not using default mode "1400x1050" (height too large for virtual size)
>(II) intel(0): Not using default mode "1400x1050" (height too large for virtual size)
>(II) intel(0): Not using default mode "1400x1050" (height too large for virtual size)
>(II) intel(0): Not using default mode "1440x900" (height too large for virtual size)
>(II) intel(0): Not using default mode "1600x1024" (height too large for virtual size)
>(II) intel(0): Not using default mode "1680x1050" (height too large for virtual size)
>(II) intel(0): Not using default mode "1680x1050" (height too large for virtual size)
>(II) intel(0): Not using default mode "1680x1050" (height too large for virtual size)
>(II) intel(0): Not using default mode "1680x1050" (height too large for virtual size)
>(II) intel(0): Not using default mode "1680x1050" (height too large for virtual size)
>(II) intel(0): Not using default mode "1920x1080" (height too large for virtual size)
>(II) intel(0): Not using default mode "1920x1200" (height too large for virtual size)
>(II) intel(0): Not using default mode "1920x1440" (height too large for virtual size)
>(II) intel(0): Not using default mode "2048x1536" (height too large for virtual size)
>(II) intel(0): Not using default mode "2048x1536" (height too large for virtual size)
>(II) intel(0): Not using default mode "2048x1536" (height too large for virtual size)
>(II) intel(0): Printing probed modes for output VGA
>(II) intel(0): Modeline "640x480"x59.9   25.18  640 656 752 800  480 490 492 525 -hsync -vsync (31.5 kHz)
>(II) intel(0): SDVOB: W: 0B                         (SDVO_CMD_GET_ATTACHED_DISPLAYS)
>(II) intel(0): SDVOB: R: 00 00                   (Success)
>(II) intel(0): EDID for output TMDS-1
>(II) intel(0): Output VGA enabled by config file
>(II) intel(0): Output TMDS-1 disconnected
>(II) intel(0): Output VGA using initial mode 640x480
>(II) intel(0): SDVOB: W: 05 00 00                   (SDVO_CMD_SET_ACTIVE_OUTPUTS)
>(II) intel(0): SDVOB: R:                         (Success)
>(II) intel(0): SDVOB: W: 05 00 00                   (SDVO_CMD_SET_ACTIVE_OUTPUTS)
>(II) intel(0): SDVOB: R:                         (Success)
>(II) intel(0): SDVOB: W: 11 01 00                   (SDVO_CMD_SET_TARGET_OUTPUT)
>(II) intel(0): SDVOB: R:                         (Success)
>(II) intel(0): SDVOB: W: 16 64 19 00 40 41 00 26 30 (SDVO_CMD_SET_OUTPUT_TIMINGS_PART1)
>(II) intel(0): SDVOB: R:                         (Success)
>(II) intel(0): SDVOB: W: 17 18 88 36 00 18 00 00 00 (SDVO_CMD_SET_OUTPUT_TIMINGS_PART2)
>(II) intel(0): SDVOB: R:                         (Success)
>(II) intel(0): SDVOB: W: 10 00                      (SDVO_CMD_SET_TARGET_INPUT)
>(II) intel(0): SDVOB: R:                         (Success)
>(II) intel(0): SDVOB: W: 14 64 19 00 40 41 00 26 30 (SDVO_CMD_SET_INPUT_TIMINGS_PART1)
>(II) intel(0): SDVOB: R:                         (Success)
>(II) intel(0): SDVOB: W: 15 18 88 36 00 18 00 00 00 (SDVO_CMD_SET_INPUT_TIMINGS_PART2)
>(II) intel(0): SDVOB: R:                         (Success)
>(II) intel(0): SDVOB: W: 21 01                      (SDVO_CMD_SET_CLOCK_RATE_MULT)
>(II) intel(0): SDVOB: R:                         (Success)
>(II) intel(0): SDVOB: W: 05 00 00                   (SDVO_CMD_SET_ACTIVE_OUTPUTS)
>(II) intel(0): SDVOB: R:                         (Success)
>(II) intel(0): Monitoring connected displays enabled
>(II) intel(0): detected 512 kB GTT.
>(II) intel(0): detected 7676 kB stolen memory.
>(==) intel(0): video overlay key set to 0x101fe
>(==) intel(0): Will not try to enable page flipping
>(==) intel(0): Triple buffering disabled
>(==) intel(0): Intel XvMC decoder disabled
>(**) intel(0): Using gamma correction (1.0, 1.0, 1.0)
>(++) intel(0): DPI set to (75, 75)
>(II) Loading sub module "fb"
>(II) LoadModule: "fb"
>(II) Loading /usr/lib/xorg/modules//libfb.so
>(II) Module fb: vendor="X.Org Foundation"
>	compiled for 1.3.0, module version = 1.0.0
>	ABI class: X.Org ANSI C Emulation, version 0.3
>(II) Loading sub module "exa"
>(II) LoadModule: "exa"
>(II) Loading /usr/lib/xorg/modules//libexa.so
>(II) Module exa: vendor="X.Org Foundation"
>	compiled for 1.3.0, module version = 2.2.0
>	ABI class: X.Org Video Driver, version 1.2
>(II) Loading sub module "ramdac"
>(II) LoadModule: "ramdac"(II) Module already built-in
>(II) intel(0): Comparing regs from server start up to After PreInit
>(==) Depth 24 pixmap format is 32 bpp
>(II) do I need RAC?  No, I don't.
>(II) resource ranges after preInit:
>	[0] 0	0	0xd0000000 - 0xdfffffff (0x10000000) MS[B]
>	[1] 0	0	0xfe800000 - 0xfe8fffff (0x100000) MS[B]
>	[2] -1	0	0x00100000 - 0x3fffffff (0x3ff00000) MX[B]E(B)
>	[3] -1	0	0x000f0000 - 0x000fffff (0x10000) MX[B]
>	[4] -1	0	0x000c0000 - 0x000effff (0x30000) MX[B]
>	[5] -1	0	0x00000000 - 0x0009ffff (0xa0000) MX[B]
>	[6] -1	0	0xfebff000 - 0xfebfffff (0x1000) MX[B]
>	[7] -1	0	0xfeaff800 - 0xfeafffff (0x800) MX[B]
>	[8] -1	0	0xfe9ffc00 - 0xfe9ffcff (0x100) MX[B]
>	[9] -1	0	0xfe9ff800 - 0xfe9ffbff (0x400) MX[B]
>	[10] -1	0	0xfe9f8000 - 0xfe9fbfff (0x4000) MX[B]
>	[11] -1	0	0xfe9ff400 - 0xfe9ff7ff (0x400) MX[B]
>	[12] -1	0	0xfe700000 - 0xfe7fffff (0x100000) MX[B](B)
>	[13] -1	0	0xd0000000 - 0xdfffffff (0x10000000) MX[B](B)
>	[14] -1	0	0xfe800000 - 0xfe8fffff (0x100000) MX[B](B)
>	[15] 0	0	0x000a0000 - 0x000affff (0x10000) MS[B](OprD)
>	[16] 0	0	0x000b0000 - 0x000b7fff (0x8000) MS[B](OprD)
>	[17] 0	0	0x000b8000 - 0x000bffff (0x8000) MS[B](OprD)
>	[18] 0	0	0x0000c080 - 0x0000c087 (0x8) IS[B]
>	[19] -1	0	0x0000ffff - 0x0000ffff (0x1) IX[B]
>	[20] -1	0	0x00000000 - 0x000000ff (0x100) IX[B]
>	[21] -1	0	0x0000e800 - 0x0000e8ff (0x100) IX[B]
>	[22] -1	0	0x00000400 - 0x0000041f (0x20) IX[B]
>	[23] -1	0	0x0000d080 - 0x0000d08f (0x10) IX[B]
>	[24] -1	0	0x0000d400 - 0x0000d40f (0x10) IX[B]
>	[25] -1	0	0x0000d480 - 0x0000d483 (0x4) IX[B]
>	[26] -1	0	0x0000d800 - 0x0000d807 (0x8) IX[B]
>	[27] -1	0	0x0000d880 - 0x0000d883 (0x4) IX[B]
>	[28] -1	0	0x0000dc00 - 0x0000dc07 (0x8) IX[B]
>	[29] -1	0	0x0000ffa0 - 0x0000ffaf (0x10) IX[B]
>	[30] -1	0	0x00000374 - 0x00000374 (0x1) IX[B]
>	[31] -1	0	0x00000170 - 0x00000177 (0x8) IX[B]
>	[32] -1	0	0x000001f0 - 0x000001f0 (0x1) IX[B]
>	[33] -1	0	0x000001f0 - 0x000001f7 (0x8) IX[B]
>	[34] -1	0	0x0000c800 - 0x0000c81f (0x20) IX[B]
>	[35] -1	0	0x0000c880 - 0x0000c89f (0x20) IX[B]
>	[36] -1	0	0x0000cc00 - 0x0000cc1f (0x20) IX[B]
>	[37] -1	0	0x0000c400 - 0x0000c41f (0x20) IX[B]
>	[38] -1	0	0x0000c480 - 0x0000c49f (0x20) IX[B]
>	[39] -1	0	0x0000c080 - 0x0000c087 (0x8) IX[B](B)
>	[40] 0	0	0x000003b0 - 0x000003bb (0xc) IS[B](OprU)
>	[41] 0	0	0x000003c0 - 0x000003df (0x20) IS[B](OprU)
>(II) intel(0): Kernel reported 238848 total, 1 used
>(II) intel(0): I830CheckAvailableMemory: 955388 kB available
>drmOpenDevice: node name is /dev/dri/card0
>drmOpenDevice: open result is 9, (OK)
>drmOpenDevice: node name is /dev/dri/card0
>drmOpenDevice: open result is 9, (OK)
>drmOpenByBusid: Searching for BusID pci:0000:00:02.0
>drmOpenDevice: node name is /dev/dri/card0
>drmOpenDevice: open result is 9, (OK)
>drmOpenByBusid: drmOpenMinor returns 9
>drmOpenByBusid: drmGetBusid reports pci:0000:00:02.0
>(II) [drm] DRM interface version 1.3
>(II) [drm] DRM open master succeeded.
>(II) intel(0): [drm] Using the DRM lock SAREA also for drawables.
>(II) intel(0): [drm] framebuffer mapped by ddx driver
>(II) intel(0): [drm] added 1 reserved context for kernel
>(II) intel(0): X context handle = 0x1
>(II) intel(0): [drm] installed DRM signal handler
>(**) intel(0): Framebuffer compression enabled
>(**) intel(0): Tiling enabled
>(==) intel(0): VideoRam: 262144 KB
>(II) intel(0): Attempting memory allocation with tiled buffers.
>(II) intel(0): Tiled allocation successful.
>(II) intel(0): [drm] Registers = 0xfe800000
>(II) intel(0): [drm] ring buffer = 0xd0000000
>(II) intel(0): [drm] mapped front buffer at 0xd0700000, handle = 0xd0700000
>(II) intel(0): [drm] mapped back buffer at 0xd0c14000, handle = 0xd0c14000
>(II) intel(0): [drm] mapped depth buffer at 0xd0d40000, handle = 0xd0d40000
>(II) intel(0): [drm] mapped classic textures at 0xd0e6c000, handle = 0xd0e6c000
>(II) intel(0): [drm] Initialized kernel agp heap manager, 33554432
>(II) intel(0): [dri] visual configs initialized
>(II) intel(0): Page Flipping disabled
>(==) intel(0): Write-combining range (0xd0000000,0x10000000)
>(II) intel(0): vgaHWGetIOBase: hwp->IOBase is 0x03d0, hwp->PIOOffset is 0x0000
>(II) EXA(0): Offscreen pixmap area of 3686400 bytes
>(II) EXA(0): Driver registered support for the following operations:
>(II)         Solid
>(II)         Copy
>(II)         Composite (RENDER acceleration)
>(==) intel(0): Backing store disabled
>(==) intel(0): Silken mouse enabled
>(II) intel(0): Initializing HW Cursor
>(II) intel(0): [DRI] installation complete
>(II) intel(0): SDVOB: W: 20                         (SDVO_CMD_GET_CLOCK_RATE_MULT)
>(II) intel(0): SDVOB: R: 01                      (Success)
>(II) intel(0): Current clock rate multiplier: 1
>(II) intel(0): SDVOB: W: 04                         (SDVO_CMD_GET_ACTIVE_OUTPUTS)
>(II) intel(0): SDVOB: R: 00 00                   (Success)
>(II) intel(0): SDVOB: W: 10 00                      (SDVO_CMD_SET_TARGET_INPUT)
>(II) intel(0): SDVOB: R:                         (Success)
>(II) intel(0): SDVOB: W: 12                         (SDVO_CMD_GET_INPUT_TIMINGS_PART1)
>(II) intel(0): SDVOB: R: 64 19 00 40 41 00 26 30 (Success)
>(II) intel(0): SDVOB: W: 13                         (SDVO_CMD_GET_INPUT_TIMINGS_PART2)
>(II) intel(0): SDVOB: R: 18 88 36 00 18 00 00 00 (Success)
>(II) intel(0): SDVOB: W: 11 01 00                   (SDVO_CMD_SET_TARGET_OUTPUT)
>(II) intel(0): SDVOB: R:                         (Success)
>(II) intel(0): SDVOB: W: 18                         (SDVO_CMD_GET_OUTPUT_TIMINGS_PART1)
>(II) intel(0): SDVOB: R: 64 19 00 40 41 00 26 30 (Success)
>(II) intel(0): SDVOB: W: 19                         (SDVO_CMD_GET_OUTPUT_TIMINGS_PART2)
>(II) intel(0): SDVOB: R: 18 88 36 00 18 00 00 00 (Success)
>(II) intel(0): xf86BindGARTMemory: bind key 0 at 0x0077f000 (pgoffset 1919)
>(II) intel(0): xf86BindGARTMemory: bind key 1 at 0x00890000 (pgoffset 2192)
>(II) intel(0): xf86BindGARTMemory: bind key 2 at 0x00c14000 (pgoffset 3092)
>(II) intel(0): xf86BindGARTMemory: bind key 3 at 0x00d40000 (pgoffset 3392)
>(II) intel(0): xf86BindGARTMemory: bind key 4 at 0x00e6c000 (pgoffset 3692)
>(II) intel(0): Fixed memory allocation layout:
>(II) intel(0): 0x00000000-0x0001ffff: ring buffer (128 kB)
>(II) intel(0): 0x00020000-0x0061ffff: compressed frame buffer (6144 kB, 0x000000003f820000 physical
>)
>(II) intel(0): 0x00620000-0x00620fff: compressed ll buffer (4 kB, 0x000000003fe20000 physical
>)
>(II) intel(0): 0x00621000-0x0062afff: HW cursors (40 kB)
>(II) intel(0): 0x0062b000-0x00632fff: logical 3D context (32 kB)
>(II) intel(0): 0x00633000-0x00644fff: exa G965 state buffer (72 kB)
>(II) intel(0): 0x00645000-0x00645fff: overlay registers (4 kB)
>(II) intel(0): 0x00646000-0x00646fff: power context (4 kB)
>(II) intel(0): 0x00700000-0x0088ffff: front buffer (1600 kB) X tiled
>(II) intel(0): 0x0077f000:            end of stolen memory
>(II) intel(0): 0x00890000-0x00c13fff: exa offscreen (3600 kB)
>(II) intel(0): 0x00c14000-0x00d3ffff: back buffer (1200 kB) X tiled
>(II) intel(0): 0x00d40000-0x00e6bfff: depth buffer (1200 kB) Y tiled
>(II) intel(0): 0x00e6c000-0x02e6bfff: classic textures (32768 kB)
>(II) intel(0): 0x10000000:            end of aperture
>(II) intel(0): SDVOB: W: 05 00 00                   (SDVO_CMD_SET_ACTIVE_OUTPUTS)
>(II) intel(0): SDVOB: R:                         (Success)
>(II) intel(0): Mode for pipe A:
>(II) intel(0): Modeline "640x480"x59.9   25.18  640 656 752 800  480 490 492 525 -hsync -vsync (31.5 kHz)
>(II) intel(0): chosen: dotclock 25200 vco 2016000 ((m 84, m1 13, m2 7), n 2, (p 80, p1 8, p2 10))
>(II) intel(0): SDVOB: W: 05 00 00                   (SDVO_CMD_SET_ACTIVE_OUTPUTS)
>(II) intel(0): SDVOB: R:                         (Success)
>(II) intel(0): Hardware state at EnterVT:
>(II) intel(0): DumpRegsBegin
>(II) intel(0):    VCLK_DIVISOR_VGA0: 0x00031108 (n = 3, m1 = 17, m2 = 8)
>(II) intel(0):    VCLK_DIVISOR_VGA1: 0x00031406 (n = 3, m1 = 20, m2 = 6)
>(II) intel(0):        VCLK_POST_DIV: 0x00020002 (vga0 p1 = 4, p2 = 2, vga1 p1 = 2, p2 = 2)
>(II) intel(0):            DPLL_TEST: 0x00010001 ()
>(II) intel(0):         CACHE_MODE_0: 0x00006800
>(II) intel(0):              D_STATE: 0x00000000
>(II) intel(0):        DSPCLK_GATE_D: 0x00000000 (clock gates disabled:)
>(II) intel(0):       RENCLK_GATE_D1: 0x20000000
>(II) intel(0):       RENCLK_GATE_D2: 0x00000000
>(II) intel(0):                SDVOB: 0x0008001c (disabled, pipe A, stall disabled, detected)
>(II) intel(0):                SDVOC: 0x00080018 (disabled, pipe A, stall disabled, not detected)
>(II) intel(0):              SDVOUDI: 0x00000000
>(II) intel(0):               DSPARB: 0x00001d9c
>(II) intel(0):               DSPFW1: 0x3f880808
>(II) intel(0):               DSPFW2: 0x00000808
>(II) intel(0):               DSPFW3: 0x00000000
>(II) intel(0):                 ADPA: 0x80000000 (enabled, pipe A, -hsync, -vsync)
>(II) intel(0):                 LVDS: 0x42000300 (disabled, pipe B, 18 bit, 1 channel)
>(II) intel(0):                 DVOA: 0x00000000 (disabled, pipe A, no stall, -hsync, -vsync)
>(II) intel(0):                 DVOB: 0x0008001c (disabled, pipe A, no stall, +hsync, +vsync)
>(II) intel(0):                 DVOC: 0x00080018 (disabled, pipe A, no stall, +hsync, +vsync)
>(II) intel(0):          DVOA_SRCDIM: 0x00000000
>(II) intel(0):          DVOB_SRCDIM: 0x00000000
>(II) intel(0):          DVOC_SRCDIM: 0x00000000
>(II) intel(0):           PP_CONTROL: 0x00000002 (power target: off)
>(II) intel(0):            PP_STATUS: 0x00000000 (off, not ready, sequencing idle)
>(II) intel(0):         PFIT_CONTROL: 0x00000000
>(II) intel(0):      PFIT_PGM_RATIOS: 0x00000000
>(II) intel(0):      PORT_HOTPLUG_EN: 0x00000020
>(II) intel(0):    PORT_HOTPLUG_STAT: 0x00000b00
>(II) intel(0):             DSPACNTR: 0xd8000400 (enabled, pipe A)
>(II) intel(0):           DSPASTRIDE: 0x00000a00 (2560 bytes)
>(II) intel(0):              DSPAPOS: 0x00000000 (0, 0)
>(II) intel(0):             DSPASIZE: 0x00000000 (1, 1)
>(II) intel(0):             DSPABASE: 0x00000000
>(II) intel(0):             DSPASURF: 0x00700000
>(II) intel(0):          DSPATILEOFF: 0x00000000
>(II) intel(0):            PIPEACONF: 0xc0000000 (enabled, active)
>(II) intel(0):             PIPEASRC: 0x027f01df (640, 480)
>(II) intel(0):            PIPEASTAT: 0x80020207 (status: FIFO_UNDERRUN VBLANK_INT_ENABLE VSYNC_INT_STATUS SVBLANK_INT_STATUS VBLANK_INT_STATUS OREG_UPDATE_STATUS)
>(II) intel(0):                 FPA0: 0x00020d07 (n = 2, m1 = 13, m2 = 7)
>(II) intel(0):                 FPA1: 0x00031108 (n = 3, m1 = 17, m2 = 8)
>(II) intel(0):               DPLL_A: 0x94800c00 (enabled, non-dvo, default clock, DAC/serial mode, p1 = 8, p2 = 10)
>(II) intel(0):            DPLL_A_MD: 0x00000000
>(II) intel(0):             HTOTAL_A: 0x031f027f (640 active, 800 total)
>(II) intel(0):             HBLANK_A: 0x031f027f (640 start, 800 end)
>(II) intel(0):              HSYNC_A: 0x02ef028f (656 start, 752 end)
>(II) intel(0):             VTOTAL_A: 0x020c01df (480 active, 525 total)
>(II) intel(0):             VBLANK_A: 0x020c01df (480 start, 525 end)
>(II) intel(0):              VSYNC_A: 0x01eb01e9 (490 start, 492 end)
>(II) intel(0):            BCLRPAT_A: 0x00000000
>(II) intel(0):         VSYNCSHIFT_A: 0x00000000
>(II) intel(0):             DSPBCNTR: 0x01000000 (disabled, pipe B)
>(II) intel(0):           DSPBSTRIDE: 0x00000000 (0 bytes)
>(II) intel(0):              DSPBPOS: 0x00000000 (0, 0)
>(II) intel(0):             DSPBSIZE: 0x00000000 (1, 1)
>(II) intel(0):             DSPBBASE: 0x00000000
>(II) intel(0):             DSPBSURF: 0x00000000
>(II) intel(0):          DSPBTILEOFF: 0x00000000
>(II) intel(0):            PIPEBCONF: 0x00000000 (disabled, inactive)
>(II) intel(0):             PIPEBSRC: 0x027f01df (640, 480)
>(II) intel(0):            PIPEBSTAT: 0x00020000 (status: VBLANK_INT_ENABLE)
>(II) intel(0):                 FPB0: 0x00031108 (n = 3, m1 = 17, m2 = 8)
>(II) intel(0):                 FPB1: 0x00031108 (n = 3, m1 = 17, m2 = 8)
>(II) intel(0):               DPLL_B: 0x04800c00 (disabled, non-dvo, VGA, default clock, DAC/serial mode, p1 = 8, p2 = 10)
>(II) intel(0):            DPLL_B_MD: 0x00000303
>(II) intel(0):             HTOTAL_B: 0x031f027f (640 active, 800 total)
>(II) intel(0):             HBLANK_B: 0x03170287 (648 start, 792 end)
>(II) intel(0):              HSYNC_B: 0x02ef028f (656 start, 752 end)
>(II) intel(0):             VTOTAL_B: 0x020c01df (480 active, 525 total)
>(II) intel(0):             VBLANK_B: 0x020401e7 (488 start, 517 end)
>(II) intel(0):              VSYNC_B: 0x01eb01e9 (490 start, 492 end)
>(II) intel(0):            BCLRPAT_B: 0x00000000
>(II) intel(0):         VSYNCSHIFT_B: 0x00000000
>(II) intel(0):    VCLK_DIVISOR_VGA0: 0x00031108
>(II) intel(0):    VCLK_DIVISOR_VGA1: 0x00031406
>(II) intel(0):        VCLK_POST_DIV: 0x00020002
>(II) intel(0):             VGACNTRL: 0x80000000 (disabled)
>(II) intel(0):               TV_CTL: 0x00000010
>(II) intel(0):               TV_DAC: 0x70000000
>(II) intel(0):             TV_CSC_Y: 0x00000000
>(II) intel(0):            TV_CSC_Y2: 0x00000000
>(II) intel(0):             TV_CSC_U: 0x00000000
>(II) intel(0):            TV_CSC_U2: 0x00000000
>(II) intel(0):             TV_CSC_V: 0x00000000
>(II) intel(0):            TV_CSC_V2: 0x00000000
>(II) intel(0):         TV_CLR_KNOBS: 0x00000000
>(II) intel(0):         TV_CLR_LEVEL: 0x00000000
>(II) intel(0):           TV_H_CTL_1: 0x00000000
>(II) intel(0):           TV_H_CTL_2: 0x00000000
>(II) intel(0):           TV_H_CTL_3: 0x00000000
>(II) intel(0):           TV_V_CTL_1: 0x00000000
>(II) intel(0):           TV_V_CTL_2: 0x00000000
>(II) intel(0):           TV_V_CTL_3: 0x00000000
>(II) intel(0):           TV_V_CTL_4: 0x00000000
>(II) intel(0):           TV_V_CTL_5: 0x00000000
>(II) intel(0):           TV_V_CTL_6: 0x00000000
>(II) intel(0):           TV_V_CTL_7: 0x00000000
>(II) intel(0):          TV_SC_CTL_1: 0x00000000
>(II) intel(0):          TV_SC_CTL_2: 0x00000000
>(II) intel(0):          TV_SC_CTL_3: 0x00000000
>(II) intel(0):           TV_WIN_POS: 0x00000000
>(II) intel(0):          TV_WIN_SIZE: 0x00000000
>(II) intel(0):      TV_FILTER_CTL_1: 0x00000000
>(II) intel(0):      TV_FILTER_CTL_2: 0x00000000
>(II) intel(0):      TV_FILTER_CTL_3: 0x00000000
>(II) intel(0):        TV_CC_CONTROL: 0x00000000
>(II) intel(0):           TV_CC_DATA: 0x00000000
>(II) intel(0):          TV_H_LUMA_0: 0x00000000
>(II) intel(0):         TV_H_LUMA_59: 0x00000000
>(II) intel(0):        TV_H_CHROMA_0: 0x00000000
>(II) intel(0):       TV_H_CHROMA_59: 0x00000000
>(II) intel(0):         FBC_CFB_BASE: 0x3f820000
>(II) intel(0):          FBC_LL_BASE: 0x3fe20006
>(II) intel(0):          FBC_CONTROL: 0x43e844e0
>(II) intel(0):          FBC_COMMAND: 0x00000000
>(II) intel(0):           FBC_STATUS: 0x20000000
>(II) intel(0):         FBC_CONTROL2: 0x00000002
>(II) intel(0):        FBC_FENCE_OFF: 0x00000000
>(II) intel(0):          FBC_MOD_NUM: 0x00000000
>(II) intel(0):              MI_MODE: 0x00000200
>(II) intel(0):         MI_ARB_STATE: 0x00000044
>(II) intel(0):       MI_RDRET_STATE: 0x00000000
>(II) intel(0):              ECOSKPD: 0x00000307
>(II) intel(0):                 DP_B: 0x00000000
>(II) intel(0):       DPB_AUX_CH_CTL: 0x00000000
>(II) intel(0):     DPB_AUX_CH_DATA1: 0x00000000
>(II) intel(0):     DPB_AUX_CH_DATA2: 0x00000000
>(II) intel(0):     DPB_AUX_CH_DATA3: 0x00000000
>(II) intel(0):     DPB_AUX_CH_DATA4: 0x00000000
>(II) intel(0):     DPB_AUX_CH_DATA5: 0x00000000
>(II) intel(0):                 DP_C: 0x00000000
>(II) intel(0):       DPC_AUX_CH_CTL: 0x00000000
>(II) intel(0):     DPC_AUX_CH_DATA1: 0x00000000
>(II) intel(0):     DPC_AUX_CH_DATA2: 0x00000000
>(II) intel(0):     DPC_AUX_CH_DATA3: 0x00000000
>(II) intel(0):     DPC_AUX_CH_DATA4: 0x00000000
>(II) intel(0):     DPC_AUX_CH_DATA5: 0x00000000
>(II) intel(0):                 DP_D: 0x00000000
>(II) intel(0):       DPD_AUX_CH_CTL: 0x00000000
>(II) intel(0):     DPD_AUX_CH_DATA1: 0x00000000
>(II) intel(0):     DPD_AUX_CH_DATA2: 0x00000000
>(II) intel(0):     DPD_AUX_CH_DATA3: 0x00000000
>(II) intel(0):     DPD_AUX_CH_DATA4: 0x00000000
>(II) intel(0):     DPD_AUX_CH_DATA5: 0x00000000
>(II) intel(0): pipe A dot 25200 n 2 m1 13 m2 7 p1 8 p2 10
>(II) intel(0): pipe B dot 25200 n 3 m1 17 m2 8 p1 8 p2 10
>(II) intel(0): DumpRegsEnd
>(II) intel(0): Output configuration:
>(II) intel(0):   Pipe A is on
>(II) intel(0):   Display plane A is now enabled and connected to pipe A.
>(II) intel(0):   Pipe B is off
>(II) intel(0):   Display plane B is now disabled and connected to pipe B.
>(II) intel(0):   Output VGA is connected to pipe A
>(II) intel(0):   Output TMDS-1 is connected to pipe none
>(II) intel(0): [drm] dma control initialized, using IRQ 20
>(II) intel(0): RandR 1.2 enabled, ignore the following RandR disabled message.
>(**) Option "dpms"
>(**) intel(0): DPMS enabled
>(II) intel(0): Set up textured video
>(II) intel(0): Set up overlay video
>(II) intel(0): direct rendering: Enabled
>(WW) intel(0): Option "PreferredMode" is not used
>(WW) intel(0): Option "Enable" is not used
>(--) RandR disabled
>(II) Initializing built-in extension MIT-SHM
>(II) Initializing built-in extension XInputExtension
>(II) Initializing built-in extension XTEST
>(II) Initializing built-in extension XKEYBOARD
>(II) Initializing built-in extension XC-APPGROUP
>(II) Initializing built-in extension XAccessControlExtension
>(II) Initializing built-in extension SECURITY
>(II) Initializing built-in extension XINERAMA
>(II) Initializing built-in extension XFIXES
>(II) Initializing built-in extension XFree86-Bigfont
>(II) Initializing built-in extension RENDER
>(II) Initializing built-in extension RANDR
>(II) Initializing built-in extension COMPOSITE
>(II) Initializing built-in extension DAMAGE
>(II) Initializing built-in extension XEVIE
>drmOpenDevice: node name is /dev/dri/card0
>drmOpenDevice: open result is 10, (OK)
>drmOpenByBusid: Searching for BusID pci:0000:00:02.0
>drmOpenDevice: node name is /dev/dri/card0
>drmOpenDevice: open result is 10, (OK)
>drmOpenByBusid: drmOpenMinor returns 10
>drmOpenByBusid: drmGetBusid reports pci:0000:00:02.0
>(WW) AIGLX: 3D driver claims to not support visual 0x23
>(WW) AIGLX: 3D driver claims to not support visual 0x24
>(WW) AIGLX: 3D driver claims to not support visual 0x25
>(WW) AIGLX: 3D driver claims to not support visual 0x26
>(WW) AIGLX: 3D driver claims to not support visual 0x27
>(WW) AIGLX: 3D driver claims to not support visual 0x28
>(WW) AIGLX: 3D driver claims to not support visual 0x29
>(WW) AIGLX: 3D driver claims to not support visual 0x2a
>(WW) AIGLX: 3D driver claims to not support visual 0x2b
>(WW) AIGLX: 3D driver claims to not support visual 0x2c
>(WW) AIGLX: 3D driver claims to not support visual 0x2d
>(WW) AIGLX: 3D driver claims to not support visual 0x2e
>(WW) AIGLX: 3D driver claims to not support visual 0x2f
>(WW) AIGLX: 3D driver claims to not support visual 0x30
>(WW) AIGLX: 3D driver claims to not support visual 0x31
>(WW) AIGLX: 3D driver claims to not support visual 0x32
>(II) AIGLX: Loaded and initialized /usr/lib/dri/i965_dri.so
>(II) GLX: Initialized DRI GL provider for screen 0
>(II) intel(0): Setting screen physical size to 216 x 162
>(**) Option "Protocol" "auto"
>(**) Option "Device" "/dev/null"
>(II) Mouse0: Setting mouse protocol to "PS/2"
>(**) Mouse0: Device: "/dev/null"
>(**) Mouse0: Protocol: "auto"
>(**) Option "CorePointer"
>(**) Mouse0: Core Pointer
>(**) Option "Device" "/dev/null"
>(==) Mouse0: Emulate3Buttons, Emulate3Timeout: 50
>(**) Mouse0: ZAxisMapping: buttons 4 and 5
>(**) Mouse0: Buttons: 9
>(**) Mouse0: Sensitivity: 1
>(**) Option "CoreKeyboard"
>(**) Keyboard0: Core Keyboard
>(**) Option "Protocol" "standard"
>(**) Keyboard0: Protocol: standard
>(**) Option "AutoRepeat" "500 30"
>(**) Option "XkbRules" "xorg"
>(**) Keyboard0: XkbRules: "xorg"
>(**) Option "XkbModel" "pc105"
>(**) Keyboard0: XkbModel: "pc105"
>(**) Option "XkbLayout" "us"
>(**) Keyboard0: XkbLayout: "us"
>(**) Option "CustomKeycodes" "off"
>(**) Keyboard0: CustomKeycodes disabled
>(II) XINPUT: Adding extended input device "Keyboard0" (type: KEYBOARD)
>(II) XINPUT: Adding extended input device "Mouse0" (type: MOUSE)
>(II) Mouse0: Setting mouse protocol to "PS/2"
>(EE) intel(0): underrun on pipe A!
>(EE) intel(0): underrun on pipe A!
>(EE) intel(0): underrun on pipe A!
>(EE) intel(0): underrun on pipe A!
>(EE) intel(0): underrun on pipe A!
>(EE) intel(0): underrun on pipe A!
>(EE) intel(0): underrun on pipe A!
>(EE) intel(0): underrun on pipe A!
>(EE) intel(0): underrun on pipe A!
>(EE) intel(0): underrun on pipe A!
>(EE) intel(0): underrun on pipe A!
>(EE) intel(0): underrun on pipe A!
>(EE) intel(0): underrun on pipe A!
>(EE) intel(0): underrun on pipe A!
>(EE) intel(0): underrun on pipe A!
>(EE) intel(0): underrun on pipe A!
>(EE) intel(0): underrun on pipe A!
>(EE) intel(0): underrun on pipe A!
>(EE) intel(0): underrun on pipe A!
>(EE) intel(0): underrun on pipe A!
>(EE) intel(0): underrun on pipe A!
>(EE) intel(0): underrun on pipe A!
>(EE) intel(0): underrun on pipe A!
>(EE) intel(0): underrun on pipe A!
>(EE) intel(0): underrun on pipe A!
>(EE) intel(0): underrun on pipe A!
>(EE) intel(0): underrun on pipe A!
>(EE) intel(0): underrun on pipe A!
>(EE) intel(0): underrun on pipe A!
>(EE) intel(0): underrun on pipe A!
>(EE) intel(0): underrun on pipe A!
>(EE) intel(0): underrun on pipe A!
>(EE) intel(0): underrun on pipe A!
>(EE) intel(0): underrun on pipe A!
>(EE) intel(0): underrun on pipe A!
>(EE) intel(0): underrun on pipe A!
>(EE) intel(0): underrun on pipe A!
>(EE) intel(0): underrun on pipe A!
>(EE) intel(0): underrun on pipe A!
>(EE) intel(0): underrun on pipe A!
>(EE) intel(0): underrun on pipe A!
>(EE) intel(0): underrun on pipe A!
>(EE) intel(0): underrun on pipe A!
>(EE) intel(0): underrun on pipe A!
>(EE) intel(0): underrun on pipe A!
>(EE) intel(0): underrun on pipe A!
>(EE) intel(0): underrun on pipe A!
>(EE) intel(0): underrun on pipe A!
>(EE) intel(0): underrun on pipe A!
>(EE) intel(0): underrun on pipe A!
>(EE) intel(0): underrun on pipe A!
>(EE) intel(0): underrun on pipe A!
>(EE) intel(0): underrun on pipe A!
>(EE) intel(0): underrun on pipe A!
>(EE) intel(0): underrun on pipe A!
>(EE) intel(0): underrun on pipe A!
>(EE) intel(0): underrun on pipe A!
>(EE) intel(0): underrun on pipe A!
>(EE) intel(0): underrun on pipe A!
>(EE) intel(0): underrun on pipe A!
>(EE) intel(0): underrun on pipe A!
>(EE) intel(0): underrun on pipe A!
>(EE) intel(0): underrun on pipe A!
>(EE) intel(0): underrun on pipe A!
>(EE) intel(0): underrun on pipe A!
>(EE) intel(0): underrun on pipe A!
>(EE) intel(0): underrun on pipe A!
>(EE) intel(0): underrun on pipe A!
>(EE) intel(0): underrun on pipe A!
>(EE) intel(0): underrun on pipe A!
>(EE) intel(0): underrun on pipe A!
>(EE) intel(0): underrun on pipe A!
>(EE) intel(0): underrun on pipe A!
>(EE) intel(0): underrun on pipe A!
>(EE) intel(0): underrun on pipe A!
>(EE) intel(0): underrun on pipe A!
>(EE) intel(0): underrun on pipe A!
>(EE) intel(0): underrun on pipe A!
>(EE) intel(0): underrun on pipe A!
>(EE) intel(0): underrun on pipe A!
>(EE) intel(0): underrun on pipe A!
>(EE) intel(0): underrun on pipe A!
>(EE) intel(0): underrun on pipe A!
>(EE) intel(0): underrun on pipe A!
>(EE) intel(0): underrun on pipe A!
>(EE) intel(0): underrun on pipe A!
>(EE) intel(0): underrun on pipe A!
>(EE) intel(0): underrun on pipe A!
>(EE) intel(0): underrun on pipe A!
>(EE) intel(0): underrun on pipe A!
>(EE) intel(0): underrun on pipe A!
>(EE) intel(0): underrun on pipe A!
>(EE) intel(0): underrun on pipe A!
>(EE) intel(0): underrun on pipe A!
>(EE) intel(0): underrun on pipe A!
>(EE) intel(0): underrun on pipe A!
>(EE) intel(0): underrun on pipe A!
>(EE) intel(0): underrun on pipe A!
>(EE) intel(0): underrun on pipe A!
>(EE) intel(0): underrun on pipe A!
>(EE) intel(0): underrun on pipe A!
>(EE) intel(0): underrun on pipe A!
>(EE) intel(0): underrun on pipe A!
>(EE) intel(0): underrun on pipe A!
>(EE) intel(0): underrun on pipe A!
>(EE) intel(0): underrun on pipe A!
>(EE) intel(0): underrun on pipe A!
>(EE) intel(0): underrun on pipe A!
>(EE) intel(0): underrun on pipe A!
>(EE) intel(0): underrun on pipe A!
>(EE) intel(0): underrun on pipe A!
>(EE) intel(0): underrun on pipe A!
>(EE) intel(0): underrun on pipe A!
>(EE) intel(0): underrun on pipe A!
>(EE) intel(0): underrun on pipe A!
>(EE) intel(0): underrun on pipe A!
>(EE) intel(0): underrun on pipe A!
>(EE) intel(0): underrun on pipe A!
>(EE) intel(0): underrun on pipe A!
>(EE) intel(0): underrun on pipe A!
>(EE) intel(0): underrun on pipe A!
>(EE) intel(0): underrun on pipe A!
>(EE) intel(0): underrun on pipe A!
>(EE) intel(0): underrun on pipe A!
>(EE) intel(0): underrun on pipe A!
>(EE) intel(0): underrun on pipe A!
>(EE) intel(0): underrun on pipe A!
>(EE) intel(0): underrun on pipe A!
>(EE) intel(0): underrun on pipe A!
>(EE) intel(0): underrun on pipe A!
>(EE) intel(0): underrun on pipe A!
>(EE) intel(0): underrun on pipe A!
>(EE) intel(0): underrun on pipe A!
>(EE) intel(0): underrun on pipe A!
>(EE) intel(0): underrun on pipe A!
>(EE) intel(0): underrun on pipe A!
>(EE) intel(0): underrun on pipe A!
>(EE) intel(0): underrun on pipe A!
>(EE) intel(0): underrun on pipe A!
>(EE) intel(0): underrun on pipe A!
>(EE) intel(0): underrun on pipe A!
>(EE) intel(0): underrun on pipe A!
>(EE) intel(0): underrun on pipe A!
>(EE) intel(0): underrun on pipe A!
>(EE) intel(0): underrun on pipe A!
>(EE) intel(0): underrun on pipe A!
>(EE) intel(0): underrun on pipe A!
>(EE) intel(0): underrun on pipe A!
>(EE) intel(0): underrun on pipe A!
>(EE) intel(0): underrun on pipe A!
>(EE) intel(0): underrun on pipe A!
>(EE) intel(0): underrun on pipe A!
>(EE) intel(0): underrun on pipe A!
>(EE) intel(0): underrun on pipe A!
>(EE) intel(0): underrun on pipe A!
>(EE) intel(0): underrun on pipe A!
>(EE) intel(0): underrun on pipe A!
>(EE) intel(0): underrun on pipe A!
>(EE) intel(0): underrun on pipe A!
>(EE) intel(0): underrun on pipe A!
>(EE) intel(0): underrun on pipe A!
>(EE) intel(0): underrun on pipe A!
>(EE) intel(0): underrun on pipe A!
>(EE) intel(0): underrun on pipe A!
>(EE) intel(0): underrun on pipe A!
>(II) intel(0): SDVOB: W: 05 00 00                   (SDVO_CMD_SET_ACTIVE_OUTPUTS)
>(II) intel(0): SDVOB: R:                         (Success)
>(II) intel(0): SDVOB: W: 05 00 00                   (SDVO_CMD_SET_ACTIVE_OUTPUTS)
>(II) intel(0): SDVOB: R:                         (Success)
>(II) intel(0): SDVOB: W: 11 01 00                   (SDVO_CMD_SET_TARGET_OUTPUT)
>(II) intel(0): SDVOB: R:                         (Success)
>(II) intel(0): SDVOB: W: 16 64 19 00 40 41 00 26 30 (SDVO_CMD_SET_OUTPUT_TIMINGS_PART1)
>(II) intel(0): SDVOB: R:                         (Success)
>(II) intel(0): SDVOB: W: 17 18 88 36 00 18 00 00 00 (SDVO_CMD_SET_OUTPUT_TIMINGS_PART2)
>(II) intel(0): SDVOB: R:                         (Success)
>(II) intel(0): SDVOB: W: 10 00                      (SDVO_CMD_SET_TARGET_INPUT)
>(II) intel(0): SDVOB: R:                         (Success)
>(II) intel(0): SDVOB: W: 14 64 19 00 40 41 00 26 30 (SDVO_CMD_SET_INPUT_TIMINGS_PART1)
>(II) intel(0): SDVOB: R:                         (Success)
>(II) intel(0): SDVOB: W: 15 18 88 36 00 18 00 00 00 (SDVO_CMD_SET_INPUT_TIMINGS_PART2)
>(II) intel(0): SDVOB: R:                         (Success)
>(II) intel(0): SDVOB: W: 21 01                      (SDVO_CMD_SET_CLOCK_RATE_MULT)
>(II) intel(0): SDVOB: R:                         (Success)
>(II) intel(0): SDVOB: W: 05 00 00                   (SDVO_CMD_SET_ACTIVE_OUTPUTS)
>(II) intel(0): SDVOB: R:                         (Success)
>(II) intel(0): Comparing regs from server start up to After LeaveVT
>(II) intel(0): DumpRegsBegin
>(II) intel(0):    VCLK_DIVISOR_VGA0: 0x00031108 (n = 3, m1 = 17, m2 = 8)
>(II) intel(0):    VCLK_DIVISOR_VGA1: 0x00031406 (n = 3, m1 = 20, m2 = 6)
>(II) intel(0):        VCLK_POST_DIV: 0x00020002 (vga0 p1 = 4, p2 = 2, vga1 p1 = 2, p2 = 2)
>(II) intel(0):            DPLL_TEST: 0x00010001 ()
>(II) intel(0):         CACHE_MODE_0: 0x00006800
>(II) intel(0):              D_STATE: 0x00000000
>(II) intel(0):        DSPCLK_GATE_D: 0x00001000 (clock gates disabled: DPLUNIT)
>(II) intel(0):       RENCLK_GATE_D1: 0x00000000
>(II) intel(0):       RENCLK_GATE_D2: 0x00000000
>(II) intel(0):                SDVOB: 0x0008001c (disabled, pipe A, stall disabled, detected)
>(II) intel(0):                SDVOC: 0x00080018 (disabled, pipe A, stall disabled, not detected)
>(II) intel(0):              SDVOUDI: 0x00000000
>(II) intel(0):               DSPARB: 0x00001d9c
>(II) intel(0):               DSPFW1: 0x3f880808
>(II) intel(0):               DSPFW2: 0x00000808
>(II) intel(0):               DSPFW3: 0x00000000
>(II) intel(0):                 ADPA: 0x80008000 (enabled, pipe A, -hsync, -vsync)
>(II) intel(0):                 LVDS: 0x42000300 (disabled, pipe B, 18 bit, 1 channel)
>(II) intel(0):                 DVOA: 0x00000000 (disabled, pipe A, no stall, -hsync, -vsync)
>(II) intel(0):                 DVOB: 0x0008001c (disabled, pipe A, no stall, +hsync, +vsync)
>(II) intel(0):                 DVOC: 0x00080018 (disabled, pipe A, no stall, +hsync, +vsync)
>(II) intel(0):          DVOA_SRCDIM: 0x00000000
>(II) intel(0):          DVOB_SRCDIM: 0x00000000
>(II) intel(0):          DVOC_SRCDIM: 0x00000000
>(II) intel(0):           PP_CONTROL: 0x00000002 (power target: off)
>(II) intel(0):            PP_STATUS: 0x00000000 (off, not ready, sequencing idle)
>(II) intel(0):         PFIT_CONTROL: 0x00000000
>(II) intel(0):      PFIT_PGM_RATIOS: 0x00000000
>(II) intel(0):      PORT_HOTPLUG_EN: 0x00000020
>(II) intel(0):    PORT_HOTPLUG_STAT: 0x00000b00
>(II) intel(0):             DSPACNTR: 0x48000000 (disabled, pipe A)
>(II) intel(0):           DSPASTRIDE: 0x00000280 (640 bytes)
>(II) intel(0):              DSPAPOS: 0x00000000 (0, 0)
>(II) intel(0):             DSPASIZE: 0x00000000 (1, 1)
>(II) intel(0):             DSPABASE: 0x00000000
>(II) intel(0):             DSPASURF: 0x00000000
>(II) intel(0):          DSPATILEOFF: 0x00000000
>(II) intel(0):            PIPEACONF: 0xc0000000 (enabled, active)
>(II) intel(0):             PIPEASRC: 0x027f01df (640, 480)
>(II) intel(0):            PIPEASTAT: 0x00020000 (status: VBLANK_INT_ENABLE)
>(II) intel(0):                 FPA0: 0x00031108 (n = 3, m1 = 17, m2 = 8)
>(II) intel(0):                 FPA1: 0x00031108 (n = 3, m1 = 17, m2 = 8)
>(II) intel(0):               DPLL_A: 0x84801a00 (enabled, non-dvo, VGA, default clock, DAC/serial mode, p1 = 8, p2 = 10)
>(II) intel(0):            DPLL_A_MD: 0x00000003
>(II) intel(0):             HTOTAL_A: 0x031f027f (640 active, 800 total)
>(II) intel(0):             HBLANK_A: 0x03170287 (648 start, 792 end)
>(II) intel(0):              HSYNC_A: 0x02ef028f (656 start, 752 end)
>(II) intel(0):             VTOTAL_A: 0x020c01df (480 active, 525 total)
>(II) intel(0):             VBLANK_A: 0x020401e7 (488 start, 517 end)
>(II) intel(0):              VSYNC_A: 0x01eb01e9 (490 start, 492 end)
>(II) intel(0):            BCLRPAT_A: 0x00000000
>(II) intel(0):         VSYNCSHIFT_A: 0x00000000
>(II) intel(0):             DSPBCNTR: 0x01000000 (disabled, pipe B)
>(II) intel(0):           DSPBSTRIDE: 0x00000000 (0 bytes)
>(II) intel(0):              DSPBPOS: 0x00000000 (0, 0)
>(II) intel(0):             DSPBSIZE: 0x00000000 (1, 1)
>(II) intel(0):             DSPBBASE: 0x00000000
>(II) intel(0):             DSPBSURF: 0x00000000
>(II) intel(0):          DSPBTILEOFF: 0x00000000
>(II) intel(0):            PIPEBCONF: 0x00000000 (disabled, inactive)
>(II) intel(0):             PIPEBSRC: 0x027f01df (640, 480)
>(II) intel(0):            PIPEBSTAT: 0x00020000 (status: VBLANK_INT_ENABLE)
>(II) intel(0):                 FPB0: 0x00031108 (n = 3, m1 = 17, m2 = 8)
>(II) intel(0):                 FPB1: 0x00031108 (n = 3, m1 = 17, m2 = 8)
>(II) intel(0):               DPLL_B: 0x04800c00 (disabled, non-dvo, VGA, default clock, DAC/serial mode, p1 = 8, p2 = 10)
>(II) intel(0):            DPLL_B_MD: 0x00000303
>(II) intel(0):             HTOTAL_B: 0x031f027f (640 active, 800 total)
>(II) intel(0):             HBLANK_B: 0x03170287 (648 start, 792 end)
>(II) intel(0):              HSYNC_B: 0x02ef028f (656 start, 752 end)
>(II) intel(0):             VTOTAL_B: 0x020c01df (480 active, 525 total)
>(II) intel(0):             VBLANK_B: 0x020401e7 (488 start, 517 end)
>(II) intel(0):              VSYNC_B: 0x01eb01e9 (490 start, 492 end)
>(II) intel(0):            BCLRPAT_B: 0x00000000
>(II) intel(0):         VSYNCSHIFT_B: 0x00000000
>(II) intel(0):    VCLK_DIVISOR_VGA0: 0x00031108
>(II) intel(0):    VCLK_DIVISOR_VGA1: 0x00031406
>(II) intel(0):        VCLK_POST_DIV: 0x00020002
>(II) intel(0):             VGACNTRL: 0x0020008e (enabled)
>(II) intel(0):               TV_CTL: 0x00000010
>(II) intel(0):               TV_DAC: 0x70000000
>(II) intel(0):             TV_CSC_Y: 0x00000000
>(II) intel(0):            TV_CSC_Y2: 0x00000000
>(II) intel(0):             TV_CSC_U: 0x00000000
>(II) intel(0):            TV_CSC_U2: 0x00000000
>(II) intel(0):             TV_CSC_V: 0x00000000
>(II) intel(0):            TV_CSC_V2: 0x00000000
>(II) intel(0):         TV_CLR_KNOBS: 0x00000000
>(II) intel(0):         TV_CLR_LEVEL: 0x00000000
>(II) intel(0):           TV_H_CTL_1: 0x00000000
>(II) intel(0):           TV_H_CTL_2: 0x00000000
>(II) intel(0):           TV_H_CTL_3: 0x00000000
>(II) intel(0):           TV_V_CTL_1: 0x00000000
>(II) intel(0):           TV_V_CTL_2: 0x00000000
>(II) intel(0):           TV_V_CTL_3: 0x00000000
>(II) intel(0):           TV_V_CTL_4: 0x00000000
>(II) intel(0):           TV_V_CTL_5: 0x00000000
>(II) intel(0):           TV_V_CTL_6: 0x00000000
>(II) intel(0):           TV_V_CTL_7: 0x00000000
>(II) intel(0):          TV_SC_CTL_1: 0x00000000
>(II) intel(0):          TV_SC_CTL_2: 0x00000000
>(II) intel(0):          TV_SC_CTL_3: 0x00000000
>(II) intel(0):           TV_WIN_POS: 0x00000000
>(II) intel(0):          TV_WIN_SIZE: 0x00000000
>(II) intel(0):      TV_FILTER_CTL_1: 0x00000000
>(II) intel(0):      TV_FILTER_CTL_2: 0x00000000
>(II) intel(0):      TV_FILTER_CTL_3: 0x00000000
>(II) intel(0):        TV_CC_CONTROL: 0x00000000
>(II) intel(0):           TV_CC_DATA: 0x00000000
>(II) intel(0):          TV_H_LUMA_0: 0x00000000
>(II) intel(0):         TV_H_LUMA_59: 0x00000000
>(II) intel(0):        TV_H_CHROMA_0: 0x00000000
>(II) intel(0):       TV_H_CHROMA_59: 0x00000000
>(II) intel(0):         FBC_CFB_BASE: 0x00000000
>(II) intel(0):          FBC_LL_BASE: 0x00000000
>(II) intel(0):          FBC_CONTROL: 0x00000000
>(II) intel(0):          FBC_COMMAND: 0x00000000
>(II) intel(0):           FBC_STATUS: 0x20000000
>(II) intel(0):         FBC_CONTROL2: 0x00000000
>(II) intel(0):        FBC_FENCE_OFF: 0x00000000
>(II) intel(0):          FBC_MOD_NUM: 0x00000000
>(II) intel(0):              MI_MODE: 0x00000200
>(II) intel(0):         MI_ARB_STATE: 0x00000044
>(II) intel(0):       MI_RDRET_STATE: 0x00000000
>(II) intel(0):              ECOSKPD: 0x00000307
>(II) intel(0):                 DP_B: 0x00000000
>(II) intel(0):       DPB_AUX_CH_CTL: 0x00000000
>(II) intel(0):     DPB_AUX_CH_DATA1: 0x00000000
>(II) intel(0):     DPB_AUX_CH_DATA2: 0x00000000
>(II) intel(0):     DPB_AUX_CH_DATA3: 0x00000000
>(II) intel(0):     DPB_AUX_CH_DATA4: 0x00000000
>(II) intel(0):     DPB_AUX_CH_DATA5: 0x00000000
>(II) intel(0):                 DP_C: 0x00000000
>(II) intel(0):       DPC_AUX_CH_CTL: 0x00000000
>(II) intel(0):     DPC_AUX_CH_DATA1: 0x00000000
>(II) intel(0):     DPC_AUX_CH_DATA2: 0x00000000
>(II) intel(0):     DPC_AUX_CH_DATA3: 0x00000000
>(II) intel(0):     DPC_AUX_CH_DATA4: 0x00000000
>(II) intel(0):     DPC_AUX_CH_DATA5: 0x00000000
>(II) intel(0):                 DP_D: 0x00000000
>(II) intel(0):       DPD_AUX_CH_CTL: 0x00000000
>(II) intel(0):     DPD_AUX_CH_DATA1: 0x00000000
>(II) intel(0):     DPD_AUX_CH_DATA2: 0x00000000
>(II) intel(0):     DPD_AUX_CH_DATA3: 0x00000000
>(II) intel(0):     DPD_AUX_CH_DATA4: 0x00000000
>(II) intel(0):     DPD_AUX_CH_DATA5: 0x00000000
>(II) intel(0): SDVO phase shift 13 out of range -- probobly not an issue.
>(II) intel(0): pipe A dot 25200 n 3 m1 17 m2 8 p1 8 p2 10
>(II) intel(0): pipe B dot 25200 n 3 m1 17 m2 8 p1 8 p2 10
>(II) intel(0): DumpRegsEnd
>(II) intel(0): xf86UnbindGARTMemory: unbind key 0
>(II) intel(0): xf86UnbindGARTMemory: unbind key 1
>(II) intel(0): xf86UnbindGARTMemory: unbind key 2
>(II) intel(0): xf86UnbindGARTMemory: unbind key 3
>(II) intel(0): xf86UnbindGARTMemory: unbind key 4
>(II) intel(0): [drm] removed 1 reserved context for kernel
>(II) intel(0): [drm] unmapping 8192 bytes of SAREA 0xf8a24000 at 0xb7f98000
>(II) intel(0): [drm] Closed DRM master.

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Attachments on bug 16833: 17851 | 17852 | 17931 | 17955 | 18003 | 18004

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