Attachment 18339 Details for Bug 17178 – run intel_reg_dumper after S3 resume

run intel_reg_dumper after S3 resume

intel_reg_dumper.afterS3resume.log (text/x-log), 6.97 KB, created by joeyli.tw on 2008-08-17 20:39:19 UTC

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Creator: joeyli.tw

Created: 2008-08-17 20:39:19 UTC

Size: 6.97 KB

patch

obsolete

>(II): DumpRegsBegin
>(II):    VCLK_DIVISOR_VGA0: 0x00031108 (n = 3, m1 = 17, m2 = 8)
>(II):    VCLK_DIVISOR_VGA1: 0x00031406 (n = 3, m1 = 20, m2 = 6)
>(II):        VCLK_POST_DIV: 0x00020002 (vga0 p1 = 4, p2 = 2, vga1 p1 = 2, p2 = 2)
>(II):            DPLL_TEST: 0x00010001 ()
>(II):         CACHE_MODE_0: 0x00006820
>(II):              D_STATE: 0x00000000
>(II):        DSPCLK_GATE_D: 0x1000000c (clock gates disabled: VRHUNIT OVRUNIT OVCUNIT)
>(II):       RENCLK_GATE_D1: 0x00000000
>(II):       RENCLK_GATE_D2: 0x00000000
>(II):                SDVOB: 0x00000018 (disabled, pipe A, stall disabled, not detected)
>(II):                SDVOC: 0x00000018 (disabled, pipe A, stall disabled, not detected)
>(II):              SDVOUDI: 0x00000000
>(II):               DSPARB: 0x00000000
>(II):               DSPFW1: 0x3f8f0f0f
>(II):               DSPFW2: 0x150f0f0f
>(II):               DSPFW3: 0x00000000
>(II):                 ADPA: 0x40008c18 (disabled, pipe B, +hsync, +vsync)
>(II):                 LVDS: 0xc2008300 (enabled, pipe B, 18 bit, 1 channel)
>(II):                 DVOA: 0x00000000 (disabled, pipe A, no stall, -hsync, -vsync)
>(II):                 DVOB: 0x00000018 (disabled, pipe A, no stall, +hsync, +vsync)
>(II):                 DVOC: 0x00000018 (disabled, pipe A, no stall, +hsync, +vsync)
>(II):          DVOA_SRCDIM: 0x00000000
>(II):          DVOB_SRCDIM: 0x00000000
>(II):          DVOC_SRCDIM: 0x00000000
>(II):           PP_CONTROL: 0x00000001 (power target: on)
>(II):            PP_STATUS: 0xc0000008 (on, ready, sequencing idle)
>(II):         PFIT_CONTROL: 0x00000000
>(II):      PFIT_PGM_RATIOS: 0x0c000a00
>(II):      PORT_HOTPLUG_EN: 0x00000020
>(II):    PORT_HOTPLUG_STAT: 0x00000000
>(II):             DSPACNTR: 0x00000000 (disabled, pipe A)
>(II):           DSPASTRIDE: 0x00000000 (0 bytes)
>(II):              DSPAPOS: 0x00000000 (0, 0)
>(II):             DSPASIZE: 0x00000000 (1, 1)
>(II):             DSPABASE: 0x00000000
>(II):             DSPASURF: 0x00000000
>(II):          DSPATILEOFF: 0x00000000
>(II):            PIPEACONF: 0x00000000 (disabled, inactive)
>(II):             PIPEASRC: 0x027f01df (640, 480)
>(II):            PIPEASTAT: 0x00020000 (status: VBLANK_INT_ENABLE)
>(II):                 FPA0: 0x00031108 (n = 3, m1 = 17, m2 = 8)
>(II):                 FPA1: 0x00031108 (n = 3, m1 = 17, m2 = 8)
>(II):               DPLL_A: 0x04020c00 (disabled, non-dvo, VGA, default clock, DAC/serial mode, p1 = 2, p2 = 10)
>(II):            DPLL_A_MD: 0x00000003
>(II):             HTOTAL_A: 0x031f027f (640 active, 800 total)
>(II):             HBLANK_A: 0x03170287 (648 start, 792 end)
>(II):              HSYNC_A: 0x02ef028f (656 start, 752 end)
>(II):             VTOTAL_A: 0x020c01df (480 active, 525 total)
>(II):             VBLANK_A: 0x020401e7 (488 start, 517 end)
>(II):              VSYNC_A: 0x01eb01e9 (490 start, 492 end)
>(II):            BCLRPAT_A: 0x00000000
>(II):         VSYNCSHIFT_A: 0x00000000
>(II):             DSPBCNTR: 0xd9000400 (enabled, pipe B)
>(II):           DSPBSTRIDE: 0x00001400 (5120 bytes)
>(II):              DSPBPOS: 0x00000000 (0, 0)
>(II):             DSPBSIZE: 0x00000000 (1, 1)
>(II):             DSPBBASE: 0x00000000
>(II):             DSPBSURF: 0x00200000
>(II):          DSPBTILEOFF: 0x00000000
>(II):            PIPEBCONF: 0xc0000000 (enabled, active)
>(II):             PIPEBSRC: 0x04ff031f (1280, 800)
>(II):            PIPEBSTAT: 0x00020206 (status: VBLANK_INT_ENABLE VSYNC_INT_STATUS SVBLANK_INT_STATUS VBLANK_INT_STATUS)
>(II):                 FPB0: 0x00031009 (n = 3, m1 = 16, m2 = 9)
>(II):                 FPB1: 0x00031108 (n = 3, m1 = 17, m2 = 8)
>(II):               DPLL_B: 0x98026000 (enabled, non-dvo, spread spectrum clock, LVDS mode, p1 = 2, p2 = 14)
>(II):            DPLL_B_MD: 0x00000000
>(II):             HTOTAL_B: 0x057f04ff (1280 active, 1408 total)
>(II):             HBLANK_B: 0x057f04ff (1280 start, 1408 end)
>(II):              HSYNC_B: 0x05340514 (1301 start, 1333 end)
>(II):             VTOTAL_B: 0x032f031f (800 active, 816 total)
>(II):             VBLANK_B: 0x032f031f (800 start, 816 end)
>(II):              VSYNC_B: 0x03270322 (803 start, 808 end)
>(II):            BCLRPAT_B: 0x00000000
>(II):         VSYNCSHIFT_B: 0x00000000
>(II):    VCLK_DIVISOR_VGA0: 0x00031108
>(II):    VCLK_DIVISOR_VGA1: 0x00031406
>(II):        VCLK_POST_DIV: 0x00020002
>(II):             VGACNTRL: 0x80000000 (disabled)
>(II):               TV_CTL: 0x00000010
>(II):               TV_DAC: 0x70000000
>(II):             TV_CSC_Y: 0x00000000
>(II):            TV_CSC_Y2: 0x00000000
>(II):             TV_CSC_U: 0x00000000
>(II):            TV_CSC_U2: 0x00000000
>(II):             TV_CSC_V: 0x00000000
>(II):            TV_CSC_V2: 0x00000000
>(II):         TV_CLR_KNOBS: 0x00000000
>(II):         TV_CLR_LEVEL: 0x00000000
>(II):           TV_H_CTL_1: 0x00000000
>(II):           TV_H_CTL_2: 0x00000000
>(II):           TV_H_CTL_3: 0x00000000
>(II):           TV_V_CTL_1: 0x00000000
>(II):           TV_V_CTL_2: 0x00000000
>(II):           TV_V_CTL_3: 0x00000000
>(II):           TV_V_CTL_4: 0x00000000
>(II):           TV_V_CTL_5: 0x00000000
>(II):           TV_V_CTL_6: 0x00000000
>(II):           TV_V_CTL_7: 0x00000000
>(II):          TV_SC_CTL_1: 0x00000000
>(II):          TV_SC_CTL_2: 0x00000000
>(II):          TV_SC_CTL_3: 0x00000000
>(II):           TV_WIN_POS: 0x00000000
>(II):          TV_WIN_SIZE: 0x00000000
>(II):      TV_FILTER_CTL_1: 0x00000000
>(II):      TV_FILTER_CTL_2: 0x00000000
>(II):      TV_FILTER_CTL_3: 0x00000000
>(II):        TV_CC_CONTROL: 0x00000000
>(II):           TV_CC_DATA: 0x00000000
>(II):          TV_H_LUMA_0: 0x00000000
>(II):         TV_H_LUMA_59: 0x00000000
>(II):        TV_H_CHROMA_0: 0x00000000
>(II):       TV_H_CHROMA_59: 0x00000000
>(II):         FBC_CFB_BASE: 0x00000000
>(II):          FBC_LL_BASE: 0x00000000
>(II):          FBC_CONTROL: 0x00000000
>(II):          FBC_COMMAND: 0x00000000
>(II):           FBC_STATUS: 0x00000000
>(II):         FBC_CONTROL2: 0x00000000
>(II):        FBC_FENCE_OFF: 0xbb006e00
>(II):          FBC_MOD_NUM: 0x00000000
>(II):              MI_MODE: 0x00000200
>(II):         MI_ARB_STATE: 0x00000040
>(II):       MI_RDRET_STATE: 0x00000000
>(II):              ECOSKPD: 0x00000307
>(II):                 DP_B: 0x00000018
>(II):       DPB_AUX_CH_CTL: 0x00050000
>(II):     DPB_AUX_CH_DATA1: 0x00000000
>(II):     DPB_AUX_CH_DATA2: 0x00000000
>(II):     DPB_AUX_CH_DATA3: 0x00000000
>(II):     DPB_AUX_CH_DATA4: 0x00000000
>(II):     DPB_AUX_CH_DATA5: 0x00000000
>(II):                 DP_C: 0x00000018
>(II):       DPC_AUX_CH_CTL: 0x00050000
>(II):     DPC_AUX_CH_DATA1: 0x00000000
>(II):     DPC_AUX_CH_DATA2: 0x00000000
>(II):     DPC_AUX_CH_DATA3: 0x00000000
>(II):     DPC_AUX_CH_DATA4: 0x00000000
>(II):     DPC_AUX_CH_DATA5: 0x00000000
>(II):                 DP_D: 0x0000001c
>(II):       DPD_AUX_CH_CTL: 0x00050000
>(II):     DPD_AUX_CH_DATA1: 0x00000000
>(II):     DPD_AUX_CH_DATA2: 0x00000000
>(II):     DPD_AUX_CH_DATA3: 0x00000000
>(II):     DPD_AUX_CH_DATA4: 0x00000000
>(II):     DPD_AUX_CH_DATA5: 0x00000000
>(II): pipe A dot 100800 n 3 m1 17 m2 8 p1 2 p2 10
>(II): SDVO phase shift 0 out of range -- probobly not an issue.
>(II): pipe B dot 72142 n 3 m1 16 m2 9 p1 2 p2 14
>(II): DumpRegsEnd

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Attachments on bug 17178: 18333 | 18334 | 18335 | 18336 | 18337 | 18338 | 18339 | 18340 | 18763 | 19082

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