Attachment 20745 Details for Bug 16702 – output from intel_reg_dumper after plugging in the VGA cable and setting the monitor to 1024x768@60hz

output from intel_reg_dumper after plugging in the VGA cable and setting the monitor to 1024x768@60hz

intel_reg_dumper-after_pluggin_CRT_and_setting_mode_1024x768-60hz.txt (text/plain), 7.71 KB, created by Vincenzo Ciancia on 2008-12-02 06:50:45 UTC

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Creator: Vincenzo Ciancia

Created: 2008-12-02 06:50:45 UTC

Size: 7.71 KB

patch

obsolete

>(II): DumpRegsBegin
>(II):            CHDECMISC: 0x22b97428 (XOR bank/rank, ch2 enh disabled, ch1 enh enabled, ch0 enh disabled, flex disabled, ep not present)
>(II):               C0DRB0: 0x000f0002 (0x0002)
>(II):               C0DRB1: 0x0000000f (0x000f)
>(II):               C0DRB2: 0x00000000 (0x0000)
>(II):               C0DRB3: 0x01180000 (0x0000)
>(II):               C1DRB0: 0x0e0d0d0c (0x0d0c)
>(II):               C1DRB1: 0x0f0e0e0d (0x0e0d)
>(II):               C1DRB2: 0x100f0f0e (0x0f0e)
>(II):               C1DRB3: 0x0e0d100f (0x100f)
>(II):              C0DRA01: 0x04020118 (0x0118)
>(II):              C0DRA23: 0x00000402 (0x0402)
>(II):              C1DRA01: 0x100f0e0d (0x0e0d)
>(II):              C1DRA23: 0x1211100f (0x100f)
>(II):    VCLK_DIVISOR_VGA0: 0x00031108 (n = 3, m1 = 17, m2 = 8)
>(II):    VCLK_DIVISOR_VGA1: 0x00031406 (n = 3, m1 = 20, m2 = 6)
>(II):        VCLK_POST_DIV: 0x00020002 (vga0 p1 = 4, p2 = 2, vga1 p1 = 2, p2 = 2)
>(II):            DPLL_TEST: 0x00010001 ()
>(II):         CACHE_MODE_0: 0x00006820
>(II):              D_STATE: 0x00000000
>(II):        DSPCLK_GATE_D: 0x00001000 (clock gates disabled: DPLUNIT)
>(II):       RENCLK_GATE_D1: 0x00000000
>(II):       RENCLK_GATE_D2: 0x00000000
>(II):                SDVOB: 0x00480004 (disabled, pipe A, stall disabled, detected)
>(II):                SDVOC: 0x00480000 (disabled, pipe A, stall disabled, not detected)
>(II):              SDVOUDI: 0x000000ff
>(II):               DSPARB: 0x00002f2f
>(II):               DSPFW1: 0x00000000
>(II):               DSPFW2: 0x00000000
>(II):               DSPFW3: 0x00000000
>(II):                 ADPA: 0x80000000 (enabled, pipe A, -hsync, -vsync)
>(II):                 LVDS: 0xc030033c (enabled, pipe B, 18 bit, 2 channels)
>(II):                 DVOA: 0x00000000 (disabled, pipe A, no stall, -hsync, -vsync)
>(II):                 DVOB: 0x00480004 (disabled, pipe A, no stall, -hsync, -vsync)
>(II):                 DVOC: 0x00480000 (disabled, pipe A, no stall, -hsync, -vsync)
>(II):          DVOA_SRCDIM: 0x00000000
>(II):          DVOB_SRCDIM: 0x00000000
>(II):          DVOC_SRCDIM: 0x00000000
>(II):           PP_CONTROL: 0x00000001 (power target: on)
>(II):            PP_STATUS: 0xc0000008 (on, ready, sequencing idle)
>(II):         PP_ON_DELAYS: 0x01f40834
>(II):        PP_OFF_DELAYS: 0x0001000a
>(II):           PP_DIVISOR: 0x00270f0b
>(II):         PFIT_CONTROL: 0x80000668
>(II):      PFIT_PGM_RATIOS: 0x00000000
>(II):      PORT_HOTPLUG_EN: 0x00000020
>(II):    PORT_HOTPLUG_STAT: 0x00000b00
>(II):             DSPACNTR: 0xd8000000 (enabled, pipe A)
>(II):           DSPASTRIDE: 0x00002000 (8192 bytes)
>(II):              DSPAPOS: 0x00000000 (0, 0)
>(II):             DSPASIZE: 0x02ff03ff (1024, 768)
>(II):             DSPABASE: 0x01000000
>(II):             DSPASURF: 0x00000000
>(II):          DSPATILEOFF: 0x00000000
>(II):            PIPEACONF: 0x80000000 (enabled, single-wide)
>(II):             PIPEASRC: 0x03ff02ff (1024, 768)
>(II):            PIPEASTAT: 0x00020200 (status: VBLANK_INT_ENABLE VSYNC_INT_STATUS)
>(II):                 FPA0: 0x00010c09 (n = 1, m1 = 12, m2 = 9)
>(II):                 FPA1: 0x00031108 (n = 3, m1 = 17, m2 = 8)
>(II):               DPLL_A: 0x94080000 (enabled, non-dvo, default clock, DAC/serial mode, p1 = 4, p2 = 10, SDVO mult 1)
>(II):            DPLL_A_MD: 0x00000000
>(II):             HTOTAL_A: 0x053f03ff (1024 active, 1344 total)
>(II):             HBLANK_A: 0x053f03ff (1024 start, 1344 end)
>(II):              HSYNC_A: 0x049f0417 (1048 start, 1184 end)
>(II):             VTOTAL_A: 0x032502ff (768 active, 806 total)
>(II):             VBLANK_A: 0x032502ff (768 start, 806 end)
>(II):              VSYNC_A: 0x03080302 (771 start, 777 end)
>(II):            BCLRPAT_A: 0x00000000
>(II):         VSYNCSHIFT_A: 0x00000000
>(II):             DSPBCNTR: 0xd9000000 (enabled, pipe B)
>(II):           DSPBSTRIDE: 0x00002000 (8192 bytes)
>(II):              DSPBPOS: 0x00000000 (0, 0)
>(II):             DSPBSIZE: 0x02ff03ff (1024, 768)
>(II):             DSPBBASE: 0x01000000
>(II):             DSPBSURF: 0x00000000
>(II):          DSPBTILEOFF: 0x00000000
>(II):            PIPEBCONF: 0x80000000 (enabled, single-wide)
>(II):             PIPEBSRC: 0x03ff02ff (1024, 768)
>(II):            PIPEBSTAT: 0x00020000 (status: VBLANK_INT_ENABLE)
>(II):                 FPB0: 0x00031406 (n = 3, m1 = 20, m2 = 6)
>(II):                 FPB1: 0x00031108 (n = 3, m1 = 17, m2 = 8)
>(II):               DPLL_B: 0x99040000 (enabled, non-dvo, default clock, LVDS mode, p1 = 3, p2 = 7, SDVO mult 1)
>(II):            DPLL_B_MD: 0x00000000
>(II):             HTOTAL_B: 0x06930577 (1400 active, 1684 total)
>(II):             HBLANK_B: 0x06930577 (1400 start, 1684 end)
>(II):              HSYNC_B: 0x061305a3 (1444 start, 1556 end)
>(II):             VTOTAL_B: 0x04290419 (1050 active, 1066 total)
>(II):             VBLANK_B: 0x04290419 (1050 start, 1066 end)
>(II):              VSYNC_B: 0x041d041a (1051 start, 1054 end)
>(II):            BCLRPAT_B: 0x00000000
>(II):         VSYNCSHIFT_B: 0x00000000
>(II):    VCLK_DIVISOR_VGA0: 0x00031108
>(II):    VCLK_DIVISOR_VGA1: 0x00031406
>(II):        VCLK_POST_DIV: 0x00020002
>(II):             VGACNTRL: 0x80000000 (disabled)
>(II):               TV_CTL: 0x00000000
>(II):               TV_DAC: 0x70000000
>(II):             TV_CSC_Y: 0x00000000
>(II):            TV_CSC_Y2: 0x00000000
>(II):             TV_CSC_U: 0x00000000
>(II):            TV_CSC_U2: 0x00000000
>(II):             TV_CSC_V: 0x00000000
>(II):            TV_CSC_V2: 0x00000000
>(II):         TV_CLR_KNOBS: 0x00000000
>(II):         TV_CLR_LEVEL: 0x00000000
>(II):           TV_H_CTL_1: 0x00000000
>(II):           TV_H_CTL_2: 0x00000000
>(II):           TV_H_CTL_3: 0x00000000
>(II):           TV_V_CTL_1: 0x00000000
>(II):           TV_V_CTL_2: 0x00000000
>(II):           TV_V_CTL_3: 0x00000000
>(II):           TV_V_CTL_4: 0x00000000
>(II):           TV_V_CTL_5: 0x00000000
>(II):           TV_V_CTL_6: 0x00000000
>(II):           TV_V_CTL_7: 0x00000000
>(II):          TV_SC_CTL_1: 0x00000000
>(II):          TV_SC_CTL_2: 0x00000000
>(II):          TV_SC_CTL_3: 0x00000000
>(II):           TV_WIN_POS: 0x00000000
>(II):          TV_WIN_SIZE: 0x00000000
>(II):      TV_FILTER_CTL_1: 0x00000000
>(II):      TV_FILTER_CTL_2: 0x00000000
>(II):      TV_FILTER_CTL_3: 0x00000000
>(II):        TV_CC_CONTROL: 0x00000000
>(II):           TV_CC_DATA: 0x00000000
>(II):          TV_H_LUMA_0: 0x00000000
>(II):         TV_H_LUMA_59: 0x00000000
>(II):        TV_H_CHROMA_0: 0x00000000
>(II):       TV_H_CHROMA_59: 0x00000000
>(II):         FBC_CFB_BASE: 0x00000000
>(II):          FBC_LL_BASE: 0x00000000
>(II):          FBC_CONTROL: 0x00000000
>(II):          FBC_COMMAND: 0x00000000
>(II):           FBC_STATUS: 0x20000000
>(II):         FBC_CONTROL2: 0x00000000
>(II):        FBC_FENCE_OFF: 0x00000000
>(II):          FBC_MOD_NUM: 0x00000000
>(II):              MI_MODE: 0x00000200
>(II):         MI_ARB_STATE: 0x00000040
>(II):       MI_RDRET_STATE: 0x00000000
>(II):              ECOSKPD: 0x00000307
>(II):                 DP_B: 0x00000000
>(II):       DPB_AUX_CH_CTL: 0x00000000
>(II):     DPB_AUX_CH_DATA1: 0x00000000
>(II):     DPB_AUX_CH_DATA2: 0x00000000
>(II):     DPB_AUX_CH_DATA3: 0x00000000
>(II):     DPB_AUX_CH_DATA4: 0x00000000
>(II):     DPB_AUX_CH_DATA5: 0x00000000
>(II):                 DP_C: 0x00000000
>(II):       DPC_AUX_CH_CTL: 0x00000000
>(II):     DPC_AUX_CH_DATA1: 0x00000000
>(II):     DPC_AUX_CH_DATA2: 0x00000000
>(II):     DPC_AUX_CH_DATA3: 0x00000000
>(II):     DPC_AUX_CH_DATA4: 0x00000000
>(II):     DPC_AUX_CH_DATA5: 0x00000000
>(II):                 DP_D: 0x00000000
>(II):       DPD_AUX_CH_CTL: 0x00000000
>(II):     DPD_AUX_CH_DATA1: 0x00000000
>(II):     DPD_AUX_CH_DATA2: 0x00000000
>(II):     DPD_AUX_CH_DATA3: 0x00000000
>(II):     DPD_AUX_CH_DATA4: 0x00000000
>(II):     DPD_AUX_CH_DATA5: 0x00000000
>(II): pipe A dot 64800 n 1 m1 12 m2 9 p1 4 p2 10
>(II): pipe B dot 107885 n 3 m1 20 m2 6 p1 3 p2 7
>(II): DumpRegsEnd

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Attachments on bug 16702: 19202 | 19203 | 20743 | 20744 | 20745 | 21054 | 21055 | 22130 | 22180 | 23325 | 23326 | 23327

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