Attachment 20821 Details for Bug 18896 – intel_reg_dumper : started GDM

intel_reg_dumper : started GDM

dumpregs.in-gdm.txt (text/plain), 7.82 KB, created by Alexandre Rostovtsev on 2008-12-04 21:28:27 UTC

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Creator: Alexandre Rostovtsev

Created: 2008-12-04 21:28:27 UTC

Size: 7.82 KB

patch

obsolete

>(II): DumpRegsBegin
>(II):            CHDECMISC: 0x00000000 (none, ch2 enh disabled, ch1 enh disabled, ch0 enh disabled, flex disabled, ep not present)
>(II):               C0DRB0: 0x000f0002 (0x0002)
>(II):               C0DRB1: 0x0000000f (0x000f)
>(II):               C0DRB2: 0x00000000 (0x0000)
>(II):               C0DRB3: 0xe0000000 (0x0000)
>(II):               C1DRB0: 0x00000000 (0x0000)
>(II):               C1DRB1: 0x00000000 (0x0000)
>(II):               C1DRB2: 0x00000000 (0x0000)
>(II):               C1DRB3: 0x00000000 (0x0000)
>(II):              C0DRA01: 0x0007e000 (0xe000)
>(II):              C0DRA23: 0x00380007 (0x0007)
>(II):              C1DRA01: 0x00000000 (0x0000)
>(II):              C1DRA23: 0x00000000 (0x0000)
>(II):    VCLK_DIVISOR_VGA0: 0x00031108 (n = 3, m1 = 17, m2 = 8)
>(II):    VCLK_DIVISOR_VGA1: 0x00031406 (n = 3, m1 = 20, m2 = 6)
>(II):        VCLK_POST_DIV: 0x00020002 (vga0 p1 = 4, p2 = 2, vga1 p1 = 2, p2 = 2)
>(II):            DPLL_TEST: 0x00010001 ()
>(II):         CACHE_MODE_0: 0x00006820
>(II):              D_STATE: 0x00000000
>(II):        DSPCLK_GATE_D: 0x1004000c (clock gates disabled: VRHUNIT DSSUNIT OVRUNIT OVCUNIT)
>(II):       RENCLK_GATE_D1: 0x00000000
>(II):       RENCLK_GATE_D2: 0x000002c0
>(II):                SDVOB: 0x0000089c (disabled, pipe A, stall disabled, detected)
>(II):                SDVOC: 0x00000018 (disabled, pipe A, stall disabled, not detected)
>(II):              SDVOUDI: 0x00000000
>(II):               DSPARB: 0x00000000
>(II):               DSPFW1: 0x3f8f0f0f
>(II):               DSPFW2: 0x150f0f0f
>(II):               DSPFW3: 0x00000000
>(II):                 ADPA: 0x40000c00 (disabled, pipe B, -hsync, -vsync)
>(II):                 LVDS: 0xc2308300 (enabled, pipe B, 18 bit, 1 channel)
>(II):                 DVOA: 0x00000000 (disabled, pipe A, no stall, -hsync, -vsync)
>(II):                 DVOB: 0x0000089c (disabled, pipe A, no stall, +hsync, +vsync)
>(II):                 DVOC: 0x00000018 (disabled, pipe A, no stall, +hsync, +vsync)
>(II):          DVOA_SRCDIM: 0x00000000
>(II):          DVOB_SRCDIM: 0x00000000
>(II):          DVOC_SRCDIM: 0x00000000
>(II):           PP_CONTROL: 0x00000001 (power target: on)
>(II):            PP_STATUS: 0xc0000008 (on, ready, sequencing idle)
>(II):         PP_ON_DELAYS: 0x01c20834
>(II):        PP_OFF_DELAYS: 0x01c20834
>(II):           PP_DIVISOR: 0x003e7f05
>(II):         PFIT_CONTROL: 0x00000000
>(II):      PFIT_PGM_RATIOS: 0x0f5c0ccd
>(II):      PORT_HOTPLUG_EN: 0x38000120
>(II):    PORT_HOTPLUG_STAT: 0x18100400
>(II):             DSPACNTR: 0x58000400 (disabled, pipe A)
>(II):           DSPASTRIDE: 0x00001400 (5120 bytes)
>(II):              DSPAPOS: 0x00000000 (0, 0)
>(II):             DSPASIZE: 0x00000000 (1, 1)
>(II):             DSPABASE: 0x00000000
>(II):             DSPASURF: 0x03100000
>(II):          DSPATILEOFF: 0x00000000
>(II):            PIPEACONF: 0x00000000 (disabled, inactive)
>(II):             PIPEASRC: 0x027f01df (640, 480)
>(II):            PIPEASTAT: 0x00000000 (status:)
>(II):                 FPA0: 0x00021108 (n = 2, m1 = 17, m2 = 8)
>(II):                 FPA1: 0x00031108 (n = 3, m1 = 17, m2 = 8)
>(II):               DPLL_A: 0x14800000 (disabled, non-dvo, default clock, DAC/serial mode, p1 = 8, p2 = 10)
>(II):            DPLL_A_MD: 0x00000000
>(II):             HTOTAL_A: 0x033f027f (640 active, 832 total)
>(II):             HBLANK_A: 0x033f027f (640 start, 832 end)
>(II):              HSYNC_A: 0x02bf0297 (664 start, 704 end)
>(II):             VTOTAL_A: 0x020701df (480 active, 520 total)
>(II):             VBLANK_A: 0x020701df (480 start, 520 end)
>(II):              VSYNC_A: 0x01ea01e8 (489 start, 491 end)
>(II):            BCLRPAT_A: 0x00000000
>(II):         VSYNCSHIFT_A: 0x00000000
>(II):             DSPBCNTR: 0xd9000400 (enabled, pipe B)
>(II):           DSPBSTRIDE: 0x00001400 (5120 bytes)
>(II):              DSPBPOS: 0x00000000 (0, 0)
>(II):             DSPBSIZE: 0x00000000 (1, 1)
>(II):             DSPBBASE: 0x00000000
>(II):             DSPBSURF: 0x03100000
>(II):          DSPBTILEOFF: 0x00000000
>(II):            PIPEBCONF: 0xc0000000 (enabled, active)
>(II):             PIPEBSRC: 0x04ff031f (1280, 800)
>(II):            PIPEBSTAT: 0x00400206 (status: LBLC_EVENT_ENABLE VSYNC_INT_STATUS SVBLANK_INT_STATUS VBLANK_INT_STATUS)
>(II):                 FPB0: 0x00010d06 (n = 1, m1 = 13, m2 = 6)
>(II):                 FPB1: 0x00031108 (n = 3, m1 = 17, m2 = 8)
>(II):               DPLL_B: 0x98046000 (enabled, non-dvo, spread spectrum clock, LVDS mode, p1 = 3, p2 = 14)
>(II):            DPLL_B_MD: 0x00000000
>(II):             HTOTAL_B: 0x054904ff (1280 active, 1354 total)
>(II):             HBLANK_B: 0x054904ff (1280 start, 1354 end)
>(II):              HSYNC_B: 0x0529050b (1292 start, 1322 end)
>(II):             VTOTAL_B: 0x0329031f (800 active, 810 total)
>(II):             VBLANK_B: 0x0329031f (800 start, 810 end)
>(II):              VSYNC_B: 0x03230320 (801 start, 804 end)
>(II):            BCLRPAT_B: 0x00000000
>(II):         VSYNCSHIFT_B: 0x00000000
>(II):    VCLK_DIVISOR_VGA0: 0x00031108
>(II):    VCLK_DIVISOR_VGA1: 0x00031406
>(II):        VCLK_POST_DIV: 0x00020002
>(II):             VGACNTRL: 0x80000000 (disabled)
>(II):               TV_CTL: 0x000c00d0
>(II):               TV_DAC: 0x70000000
>(II):             TV_CSC_Y: 0x0332012d
>(II):            TV_CSC_Y2: 0x07d30104
>(II):             TV_CSC_U: 0x0733052d
>(II):            TV_CSC_U2: 0x05c70200
>(II):             TV_CSC_V: 0x0340030c
>(II):            TV_CSC_V2: 0x06d00200
>(II):         TV_CLR_KNOBS: 0x00404000
>(II):         TV_CLR_LEVEL: 0x010b00e1
>(II):           TV_H_CTL_1: 0x00400359
>(II):           TV_H_CTL_2: 0x80480022
>(II):           TV_H_CTL_3: 0x007c0344
>(II):           TV_V_CTL_1: 0x00f01415
>(II):           TV_V_CTL_2: 0x00060607
>(II):           TV_V_CTL_3: 0x80120001
>(II):           TV_V_CTL_4: 0x000900f0
>(II):           TV_V_CTL_5: 0x000a00f0
>(II):           TV_V_CTL_6: 0x000900f0
>(II):           TV_V_CTL_7: 0x000a00f0
>(II):          TV_SC_CTL_1: 0xc1710087
>(II):          TV_SC_CTL_2: 0x6b405140
>(II):          TV_SC_CTL_3: 0x00000000
>(II):           TV_WIN_POS: 0x00360024
>(II):          TV_WIN_SIZE: 0x02640198
>(II):      TV_FILTER_CTL_1: 0x8000085e
>(II):      TV_FILTER_CTL_2: 0x00012d2d
>(II):      TV_FILTER_CTL_3: 0x00009696
>(II):        TV_CC_CONTROL: 0x00000000
>(II):           TV_CC_DATA: 0x00000000
>(II):          TV_H_LUMA_0: 0xb1403000
>(II):         TV_H_LUMA_59: 0x0000b060
>(II):        TV_H_CHROMA_0: 0xb1403000
>(II):       TV_H_CHROMA_59: 0x0000b060
>(II):         FBC_CFB_BASE: 0x00000000
>(II):          FBC_LL_BASE: 0x00000000
>(II):          FBC_CONTROL: 0x20000082
>(II):          FBC_COMMAND: 0x08c80032
>(II):           FBC_STATUS: 0x00000000
>(II):         FBC_CONTROL2: 0x00000000
>(II):        FBC_FENCE_OFF: 0xc0029300
>(II):          FBC_MOD_NUM: 0x00000000
>(II):              MI_MODE: 0x00000200
>(II):         MI_ARB_STATE: 0x00000040
>(II):       MI_RDRET_STATE: 0x00000000
>(II):              ECOSKPD: 0x00000307
>(II):                 DP_B: 0x0000001c
>(II):       DPB_AUX_CH_CTL: 0x00050000
>(II):     DPB_AUX_CH_DATA1: 0x00000000
>(II):     DPB_AUX_CH_DATA2: 0x00000000
>(II):     DPB_AUX_CH_DATA3: 0x00000000
>(II):     DPB_AUX_CH_DATA4: 0x00000000
>(II):     DPB_AUX_CH_DATA5: 0x00000000
>(II):                 DP_C: 0x00000018
>(II):       DPC_AUX_CH_CTL: 0x00050000
>(II):     DPC_AUX_CH_DATA1: 0x00000000
>(II):     DPC_AUX_CH_DATA2: 0x00000000
>(II):     DPC_AUX_CH_DATA3: 0x00000000
>(II):     DPC_AUX_CH_DATA4: 0x00000000
>(II):     DPC_AUX_CH_DATA5: 0x00000000
>(II):                 DP_D: 0x0000001c
>(II):       DPD_AUX_CH_CTL: 0x00050000
>(II):     DPD_AUX_CH_DATA1: 0x00000000
>(II):     DPD_AUX_CH_DATA2: 0x00000000
>(II):     DPD_AUX_CH_DATA3: 0x00000000
>(II):     DPD_AUX_CH_DATA4: 0x00000000
>(II):     DPD_AUX_CH_DATA5: 0x00000000
>(II): SDVO phase shift 0 out of range -- probobly not an issue.
>(II): pipe A dot 31500 n 2 m1 17 m2 8 p1 8 p2 10
>(II): SDVO phase shift 0 out of range -- probobly not an issue.
>(II): pipe B dot 65873 n 1 m1 13 m2 6 p1 3 p2 14
>(II): DumpRegsEnd

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Attachments on bug 18896: 20821 | 20822 | 20823 | 20824 | 20825

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