Attachment 21449 Details for Bug 19261 – dmesg after startx

dmesg after startx

dmesg_after_startx (text/plain), 32.75 KB, created by Clemens Buchacher on 2008-12-23 10:30:17 UTC

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Description:

Filename:

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Creator: Clemens Buchacher

Created: 2008-12-23 10:30:17 UTC

Size: 32.75 KB

patch

obsolete

>[drm:drm_stub_open] 
>[drm:drm_open_helper] pid = 4424, minor = 0
>[drm:drm_addmap_core] offset = 0xce000000, size = 0x01000000, type = 1
>[drm:nouveau_init_card_mappings] regs mapped ok at 0xce000000
>[drm:drm_addmap_core] offset = 0xcc000000, size = 0x02000000, type = 1
>[drm:drm_addmap_core] offset = 0x00000000, size = 0x00002000, type = 2
>[drm:drm_addmap_core] 8192 13 ffffc2000037a000
>[drm:drm_setup] 
>[drm:drm_unlocked_ioctl] pid=4424, cmd=0xc0406400, nr=0x00, dev 0xe200, auth=1
>[drm:drm_unlocked_ioctl] pid=4424, cmd=0xc0406400, nr=0x00, dev 0xe200, auth=1
>[drm:drm_release] open_count = 1
>[drm:nouveau_fifo_cleanup] clearing FIFO enables from file_priv
>[drm:drm_release] pid = 4424, device = 0xe200, open_count = 1
>[drm:drm_fasync] fd = -1, device = 0xe200
>[drm:drm_lastclose] 
>[drm:nouveau_card_takedown] prev state = 0
>[drm:drm_lastclose] driver lastclose completed
>[drm:drm_lastclose] lastclose completed
>[drm:drm_stub_open] 
>[drm:drm_open_helper] pid = 4424, minor = 0
>[drm:drm_addmap_core] offset = 0xce000000, size = 0x01000000, type = 1
>[drm:nouveau_init_card_mappings] regs mapped ok at 0xce000000
>[drm:drm_addmap_core] offset = 0xcc000000, size = 0x02000000, type = 1
>[drm:drm_addmap_core] offset = 0x00000000, size = 0x00002000, type = 2
>[drm:drm_addmap_core] 8192 13 ffffc2000037a000
>[drm:drm_setup] 
>[drm:drm_unlocked_ioctl] pid=4424, cmd=0xc0106407, nr=0x07, dev 0xe200, auth=1
>[drm:drm_unlocked_ioctl] pid=4424, cmd=0xc0106401, nr=0x01, dev 0xe200, auth=1
>[drm:drm_unlocked_ioctl] pid=4424, cmd=0xc0106401, nr=0x01, dev 0xe200, auth=1
>[drm:drm_unlocked_ioctl] pid=4424, cmd=0xc0406400, nr=0x00, dev 0xe200, auth=1
>[drm:drm_unlocked_ioctl] pid=4424, cmd=0xc0406400, nr=0x00, dev 0xe200, auth=1
>[drm:drm_release] open_count = 1
>[drm:nouveau_fifo_cleanup] clearing FIFO enables from file_priv
>[drm:drm_release] pid = 4424, device = 0xe200, open_count = 1
>[drm:drm_fasync] fd = -1, device = 0xe200
>[drm:drm_lastclose] 
>[drm:nouveau_card_takedown] prev state = 0
>[drm:drm_lastclose] driver lastclose completed
>[drm:drm_lastclose] lastclose completed
>[drm:drm_stub_open] 
>[drm:drm_open_helper] pid = 4424, minor = 0
>[drm:drm_addmap_core] offset = 0xce000000, size = 0x01000000, type = 1
>[drm:nouveau_init_card_mappings] regs mapped ok at 0xce000000
>[drm:drm_addmap_core] offset = 0xcc000000, size = 0x02000000, type = 1
>[drm:drm_addmap_core] offset = 0x00000000, size = 0x00002000, type = 2
>[drm:drm_addmap_core] 8192 13 ffffc2000037a000
>[drm:drm_setup] 
>[drm:drm_unlocked_ioctl] pid=4424, cmd=0xc0406400, nr=0x00, dev 0xe200, auth=1
>[drm:drm_unlocked_ioctl] pid=4424, cmd=0xc0406400, nr=0x00, dev 0xe200, auth=1
>[drm:drm_release] open_count = 1
>[drm:nouveau_fifo_cleanup] clearing FIFO enables from file_priv
>[drm:drm_release] pid = 4424, device = 0xe200, open_count = 1
>[drm:drm_fasync] fd = -1, device = 0xe200
>[drm:drm_lastclose] 
>[drm:nouveau_card_takedown] prev state = 0
>[drm:drm_lastclose] driver lastclose completed
>[drm:drm_lastclose] lastclose completed
>[drm:drm_stub_open] 
>[drm:drm_open_helper] pid = 4424, minor = 0
>[drm:drm_addmap_core] offset = 0xce000000, size = 0x01000000, type = 1
>[drm:nouveau_init_card_mappings] regs mapped ok at 0xce000000
>[drm:drm_addmap_core] offset = 0xcc000000, size = 0x02000000, type = 1
>[drm:drm_addmap_core] offset = 0x00000000, size = 0x00002000, type = 2
>[drm:drm_addmap_core] 8192 13 ffffc2000037a000
>[drm:drm_setup] 
>[drm:drm_unlocked_ioctl] pid=4424, cmd=0xc0406400, nr=0x00, dev 0xe200, auth=1
>[drm:drm_unlocked_ioctl] pid=4424, cmd=0xc0406400, nr=0x00, dev 0xe200, auth=1
>[drm:drm_release] open_count = 1
>[drm:nouveau_fifo_cleanup] clearing FIFO enables from file_priv
>[drm:drm_release] pid = 4424, device = 0xe200, open_count = 1
>[drm:drm_fasync] fd = -1, device = 0xe200
>[drm:drm_lastclose] 
>[drm:nouveau_card_takedown] prev state = 0
>[drm:drm_lastclose] driver lastclose completed
>[drm:drm_lastclose] lastclose completed
>[drm:drm_stub_open] 
>[drm:drm_open_helper] pid = 4424, minor = 0
>[drm:drm_addmap_core] offset = 0xce000000, size = 0x01000000, type = 1
>[drm:nouveau_init_card_mappings] regs mapped ok at 0xce000000
>[drm:drm_addmap_core] offset = 0xcc000000, size = 0x02000000, type = 1
>[drm:drm_addmap_core] offset = 0x00000000, size = 0x00002000, type = 2
>[drm:drm_addmap_core] 8192 13 ffffc2000037a000
>[drm:drm_setup] 
>[drm:drm_unlocked_ioctl] pid=4424, cmd=0xc0106407, nr=0x07, dev 0xe200, auth=1
>[drm:drm_unlocked_ioctl] pid=4424, cmd=0xc0106401, nr=0x01, dev 0xe200, auth=1
>[drm:drm_unlocked_ioctl] pid=4424, cmd=0xc0106401, nr=0x01, dev 0xe200, auth=1
>[drm:drm_unlocked_ioctl] pid=4424, cmd=0xc0106407, nr=0x07, dev 0xe200, auth=1
>[drm:drm_unlocked_ioctl] pid=4424, cmd=0xc0286415, nr=0x15, dev 0xe200, auth=1
>[drm:drm_addmap_core] offset = 0x00000000, size = 0x00002000, type = 2
>[drm:drm_mmap_locked] start = 0x7ff4f668a000, end = 0x7ff4f668c000, page offset = 0x2efff
>[drm:drm_vm_open_locked] 0x7ff4f668a000,0x00002000
>[drm:drm_do_vm_shm_fault] shm_fault 0x0
>[drm:drm_do_vm_shm_fault] shm_fault 0x1000
>[drm:drm_unlocked_ioctl] pid=4424, cmd=0xc0286415, nr=0x15, dev 0xe200, auth=1
>[drm:drm_addmap_core] offset = 0xd0000000, size = 0x08000000, type = 0
>[drm:drm_unlocked_ioctl] pid=4424, cmd=0xc0106426, nr=0x26, dev 0xe200, auth=1
>[drm:drm_unlocked_ioctl] pid=4424, cmd=0xc0106426, nr=0x26, dev 0xe200, auth=1
>[drm:drm_unlocked_ioctl] pid=4424, cmd=0xc0086420, nr=0x20, dev 0xe200, auth=1
>[drm:drm_addctx] 1
>[drm:drm_unlocked_ioctl] pid=4424, cmd=0x40086422, nr=0x22, dev 0xe200, auth=1
>[drm:drm_unlocked_ioctl] pid=4424, cmd=0x4008642a, nr=0x2a, dev 0xe200, auth=1
>[drm:drm_lock] 1 (pid 4424) requests lock (0x00000000), flags = 0x00000000
>[drm:drm_lock] 1 has lock
>[drm:drm_fasync] fd = 8, device = 0xe200
>[drm:drm_unlocked_ioctl] pid=4424, cmd=0x6440, nr=0x40, dev 0xe200, auth=1
>[drm:nouveau_card_init] prev state = 0
>[drm:nouveau_gpuobj_early_init] 
>[drm:nv50_instmem_init]  Rsvd VRAM base: 0x0ff00000
>[drm:nv50_instmem_init]     VBIOS image: 0x0ffe0000
>[drm:nv50_instmem_init]   Aperture size: 32 MiB
>[drm:nv50_instmem_init]         PT size: 64 KiB
>[drm:nouveau_gpuobj_new_fake] p_offset=0x00000000 b_offset=0x0ff00000 size=0x00020000 flags=0x00000000
>[drm:nouveau_gpuobj_new_fake] gpuobj ffff88006c615bc0
>[drm:nouveau_gpuobj_ref_add] ch-1 h=0x00000000 gpuobj=ffff88006c615bc0
>[drm:nouveau_gpuobj_new_fake] p_offset=0x00000020 b_offset=0x0ff00020 size=0x00004000 flags=0x00000000
>[drm:nouveau_gpuobj_new_fake] gpuobj ffff88007e3517c0
>[drm:nouveau_gpuobj_ref_add] ch-1 h=0x00000000 gpuobj=ffff88007e3517c0
>[drm:nouveau_gpuobj_new_fake] p_offset=0x00000200 b_offset=0x0ff00200 size=0x00004000 flags=0x00000000
>[drm:nouveau_gpuobj_new_fake] gpuobj ffff88007f1472c0
>[drm:nouveau_gpuobj_new] ch0 size=65536 align=4096 flags=0x00000000
>[drm:nouveau_gpuobj_new] gpuobj ffff88006c6150c0
>[drm:nouveau_gpuobj_new] private heap
>[drm:nouveau_gpuobj_ref_add] ch-1 h=0x00000000 gpuobj=ffff88006c6150c0
>[drm:nouveau_gpuobj_new] ch0 size=24 align=16 flags=0x00000000
>[drm:nouveau_gpuobj_new] gpuobj ffff88006c6155c0
>[drm:nouveau_gpuobj_new] private heap
>[drm:nouveau_gpuobj_ref_add] ch0 h=0x00000000 gpuobj=ffff88006c6155c0
>[drm:nouveau_mem_init] Available VRAM: 261120KiB
>[drm:nouveau_gpuobj_new] ch-1 size=1048576 align=16 flags=0x00000007
>[drm:nouveau_gpuobj_new] gpuobj ffff88006c6158c0
>[drm:nouveau_gpuobj_new] global heap
>[drm:nouveau_mem_alloc] allocated 1048576 bytes at 0xfe00000 type=0x04000001
>[drm:nv50_instmem_bind] st=0x20000 sz=0x100000
>[drm:nv50_instmem_bind] pramin=0x20000, pte=256, pte_end=2304
>[drm:nv50_instmem_bind] first vram page: 0xfe00000
>[drm:drm_sg_alloc] 
>[drm:drm_sg_alloc] size=33554432 pages=8192
>[drm:drm_sg_alloc] handle  = 13afd200
>[drm:drm_sg_alloc] virtual = ffffc20013b01000
>[drm:nouveau_sgdma_populate] num_pages = 8192
>[drm:nouveau_sgdma_bind] pg=0x0 (0x0), cached=0
>[drm:nouveau_gpuobj_new] ch-1 size=65536 align=0 flags=0x00000003
>[drm:nouveau_gpuobj_new] gpuobj ffff88006c615d40
>[drm:nouveau_gpuobj_new] global heap
>[drm:nouveau_mem_alloc] allocated 65536 bytes at 0xfdf0000 type=0x04000001
>[drm:nv50_instmem_bind] st=0x120000 sz=0x10000
>[drm:nv50_instmem_bind] pramin=0x120000, pte=2304, pte_end=2432
>[drm:nv50_instmem_bind] first vram page: 0xfdf0000
>[drm:nouveau_gpuobj_init] 
>[drm:nv50_graph_init] 
>[drm:nv50_graph_init_reset] 
>[drm:nv50_graph_init_intr] 
>[drm:nv50_graph_init_regs__nv] 
>[drm:nv50_graph_init_regs] 
>[drm:nv50_graph_init_ctxctl] 
>[drm:nv50_fifo_init] 
>[drm:nv50_fifo_init_reset] 
>[drm:nv50_fifo_init_intr] 
>[drm:nouveau_gpuobj_new] ch-1 size=512 align=4096 flags=0x00000002
>[drm:nouveau_gpuobj_new] gpuobj ffff88006c615640
>[drm:nouveau_gpuobj_new] global heap
>[drm:nouveau_mem_alloc] allocated 65536 bytes at 0xfde0000 type=0x04000001
>[drm:nv50_instmem_bind] st=0x130000 sz=0x1000
>[drm:nv50_instmem_bind] pramin=0x130000, pte=2432, pte_end=2440
>[drm:nv50_instmem_bind] first vram page: 0xfde0000
>[drm:nouveau_gpuobj_ref_add] ch-1 h=0x00000000 gpuobj=ffff88006c615640
>[drm:nouveau_gpuobj_new] ch-1 size=512 align=4096 flags=0x00000002
>[drm:nouveau_gpuobj_new] gpuobj ffff88006c615240
>[drm:nouveau_gpuobj_new] global heap
>[drm:nouveau_mem_alloc] allocated 65536 bytes at 0xfdd0000 type=0x04000001
>[drm:nv50_instmem_bind] st=0x131000 sz=0x1000
>[drm:nv50_instmem_bind] pramin=0x131000, pte=2440, pte_end=2448
>[drm:nv50_instmem_bind] first vram page: 0xfdd0000
>[drm:nouveau_gpuobj_ref_add] ch-1 h=0x00000000 gpuobj=ffff88006c615240
>[drm:nv50_fifo_init_context_table] 
>[drm:nv50_fifo_channel_disable] ch0, nt=1
>[drm:nv50_fifo_channel_disable] ch1, nt=1
>[drm:nv50_fifo_channel_disable] ch2, nt=1
>[drm:nv50_fifo_channel_disable] ch3, nt=1
>[drm:nv50_fifo_channel_disable] ch4, nt=1
>[drm:nv50_fifo_channel_disable] ch5, nt=1
>[drm:nv50_fifo_channel_disable] ch6, nt=1
>[drm:nv50_fifo_channel_disable] ch7, nt=1
>[drm:nv50_fifo_channel_disable] ch8, nt=1
>[drm:nv50_fifo_channel_disable] ch9, nt=1
>[drm:nv50_fifo_channel_disable] ch10, nt=1
>[drm:nv50_fifo_channel_disable] ch11, nt=1
>[drm:nv50_fifo_channel_disable] ch12, nt=1
>[drm:nv50_fifo_channel_disable] ch13, nt=1
>[drm:nv50_fifo_channel_disable] ch14, nt=1
>[drm:nv50_fifo_channel_disable] ch15, nt=1
>[drm:nv50_fifo_channel_disable] ch16, nt=1
>[drm:nv50_fifo_channel_disable] ch17, nt=1
>[drm:nv50_fifo_channel_disable] ch18, nt=1
>[drm:nv50_fifo_channel_disable] ch19, nt=1
>[drm:nv50_fifo_channel_disable] ch20, nt=1
>[drm:nv50_fifo_channel_disable] ch21, nt=1
>[drm:nv50_fifo_channel_disable] ch22, nt=1
>[drm:nv50_fifo_channel_disable] ch23, nt=1
>[drm:nv50_fifo_channel_disable] ch24, nt=1
>[drm:nv50_fifo_channel_disable] ch25, nt=1
>[drm:nv50_fifo_channel_disable] ch26, nt=1
>[drm:nv50_fifo_channel_disable] ch27, nt=1
>[drm:nv50_fifo_channel_disable] ch28, nt=1
>[drm:nv50_fifo_channel_disable] ch29, nt=1
>[drm:nv50_fifo_channel_disable] ch30, nt=1
>[drm:nv50_fifo_channel_disable] ch31, nt=1
>[drm:nv50_fifo_channel_disable] ch32, nt=1
>[drm:nv50_fifo_channel_disable] ch33, nt=1
>[drm:nv50_fifo_channel_disable] ch34, nt=1
>[drm:nv50_fifo_channel_disable] ch35, nt=1
>[drm:nv50_fifo_channel_disable] ch36, nt=1
>[drm:nv50_fifo_channel_disable] ch37, nt=1
>[drm:nv50_fifo_channel_disable] ch38, nt=1
>[drm:nv50_fifo_channel_disable] ch39, nt=1
>[drm:nv50_fifo_channel_disable] ch40, nt=1
>[drm:nv50_fifo_channel_disable] ch41, nt=1
>[drm:nv50_fifo_channel_disable] ch42, nt=1
>[drm:nv50_fifo_channel_disable] ch43, nt=1
>[drm:nv50_fifo_channel_disable] ch44, nt=1
>[drm:nv50_fifo_channel_disable] ch45, nt=1
>[drm:nv50_fifo_channel_disable] ch46, nt=1
>[drm:nv50_fifo_channel_disable] ch47, nt=1
>[drm:nv50_fifo_channel_disable] ch48, nt=1
>[drm:nv50_fifo_channel_disable] ch49, nt=1
>[drm:nv50_fifo_channel_disable] ch50, nt=1
>[drm:nv50_fifo_channel_disable] ch51, nt=1
>[drm:nv50_fifo_channel_disable] ch52, nt=1
>[drm:nv50_fifo_channel_disable] ch53, nt=1
>[drm:nv50_fifo_channel_disable] ch54, nt=1
>[drm:nv50_fifo_channel_disable] ch55, nt=1
>[drm:nv50_fifo_channel_disable] ch56, nt=1
>[drm:nv50_fifo_channel_disable] ch57, nt=1
>[drm:nv50_fifo_channel_disable] ch58, nt=1
>[drm:nv50_fifo_channel_disable] ch59, nt=1
>[drm:nv50_fifo_channel_disable] ch60, nt=1
>[drm:nv50_fifo_channel_disable] ch61, nt=1
>[drm:nv50_fifo_channel_disable] ch62, nt=1
>[drm:nv50_fifo_channel_disable] ch63, nt=1
>[drm:nv50_fifo_channel_disable] ch64, nt=1
>[drm:nv50_fifo_channel_disable] ch65, nt=1
>[drm:nv50_fifo_channel_disable] ch66, nt=1
>[drm:nv50_fifo_channel_disable] ch67, nt=1
>[drm:nv50_fifo_channel_disable] ch68, nt=1
>[drm:nv50_fifo_channel_disable] ch69, nt=1
>[drm:nv50_fifo_channel_disable] ch70, nt=1
>[drm:nv50_fifo_channel_disable] ch71, nt=1
>[drm:nv50_fifo_channel_disable] ch72, nt=1
>[drm:nv50_fifo_channel_disable] ch73, nt=1
>[drm:nv50_fifo_channel_disable] ch74, nt=1
>[drm:nv50_fifo_channel_disable] ch75, nt=1
>[drm:nv50_fifo_channel_disable] ch76, nt=1
>[drm:nv50_fifo_channel_disable] ch77, nt=1
>[drm:nv50_fifo_channel_disable] ch78, nt=1
>[drm:nv50_fifo_channel_disable] ch79, nt=1
>[drm:nv50_fifo_channel_disable] ch80, nt=1
>[drm:nv50_fifo_channel_disable] ch81, nt=1
>[drm:nv50_fifo_channel_disable] ch82, nt=1
>[drm:nv50_fifo_channel_disable] ch83, nt=1
>[drm:nv50_fifo_channel_disable] ch84, nt=1
>[drm:nv50_fifo_channel_disable] ch85, nt=1
>[drm:nv50_fifo_channel_disable] ch86, nt=1
>[drm:nv50_fifo_channel_disable] ch87, nt=1
>[drm:nv50_fifo_channel_disable] ch88, nt=1
>[drm:nv50_fifo_channel_disable] ch89, nt=1
>[drm:nv50_fifo_channel_disable] ch90, nt=1
>[drm:nv50_fifo_channel_disable] ch91, nt=1
>[drm:nv50_fifo_channel_disable] ch92, nt=1
>[drm:nv50_fifo_channel_disable] ch93, nt=1
>[drm:nv50_fifo_channel_disable] ch94, nt=1
>[drm:nv50_fifo_channel_disable] ch95, nt=1
>[drm:nv50_fifo_channel_disable] ch96, nt=1
>[drm:nv50_fifo_channel_disable] ch97, nt=1
>[drm:nv50_fifo_channel_disable] ch98, nt=1
>[drm:nv50_fifo_channel_disable] ch99, nt=1
>[drm:nv50_fifo_channel_disable] ch100, nt=1
>[drm:nv50_fifo_channel_disable] ch101, nt=1
>[drm:nv50_fifo_channel_disable] ch102, nt=1
>[drm:nv50_fifo_channel_disable] ch103, nt=1
>[drm:nv50_fifo_channel_disable] ch104, nt=1
>[drm:nv50_fifo_channel_disable] ch105, nt=1
>[drm:nv50_fifo_channel_disable] ch106, nt=1
>[drm:nv50_fifo_channel_disable] ch107, nt=1
>[drm:nv50_fifo_channel_disable] ch108, nt=1
>[drm:nv50_fifo_channel_disable] ch109, nt=1
>[drm:nv50_fifo_channel_disable] ch110, nt=1
>[drm:nv50_fifo_channel_disable] ch111, nt=1
>[drm:nv50_fifo_channel_disable] ch112, nt=1
>[drm:nv50_fifo_channel_disable] ch113, nt=1
>[drm:nv50_fifo_channel_disable] ch114, nt=1
>[drm:nv50_fifo_channel_disable] ch115, nt=1
>[drm:nv50_fifo_channel_disable] ch116, nt=1
>[drm:nv50_fifo_channel_disable] ch117, nt=1
>[drm:nv50_fifo_channel_disable] ch118, nt=1
>[drm:nv50_fifo_channel_disable] ch119, nt=1
>[drm:nv50_fifo_channel_disable] ch120, nt=1
>[drm:nv50_fifo_channel_disable] ch121, nt=1
>[drm:nv50_fifo_channel_disable] ch122, nt=1
>[drm:nv50_fifo_channel_disable] ch123, nt=1
>[drm:nv50_fifo_channel_disable] ch124, nt=1
>[drm:nv50_fifo_channel_disable] ch125, nt=1
>[drm:nv50_fifo_channel_disable] ch126, nt=1
>[drm:nv50_fifo_channel_disable] ch127, nt=1
>[drm:nv50_fifo_init_thingo] 
>[drm:nv50_fifo_init_regs__nv] 
>[drm:nv50_fifo_init_regs] 
>[drm:nv50_fifo_channel_enable] ch0
>[drm:nv50_fifo_channel_enable] ch127
>[drm:drm_irq_install] irq=16
>[drm:nouveau_dma_channel_init] 
>[drm:drm_addmap_core] offset = 0xdfdc0000, size = 0x00010000, type = 0
>[drm:nouveau_mem_alloc] allocated 65536 bytes at 0xfdc0000 type=0x00000101
>[drm] Allocating FIFO number 1
>[drm:drm_addmap_core] offset = 0xdfdbf000, size = 0x00001000, type = 0
>[drm:nouveau_mem_alloc] allocated 4096 bytes at 0xfdbf000 type=0x00000101
>[drm:nouveau_notifier_init_channel] Allocated notifier block in 0x00000101
>[drm:nouveau_gpuobj_channel_init] ch1 vram=0x8003d001 tt=0x8003d002
>[drm:nouveau_gpuobj_channel_init_pramin] ch1
>[drm:nouveau_gpuobj_channel_init_pramin] ch1 PRAMIN size: 0x0007f400 bytes, base alloc=0x00006000
>[drm:nouveau_gpuobj_new] ch-1 size=521216 align=4096 flags=0x00000000
>[drm:nouveau_gpuobj_new] gpuobj ffff88006c615c40
>[drm:nouveau_gpuobj_new] global heap
>[drm:nouveau_mem_alloc] allocated 524288 bytes at 0xfd3f000 type=0x04000001
>[drm:nv50_instmem_bind] st=0x132000 sz=0x80000
>[drm:nv50_instmem_bind] pramin=0x132000, pte=2448, pte_end=3472
>[drm:nv50_instmem_bind] first vram page: 0xfd3f000
>[drm:nouveau_gpuobj_ref_add] ch-1 h=0x00000000 gpuobj=ffff88006c615c40
>[drm:nouveau_gpuobj_new_fake] p_offset=0x00132200 b_offset=0xffffffff size=0x00004000 flags=0x00000000
>[drm:nouveau_gpuobj_new_fake] gpuobj ffff88006c6156c0
>[drm:nouveau_gpuobj_ref_add] ch-1 h=0x00000000 gpuobj=ffff88006c6158c0
>[drm:nouveau_gpuobj_ref_add] ch-1 h=0x00000000 gpuobj=ffff88006c615d40
>[drm:nouveau_gpuobj_new] ch1 size=32768 align=16 flags=0x00000002
>[drm:nouveau_gpuobj_new] gpuobj ffff88006c615b40
>[drm:nouveau_gpuobj_new] private heap
>[drm:nouveau_gpuobj_ref_add] ch1 h=0x00000000 gpuobj=ffff88006c615b40
>[drm:nouveau_gpuobj_dma_new] ch1 class=0x003d offset=0x0 size=0x100000000
>[drm:nouveau_gpuobj_dma_new] access=0 target=3
>[drm:nouveau_gpuobj_new] ch1 size=24 align=16 flags=0x00000006
>[drm:nouveau_gpuobj_new] gpuobj ffff88006c615740
>[drm:nouveau_gpuobj_new] private heap
>[drm:nouveau_gpuobj_ref_add] ch1 h=0x8003d001 gpuobj=ffff88006c615740
>[drm:nouveau_ramht_hash_handle] ch1 handle=0x8003d001
>[drm:nouveau_ramht_hash_handle] hash=0x00000fc8
>[drm:nouveau_ramht_insert] insert ch1 0x00000fc8: h=0x8003d001, c=0x00000e00
>[drm:nouveau_gpuobj_ref_add] ch1 h=0x8003d002 gpuobj=ffff88006c615740
>[drm:nouveau_ramht_hash_handle] ch1 handle=0x8003d002
>[drm:nouveau_ramht_hash_handle] hash=0x00000fd0
>[drm:nouveau_ramht_insert] insert ch1 0x00000fd0: h=0x8003d002, c=0x00000e00
>[drm:nouveau_gpuobj_dma_new] ch1 class=0x003d offset=0xfdc0000 size=0x10000
>[drm:nouveau_gpuobj_dma_new] access=1 target=0
>[drm:nouveau_gpuobj_new] ch1 size=24 align=16 flags=0x00000006
>[drm:nouveau_gpuobj_new] gpuobj ffff88006c6152c0
>[drm:nouveau_gpuobj_new] private heap
>[drm:nouveau_gpuobj_ref_add] ch1 h=0x00000000 gpuobj=ffff88006c6152c0
>[drm:nv50_graph_create_context] ch1
>[drm:nouveau_gpuobj_new] ch1 size=458752 align=4096 flags=0x00000006
>[drm:nouveau_gpuobj_new] gpuobj ffff88006c615140
>[drm:nouveau_gpuobj_new] private heap
>[drm:nouveau_gpuobj_ref_add] ch-1 h=0x00000000 gpuobj=ffff88006c615140
>[drm:nv50_fifo_create_context] ch1
>[drm:nouveau_gpuobj_new] ch1 size=256 align=256 flags=0x00000006
>[drm:nouveau_gpuobj_new] gpuobj ffff88006c615cc0
>[drm:nouveau_gpuobj_new] private heap
>[drm:nouveau_gpuobj_ref_add] ch-1 h=0x00000000 gpuobj=ffff88006c615cc0
>[drm:nv50_fifo_channel_enable] ch1
>[drm:nv50_fifo_init_thingo] 
>[drm:nv50_fifo_load_context] ch1
>[drm:nv50_graph_load_context] ch1
>[drm] nouveau_fifo_alloc: initialised FIFO 1
>[drm:nouveau_dma_channel_init] Using FIFO channel 1
>[drm:nouveau_gpuobj_dma_new] ch1 class=0x003d offset=0xfdbf000 size=0x20
>[drm:nouveau_gpuobj_dma_new] access=0 target=0
>[drm:nouveau_gpuobj_new] ch1 size=24 align=16 flags=0x00000006
>[drm:nouveau_gpuobj_new] gpuobj ffff88006c6157c0
>[drm:nouveau_gpuobj_new] private heap
>[drm:nouveau_gpuobj_ref_add] ch1 h=0x8003d003 gpuobj=ffff88006c6157c0
>[drm:nouveau_ramht_hash_handle] ch1 handle=0x8003d003
>[drm:nouveau_ramht_hash_handle] hash=0x00000fd8
>[drm:nouveau_ramht_insert] insert ch1 0x00000fd8: h=0x8003d003, c=0x00000e04
>[drm:nouveau_gpuobj_gr_new] ch1 class=0x5039
>[drm:nouveau_gpuobj_new] ch1 size=24 align=16 flags=0x00000006
>[drm:nouveau_gpuobj_new] gpuobj ffff88006c615440
>[drm:nouveau_gpuobj_new] private heap
>[drm:nouveau_gpuobj_ref_add] ch1 h=0x80039001 gpuobj=ffff88006c615440
>[drm:nouveau_ramht_hash_handle] ch1 handle=0x80039001
>[drm:nouveau_ramht_hash_handle] hash=0x00000ec8
>[drm:nouveau_ramht_insert] insert ch1 0x00000ec8: h=0x80039001, c=0x00100e06
>[drm:drm_unlocked_ioctl] pid=4424, cmd=0xc0106441, nr=0x41, dev 0xe200, auth=1
>[drm:drm_unlocked_ioctl] pid=4424, cmd=0xc0106441, nr=0x41, dev 0xe200, auth=1
>[drm:drm_unlocked_ioctl] pid=4424, cmd=0xc0106441, nr=0x41, dev 0xe200, auth=1
>[drm:drm_unlocked_ioctl] pid=4424, cmd=0xc0206448, nr=0x48, dev 0xe200, auth=1
>[drm:drm_addmap_core] offset = 0xd0000000, size = 0x08000000, type = 0
>[drm:nouveau_mem_alloc] allocated 134217728 bytes at 0x0 type=0x00000101
>[drm:drm_mmap_locked] start = 0x7ff4e92d0000, end = 0x7ff4f12d0000, page offset = 0xd0000
>[drm:drm_mmap_locked]    Type = 0; start = 0x7ff4e92d0000, end = 0x7ff4f12d0000, offset = 0xd0000000
>[drm:drm_vm_open_locked] 0x7ff4e92d0000,0x08000000
>[drm:drm_unlocked_ioctl] pid=4424, cmd=0xc0206448, nr=0x48, dev 0xe200, auth=1
>[drm:drm_addmap_core] offset = 0x00000000, size = 0x01000000, type = 4
>[drm:nouveau_mem_alloc] allocated 16777216 bytes at 0x0 type=0x04000102
>[drm:drm_mmap_locked] start = 0x7ff4e82d0000, end = 0x7ff4e92d0000, page offset = 0x1effe
>[drm:drm_vm_open_locked] 0x7ff4e82d0000,0x01000000
>[drm:drm_unlocked_ioctl] pid=4424, cmd=0xc0206448, nr=0x48, dev 0xe200, auth=1
>[drm:drm_addmap_core] offset = 0xd8000000, size = 0x00010000, type = 0
>[drm:nouveau_mem_alloc] allocated 65536 bytes at 0x8000000 type=0x00000101
>[drm:drm_mmap_locked] start = 0x7ff4e82c0000, end = 0x7ff4e82d0000, page offset = 0xd8000
>[drm:drm_mmap_locked]    Type = 0; start = 0x7ff4e82c0000, end = 0x7ff4e82d0000, offset = 0xd8000000
>[drm:drm_vm_open_locked] 0x7ff4e82c0000,0x00010000
>[drm:drm_unlocked_ioctl] pid=4424, cmd=0xc0206448, nr=0x48, dev 0xe200, auth=1
>[drm:drm_addmap_core] offset = 0xd8010000, size = 0x00010000, type = 0
>[drm:nouveau_mem_alloc] allocated 65536 bytes at 0x8010000 type=0x00000101
>[drm:drm_mmap_locked] start = 0x7ff4e82b0000, end = 0x7ff4e82c0000, page offset = 0xd8010
>[drm:drm_mmap_locked]    Type = 0; start = 0x7ff4e82b0000, end = 0x7ff4e82c0000, offset = 0xd8010000
>[drm:drm_vm_open_locked] 0x7ff4e82b0000,0x00010000
>[drm:drm_unlocked_ioctl] pid=4424, cmd=0xc0206448, nr=0x48, dev 0xe200, auth=1
>[drm:drm_addmap_core] offset = 0xd8020000, size = 0x00010000, type = 0
>[drm:nouveau_mem_alloc] allocated 65536 bytes at 0x8020000 type=0x00000101
>[drm:drm_mmap_locked] start = 0x7ff4e82af000, end = 0x7ff4e82b0000, page offset = 0xd8020
>[drm:drm_mmap_locked]    Type = 0; start = 0x7ff4e82af000, end = 0x7ff4e82b0000, offset = 0xd8020000
>[drm:drm_vm_open_locked] 0x7ff4e82af000,0x00001000
>[drm:drm_unlocked_ioctl] pid=4424, cmd=0xc0206448, nr=0x48, dev 0xe200, auth=1
>[drm:drm_addmap_core] offset = 0xd8030000, size = 0x00010000, type = 0
>[drm:nouveau_mem_alloc] allocated 65536 bytes at 0x8030000 type=0x00000101
>[drm:drm_mmap_locked] start = 0x7ff4e82ae000, end = 0x7ff4e82af000, page offset = 0xd8030
>[drm:drm_mmap_locked]    Type = 0; start = 0x7ff4e82ae000, end = 0x7ff4e82af000, offset = 0xd8030000
>[drm:drm_vm_open_locked] 0x7ff4e82ae000,0x00001000
>[drm:drm_unlocked_ioctl] pid=4424, cmd=0xc0106442, nr=0x42, dev 0xe200, auth=1
>[drm:drm_unlocked_ioctl] pid=4424, cmd=0xc0286443, nr=0x43, dev 0xe200, auth=1
>[drm:drm_addmap_core] offset = 0x01ff8000, size = 0x00008000, type = 4
>[drm:nouveau_mem_alloc] allocated 32768 bytes at 0x1ff8000 type=0x04000102
>[drm] Allocating FIFO number 2
>[drm:drm_addmap_core] offset = 0xdfd3e000, size = 0x00001000, type = 0
>[drm:nouveau_mem_alloc] allocated 4096 bytes at 0xfd3e000 type=0x00000101
>[drm:nouveau_notifier_init_channel] Allocated notifier block in 0x00000101
>[drm:nouveau_gpuobj_channel_init] ch2 vram=0xd8000001 tt=0xd8000002
>[drm:nouveau_gpuobj_channel_init_pramin] ch2
>[drm:nouveau_gpuobj_channel_init_pramin] ch2 PRAMIN size: 0x0007f400 bytes, base alloc=0x00006000
>[drm:nouveau_gpuobj_new] ch-1 size=521216 align=4096 flags=0x00000000
>[drm:nouveau_gpuobj_new] gpuobj ffff88006c6159c0
>[drm:nouveau_gpuobj_new] global heap
>[drm:nouveau_mem_alloc] allocated 524288 bytes at 0xfcbe000 type=0x04000001
>[drm:nv50_instmem_bind] st=0x1b2000 sz=0x80000
>[drm:nv50_instmem_bind] pramin=0x1b2000, pte=3472, pte_end=4496
>[drm:nv50_instmem_bind] first vram page: 0xfcbe000
>[drm:nouveau_gpuobj_ref_add] ch-1 h=0x00000000 gpuobj=ffff88006c6159c0
>[drm:nouveau_gpuobj_new_fake] p_offset=0x001b2200 b_offset=0xffffffff size=0x00004000 flags=0x00000000
>[drm:nouveau_gpuobj_new_fake] gpuobj ffff88006c615340
>[drm:nouveau_gpuobj_ref_add] ch-1 h=0x00000000 gpuobj=ffff88006c6158c0
>[drm:nouveau_gpuobj_ref_add] ch-1 h=0x00000000 gpuobj=ffff88006c615d40
>[drm:nouveau_gpuobj_new] ch2 size=32768 align=16 flags=0x00000002
>[drm:nouveau_gpuobj_new] gpuobj ffff880059a1b440
>[drm:nouveau_gpuobj_new] private heap
>[drm:nouveau_gpuobj_ref_add] ch2 h=0x00000000 gpuobj=ffff880059a1b440
>[drm:nouveau_gpuobj_dma_new] ch2 class=0x003d offset=0x0 size=0x100000000
>[drm:nouveau_gpuobj_dma_new] access=0 target=3
>[drm:nouveau_gpuobj_new] ch2 size=24 align=16 flags=0x00000006
>[drm:nouveau_gpuobj_new] gpuobj ffff880059a1ba40
>[drm:nouveau_gpuobj_new] private heap
>[drm:nouveau_gpuobj_ref_add] ch2 h=0xd8000001 gpuobj=ffff880059a1ba40
>[drm:nouveau_ramht_hash_handle] ch2 handle=0xd8000001
>[drm:nouveau_ramht_hash_handle] hash=0x000000d0
>[drm:nouveau_ramht_insert] insert ch2 0x000000d0: h=0xd8000001, c=0x00000e00
>[drm:nouveau_gpuobj_ref_add] ch2 h=0xd8000002 gpuobj=ffff880059a1ba40
>[drm:nouveau_ramht_hash_handle] ch2 handle=0xd8000002
>[drm:nouveau_ramht_hash_handle] hash=0x000000c8
>[drm:nouveau_ramht_insert] insert ch2 0x000000c8: h=0xd8000002, c=0x00000e00
>[drm:nouveau_gpuobj_dma_new] ch2 class=0x003d offset=0x1ff8000 size=0x8000
>[drm:nouveau_gpuobj_dma_new] access=1 target=3
>[drm:nouveau_gpuobj_new] ch2 size=24 align=16 flags=0x00000006
>[drm:nouveau_gpuobj_new] gpuobj ffff880059a1b3c0
>[drm:nouveau_gpuobj_new] private heap
>[drm:nouveau_gpuobj_ref_add] ch2 h=0x00000000 gpuobj=ffff880059a1b3c0
>[drm:nv50_graph_create_context] ch2
>[drm:nouveau_gpuobj_new] ch2 size=458752 align=4096 flags=0x00000006
>[drm:nouveau_gpuobj_new] gpuobj ffff880059a1bdc0
>[drm:nouveau_gpuobj_new] private heap
>[drm:nouveau_gpuobj_ref_add] ch-1 h=0x00000000 gpuobj=ffff880059a1bdc0
>[drm:nv50_fifo_create_context] ch2
>[drm:nouveau_gpuobj_new] ch2 size=256 align=256 flags=0x00000006
>[drm:nouveau_gpuobj_new] gpuobj ffff880059a1b2c0
>[drm:nouveau_gpuobj_new] private heap
>[drm:nouveau_gpuobj_ref_add] ch-1 h=0x00000000 gpuobj=ffff880059a1b2c0
>[drm:nv50_fifo_channel_enable] ch2
>[drm:nv50_fifo_init_thingo] 
>[drm] nouveau_fifo_alloc: initialised FIFO 2
>[drm:drm_addmap_core] offset = 0xcec04000, size = 0x00002000, type = 1
>[drm:drm_mmap_locked] start = 0x7ff4e82ac000, end = 0x7ff4e82ae000, page offset = 0xcec04
>[drm:drm_mmap_locked]    Type = 1; start = 0x7ff4e82ac000, end = 0x7ff4e82ae000, offset = 0xcec04000
>[drm:drm_vm_open_locked] 0x7ff4e82ac000,0x00002000
>[drm:drm_mmap_locked] start = 0x7ff4e82ab000, end = 0x7ff4e82ac000, page offset = 0xdfd3e
>[drm:drm_mmap_locked]    Type = 0; start = 0x7ff4e82ab000, end = 0x7ff4e82ac000, offset = 0xdfd3e000
>[drm:drm_vm_open_locked] 0x7ff4e82ab000,0x00001000
>[drm:drm_mmap_locked] start = 0x7ff4e82a3000, end = 0x7ff4e82ab000, page offset = 0x1efff
>[drm:drm_vm_open_locked] 0x7ff4e82a3000,0x00008000
>[drm:drm_unlocked_ioctl] pid=4424, cmd=0x400c6445, nr=0x45, dev 0xe200, auth=1
>[drm:nouveau_gpuobj_gr_new] ch2 class=0x0030
>[drm:nouveau_gpuobj_new] ch2 size=24 align=16 flags=0x00000006
>[drm:nouveau_gpuobj_new] gpuobj ffff880059a1b940
>[drm:nouveau_gpuobj_new] private heap
>[drm:nouveau_gpuobj_ref_add] ch2 h=0x00000000 gpuobj=ffff880059a1b940
>[drm:nouveau_ramht_hash_handle] ch2 handle=0x00000000
>[drm:nouveau_ramht_hash_handle] hash=0x00000000
>[drm:nouveau_ramht_insert] insert ch2 0x00000000: h=0x00000000, c=0x00100e04
>[drm:drm_unlocked_ioctl] pid=4424, cmd=0xc0106446, nr=0x46, dev 0xe200, auth=1
>[drm:nouveau_gpuobj_dma_new] ch2 class=0x003d offset=0xfd3e000 size=0x20
>[drm:nouveau_gpuobj_dma_new] access=0 target=0
>[drm:nouveau_gpuobj_new] ch2 size=24 align=16 flags=0x00000006
>[drm:nouveau_gpuobj_new] gpuobj ffff880059a1b4c0
>[drm:nouveau_gpuobj_new] private heap
>[drm:nouveau_gpuobj_ref_add] ch2 h=0xd8000003 gpuobj=ffff880059a1b4c0
>[drm:nouveau_ramht_hash_handle] ch2 handle=0xd8000003
>[drm:nouveau_ramht_hash_handle] hash=0x000000c0
>[drm:nouveau_ramht_insert] insert ch2 0x000000c0: h=0xd8000003, c=0x00000e06
>[drm:drm_unlocked_ioctl] pid=4424, cmd=0x400c6445, nr=0x45, dev 0xe200, auth=1
>[drm:nouveau_gpuobj_gr_new] ch2 class=0x502d
>[drm:nouveau_gpuobj_new] ch2 size=24 align=16 flags=0x00000006
>[drm:nouveau_gpuobj_new] gpuobj ffff880059a1b140
>[drm:nouveau_gpuobj_new] private heap
>[drm:nouveau_gpuobj_ref_add] ch2 h=0x80000020 gpuobj=ffff880059a1b140
>[drm:nouveau_ramht_hash_handle] ch2 handle=0x80000020
>[drm:nouveau_ramht_hash_handle] hash=0x00000180
>[drm:nouveau_ramht_insert] insert ch2 0x00000180: h=0x80000020, c=0x00100e08
>[drm:drm_unlocked_ioctl] pid=4424, cmd=0x400c6445, nr=0x45, dev 0xe200, auth=1
>[drm:nouveau_gpuobj_gr_new] ch2 class=0x5039
>[drm:nouveau_gpuobj_new] ch2 size=24 align=16 flags=0x00000006
>[drm:nouveau_gpuobj_new] gpuobj ffff880059a1b840
>[drm:nouveau_gpuobj_new] private heap
>[drm:nouveau_gpuobj_ref_add] ch2 h=0x80000018 gpuobj=ffff880059a1b840
>[drm:nouveau_ramht_hash_handle] ch2 handle=0x80000018
>[drm:nouveau_ramht_hash_handle] hash=0x00000040
>[drm:nouveau_ramht_insert] insert ch2 0x00000040: h=0x80000018, c=0x00100e0a
>[drm:drm_unlocked_ioctl] pid=4424, cmd=0x400c6445, nr=0x45, dev 0xe200, auth=1
>[drm:nouveau_gpuobj_gr_new] ch2 class=0x8297
>[drm:nouveau_gpuobj_new] ch2 size=24 align=16 flags=0x00000006
>[drm:nouveau_gpuobj_new] gpuobj ffff880059a1b640
>[drm:nouveau_gpuobj_new] private heap
>[drm:nouveau_gpuobj_ref_add] ch2 h=0x80000019 gpuobj=ffff880059a1b640
>[drm:nouveau_ramht_hash_handle] ch2 handle=0x80000019
>[drm:nouveau_ramht_hash_handle] hash=0x00000048
>[drm:nouveau_ramht_insert] insert ch2 0x00000048: h=0x80000019, c=0x00100e0c
>[drm:drm_unlocked_ioctl] pid=4424, cmd=0xc0206448, nr=0x48, dev 0xe200, auth=1
>[drm:drm_addmap_core] offset = 0xd8040000, size = 0x00010000, type = 0
>[drm:nouveau_mem_alloc] allocated 65536 bytes at 0x8040000 type=0x00000101
>[drm:drm_mmap_locked] start = 0x7ff4e8252000, end = 0x7ff4e8262000, page offset = 0xd8040
>[drm:drm_mmap_locked]    Type = 0; start = 0x7ff4e8252000, end = 0x7ff4e8262000, offset = 0xd8040000
>[drm:drm_vm_open_locked] 0x7ff4e8252000,0x00010000
>[drm:drm_unlocked_ioctl] pid=4424, cmd=0x4020644a, nr=0x4a, dev 0xe200, auth=1
>[drm:drm_stub_open] 
>[drm:drm_open_helper] pid = 4424, minor = 0
>[drm:drm_unlocked_ioctl] pid=4424, cmd=0xc0406400, nr=0x00, dev 0xe200, auth=1
>[drm:drm_unlocked_ioctl] pid=4424, cmd=0xc0406400, nr=0x00, dev 0xe200, auth=1
>[drm:drm_release] open_count = 2
>[drm:nouveau_fifo_cleanup] clearing FIFO enables from file_priv
>[drm:drm_release] pid = 4424, device = 0xe200, open_count = 2
>[drm:drm_fasync] fd = -1, device = 0xe200
>[drm:drm_stub_open] 
>[drm:drm_open_helper] pid = 4424, minor = 0
>[drm:drm_unlocked_ioctl] pid=4424, cmd=0xc0106407, nr=0x07, dev 0xe200, auth=1
>[drm:drm_unlocked_ioctl] ret = -13
>[drm:drm_unlocked_ioctl] pid=4424, cmd=0xc0106401, nr=0x01, dev 0xe200, auth=1
>[drm:drm_unlocked_ioctl] pid=4424, cmd=0xc0106401, nr=0x01, dev 0xe200, auth=1
>[drm:drm_unlocked_ioctl] pid=4424, cmd=0x80046402, nr=0x02, dev 0xe200, auth=1
>[drm:drm_add_magic] 5
>[drm:drm_getmagic] 5
>[drm:drm_unlocked_ioctl] pid=4424, cmd=0xc0406400, nr=0x00, dev 0xe200, auth=1
>[drm:drm_unlocked_ioctl] pid=4424, cmd=0xc0406400, nr=0x00, dev 0xe200, auth=1
>[drm:drm_unlocked_ioctl] pid=4424, cmd=0x40046411, nr=0x11, dev 0xe200, auth=1
>[drm:drm_authmagic] 5
>[drm:drm_remove_magic] 5
>[drm:drm_release] open_count = 2
>[drm:nouveau_fifo_cleanup] clearing FIFO enables from file_priv
>[drm:drm_release] pid = 4424, device = 0xe200, open_count = 2
>[drm:drm_fasync] fd = -1, device = 0xe200
>[drm:drm_vm_open_locked] 0x7ff4e8252000,0x00010000
>[drm:drm_vm_open_locked] 0x7ff4e82a3000,0x00008000
>[drm:drm_vm_open_locked] 0x7ff4e82ab000,0x00001000
>[drm:drm_vm_open_locked] 0x7ff4e82ac000,0x00002000
>[drm:drm_vm_open_locked] 0x7ff4e82ae000,0x00001000
>[drm:drm_vm_open_locked] 0x7ff4e82af000,0x00001000
>[drm:drm_vm_open_locked] 0x7ff4e82b0000,0x00010000
>[drm:drm_vm_open_locked] 0x7ff4e82c0000,0x00010000
>[drm:drm_vm_open_locked] 0x7ff4e82d0000,0x01000000
>[drm:drm_vm_open_locked] 0x7ff4e92d0000,0x08000000
>[drm:drm_vm_open_locked] 0x7ff4f668a000,0x00002000
>[drm:drm_vm_close] 0x7ff4e8252000,0x00010000
>[drm:drm_vm_close] 0x7ff4e82a3000,0x00008000
>[drm:drm_vm_close] 0x7ff4e82ab000,0x00001000
>[drm:drm_vm_close] 0x7ff4e82ac000,0x00002000
>[drm:drm_vm_close] 0x7ff4e82ae000,0x00001000
>[drm:drm_vm_close] 0x7ff4e82af000,0x00001000
>[drm:drm_vm_close] 0x7ff4e82b0000,0x00010000
>[drm:drm_vm_close] 0x7ff4e82c0000,0x00010000
>[drm:drm_vm_close] 0x7ff4e82d0000,0x01000000
>[drm:drm_vm_close] 0x7ff4e92d0000,0x08000000
>[drm:drm_vm_shm_close] 0x7ff4f668a000,0x00002000
>evdev.c(EVIOCGBIT): Suspicious buffer size 511, limiting output to 64 bytes. See http://userweb.kernel.org/~dtor/eviocgbit-bug.html
>[drm:drm_vm_open_locked] 0x7ff4e8252000,0x00010000
>[drm:drm_vm_open_locked] 0x7ff4e82a3000,0x00008000
>[drm:drm_vm_open_locked] 0x7ff4e82ab000,0x00001000
>[drm:drm_vm_open_locked] 0x7ff4e82ac000,0x00002000
>[drm:drm_vm_open_locked] 0x7ff4e82ae000,0x00001000
>[drm:drm_vm_open_locked] 0x7ff4e82af000,0x00001000
>[drm:drm_vm_open_locked] 0x7ff4e82b0000,0x00010000
>[drm:drm_vm_open_locked] 0x7ff4e82c0000,0x00010000
>[drm:drm_vm_open_locked] 0x7ff4e82d0000,0x01000000
>[drm:drm_vm_open_locked] 0x7ff4e92d0000,0x08000000
>[drm:drm_vm_open_locked] 0x7ff4f668a000,0x00002000
>[drm:drm_vm_close] 0x7ff4e8252000,0x00010000
>[drm:drm_vm_close] 0x7ff4e82a3000,0x00008000
>[drm:drm_vm_close] 0x7ff4e82ab000,0x00001000
>[drm:drm_vm_close] 0x7ff4e82ac000,0x00002000
>[drm:drm_vm_close] 0x7ff4e82ae000,0x00001000
>[drm:drm_vm_close] 0x7ff4e82af000,0x00001000
>[drm:drm_vm_close] 0x7ff4e82b0000,0x00010000
>[drm:drm_vm_close] 0x7ff4e82c0000,0x00010000
>[drm:drm_vm_close] 0x7ff4e82d0000,0x01000000
>[drm:drm_vm_close] 0x7ff4e92d0000,0x08000000
>[drm:drm_vm_shm_close] 0x7ff4f668a000,0x00002000

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Attachments on bug 19261: 21446 | 21447 | 21449

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