Attachment 23522 Details for Bug 20463 – Occational output of intel_reg_dumper in the "bad" case (2)

Occational output of intel_reg_dumper in the "bad" case (2)

irg-bad-special2.txt (text/plain), 10.59 KB, created by Geir Ove Myhr on 2009-03-04 10:59:42 UTC

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Creator: Geir Ove Myhr

Created: 2009-03-04 10:59:42 UTC

Size: 10.59 KB

patch

obsolete

>(II): DumpRegsBegin
>(II):            CHDECMISC: 0x22b95028 (XOR bank/rank, ch2 enh disabled, ch1 enh enabled, ch0 enh disabled, flex disabled, ep not present)
>(II):               C0DRB0: 0x000f0202 (0x0202)
>(II):               C0DRB1: 0x0000000f (0x000f)
>(II):               C0DRB2: 0x00000000 (0x0000)
>(II):               C0DRB3: 0x04000000 (0x0000)
>(II):               C1DRB0: 0x05040302 (0x0302)
>(II):               C1DRB1: 0x07060504 (0x0504)
>(II):               C1DRB2: 0x09080706 (0x0706)
>(II):               C1DRB3: 0x0b0a0908 (0x0908)
>(II):              C0DRA01: 0x02010400 (0x0400)
>(II):              C0DRA23: 0x00000201 (0x0201)
>(II):              C1DRA01: 0x0d0c0b0a (0x0b0a)
>(II):              C1DRA23: 0x0f0e0d0c (0x0d0c)
>(II):    VCLK_DIVISOR_VGA0: 0x00031108 (n = 3, m1 = 17, m2 = 8)
>(II):    VCLK_DIVISOR_VGA1: 0x00031406 (n = 3, m1 = 20, m2 = 6)
>(II):        VCLK_POST_DIV: 0x00020002 (vga0 p1 = 4, p2 = 2, vga1 p1 = 2, p2 = 2)
>(II):            DPLL_TEST: 0x00010001 ()
>(II):         CACHE_MODE_0: 0x00006820
>(II):              D_STATE: 0x00000000
>(II):        DSPCLK_GATE_D: 0x00000000 (clock gates disabled:)
>(II):       RENCLK_GATE_D1: 0x00000000
>(II):       RENCLK_GATE_D2: 0x00000000
>(II):                SDVOB: 0xc0480084 (enabled, pipe B, stall disabled, detected, SDVO mult 1)
>(II):                SDVOC: 0x00480000 (disabled, pipe A, stall disabled, not detected, SDVO mult 1)
>(II):              SDVOUDI: 0x00000000
>(II):               DSPARB: 0x00002f2f
>(II):               DSPFW1: 0x00000000
>(II):               DSPFW2: 0x00000000
>(II):               DSPFW3: 0x00000000
>(II):                 ADPA: 0x80000010 (enabled, pipe A, -hsync, +vsync)
>(II):                 LVDS: 0x00000000 (disabled, pipe A, 18 bit, 1 channel)
>(II):                 DVOA: 0x00000000 (disabled, pipe A, no stall, -hsync, -vsync)
>(II):                 DVOB: 0xc0480084 (enabled, pipe B, no stall, -hsync, -vsync)
>(II):                 DVOC: 0x00480000 (disabled, pipe A, no stall, -hsync, -vsync)
>(II):          DVOA_SRCDIM: 0x00000000
>(II):          DVOB_SRCDIM: 0x00000000
>(II):          DVOC_SRCDIM: 0x00000000
>(II):           PP_CONTROL: 0x00000000 (power target: off)
>(II):            PP_STATUS: 0x00000000 (off, not ready, sequencing idle)
>(II):         PP_ON_DELAYS: 0x00000000
>(II):        PP_OFF_DELAYS: 0x00000000
>(II):           PP_DIVISOR: 0x00000000
>(II):         PFIT_CONTROL: 0x00000000
>(II):      PFIT_PGM_RATIOS: 0x00000000
>(II):      PORT_HOTPLUG_EN: 0x00000000
>(II):    PORT_HOTPLUG_STAT: 0x00000000
>(II):             DSPACNTR: 0xd8000000 (enabled, pipe A)
>(II):           DSPASTRIDE: 0x00002000 (8192 bytes)
>(II):              DSPAPOS: 0x00000000 (0, 0)
>(II):             DSPASIZE: 0x035f047f (1152, 864)
>(II):             DSPABASE: 0x03000000
>(II):             DSPASURF: 0x00000000
>(II):          DSPATILEOFF: 0x00000000
>(II):            PIPEACONF: 0x80000000 (enabled, single-wide)
>(II):             PIPEASRC: 0x047f035f (1152, 864)
>(II):            PIPEASTAT: 0x00000000 (status:)
>(II):                 FPA0: 0x00030d08 (n = 3, m1 = 13, m2 = 8)
>(II):                 FPA1: 0x00031108 (n = 3, m1 = 17, m2 = 8)
>(II):               DPLL_A: 0x94020000 (enabled, non-dvo, default clock, DAC/serial mode, p1 = 2, p2 = 10)
>(II):            DPLL_A_MD: 0x00000000
>(II):             HTOTAL_A: 0x05ef047f (1152 active, 1520 total)
>(II):             HBLANK_A: 0x05ef047f (1152 start, 1520 end)
>(II):              HSYNC_A: 0x053704bf (1216 start, 1336 end)
>(II):             VTOTAL_A: 0x037e035f (864 active, 895 total)
>(II):             VBLANK_A: 0x037e035f (864 start, 895 end)
>(II):              VSYNC_A: 0x03630360 (865 start, 868 end)
>(II):            BCLRPAT_A: 0x00000000
>(II):         VSYNCSHIFT_A: 0x00000000
>(II):             DSPBCNTR: 0xd9000000 (enabled, pipe B)
>(II):           DSPBSTRIDE: 0x00002000 (8192 bytes)
>(II):              DSPBPOS: 0x00000000 (0, 0)
>(II):             DSPBSIZE: 0x035f047f (1152, 864)
>(II):             DSPBBASE: 0x03000000
>(II):             DSPBSURF: 0x00000000
>(II):          DSPBTILEOFF: 0x00000000
>(II):            PIPEBCONF: 0x80000000 (enabled, single-wide)
>(II):             PIPEBSRC: 0x047f035f (1152, 864)
>(II):            PIPEBSTAT: 0x00000202 (status: VSYNC_INT_STATUS VBLANK_INT_STATUS)
>(II):                 FPB0: 0x00020e08 (n = 2, m1 = 14, m2 = 8)
>(II):                 FPB1: 0x00031108 (n = 3, m1 = 17, m2 = 8)
>(II):               DPLL_B: 0xd4020000 (enabled, dvo, default clock, DAC/serial mode, p1 = 2, p2 = 10)
>(II):            DPLL_B_MD: 0x00000000
>(II):             HTOTAL_B: 0x063f047f (1152 active, 1600 total)
>(II):             HBLANK_B: 0x063f047f (1152 start, 1600 end)
>(II):              HSYNC_B: 0x053f04bf (1216 start, 1344 end)
>(II):             VTOTAL_B: 0x0383035f (864 active, 900 total)
>(II):             VBLANK_B: 0x0383035f (864 start, 900 end)
>(II):              VSYNC_B: 0x03630360 (865 start, 868 end)
>(II):            BCLRPAT_B: 0x00000000
>(II):         VSYNCSHIFT_B: 0x00000000
>(II):    VCLK_DIVISOR_VGA0: 0x00031108
>(II):    VCLK_DIVISOR_VGA1: 0x00031406
>(II):        VCLK_POST_DIV: 0x00020002
>(II):             VGACNTRL: 0x8000008e (disabled)
>(II):               TV_CTL: 0x00000000
>(II):               TV_DAC: 0x00000000
>(II):             TV_CSC_Y: 0x00000000
>(II):            TV_CSC_Y2: 0x00000000
>(II):             TV_CSC_U: 0x00000000
>(II):            TV_CSC_U2: 0x00000000
>(II):             TV_CSC_V: 0x00000000
>(II):            TV_CSC_V2: 0x00000000
>(II):         TV_CLR_KNOBS: 0x00000000
>(II):         TV_CLR_LEVEL: 0x00000000
>(II):           TV_H_CTL_1: 0x00000000
>(II):           TV_H_CTL_2: 0x00000000
>(II):           TV_H_CTL_3: 0x00000000
>(II):           TV_V_CTL_1: 0x00000000
>(II):           TV_V_CTL_2: 0x00000000
>(II):           TV_V_CTL_3: 0x00000000
>(II):           TV_V_CTL_4: 0x00000000
>(II):           TV_V_CTL_5: 0x00000000
>(II):           TV_V_CTL_6: 0x00000000
>(II):           TV_V_CTL_7: 0x00000000
>(II):          TV_SC_CTL_1: 0x00000000
>(II):          TV_SC_CTL_2: 0x00000000
>(II):          TV_SC_CTL_3: 0x00000000
>(II):           TV_WIN_POS: 0x00000000
>(II):          TV_WIN_SIZE: 0x00000000
>(II):      TV_FILTER_CTL_1: 0x00000000
>(II):      TV_FILTER_CTL_2: 0x00000000
>(II):      TV_FILTER_CTL_3: 0x00000000
>(II):        TV_CC_CONTROL: 0x00000000
>(II):           TV_CC_DATA: 0x00000000
>(II):          TV_H_LUMA_0: 0x00000000
>(II):         TV_H_LUMA_59: 0x00000000
>(II):        TV_H_CHROMA_0: 0x00000000
>(II):       TV_H_CHROMA_59: 0x00000000
>(II):         FBC_CFB_BASE: 0x00000000
>(II):          FBC_LL_BASE: 0x00000000
>(II):          FBC_CONTROL: 0x00000000
>(II):          FBC_COMMAND: 0x00000000
>(II):           FBC_STATUS: 0x20000000
>(II):         FBC_CONTROL2: 0x00000000
>(II):        FBC_FENCE_OFF: 0x00000000
>(II):          FBC_MOD_NUM: 0x00000000
>(II):              MI_MODE: 0x00000200
>(II):         MI_ARB_STATE: 0x00000040
>(II):       MI_RDRET_STATE: 0x00000000
>(II):              ECOSKPD: 0x00000307
>(II):                 DP_B: 0x00000000
>(II):       DPB_AUX_CH_CTL: 0x00000000
>(II):     DPB_AUX_CH_DATA1: 0x00000000
>(II):     DPB_AUX_CH_DATA2: 0x00000000
>(II):     DPB_AUX_CH_DATA3: 0x00000000
>(II):     DPB_AUX_CH_DATA4: 0x00000000
>(II):     DPB_AUX_CH_DATA5: 0x00000000
>(II):                 DP_C: 0x00000000
>(II):       DPC_AUX_CH_CTL: 0x00000000
>(II):     DPC_AUX_CH_DATA1: 0x00000000
>(II):     DPC_AUX_CH_DATA2: 0x00000000
>(II):     DPC_AUX_CH_DATA3: 0x00000000
>(II):     DPC_AUX_CH_DATA4: 0x00000000
>(II):     DPC_AUX_CH_DATA5: 0x00000000
>(II):                 DP_D: 0x00000000
>(II):       DPD_AUX_CH_CTL: 0x00000000
>(II):     DPD_AUX_CH_DATA1: 0x00000000
>(II):     DPD_AUX_CH_DATA2: 0x00000000
>(II):     DPD_AUX_CH_DATA3: 0x00000000
>(II):     DPD_AUX_CH_DATA4: 0x00000000
>(II):     DPD_AUX_CH_DATA5: 0x00000000
>(II):        FENCE START 0: 0xffffffff ( enabled, Y tile walk, 130944 pitch, 0xfffff000 start)
>(II):          FENCE END 0: 0xffffffff (                                   0xfffff000 end)
>(II):        FENCE START 1: 0xffffffff ( enabled, Y tile walk, 130944 pitch, 0xfffff000 start)
>(II):          FENCE END 1: 0xffffffff (                                   0xfffff000 end)
>(II):        FENCE START 2: 0xffffffff ( enabled, Y tile walk, 130944 pitch, 0xfffff000 start)
>(II):          FENCE END 2: 0xffffffff (                                   0xfffff000 end)
>(II):        FENCE START 3: 0xffffffff ( enabled, Y tile walk, 130944 pitch, 0xfffff000 start)
>(II):          FENCE END 3: 0xffffffff (                                   0xfffff000 end)
>(II):        FENCE START 4: 0xffffffff ( enabled, Y tile walk, 130944 pitch, 0xfffff000 start)
>(II):          FENCE END 4: 0xffffffff (                                   0xfffff000 end)
>(II):        FENCE START 5: 0xffffffff ( enabled, Y tile walk, 130944 pitch, 0xfffff000 start)
>(II):          FENCE END 5: 0xffffffff (                                   0xfffff000 end)
>(II):        FENCE START 6: 0xffffffff ( enabled, Y tile walk, 130944 pitch, 0xfffff000 start)
>(II):          FENCE END 6: 0xffffffff (                                   0xfffff000 end)
>(II):        FENCE START 7: 0xffffffff ( enabled, Y tile walk, 130944 pitch, 0xfffff000 start)
>(II):          FENCE END 7: 0xffffffff (                                   0xfffff000 end)
>(II):        FENCE START 8: 0xffffffff ( enabled, Y tile walk, 130944 pitch, 0xfffff000 start)
>(II):          FENCE END 8: 0xffffffff (                                   0xfffff000 end)
>(II):        FENCE START 9: 0xffffffff ( enabled, Y tile walk, 130944 pitch, 0xfffff000 start)
>(II):          FENCE END 9: 0xffffffff (                                   0xfffff000 end)
>(II):       FENCE START 10: 0xffffffff ( enabled, Y tile walk, 130944 pitch, 0xfffff000 start)
>(II):         FENCE END 10: 0xffffffff (                                   0xfffff000 end)
>(II):       FENCE START 11: 0xffffffff ( enabled, Y tile walk, 130944 pitch, 0xfffff000 start)
>(II):         FENCE END 11: 0xffffffff (                                   0xfffff000 end)
>(II):       FENCE START 12: 0xffffffff ( enabled, Y tile walk, 130944 pitch, 0xfffff000 start)
>(II):         FENCE END 12: 0xffffffff (                                   0xfffff000 end)
>(II):       FENCE START 13: 0xffffffff ( enabled, Y tile walk, 130944 pitch, 0xfffff000 start)
>(II):         FENCE END 13: 0xffffffff (                                   0xfffff000 end)
>(II):       FENCE START 14: 0xffffffff ( enabled, Y tile walk, 130944 pitch, 0xfffff000 start)
>(II):         FENCE END 14: 0xffffffff (                                   0xfffff000 end)
>(II):       FENCE START 15: 0xffffffff ( enabled, Y tile walk, 130944 pitch, 0xfffff000 start)
>(II):         FENCE END 15: 0xffffffff (                                   0xfffff000 end)
>(II): pipe A dot 81600 n 3 m1 13 m2 8 p1 2 p2 10
>(II): pipe B dot 108000 n 2 m1 14 m2 8 p1 2 p2 10
>(II): DumpRegsEnd

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Attachments on bug 20463: 23515 | 23516 | 23517 | 23518 | 23519 | 23520 | 23521 | 23522 | 23523 | 23524 | 23526 | 23527 | 23673 | 23759 | 23760 | 23761 | 24673 | 24674 | 24675 | 25461 | 25482 | 25483 | 25484 | 25556 | 25557 | 25558 | 25559 | 25851 | 25864

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