Attachment 26945 Details for Bug 22262 – kernel 2.6.30-03165-g6b70246 intel_reg_dumper output

kernel 2.6.30-03165-g6b70246 intel_reg_dumper output

intel_reg_dumper_output_after_xstart_kms_drmMerge.txt (text/plain), 10.61 KB, created by Florian Mickler on 2009-06-19 00:09:43 UTC

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Creator: Florian Mickler

Created: 2009-06-19 00:09:43 UTC

Size: 10.61 KB

patch

obsolete

>(II): DumpRegsBegin
>(II):            CHDECMISC: 0x00000000 (none, ch2 enh disabled, ch1 enh disabled, ch0 enh disabled, flex disabled, ep not present)
>(II):               C0DRB0: 0x000f0002 (0x0002)
>(II):               C0DRB1: 0x0000000f (0x000f)
>(II):               C0DRB2: 0x00000000 (0x0000)
>(II):               C0DRB3: 0x0e000000 (0x0000)
>(II):               C1DRB0: 0x17cbe000 (0xe000)
>(II):               C1DRB1: 0x000017cb (0x17cb)
>(II):               C1DRB2: 0x00000000 (0x0000)
>(II):               C1DRB3: 0x00000000 (0x0000)
>(II):              C0DRA01: 0x00030e00 (0x0e00)
>(II):              C0DRA23: 0x000c0003 (0x0003)
>(II):              C1DRA01: 0x00000000 (0x0000)
>(II):              C1DRA23: 0x00000000 (0x0000)
>(II):    VCLK_DIVISOR_VGA0: 0x00031108 (n = 3, m1 = 17, m2 = 8)
>(II):    VCLK_DIVISOR_VGA1: 0x00031406 (n = 3, m1 = 20, m2 = 6)
>(II):        VCLK_POST_DIV: 0x00020002 (vga0 p1 = 4, p2 = 2, vga1 p1 = 2, p2 = 2)
>(II):            DPLL_TEST: 0x00010001 ()
>(II):         CACHE_MODE_0: 0x00006800
>(II):              D_STATE: 0x00000000
>(II):        DSPCLK_GATE_D: 0x00001000 (clock gates disabled: DPLUNIT)
>(II):       RENCLK_GATE_D1: 0x00000000
>(II):       RENCLK_GATE_D2: 0x00000000
>(II):                SDVOB: 0x00080018 (disabled, pipe A, stall disabled, not detected)
>(II):                SDVOC: 0x00080018 (disabled, pipe A, stall disabled, not detected)
>(II):              SDVOUDI: 0x00000000
>(II):               DSPARB: 0x00001d9c
>(II):               DSPFW1: 0x3f8f0f0f
>(II):               DSPFW2: 0x00000f0f
>(II):               DSPFW3: 0x00000000
>(II):                 ADPA: 0x80000010 (enabled, pipe A, -hsync, +vsync)
>(II):                 LVDS: 0xc2300300 (enabled, pipe B, 18 bit, 1 channel)
>(II):                 DVOA: 0x00000000 (disabled, pipe A, no stall, -hsync, -vsync)
>(II):                 DVOB: 0x00080018 (disabled, pipe A, no stall, +hsync, +vsync)
>(II):                 DVOC: 0x00080018 (disabled, pipe A, no stall, +hsync, +vsync)
>(II):          DVOA_SRCDIM: 0x00000000
>(II):          DVOB_SRCDIM: 0x00000000
>(II):          DVOC_SRCDIM: 0x00000000
>(II):           PP_CONTROL: 0x00000003 (power target: on)
>(II):            PP_STATUS: 0xc0000008 (on, ready, sequencing idle)
>(II):         PP_ON_DELAYS: 0x00fa09c4
>(II):        PP_OFF_DELAYS: 0x00fa09c4
>(II):           PP_DIVISOR: 0x00410903
>(II):         PFIT_CONTROL: 0x20000000
>(II):      PFIT_PGM_RATIOS: 0x00000000
>(II):      PORT_HOTPLUG_EN: 0x06040220
>(II):    PORT_HOTPLUG_STAT: 0x00000300
>(II):             DSPACNTR: 0xd8000400 (enabled, pipe A)
>(II):           DSPASTRIDE: 0x00003200 (12800 bytes)
>(II):              DSPAPOS: 0x00000000 (0, 0)
>(II):             DSPASIZE: 0x00000000 (1, 1)
>(II):             DSPABASE: 0x00000000
>(II):             DSPASURF: 0x01f96000
>(II):          DSPATILEOFF: 0x00000000
>(II):            PIPEACONF: 0xc0000000 (enabled, active)
>(II):             PIPEASRC: 0x068f0419 (1680, 1050)
>(II):            PIPEASTAT: 0x00040200 (status: SVBLANK_INT_ENABLE VSYNC_INT_STATUS)
>(II):                 FPA0: 0x00030b09 (n = 3, m1 = 11, m2 = 9)
>(II):                 FPA1: 0x00031108 (n = 3, m1 = 17, m2 = 8)
>(II):               DPLL_A: 0x94010c00 (enabled, non-dvo, default clock, DAC/serial mode, p1 = 1, p2 = 10)
>(II):            DPLL_A_MD: 0x00000000
>(II):             HTOTAL_A: 0x08bf068f (1680 active, 2240 total)
>(II):             HBLANK_A: 0x08bf068f (1680 start, 2240 end)
>(II):              HSYNC_A: 0x07a706f7 (1784 start, 1960 end)
>(II):             VTOTAL_A: 0x04400419 (1050 active, 1089 total)
>(II):             VBLANK_A: 0x04400419 (1050 start, 1089 end)
>(II):              VSYNC_A: 0x0422041c (1053 start, 1059 end)
>(II):            BCLRPAT_A: 0x00000000
>(II):         VSYNCSHIFT_A: 0x00000000
>(II):             DSPBCNTR: 0xd9000400 (enabled, pipe B)
>(II):           DSPBSTRIDE: 0x00003200 (12800 bytes)
>(II):              DSPBPOS: 0x00000000 (0, 0)
>(II):             DSPBSIZE: 0x00000000 (1, 1)
>(II):             DSPBBASE: 0x00001a40
>(II):             DSPBSURF: 0x01f96000
>(II):          DSPBTILEOFF: 0x00000690
>(II):            PIPEBCONF: 0xc0000000 (enabled, active)
>(II):             PIPEBSRC: 0x05770419 (1400, 1050)
>(II):            PIPEBSTAT: 0x00400206 (status: LBLC_EVENT_ENABLE VSYNC_INT_STATUS SVBLANK_INT_STATUS VBLANK_INT_STATUS)
>(II):                 FPB0: 0x00051109 (n = 5, m1 = 17, m2 = 9)
>(II):                 FPB1: 0x00031108 (n = 3, m1 = 17, m2 = 8)
>(II):               DPLL_B: 0x98016c00 (enabled, non-dvo, spread spectrum clock, LVDS mode, p1 = 1, p2 = 14)
>(II):            DPLL_B_MD: 0x00000000
>(II):             HTOTAL_B: 0x06970577 (1400 active, 1688 total)
>(II):             HBLANK_B: 0x06970577 (1400 start, 1688 end)
>(II):              HSYNC_B: 0x061705a7 (1448 start, 1560 end)
>(II):             VTOTAL_B: 0x04290419 (1050 active, 1066 total)
>(II):             VBLANK_B: 0x04290419 (1050 start, 1066 end)
>(II):              VSYNC_B: 0x041d041a (1051 start, 1054 end)
>(II):            BCLRPAT_B: 0x00000000
>(II):         VSYNCSHIFT_B: 0x00000000
>(II):    VCLK_DIVISOR_VGA0: 0x00031108
>(II):    VCLK_DIVISOR_VGA1: 0x00031406
>(II):        VCLK_POST_DIV: 0x00020002
>(II):             VGACNTRL: 0x80000000 (disabled)
>(II):               TV_CTL: 0x000c00c0
>(II):               TV_DAC: 0x70000000
>(II):             TV_CSC_Y: 0x0332012d
>(II):            TV_CSC_Y2: 0x07d30104
>(II):             TV_CSC_U: 0x0733052d
>(II):            TV_CSC_U2: 0x05c70200
>(II):             TV_CSC_V: 0x0340030c
>(II):            TV_CSC_V2: 0x06d00200
>(II):         TV_CLR_KNOBS: 0x00404000
>(II):         TV_CLR_LEVEL: 0x010b00e1
>(II):           TV_H_CTL_1: 0x00400359
>(II):           TV_H_CTL_2: 0x80480022
>(II):           TV_H_CTL_3: 0x007c0344
>(II):           TV_V_CTL_1: 0x00f01415
>(II):           TV_V_CTL_2: 0x00060607
>(II):           TV_V_CTL_3: 0x80120001
>(II):           TV_V_CTL_4: 0x000900f0
>(II):           TV_V_CTL_5: 0x000a00f0
>(II):           TV_V_CTL_6: 0x000900f0
>(II):           TV_V_CTL_7: 0x000a00f0
>(II):          TV_SC_CTL_1: 0xc1710087
>(II):          TV_SC_CTL_2: 0x6b405140
>(II):          TV_SC_CTL_3: 0x00000000
>(II):           TV_WIN_POS: 0x00360024
>(II):          TV_WIN_SIZE: 0x02640198
>(II):      TV_FILTER_CTL_1: 0x80000afb
>(II):      TV_FILTER_CTL_2: 0x000292d3
>(II):      TV_FILTER_CTL_3: 0x00014969
>(II):        TV_CC_CONTROL: 0x00000000
>(II):           TV_CC_DATA: 0x00000000
>(II):          TV_H_LUMA_0: 0xb1403000
>(II):         TV_H_LUMA_59: 0x0000b060
>(II):        TV_H_CHROMA_0: 0xb1403000
>(II):       TV_H_CHROMA_59: 0x0000b060
>(II):         FBC_CFB_BASE: 0x00000000
>(II):          FBC_LL_BASE: 0x00000000
>(II):          FBC_CONTROL: 0x00000000
>(II):          FBC_COMMAND: 0x00000000
>(II):           FBC_STATUS: 0x20000000
>(II):         FBC_CONTROL2: 0x00000000
>(II):        FBC_FENCE_OFF: 0x00000000
>(II):          FBC_MOD_NUM: 0x00000000
>(II):              MI_MODE: 0x00000200
>(II):         MI_ARB_STATE: 0x00000044
>(II):       MI_RDRET_STATE: 0x00000000
>(II):              ECOSKPD: 0x00000307
>(II):                 DP_B: 0x00000000
>(II):       DPB_AUX_CH_CTL: 0x00000000
>(II):     DPB_AUX_CH_DATA1: 0x00000000
>(II):     DPB_AUX_CH_DATA2: 0x00000000
>(II):     DPB_AUX_CH_DATA3: 0x00000000
>(II):     DPB_AUX_CH_DATA4: 0x00000000
>(II):     DPB_AUX_CH_DATA5: 0x00000000
>(II):                 DP_C: 0x00000000
>(II):       DPC_AUX_CH_CTL: 0x00000000
>(II):     DPC_AUX_CH_DATA1: 0x00000000
>(II):     DPC_AUX_CH_DATA2: 0x00000000
>(II):     DPC_AUX_CH_DATA3: 0x00000000
>(II):     DPC_AUX_CH_DATA4: 0x00000000
>(II):     DPC_AUX_CH_DATA5: 0x00000000
>(II):                 DP_D: 0x00000000
>(II):       DPD_AUX_CH_CTL: 0x00000000
>(II):     DPD_AUX_CH_DATA1: 0x00000000
>(II):     DPD_AUX_CH_DATA2: 0x00000000
>(II):     DPD_AUX_CH_DATA3: 0x00000000
>(II):     DPD_AUX_CH_DATA4: 0x00000000
>(II):     DPD_AUX_CH_DATA5: 0x00000000
>(II):        FENCE START 0: 0x00000000 (disabled, X tile walk,    0 pitch, 0x00000000 start)
>(II):          FENCE END 0: 0x00000000 (                                   0x00000000 end)
>(II):        FENCE START 1: 0x00000000 (disabled, X tile walk,    0 pitch, 0x00000000 start)
>(II):          FENCE END 1: 0x00000000 (                                   0x00000000 end)
>(II):        FENCE START 2: 0x00000000 (disabled, X tile walk,    0 pitch, 0x00000000 start)
>(II):          FENCE END 2: 0x00000000 (                                   0x00000000 end)
>(II):        FENCE START 3: 0x01f9618d ( enabled, X tile walk, 12672 pitch, 0x01f96000 start)
>(II):          FENCE END 3: 0x02f95000 (                                   0x02f95000 end)
>(II):        FENCE START 4: 0x00000000 (disabled, X tile walk,    0 pitch, 0x00000000 start)
>(II):          FENCE END 4: 0x00000000 (                                   0x00000000 end)
>(II):        FENCE START 5: 0x00000000 (disabled, X tile walk,    0 pitch, 0x00000000 start)
>(II):          FENCE END 5: 0x00000000 (                                   0x00000000 end)
>(II):        FENCE START 6: 0x00000000 (disabled, X tile walk,    0 pitch, 0x00000000 start)
>(II):          FENCE END 6: 0x00000000 (                                   0x00000000 end)
>(II):        FENCE START 7: 0x00000000 (disabled, X tile walk,    0 pitch, 0x00000000 start)
>(II):          FENCE END 7: 0x00000000 (                                   0x00000000 end)
>(II):        FENCE START 8: 0x00000000 (disabled, X tile walk,    0 pitch, 0x00000000 start)
>(II):          FENCE END 8: 0x00000000 (                                   0x00000000 end)
>(II):        FENCE START 9: 0x00000000 (disabled, X tile walk,    0 pitch, 0x00000000 start)
>(II):          FENCE END 9: 0x00000000 (                                   0x00000000 end)
>(II):       FENCE START 10: 0x00000000 (disabled, X tile walk,    0 pitch, 0x00000000 start)
>(II):         FENCE END 10: 0x00000000 (                                   0x00000000 end)
>(II):       FENCE START 11: 0x00000000 (disabled, X tile walk,    0 pitch, 0x00000000 start)
>(II):         FENCE END 11: 0x00000000 (                                   0x00000000 end)
>(II):       FENCE START 12: 0x00000000 (disabled, X tile walk,    0 pitch, 0x00000000 start)
>(II):         FENCE END 12: 0x00000000 (                                   0x00000000 end)
>(II):       FENCE START 13: 0x00000000 (disabled, X tile walk,    0 pitch, 0x00000000 start)
>(II):         FENCE END 13: 0x00000000 (                                   0x00000000 end)
>(II):       FENCE START 14: 0x00000000 (disabled, X tile walk,    0 pitch, 0x00000000 start)
>(II):         FENCE END 14: 0x00000000 (                                   0x00000000 end)
>(II):       FENCE START 15: 0x00000000 (disabled, X tile walk,    0 pitch, 0x00000000 start)
>(II):         FENCE END 15: 0x00000000 (                                   0x00000000 end)
>(II): pipe A dot 145920 n 3 m1 11 m2 9 p1 1 p2 10
>(II): pipe B dot 108163 n 5 m1 17 m2 9 p1 1 p2 14
>(II): DumpRegsEnd

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Attachments on bug 22262: 26942 | 26943 | 26944 | 26945 | 26947 | 26948 | 27213 | 27240 | 27441 | 27442 | 27445 | 27450 | 27708 | 27781

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