Attachment 26994 Details for Bug 22317 – nv17_interlace.patch

[patch] nv17_interlace.patch

nv17_interlace.patch (text/plain), 2.99 KB, created by Francisco Jerez on 2009-06-21 04:22:31 UTC

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Creator: Francisco Jerez

Created: 2009-06-21 04:22:31 UTC

Size: 2.99 KB

patch

obsolete

>diff --git a/src/nouveau_hw.c b/src/nouveau_hw.c
>index 7d210d7..a0d8121 100644
>--- a/src/nouveau_hw.c
>+++ b/src/nouveau_hw.c
>@@ -849,6 +849,7 @@ nv_save_state_ext(NVPtr pNv, int head, struct nouveau_mode_state *state)
> 	rd_cio_state(pNv, head, regp, NV_CIO_CRE_SCRATCH4__INDEX);
> 	if (pNv->Architecture >= NV_ARCH_10) {
> 		rd_cio_state(pNv, head, regp, NV_CIO_CRE_EBR_INDEX);
>+                rd_cio_state(pNv, head, regp, NV_CIO_CRE_43);
> 		rd_cio_state(pNv, head, regp, NV_CIO_CRE_CSB);
> 		rd_cio_state(pNv, head, regp, NV_CIO_CRE_4B);
> 		rd_cio_state(pNv, head, regp, NV_CIO_CRE_TVOUT_LATENCY);
>@@ -934,6 +935,7 @@ static void nv_load_state_ext(NVPtr pNv, int head, struct nouveau_mode_state *st
> 	wr_cio_state(pNv, head, regp, NV_CIO_CRE_SCRATCH4__INDEX);
> 	if (pNv->Architecture >= NV_ARCH_10) {
> 		wr_cio_state(pNv, head, regp, NV_CIO_CRE_EBR_INDEX);
>+		wr_cio_state(pNv, head, regp, NV_CIO_CRE_43);
> 		wr_cio_state(pNv, head, regp, NV_CIO_CRE_CSB);
> 		wr_cio_state(pNv, head, regp, NV_CIO_CRE_4B);
> 		wr_cio_state(pNv, head, regp, NV_CIO_CRE_TVOUT_LATENCY);
>diff --git a/src/nv_crtc.c b/src/nv_crtc.c
>index b8524fb..3432f2f 100644
>--- a/src/nv_crtc.c
>+++ b/src/nv_crtc.c
>@@ -545,7 +545,18 @@ nv_crtc_mode_set_regs(xf86CrtcPtr crtc, DisplayModePtr mode)
> 	if (pNv->Architecture == NV_ARCH_40)
> 		regp->gpio_ext = NVReadCRTC(pNv, 0, NV_PCRTC_GPIO_EXT);
> 
>-	regp->crtc_cfg = NV_PCRTC_CONFIG_START_ADDRESS_HSYNC;
>+        if (mode->Flags & V_INTERLACE &&
>+            (pNv->Architecture == NV_ARCH_20 ||
>+             (pNv->Architecture == NV_ARCH_10 &&
>+              (pNv->Chipset & 0x0ff0) != CHIPSET_NV10 &&
>+              (pNv->Chipset & 0x0ff0) != CHIPSET_NV15))){
>+
>+                regp->crtc_cfg = 0;
>+                regp->CRTC[NV_CIO_CRE_43] = 0x0;
>+        }else{
>+                regp->crtc_cfg = NV_PCRTC_CONFIG_START_ADDRESS_HSYNC;
>+                regp->CRTC[NV_CIO_CRE_43] = 0x1;
>+        }
> 
> 	/* Some misc regs */
> 	if (pNv->Architecture == NV_ARCH_40) {
>diff --git a/src/nv_output.c b/src/nv_output.c
>index 0979bb9..a414a85 100644
>--- a/src/nv_output.c
>+++ b/src/nv_output.c
>@@ -321,14 +321,7 @@ update_output_fields(xf86OutputPtr output, struct nouveau_encoder *det_encoder)
> 		output->interlaceAllowed = false;
> 	} else {
> 		output->doubleScanAllowed = true;
>-		if (pNv->Architecture == NV_ARCH_20 ||
>-		   (pNv->Architecture == NV_ARCH_10 &&
>-		    (pNv->Chipset & 0x0ff0) != CHIPSET_NV10 &&
>-		    (pNv->Chipset & 0x0ff0) != CHIPSET_NV15))
>-			/* HW is broken */
>-			output->interlaceAllowed = false;
>-		else
>-			output->interlaceAllowed = true;
>+                output->interlaceAllowed = true;
> 	}
> }
> 
>diff --git a/src/nvreg.h b/src/nvreg.h
>index 060e243..7cad8fa 100644
>--- a/src/nvreg.h
>+++ b/src/nvreg.h
>@@ -288,6 +288,7 @@
> #		define NV_CIO_CRE_EBR_VDE_11		2:2
> #		define NV_CIO_CRE_EBR_VRS_11		4:4
> #		define NV_CIO_CRE_EBR_VBS_11		6:6
>+#	define NV_CIO_CRE_43                    0x43
> #	define NV_CIO_CRE_44			0x44	/* head control */
> #	define NV_CIO_CRE_CSB			0x45	/* colour saturation boost */
> #	define NV_CIO_CRE_RCR			0x46

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