Attachment 27883 Details for Bug 22742 – prey console output with DEBUG_CMDBUF defined to 1 and RADEON_DEBUG=all

prey console output with DEBUG_CMDBUF defined to 1 and RADEON_DEBUG=all

prey-output.txt (text/plain), 229.04 KB, created by Fabio Pedretti on 2009-07-21 08:40:14 UTC

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Description:

Filename:

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Creator: Fabio Pedretti

Created: 2009-07-21 08:40:14 UTC

Size: 229.04 KB

patch

obsolete

>r300NewTextureObject( 0xc481168 (target = GL_TEXTURE_2D_ARRAY_EXT) )
>r300NewTextureObject( 0xc4813d0 (target = GL_TEXTURE_1D_ARRAY_EXT) )
>r300NewTextureObject( 0xc4f3188 (target = GL_TEXTURE_CUBE_MAP) )
>r300NewTextureObject( 0xc4f33f0 (target = GL_TEXTURE_3D) )
>r300NewTextureObject( 0xc4f3658 (target = GL_TEXTURE_RECTANGLE_ARB) )
>r300NewTextureObject( 0xc50b2d0 (target = GL_TEXTURE_2D) )
>r300NewTextureObject( 0xc50b538 (target = GL_TEXTURE_1D) )
>r300NewTextureObject( 0xc5fc868 (target = GL_TEXTURE_1D) )
>r300NewTextureObject( 0xc5fcad0 (target = GL_TEXTURE_2D) )
>r300NewTextureObject( 0xc5fcd38 (target = GL_TEXTURE_3D) )
>r300NewTextureObject( 0xc5fcfa0 (target = GL_TEXTURE_CUBE_MAP) )
>r300NewTextureObject( 0xc5fd208 (target = GL_TEXTURE_RECTANGLE_ARB) )
>r300NewTextureObject( 0xc5fd470 (target = GL_TEXTURE_1D_ARRAY_EXT) )
>r300NewTextureObject( 0xc5fd6d8 (target = GL_TEXTURE_2D_ARRAY_EXT) )
>Using 8 maximum texture units..
>sizeof(drm_r300_cmd_header_t)=4
>sizeof(drm_radeon_cmd_buffer_t)=16
>Allocating 65536 bytes command buffer (max state is 25920 bytes)
>r300ResetHwState
>r300Enable( GL_DEPTH_TEST = GL_FALSE )
>r300Enable( GL_STENCIL_TEST = GL_FALSE )
>r300Enable( GL_ALPHA_TEST = GL_FALSE )
>r300Enable( GL_POLYGON_OFFSET_POINT = GL_FALSE )
>r300Enable( GL_POLYGON_OFFSET_LINE = GL_FALSE )
>r300Enable( GL_POLYGON_OFFSET_FILL = GL_FALSE )
>radeonMakeCurrent ctx 0xc5e53b8 dfb 0xc917a60 rfb 0xc917a60
>r300Enable( GL_DEPTH_TEST = GL_FALSE )
>r300Enable( GL_STENCIL_TEST = GL_FALSE )
>r300Enable( GL_DEPTH_TEST = GL_FALSE )
>r300Enable( GL_STENCIL_TEST = GL_FALSE )
>End radeonMakeCurrent
>radeonMakeCurrent ctx 0xc5e53b8 dfb 0xc917a60 rfb 0xc917a60
>r300Enable( GL_DEPTH_TEST = GL_FALSE )
>r300Enable( GL_STENCIL_TEST = GL_FALSE )
>r300Enable( GL_DEPTH_TEST = GL_FALSE )
>r300Enable( GL_STENCIL_TEST = GL_FALSE )
>End radeonMakeCurrent
>Prey 1.4.119 linux-x86 Nov 25 2008 23:53:42
>found interface lo - loopback
>found interface eth0 - 10.33.4.8/255.255.0.0
>found interface virbr0 - 192.168.122.1/255.255.255.0
>------ Initializing File System ------
>Loaded pk4 /home/fabio/games/prey-demo/base/demo00.pk4 with checksum 0x86294060
>Current search path:
>/home/fabio/.prey-demo/base
>/home/fabio/games/prey-demo/base
>/home/fabio/games/prey-demo/base/demo00.pk4 (11273 files)
>game DLL: 0x0 in pak: 0x0
>Addon pk4s:
>file system initialized.
>--------------------------------------
>
>Running in restricted demo mode.
>
>----- Initializing Decls -----
>------------------------------
>------- Initializing renderSystem --------
>using ARB renderSystem
>renderSystem initialized.
>--------------------------------------
>2647 strings read from strings/english001.lang
>Couldn't open journal files
>couldn't exec editor.cfg
>execing default.cfg
>execing preyconfig.cfg
>couldn't exec autoexec.cfg
>2648 strings read from strings/italian.lang
>----- Initializing Sound System ------
>sound system initialized.
>--------------------------------------
>----- R_InitOpenGL -----
>Setup SDL display connection
>Initializing OpenGL display
>Loading GL driver '(default)' through SDL
>GL_RENDERER: Mesa DRI R300 (RV530 71C5) 20090101 x86/MMX/SSE2 TCL
>GL_VENDOR: DRI R300 Project
>GL_VERSION: 1.4 Mesa 7.6-devel
>GL_EXTENSIONS: GL_ARB_depth_texture GL_ARB_draw_buffers GL_ARB_fragment_program GL_ARB_imaging GL_ARB_multisample GL_ARB_multitexture GL_ARB_point_parameters GL_ARB_shadow GL_ARB_shadow_ambient GL_ARB_texture_border_clamp GL_ARB_texture_compression GL_ARB_texture_cube_map GL_ARB_texture_env_add GL_ARB_texture_env_combine GL_ARB_texture_env_crossbar GL_ARB_texture_env_dot3 GL_MESAX_texture_float GL_ARB_texture_mirrored_repeat GL_ARB_texture_rectangle GL_ARB_transpose_matrix GL_ARB_vertex_buffer_object GL_ARB_vertex_program GL_ARB_window_pos GL_EXT_abgr GL_EXT_bgra GL_EXT_blend_color GL_EXT_blend_equation_separate GL_EXT_blend_func_separate GL_EXT_blend_logic_op GL_EXT_blend_minmax GL_EXT_blend_subtract GL_EXT_compiled_vertex_array GL_EXT_convolution GL_EXT_copy_texture GL_EXT_draw_range_elements GL_EXT_fog_coord GL_EXT_gpu_program_parameters GL_EXT_histogram GL_EXT_multi_draw_arrays GL_EXT_packed_depth_stencil GL_EXT_packed_pixels GL_EXT_point_parameters GL_EXT_polygon_offset GL_EXT_rescale_normal GL_EXT_secondary_color GL_EXT_separate_specular_color GL_EXT_shadow_funcs GL_EXT_stencil_two_side GL_EXT_stencil_wrap GL_EXT_subtexture GL_EXT_texture GL_EXT_texture3D GL_EXT_texture_edge_clamp GL_EXT_texture_env_add GL_EXT_texture_env_combine GL_EXT_texture_env_dot3 GL_EXT_texture_filter_anisotropic GL_EXT_texture_lod_bias GL_EXT_texture_mirror_clamp GL_EXT_texture_object GL_EXT_texture_rectangle GL_EXT_texture_sRGB GL_EXT_vertex_array GL_EXT_vertex_array_bgra GL_APPLE_packed_pixels GL_ATI_blend_equation_separate GL_ATI_texture_env_combine3 GL_ATI_texture_mirror_once GL_ATI_separate_stencil GL_IBM_multimode_draw_arrays GL_IBM_rasterpos_clip GL_IBM_texture_mirrored_repeat GL_INGR_blend_func_separate GL_MESA_pack_invert GL_MESA_ycbcr_texture GL_MESA_window_pos GL_NV_blend_square GL_NV_light_max_exponent GL_NV_texture_rectangle GL_NV_texgen_reflection GL_NV_vertex_program GL_OES_read_format GL_SGI_color_matrix GL_SGI_color_table GL_SGIS_generate_mipmap GL_SGIS_texture_border_clamp GL_SGIS_texture_edge_clamp GL_SGIS_texture_lod GL_SUN_multi_draw_arrays
>
>------- Input Initialization -------
>------------------------------------
>...initializing OpenAL
>...calling LoadLibrary( './openal.so' ): dlopen './openal.so' failed: ./openal.so: cannot open shared object file: No such file or directory
>failed
>...initializing OpenAL
>...calling LoadLibrary( './openal.so' ): dlopen './openal.so' failed: ./openal.so: cannot open shared object file: No such file or directory
>failed
>------ SDL Sound Initialization ------
>SDL is using audio backend 'pulse'.
>allocated a mix buffer of 32768 bytes
>SDL_AudioSpec: 44100 freq, S16LSB, 2 channels, 512 samples.
>Opening audio device...
>Audio device is ready.
>--------------------------------------
>...using GL_ARr300NewTextureObject( 0xc983770 (target = GL_FALSE) )
>r300Enable( GL_TEXTURE_2D = GL_TRUE )
>level 0, face 0: rs:32 16x16 at 0
>level 1, face 0: rs:32 8x8 at 512
>level 2, face 0: rs:32 4x4 at 768
>level 3, face 0: rs:32 2x2 at 896
>level 4, face 0: rs:32 1x1 at 960
>r300TexParameter( GL_TEXTURE_MIN_FILTER )
>r300NewTextureObject( 0xc984f88 (target = GL_FALSE) )
>level 0, face 0: rs:32 16x16 at 0
>level 1, face 0: rs:32 8x8 at 512
>level 2, face 0: rs:32 4x4 at 768
>level 3, face 0: rs:32 2x2 at 896
>level 4, face 0: rs:32 1x1 at 960
>r300TexParameter( GL_TEXTURE_MIN_FILTER )
>r300NewTextureObject( 0xc986768 (target = GL_FALSE) )
>level 0, face 0: rs:32 16x16 at 0
>level 1, face 0: rs:32 8x8 at 512
>level 2, face 0: rs:32 4x4 at 768
>level 3, face 0: rs:32 2x2 at 896
>level 4, face 0: rs:32 1x1 at 960
>r300TexParameter( GL_TEXTURE_MIN_FILTER )
>r300NewTextureObject( 0xc987f48 (target = GL_FALSE) )
>level 0, face 0: rs:32 32x32 at 0
>level 1, face 0: rs:32 16x16 at 1024
>level 2, face 0: rs:32 8x8 at 1536
>level 3, face 0: rs:32 4x4 at 1792
>level 4, face 0: rs:32 2x2 at 1920
>level 5, face 0: rs:32 1x1 at 1984
>r300TexParameter( GL_TEXTURE_MIN_FILTER )
>r300TexParameter( GL_TEXTURE_WRAP_S )
>r300TexParameter( GL_TEXTURE_WRAP_T )
>r300TexParameter( GL_TEXTURE_BORDER_COLOR )
>r300NewTextureObject( 0xc9897a8 (target = GL_FALSE) )
>level 0, face 0: rs:32 2x2 at 0
>level 1, face 0: rs:32 1x1 at 64
>r300TexParameter( GL_TEXTURE_MIN_FILTER )
>r300NewTextureObject( 0xc98ae08 (target = GL_FALSE) )
>r300Enable( GL_TEXTURE_2D = GL_FALSE )
>r300Enable( GL_TEXTURE_CUBE_MAP = GL_TRUE )
>r300TexParameter( GL_TEXTURE_WRAP_S )
>r300TexParameter( GL_TEXTURE_WRAP_T )
>r300TexParameter( GL_TEXTURE_MIN_FILTER )
>level 0, face 0: rs:32 2x2 at 0
>level 0, face 1: rs:32 2x2 at 64
>level 0, face 2: rs:32 2x2 at 128
>level 0, face 3: rs:32 2x2 at 192
>level 0, face 4: rs:32 2x2 at 256
>level 0, face 5: rs:32 2x2 at 320
>level 1, face 0: rs:32 1x1 at 384
>level 1, face 1: rs:32 1x1 at 416
>level 1, face 2: rs:32 1x1 at 448
>level 1, face 3: rs:32 1x1 at 480
>level 1, face 4: rs:32 1x1 at 512
>level 1, face 5: rs:32 1x1 at 544
>r300NewTextureObject( 0xc98c968 (target = GL_FALSE) )
>r300Enable( GL_TEXTURE_CUBE_MAP = GL_FALSE )
>r300Enable( GL_TEXTURE_2D = GL_TRUE )
>level 0, face 0: rs:256 256x1 at 0
>level 1, face 0: rs:128 128x1 at 256
>level 2, face 0: rs:64 64x1 at 384
>level 3, face 0: rs:32 32x1 at 448
>level 4, face 0: rs:32 16x1 at 480
>level 5, face 0: rs:32 8x1 at 512
>level 6, face 0: rs:32 4x1 at 544
>level 7, face 0: rs:32 2x1 at 576
>level 8, face 0: rs:32 1x1 at 608
>r300TexParameter( GL_TEXTURE_MIN_FILTER )
>r300TexParameter( GL_TEXTURE_WRAP_S )
>r300TexParameter( GL_TEXTURE_WRAP_T )
>r300NewTextureObject( 0xc98e348 (target = GL_FALSE) )
>level 0, face 0: rs:256 256x1 at 0
>level 1, face 0: rs:128 128x1 at 256
>level 2, face 0: rs:64 64x1 at 384
>level 3, face 0: rs:32 32x1 at 448
>level 4, face 0: rs:32 16x1 at 480
>level 5, face 0: rs:32 8x1 at 512
>level 6, face 0: rs:32 4x1 at 544
>level 7, face 0: rs:32 2x1 at 576
>level 8, face 0: rs:32 1x1 at 608
>r300TexParameter( GL_TEXTURE_MIN_FILTER )
>r300TexParameter( GL_TEXTURE_MAG_FILTER )
>r300TexParameter( GL_TEXTURE_WRAP_S )
>r300TexParameter( GL_TEXTURE_WRAP_T )
>r300NewTextureObject( 0xc98fd28 (target = GL_FALSE) )
>level 0, face 0: rs:256 256x1 at 0
>level 1, face 0: rs:128 128x1 at 256
>level 2, face 0: rs:64 64x1 at 384
>level 3, face 0: rs:32 32x1 at 448
>level 4, face 0: rs:32 16x1 at 480
>level 5, face 0: rs:32 8x1 at 512
>level 6, face 0: rs:32 4x1 at 544
>level 7, face 0: rs:32 2x1 at 576
>level 8, face 0: rs:32 1x1 at 608
>r300TexParameter( GL_TEXTURE_MIN_FILTER )
>r300TexParameter( GL_TEXTURE_MAG_FILTER )
>r300TexParameter( GL_TEXTURE_WRAP_S )
>r300TexParameter( GL_TEXTURE_WRAP_T )
>r300NewTextureObject( 0xc991708 (target = GL_FALSE) )
>level 0, face 0: rs:32 2x1 at 0
>level 1, face 0: rs:32 1x1 at 32
>r300TexParameter( GL_TEXTURE_MIN_FILTER )
>r300TexParameter( GL_TEXTURE_MAG_FILTER )
>r300TexParameter( GL_TEXTURE_WRAP_S )
>r300TexParameter( GL_TEXTURE_WRAP_T )
>r300NewTextureObject( 0xc992d68 (target = GL_FALSE) )
>level 0, face 0: rs:512 128x128 at 0
>level 1, face 0: rs:256 64x64 at 65536
>level 2, face 0: rs:128 32x32 at 81920
>level 3, face 0: rs:64 16x16 at 86016
>level 4, face 0: rs:32 8x8 at 87040
>level 5, face 0: rs:32 4x4 at 87296
>level 6, face 0: rs:32 2x2 at 87424
>level 7, face 0: rs:32 1x1 at 87488
>r300TexParameter( GL_TEXTURE_MIN_FILTER )
>r300TexParameter( GL_TEXTURE_WRAP_S )
>r300TexParameter( GL_TEXTURE_WRAP_T )
>r300NewTextureObject( 0xc9933c0 (target = GL_FALSE) )
>level 0, face 0: rs:256 64x64 at 0
>level 1, face 0: rs:128 32x32 at 16384
>level 2, face 0: rs:64 16x16 at 20480
>level 3, face 0: rs:32 8x8 at 21504
>level 4, face 0: rs:32 4x4 at 21760
>level 5, face 0: rs:32 2x2 at 21888
>level 6, face 0: rs:32 1x1 at 21952
>r300TexParameter( GL_TEXTURE_MIN_FILTER )
>r300TexParameter( GL_TEXTURE_WRAP_S )
>r300TexParameter( GL_TEXTURE_WRAP_T )
>r300NewTextureObject( 0xc999d10 (target = GL_FALSE) )
>r300Enable( GL_TEXTURE_2D = GL_FALSE )
>r300Enable( GL_TEXTURE_CUBE_MAP = GL_TRUE )
>r300TexParameter( GL_TEXTURE_WRAP_S )
>r300TexParameter( GL_TEXTURE_WRAP_T )
>r300TexParameter( GL_TEXTURE_MIN_FILTER )
>level 0, face 0: rs:128 32x32 at 0
>level 0, face 1: rs:128 32x32 at 4096
>level 0, face 2: rs:128 32x32 at 8192
>level 0, face 3: rs:128 32x32 at 12288
>level 0, face 4: rs:128 32x32 at 16384
>level 0, face 5: rs:128 32x32 at 20480
>r300NewTextureObject( 0xc9bbe10 (target = GL_FALSE) )
>r300Enable( GL_TEXTURE_CUBE_MAP = GL_FALSE )
>r300Enable( GL_TEXTURE_2D = GL_TRUE )
>level 0, face 0: rs:64 64x16 at 0
>level 1, face 0: rs:32 32x8 at 1024
>level 2, face 0: rs:32 16x4 at 1280
>level 3, face 0: rs:32 8x2 at 1408
>level 4, face 0: rs:32 4x1 at 1472
>level 5, face 0: rs:32 2x1 at 1504
>level 6, face 0: rs:32 1x1 at 1536
>r300TexParameter( GL_TEXTURE_MIN_FILTER )
>r300TexParameter( GL_TEXTURE_WRAP_S )
>r300TexParameter( GL_TEXTURE_WRAP_T )
>r300NewTextureObject( 0xc9bd300 (target = GL_FALSE) )
>level 0, face 0: rs:128 32x4 at 0
>level 1, face 0: rs:64 16x2 at 512
>level 2, face 0: rs:32 8x1 at 640
>level 3, face 0: rs:32 4x1 at 672
>level 4, face 0: rs:32 2x1 at 704
>level 5, face 0: rs:32 1x1 at 736
>r300TexParameter( GL_TEXTURE_MIN_FILTER )
>r300TexParameter( GL_TEXTURE_WRAP_S )
>r300TexParameter( GL_TEXTURE_WRAP_T )
>r300NewTextureObject( 0xc9be7f0 (target = GL_FALSE) )
>level 0, face 0: rs:64 16x16 at 0
>level 1, face 0: rs:32 8x8 at 1024
>level 2, face 0: rs:32 4x4 at 1280
>level 3, face 0: rs:32 2x2 at 1408
>level 4, face 0: rs:32 1x1 at 1472
>r300TexParameter( GL_TEXTURE_MIN_FILTER )
>r300NewTextureObject( 0xc9bfce0 (target = GL_FALSE) )
>level 0, face 0: rs:64 16x16 at 0
>level 1, face 0: rs:32 8x8 at 1024
>level 2, face 0: rs:32 4x4 at 1280
>level 3, face 0: rs:32 2x2 at 1408
>level 4, face 0: rs:32 1x1 at 1472
>r300TexParameter( GL_TEXTURE_MIN_FILTER )
>r300NewTextureObject( 0xc9c11d0 (target = GL_FALSE) )
>level 0, face 0: rs:64 16x16 at 0
>level 1, face 0: rs:32 8x8 at 1024
>level 2, face 0: rs:32 4x4 at 1280
>level 3, face 0: rs:32 2x2 at 1408
>level 4, face 0: rs:32 1x1 at 1472
>r300TexParameter( GL_TEXTURE_MIN_FILTER )
>r300NewTextureObject( 0xc9c26c0 (target = GL_FALSE) )
>level 0, face 0: rs:64 16x16 at 0
>level 1, face 0: rs:32 8x8 at 1024
>level 2, face 0: rs:32 4x4 at 1280
>level 3, face 0: rs:32 2x2 at 1408
>level 4, face 0: rs:32 1x1 at 1472
>r300TexParameter( GL_TEXTURE_MIN_FILTER )
>r300NewTextureObject( 0xc9c3bb0 (target = GL_FALSE) )
>level 0, face 0: rs:64 16x16 at 0
>level 1, face 0: rs:32 8x8 at 1024
>level 2, face 0: rs:32 4x4 at 1280
>level 3, face 0: rs:32 2x2 at 1408
>level 4, face 0: rs:32 1x1 at 1472
>r300TexParameter( GL_TEXTURE_MIN_FILTER )
>r300NewTextureObject( 0xc9c50a0 (target = GL_FALSE) )
>level 0, face 0: rs:64 16x16 at 0
>level 1, face 0: rs:32 8x8 at 1024
>level 2, face 0: rs:32 4x4 at 1280
>level 3, face 0: rs:32 2x2 at 1408
>level 4, face 0: rs:32 1x1 at 1472
>r300TexParameter( GL_TEXTURE_MIN_FILTER )
>r300NewTextureObject( 0xc9c6610 (target = GL_FALSE) )
>level 0, face 0: rs:64 16x16 at 0
>level 1, face 0: rs:32 8x8 at 1024
>level 2, face 0: rs:32 4x4 at 1280
>level 3, face 0: rs:32 2x2 at 1408
>level 4, face 0: rs:32 1x1 at 1472
>r300TexParameter( GL_TEXTURE_MIN_FILTER )
>r300NewTextureObject( 0xc9c7df0 (target = GL_FALSE) )
>level 0, face 0: rs:64 16x16 at 0
>level 1, face 0: rs:32 8x8 at 1024
>level 2, face 0: rs:32 4x4 at 1280
>level 3, face 0: rs:32 2x2 at 1408
>level 4, face 0: rs:32 1x1 at 1472
>r300TexParameter( GL_TEXTURE_MIN_FILTER )
>r300NewTextureObject( 0xc9c95d0 (target = GL_FALSE) )
>level 0, face 0: rs:64 64x8 at 0
>level 1, face 0: rs:32 32x4 at 512
>level 2, face 0: rs:32 16x2 at 640
>level 3, face 0: rs:32 8x1 at 704
>level 4, face 0: rs:32 4x1 at 736
>level 5, face 0: rs:32 2x1 at 768
>level 6, face 0: rs:32 1x1 at 800
>r300TexParameter( GL_TEXTURE_MIN_FILTER )
>r300TexParameter( GL_TEXTURE_WRAP_S )
>r300TexParameter( GL_TEXTURE_WRAP_T )
>r300NewTextureObject( 0xc9daee0 (target = GL_FALSE) )
>level 0, face 0: rs:512 128x128 at 0
>level 1, face 0: rs:256 64x64 at 65536
>level 2, face 0: rs:128 32x32 at 81920
>level 3, face 0: rs:64 16x16 at 86016
>level 4, face 0: rs:32 8x8 at 87040
>level 5, face 0: rs:32 4x4 at 87296
>level 6, face 0: rs:32 2x2 at 87424
>level 7, face 0: rs:32 1x1 at 87488
>r300TexParameter( GL_TEXTURE_MIN_FILTER )
>r300TexParameter( GL_TEXTURE_WRAP_S )
>r300TexParameter( GL_TEXTURE_WRAP_T )
>r300NewTextureObject( 0xc9db538 (target = GL_FALSE) )
>level 0, face 0: rs:2048 1024x1024 at 0
>level 1, face 0: rs:1024 512x512 at 2097152
>level 2, face 0: rs:512 256x256 at 2621440
>level 3, face 0: rs:256 128x128 at 2752512
>level 4, face 0: rs:128 64x64 at 2785280
>level 5, face 0: rs:64 32x32 at 2793472
>level 6, face 0: rs:32 16x16 at 2795520
>level 7, face 0: rs:32 8x8 at 2796032
>level 8, face 0: rs:32 4x4 at 2796288
>level 9, face 0: rs:32 2x2 at 2796416
>level 10, face 0: rs:32 1x1 at 2796480
>r300TexParameter( GL_TEXTURE_MIN_FILTER )
>r300NewTextureObject( 0xc9dc0c0 (target = GL_FALSE) )
>level 0, face 0: rs:512 256x256 at 0
>level 1, face 0: rs:256 128x128 at 131072
>level 2, face 0: rs:128 64x64 at 163840
>level 3, face 0: rs:64 32x32 at 172032
>level 4, face 0: rs:32 16x16 at 174080
>level 5, face 0: rs:32 8x8 at 174592
>level 6, face 0: rs:32 4x4 at 174848
>level 7, face 0: rs:32 2x2 at 174976
>level 8, face 0: rs:32 1x1 at 175040
>r300TexParameter( GL_TEXTURE_MIN_FILTER )
>r300NewTextureObject( 0xc9dcb28 (target = GL_FALSE) )
>level 0, face 0: rs:128 64x64 at 0
>level 1, face 0: rs:64 32x32 at 8192
>level 2, face 0: rs:32 16x16 at 10240
>level 3, face 0: rs:32 8x8 at 10752
>level 4, face 0: rs:32 4x4 at 11008
>level 5, face 0: rs:32 2x2 at 11136
>level 6, face 0: rs:32 1x1 at 11200
>r300TexParameter( GL_TEXTURE_MIN_FILTER )
>r300Enable( GL_VERTEX_ARRAY = GL_TRUE )
>r300Enable( GL_TEXTURE_COORD_ARRAY = GL_TRUE )
>r300Enable( GL_DEPTH_TEST = GL_TRUE )
>r300Enable( GL_BLEND = GL_TRUE )
>r300Enable( GL_SCISSOR_TEST = GL_TRUE )
>r300Enable( GL_CULL_FACE = GL_TRUE )
>r300Enable( GL_TEXTURE_2D = GL_FALSE )
>radeonDrawBuffer GL_BACK
>r300Enable( GL_DEPTH_TEST = GL_TRUE )
>r300Enable( GL_STENCIL_TEST = GL_FALSE )
>r300Clear
>r300Enable( GL_DEPTH_TEST = GL_TRUE )
>r300Enable( GL_STENCIL_TEST = GL_FALSE )
>Reemit state after flush (from r300EmitClearState)
>radeonEmitState
>Begin reemit state
>BEGIN_BATCH(1) at 0, from cp_wait:185
>BEGIN_BATCH(2) at 1, from r300_vtbl_pre_emit_atoms:234
>BEGIN_BATCH(1) at 3, from end_3d:162
>Begin dirty state
>BEGIN_BATCH(1) at 4, from cp_wait:185
>BEGIN_BATCH(2) at 5, from r300_vtbl_pre_emit_atoms:234
>BEGIN_BATCH(1) at 7, from end_3d:162
>  emit vpt 7/7
>      vpt[0]: cmdpacket0 (first reg=0x1d98, count=6)
>      vpt[1]: 0x1d98 = 43a00000
>      vpt[2]: 0x1d9c = 43a00000
>      vpt[3]: 0x1da0 = c3700000
>      vpt[4]: 0x1da4 = 43700000
>      vpt[5]: 0x1da8 = 3f000000
>      vpt[6]: 0x1dac = 3f000000
>BEGIN_BATCH(7) at 8, from radeonEmitAtoms:996
>  emit vap_cntl 4/4
>      vap_cntl[0]: cmdpacket0 (first reg=0x2284, count=1)
>      vap_cntl[1]: 0x2284 = 00000000
>      vap_cntl[2]: cmdpacket0 (first reg=0x2080, count=1)
>      vap_cntl[3]: 0x2080 = 00b0056a
>BEGIN_BATCH(4) at 15, from radeonEmitAtoms:996
>  emit vap_index_offset 2/2
>      vap_index_offset[0]: cmdpacket0 (first reg=0x208c, count=1)
>      vap_index_offset[1]: 0x208c = 00000000
>BEGIN_BATCH(2) at 19, from radeonEmitAtoms:996
>  emit vte 3/3
>      vte[0]: cmdpacket0 (first reg=0x20b0, count=2)
>      vte[1]: 0x20b0 = 0000043f
>      vte[2]: 0x20b4 = 00000008
>BEGIN_BATCH(3) at 21, from radeonEmitAtoms:996
>  emit vap_vf_max_vtx_indx 3/3
>      vap_vf_max_vtx_indx[0]: cmdpacket0 (first reg=0x2134, count=2)
>      vap_vf_max_vtx_indx[1]: 0x2134 = 00ffffff
>      vap_vf_max_vtx_indx[2]: 0x2138 = 00000000
>BEGIN_BATCH(3) at 24, from radeonEmitAtoms:996
>  emit vap_cntl_status 2/2
>      vap_cntl_status[0]: cmdpacket0 (first reg=0x2140, count=1)
>      vap_cntl_status[1]: 0x2140 = 00000000
>BEGIN_BATCH(2) at 27, from radeonEmitAtoms:996
>  emit vir[0] 2/9
>      vir[0][0]: cmdpacket0 (first reg=0x2150, count=1)
>      vir[0][1]: 0x2150 = 00000000
>BEGIN_BATCH(2) at 29, from radeonEmitAtoms:996
>  emit vir[1] 2/9
>      vir[1][0]: cmdpacket0 (first reg=0x21e0, count=1)
>      vir[1][1]: 0x21e0 = 00000000
>BEGIN_BATCH(2) at 31, from radeonEmitAtoms:996
>  emit vic 3/3
>      vic[0]: cmdpacket0 (first reg=0x2180, count=2)
>      vic[1]: 0x2180 = 00000000
>      vic[2]: 0x2184 = 00000000
>BEGIN_BATCH(3) at 33, from radeonEmitAtoms:996
>  emit vap_psc_sgn_norm_cntl 2/2
>      vap_psc_sgn_norm_cntl[0]: cmdpacket0 (first reg=0x21dc, count=1)
>      vap_psc_sgn_norm_cntl[1]: 0x21dc = aaaaaaaa
>BEGIN_BATCH(2) at 36, from radeonEmitAtoms:996
>  emit vap_clip_cntl 2/2
>      vap_clip_cntl[0]: cmdpacket0 (first reg=0x221c, count=1)
>      vap_clip_cntl[1]: 0x221c = 00000000
>BEGIN_BATCH(2) at 38, from radeonEmitAtoms:996
>  emit vap_clip 5/5
>      vap_clip[0]: cmdpacket0 (first reg=0x2220, count=4)
>      vap_clip[1]: 0x2220 = 3f800000
>      vap_clip[2]: 0x2224 = 3f800000
>      vap_clip[3]: 0x2228 = 3f800000
>      vap_clip[4]: 0x222c = 3f800000
>BEGIN_BATCH(5) at 40, from radeonEmitAtoms:996
>  emit vap_pvs_vtx_timeout_reg 2/2
>      vap_pvs_vtx_timeout_reg[0]: cmdpacket0 (first reg=0x2288, count=1)
>      vap_pvs_vtx_timeout_reg[1]: 0x2288 = 0000ffff
>BEGIN_BATCH(2) at 45, from radeonEmitAtoms:996
>  emit vof 3/3
>      vof[0]: cmdpacket0 (first reg=0x2090, count=2)
>      vof[1]: 0x2090 = 00000000
>      vof[2]: 0x2094 = 00000000
>BEGIN_BATCH(3) at 47, from radeonEmitAtoms:996
>  emit pvs 4/4
>      pvs[0]: cmdpacket0 (first reg=0x22d0, count=3)
>      pvs[1]: 0x22d0 = 00000000
>      pvs[2]: 0x22d4 = 00000000
>      pvs[3]: 0x22d8 = 00000000
>BEGIN_BATCH(4) at 50, from radeonEmitAtoms:996
>  emit gb_enable 2/2
>      gb_enable[0]: cmdpacket0 (first reg=0x4008, count=1)
>      gb_enable[1]: 0x4008 = 00000007
>BEGIN_BATCH(2) at 54, from radeonEmitAtoms:996
>  emit gb_misc 4/4
>      gb_misc[0]: cmdpacket0 (first reg=0x4010, count=3)
>      gb_misc[1]: 0x4010 = 66666666
>      gb_misc[2]: 0x4014 = 06666666
>      gb_misc[3]: 0x4018 = 00000011
>BEGIN_BATCH(4) at 56, from emit_gb_misc:382
>  emit gb_misc2 3/3
>      gb_misc2[0]: cmdpacket0 (first reg=0x401c, count=2)
>      gb_misc2[1]: 0x401c = 00000000
>      gb_misc2[2]: 0x4020 = 00000000
>BEGIN_BATCH(3) at 60, from radeonEmitAtoms:996
>  emit txe 2/2
>      txe[0]: cmdpacket0 (first reg=0x4104, count=1)
>      txe[1]: 0x4104 = 00000000
>BEGIN_BATCH(2) at 63, from radeonEmitAtoms:996
>  emit ga_point_s0 5/5
>      ga_point_s0[0]: cmdpacket0 (first reg=0x4200, count=4)
>      ga_point_s0[1]: 0x4200 = 00000000
>      ga_point_s0[2]: 0x4204 = 00000000
>      ga_point_s0[3]: 0x4208 = 3f800000
>      ga_point_s0[4]: 0x420c = 3f800000
>BEGIN_BATCH(5) at 65, from radeonEmitAtoms:996
>  emit ga_triangle_stipple 2/2
>      ga_triangle_stipple[0]: cmdpacket0 (first reg=0x4214, count=1)
>      ga_triangle_stipple[1]: 0x4214 = 00050005
>BEGIN_BATCH(2) at 70, from radeonEmitAtoms:996
>  emit ps 2/2
>      ps[0]: cmdpacket0 (first reg=0x421c, count=1)
>      ps[1]: 0x421c = 00060006
>BEGIN_BATCH(2) at 72, from radeonEmitAtoms:996
>  emit ga_point_minmax 4/4
>      ga_point_minmax[0]: cmdpacket0 (first reg=0x4230, count=3)
>      ga_point_minmax[1]: 0x4230 = 18000006
>      ga_point_minmax[2]: 0x4234 = 00020006
>      ga_point_minmax[3]: 0x4238 = 3baaaaab
>BEGIN_BATCH(4) at 74, from radeonEmitAtoms:996
>  emit lcntl 2/2
>      lcntl[0]: cmdpacket0 (first reg=0x4234, count=1)
>      lcntl[1]: 0x4234 = 00030006
>BEGIN_BATCH(2) at 78, from radeonEmitAtoms:996
>  emit ga_line_stipple 4/4
>      ga_line_stipple[0]: cmdpacket0 (first reg=0x4260, count=3)
>      ga_line_stipple[1]: 0x4260 = 00000000
>      ga_line_stipple[2]: 0x4264 = 00000000
>      ga_line_stipple[3]: 0x4268 = 3f800000
>BEGIN_BATCH(4) at 80, from radeonEmitAtoms:996
>  emit shade 2/2
>      shade[0]: cmdpacket0 (first reg=0x4274, count=1)
>      shade[1]: 0x4274 = 00000002
>BEGIN_BATCH(2) at 84, from emit_shade_misc:410
>  emit shade2 4/4
>      shade2[0]: cmdpacket0 (first reg=0x4278, count=3)
>      shade2[1]: 0x4278 = 0003aaaa
>      shade2[2]: 0x427c = 00000000
>      shade2[3]: 0x4280 = 00000000
>BEGIN_BATCH(4) at 86, from radeonEmitAtoms:996
>  emit polygon_mode 4/4
>      polygon_mode[0]: cmdpacket0 (first reg=0x4288, count=3)
>      polygon_mode[1]: 0x4288 = 00000000
>      polygon_mode[2]: 0x428c = 00000001
>      polygon_mode[3]: 0x4290 = 00000000
>BEGIN_BATCH(4) at 90, from radeonEmitAtoms:996
>  emit fogp 3/3
>      fogp[0]: cmdpacket0 (first reg=0x4294, count=2)
>      fogp[1]: 0x4294 = 00000000
>      fogp[2]: 0x4298 = 00000000
>BEGIN_BATCH(3) at 94, from radeonEmitAtoms:996
>  emit zbias_cntl 2/2
>      zbias_cntl[0]: cmdpacket0 (first reg=0x42a0, count=1)
>      zbias_cntl[1]: 0x42a0 = 00000000
>BEGIN_BATCH(2) at 97, from radeonEmitAtoms:996
>  emit zbs 5/5
>      zbs[0]: cmdpacket0 (first reg=0x42a4, count=4)
>      zbs[1]: 0x42a4 = 00000000
>      zbs[2]: 0x42a8 = 00000000
>      zbs[3]: 0x42ac = 00000000
>      zbs[4]: 0x42b0 = 00000000
>BEGIN_BATCH(5) at 99, from radeonEmitAtoms:996
>  emit occlusion_cntl 2/2
>      occlusion_cntl[0]: cmdpacket0 (first reg=0x42b4, count=1)
>      occlusion_cntl[1]: 0x42b4 = 00000000
>BEGIN_BATCH(2) at 104, from radeonEmitAtoms:996
>  emit cul 2/2
>      cul[0]: cmdpacket0 (first reg=0x42b8, count=1)
>      cul[1]: 0x42b8 = 00000003
>BEGIN_BATCH(2) at 106, from radeonEmitAtoms:996
>  emit su_depth_scale 3/3
>      su_depth_scale[0]: cmdpacket0 (first reg=0x42c0, count=2)
>      su_depth_scale[1]: 0x42c0 = 4b7fffff
>      su_depth_scale[2]: 0x42c4 = 00000000
>BEGIN_BATCH(3) at 108, from radeonEmitAtoms:996
>  emit rc 3/3
>      rc[0]: cmdpacket0 (first reg=0x4300, count=2)
>      rc[1]: 0x4300 = 00000000
>      rc[2]: 0x4304 = 00000000
>BEGIN_BATCH(3) at 111, from radeonEmitAtoms:996
>  emit ri 17/17
>      ri[0]: cmdpacket0 (first reg=0x4074, count=16)
>      ri[1]: 0x4074 = 00000000
>      ri[2]: 0x4078 = 00000000
>      ri[3]: 0x407c = 00000000
>      ri[4]: 0x4080 = 00000000
>      ri[5]: 0x4084 = 00000000
>      ri[6]: 0x4088 = 00000000
>      ri[7]: 0x408c = 00000000
>      ri[8]: 0x4090 = 00000000
>      ri[9]: 0x4094 = 00000000
>      ri[10]: 0x4098 = 00000000
>      ri[11]: 0x409c = 00000000
>      ri[12]: 0x40a0 = 00000000
>      ri[13]: 0x40a4 = 00000000
>      ri[14]: 0x40a8 = 00000000
>      ri[15]: 0x40ac = 00000000
>      ri[16]: 0x40b0 = 00000000
>BEGIN_BATCH(17) at 114, from radeonEmitAtoms:996
>  emit rr 2/9
>      rr[0]: cmdpacket0 (first reg=0x4320, count=1)
>      rr[1]: 0x4320 = 00000000
>BEGIN_BATCH(2) at 131, from radeonEmitAtoms:996
>  emit sc_hyperz 3/3
>      sc_hyperz[0]: cmdpacket0 (first reg=0x43a4, count=2)
>      sc_hyperz[1]: 0x43a4 = 0000001c
>      sc_hyperz[2]: 0x43a8 = 2da49525
>BEGIN_BATCH(3) at 133, from radeonEmitAtoms:996
>  emit sc_screendoor 2/2
>      sc_screendoor[0]: cmdpacket0 (first reg=0x43e8, count=1)
>      sc_screendoor[1]: 0x43e8 = 00ffffff
>BEGIN_BATCH(2) at 136, from radeonEmitAtoms:996
>  emit us_out_fmt 6/6
>      us_out_fmt[0]: cmdpacket0 (first reg=0x46a4, count=5)
>      us_out_fmt[1]: 0x46a4 = 00001b00
>      us_out_fmt[2]: 0x46a8 = 00001b0f
>      us_out_fmt[3]: 0x46ac = 00001b0f
>      us_out_fmt[4]: 0x46b0 = 00001b0f
>      us_out_fmt[5]: 0x46b4 = 00000000
>BEGIN_BATCH(6) at 138, from radeonEmitAtoms:996
>  emit fp 9/9
>      fp[0]: cmdpacket0 (first reg=0x4600, count=2)
>      fp[1]: 0x4600 = 00000002
>      fp[2]: 0x4604 = 00000000
>      fp[3]: cmdpacket0 (first reg=0x4630, count=3)
>      fp[4]: 0x4630 = 00000000
>      fp[5]: 0x4634 = 00000000
>      fp[6]: 0x4638 = 00000000
>      fp[7]: cmdpacket0 (first reg=0x4624, count=1)
>      fp[8]: 0x4624 = 00000000
>BEGIN_BATCH(9) at 144, from radeonEmitAtoms:996
>  skip state r500fp
>  skip state r500fp_const
>  emit fogs 2/2
>      fogs[0]: cmdpacket0 (first reg=0x4bc0, count=1)
>      fogs[1]: 0x4bc0 = 00000000
>BEGIN_BATCH(2) at 153, from radeonEmitAtoms:996
>  emit fogc 4/4
>      fogc[0]: cmdpacket0 (first reg=0x4bc8, count=3)
>      fogc[1]: 0x4bc8 = 00000000
>      fogc[2]: 0x4bcc = 00000000
>      fogc[3]: 0x4bd0 = 00000000
>BEGIN_BATCH(4) at 155, from radeonEmitAtoms:996
>  emit at 3/3
>      at[0]: cmdpacket0 (first reg=0x4bd4, count=2)
>      at[1]: 0x4bd4 = 00000000
>      at[2]: 0x4bd8 = 00000000
>BEGIN_BATCH(3) at 159, from radeonEmitAtoms:996
>  emit fg_depth_src 2/2
>      fg_depth_src[0]: cmdpacket0 (first reg=0x4bd8, count=1)
>      fg_depth_src[1]: 0x4bd8 = 00000000
>BEGIN_BATCH(2) at 162, from radeonEmitAtoms:996
>  emit rb3d_cctl 2/2
>      rb3d_cctl[0]: cmdpacket0 (first reg=0x4e00, count=1)
>      rb3d_cctl[1]: 0x4e00 = 00000000
>BEGIN_BATCH(2) at 164, from radeonEmitAtoms:996
>  emit bld 3/3
>      bld[0]: cmdpacket0 (first reg=0x4e04, count=2)
>      bld[1]: 0x4e04 = 20210007
>      bld[2]: 0x4e08 = 20210000
>BEGIN_BATCH(3) at 166, from radeonEmitAtoms:996
>  emit cmk 2/2
>      cmk[0]: cmdpacket0 (first reg=0x4e0c, count=1)
>      cmk[1]: 0x4e0c = 0000000f
>BEGIN_BATCH(2) at 169, from radeonEmitAtoms:996
>  emit blend_color 3/3
>      blend_color[0]: cmdpacket0 (first reg=0x4ef8, count=2)
>      blend_color[1]: 0x4ef8 = 00000000
>      blend_color[2]: 0x4efc = 00000000
>BEGIN_BATCH(3) at 171, from radeonEmitAtoms:996
>  emit rop 2/2
>      rop[0]: cmdpacket0 (first reg=0x4e18, count=1)
>      rop[1]: 0x4e18 = 00000000
>BEGIN_BATCH(2) at 174, from radeonEmitAtoms:996
>  emit cb 4/4
>      cb[0]: cmdpacket0 (first reg=0x0000, count=0)
>      cb[1]: cmdpacket0 (first reg=0x0000, count=0)
>      cb[2]: cmdpacket0 (first reg=0x0000, count=0)
>      cb[3]: cmdpacket0 (first reg=0x0000, count=0)
>rrb is 0xc917e68 0 640x480
>BEGIN_BATCH(6) at 176, from emit_cb_offset:289
>  emit rb3d_dither_ctl 10/10
>      rb3d_dither_ctl[0]: cmdpacket0 (first reg=0x4e50, count=9)
>      rb3d_dither_ctl[1]: 0x4e50 = 00000000
>      rb3d_dither_ctl[2]: 0x4e54 = 00000000
>      rb3d_dither_ctl[3]: 0x4e58 = 00000000
>      rb3d_dither_ctl[4]: 0x4e5c = 00000000
>      rb3d_dither_ctl[5]: 0x4e60 = 00000000
>      rb3d_dither_ctl[6]: 0x4e64 = 00000000
>      rb3d_dither_ctl[7]: 0x4e68 = 00000000
>      rb3d_dither_ctl[8]: 0x4e6c = 00000000
>      rb3d_dither_ctl[9]: 0x4e70 = 00000000
>BEGIN_BATCH(10) at 180, from radeonEmitAtoms:996
>  emit rb3d_aaresolve_ctl 2/2
>      rb3d_aaresolve_ctl[0]: cmdpacket0 (first reg=0x4e88, count=1)
>      rb3d_aaresolve_ctl[1]: 0x4e88 = 00000000
>BEGIN_BATCH(2) at 190, from radeonEmitAtoms:996
>  emit rb3d_discard_src_pixel_lte_threshold 3/3
>      rb3d_discard_src_pixel_lte_threshold[0]: cmdpacket0 (first reg=0x4ea0, count=2)
>      rb3d_discard_src_pixel_lte_threshold[1]: 0x4ea0 = 00000000
>      rb3d_discard_src_pixel_lte_threshold[2]: 0x4ea4 = ffffffff
>BEGIN_BATCH(3) at 192, from emit_threshold_misc:396
>  emit zs 4/4
>      zs[0]: cmdpacket0 (first reg=0x4f00, count=3)
>      zs[1]: 0x4f00 = 00000016
>      zs[2]: 0x4f04 = 0003803f
>      zs[3]: 0x4f08 = 00ffff00
>BEGIN_BATCH(4) at 195, from radeonEmitAtoms:996
>  emit zstencil_format 5/5
>      zstencil_format[0]: cmdpacket0 (first reg=0x4f10, count=4)
>      zstencil_format[1]: 0x4f10 = 00000000
>      zstencil_format[2]: 0x4f14 = 00000001
>      zstencil_format[3]: 0x4f18 = 00000003
>      zstencil_format[4]: 0x4f1c = 00000000
>  emit zb 3/3
>      zb[0]: cmdpacket0 (first reg=0x0000, count=0)
>      zb[1]: cmdpacket0 (first reg=0x0000, count=0)
>      zb[2]: cmdpacket0 (first reg=0x0000, count=0)
>BEGIN_BATCH(6) at 204, from emit_zb_offset:366
>  emit zb_depthclearvalue 2/2
>      zb_depthclearvalue[0]: cmdpacket0 (first reg=0x4f28, count=1)
>      zb_depthclearvalue[1]: 0x4f28 = 00000000
>BEGIN_BATCH(2) at 208, from radeonEmitAtoms:996
>  emit zb_zmask 3/3
>      zb_zmask[0]: cmdpacket0 (first reg=0x4f30, count=2)
>      zb_zmask[1]: 0x4f30 = 00000000
>      zb_zmask[2]: 0x4f34 = 00000000
>BEGIN_BATCH(3) at 210, from radeonEmitAtoms:996
>  emit zb_hiz_offset 2/2
>      zb_hiz_offset[0]: cmdpacket0 (first reg=0x4f44, count=1)
>      zb_hiz_offset[1]: 0x4f44 = 00000000
>BEGIN_BATCH(2) at 213, from radeonEmitAtoms:996
>  emit zb_hiz_pitch 2/2
>      zb_hiz_pitch[0]: cmdpacket0 (first reg=0x4f54, count=1)
>      zb_hiz_pitch[1]: 0x4f54 = 00000000
>BEGIN_BATCH(2) at 215, from radeonEmitAtoms:996
>  skip state vpi
>  skip state vpp
>  emit vps 5/5
>      vps[0]: cmdpacket0 (first reg=0x0606, count=1)
>      vps[1]: 0x0606 = 00000000
>      vps[2]: cmdpacket0 (first reg=0x0000, count=0)
>      vps[3]: cmdpacket0 (first reg=0x3f80, count=0)
>      vps[4]: cmdpacket0 (first reg=0x0000, count=0)
>BEGIN_BATCH(5) at 217, from emit_vpu:86
>  emit vpucp[i] 5/5
>      vpucp[i][0]: cmdpacket0 (first reg=0x0600, count=1)
>      vpucp[i][1]: 0x0600 = 00000000
>      vpucp[i][2]: cmdpacket0 (first reg=0x0000, count=0)
>      vpucp[i][3]: cmdpacket0 (first reg=0x0000, count=0)
>      vpucp[i][4]: cmdpacket0 (first reg=0x0000, count=0)
>BEGIN_BATCH(5) at 222, from emit_vpu:86
>  emit vpucp[i] 5/5
>      vpucp[i][0]: cmdpacket0 (first reg=0x0601, count=1)
>      vpucp[i][1]: 0x0601 = 00000000
>      vpucp[i][2]: cmdpacket0 (first reg=0x0000, count=0)
>      vpucp[i][3]: cmdpacket0 (first reg=0x0000, count=0)
>      vpucp[i][4]: cmdpacket0 (first reg=0x0000, count=0)
>BEGIN_BATCH(5) at 227, from emit_vpu:86
>  emit vpucp[i] 5/5
>      vpucp[i][0]: cmdpacket0 (first reg=0x0602, count=1)
>      vpucp[i][1]: 0x0602 = 00000000
>      vpucp[i][2]: cmdpacket0 (first reg=0x0000, count=0)
>      vpucp[i][3]: cmdpacket0 (first reg=0x0000, count=0)
>      vpucp[i][4]: cmdpacket0 (first reg=0x0000, count=0)
>BEGIN_BATCH(5) at 232, from emit_vpu:86
>  emit vpucp[i] 5/5
>      vpucp[i][0]: cmdpacket0 (first reg=0x0603, count=1)
>      vpucp[i][1]: 0x0603 = 00000000
>      vpucp[i][2]: cmdpacket0 (first reg=0x0000, count=0)
>      vpucp[i][3]: cmdpacket0 (first reg=0x0000, count=0)
>      vpucp[i][4]: cmdpacket0 (first reg=0x0000, count=0)
>BEGIN_BATCH(5) at 237, from emit_vpu:86
>  emit vpucp[i] 5/5
>      vpucp[i][0]: cmdpacket0 (first reg=0x0604, count=1)
>      vpucp[i][1]: 0x0604 = 00000000
>      vpucp[i][2]: cmdpacket0 (first reg=0x0000, count=0)
>      vpucp[i][3]: cmdpacket0 (first reg=0x0000, count=0)
>      vpucp[i][4]: cmdpacket0 (first reg=0x0000, count=0)
>BEGIN_BATCH(5) at 242, from emit_vpu:86
>  emit vpucp[i] 5/5
>      vpucp[i][0]: cmdpacket0 (first reg=0x0605, count=1)
>      vpucp[i][1]: 0x0605 = 00000000
>      vpucp[i][2]: cmdpacket0 (first reg=0x0000, count=0)
>      vpucp[i][3]: cmdpacket0 (first reg=0x0000, count=0)
>      vpucp[i][4]: cmdpacket0 (first reg=0x0000, count=0)
>BEGIN_BATCH(5) at 247, from emit_vpu:86
>  skip state tex.filter
>  skip state tex.filter_1
>  skip state tex.size
>  skip state tex.format
>  skip state tex.pitch
>  skip state tex.offset
>  skip state tex.chroma_key
>  skip state tex.border_color
>BEGIN_BATCH(31) at 252, from r300EmitClearState:238
>BEGIN_BATCH(2) at 283, from r300EmitClearState:314
>BEGIN_BATCH(2) at 285, from r300EmitClearState:319
>BEGIN_BATCH(14) at 287, from r300EmitClearState:346
>BEGIN_BATCH(7) at 301, from r300EmitClearState:397
>BEGIN_BATCH(7) at 308, from emit_r500fp:131
>BEGIN_BATCH(2) at 315, from r300EmitClearState:450
>BEGIN_BATCH(2) at 317, from r300EmitClearState:483
>BEGIN_BATCH(4) at 319, from r300EmitClearState:493
>BEGIN_BATCH(9) at 323, from emit_vpu:86
>r300ClearBuffer: buffer 0xc917e68 (0,0 640x480)
>BEGIN_BATCH(1) at 332, from cp_wait:185
>BEGIN_BATCH(1) at 333, from end_3d:162
>BEGIN_BATCH(6) at 334, from r300ClearBuffer:104
>BEGIN_BATCH(6) at 338, from r300ClearBuffer:127
>BEGIN_BATCH(9) at 344, from r300ClearBuffer:174
>BEGIN_BATCH(4) at 353, from r300EmitCacheFlush:166
>BEGIN_BATCH(1) at 357, from cp_wait:185
>radeonDrawBuffer GL_BACK
>r300Enable( GL_DEPTH_TEST = GL_TRUE )
>r300Enable( GL_STENCIL_TEST = GL_FALSE )
>r300Clear
>BEGIN_BATCH(31) at 358, from r300EmitClearState:238
>BEGIN_BATCH(2) at 389, from r300EmitClearState:314
>BEGIN_BATCH(2) at 391, from r300EmitClearState:319
>BEGIN_BATCH(14) at 393, from r300EmitClearState:346
>BEGIN_BATCH(7) at 407, from r300EmitClearState:397
>BEGIN_BATCH(7) at 414, from emit_r500fp:131
>BEGIN_BATCH(2) at 421, from r300EmitClearState:450
>BEGIN_BATCH(2) at 423, from r300EmitClearState:483
>BEGIN_BATCH(4) at 425, from r300EmitClearState:493
>BEGIN_BATCH(9) at 429, from emit_vpu:86
>r300ClearBuffer: buffer 0xc917e68 (0,0 640x480)
>BEGIN_BATCH(1) at 438, from cp_wait:185
>BEGIN_BATCH(1) at 439, from end_3d:162
>BEGIN_BATCH(6) at 440, from r300ClearBuffer:104
>BEGIN_BATCH(6) at 444, from r300ClearBuffer:127
>BEGIN_BATCH(9) at 450, from r300ClearBuffer:174
>BEGIN_BATCH(4) at 459, from r300EmitCacheFlush:166
>BEGIN_BATCH(1) at 463, from cp_wait:185
>r300Enable( GL_DEPTH_TEST = GL_FALSE )
>r300Enable( GL_TEXTURE_COORD_ARRAY = GL_FALSE )
>r300Enable( GL_TEXTURE_COORD_ARRAY = GL_TRUE )
>r300Enable( GL_TEXTURE_2D = GL_TRUE )
>r300Enable( GL_DEPTH_TEST = GL_FALSE )
>r300Enable( GL_STENCIL_TEST = GL_FALSE )
>radeonFlush 464
>radeonEmitState
>Begin dirty state
>BEGIN_BATCH(1) at 464, from cp_wait:185
>BEGIN_BATCH(2) at 465, from r300_vtbl_pre_emit_atoms:234
>BEGIN_BATCH(1) at 467, from end_3d:162
>  emit vpt 7/7
>      vpt[0]: cmdpacket0 (first reg=0x1d98, count=6)
>      vpt[1]: 0x1d98 = 43a00000
>      vpt[2]: 0x1d9c = 43a00000
>      vpt[3]: 0x1da0 = c3700000
>      vpt[4]: 0x1da4 = 43700000
>      vpt[5]: 0x1da8 = 3f000000
>      vpt[6]: 0x1dac = 3f000000
>BEGIN_BATCH(7) at 468, from radeonEmitAtoms:996
>  emit vap_cntl 4/4
>      vap_cntl[0]: cmdpacket0 (first reg=0x2284, count=1)
>      vap_cntl[1]: 0x2284 = 00000000
>      vap_cntl[2]: cmdpacket0 (first reg=0x2080, count=1)
>      vap_cntl[3]: 0x2080 = 00b0056a
>BEGIN_BATCH(4) at 475, from radeonEmitAtoms:996
>  emit vte 3/3
>      vte[0]: cmdpacket0 (first reg=0x20b0, count=2)
>      vte[1]: 0x20b0 = 0000043f
>      vte[2]: 0x20b4 = 00000008
>BEGIN_BATCH(3) at 479, from radeonEmitAtoms:996
>  emit vir[0] 2/9
>      vir[0][0]: cmdpacket0 (first reg=0x2150, count=1)
>      vir[0][1]: 0x2150 = 00000000
>BEGIN_BATCH(2) at 482, from radeonEmitAtoms:996
>  emit vir[1] 2/9
>      vir[1][0]: cmdpacket0 (first reg=0x21e0, count=1)
>      vir[1][1]: 0x21e0 = 00000000
>BEGIN_BATCH(2) at 484, from radeonEmitAtoms:996
>  emit vic 3/3
>      vic[0]: cmdpacket0 (first reg=0x2180, count=2)
>      vic[1]: 0x2180 = 00000000
>      vic[2]: 0x2184 = 00000000
>BEGIN_BATCH(3) at 486, from radeonEmitAtoms:996
>  emit vap_clip_cntl 2/2
>      vap_clip_cntl[0]: cmdpacket0 (first reg=0x221c, count=1)
>      vap_clip_cntl[1]: 0x221c = 00000000
>BEGIN_BATCH(2) at 489, from radeonEmitAtoms:996
>  emit vof 3/3
>      vof[0]: cmdpacket0 (first reg=0x2090, count=2)
>      vof[1]: 0x2090 = 00000000
>      vof[2]: 0x2094 = 00000000
>BEGIN_BATCH(3) at 491, from radeonEmitAtoms:996
>  emit pvs 4/4
>      pvs[0]: cmdpacket0 (first reg=0x22d0, count=3)
>      pvs[1]: 0x22d0 = 00000000
>      pvs[2]: 0x22d4 = 00000000
>      pvs[3]: 0x22d8 = 00000000
>BEGIN_BATCH(4) at 494, from radeonEmitAtoms:996
>  emit txe 2/2
>      txe[0]: cmdpacket0 (first reg=0x4104, count=1)
>      txe[1]: 0x4104 = 00000000
>BEGIN_BATCH(2) at 498, from radeonEmitAtoms:996
>  emit ps 2/2
>      ps[0]: cmdpacket0 (first reg=0x421c, count=1)
>      ps[1]: 0x421c = 00060006
>BEGIN_BATCH(2) at 500, from radeonEmitAtoms:996
>  emit cul 2/2
>      cul[0]: cmdpacket0 (first reg=0x42b8, count=1)
>      cul[1]: 0x42b8 = 00000001
>BEGIN_BATCH(2) at 502, from radeonEmitAtoms:996
>  emit rc 3/3
>      rc[0]: cmdpacket0 (first reg=0x4300, count=2)
>      rc[1]: 0x4300 = 00000000
>      rc[2]: 0x4304 = 00000000
>BEGIN_BATCH(3) at 504, from radeonEmitAtoms:996
>  emit ri 17/17
>      ri[0]: cmdpacket0 (first reg=0x4074, count=16)
>      ri[1]: 0x4074 = 00000000
>      ri[2]: 0x4078 = 00000000
>      ri[3]: 0x407c = 00000000
>      ri[4]: 0x4080 = 00000000
>      ri[5]: 0x4084 = 00000000
>      ri[6]: 0x4088 = 00000000
>      ri[7]: 0x408c = 00000000
>      ri[8]: 0x4090 = 00000000
>      ri[9]: 0x4094 = 00000000
>      ri[10]: 0x4098 = 00000000
>      ri[11]: 0x409c = 00000000
>      ri[12]: 0x40a0 = 00000000
>      ri[13]: 0x40a4 = 00000000
>      ri[14]: 0x40a8 = 00000000
>      ri[15]: 0x40ac = 00000000
>      ri[16]: 0x40b0 = 00000000
>BEGIN_BATCH(17) at 507, from radeonEmitAtoms:996
>  emit rr 2/9
>      rr[0]: cmdpacket0 (first reg=0x4320, count=1)
>      rr[1]: 0x4320 = 00000000
>BEGIN_BATCH(2) at 524, from radeonEmitAtoms:996
>  emit fp 9/9
>      fp[0]: cmdpacket0 (first reg=0x4600, count=2)
>      fp[1]: 0x4600 = 00000002
>      fp[2]: 0x4604 = 00000000
>      fp[3]: cmdpacket0 (first reg=0x4630, count=3)
>      fp[4]: 0x4630 = 00000000
>      fp[5]: 0x4634 = 00000000
>      fp[6]: 0x4638 = 00000000
>      fp[7]: cmdpacket0 (first reg=0x4624, count=1)
>      fp[8]: 0x4624 = 00000000
>BEGIN_BATCH(9) at 526, from radeonEmitAtoms:996
>  skip state r500fp
>  emit fogs 2/2
>      fogs[0]: cmdpacket0 (first reg=0x4bc0, count=1)
>      fogs[1]: 0x4bc0 = 00000000
>BEGIN_BATCH(2) at 535, from radeonEmitAtoms:996
>  emit at 3/3
>      at[0]: cmdpacket0 (first reg=0x4bd4, count=2)
>      at[1]: 0x4bd4 = 00000000
>      at[2]: 0x4bd8 = 00000000
>BEGIN_BATCH(3) at 537, from radeonEmitAtoms:996
>  emit bld 3/3
>      bld[0]: cmdpacket0 (first reg=0x4e04, count=2)
>      bld[1]: 0x4e04 = 20210007
>      bld[2]: 0x4e08 = 20210000
>BEGIN_BATCH(3) at 540, from radeonEmitAtoms:996
>  emit cmk 2/2
>      cmk[0]: cmdpacket0 (first reg=0x4e0c, count=1)
>      cmk[1]: 0x4e0c = 0000000f
>BEGIN_BATCH(2) at 543, from radeonEmitAtoms:996
>  emit cb 4/4
>      cb[0]: cmdpacket0 (first reg=0x0000, count=0)
>      cb[1]: cmdpacket0 (first reg=0x0000, count=0)
>      cb[2]: cmdpacket0 (first reg=0x0000, count=0)
>      cb[3]: cmdpacket0 (first reg=0x0000, count=0)
>rrb is 0xc917e68 0 640x480
>BEGIN_BATCH(6) at 545, from emit_cb_offset:289
>  emit zs 4/4
>      zs[0]: cmdpacket0 (first reg=0x4f00, count=3)
>      zs[1]: 0x4f00 = 00000010
>      zs[2]: 0x4f04 = 00038038
>      zs[3]: 0x4f08 = 00ffff80
>BEGIN_BATCH(4) at 549, from radeonEmitAtoms:996
>  skip state vpi
>radeonReleaseDmaRegion (nil)
>rcommonFlushCmdBufLocked from radeonFlush - 1 cliprects
>r300TexParameter( GL_TEXTURE_MIN_FILTER )
>r300TexParameter( GL_TEXTURE_WRAP_S )
>r300TexParameter( GL_TEXTURE_WRAP_T )
>B_multitexture
>...using GL_ARB_texture_env_combine
>...using GL_ARB_texture_cube_map
>...using GL_ARB_texture_env_dot3
>...using GL_ARB_texture_env_add
>X..GL_ARB_texture_non_power_of_two not found
>...using GL_ARB_texture_compression
>X..GL_EXT_texture_compression_s3tc not found
>...using GL_EXT_texture_filter_anisotropic
>   maxTextureAnisotropy: 16.000000
>...using GL_EXT_texture_lod
>...using GL_1.4_texture_lod_bias
>X..GL_EXT_shared_texture_palette not found
>...using GL_EXT_texture3D
>...using GL_EXT_stencil_wrap
>X..GL_NV_register_combiners not found
>...using GL_EXT_stencil_two_side
>X..GL_ATI_fragment_shader not found
>X..GL_ATI_text_fragment_shader not found
>...using GL_ARB_vertex_buffer_object
>...using GL_ARB_vertex_program
>...using GL_ARB_fragment_program
>X..EXT_depth_bounds_test not found
>---------- R_NV20_Init ----------
>Not available.
>----------- R200_Init -----------
>Not available.
>---------- R_ARB2_Init ----------
>Available.
>---------------------------------
>----- R_ReloadARBPrograms -----
>glprogs/test.vfp
>glprogs/test.vfp
>glprogs/interaction.vfp
>glprogs/interaction.vfp
>glprogs/bumpyEnvironment.vfp
>glprogs/bumpyEnvironment.vfp
>glprogs/ambientLight.vfp
>glprogs/ambientLight.vfp
>glprogs/shadow.vp
>glprogs/R200_interaction.vp
>glprogs/nv20_bumpAndLight.vp
>glprogs/nv20_diffuseColor.vp
>glprogs/nv20_specularColor.vp
>glprogs/nv20_diffuseAndSpecularColor.vp
>glprogs/environment.vfp
>glprogs/environment.vfp
>glprogs/arbVP_glasswarp.txt: File not found
>glprogs/arbFP_glasswarp.txt: File not found
>glprogs/interactionUpdate.vfp
>glprogs/interactionUpdate.vfp
>glprogs/interactionCubeMaps.vfp
>glprogs/interactionCubeMaps.vfp
>glprogs/interactionNormBump.vfp
>glprogs/interactionNormBump.vfp
>glprogs/interactionNormBumpH.vfp
>glprogs/interactionNormBumpH.vfp
>glprogs/interactionAll.vfp
>glprogs/interactionAll.vfp
>-------------------------------
>using ARB_vertex_buffer_object memory
>using ARB2 renderSystem
>Fragment Program: Initial program:
># Fragment Program/Shader
>  0: TXP TEMP[0], INPUT[4], texture[0], 2D;
>  1: MUL OUTPUT[1].xyz, TEMP[0], STATE[0];
>  2: MOV OUTPUT[1].w, STATE[0];
>  3: END
>Fragment Program: After native rewrite:
># Fragment Program/Shader
>  0: TXP TEMP[0], INPUT[4], texture[0], 2D;
>  1: MUL OUTPUT[1].xyz, TEMP[0], STATE[0];
>  2: MOV OUTPUT[1].w, STATE[0];
>  3: END
>Compiler: after NqSSA-DCE:
># Fragment Program/Shader
>  0: TXP TEMP[0].xyz, INPUT[4], texture[0], 2D;
>  1: MUL OUTPUT[1].xyz, TEMP[0].xyz?, STATE[0].xyz?;
>  2: MOV OUTPUT[1].w, STATE[0].???w;
>  3: END
>Emit paired program
> BEGIN_TEX
>   TXP TEMP[1].xyz, INPUT[0], texture[0], 2D;
> END_TEX
>       RGB:    Src0 = TEMP[1]  Src1 = CNST[0]
>       Alpha:  Src0 = CNST[0]
>  MAD COLOR.xyz, Src0.xyz, Src1.xyz, Src0.000
>  MAD COLOR.w, Src0.w, Src0.1, Src0.0
> END
>R500 Fragment Program:
>--------
>--------
>Constants:
>Constant 0: 6[0]
>--------
>0	0:CMN_INST   0x00003807:TEX TEX_WAIT    wmask: RGB omask: NONE
>	1:TEX_INST:  0x06c00000: id: 0 op:PROJ, ACQ, IGNUNC SCALED
>	2:TEX_ADDR:  0xe401e400: src: 0 R/G/B/A dst: 1 R/G/B/A
>	3:TEX_DXDY:  0x00000000
>
>1	0:CMN_INST   0x00078005:OUT TEX_WAIT    wmask: NONE omask: ARGB
>	1:RGB_ADDR   0x00040001:Addr0: 1t, Addr1: 0c, Addr2: 0t, srcp:0
>	2:ALPHA_ADDR 0x00000100:Addr0: 0c, Addr1: 0t, Addr2: 0t, srcp:0
>	3 RGB_INST:  0x00442220:rgb_A_src:0 R/G/B 0 rgb_B_src:1 R/G/B 0
>	4 ALPHA_INST:0x00c0c000:MAD dest:0 alp_A_src:0 A 0 alp_B_src:0 1 0 w:0
>	5 RGBA_INST: 0x20490000:MAD dest:0 rgb_C_src:0 0/0/0 0 alp_C_src:0 0 0
>
>Initial vertex program:
># Vertex Program/Shader
>  0: DP4 OUTPUT[0].x, INPUT[0], STATE[0];
>  1: DP4 OUTPUT[0].y, INPUT[0], STATE[1];
>  2: DP4 OUTPUT[0].z, INPUT[0], STATE[2];
>  3: DP4 OUTPUT[0].w, INPUT[0], STATE[3];
>  4: MOV OUTPUT[4], INPUT[8];
>  5: END
>Vertex program after native rewrite:
># Vertex Program/Shader
>  0: DP4 OUTPUT[0].x, INPUT[0], STATE[0];
>  1: DP4 OUTPUT[0].y, INPUT[0], STATE[1];
>  2: DP4 OUTPUT[0].z, INPUT[0], STATE[2];
>  3: DP4 OUTPUT[0].w, INPUT[0], STATE[3];
>  4: MOV OUTPUT[4], INPUT[8];
>  5: END
>Vertex program after NQSSADCE:
># Vertex Program/Shader
>  0: DP4 OUTPUT[0].x, INPUT[0], STATE[0];
>  1: DP4 OUTPUT[0].y, INPUT[0], STATE[1];
>  2: DP4 OUTPUT[0].z, INPUT[0], STATE[2];
>  3: DP4 OUTPUT[0].w, INPUT[0], STATE[3];
>  4: MOV OUTPUT[4], INPUT[8];
>  5: END
>radeon_validate_texture_miptree: Validating texture 0xc9db538 now
> Allocate new miptree
>level 0, face 0: rs:2048 1024x1024 at 0
> face 0, level 0... 0xca0e7f8 vs 0xc9db830 migrating
>radeonAllocDmaRegion 48
>radeonRefillCurrentDmaRegion
>radeonEmitVec12 count 4 stride 60 out 0xa428e000 data 0x9e7fe008
>radeonAllocDmaRegion 32
>radeonEmitVec8 count 4 stride 60 out 0xa428e040 data 0x9e7fe014
>mtu=8
>Activating texture unit 0
>TX_ENABLE: 00000001  last_hw_tmu=0
>BEGIN_BATCH(4) at 0, from r300EmitCacheFlush:166
>radeonEmitState
>Begin dirty state
>BEGIN_BATCH(1) at 4, from cp_wait:185
>BEGIN_BATCH(2) at 5, from r300_vtbl_pre_emit_atoms:234
>BEGIN_BATCH(1) at 7, from end_3d:162
>  emit vpt 7/7
>      vpt[0]: cmdpacket0 (first reg=0x1d98, count=6)
>      vpt[1]: 0x1d98 = 43a00000
>      vpt[2]: 0x1d9c = 43a00000
>      vpt[3]: 0x1da0 = c3700000
>      vpt[4]: 0x1da4 = 43700000
>      vpt[5]: 0x1da8 = 3f000000
>      vpt[6]: 0x1dac = 3f000000
>BEGIN_BATCH(7) at 8, from radeonEmitAtoms:996
>  emit vap_cntl 4/4
>      vap_cntl[0]: cmdpacket0 (first reg=0x2284, count=1)
>      vap_cntl[1]: 0x2284 = 00000000
>      vap_cntl[2]: cmdpacket0 (first reg=0x2080, count=1)
>      vap_cntl[3]: 0x2080 = 00b0056a
>BEGIN_BATCH(4) at 15, from radeonEmitAtoms:996
>  emit vap_index_offset 2/2
>      vap_index_offset[0]: cmdpacket0 (first reg=0x208c, count=1)
>      vap_index_offset[1]: 0x208c = 00000000
>BEGIN_BATCH(2) at 19, from radeonEmitAtoms:996
>  emit vte 3/3
>      vte[0]: cmdpacket0 (first reg=0x20b0, count=2)
>      vte[1]: 0x20b0 = 0000043f
>      vte[2]: 0x20b4 = 00000008
>BEGIN_BATCH(3) at 21, from radeonEmitAtoms:996
>  emit vap_vf_max_vtx_indx 3/3
>      vap_vf_max_vtx_indx[0]: cmdpacket0 (first reg=0x2134, count=2)
>      vap_vf_max_vtx_indx[1]: 0x2134 = 00ffffff
>      vap_vf_max_vtx_indx[2]: 0x2138 = 00000000
>BEGIN_BATCH(3) at 24, from radeonEmitAtoms:996
>  emit vap_cntl_status 2/2
>      vap_cntl_status[0]: cmdpacket0 (first reg=0x2140, count=1)
>      vap_cntl_status[1]: 0x2140 = 00000000
>BEGIN_BATCH(2) at 27, from radeonEmitAtoms:996
>  emit vir[0] 2/9
>      vir[0][0]: cmdpacket0 (first reg=0x2150, count=1)
>      vir[0][1]: 0x2150 = 21010002
>BEGIN_BATCH(2) at 29, from radeonEmitAtoms:996
>  emit vir[1] 2/9
>      vir[1][0]: cmdpacket0 (first reg=0x21e0, count=1)
>      vir[1][1]: 0x21e0 = fb08fa88
>BEGIN_BATCH(2) at 31, from radeonEmitAtoms:996
>  emit vic 3/3
>      vic[0]: cmdpacket0 (first reg=0x2180, count=2)
>      vic[1]: 0x2180 = 00005555
>      vic[2]: 0x2184 = 00000401
>BEGIN_BATCH(3) at 33, from radeonEmitAtoms:996
>  emit vap_psc_sgn_norm_cntl 2/2
>      vap_psc_sgn_norm_cntl[0]: cmdpacket0 (first reg=0x21dc, count=1)
>      vap_psc_sgn_norm_cntl[1]: 0x21dc = aaaaaaaa
>BEGIN_BATCH(2) at 36, from radeonEmitAtoms:996
>  emit vap_clip_cntl 2/2
>      vap_clip_cntl[0]: cmdpacket0 (first reg=0x221c, count=1)
>      vap_clip_cntl[1]: 0x221c = 00000000
>BEGIN_BATCH(2) at 38, from radeonEmitAtoms:996
>  emit vap_clip 5/5
>      vap_clip[0]: cmdpacket0 (first reg=0x2220, count=4)
>      vap_clip[1]: 0x2220 = 3f800000
>      vap_clip[2]: 0x2224 = 3f800000
>      vap_clip[3]: 0x2228 = 3f800000
>      vap_clip[4]: 0x222c = 3f800000
>BEGIN_BATCH(5) at 40, from radeonEmitAtoms:996
>  emit vap_pvs_vtx_timeout_reg 2/2
>      vap_pvs_vtx_timeout_reg[0]: cmdpacket0 (first reg=0x2288, count=1)
>      vap_pvs_vtx_timeout_reg[1]: 0x2288 = 0000ffff
>BEGIN_BATCH(2) at 45, from radeonEmitAtoms:996
>  emit vof 3/3
>      vof[0]: cmdpacket0 (first reg=0x2090, count=2)
>      vof[1]: 0x2090 = 00000001
>      vof[2]: 0x2094 = 00000004
>BEGIN_BATCH(3) at 47, from radeonEmitAtoms:996
>  emit pvs 4/4
>      pvs[0]: cmdpacket0 (first reg=0x22d0, count=3)
>      pvs[1]: 0x22d0 = 00401000
>      pvs[2]: 0x22d4 = 00040000
>      pvs[3]: 0x22d8 = 00000004
>BEGIN_BATCH(4) at 50, from radeonEmitAtoms:996
>  emit gb_enable 2/2
>      gb_enable[0]: cmdpacket0 (first reg=0x4008, count=1)
>      gb_enable[1]: 0x4008 = 00000007
>BEGIN_BATCH(2) at 54, from radeonEmitAtoms:996
>  emit gb_misc 4/4
>      gb_misc[0]: cmdpacket0 (first reg=0x4010, count=3)
>      gb_misc[1]: 0x4010 = 66666666
>      gb_misc[2]: 0x4014 = 06666666
>      gb_misc[3]: 0x4018 = 00000011
>BEGIN_BATCH(4) at 56, from emit_gb_misc:382
>  emit gb_misc2 3/3
>      gb_misc2[0]: cmdpacket0 (first reg=0x401c, count=2)
>      gb_misc2[1]: 0x401c = 00000000
>      gb_misc2[2]: 0x4020 = 00000000
>BEGIN_BATCH(3) at 60, from radeonEmitAtoms:996
>  emit txe 2/2
>      txe[0]: cmdpacket0 (first reg=0x4104, count=1)
>      txe[1]: 0x4104 = 00000001
>BEGIN_BATCH(2) at 63, from radeonEmitAtoms:996
>  emit ga_point_s0 5/5
>      ga_point_s0[0]: cmdpacket0 (first reg=0x4200, count=4)
>      ga_point_s0[1]: 0x4200 = 00000000
>      ga_point_s0[2]: 0x4204 = 00000000
>      ga_point_s0[3]: 0x4208 = 3f800000
>      ga_point_s0[4]: 0x420c = 3f800000
>BEGIN_BATCH(5) at 65, from radeonEmitAtoms:996
>  emit ga_triangle_stipple 2/2
>      ga_triangle_stipple[0]: cmdpacket0 (first reg=0x4214, count=1)
>      ga_triangle_stipple[1]: 0x4214 = 00050005
>BEGIN_BATCH(2) at 70, from radeonEmitAtoms:996
>  emit ps 2/2
>      ps[0]: cmdpacket0 (first reg=0x421c, count=1)
>      ps[1]: 0x421c = 00060006
>BEGIN_BATCH(2) at 72, from radeonEmitAtoms:996
>  emit ga_point_minmax 4/4
>      ga_point_minmax[0]: cmdpacket0 (first reg=0x4230, count=3)
>      ga_point_minmax[1]: 0x4230 = 18000006
>      ga_point_minmax[2]: 0x4234 = 00020006
>      ga_point_minmax[3]: 0x4238 = 3baaaaab
>BEGIN_BATCH(4) at 74, from radeonEmitAtoms:996
>  emit lcntl 2/2
>      lcntl[0]: cmdpacket0 (first reg=0x4234, count=1)
>      lcntl[1]: 0x4234 = 00030006
>BEGIN_BATCH(2) at 78, from radeonEmitAtoms:996
>  emit ga_line_stipple 4/4
>      ga_line_stipple[0]: cmdpacket0 (first reg=0x4260, count=3)
>      ga_line_stipple[1]: 0x4260 = 00000000
>      ga_line_stipple[2]: 0x4264 = 00000000
>      ga_line_stipple[3]: 0x4268 = 3f800000
>BEGIN_BATCH(4) at 80, from radeonEmitAtoms:996
>  emit shade 2/2
>      shade[0]: cmdpacket0 (first reg=0x4274, count=1)
>      shade[1]: 0x4274 = 00000002
>BEGIN_BATCH(2) at 84, from emit_shade_misc:410
>  emit shade2 4/4
>      shade2[0]: cmdpacket0 (first reg=0x4278, count=3)
>      shade2[1]: 0x4278 = 0003aaaa
>      shade2[2]: 0x427c = 00000000
>      shade2[3]: 0x4280 = 00000000
>BEGIN_BATCH(4) at 86, from radeonEmitAtoms:996
>  emit polygon_mode 4/4
>      polygon_mode[0]: cmdpacket0 (first reg=0x4288, count=3)
>      polygon_mode[1]: 0x4288 = 00000000
>      polygon_mode[2]: 0x428c = 00000001
>      polygon_mode[3]: 0x4290 = 00000000
>BEGIN_BATCH(4) at 90, from radeonEmitAtoms:996
>  emit fogp 3/3
>      fogp[0]: cmdpacket0 (first reg=0x4294, count=2)
>      fogp[1]: 0x4294 = 00000000
>      fogp[2]: 0x4298 = 00000000
>BEGIN_BATCH(3) at 94, from radeonEmitAtoms:996
>  emit zbias_cntl 2/2
>      zbias_cntl[0]: cmdpacket0 (first reg=0x42a0, count=1)
>      zbias_cntl[1]: 0x42a0 = 00000000
>BEGIN_BATCH(2) at 97, from radeonEmitAtoms:996
>  emit zbs 5/5
>      zbs[0]: cmdpacket0 (first reg=0x42a4, count=4)
>      zbs[1]: 0x42a4 = 00000000
>      zbs[2]: 0x42a8 = 00000000
>      zbs[3]: 0x42ac = 00000000
>      zbs[4]: 0x42b0 = 00000000
>BEGIN_BATCH(5) at 99, from radeonEmitAtoms:996
>  emit occlusion_cntl 2/2
>      occlusion_cntl[0]: cmdpacket0 (first reg=0x42b4, count=1)
>      occlusion_cntl[1]: 0x42b4 = 00000000
>BEGIN_BATCH(2) at 104, from radeonEmitAtoms:996
>  emit cul 2/2
>      cul[0]: cmdpacket0 (first reg=0x42b8, count=1)
>      cul[1]: 0x42b8 = 00000001
>BEGIN_BATCH(2) at 106, from radeonEmitAtoms:996
>  emit su_depth_scale 3/3
>      su_depth_scale[0]: cmdpacket0 (first reg=0x42c0, count=2)
>      su_depth_scale[1]: 0x42c0 = 4b7fffff
>      su_depth_scale[2]: 0x42c4 = 00000000
>BEGIN_BATCH(3) at 108, from radeonEmitAtoms:996
>  emit rc 3/3
>      rc[0]: cmdpacket0 (first reg=0x4300, count=2)
>      rc[1]: 0x4300 = 00040004
>      rc[2]: 0x4304 = 000000c0
>BEGIN_BATCH(3) at 111, from radeonEmitAtoms:996
>  emit ri 2/17
>      ri[0]: cmdpacket0 (first reg=0x4074, count=1)
>      ri[1]: 0x4074 = 000c2040
>BEGIN_BATCH(2) at 114, from radeonEmitAtoms:996
>  emit rr 2/9
>      rr[0]: cmdpacket0 (first reg=0x4320, count=1)
>      rr[1]: 0x4320 = 00000010
>BEGIN_BATCH(2) at 116, from radeonEmitAtoms:996
>  emit sc_hyperz 3/3
>      sc_hyperz[0]: cmdpacket0 (first reg=0x43a4, count=2)
>      sc_hyperz[1]: 0x43a4 = 0000001c
>      sc_hyperz[2]: 0x43a8 = 2da49525
>BEGIN_BATCH(3) at 118, from radeonEmitAtoms:996
>  emit sc_screendoor 2/2
>      sc_screendoor[0]: cmdpacket0 (first reg=0x43e8, count=1)
>      sc_screendoor[1]: 0x43e8 = 00ffffff
>BEGIN_BATCH(2) at 121, from radeonEmitAtoms:996
>  emit us_out_fmt 6/6
>      us_out_fmt[0]: cmdpacket0 (first reg=0x46a4, count=5)
>      us_out_fmt[1]: 0x46a4 = 00001b00
>      us_out_fmt[2]: 0x46a8 = 00001b0f
>      us_out_fmt[3]: 0x46ac = 00001b0f
>      us_out_fmt[4]: 0x46b0 = 00001b0f
>      us_out_fmt[5]: 0x46b4 = 00000000
>BEGIN_BATCH(6) at 123, from radeonEmitAtoms:996
>  emit fp 9/9
>      fp[0]: cmdpacket0 (first reg=0x4600, count=2)
>      fp[1]: 0x4600 = 00000002
>      fp[2]: 0x4604 = 00000001
>      fp[3]: cmdpacket0 (first reg=0x4630, count=3)
>      fp[4]: 0x4630 = 00010000
>      fp[5]: 0x4634 = 00010000
>      fp[6]: 0x4638 = 00000000
>      fp[7]: cmdpacket0 (first reg=0x4624, count=1)
>      fp[8]: 0x4624 = 00000000
>BEGIN_BATCH(9) at 129, from radeonEmitAtoms:996
>  emit r500fp 13/3073
>      r500fp[0]: cmdpacket0 (first reg=0x0000, count=2)
>      r500fp[1]: 0x0000 = 00003807
>      r500fp[2]: 0x0004 = 06c00000
>      r500fp[3]: cmdpacket0 (first reg=0xe401, count=228)
>      r500fp[4]: 0xe401 = 00000000
>      r500fp[5]: 0xe405 = 00000000
>      r500fp[6]: 0xe409 = 00000000
>      r500fp[7]: 0xe40d = 00078005
>      r500fp[8]: 0xe411 = 00040001
>      r500fp[9]: 0xe415 = 00000100
>      r500fp[10]: 0xe419 = 00442220
>      r500fp[11]: 0xe41d = 00c0c000
>      r500fp[12]: 0xe421 = 20490000
>BEGIN_BATCH(13) at 138, from emit_r500fp:131
>  emit r500fp_const 5/1025
>      r500fp_const[0]: cmdpacket0 (first reg=0x0200, count=1)
>      r500fp_const[1]: 0x0200 = 3f800000
>      r500fp_const[2]: cmdpacket0 (first reg=0x3f80, count=0)
>      r500fp_const[3]: cmdpacket0 (first reg=0x3f80, count=0)
>      r500fp_const[4]: cmdpacket0 (first reg=0x3f80, count=0)
>BEGIN_BATCH(5) at 151, from emit_r500fp:131
>  emit fogs 2/2
>      fogs[0]: cmdpacket0 (first reg=0x4bc0, count=1)
>      fogs[1]: 0x4bc0 = 00000000
>BEGIN_BATCH(2) at 156, from radeonEmitAtoms:996
>  emit fogc 4/4
>      fogc[0]: cmdpacket0 (first reg=0x4bc8, count=3)
>      fogc[1]: 0x4bc8 = 00000000
>      fogc[2]: 0x4bcc = 00000000
>      fogc[3]: 0x4bd0 = 00000000
>BEGIN_BATCH(4) at 158, from radeonEmitAtoms:996
>  emit at 3/3
>      at[0]: cmdpacket0 (first reg=0x4bd4, count=2)
>      at[1]: 0x4bd4 = 00000000
>      at[2]: 0x4bd8 = 00000000
>BEGIN_BATCH(3) at 162, from radeonEmitAtoms:996
>  emit fg_depth_src 2/2
>      fg_depth_src[0]: cmdpacket0 (first reg=0x4bd8, count=1)
>      fg_depth_src[1]: 0x4bd8 = 00000000
>BEGIN_BATCH(2) at 165, from radeonEmitAtoms:996
>  emit rb3d_cctl 2/2
>      rb3d_cctl[0]: cmdpacket0 (first reg=0x4e00, count=1)
>      rb3d_cctl[1]: 0x4e00 = 00000000
>BEGIN_BATCH(2) at 167, from radeonEmitAtoms:996
>  emit bld 3/3
>      bld[0]: cmdpacket0 (first reg=0x4e04, count=2)
>      bld[1]: 0x4e04 = 20210007
>      bld[2]: 0x4e08 = 20210000
>BEGIN_BATCH(3) at 169, from radeonEmitAtoms:996
>  emit cmk 2/2
>      cmk[0]: cmdpacket0 (first reg=0x4e0c, count=1)
>      cmk[1]: 0x4e0c = 0000000f
>BEGIN_BATCH(2) at 172, from radeonEmitAtoms:996
>  emit blend_color 3/3
>      blend_color[0]: cmdpacket0 (first reg=0x4ef8, count=2)
>      blend_color[1]: 0x4ef8 = 00000000
>      blend_color[2]: 0x4efc = 00000000
>BEGIN_BATCH(3) at 174, from radeonEmitAtoms:996
>  emit rop 2/2
>      rop[0]: cmdpacket0 (first reg=0x4e18, count=1)
>      rop[1]: 0x4e18 = 00000000
>BEGIN_BATCH(2) at 177, from radeonEmitAtoms:996
>  emit cb 4/4
>      cb[0]: cmdpacket0 (first reg=0x0000, count=0)
>      cb[1]: cmdpacket0 (first reg=0x0000, count=0)
>      cb[2]: cmdpacket0 (first reg=0x0000, count=0)
>      cb[3]: cmdpacket0 (first reg=0x0000, count=0)
>rrb is 0xc917e68 0 640x480
>BEGIN_BATCH(6) at 179, from emit_cb_offset:289
>  emit rb3d_dither_ctl 10/10
>      rb3d_dither_ctl[0]: cmdpacket0 (first reg=0x4e50, count=9)
>      rb3d_dither_ctl[1]: 0x4e50 = 00000000
>      rb3d_dither_ctl[2]: 0x4e54 = 00000000
>      rb3d_dither_ctl[3]: 0x4e58 = 00000000
>      rb3d_dither_ctl[4]: 0x4e5c = 00000000
>      rb3d_dither_ctl[5]: 0x4e60 = 00000000
>      rb3d_dither_ctl[6]: 0x4e64 = 00000000
>      rb3d_dither_ctl[7]: 0x4e68 = 00000000
>      rb3d_dither_ctl[8]: 0x4e6c = 00000000
>      rb3d_dither_ctl[9]: 0x4e70 = 00000000
>BEGIN_BATCH(10) at 183, from radeonEmitAtoms:996
>  emit rb3d_aaresolve_ctl 2/2
>      rb3d_aaresolve_ctl[0]: cmdpacket0 (first reg=0x4e88, count=1)
>      rb3d_aaresolve_ctl[1]: 0x4e88 = 00000000
>BEGIN_BATCH(2) at 193, from radeonEmitAtoms:996
>  emit rb3d_discard_src_pixel_lte_threshold 3/3
>      rb3d_discard_src_pixel_lte_threshold[0]: cmdpacket0 (first reg=0x4ea0, count=2)
>      rb3d_discard_src_pixel_lte_threshold[1]: 0x4ea0 = 00000000
>      rb3d_discard_src_pixel_lte_threshold[2]: 0x4ea4 = ffffffff
>BEGIN_BATCH(3) at 195, from emit_threshold_misc:396
>  emit zs 4/4
>      zs[0]: cmdpacket0 (first reg=0x4f00, count=3)
>      zs[1]: 0x4f00 = 00000010
>      zs[2]: 0x4f04 = 00038038
>      zs[3]: 0x4f08 = 00ffff80
>BEGIN_BATCH(4) at 198, from radeonEmitAtoms:996
>  emit zstencil_format 5/5
>      zstencil_format[0]: cmdpacket0 (first reg=0x4f10, count=4)
>      zstencil_format[1]: 0x4f10 = 00000002
>      zstencil_format[2]: 0x4f14 = 00000001
>      zstencil_format[3]: 0x4f18 = 00000003
>      zstencil_format[4]: 0x4f1c = 00000000
>  emit zb 3/3
>      zb[0]: cmdpacket0 (first reg=0x0000, count=0)
>      zb[1]: cmdpacket0 (first reg=0x0000, count=0)
>      zb[2]: cmdpacket0 (first reg=0x0000, count=0)
>BEGIN_BATCH(6) at 207, from emit_zb_offset:366
>  emit zb_depthclearvalue 2/2
>      zb_depthclearvalue[0]: cmdpacket0 (first reg=0x4f28, count=1)
>      zb_depthclearvalue[1]: 0x4f28 = 00000000
>BEGIN_BATCH(2) at 211, from radeonEmitAtoms:996
>  emit zb_zmask 3/3
>      zb_zmask[0]: cmdpacket0 (first reg=0x4f30, count=2)
>      zb_zmask[1]: 0x4f30 = 00000000
>      zb_zmask[2]: 0x4f34 = 00000000
>BEGIN_BATCH(3) at 213, from radeonEmitAtoms:996
>  emit zb_hiz_offset 2/2
>      zb_hiz_offset[0]: cmdpacket0 (first reg=0x4f44, count=1)
>      zb_hiz_offset[1]: 0x4f44 = 00000000
>BEGIN_BATCH(2) at 216, from radeonEmitAtoms:996
>  emit zb_hiz_pitch 2/2
>      zb_hiz_pitch[0]: cmdpacket0 (first reg=0x4f54, count=1)
>      zb_hiz_pitch[1]: 0x4f54 = 00000000
>BEGIN_BATCH(2) at 218, from radeonEmitAtoms:996
>  emit vpi 21/1025
>      vpi[0]: cmdpacket0 (first reg=0x0000, count=5)
>      vpi[1]: 0x0000 = 00100201
>      vpi[2]: 0x0004 = 00d10001
>      vpi[3]: 0x0008 = 00d10002
>      vpi[4]: 0x000c = 01248002
>      vpi[5]: 0x0010 = 00200201
>      vpi[6]: cmdpacket0 (first reg=0x00d1, count=0)
>      vpi[7]: cmdpacket0 (first reg=0x00d1, count=0)
>      vpi[8]: cmdpacket0 (first reg=0x0124, count=128)
>      vpi[9]: 0x0124 = 00400201
>      vpi[10]: 0x0128 = 00d10001
>      vpi[11]: 0x012c = 00d10042
>      vpi[12]: 0x0130 = 01248042
>      vpi[13]: 0x0134 = 00800201
>      vpi[14]: 0x0138 = 00d10001
>      vpi[15]: 0x013c = 00d10062
>      vpi[16]: 0x0140 = 01248062
>      vpi[17]: 0x0144 = 00f02203
>      vpi[18]: 0x0148 = 00d10021
>      vpi[19]: 0x014c = 01248021
>      vpi[20]: 0x0150 = 01248021
>BEGIN_BATCH(21) at 220, from emit_vpu:86
>  emit vpp 17/1025
>      vpp[0]: cmdpacket0 (first reg=0x0400, count=4)
>      vpp[1]: 0x0400 = 3b4ccccd
>      vpp[2]: 0x0404 = 00000000
>      vpp[3]: 0x0408 = 00000000
>      vpp[4]: 0x040c = bf800000
>      vpp[5]: cmdpacket0 (first reg=0x0000, count=0)
>      vpp[6]: cmdpacket0 (first reg=0xbb88, count=136)
>      vpp[7]: 0xbb88 = 00000000
>      vpp[8]: 0xbb8c = 3f800000
>      vpp[9]: 0xbb90 = 00000000
>      vpp[10]: 0xbb94 = 00000000
>      vpp[11]: 0xbb98 = c0000000
>      vpp[12]: 0xbb9c = bf800000
>      vpp[13]: 0xbba0 = 00000000
>      vpp[14]: 0xbba4 = 00000000
>      vpp[15]: 0xbba8 = 00000000
>      vpp[16]: 0xbbac = 3f800000
>BEGIN_BATCH(17) at 241, from emit_vpu:86
>  skip state vps
>  emit vpucp[i] 5/5
>      vpucp[i][0]: cmdpacket0 (first reg=0x0600, count=1)
>      vpucp[i][1]: 0x0600 = 00000000
>      vpucp[i][2]: cmdpacket0 (first reg=0x0000, count=0)
>      vpucp[i][3]: cmdpacket0 (first reg=0x0000, count=0)
>      vpucp[i][4]: cmdpacket0 (first reg=0x0000, count=0)
>BEGIN_BATCH(5) at 258, from emit_vpu:86
>  emit vpucp[i] 5/5
>      vpucp[i][0]: cmdpacket0 (first reg=0x0601, count=1)
>      vpucp[i][1]: 0x0601 = 00000000
>      vpucp[i][2]: cmdpacket0 (first reg=0x0000, count=0)
>      vpucp[i][3]: cmdpacket0 (first reg=0x0000, count=0)
>      vpucp[i][4]: cmdpacket0 (first reg=0x0000, count=0)
>BEGIN_BATCH(5) at 263, from emit_vpu:86
>  emit vpucp[i] 5/5
>      vpucp[i][0]: cmdpacket0 (first reg=0x0602, count=1)
>      vpucp[i][1]: 0x0602 = 00000000
>      vpucp[i][2]: cmdpacket0 (first reg=0x0000, count=0)
>      vpucp[i][3]: cmdpacket0 (first reg=0x0000, count=0)
>      vpucp[i][4]: cmdpacket0 (first reg=0x0000, count=0)
>BEGIN_BATCH(5) at 268, from emit_vpu:86
>  emit vpucp[i] 5/5
>      vpucp[i][0]: cmdpacket0 (first reg=0x0603, count=1)
>      vpucp[i][1]: 0x0603 = 00000000
>      vpucp[i][2]: cmdpacket0 (first reg=0x0000, count=0)
>      vpucp[i][3]: cmdpacket0 (first reg=0x0000, count=0)
>      vpucp[i][4]: cmdpacket0 (first reg=0x0000, count=0)
>BEGIN_BATCH(5) at 273, from emit_vpu:86
>  emit vpucp[i] 5/5
>      vpucp[i][0]: cmdpacket0 (first reg=0x0604, count=1)
>      vpucp[i][1]: 0x0604 = 00000000
>      vpucp[i][2]: cmdpacket0 (first reg=0x0000, count=0)
>      vpucp[i][3]: cmdpacket0 (first reg=0x0000, count=0)
>      vpucp[i][4]: cmdpacket0 (first reg=0x0000, count=0)
>BEGIN_BATCH(5) at 278, from emit_vpu:86
>  emit vpucp[i] 5/5
>      vpucp[i][0]: cmdpacket0 (first reg=0x0605, count=1)
>      vpucp[i][1]: 0x0605 = 00000000
>      vpucp[i][2]: cmdpacket0 (first reg=0x0000, count=0)
>      vpucp[i][3]: cmdpacket0 (first reg=0x0000, count=0)
>      vpucp[i][4]: cmdpacket0 (first reg=0x0000, count=0)
>BEGIN_BATCH(5) at 283, from emit_vpu:86
>  emit tex.filter 2/9
>      tex.filter[0]: cmdpacket0 (first reg=0x4400, count=1)
>      tex.filter[1]: 0x4400 = 00001400
>BEGIN_BATCH(2) at 288, from radeonEmitAtoms:996
>  emit tex.filter_1 2/9
>      tex.filter_1[0]: cmdpacket0 (first reg=0x4440, count=1)
>      tex.filter_1[1]: 0x4440 = 00000000
>BEGIN_BATCH(2) at 290, from radeonEmitAtoms:996
>  emit tex.size 2/9
>      tex.size[0]: cmdpacket0 (first reg=0x4480, count=1)
>      tex.size[1]: 0x4480 = 001ffbff
>BEGIN_BATCH(2) at 292, from radeonEmitAtoms:996
>  emit tex.format 2/9
>      tex.format[0]: cmdpacket0 (first reg=0x44c0, count=1)
>      tex.format[1]: 0x44c0 = 0000aa06
>BEGIN_BATCH(2) at 294, from radeonEmitAtoms:996
>  emit tex.pitch 2/9
>      tex.pitch[0]: cmdpacket0 (first reg=0x4500, count=1)
>      tex.pitch[1]: 0x4500 = 00000000
>BEGIN_BATCH(2) at 296, from radeonEmitAtoms:996
>  emit tex.offset 2/1
>      tex.offset[0]: cmdpacket0 (first reg=0x4540, count=1)
>      tex.offset[1]: 0x4540 = 00000000
>BEGIN_BATCH(4) at 298, from emit_tex_offsets:185
>  emit tex.chroma_key 2/9
>      tex.chroma_key[0]: cmdpacket0 (first reg=0x4580, count=1)
>      tex.chroma_key[1]: 0x4580 = 00000000
>BEGIN_BATCH(2) at 300, from radeonEmitAtoms:996
>  emit tex.border_color 2/9
>      tex.border_color[0]: cmdpacket0 (first reg=0x45c0, count=1)
>      tex.border_color[1]: 0x45c0 = 00000000
>BEGIN_BATCH(2) at 302, from radeonEmitAtoms:996
>radeonAllocDmaRegion 24
>r300EmitAOS: nr=2, ofs=0x00000000
>BEGIN_BATCH(10) at 304, from r300EmitAOS:247
>BEGIN_BATCH(10) at 310, from r300FireEB:199
>BEGIN_BATCH(4) at 318, from r300EmitCacheFlush:166
>r300Enable( GL_STENCIL_TEST = GL_TRUE )
>radeonFlush 322
>radeonEmitState
>Begin dirty state
>BEGIN_BATCH(1) at 322, from cp_wait:185
>BEGIN_BATCH(2) at 323, from r300_vtbl_pre_emit_atoms:234
>BEGIN_BATCH(1) at 325, from end_3d:162
>  emit zs 4/4
>      zs[0]: cmdpacket0 (first reg=0x4f00, count=3)
>      zs[1]: 0x4f00 = 00000011
>      zs[2]: 0x4f04 = 00038038
>      zs[3]: 0x4f08 = 00ffff80
>BEGIN_BATCH(4) at 326, from radeonEmitAtoms:996
>radeonReleaseDmaRegion 0xc9ea9e8
>rcommonFlushCmdBufLocked from radeonFlush - 1 cliprects
>radeonFlush 0
>
>radeonCopyBuffer( 0xc5e53b8 )
>
>r300Enable( GL_DEPTH_TEST = GL_TRUE )
>r300Enable( GL_STENCIL_TEST = GL_FALSE )
>r300Enable( GL_TEXTURE_2D = GL_FALSE )
>radeonDrawBuffer GL_BACK
>r300Enable( GL_DEPTH_TEST = GL_TRUE )
>r300Enable( GL_STENCIL_TEST = GL_FALSE )
>r300Clear
>Reemit state after flush (from r300EmitClearState)
>radeonEmitState
>Begin reemit state
>BEGIN_BATCH(1) at 0, from cp_wait:185
>BEGIN_BATCH(2) at 1, from r300_vtbl_pre_emit_atoms:234
>BEGIN_BATCH(1) at 3, from end_3d:162
>Begin dirty state
>BEGIN_BATCH(1) at 4, from cp_wait:185
>BEGIN_BATCH(2) at 5, from r300_vtbl_pre_emit_atoms:234
>BEGIN_BATCH(1) at 7, from end_3d:162
>  emit vpt 7/7
>      vpt[0]: cmdpacket0 (first reg=0x1d98, count=6)
>      vpt[1]: 0x1d98 = 43a00000
>      vpt[2]: 0x1d9c = 43a00000
>      vpt[3]: 0x1da0 = c3700000
>      vpt[4]: 0x1da4 = 43700000
>      vpt[5]: 0x1da8 = 3f000000
>      vpt[6]: 0x1dac = 3f000000
>BEGIN_BATCH(7) at 8, from radeonEmitAtoms:996
>  emit vap_cntl 4/4
>      vap_cntl[0]: cmdpacket0 (first reg=0x2284, count=1)
>      vap_cntl[1]: 0x2284 = 00000000
>      vap_cntl[2]: cmdpacket0 (first reg=0x2080, count=1)
>      vap_cntl[3]: 0x2080 = 00b0056a
>BEGIN_BATCH(4) at 15, from radeonEmitAtoms:996
>  emit vap_index_offset 2/2
>      vap_index_offset[0]: cmdpacket0 (first reg=0x208c, count=1)
>      vap_index_offset[1]: 0x208c = 00000000
>BEGIN_BATCH(2) at 19, from radeonEmitAtoms:996
>  emit vte 3/3
>      vte[0]: cmdpacket0 (first reg=0x20b0, count=2)
>      vte[1]: 0x20b0 = 0000043f
>      vte[2]: 0x20b4 = 00000008
>BEGIN_BATCH(3) at 21, from radeonEmitAtoms:996
>  emit vap_vf_max_vtx_indx 3/3
>      vap_vf_max_vtx_indx[0]: cmdpacket0 (first reg=0x2134, count=2)
>      vap_vf_max_vtx_indx[1]: 0x2134 = 00ffffff
>      vap_vf_max_vtx_indx[2]: 0x2138 = 00000000
>BEGIN_BATCH(3) at 24, from radeonEmitAtoms:996
>  emit vap_cntl_status 2/2
>      vap_cntl_status[0]: cmdpacket0 (first reg=0x2140, count=1)
>      vap_cntl_status[1]: 0x2140 = 00000000
>BEGIN_BATCH(2) at 27, from radeonEmitAtoms:996
>  emit vir[0] 2/9
>      vir[0][0]: cmdpacket0 (first reg=0x2150, count=1)
>      vir[0][1]: 0x2150 = 21010002
>BEGIN_BATCH(2) at 29, from radeonEmitAtoms:996
>  emit vir[1] 2/9
>      vir[1][0]: cmdpacket0 (first reg=0x21e0, count=1)
>      vir[1][1]: 0x21e0 = fb08fa88
>BEGIN_BATCH(2) at 31, from radeonEmitAtoms:996
>  emit vic 3/3
>      vic[0]: cmdpacket0 (first reg=0x2180, count=2)
>      vic[1]: 0x2180 = 00005555
>      vic[2]: 0x2184 = 00000401
>BEGIN_BATCH(3) at 33, from radeonEmitAtoms:996
>  emit vap_psc_sgn_norm_cntl 2/2
>      vap_psc_sgn_norm_cntl[0]: cmdpacket0 (first reg=0x21dc, count=1)
>      vap_psc_sgn_norm_cntl[1]: 0x21dc = aaaaaaaa
>BEGIN_BATCH(2) at 36, from radeonEmitAtoms:996
>  emit vap_clip_cntl 2/2
>      vap_clip_cntl[0]: cmdpacket0 (first reg=0x221c, count=1)
>      vap_clip_cntl[1]: 0x221c = 00000000
>BEGIN_BATCH(2) at 38, from radeonEmitAtoms:996
>  emit vap_clip 5/5
>      vap_clip[0]: cmdpacket0 (first reg=0x2220, count=4)
>      vap_clip[1]: 0x2220 = 3f800000
>      vap_clip[2]: 0x2224 = 3f800000
>      vap_clip[3]: 0x2228 = 3f800000
>      vap_clip[4]: 0x222c = 3f800000
>BEGIN_BATCH(5) at 40, from radeonEmitAtoms:996
>  emit vap_pvs_vtx_timeout_reg 2/2
>      vap_pvs_vtx_timeout_reg[0]: cmdpacket0 (first reg=0x2288, count=1)
>      vap_pvs_vtx_timeout_reg[1]: 0x2288 = 0000ffff
>BEGIN_BATCH(2) at 45, from radeonEmitAtoms:996
>  emit vof 3/3
>      vof[0]: cmdpacket0 (first reg=0x2090, count=2)
>      vof[1]: 0x2090 = 00000001
>      vof[2]: 0x2094 = 00000004
>BEGIN_BATCH(3) at 47, from radeonEmitAtoms:996
>  emit pvs 4/4
>      pvs[0]: cmdpacket0 (first reg=0x22d0, count=3)
>      pvs[1]: 0x22d0 = 00401000
>      pvs[2]: 0x22d4 = 00040000
>      pvs[3]: 0x22d8 = 00000004
>BEGIN_BATCH(4) at 50, from radeonEmitAtoms:996
>  emit gb_enable 2/2
>      gb_enable[0]: cmdpacket0 (first reg=0x4008, count=1)
>      gb_enable[1]: 0x4008 = 00000007
>BEGIN_BATCH(2) at 54, from radeonEmitAtoms:996
>  emit gb_misc 4/4
>      gb_misc[0]: cmdpacket0 (first reg=0x4010, count=3)
>      gb_misc[1]: 0x4010 = 66666666
>      gb_misc[2]: 0x4014 = 06666666
>      gb_misc[3]: 0x4018 = 00000011
>BEGIN_BATCH(4) at 56, from emit_gb_misc:382
>  emit gb_misc2 3/3
>      gb_misc2[0]: cmdpacket0 (first reg=0x401c, count=2)
>      gb_misc2[1]: 0x401c = 00000000
>      gb_misc2[2]: 0x4020 = 00000000
>BEGIN_BATCH(3) at 60, from radeonEmitAtoms:996
>  emit txe 2/2
>      txe[0]: cmdpacket0 (first reg=0x4104, count=1)
>      txe[1]: 0x4104 = 00000001
>BEGIN_BATCH(2) at 63, from radeonEmitAtoms:996
>  emit ga_point_s0 5/5
>      ga_point_s0[0]: cmdpacket0 (first reg=0x4200, count=4)
>      ga_point_s0[1]: 0x4200 = 00000000
>      ga_point_s0[2]: 0x4204 = 00000000
>      ga_point_s0[3]: 0x4208 = 3f800000
>      ga_point_s0[4]: 0x420c = 3f800000
>BEGIN_BATCH(5) at 65, from radeonEmitAtoms:996
>  emit ga_triangle_stipple 2/2
>      ga_triangle_stipple[0]: cmdpacket0 (first reg=0x4214, count=1)
>      ga_triangle_stipple[1]: 0x4214 = 00050005
>BEGIN_BATCH(2) at 70, from radeonEmitAtoms:996
>  emit ps 2/2
>      ps[0]: cmdpacket0 (first reg=0x421c, count=1)
>      ps[1]: 0x421c = 00060006
>BEGIN_BATCH(2) at 72, from radeonEmitAtoms:996
>  emit ga_point_minmax 4/4
>      ga_point_minmax[0]: cmdpacket0 (first reg=0x4230, count=3)
>      ga_point_minmax[1]: 0x4230 = 18000006
>      ga_point_minmax[2]: 0x4234 = 00020006
>      ga_point_minmax[3]: 0x4238 = 3baaaaab
>BEGIN_BATCH(4) at 74, from radeonEmitAtoms:996
>  emit lcntl 2/2
>      lcntl[0]: cmdpacket0 (first reg=0x4234, count=1)
>      lcntl[1]: 0x4234 = 00030006
>BEGIN_BATCH(2) at 78, from radeonEmitAtoms:996
>  emit ga_line_stipple 4/4
>      ga_line_stipple[0]: cmdpacket0 (first reg=0x4260, count=3)
>      ga_line_stipple[1]: 0x4260 = 00000000
>      ga_line_stipple[2]: 0x4264 = 00000000
>      ga_line_stipple[3]: 0x4268 = 3f800000
>BEGIN_BATCH(4) at 80, from radeonEmitAtoms:996
>  emit shade 2/2
>      shade[0]: cmdpacket0 (first reg=0x4274, count=1)
>      shade[1]: 0x4274 = 00000002
>BEGIN_BATCH(2) at 84, from emit_shade_misc:410
>  emit shade2 4/4
>      shade2[0]: cmdpacket0 (first reg=0x4278, count=3)
>      shade2[1]: 0x4278 = 0003aaaa
>      shade2[2]: 0x427c = 00000000
>      shade2[3]: 0x4280 = 00000000
>BEGIN_BATCH(4) at 86, from radeonEmitAtoms:996
>  emit polygon_mode 4/4
>      polygon_mode[0]: cmdpacket0 (first reg=0x4288, count=3)
>      polygon_mode[1]: 0x4288 = 00000000
>      polygon_mode[2]: 0x428c = 00000001
>      polygon_mode[3]: 0x4290 = 00000000
>BEGIN_BATCH(4) at 90, from radeonEmitAtoms:996
>  emit fogp 3/3
>      fogp[0]: cmdpacket0 (first reg=0x4294, count=2)
>      fogp[1]: 0x4294 = 00000000
>      fogp[2]: 0x4298 = 00000000
>BEGIN_BATCH(3) at 94, from radeonEmitAtoms:996
>  emit zbias_cntl 2/2
>      zbias_cntl[0]: cmdpacket0 (first reg=0x42a0, count=1)
>      zbias_cntl[1]: 0x42a0 = 00000000
>BEGIN_BATCH(2) at 97, from radeonEmitAtoms:996
>  emit zbs 5/5
>      zbs[0]: cmdpacket0 (first reg=0x42a4, count=4)
>      zbs[1]: 0x42a4 = 00000000
>      zbs[2]: 0x42a8 = 00000000
>      zbs[3]: 0x42ac = 00000000
>      zbs[4]: 0x42b0 = 00000000
>BEGIN_BATCH(5) at 99, from radeonEmitAtoms:996
>  emit occlusion_cntl 2/2
>      occlusion_cntl[0]: cmdpacket0 (first reg=0x42b4, count=1)
>      occlusion_cntl[1]: 0x42b4 = 00000000
>BEGIN_BATCH(2) at 104, from radeonEmitAtoms:996
>  emit cul 2/2
>      cul[0]: cmdpacket0 (first reg=0x42b8, count=1)
>      cul[1]: 0x42b8 = 00000003
>BEGIN_BATCH(2) at 106, from radeonEmitAtoms:996
>  emit su_depth_scale 3/3
>      su_depth_scale[0]: cmdpacket0 (first reg=0x42c0, count=2)
>      su_depth_scale[1]: 0x42c0 = 4b7fffff
>      su_depth_scale[2]: 0x42c4 = 00000000
>BEGIN_BATCH(3) at 108, from radeonEmitAtoms:996
>  emit rc 3/3
>      rc[0]: cmdpacket0 (first reg=0x4300, count=2)
>      rc[1]: 0x4300 = 00040004
>      rc[2]: 0x4304 = 000000c0
>BEGIN_BATCH(3) at 111, from radeonEmitAtoms:996
>  emit ri 2/17
>      ri[0]: cmdpacket0 (first reg=0x4074, count=1)
>      ri[1]: 0x4074 = 000c2040
>BEGIN_BATCH(2) at 114, from radeonEmitAtoms:996
>  emit rr 2/9
>      rr[0]: cmdpacket0 (first reg=0x4320, count=1)
>      rr[1]: 0x4320 = 00000010
>BEGIN_BATCH(2) at 116, from radeonEmitAtoms:996
>  emit sc_hyperz 3/3
>      sc_hyperz[0]: cmdpacket0 (first reg=0x43a4, count=2)
>      sc_hyperz[1]: 0x43a4 = 0000001c
>      sc_hyperz[2]: 0x43a8 = 2da49525
>BEGIN_BATCH(3) at 118, from radeonEmitAtoms:996
>  emit sc_screendoor 2/2
>      sc_screendoor[0]: cmdpacket0 (first reg=0x43e8, count=1)
>      sc_screendoor[1]: 0x43e8 = 00ffffff
>BEGIN_BATCH(2) at 121, from radeonEmitAtoms:996
>  emit us_out_fmt 6/6
>      us_out_fmt[0]: cmdpacket0 (first reg=0x46a4, count=5)
>      us_out_fmt[1]: 0x46a4 = 00001b00
>      us_out_fmt[2]: 0x46a8 = 00001b0f
>      us_out_fmt[3]: 0x46ac = 00001b0f
>      us_out_fmt[4]: 0x46b0 = 00001b0f
>      us_out_fmt[5]: 0x46b4 = 00000000
>BEGIN_BATCH(6) at 123, from radeonEmitAtoms:996
>  emit fp 9/9
>      fp[0]: cmdpacket0 (first reg=0x4600, count=2)
>      fp[1]: 0x4600 = 00000002
>      fp[2]: 0x4604 = 00000001
>      fp[3]: cmdpacket0 (first reg=0x4630, count=3)
>      fp[4]: 0x4630 = 00010000
>      fp[5]: 0x4634 = 00010000
>      fp[6]: 0x4638 = 00000000
>      fp[7]: cmdpacket0 (first reg=0x4624, count=1)
>      fp[8]: 0x4624 = 00000000
>BEGIN_BATCH(9) at 129, from radeonEmitAtoms:996
>  emit r500fp 13/3073
>      r500fp[0]: cmdpacket0 (first reg=0x0000, count=2)
>      r500fp[1]: 0x0000 = 00003807
>      r500fp[2]: 0x0004 = 06c00000
>      r500fp[3]: cmdpacket0 (first reg=0xe401, count=228)
>      r500fp[4]: 0xe401 = 00000000
>      r500fp[5]: 0xe405 = 00000000
>      r500fp[6]: 0xe409 = 00000000
>      r500fp[7]: 0xe40d = 00078005
>      r500fp[8]: 0xe411 = 00040001
>      r500fp[9]: 0xe415 = 00000100
>      r500fp[10]: 0xe419 = 00442220
>      r500fp[11]: 0xe41d = 00c0c000
>      r500fp[12]: 0xe421 = 20490000
>BEGIN_BATCH(13) at 138, from emit_r500fp:131
>  emit r500fp_const 5/1025
>      r500fp_const[0]: cmdpacket0 (first reg=0x0200, count=1)
>      r500fp_const[1]: 0x0200 = 3f800000
>      r500fp_const[2]: cmdpacket0 (first reg=0x3f80, count=0)
>      r500fp_const[3]: cmdpacket0 (first reg=0x3f80, count=0)
>      r500fp_const[4]: cmdpacket0 (first reg=0x3f80, count=0)
>BEGIN_BATCH(5) at 151, from emit_r500fp:131
>  emit fogs 2/2
>      fogs[0]: cmdpacket0 (first reg=0x4bc0, count=1)
>      fogs[1]: 0x4bc0 = 00000000
>BEGIN_BATCH(2) at 156, from radeonEmitAtoms:996
>  emit fogc 4/4
>      fogc[0]: cmdpacket0 (first reg=0x4bc8, count=3)
>      fogc[1]: 0x4bc8 = 00000000
>      fogc[2]: 0x4bcc = 00000000
>      fogc[3]: 0x4bd0 = 00000000
>BEGIN_BATCH(4) at 158, from radeonEmitAtoms:996
>  emit at 3/3
>      at[0]: cmdpacket0 (first reg=0x4bd4, count=2)
>      at[1]: 0x4bd4 = 00000000
>      at[2]: 0x4bd8 = 00000000
>BEGIN_BATCH(3) at 162, from radeonEmitAtoms:996
>  emit fg_depth_src 2/2
>      fg_depth_src[0]: cmdpacket0 (first reg=0x4bd8, count=1)
>      fg_depth_src[1]: 0x4bd8 = 00000000
>BEGIN_BATCH(2) at 165, from radeonEmitAtoms:996
>  emit rb3d_cctl 2/2
>      rb3d_cctl[0]: cmdpacket0 (first reg=0x4e00, count=1)
>      rb3d_cctl[1]: 0x4e00 = 00000000
>BEGIN_BATCH(2) at 167, from radeonEmitAtoms:996
>  emit bld 3/3
>      bld[0]: cmdpacket0 (first reg=0x4e04, count=2)
>      bld[1]: 0x4e04 = 20210007
>      bld[2]: 0x4e08 = 20210000
>BEGIN_BATCH(3) at 169, from radeonEmitAtoms:996
>  emit cmk 2/2
>      cmk[0]: cmdpacket0 (first reg=0x4e0c, count=1)
>      cmk[1]: 0x4e0c = 0000000f
>BEGIN_BATCH(2) at 172, from radeonEmitAtoms:996
>  emit blend_color 3/3
>      blend_color[0]: cmdpacket0 (first reg=0x4ef8, count=2)
>      blend_color[1]: 0x4ef8 = 00000000
>      blend_color[2]: 0x4efc = 00000000
>BEGIN_BATCH(3) at 174, from radeonEmitAtoms:996
>  emit rop 2/2
>      rop[0]: cmdpacket0 (first reg=0x4e18, count=1)
>      rop[1]: 0x4e18 = 00000000
>BEGIN_BATCH(2) at 177, from radeonEmitAtoms:996
>  emit cb 4/4
>      cb[0]: cmdpacket0 (first reg=0x0000, count=0)
>      cb[1]: cmdpacket0 (first reg=0x0000, count=0)
>      cb[2]: cmdpacket0 (first reg=0x0000, count=0)
>      cb[3]: cmdpacket0 (first reg=0x0000, count=0)
>rrb is 0xc917e68 0 640x480
>BEGIN_BATCH(6) at 179, from emit_cb_offset:289
>  emit rb3d_dither_ctl 10/10
>      rb3d_dither_ctl[0]: cmdpacket0 (first reg=0x4e50, count=9)
>      rb3d_dither_ctl[1]: 0x4e50 = 00000000
>      rb3d_dither_ctl[2]: 0x4e54 = 00000000
>      rb3d_dither_ctl[3]: 0x4e58 = 00000000
>      rb3d_dither_ctl[4]: 0x4e5c = 00000000
>      rb3d_dither_ctl[5]: 0x4e60 = 00000000
>      rb3d_dither_ctl[6]: 0x4e64 = 00000000
>      rb3d_dither_ctl[7]: 0x4e68 = 00000000
>      rb3d_dither_ctl[8]: 0x4e6c = 00000000
>      rb3d_dither_ctl[9]: 0x4e70 = 00000000
>BEGIN_BATCH(10) at 183, from radeonEmitAtoms:996
>  emit rb3d_aaresolve_ctl 2/2
>      rb3d_aaresolve_ctl[0]: cmdpacket0 (first reg=0x4e88, count=1)
>      rb3d_aaresolve_ctl[1]: 0x4e88 = 00000000
>BEGIN_BATCH(2) at 193, from radeonEmitAtoms:996
>  emit rb3d_discard_src_pixel_lte_threshold 3/3
>      rb3d_discard_src_pixel_lte_threshold[0]: cmdpacket0 (first reg=0x4ea0, count=2)
>      rb3d_discard_src_pixel_lte_threshold[1]: 0x4ea0 = 00000000
>      rb3d_discard_src_pixel_lte_threshold[2]: 0x4ea4 = ffffffff
>BEGIN_BATCH(3) at 195, from emit_threshold_misc:396
>  emit zs 4/4
>      zs[0]: cmdpacket0 (first reg=0x4f00, count=3)
>      zs[1]: 0x4f00 = 00000016
>      zs[2]: 0x4f04 = 0003803f
>      zs[3]: 0x4f08 = 00ffff80
>BEGIN_BATCH(4) at 198, from radeonEmitAtoms:996
>  emit zstencil_format 5/5
>      zstencil_format[0]: cmdpacket0 (first reg=0x4f10, count=4)
>      zstencil_format[1]: 0x4f10 = 00000002
>      zstencil_format[2]: 0x4f14 = 00000001
>      zstencil_format[3]: 0x4f18 = 00000003
>      zstencil_format[4]: 0x4f1c = 00000000
>  emit zb 3/3
>      zb[0]: cmdpacket0 (first reg=0x0000, count=0)
>      zb[1]: cmdpacket0 (first reg=0x0000, count=0)
>      zb[2]: cmdpacket0 (first reg=0x0000, count=0)
>BEGIN_BATCH(6) at 207, from emit_zb_offset:366
>  emit zb_depthclearvalue 2/2
>      zb_depthclearvalue[0]: cmdpacket0 (first reg=0x4f28, count=1)
>      zb_depthclearvalue[1]: 0x4f28 = 00000000
>BEGIN_BATCH(2) at 211, from radeonEmitAtoms:996
>  emit zb_zmask 3/3
>      zb_zmask[0]: cmdpacket0 (first reg=0x4f30, count=2)
>      zb_zmask[1]: 0x4f30 = 00000000
>      zb_zmask[2]: 0x4f34 = 00000000
>BEGIN_BATCH(3) at 213, from radeonEmitAtoms:996
>  emit zb_hiz_offset 2/2
>      zb_hiz_offset[0]: cmdpacket0 (first reg=0x4f44, count=1)
>      zb_hiz_offset[1]: 0x4f44 = 00000000
>BEGIN_BATCH(2) at 216, from radeonEmitAtoms:996
>  emit zb_hiz_pitch 2/2
>      zb_hiz_pitch[0]: cmdpacket0 (first reg=0x4f54, count=1)
>      zb_hiz_pitch[1]: 0x4f54 = 00000000
>BEGIN_BATCH(2) at 218, from radeonEmitAtoms:996
>  emit vpi 21/1025
>      vpi[0]: cmdpacket0 (first reg=0x0000, count=5)
>      vpi[1]: 0x0000 = 00100201
>      vpi[2]: 0x0004 = 00d10001
>      vpi[3]: 0x0008 = 00d10002
>      vpi[4]: 0x000c = 01248002
>      vpi[5]: 0x0010 = 00200201
>      vpi[6]: cmdpacket0 (first reg=0x00d1, count=0)
>      vpi[7]: cmdpacket0 (first reg=0x00d1, count=0)
>      vpi[8]: cmdpacket0 (first reg=0x0124, count=128)
>      vpi[9]: 0x0124 = 00400201
>      vpi[10]: 0x0128 = 00d10001
>      vpi[11]: 0x012c = 00d10042
>      vpi[12]: 0x0130 = 01248042
>      vpi[13]: 0x0134 = 00800201
>      vpi[14]: 0x0138 = 00d10001
>      vpi[15]: 0x013c = 00d10062
>      vpi[16]: 0x0140 = 01248062
>      vpi[17]: 0x0144 = 00f02203
>      vpi[18]: 0x0148 = 00d10021
>      vpi[19]: 0x014c = 01248021
>      vpi[20]: 0x0150 = 01248021
>BEGIN_BATCH(21) at 220, from emit_vpu:86
>  emit vpp 17/1025
>      vpp[0]: cmdpacket0 (first reg=0x0400, count=4)
>      vpp[1]: 0x0400 = 3b4ccccd
>      vpp[2]: 0x0404 = 00000000
>      vpp[3]: 0x0408 = 00000000
>      vpp[4]: 0x040c = bf800000
>      vpp[5]: cmdpacket0 (first reg=0x0000, count=0)
>      vpp[6]: cmdpacket0 (first reg=0xbb88, count=136)
>      vpp[7]: 0xbb88 = 00000000
>      vpp[8]: 0xbb8c = 3f800000
>      vpp[9]: 0xbb90 = 00000000
>      vpp[10]: 0xbb94 = 00000000
>      vpp[11]: 0xbb98 = c0000000
>      vpp[12]: 0xbb9c = bf800000
>      vpp[13]: 0xbba0 = 00000000
>      vpp[14]: 0xbba4 = 00000000
>      vpp[15]: 0xbba8 = 00000000
>      vpp[16]: 0xbbac = 3f800000
>BEGIN_BATCH(17) at 241, from emit_vpu:86
>  skip state vps
>  emit vpucp[i] 5/5
>      vpucp[i][0]: cmdpacket0 (first reg=0x0600, count=1)
>      vpucp[i][1]: 0x0600 = 00000000
>      vpucp[i][2]: cmdpacket0 (first reg=0x0000, count=0)
>      vpucp[i][3]: cmdpacket0 (first reg=0x0000, count=0)
>      vpucp[i][4]: cmdpacket0 (first reg=0x0000, count=0)
>BEGIN_BATCH(5) at 258, from emit_vpu:86
>  emit vpucp[i] 5/5
>      vpucp[i][0]: cmdpacket0 (first reg=0x0601, count=1)
>      vpucp[i][1]: 0x0601 = 00000000
>      vpucp[i][2]: cmdpacket0 (first reg=0x0000, count=0)
>      vpucp[i][3]: cmdpacket0 (first reg=0x0000, count=0)
>      vpucp[i][4]: cmdpacket0 (first reg=0x0000, count=0)
>BEGIN_BATCH(5) at 263, from emit_vpu:86
>  emit vpucp[i] 5/5
>      vpucp[i][0]: cmdpacket0 (first reg=0x0602, count=1)
>      vpucp[i][1]: 0x0602 = 00000000
>      vpucp[i][2]: cmdpacket0 (first reg=0x0000, count=0)
>      vpucp[i][3]: cmdpacket0 (first reg=0x0000, count=0)
>      vpucp[i][4]: cmdpacket0 (first reg=0x0000, count=0)
>BEGIN_BATCH(5) at 268, from emit_vpu:86
>  emit vpucp[i] 5/5
>      vpucp[i][0]: cmdpacket0 (first reg=0x0603, count=1)
>      vpucp[i][1]: 0x0603 = 00000000
>      vpucp[i][2]: cmdpacket0 (first reg=0x0000, count=0)
>      vpucp[i][3]: cmdpacket0 (first reg=0x0000, count=0)
>      vpucp[i][4]: cmdpacket0 (first reg=0x0000, count=0)
>BEGIN_BATCH(5) at 273, from emit_vpu:86
>  emit vpucp[i] 5/5
>      vpucp[i][0]: cmdpacket0 (first reg=0x0604, count=1)
>      vpucp[i][1]: 0x0604 = 00000000
>      vpucp[i][2]: cmdpacket0 (first reg=0x0000, count=0)
>      vpucp[i][3]: cmdpacket0 (first reg=0x0000, count=0)
>      vpucp[i][4]: cmdpacket0 (first reg=0x0000, count=0)
>BEGIN_BATCH(5) at 278, from emit_vpu:86
>  emit vpucp[i] 5/5
>      vpucp[i][0]: cmdpacket0 (first reg=0x0605, count=1)
>      vpucp[i][1]: 0x0605 = 00000000
>      vpucp[i][2]: cmdpacket0 (first reg=0x0000, count=0)
>      vpucp[i][3]: cmdpacket0 (first reg=0x0000, count=0)
>      vpucp[i][4]: cmdpacket0 (first reg=0x0000, count=0)
>BEGIN_BATCH(5) at 283, from emit_vpu:86
>  emit tex.filter 2/9
>      tex.filter[0]: cmdpacket0 (first reg=0x4400, count=1)
>      tex.filter[1]: 0x4400 = 00001400
>BEGIN_BATCH(2) at 288, from radeonEmitAtoms:996
>  emit tex.filter_1 2/9
>      tex.filter_1[0]: cmdpacket0 (first reg=0x4440, count=1)
>      tex.filter_1[1]: 0x4440 = 00000000
>BEGIN_BATCH(2) at 290, from radeonEmitAtoms:996
>  emit tex.size 2/9
>      tex.size[0]: cmdpacket0 (first reg=0x4480, count=1)
>      tex.size[1]: 0x4480 = 001ffbff
>BEGIN_BATCH(2) at 292, from radeonEmitAtoms:996
>  emit tex.format 2/9
>      tex.format[0]: cmdpacket0 (first reg=0x44c0, count=1)
>      tex.format[1]: 0x44c0 = 0000aa06
>BEGIN_BATCH(2) at 294, from radeonEmitAtoms:996
>  emit tex.pitch 2/9
>      tex.pitch[0]: cmdpacket0 (first reg=0x4500, count=1)
>      tex.pitch[1]: 0x4500 = 00000000
>BEGIN_BATCH(2) at 296, from radeonEmitAtoms:996
>  emit tex.offset 2/1
>      tex.offset[0]: cmdpacket0 (first reg=0x4540, count=1)
>      tex.offset[1]: 0x4540 = 00000000
>BEGIN_BATCH(4) at 298, from emit_tex_offsets:185
>  emit tex.chroma_key 2/9
>      tex.chroma_key[0]: cmdpacket0 (first reg=0x4580, count=1)
>      tex.chroma_key[1]: 0x4580 = 00000000
>BEGIN_BATCH(2) at 300, from radeonEmitAtoms:996
>  emit tex.border_color 2/9
>      tex.border_color[0]: cmdpacket0 (first reg=0x45c0, count=1)
>      tex.border_color[1]: 0x45c0 = 00000000
>BEGIN_BATCH(2) at 302, from radeonEmitAtoms:996
>BEGIN_BATCH(31) at 304, from r300EmitClearState:238
>BEGIN_BATCH(2) at 335, from r300EmitClearState:314
>BEGIN_BATCH(2) at 337, from r300EmitClearState:319
>BEGIN_BATCH(14) at 339, from r300EmitClearState:346
>BEGIN_BATCH(7) at 353, from r300EmitClearState:397
>BEGIN_BATCH(7) at 360, from emit_r500fp:131
>BEGIN_BATCH(2) at 367, from r300EmitClearState:450
>BEGIN_BATCH(2) at 369, from r300EmitClearState:483
>BEGIN_BATCH(4) at 371, from r300EmitClearState:493
>BEGIN_BATCH(9) at 375, from emit_vpu:86
>r300ClearBuffer: buffer 0xc917e68 (0,0 640x480)
>BEGIN_BATCH(1) at 384, from cp_wait:185
>BEGIN_BATCH(1) at 385, from end_3d:162
>BEGIN_BATCH(6) at 386, from r300ClearBuffer:104
>BEGIN_BATCH(6) at 390, from r300ClearBuffer:127
>BEGIN_BATCH(9) at 396, from r300ClearBuffer:174
>BEGIN_BATCH(4) at 405, from r300EmitCacheFlush:166
>BEGIN_BATCH(1) at 409, from cp_wait:185
>radeonDrawBuffer GL_BACK
>r300Enable( GL_DEPTH_TEST = GL_TRUE )
>r300Enable( GL_STENCIL_TEST = GL_FALSE )
>r300Clear
>BEGIN_BATCH(31) at 410, from r300EmitClearState:238
>BEGIN_BATCH(2) at 441, from r300EmitClearState:314
>BEGIN_BATCH(2) at 443, from r300EmitClearState:319
>BEGIN_BATCH(14) at 445, from r300EmitClearState:346
>BEGIN_BATCH(7) at 459, from r300EmitClearState:397
>BEGIN_BATCH(7) at 466, from emit_r500fp:131
>BEGIN_BATCH(2) at 473, from r300EmitClearState:450
>BEGIN_BATCH(2) at 475, from r300EmitClearState:483
>BEGIN_BATCH(4) at 477, from r300EmitClearState:493
>BEGIN_BATCH(9) at 481, from emit_vpu:86
>r300ClearBuffer: buffer 0xc917e68 (0,0 640x480)
>BEGIN_BATCH(1) at 490, from cp_wait:185
>BEGIN_BATCH(1) at 491, from end_3d:162
>BEGIN_BATCH(6) at 492, from r300ClearBuffer:104
>BEGIN_BATCH(6) at 496, from r300ClearBuffer:127
>BEGIN_BATCH(9) at 502, from r300ClearBuffer:174
>BEGIN_BATCH(4) at 511, from r300EmitCacheFlush:166
>BEGIN_BATCH(1) at 515, from cp_wait:185
>r300Enable( GL_DEPTH_TEST = GL_FALSE )
>r300Enable( GL_TEXTURE_COORD_ARRAY = GL_FALSE )
>r300Enable( GL_TEXTURE_COORD_ARRAY = GL_TRUE )
>r300Enable( GL_TEXTURE_2D = GL_TRUE )
>radeonAllocDmaRegion 48
>radeonRefillCurrentDmaRegion
>radeonEmitVec12 count 4 stride 60 out 0xa428e000 data 0x9e5fd008
>radeonAllocDmaRegion 32
>radeonEmitVec8 count 4 stride 60 out 0xa428e040 data 0x9e5fd014
>mtu=8
>Activating texture unit 0
>TX_ENABLE: 00000001  last_hw_tmu=0
>BEGIN_BATCH(4) at 516, from r300EmitCacheFlush:166
>radeonEmitState
>Begin dirty state
>BEGIN_BATCH(1) at 520, from cp_wait:185
>BEGIN_BATCH(2) at 521, from r300_vtbl_pre_emit_atoms:234
>BEGIN_BATCH(1) at 523, from end_3d:162
>  emit vpt 7/7
>      vpt[0]: cmdpacket0 (first reg=0x1d98, count=6)
>      vpt[1]: 0x1d98 = 43a00000
>      vpt[2]: 0x1d9c = 43a00000
>      vpt[3]: 0x1da0 = c3700000
>      vpt[4]: 0x1da4 = 43700000
>      vpt[5]: 0x1da8 = 3f000000
>      vpt[6]: 0x1dac = 3f000000
>BEGIN_BATCH(7) at 524, from radeonEmitAtoms:996
>  emit vap_cntl 4/4
>      vap_cntl[0]: cmdpacket0 (first reg=0x2284, count=1)
>      vap_cntl[1]: 0x2284 = 00000000
>      vap_cntl[2]: cmdpacket0 (first reg=0x2080, count=1)
>      vap_cntl[3]: 0x2080 = 00b0056a
>BEGIN_BATCH(4) at 531, from radeonEmitAtoms:996
>  emit vte 3/3
>      vte[0]: cmdpacket0 (first reg=0x20b0, count=2)
>      vte[1]: 0x20b0 = 0000043f
>      vte[2]: 0x20b4 = 00000008
>BEGIN_BATCH(3) at 535, from radeonEmitAtoms:996
>  emit vir[0] 2/9
>      vir[0][0]: cmdpacket0 (first reg=0x2150, count=1)
>      vir[0][1]: 0x2150 = 21010002
>BEGIN_BATCH(2) at 538, from radeonEmitAtoms:996
>  emit vir[1] 2/9
>      vir[1][0]: cmdpacket0 (first reg=0x21e0, count=1)
>      vir[1][1]: 0x21e0 = fb08fa88
>BEGIN_BATCH(2) at 540, from radeonEmitAtoms:996
>  emit vic 3/3
>      vic[0]: cmdpacket0 (first reg=0x2180, count=2)
>      vic[1]: 0x2180 = 00005555
>      vic[2]: 0x2184 = 00000401
>BEGIN_BATCH(3) at 542, from radeonEmitAtoms:996
>  emit vap_clip_cntl 2/2
>      vap_clip_cntl[0]: cmdpacket0 (first reg=0x221c, count=1)
>      vap_clip_cntl[1]: 0x221c = 00000000
>BEGIN_BATCH(2) at 545, from radeonEmitAtoms:996
>  emit vof 3/3
>      vof[0]: cmdpacket0 (first reg=0x2090, count=2)
>      vof[1]: 0x2090 = 00000001
>      vof[2]: 0x2094 = 00000004
>BEGIN_BATCH(3) at 547, from radeonEmitAtoms:996
>  emit pvs 4/4
>      pvs[0]: cmdpacket0 (first reg=0x22d0, count=3)
>      pvs[1]: 0x22d0 = 00401000
>      pvs[2]: 0x22d4 = 00040000
>      pvs[3]: 0x22d8 = 00000004
>BEGIN_BATCH(4) at 550, from radeonEmitAtoms:996
>  emit txe 2/2
>      txe[0]: cmdpacket0 (first reg=0x4104, count=1)
>      txe[1]: 0x4104 = 00000001
>BEGIN_BATCH(2) at 554, from radeonEmitAtoms:996
>  emit ps 2/2
>      ps[0]: cmdpacket0 (first reg=0x421c, count=1)
>      ps[1]: 0x421c = 00060006
>BEGIN_BATCH(2) at 556, from radeonEmitAtoms:996
>  emit cul 2/2
>      cul[0]: cmdpacket0 (first reg=0x42b8, count=1)
>      cul[1]: 0x42b8 = 00000001
>BEGIN_BATCH(2) at 558, from radeonEmitAtoms:996
>  emit rc 3/3
>      rc[0]: cmdpacket0 (first reg=0x4300, count=2)
>      rc[1]: 0x4300 = 00040004
>      rc[2]: 0x4304 = 000000c0
>BEGIN_BATCH(3) at 560, from radeonEmitAtoms:996
>  emit ri 2/17
>      ri[0]: cmdpacket0 (first reg=0x4074, count=1)
>      ri[1]: 0x4074 = 000c2040
>BEGIN_BATCH(2) at 563, from radeonEmitAtoms:996
>  emit rr 2/9
>      rr[0]: cmdpacket0 (first reg=0x4320, count=1)
>      rr[1]: 0x4320 = 00000010
>BEGIN_BATCH(2) at 565, from radeonEmitAtoms:996
>  emit fp 9/9
>      fp[0]: cmdpacket0 (first reg=0x4600, count=2)
>      fp[1]: 0x4600 = 00000002
>      fp[2]: 0x4604 = 00000001
>      fp[3]: cmdpacket0 (first reg=0x4630, count=3)
>      fp[4]: 0x4630 = 00010000
>      fp[5]: 0x4634 = 00010000
>      fp[6]: 0x4638 = 00000000
>      fp[7]: cmdpacket0 (first reg=0x4624, count=1)
>      fp[8]: 0x4624 = 00000000
>BEGIN_BATCH(9) at 567, from radeonEmitAtoms:996
>  emit r500fp 13/3073
>      r500fp[0]: cmdpacket0 (first reg=0x0000, count=2)
>      r500fp[1]: 0x0000 = 00003807
>      r500fp[2]: 0x0004 = 06c00000
>      r500fp[3]: cmdpacket0 (first reg=0xe401, count=228)
>      r500fp[4]: 0xe401 = 00000000
>      r500fp[5]: 0xe405 = 00000000
>      r500fp[6]: 0xe409 = 00000000
>      r500fp[7]: 0xe40d = 00078005
>      r500fp[8]: 0xe411 = 00040001
>      r500fp[9]: 0xe415 = 00000100
>      r500fp[10]: 0xe419 = 00442220
>      r500fp[11]: 0xe41d = 00c0c000
>      r500fp[12]: 0xe421 = 20490000
>BEGIN_BATCH(13) at 576, from emit_r500fp:131
>  emit r500fp_const 5/1025
>      r500fp_const[0]: cmdpacket0 (first reg=0x0200, count=1)
>      r500fp_const[1]: 0x0200 = 3f800000
>      r500fp_const[2]: cmdpacket0 (first reg=0x3f80, count=0)
>      r500fp_const[3]: cmdpacket0 (first reg=0x3f80, count=0)
>      r500fp_const[4]: cmdpacket0 (first reg=0x3f80, count=0)
>BEGIN_BATCH(5) at 589, from emit_r500fp:131
>  emit fogs 2/2
>      fogs[0]: cmdpacket0 (first reg=0x4bc0, count=1)
>      fogs[1]: 0x4bc0 = 00000000
>BEGIN_BATCH(2) at 594, from radeonEmitAtoms:996
>  emit at 3/3
>      at[0]: cmdpacket0 (first reg=0x4bd4, count=2)
>      at[1]: 0x4bd4 = 00000000
>      at[2]: 0x4bd8 = 00000000
>BEGIN_BATCH(3) at 596, from radeonEmitAtoms:996
>  emit bld 3/3
>      bld[0]: cmdpacket0 (first reg=0x4e04, count=2)
>      bld[1]: 0x4e04 = 20210007
>      bld[2]: 0x4e08 = 20210000
>BEGIN_BATCH(3) at 599, from radeonEmitAtoms:996
>  emit cmk 2/2
>      cmk[0]: cmdpacket0 (first reg=0x4e0c, count=1)
>      cmk[1]: 0x4e0c = 0000000f
>BEGIN_BATCH(2) at 602, from radeonEmitAtoms:996
>  emit cb 4/4
>      cb[0]: cmdpacket0 (first reg=0x0000, count=0)
>      cb[1]: cmdpacket0 (first reg=0x0000, count=0)
>      cb[2]: cmdpacket0 (first reg=0x0000, count=0)
>      cb[3]: cmdpacket0 (first reg=0x0000, count=0)
>rrb is 0xc917e68 0 640x480
>BEGIN_BATCH(6) at 604, from emit_cb_offset:289
>  emit zs 4/4
>      zs[0]: cmdpacket0 (first reg=0x4f00, count=3)
>      zs[1]: 0x4f00 = 00000010
>      zs[2]: 0x4f04 = 00038038
>      zs[3]: 0x4f08 = 00ffff80
>BEGIN_BATCH(4) at 608, from radeonEmitAtoms:996
>  emit vpi 21/1025
>      vpi[0]: cmdpacket0 (first reg=0x0000, count=5)
>      vpi[1]: 0x0000 = 00100201
>      vpi[2]: 0x0004 = 00d10001
>      vpi[3]: 0x0008 = 00d10002
>      vpi[4]: 0x000c = 01248002
>      vpi[5]: 0x0010 = 00200201
>      vpi[6]: cmdpacket0 (first reg=0x00d1, count=0)
>      vpi[7]: cmdpacket0 (first reg=0x00d1, count=0)
>      vpi[8]: cmdpacket0 (first reg=0x0124, count=128)
>      vpi[9]: 0x0124 = 00400201
>      vpi[10]: 0x0128 = 00d10001
>      vpi[11]: 0x012c = 00d10042
>      vpi[12]: 0x0130 = 01248042
>      vpi[13]: 0x0134 = 00800201
>      vpi[14]: 0x0138 = 00d10001
>      vpi[15]: 0x013c = 00d10062
>      vpi[16]: 0x0140 = 01248062
>      vpi[17]: 0x0144 = 00f02203
>      vpi[18]: 0x0148 = 00d10021
>      vpi[19]: 0x014c = 01248021
>      vpi[20]: 0x0150 = 01248021
>BEGIN_BATCH(21) at 612, from emit_vpu:86
>  emit vpp 17/1025
>      vpp[0]: cmdpacket0 (first reg=0x0400, count=4)
>      vpp[1]: 0x0400 = 3b4ccccd
>      vpp[2]: 0x0404 = 00000000
>      vpp[3]: 0x0408 = 00000000
>      vpp[4]: 0x040c = bf800000
>      vpp[5]: cmdpacket0 (first reg=0x0000, count=0)
>      vpp[6]: cmdpacket0 (first reg=0xbb88, count=136)
>      vpp[7]: 0xbb88 = 00000000
>      vpp[8]: 0xbb8c = 3f800000
>      vpp[9]: 0xbb90 = 00000000
>      vpp[10]: 0xbb94 = 00000000
>      vpp[11]: 0xbb98 = c0000000
>      vpp[12]: 0xbb9c = bf800000
>      vpp[13]: 0xbba0 = 00000000
>      vpp[14]: 0xbba4 = 00000000
>      vpp[15]: 0xbba8 = 00000000
>      vpp[16]: 0xbbac = 3f800000
>BEGIN_BATCH(17) at 633, from emit_vpu:86
>  emit tex.filter 2/9
>      tex.filter[0]: cmdpacket0 (first reg=0x4400, count=1)
>      tex.filter[1]: 0x4400 = 00001400
>BEGIN_BATCH(2) at 650, from radeonEmitAtoms:996
>  emit tex.filter_1 2/9
>      tex.filter_1[0]: cmdpacket0 (first reg=0x4440, count=1)
>      tex.filter_1[1]: 0x4440 = 00000000
>BEGIN_BATCH(2) at 652, from radeonEmitAtoms:996
>  emit tex.size 2/9
>      tex.size[0]: cmdpacket0 (first reg=0x4480, count=1)
>      tex.size[1]: 0x4480 = 001ffbff
>BEGIN_BATCH(2) at 654, from radeonEmitAtoms:996
>  emit tex.format 2/9
>      tex.format[0]: cmdpacket0 (first reg=0x44c0, count=1)
>      tex.format[1]: 0x44c0 = 0000aa06
>BEGIN_BATCH(2) at 656, from radeonEmitAtoms:996
>  emit tex.pitch 2/9
>      tex.pitch[0]: cmdpacket0 (first reg=0x4500, count=1)
>      tex.pitch[1]: 0x4500 = 00000000
>BEGIN_BATCH(2) at 658, from radeonEmitAtoms:996
>  emit tex.offset 2/1
>      tex.offset[0]: cmdpacket0 (first reg=0x4540, count=1)
>      tex.offset[1]: 0x4540 = 00000000
>BEGIN_BATCH(4) at 660, from emit_tex_offsets:185
>  emit tex.chroma_key 2/9
>      tex.chroma_key[0]: cmdpacket0 (first reg=0x4580, count=1)
>      tex.chroma_key[1]: 0x4580 = 00000000
>BEGIN_BATCH(2) at 662, from radeonEmitAtoms:996
>  emit tex.border_color 2/9
>      tex.border_color[0]: cmdpacket0 (first reg=0x45c0, count=1)
>      tex.border_color[1]: 0x45c0 = 00000000
>BEGIN_BATCH(2) at 664, from radeonEmitAtoms:996
>radeonAllocDmaRegion 24
>r300EmitAOS: nr=2, ofs=0x00000000
>BEGIN_BATCH(10) at 666, from r300EmitAOS:247
>BEGIN_BATCH(10) at 672, from r300FireEB:199
>BEGIN_BATCH(4) at 680, from r300EmitCacheFlush:166
>r300Enable( GL_STENCIL_TEST = GL_TRUE )
>radeonFlush 684
>radeonEmitState
>Begin dirty state
>BEGIN_BATCH(1) at 684, from cp_wait:185
>BEGIN_BATCH(2) at 685, from r300_vtbl_pre_emit_atoms:234
>BEGIN_BATCH(1) at 687, from end_3d:162
>  emit zs 4/4
>      zs[0]: cmdpacket0 (first reg=0x4f00, count=3)
>      zs[1]: 0x4f00 = 00000011
>      zs[2]: 0x4f04 = 00038038
>      zs[3]: 0x4f08 = 00ffff80
>BEGIN_BATCH(4) at 688, from radeonEmitAtoms:996
>radeonReleaseDmaRegion 0xca119f8
>rcommonFlushCmdBufLocked from radeonFlush - 1 cliprects
>radeonFlush 0
>
>radeonCopyBuffer( 0xc5e53b8 )
>
>r300NewTextureObject( 0xca12078 (target = GL_FALSE) )
>level 0, face 0: rs:32 4x4 at 0
>level 1, face 0: rs:32 2x2 at 128
>level 2, face 0: rs:32 1x1 at 192
>r300TexParameter( GL_TEXTURE_MIN_FILTER )
>r300TexParameter( GL_TEXTURE_WRAP_S )
>r300TexParameter( GL_TEXTURE_WRAP_T )
>r300NewTextureObject( 0xca22e38 (target = GL_FALSE) )
>level 0, face 0: rs:512 256x256 at 0
>level 1, face 0: rs:256 128x128 at 131072
>level 2, face 0: rs:128 64x64 at 163840
>level 3, face 0: rs:64 32x32 at 172032
>level 4, face 0: rs:32 16x16 at 174080
>level 5, face 0: rs:32 8x8 at 174592
>level 6, face 0: rs:32 4x4 at 174848
>level 7, face 0: rs:32 2x2 at 174976
>level 8, face 0: rs:32 1x1 at 175040
>r300TexParameter( GL_TEXTURE_MIN_FILTER )
>r300TexParameter( GL_TEXTURE_WRAP_S )
>r300TexParameter( GL_TEXTURE_WRAP_T )
>r300NewTextureObject( 0xca73f00 (target = GL_FALSE) )
>level 0, face 0: rs:512 256x256 at 0
>level 1, face 0: rs:256 128x128 at 131072
>level 2, face 0: rs:128 64x64 at 163840
>level 3, face 0: rs:64 32x32 at 172032
>level 4, face 0: rs:32 16x16 at 174080
>level 5, face 0: rs:32 8x8 at 174592
>level 6, face 0: rs:32 4x4 at 174848
>level 7, face 0: rs:32 2x2 at 174976
>level 8, face 0: rs:32 1x1 at 175040
>r300TexParameter( GL_TEXTURE_MIN_FILTER )
>r300TexParameter( GL_TEXTURE_WRAP_S )
>r300TexParameter( GL_TEXTURE_WRAP_T )
>r300NewTextureObject( 0xca74f78 (target = GL_FALSE) )
>level 0, face 0: rs:512 256x256 at 0
>level 1, face 0: rs:256 128x128 at 131072
>level 2, face 0: rs:128 64x64 at 163840
>level 3, face 0: rs:64 32x32 at 172032
>level 4, face 0: rs:32 16x16 at 174080
>level 5, face 0: rs:32 8x8 at 174592
>level 6, face 0: rs:32 4x4 at 174848
>level 7, face 0: rs:32 2x2 at 174976
>level 8, face 0: rs:32 1x1 at 175040
>r300TexParameter( GL_TEXTURE_MIN_FILTER )
>r300TexParameter( GL_TEXTURE_WRAP_S )
>r300TexParameter( GL_TEXTURE_WRAP_T )
>r300NewTextureObject( 0xca75ff0 (target = GL_FALSE) )
>level 0, face 0: rs:512 256x256 at 0
>level 1, face 0: rs:256 128x128 at 131072
>level 2, face 0: rs:128 64x64 at 163840
>level 3, face 0: rs:64 32x32 at 172032
>level 4, face 0: rs:32 16x16 at 174080
>level 5, face 0: rs:32 8x8 at 174592
>level 6, face 0: rs:32 4x4 at 174848
>level 7, face 0: rs:32 2x2 at 174976
>level 8, face 0: rs:32 1x1 at 175040
>r300TexParameter( GL_TEXTURE_MIN_FILTER )
>r300TexParameter( GL_TEXTURE_WRAP_S )
>r300TexParameter( GL_TEXTURE_WRAP_T )
>r300NewTextureObject( 0xca77068 (target = GL_FALSE) )
>level 0, face 0: rs:512 256x256 at 0
>level 1, face 0: rs:256 128x128 at 131072
>level 2, face 0: rs:128 64x64 at 163840
>level 3, face 0: rs:64 32x32 at 172032
>level 4, face 0: rs:32 16x16 at 174080
>level 5, face 0: rs:32 8x8 at 174592
>level 6, face 0: rs:32 4x4 at 174848
>level 7, face 0: rs:32 2x2 at 174976
>level 8, face 0: rs:32 1x1 at 175040
>r300TexParameter( GL_TEXTURE_MIN_FILTER )
>r300TexParameter( GL_TEXTURE_WRAP_S )
>r300TexParameter( GL_TEXTURE_WRAP_T )
>r300NewTextureObject( 0xca780e0 (target = GL_FALSE) )
>level 0, face 0: rs:512 256x256 at 0
>level 1, face 0: rs:256 128x128 at 131072
>level 2, face 0: rs:128 64x64 at 163840
>level 3, face 0: rs:64 32x32 at 172032
>level 4, face 0: rs:32 16x16 at 174080
>level 5, face 0: rs:32 8x8 at 174592
>level 6, face 0: rs:32 4x4 at 174848
>level 7, face 0: rs:32 2x2 at 174976
>level 8, face 0: rs:32 1x1 at 175040
>r300TexParameter( GL_TEXTURE_MIN_FILTER )
>r300TexParameter( GL_TEXTURE_WRAP_S )
>r300TexParameter( GL_TEXTURE_WRAP_T )
>r300NewTextureObject( 0xca79158 (target = GL_FALSE) )
>level 0, face 0: rs:512 256x256 at 0
>level 1, face 0: rs:256 128x128 at 131072
>level 2, face 0: rs:128 64x64 at 163840
>level 3, face 0: rs:64 32x32 at 172032
>level 4, face 0: rs:32 16x16 at 174080
>level 5, face 0: rs:32 8x8 at 174592
>level 6, face 0: rs:32 4x4 at 174848
>level 7, face 0: rs:32 2x2 at 174976
>level 8, face 0: rs:32 1x1 at 175040
>r300TexParameter( GL_TEXTURE_MIN_FILTER )
>r300TexParameter( GL_TEXTURE_WRAP_S )
>r300TexParameter( GL_TEXTURE_WRAP_T )
>r300NewTextureObject( 0xca7a1d0 (target = GL_FALSE) )
>level 0, face 0: rs:512 256x256 at 0
>level 1, face 0: rs:256 128x128 at 131072
>level 2, face 0: rs:128 64x64 at 163840
>level 3, face 0: rs:64 32x32 at 172032
>level 4, face 0: rs:32 16x16 at 174080
>level 5, face 0: rs:32 8x8 at 174592
>level 6, face 0: rs:32 4x4 at 174848
>level 7, face 0: rs:32 2x2 at 174976
>level 8, face 0: rs:32 1x1 at 175040
>r300TexParameter( GL_TEXTURE_MIN_FILTER )
>r300TexParameter( GL_TEXTURE_WRAP_S )
>r300TexParameter( GL_TEXTURE_WRAP_T )
>r300NewTextureObject( 0xca7b248 (target = GL_FALSE) )
>level 0, face 0: rs:64 32x32 at 0
>level 1, face 0: rs:32 16x16 at 2048
>level 2, face 0: rs:32 8x8 at 2560
>level 3, face 0: rs:32 4x4 at 2816
>level 4, face 0: rs:32 2x2 at 2944
>level 5, face 0: rs:32 1x1 at 3008
>r300TexParameter( GL_TEXTURE_MIN_FILTER )
>r300TexParameter( GL_TEXTURE_WRAP_S )
>r300TexParameter( GL_TEXTURE_WRAP_T )
>r300NewTextureObject( 0xca7d1a0 (target = GL_FALSE) )
>level 0, face 0: rs:64 32x32 at 0
>level 1, face 0: rs:32 16x16 at 2048
>level 2, face 0: rs:32 8x8 at 2560
>level 3, face 0: rs:32 4x4 at 2816
>level 4, face 0: rs:32 2x2 at 2944
>level 5, face 0: rs:32 1x1 at 3008
>r300TexParameter( GL_TEXTURE_MIN_FILTER )
>r300TexParameter( GL_TEXTURE_WRAP_S )
>r300TexParameter( GL_TEXTURE_WRAP_T )
>r300NewTextureObject( 0xca7f0e0 (target = GL_FALSE) )
>level 0, face 0: rs:64 32x32 at 0
>level 1, face 0: rs:32 16x16 at 2048
>level 2, face 0: rs:32 8x8 at 2560
>level 3, face 0: rs:32 4x4 at 2816
>level 4, face 0: rs:32 2x2 at 2944
>level 5, face 0: rs:32 1x1 at 3008
>r300TexParameter( GL_TEXTURE_MIN_FILTER )
>r300TexParameter( GL_TEXTURE_WRAP_S )
>r300TexParameter( GL_TEXTURE_WRAP_T )
>r300Enable( GL_DEPTH_TEST = GL_TRUE )
>r300Enable( GL_STENCIL_TEST = GL_FALSE )
>r300Enable( GL_TEXTURE_2D = GL_FALSE )
>radeonDrawBuffer GL_BACK
>r300Enable( GL_DEPTH_TEST = GL_TRUE )
>r300Enable( GL_STENCIL_TEST = GL_FALSE )
>r300Clear
>Reemit state after flush (from r300EmitClearState)
>radeonEmitState
>Begin reemit state
>BEGIN_BATCH(1) at 0, from cp_wait:185
>BEGIN_BATCH(2) at 1, from r300_vtbl_pre_emit_atoms:234
>BEGIN_BATCH(1) at 3, from end_3d:162
>Begin dirty state
>BEGIN_BATCH(1) at 4, from cp_wait:185
>BEGIN_BATCH(2) at 5, from r300_vtbl_pre_emit_atoms:234
>BEGIN_BATCH(1) at 7, from end_3d:162
>  emit vpt 7/7
>      vpt[0]: cmdpacket0 (first reg=0x1d98, count=6)
>      vpt[1]: 0x1d98 = 43a00000
>      vpt[2]: 0x1d9c = 43a00000
>      vpt[3]: 0x1da0 = c3700000
>      vpt[4]: 0x1da4 = 43700000
>      vpt[5]: 0x1da8 = 3f000000
>      vpt[6]: 0x1dac = 3f000000
>BEGIN_BATCH(7) at 8, from radeonEmitAtoms:996
>  emit vap_cntl 4/4
>      vap_cntl[0]: cmdpacket0 (first reg=0x2284, count=1)
>      vap_cntl[1]: 0x2284 = 00000000
>      vap_cntl[2]: cmdpacket0 (first reg=0x2080, count=1)
>      vap_cntl[3]: 0x2080 = 00b0056a
>BEGIN_BATCH(4) at 15, from radeonEmitAtoms:996
>  emit vap_index_offset 2/2
>      vap_index_offset[0]: cmdpacket0 (first reg=0x208c, count=1)
>      vap_index_offset[1]: 0x208c = 00000000
>BEGIN_BATCH(2) at 19, from radeonEmitAtoms:996
>  emit vte 3/3
>      vte[0]: cmdpacket0 (first reg=0x20b0, count=2)
>      vte[1]: 0x20b0 = 0000043f
>      vte[2]: 0x20b4 = 00000008
>BEGIN_BATCH(3) at 21, from radeonEmitAtoms:996
>  emit vap_vf_max_vtx_indx 3/3
>      vap_vf_max_vtx_indx[0]: cmdpacket0 (first reg=0x2134, count=2)
>      vap_vf_max_vtx_indx[1]: 0x2134 = 00ffffff
>      vap_vf_max_vtx_indx[2]: 0x2138 = 00000000
>BEGIN_BATCH(3) at 24, from radeonEmitAtoms:996
>  emit vap_cntl_status 2/2
>      vap_cntl_status[0]: cmdpacket0 (first reg=0x2140, count=1)
>      vap_cntl_status[1]: 0x2140 = 00000000
>BEGIN_BATCH(2) at 27, from radeonEmitAtoms:996
>  emit vir[0] 2/9
>      vir[0][0]: cmdpacket0 (first reg=0x2150, count=1)
>      vir[0][1]: 0x2150 = 21010002
>BEGIN_BATCH(2) at 29, from radeonEmitAtoms:996
>  emit vir[1] 2/9
>      vir[1][0]: cmdpacket0 (first reg=0x21e0, count=1)
>      vir[1][1]: 0x21e0 = fb08fa88
>BEGIN_BATCH(2) at 31, from radeonEmitAtoms:996
>  emit vic 3/3
>      vic[0]: cmdpacket0 (first reg=0x2180, count=2)
>      vic[1]: 0x2180 = 00005555
>      vic[2]: 0x2184 = 00000401
>BEGIN_BATCH(3) at 33, from radeonEmitAtoms:996
>  emit vap_psc_sgn_norm_cntl 2/2
>      vap_psc_sgn_norm_cntl[0]: cmdpacket0 (first reg=0x21dc, count=1)
>      vap_psc_sgn_norm_cntl[1]: 0x21dc = aaaaaaaa
>BEGIN_BATCH(2) at 36, from radeonEmitAtoms:996
>  emit vap_clip_cntl 2/2
>      vap_clip_cntl[0]: cmdpacket0 (first reg=0x221c, count=1)
>      vap_clip_cntl[1]: 0x221c = 00000000
>BEGIN_BATCH(2) at 38, from radeonEmitAtoms:996
>  emit vap_clip 5/5
>      vap_clip[0]: cmdpacket0 (first reg=0x2220, count=4)
>      vap_clip[1]: 0x2220 = 3f800000
>      vap_clip[2]: 0x2224 = 3f800000
>      vap_clip[3]: 0x2228 = 3f800000
>      vap_clip[4]: 0x222c = 3f800000
>BEGIN_BATCH(5) at 40, from radeonEmitAtoms:996
>  emit vap_pvs_vtx_timeout_reg 2/2
>      vap_pvs_vtx_timeout_reg[0]: cmdpacket0 (first reg=0x2288, count=1)
>      vap_pvs_vtx_timeout_reg[1]: 0x2288 = 0000ffff
>BEGIN_BATCH(2) at 45, from radeonEmitAtoms:996
>  emit vof 3/3
>      vof[0]: cmdpacket0 (first reg=0x2090, count=2)
>      vof[1]: 0x2090 = 00000001
>      vof[2]: 0x2094 = 00000004
>BEGIN_BATCH(3) at 47, from radeonEmitAtoms:996
>  emit pvs 4/4
>      pvs[0]: cmdpacket0 (first reg=0x22d0, count=3)
>      pvs[1]: 0x22d0 = 00401000
>      pvs[2]: 0x22d4 = 00040000
>      pvs[3]: 0x22d8 = 00000004
>BEGIN_BATCH(4) at 50, from radeonEmitAtoms:996
>  emit gb_enable 2/2
>      gb_enable[0]: cmdpacket0 (first reg=0x4008, count=1)
>      gb_enable[1]: 0x4008 = 00000007
>BEGIN_BATCH(2) at 54, from radeonEmitAtoms:996
>  emit gb_misc 4/4
>      gb_misc[0]: cmdpacket0 (first reg=0x4010, count=3)
>      gb_misc[1]: 0x4010 = 66666666
>      gb_misc[2]: 0x4014 = 06666666
>      gb_misc[3]: 0x4018 = 00000011
>BEGIN_BATCH(4) at 56, from emit_gb_misc:382
>  emit gb_misc2 3/3
>      gb_misc2[0]: cmdpacket0 (first reg=0x401c, count=2)
>      gb_misc2[1]: 0x401c = 00000000
>      gb_misc2[2]: 0x4020 = 00000000
>BEGIN_BATCH(3) at 60, from radeonEmitAtoms:996
>  emit txe 2/2
>      txe[0]: cmdpacket0 (first reg=0x4104, count=1)
>      txe[1]: 0x4104 = 00000001
>BEGIN_BATCH(2) at 63, from radeonEmitAtoms:996
>  emit ga_point_s0 5/5
>      ga_point_s0[0]: cmdpacket0 (first reg=0x4200, count=4)
>      ga_point_s0[1]: 0x4200 = 00000000
>      ga_point_s0[2]: 0x4204 = 00000000
>      ga_point_s0[3]: 0x4208 = 3f800000
>      ga_point_s0[4]: 0x420c = 3f800000
>BEGIN_BATCH(5) at 65, from radeonEmitAtoms:996
>  emit ga_triangle_stipple 2/2
>      ga_triangle_stipple[0]: cmdpacket0 (first reg=0x4214, count=1)
>      ga_triangle_stipple[1]: 0x4214 = 00050005
>BEGIN_BATCH(2) at 70, from radeonEmitAtoms:996
>  emit ps 2/2
>      ps[0]: cmdpacket0 (first reg=0x421c, count=1)
>      ps[1]: 0x421c = 00060006
>BEGIN_BATCH(2) at 72, from radeonEmitAtoms:996
>  emit ga_point_minmax 4/4
>      ga_point_minmax[0]: cmdpacket0 (first reg=0x4230, count=3)
>      ga_point_minmax[1]: 0x4230 = 18000006
>      ga_point_minmax[2]: 0x4234 = 00020006
>      ga_point_minmax[3]: 0x4238 = 3baaaaab
>BEGIN_BATCH(4) at 74, from radeonEmitAtoms:996
>  emit lcntl 2/2
>      lcntl[0]: cmdpacket0 (first reg=0x4234, count=1)
>      lcntl[1]: 0x4234 = 00030006
>BEGIN_BATCH(2) at 78, from radeonEmitAtoms:996
>  emit ga_line_stipple 4/4
>      ga_line_stipple[0]: cmdpacket0 (first reg=0x4260, count=3)
>      ga_line_stipple[1]: 0x4260 = 00000000
>      ga_line_stipple[2]: 0x4264 = 00000000
>      ga_line_stipple[3]: 0x4268 = 3f800000
>BEGIN_BATCH(4) at 80, from radeonEmitAtoms:996
>  emit shade 2/2
>      shade[0]: cmdpacket0 (first reg=0x4274, count=1)
>      shade[1]: 0x4274 = 00000002
>BEGIN_BATCH(2) at 84, from emit_shade_misc:410
>  emit shade2 4/4
>      shade2[0]: cmdpacket0 (first reg=0x4278, count=3)
>      shade2[1]: 0x4278 = 0003aaaa
>      shade2[2]: 0x427c = 00000000
>      shade2[3]: 0x4280 = 00000000
>BEGIN_BATCH(4) at 86, from radeonEmitAtoms:996
>  emit polygon_mode 4/4
>      polygon_mode[0]: cmdpacket0 (first reg=0x4288, count=3)
>      polygon_mode[1]: 0x4288 = 00000000
>      polygon_mode[2]: 0x428c = 00000001
>      polygon_mode[3]: 0x4290 = 00000000
>BEGIN_BATCH(4) at 90, from radeonEmitAtoms:996
>  emit fogp 3/3
>      fogp[0]: cmdpacket0 (first reg=0x4294, count=2)
>      fogp[1]: 0x4294 = 00000000
>      fogp[2]: 0x4298 = 00000000
>BEGIN_BATCH(3) at 94, from radeonEmitAtoms:996
>  emit zbias_cntl 2/2
>      zbias_cntl[0]: cmdpacket0 (first reg=0x42a0, count=1)
>      zbias_cntl[1]: 0x42a0 = 00000000
>BEGIN_BATCH(2) at 97, from radeonEmitAtoms:996
>  emit zbs 5/5
>      zbs[0]: cmdpacket0 (first reg=0x42a4, count=4)
>      zbs[1]: 0x42a4 = 00000000
>      zbs[2]: 0x42a8 = 00000000
>      zbs[3]: 0x42ac = 00000000
>      zbs[4]: 0x42b0 = 00000000
>BEGIN_BATCH(5) at 99, from radeonEmitAtoms:996
>  emit occlusion_cntl 2/2
>      occlusion_cntl[0]: cmdpacket0 (first reg=0x42b4, count=1)
>      occlusion_cntl[1]: 0x42b4 = 00000000
>BEGIN_BATCH(2) at 104, from radeonEmitAtoms:996
>  emit cul 2/2
>      cul[0]: cmdpacket0 (first reg=0x42b8, count=1)
>      cul[1]: 0x42b8 = 00000003
>BEGIN_BATCH(2) at 106, from radeonEmitAtoms:996
>  emit su_depth_scale 3/3
>      su_depth_scale[0]: cmdpacket0 (first reg=0x42c0, count=2)
>      su_depth_scale[1]: 0x42c0 = 4b7fffff
>      su_depth_scale[2]: 0x42c4 = 00000000
>BEGIN_BATCH(3) at 108, from radeonEmitAtoms:996
>  emit rc 3/3
>      rc[0]: cmdpacket0 (first reg=0x4300, count=2)
>      rc[1]: 0x4300 = 00040004
>      rc[2]: 0x4304 = 000000c0
>BEGIN_BATCH(3) at 111, from radeonEmitAtoms:996
>  emit ri 2/17
>      ri[0]: cmdpacket0 (first reg=0x4074, count=1)
>      ri[1]: 0x4074 = 000c2040
>BEGIN_BATCH(2) at 114, from radeonEmitAtoms:996
>  emit rr 2/9
>      rr[0]: cmdpacket0 (first reg=0x4320, count=1)
>      rr[1]: 0x4320 = 00000010
>BEGIN_BATCH(2) at 116, from radeonEmitAtoms:996
>  emit sc_hyperz 3/3
>      sc_hyperz[0]: cmdpacket0 (first reg=0x43a4, count=2)
>      sc_hyperz[1]: 0x43a4 = 0000001c
>      sc_hyperz[2]: 0x43a8 = 2da49525
>BEGIN_BATCH(3) at 118, from radeonEmitAtoms:996
>  emit sc_screendoor 2/2
>      sc_screendoor[0]: cmdpacket0 (first reg=0x43e8, count=1)
>      sc_screendoor[1]: 0x43e8 = 00ffffff
>BEGIN_BATCH(2) at 121, from radeonEmitAtoms:996
>  emit us_out_fmt 6/6
>      us_out_fmt[0]: cmdpacket0 (first reg=0x46a4, count=5)
>      us_out_fmt[1]: 0x46a4 = 00001b00
>      us_out_fmt[2]: 0x46a8 = 00001b0f
>      us_out_fmt[3]: 0x46ac = 00001b0f
>      us_out_fmt[4]: 0x46b0 = 00001b0f
>      us_out_fmt[5]: 0x46b4 = 00000000
>BEGIN_BATCH(6) at 123, from radeonEmitAtoms:996
>  emit fp 9/9
>      fp[0]: cmdpacket0 (first reg=0x4600, count=2)
>      fp[1]: 0x4600 = 00000002
>      fp[2]: 0x4604 = 00000001
>      fp[3]: cmdpacket0 (first reg=0x4630, count=3)
>      fp[4]: 0x4630 = 00010000
>      fp[5]: 0x4634 = 00010000
>      fp[6]: 0x4638 = 00000000
>      fp[7]: cmdpacket0 (first reg=0x4624, count=1)
>      fp[8]: 0x4624 = 00000000
>BEGIN_BATCH(9) at 129, from radeonEmitAtoms:996
>  emit r500fp 13/3073
>      r500fp[0]: cmdpacket0 (first reg=0x0000, count=2)
>      r500fp[1]: 0x0000 = 00003807
>      r500fp[2]: 0x0004 = 06c00000
>      r500fp[3]: cmdpacket0 (first reg=0xe401, count=228)
>      r500fp[4]: 0xe401 = 00000000
>      r500fp[5]: 0xe405 = 00000000
>      r500fp[6]: 0xe409 = 00000000
>      r500fp[7]: 0xe40d = 00078005
>      r500fp[8]: 0xe411 = 00040001
>      r500fp[9]: 0xe415 = 00000100
>      r500fp[10]: 0xe419 = 00442220
>      r500fp[11]: 0xe41d = 00c0c000
>      r500fp[12]: 0xe421 = 20490000
>BEGIN_BATCH(13) at 138, from emit_r500fp:131
>  emit r500fp_const 5/1025
>      r500fp_const[0]: cmdpacket0 (first reg=0x0200, count=1)
>      r500fp_const[1]: 0x0200 = 3f800000
>      r500fp_const[2]: cmdpacket0 (first reg=0x3f80, count=0)
>      r500fp_const[3]: cmdpacket0 (first reg=0x3f80, count=0)
>      r500fp_const[4]: cmdpacket0 (first reg=0x3f80, count=0)
>BEGIN_BATCH(5) at 151, from emit_r500fp:131
>  emit fogs 2/2
>      fogs[0]: cmdpacket0 (first reg=0x4bc0, count=1)
>      fogs[1]: 0x4bc0 = 00000000
>BEGIN_BATCH(2) at 156, from radeonEmitAtoms:996
>  emit fogc 4/4
>      fogc[0]: cmdpacket0 (first reg=0x4bc8, count=3)
>      fogc[1]: 0x4bc8 = 00000000
>      fogc[2]: 0x4bcc = 00000000
>      fogc[3]: 0x4bd0 = 00000000
>BEGIN_BATCH(4) at 158, from radeonEmitAtoms:996
>  emit at 3/3
>      at[0]: cmdpacket0 (first reg=0x4bd4, count=2)
>      at[1]: 0x4bd4 = 00000000
>      at[2]: 0x4bd8 = 00000000
>BEGIN_BATCH(3) at 162, from radeonEmitAtoms:996
>  emit fg_depth_src 2/2
>      fg_depth_src[0]: cmdpacket0 (first reg=0x4bd8, count=1)
>      fg_depth_src[1]: 0x4bd8 = 00000000
>BEGIN_BATCH(2) at 165, from radeonEmitAtoms:996
>  emit rb3d_cctl 2/2
>      rb3d_cctl[0]: cmdpacket0 (first reg=0x4e00, count=1)
>      rb3d_cctl[1]: 0x4e00 = 00000000
>BEGIN_BATCH(2) at 167, from radeonEmitAtoms:996
>  emit bld 3/3
>      bld[0]: cmdpacket0 (first reg=0x4e04, count=2)
>      bld[1]: 0x4e04 = 20210007
>      bld[2]: 0x4e08 = 20210000
>BEGIN_BATCH(3) at 169, from radeonEmitAtoms:996
>  emit cmk 2/2
>      cmk[0]: cmdpacket0 (first reg=0x4e0c, count=1)
>      cmk[1]: 0x4e0c = 0000000f
>BEGIN_BATCH(2) at 172, from radeonEmitAtoms:996
>  emit blend_color 3/3
>      blend_color[0]: cmdpacket0 (first reg=0x4ef8, count=2)
>      blend_color[1]: 0x4ef8 = 00000000
>      blend_color[2]: 0x4efc = 00000000
>BEGIN_BATCH(3) at 174, from radeonEmitAtoms:996
>  emit rop 2/2
>      rop[0]: cmdpacket0 (first reg=0x4e18, count=1)
>      rop[1]: 0x4e18 = 00000000
>BEGIN_BATCH(2) at 177, from radeonEmitAtoms:996
>  emit cb 4/4
>      cb[0]: cmdpacket0 (first reg=0x0000, count=0)
>      cb[1]: cmdpacket0 (first reg=0x0000, count=0)
>      cb[2]: cmdpacket0 (first reg=0x0000, count=0)
>      cb[3]: cmdpacket0 (first reg=0x0000, count=0)
>rrb is 0xc917e68 0 640x480
>BEGIN_BATCH(6) at 179, from emit_cb_offset:289
>  emit rb3d_dither_ctl 10/10
>      rb3d_dither_ctl[0]: cmdpacket0 (first reg=0x4e50, count=9)
>      rb3d_dither_ctl[1]: 0x4e50 = 00000000
>      rb3d_dither_ctl[2]: 0x4e54 = 00000000
>      rb3d_dither_ctl[3]: 0x4e58 = 00000000
>      rb3d_dither_ctl[4]: 0x4e5c = 00000000
>      rb3d_dither_ctl[5]: 0x4e60 = 00000000
>      rb3d_dither_ctl[6]: 0x4e64 = 00000000
>      rb3d_dither_ctl[7]: 0x4e68 = 00000000
>      rb3d_dither_ctl[8]: 0x4e6c = 00000000
>      rb3d_dither_ctl[9]: 0x4e70 = 00000000
>BEGIN_BATCH(10) at 183, from radeonEmitAtoms:996
>  emit rb3d_aaresolve_ctl 2/2
>      rb3d_aaresolve_ctl[0]: cmdpacket0 (first reg=0x4e88, count=1)
>      rb3d_aaresolve_ctl[1]: 0x4e88 = 00000000
>BEGIN_BATCH(2) at 193, from radeonEmitAtoms:996
>  emit rb3d_discard_src_pixel_lte_threshold 3/3
>      rb3d_discard_src_pixel_lte_threshold[0]: cmdpacket0 (first reg=0x4ea0, count=2)
>      rb3d_discard_src_pixel_lte_threshold[1]: 0x4ea0 = 00000000
>      rb3d_discard_src_pixel_lte_threshold[2]: 0x4ea4 = ffffffff
>BEGIN_BATCH(3) at 195, from emit_threshold_misc:396
>  emit zs 4/4
>      zs[0]: cmdpacket0 (first reg=0x4f00, count=3)
>      zs[1]: 0x4f00 = 00000016
>      zs[2]: 0x4f04 = 0003803f
>      zs[3]: 0x4f08 = 00ffff80
>BEGIN_BATCH(4) at 198, from radeonEmitAtoms:996
>  emit zstencil_format 5/5
>      zstencil_format[0]: cmdpacket0 (first reg=0x4f10, count=4)
>      zstencil_format[1]: 0x4f10 = 00000002
>      zstencil_format[2]: 0x4f14 = 00000001
>      zstencil_format[3]: 0x4f18 = 00000003
>      zstencil_format[4]: 0x4f1c = 00000000
>  emit zb 3/3
>      zb[0]: cmdpacket0 (first reg=0x0000, count=0)
>      zb[1]: cmdpacket0 (first reg=0x0000, count=0)
>      zb[2]: cmdpacket0 (first reg=0x0000, count=0)
>BEGIN_BATCH(6) at 207, from emit_zb_offset:366
>  emit zb_depthclearvalue 2/2
>      zb_depthclearvalue[0]: cmdpacket0 (first reg=0x4f28, count=1)
>      zb_depthclearvalue[1]: 0x4f28 = 00000000
>BEGIN_BATCH(2) at 211, from radeonEmitAtoms:996
>  emit zb_zmask 3/3
>      zb_zmask[0]: cmdpacket0 (first reg=0x4f30, count=2)
>      zb_zmask[1]: 0x4f30 = 00000000
>      zb_zmask[2]: 0x4f34 = 00000000
>BEGIN_BATCH(3) at 213, from radeonEmitAtoms:996
>  emit zb_hiz_offset 2/2
>      zb_hiz_offset[0]: cmdpacket0 (first reg=0x4f44, count=1)
>      zb_hiz_offset[1]: 0x4f44 = 00000000
>BEGIN_BATCH(2) at 216, from radeonEmitAtoms:996
>  emit zb_hiz_pitch 2/2
>      zb_hiz_pitch[0]: cmdpacket0 (first reg=0x4f54, count=1)
>      zb_hiz_pitch[1]: 0x4f54 = 00000000
>BEGIN_BATCH(2) at 218, from radeonEmitAtoms:996
>  emit vpi 21/1025
>      vpi[0]: cmdpacket0 (first reg=0x0000, count=5)
>      vpi[1]: 0x0000 = 00100201
>      vpi[2]: 0x0004 = 00d10001
>      vpi[3]: 0x0008 = 00d10002
>      vpi[4]: 0x000c = 01248002
>      vpi[5]: 0x0010 = 00200201
>      vpi[6]: cmdpacket0 (first reg=0x00d1, count=0)
>      vpi[7]: cmdpacket0 (first reg=0x00d1, count=0)
>      vpi[8]: cmdpacket0 (first reg=0x0124, count=128)
>      vpi[9]: 0x0124 = 00400201
>      vpi[10]: 0x0128 = 00d10001
>      vpi[11]: 0x012c = 00d10042
>      vpi[12]: 0x0130 = 01248042
>      vpi[13]: 0x0134 = 00800201
>      vpi[14]: 0x0138 = 00d10001
>      vpi[15]: 0x013c = 00d10062
>      vpi[16]: 0x0140 = 01248062
>      vpi[17]: 0x0144 = 00f02203
>      vpi[18]: 0x0148 = 00d10021
>      vpi[19]: 0x014c = 01248021
>      vpi[20]: 0x0150 = 01248021
>BEGIN_BATCH(21) at 220, from emit_vpu:86
>  emit vpp 17/1025
>      vpp[0]: cmdpacket0 (first reg=0x0400, count=4)
>      vpp[1]: 0x0400 = 3b4ccccd
>      vpp[2]: 0x0404 = 00000000
>      vpp[3]: 0x0408 = 00000000
>      vpp[4]: 0x040c = bf800000
>      vpp[5]: cmdpacket0 (first reg=0x0000, count=0)
>      vpp[6]: cmdpacket0 (first reg=0xbb88, count=136)
>      vpp[7]: 0xbb88 = 00000000
>      vpp[8]: 0xbb8c = 3f800000
>      vpp[9]: 0xbb90 = 00000000
>      vpp[10]: 0xbb94 = 00000000
>      vpp[11]: 0xbb98 = c0000000
>      vpp[12]: 0xbb9c = bf800000
>      vpp[13]: 0xbba0 = 00000000
>      vpp[14]: 0xbba4 = 00000000
>      vpp[15]: 0xbba8 = 00000000
>      vpp[16]: 0xbbac = 3f800000
>BEGIN_BATCH(17) at 241, from emit_vpu:86
>  skip state vps
>  emit vpucp[i] 5/5
>      vpucp[i][0]: cmdpacket0 (first reg=0x0600, count=1)
>      vpucp[i][1]: 0x0600 = 00000000
>      vpucp[i][2]: cmdpacket0 (first reg=0x0000, count=0)
>      vpucp[i][3]: cmdpacket0 (first reg=0x0000, count=0)
>      vpucp[i][4]: cmdpacket0 (first reg=0x0000, count=0)
>BEGIN_BATCH(5) at 258, from emit_vpu:86
>  emit vpucp[i] 5/5
>      vpucp[i][0]: cmdpacket0 (first reg=0x0601, count=1)
>      vpucp[i][1]: 0x0601 = 00000000
>      vpucp[i][2]: cmdpacket0 (first reg=0x0000, count=0)
>      vpucp[i][3]: cmdpacket0 (first reg=0x0000, count=0)
>      vpucp[i][4]: cmdpacket0 (first reg=0x0000, count=0)
>BEGIN_BATCH(5) at 263, from emit_vpu:86
>  emit vpucp[i] 5/5
>      vpucp[i][0]: cmdpacket0 (first reg=0x0602, count=1)
>      vpucp[i][1]: 0x0602 = 00000000
>      vpucp[i][2]: cmdpacket0 (first reg=0x0000, count=0)
>      vpucp[i][3]: cmdpacket0 (first reg=0x0000, count=0)
>      vpucp[i][4]: cmdpacket0 (first reg=0x0000, count=0)
>BEGIN_BATCH(5) at 268, from emit_vpu:86
>  emit vpucp[i] 5/5
>      vpucp[i][0]: cmdpacket0 (first reg=0x0603, count=1)
>      vpucp[i][1]: 0x0603 = 00000000
>      vpucp[i][2]: cmdpacket0 (first reg=0x0000, count=0)
>      vpucp[i][3]: cmdpacket0 (first reg=0x0000, count=0)
>      vpucp[i][4]: cmdpacket0 (first reg=0x0000, count=0)
>BEGIN_BATCH(5) at 273, from emit_vpu:86
>  emit vpucp[i] 5/5
>      vpucp[i][0]: cmdpacket0 (first reg=0x0604, count=1)
>      vpucp[i][1]: 0x0604 = 00000000
>      vpucp[i][2]: cmdpacket0 (first reg=0x0000, count=0)
>      vpucp[i][3]: cmdpacket0 (first reg=0x0000, count=0)
>      vpucp[i][4]: cmdpacket0 (first reg=0x0000, count=0)
>BEGIN_BATCH(5) at 278, from emit_vpu:86
>  emit vpucp[i] 5/5
>      vpucp[i][0]: cmdpacket0 (first reg=0x0605, count=1)
>      vpucp[i][1]: 0x0605 = 00000000
>      vpucp[i][2]: cmdpacket0 (first reg=0x0000, count=0)
>      vpucp[i][3]: cmdpacket0 (first reg=0x0000, count=0)
>      vpucp[i][4]: cmdpacket0 (first reg=0x0000, count=0)
>BEGIN_BATCH(5) at 283, from emit_vpu:86
>  emit tex.filter 2/9
>      tex.filter[0]: cmdpacket0 (first reg=0x4400, count=1)
>      tex.filter[1]: 0x4400 = 00001400
>BEGIN_BATCH(2) at 288, from radeonEmitAtoms:996
>  emit tex.filter_1 2/9
>      tex.filter_1[0]: cmdpacket0 (first reg=0x4440, count=1)
>      tex.filter_1[1]: 0x4440 = 00000000
>BEGIN_BATCH(2) at 290, from radeonEmitAtoms:996
>  emit tex.size 2/9
>      tex.size[0]: cmdpacket0 (first reg=0x4480, count=1)
>      tex.size[1]: 0x4480 = 001ffbff
>BEGIN_BATCH(2) at 292, from radeonEmitAtoms:996
>  emit tex.format 2/9
>      tex.format[0]: cmdpacket0 (first reg=0x44c0, count=1)
>      tex.format[1]: 0x44c0 = 0000aa06
>BEGIN_BATCH(2) at 294, from radeonEmitAtoms:996
>  emit tex.pitch 2/9
>      tex.pitch[0]: cmdpacket0 (first reg=0x4500, count=1)
>      tex.pitch[1]: 0x4500 = 00000000
>BEGIN_BATCH(2) at 296, from radeonEmitAtoms:996
>  emit tex.offset 2/1
>      tex.offset[0]: cmdpacket0 (first reg=0x4540, count=1)
>      tex.offset[1]: 0x4540 = 00000000
>BEGIN_BATCH(4) at 298, from emit_tex_offsets:185
>  emit tex.chroma_key 2/9
>      tex.chroma_key[0]: cmdpacket0 (first reg=0x4580, count=1)
>      tex.chroma_key[1]: 0x4580 = 00000000
>BEGIN_BATCH(2) at 300, from radeonEmitAtoms:996
>  emit tex.border_color 2/9
>      tex.border_color[0]: cmdpacket0 (first reg=0x45c0, count=1)
>      tex.border_color[1]: 0x45c0 = 00000000
>BEGIN_BATCH(2) at 302, from radeonEmitAtoms:996
>BEGIN_BATCH(31) at 304, from r300EmitClearState:238
>BEGIN_BATCH(2) at 335, from r300EmitClearState:314
>BEGIN_BATCH(2) at 337, from r300EmitClearState:319
>BEGIN_BATCH(14) at 339, from r300EmitClearState:346
>BEGIN_BATCH(7) at 353, from r300EmitClearState:397
>BEGIN_BATCH(7) at 360, from emit_r500fp:131
>BEGIN_BATCH(2) at 367, from r300EmitClearState:450
>BEGIN_BATCH(2) at 369, from r300EmitClearState:483
>BEGIN_BATCH(4) at 371, from r300EmitClearState:493
>BEGIN_BATCH(9) at 375, from emit_vpu:86
>r300ClearBuffer: buffer 0xc917e68 (0,0 640x480)
>BEGIN_BATCH(1) at 384, from cp_wait:185
>BEGIN_BATCH(1) at 385, from end_3d:162
>BEGIN_BATCH(6) at 386, from r300ClearBuffer:104
>BEGIN_BATCH(6) at 390, from r300ClearBuffer:127
>BEGIN_BATCH(9) at 396, from r300ClearBuffer:174
>BEGIN_BATCH(4) at 405, from r300EmitCacheFlush:166
>BEGIN_BATCH(1) at 409, from cp_wait:185
>radeonDrawBuffer GL_BACK
>r300Enable( GL_DEPTH_TEST = GL_TRUE )
>r300Enable( GL_STENCIL_TEST = GL_FALSE )
>r300Clear
>BEGIN_BATCH(31) at 410, from r300EmitClearState:238
>BEGIN_BATCH(2) at 441, from r300EmitClearState:314
>BEGIN_BATCH(2) at 443, from r300EmitClearState:319
>BEGIN_BATCH(14) at 445, from r300EmitClearState:346
>BEGIN_BATCH(7) at 459, from r300EmitClearState:397
>BEGIN_BATCH(7) at 466, from emit_r500fp:131
>BEGIN_BATCH(2) at 473, from r300EmitClearState:450
>BEGIN_BATCH(2) at 475, from r300EmitClearState:483
>BEGIN_BATCH(4) at 477, from r300EmitClearState:493
>BEGIN_BATCH(9) at 481, from emit_vpu:86
>r300ClearBuffer: buffer 0xc917e68 (0,0 640x480)
>BEGIN_BATCH(1) at 490, from cp_wait:185
>BEGIN_BATCH(1) at 491, from end_3d:162
>BEGIN_BATCH(6) at 492, from r300ClearBuffer:104
>BEGIN_BATCH(6) at 496, from r300ClearBuffer:127
>BEGIN_BATCH(9) at 502, from r300ClearBuffer:174
>BEGIN_BATCH(4) at 511, from r300EmitCacheFlush:166
>BEGIN_BATCH(1) at 515, from cp_wait:185
>r300Enable( GL_DEPTH_TEST = GL_FALSE )
>r300Enable( GL_TEXTURE_COORD_ARRAY = GL_FALSE )
>r300Enable( GL_TEXTURE_COORD_ARRAY = GL_TRUE )
>r300Enable( GL_TEXTURE_2D = GL_TRUE )
>radeonAllocDmaRegion 48
>radeonRefillCurrentDmaRegion
>radeonEmitVec12 count 4 stride 60 out 0xa428e000 data 0x9e7fe008
>radeonAllocDmaRegion 32
>radeonEmitVec8 count 4 stride 60 out 0xa428e040 data 0x9e7fe014
>mtu=8
>Activating texture unit 0
>TX_ENABLE: 00000001  last_hw_tmu=0
>BEGIN_BATCH(4) at 516, from r300EmitCacheFlush:166
>radeonEmitState
>Begin dirty state
>BEGIN_BATCH(1) at 520, from cp_wait:185
>BEGIN_BATCH(2) at 521, from r300_vtbl_pre_emit_atoms:234
>BEGIN_BATCH(1) at 523, from end_3d:162
>  emit vpt 7/7
>      vpt[0]: cmdpacket0 (first reg=0x1d98, count=6)
>      vpt[1]: 0x1d98 = 43a00000
>      vpt[2]: 0x1d9c = 43a00000
>      vpt[3]: 0x1da0 = c3700000
>      vpt[4]: 0x1da4 = 43700000
>      vpt[5]: 0x1da8 = 3f000000
>      vpt[6]: 0x1dac = 3f000000
>BEGIN_BATCH(7) at 524, from radeonEmitAtoms:996
>  emit vap_cntl 4/4
>      vap_cntl[0]: cmdpacket0 (first reg=0x2284, count=1)
>      vap_cntl[1]: 0x2284 = 00000000
>      vap_cntl[2]: cmdpacket0 (first reg=0x2080, count=1)
>      vap_cntl[3]: 0x2080 = 00b0056a
>BEGIN_BATCH(4) at 531, from radeonEmitAtoms:996
>  emit vte 3/3
>      vte[0]: cmdpacket0 (first reg=0x20b0, count=2)
>      vte[1]: 0x20b0 = 0000043f
>      vte[2]: 0x20b4 = 00000008
>BEGIN_BATCH(3) at 535, from radeonEmitAtoms:996
>  emit vir[0] 2/9
>      vir[0][0]: cmdpacket0 (first reg=0x2150, count=1)
>      vir[0][1]: 0x2150 = 21010002
>BEGIN_BATCH(2) at 538, from radeonEmitAtoms:996
>  emit vir[1] 2/9
>      vir[1][0]: cmdpacket0 (first reg=0x21e0, count=1)
>      vir[1][1]: 0x21e0 = fb08fa88
>BEGIN_BATCH(2) at 540, from radeonEmitAtoms:996
>  emit vic 3/3
>      vic[0]: cmdpacket0 (first reg=0x2180, count=2)
>      vic[1]: 0x2180 = 00005555
>      vic[2]: 0x2184 = 00000401
>BEGIN_BATCH(3) at 542, from radeonEmitAtoms:996
>  emit vap_clip_cntl 2/2
>      vap_clip_cntl[0]: cmdpacket0 (first reg=0x221c, count=1)
>      vap_clip_cntl[1]: 0x221c = 00000000
>BEGIN_BATCH(2) at 545, from radeonEmitAtoms:996
>  emit vof 3/3
>      vof[0]: cmdpacket0 (first reg=0x2090, count=2)
>      vof[1]: 0x2090 = 00000001
>      vof[2]: 0x2094 = 00000004
>BEGIN_BATCH(3) at 547, from radeonEmitAtoms:996
>  emit pvs 4/4
>      pvs[0]: cmdpacket0 (first reg=0x22d0, count=3)
>      pvs[1]: 0x22d0 = 00401000
>      pvs[2]: 0x22d4 = 00040000
>      pvs[3]: 0x22d8 = 00000004
>BEGIN_BATCH(4) at 550, from radeonEmitAtoms:996
>  emit txe 2/2
>      txe[0]: cmdpacket0 (first reg=0x4104, count=1)
>      txe[1]: 0x4104 = 00000001
>BEGIN_BATCH(2) at 554, from radeonEmitAtoms:996
>  emit ps 2/2
>      ps[0]: cmdpacket0 (first reg=0x421c, count=1)
>      ps[1]: 0x421c = 00060006
>BEGIN_BATCH(2) at 556, from radeonEmitAtoms:996
>  emit cul 2/2
>      cul[0]: cmdpacket0 (first reg=0x42b8, count=1)
>      cul[1]: 0x42b8 = 00000001
>BEGIN_BATCH(2) at 558, from radeonEmitAtoms:996
>  emit rc 3/3
>      rc[0]: cmdpacket0 (first reg=0x4300, count=2)
>      rc[1]: 0x4300 = 00040004
>      rc[2]: 0x4304 = 000000c0
>BEGIN_BATCH(3) at 560, from radeonEmitAtoms:996
>  emit ri 2/17
>      ri[0]: cmdpacket0 (first reg=0x4074, count=1)
>      ri[1]: 0x4074 = 000c2040
>BEGIN_BATCH(2) at 563, from radeonEmitAtoms:996
>  emit rr 2/9
>      rr[0]: cmdpacket0 (first reg=0x4320, count=1)
>      rr[1]: 0x4320 = 00000010
>BEGIN_BATCH(2) at 565, from radeonEmitAtoms:996
>  emit fp 9/9
>      fp[0]: cmdpacket0 (first reg=0x4600, count=2)
>      fp[1]: 0x4600 = 00000002
>      fp[2]: 0x4604 = 00000001
>      fp[3]: cmdpacket0 (first reg=0x4630, count=3)
>      fp[4]: 0x4630 = 00010000
>      fp[5]: 0x4634 = 00010000
>      fp[6]: 0x4638 = 00000000
>      fp[7]: cmdpacket0 (first reg=0x4624, count=1)
>      fp[8]: 0x4624 = 00000000
>BEGIN_BATCH(9) at 567, from radeonEmitAtoms:996
>  emit r500fp 13/3073
>      r500fp[0]: cmdpacket0 (first reg=0x0000, count=2)
>      r500fp[1]: 0x0000 = 00003807
>      r500fp[2]: 0x0004 = 06c00000
>      r500fp[3]: cmdpacket0 (first reg=0xe401, count=228)
>      r500fp[4]: 0xe401 = 00000000
>      r500fp[5]: 0xe405 = 00000000
>      r500fp[6]: 0xe409 = 00000000
>      r500fp[7]: 0xe40d = 00078005
>      r500fp[8]: 0xe411 = 00040001
>      r500fp[9]: 0xe415 = 00000100
>      r500fp[10]: 0xe419 = 00442220
>      r500fp[11]: 0xe41d = 00c0c000
>      r500fp[12]: 0xe421 = 20490000
>BEGIN_BATCH(13) at 576, from emit_r500fp:131
>  emit r500fp_const 5/1025
>      r500fp_const[0]: cmdpacket0 (first reg=0x0200, count=1)
>      r500fp_const[1]: 0x0200 = 3f800000
>      r500fp_const[2]: cmdpacket0 (first reg=0x3f80, count=0)
>      r500fp_const[3]: cmdpacket0 (first reg=0x3f80, count=0)
>      r500fp_const[4]: cmdpacket0 (first reg=0x3f80, count=0)
>BEGIN_BATCH(5) at 589, from emit_r500fp:131
>  emit fogs 2/2
>      fogs[0]: cmdpacket0 (first reg=0x4bc0, count=1)
>      fogs[1]: 0x4bc0 = 00000000
>BEGIN_BATCH(2) at 594, from radeonEmitAtoms:996
>  emit at 3/3
>      at[0]: cmdpacket0 (first reg=0x4bd4, count=2)
>      at[1]: 0x4bd4 = 00000000
>      at[2]: 0x4bd8 = 00000000
>BEGIN_BATCH(3) at 596, from radeonEmitAtoms:996
>  emit bld 3/3
>      bld[0]: cmdpacket0 (first reg=0x4e04, count=2)
>      bld[1]: 0x4e04 = 20210007
>      bld[2]: 0x4e08 = 20210000
>BEGIN_BATCH(3) at 599, from radeonEmitAtoms:996
>  emit cmk 2/2
>      cmk[0]: cmdpacket0 (first reg=0x4e0c, count=1)
>      cmk[1]: 0x4e0c = 0000000f
>BEGIN_BATCH(2) at 602, from radeonEmitAtoms:996
>  emit cb 4/4
>      cb[0]: cmdpacket0 (first reg=0x0000, count=0)
>      cb[1]: cmdpacket0 (first reg=0x0000, count=0)
>      cb[2]: cmdpacket0 (first reg=0x0000, count=0)
>      cb[3]: cmdpacket0 (first reg=0x0000, count=0)
>rrb is 0xc917e68 0 640x480
>BEGIN_BATCH(6) at 604, from emit_cb_offset:289
>  emit zs 4/4
>      zs[0]: cmdpacket0 (first reg=0x4f00, count=3)
>      zs[1]: 0x4f00 = 00000010
>      zs[2]: 0x4f04 = 00038038
>      zs[3]: 0x4f08 = 00ffff80
>BEGIN_BATCH(4) at 608, from radeonEmitAtoms:996
>  emit vpi 21/1025
>      vpi[0]: cmdpacket0 (first reg=0x0000, count=5)
>      vpi[1]: 0x0000 = 00100201
>      vpi[2]: 0x0004 = 00d10001
>      vpi[3]: 0x0008 = 00d10002
>      vpi[4]: 0x000c = 01248002
>      vpi[5]: 0x0010 = 00200201
>      vpi[6]: cmdpacket0 (first reg=0x00d1, count=0)
>      vpi[7]: cmdpacket0 (first reg=0x00d1, count=0)
>      vpi[8]: cmdpacket0 (first reg=0x0124, count=128)
>      vpi[9]: 0x0124 = 00400201
>      vpi[10]: 0x0128 = 00d10001
>      vpi[11]: 0x012c = 00d10042
>      vpi[12]: 0x0130 = 01248042
>      vpi[13]: 0x0134 = 00800201
>      vpi[14]: 0x0138 = 00d10001
>      vpi[15]: 0x013c = 00d10062
>      vpi[16]: 0x0140 = 01248062
>      vpi[17]: 0x0144 = 00f02203
>      vpi[18]: 0x0148 = 00d10021
>      vpi[19]: 0x014c = 01248021
>      vpi[20]: 0x0150 = 01248021
>BEGIN_BATCH(21) at 612, from emit_vpu:86
>  emit vpp 17/1025
>      vpp[0]: cmdpacket0 (first reg=0x0400, count=4)
>      vpp[1]: 0x0400 = 3b4ccccd
>      vpp[2]: 0x0404 = 00000000
>      vpp[3]: 0x0408 = 00000000
>      vpp[4]: 0x040c = bf800000
>      vpp[5]: cmdpacket0 (first reg=0x0000, count=0)
>      vpp[6]: cmdpacket0 (first reg=0xbb88, count=136)
>      vpp[7]: 0xbb88 = 00000000
>      vpp[8]: 0xbb8c = 3f800000
>      vpp[9]: 0xbb90 = 00000000
>      vpp[10]: 0xbb94 = 00000000
>      vpp[11]: 0xbb98 = c0000000
>      vpp[12]: 0xbb9c = bf800000
>      vpp[13]: 0xbba0 = 00000000
>      vpp[14]: 0xbba4 = 00000000
>      vpp[15]: 0xbba8 = 00000000
>      vpp[16]: 0xbbac = 3f800000
>BEGIN_BATCH(17) at 633, from emit_vpu:86
>  emit tex.filter 2/9
>      tex.filter[0]: cmdpacket0 (first reg=0x4400, count=1)
>      tex.filter[1]: 0x4400 = 00001400
>BEGIN_BATCH(2) at 650, from radeonEmitAtoms:996
>  emit tex.filter_1 2/9
>      tex.filter_1[0]: cmdpacket0 (first reg=0x4440, count=1)
>      tex.filter_1[1]: 0x4440 = 00000000
>BEGIN_BATCH(2) at 652, from radeonEmitAtoms:996
>  emit tex.size 2/9
>      tex.size[0]: cmdpacket0 (first reg=0x4480, count=1)
>      tex.size[1]: 0x4480 = 001ffbff
>BEGIN_BATCH(2) at 654, from radeonEmitAtoms:996
>  emit tex.format 2/9
>      tex.format[0]: cmdpacket0 (first reg=0x44c0, count=1)
>      tex.format[1]: 0x44c0 = 0000aa06
>BEGIN_BATCH(2) at 656, from radeonEmitAtoms:996
>  emit tex.pitch 2/9
>      tex.pitch[0]: cmdpacket0 (first reg=0x4500, count=1)
>      tex.pitch[1]: 0x4500 = 00000000
>BEGIN_BATCH(2) at 658, from radeonEmitAtoms:996
>  emit tex.offset 2/1
>      tex.offset[0]: cmdpacket0 (first reg=0x4540, count=1)
>      tex.offset[1]: 0x4540 = 00000000
>BEGIN_BATCH(4) at 660, from emit_tex_offsets:185
>  emit tex.chroma_key 2/9
>      tex.chroma_key[0]: cmdpacket0 (first reg=0x4580, count=1)
>      tex.chroma_key[1]: 0x4580 = 00000000
>BEGIN_BATCH(2) at 662, from radeonEmitAtoms:996
>  emit tex.border_color 2/9
>      tex.border_color[0]: cmdpacket0 (first reg=0x45c0, count=1)
>      tex.border_color[1]: 0x45c0 = 00000000
>BEGIN_BATCH(2) at 664, from radeonEmitAtoms:996
>radeonAllocDmaRegion 24
>r300EmitAOS: nr=2, ofs=0x00000000
>BEGIN_BATCH(10) at 666, from r300EmitAOS:247
>BEGIN_BATCH(10) at 672, from r300FireEB:199
>BEGIN_BATCH(4) at 680, from r300EmitCacheFlush:166
>r300Enable( GL_STENCIL_TEST = GL_TRUE )
>radeonFlush 684
>radeonEmitState
>Begin dirty state
>BEGIN_BATCH(1) at 684, from cp_wait:185
>BEGIN_BATCH(2) at 685, from r300_vtbl_pre_emit_atoms:234
>BEGIN_BATCH(1) at 687, from end_3d:162
>  emit zs 4/4
>      zs[0]: cmdpacket0 (first reg=0x4f00, count=3)
>      zs[1]: 0x4f00 = 00000011
>      zs[2]: 0x4f04 = 00038038
>      zs[3]: 0x4f08 = 00ffff80
>BEGIN_BATCH(4) at 688, from radeonEmitAtoms:996
>radeonReleaseDmaRegion 0xca80a00
>rcommonFlushCmdBufLocked from radeonFlush - 1 cliprects
>radeonFlush 0
>
>radeonCopyBuffer( 0xc5e53b8 )
>
>r300NewTextureObject( 0xd0fded0 (target = GL_FALSE) )
>level 0, face 0: rs:512 256x256 at 0
>level 1, face 0: rs:256 128x128 at 131072
>level 2, face 0: rs:128 64x64 at 163840
>level 3, face 0: rs:64 32x32 at 172032
>level 4, face 0: rs:32 16x16 at 174080
>level 5, face 0: rs:32 8x8 at 174592
>level 6, face 0: rs:32 4x4 at 174848
>level 7, face 0: rs:32 2x2 at 174976
>level 8, face 0: rs:32 1x1 at 175040
>r300TexParameter( GL_TEXTURE_MIN_FILTER )
>r300NewTextureObject( 0xd25d120 (target = GL_FALSE) )
>level 0, face 0: rs:32 2x64 at 0
>level 1, face 0: rs:32 1x32 at 2048
>level 2, face 0: rs:32 1x16 at 3072
>level 3, face 0: rs:32 1x8 at 3584
>level 4, face 0: rs:32 1x4 at 3840
>level 5, face 0: rs:32 1x2 at 3968
>level 6, face 0: rs:32 1x1 at 4032
>r300TexParameter( GL_TEXTURE_MIN_FILTER )
>r300NewTextureObject( 0xd2ff628 (target = GL_FALSE) )
>level 0, face 0: rs:512 256x32 at 0
>level 1, face 0: rs:256 128x16 at 16384
>level 2, face 0: rs:128 64x8 at 20480
>level 3, face 0: rs:64 32x4 at 21504
>level 4, face 0: rs:32 16x2 at 21760
>level 5, face 0: rs:32 8x1 at 21824
>level 6, face 0: rs:32 4x1 at 21856
>level 7, face 0: rs:32 2x1 at 21888
>level 8, face 0: rs:32 1x1 at 21920
>r300TexParameter( GL_TEXTURE_MIN_FILTER )
>r300NewTextureObject( 0xd2cf638 (target = GL_FALSE) )
>level 0, face 0: rs:512 256x32 at 0
>level 1, face 0: rs:256 128x16 at 16384
>level 2, face 0: rs:128 64x8 at 20480
>level 3, face 0: rs:64 32x4 at 21504
>level 4, face 0: rs:32 16x2 at 21760
>level 5, face 0: rs:32 8x1 at 21824
>level 6, face 0: rs:32 4x1 at 21856
>level 7, face 0: rs:32 2x1 at 21888
>level 8, face 0: rs:32 1x1 at 21920
>r300TexParameter( GL_TEXTURE_MIN_FILTER )
>r300NewTextureObject( 0xd2e9698 (target = GL_FALSE) )
>level 0, face 0: rs:512 256x32 at 0
>level 1, face 0: rs:256 128x16 at 16384
>level 2, face 0: rs:128 64x8 at 20480
>level 3, face 0: rs:64 32x4 at 21504
>level 4, face 0: rs:32 16x2 at 21760
>level 5, face 0: rs:32 8x1 at 21824
>level 6, face 0: rs:32 4x1 at 21856
>level 7, face 0: rs:32 2x1 at 21888
>level 8, face 0: rs:32 1x1 at 21920
>r300TexParameter( GL_TEXTURE_MIN_FILTER )
>r300NewTextureObject( 0xd2ea3b8 (target = GL_FALSE) )
>level 0, face 0: rs:1024 512x64 at 0
>level 1, face 0: rs:512 256x32 at 65536
>level 2, face 0: rs:256 128x16 at 81920
>level 3, face 0: rs:128 64x8 at 86016
>level 4, face 0: rs:64 32x4 at 87040
>level 5, face 0: rs:32 16x2 at 87296
>level 6, face 0: rs:32 8x1 at 87360
>level 7, face 0: rs:32 4x1 at 87392
>level 8, face 0: rs:32 2x1 at 87424
>level 9, face 0: rs:32 1x1 at 87456
>r300TexParameter( GL_TEXTURE_MIN_FILTER )
>r300TexParameter( GL_TEXTURE_WRAP_S )
>r300TexParameter( GL_TEXTURE_WRAP_T )
>r300NewTextureObject( 0xd2eb388 (target = GL_FALSE) )
>level 0, face 0: rs:32 2x64 at 0
>level 1, face 0: rs:32 1x32 at 2048
>level 2, face 0: rs:32 1x16 at 3072
>level 3, face 0: rs:32 1x8 at 3584
>level 4, face 0: rs:32 1x4 at 3840
>level 5, face 0: rs:32 1x2 at 3968
>level 6, face 0: rs:32 1x1 at 4032
>r300TexParameter( GL_TEXTURE_MIN_FILTER )
>r300TexParameter( GL_TEXTURE_WRAP_S )
>r300TexParameter( GL_TEXTURE_WRAP_T )
>r300NewTextureObject( 0xd0fac18 (target = GL_FALSE) )
>level 0, face 0: rs:256 128x64 at 0
>level 1, face 0: rs:128 64x32 at 16384
>level 2, face 0: rs:64 32x16 at 20480
>level 3, face 0: rs:32 16x8 at 21504
>level 4, face 0: rs:32 8x4 at 21760
>level 5, face 0: rs:32 4x2 at 21888
>level 6, face 0: rs:32 2x1 at 21952
>level 7, face 0: rs:32 1x1 at 21984
>r300TexParameter( GL_TEXTURE_MIN_FILTER )
>r300NewTextureObject( 0xd2c2150 (target = GL_FALSE) )
>level 0, face 0: rs:256 128x128 at 0
>level 1, face 0: rs:128 64x64 at 32768
>level 2, face 0: rs:64 32x32 at 40960
>level 3, face 0: rs:32 16x16 at 43008
>level 4, face 0: rs:32 8x8 at 43520
>level 5, face 0: rs:32 4x4 at 43776
>level 6, face 0: rs:32 2x2 at 43904
>level 7, face 0: rs:32 1x1 at 43968
>r300TexParameter( GL_TEXTURE_MIN_FILTER )
>r300NewTextureObject( 0xd2c3138 (target = GL_FALSE) )
>level 0, face 0: rs:256 128x128 at 0
>level 1, face 0: rs:128 64x64 at 32768
>level 2, face 0: rs:64 32x32 at 40960
>level 3, face 0: rs:32 16x16 at 43008
>level 4, face 0: rs:32 8x8 at 43520
>level 5, face 0: rs:32 4x4 at 43776
>level 6, face 0: rs:32 2x2 at 43904
>level 7, face 0: rs:32 1x1 at 43968
>r300TexParameter( GL_TEXTURE_MIN_FILTER )
>r300NewTextureObject( 0xd2b3d10 (target = GL_FALSE) )
>level 0, face 0: rs:256 128x128 at 0
>level 1, face 0: rs:128 64x64 at 32768
>level 2, face 0: rs:64 32x32 at 40960
>level 3, face 0: rs:32 16x16 at 43008
>level 4, face 0: rs:32 8x8 at 43520
>level 5, face 0: rs:32 4x4 at 43776
>level 6, face 0: rs:32 2x2 at 43904
>level 7, face 0: rs:32 1x1 at 43968
>r300TexParameter( GL_TEXTURE_MIN_FILTER )
>r300NewTextureObject( 0xd2b4c88 (target = GL_FALSE) )
>level 0, face 0: rs:256 128x128 at 0
>level 1, face 0: rs:128 64x64 at 32768
>level 2, face 0: rs:64 32x32 at 40960
>level 3, face 0: rs:32 16x16 at 43008
>level 4, face 0: rs:32 8x8 at 43520
>level 5, face 0: rs:32 4x4 at 43776
>level 6, face 0: rs:32 2x2 at 43904
>level 7, face 0: rs:32 1x1 at 43968
>r300TexParameter( GL_TEXTURE_MIN_FILTER )
>r300NewTextureObject( 0xd2b5c70 (target = GL_FALSE) )
>level 0, face 0: rs:256 128x128 at 0
>level 1, face 0: rs:128 64x64 at 32768
>level 2, face 0: rs:64 32x32 at 40960
>level 3, face 0: rs:32 16x16 at 43008
>level 4, face 0: rs:32 8x8 at 43520
>level 5, face 0: rs:32 4x4 at 43776
>level 6, face 0: rs:32 2x2 at 43904
>level 7, face 0: rs:32 1x1 at 43968
>r300TexParameter( GL_TEXTURE_MIN_FILTER )
>r300NewTextureObject( 0xd2b6c58 (target = GL_FALSE) )
>level 0, face 0: rs:256 128x128 at 0
>level 1, face 0: rs:128 64x64 at 32768
>level 2, face 0: rs:64 32x32 at 40960
>level 3, face 0: rs:32 16x16 at 43008
>level 4, face 0: rs:32 8x8 at 43520
>level 5, face 0: rs:32 4x4 at 43776
>level 6, face 0: rs:32 2x2 at 43904
>level 7, face 0: rs:32 1x1 at 43968
>r300TexParameter( GL_TEXTURE_MIN_FILTER )
>r300NewTextureObject( 0xd2b7c40 (target = GL_FALSE) )
>level 0, face 0: rs:256 128x128 at 0
>level 1, face 0: rs:128 64x64 at 32768
>level 2, face 0: rs:64 32x32 at 40960
>level 3, face 0: rs:32 16x16 at 43008
>level 4, face 0: rs:32 8x8 at 43520
>level 5, face 0: rs:32 4x4 at 43776
>level 6, face 0: rs:32 2x2 at 43904
>level 7, face 0: rs:32 1x1 at 43968
>r300TexParameter( GL_TEXTURE_MIN_FILTER )
>r300TexParameter( GL_TEXTURE_WRAP_S )
>r300TexParameter( GL_TEXTURE_WRAP_T )
>r300NewTextureObject( 0xd2b8c88 (target = GL_FALSE) )
>level 0, face 0: rs:256 128x128 at 0
>level 1, face 0: rs:128 64x64 at 32768
>level 2, face 0: rs:64 32x32 at 40960
>level 3, face 0: rs:32 16x16 at 43008
>level 4, face 0: rs:32 8x8 at 43520
>level 5, face 0: rs:32 4x4 at 43776
>level 6, face 0: rs:32 2x2 at 43904
>level 7, face 0: rs:32 1x1 at 43968
>r300TexParameter( GL_TEXTURE_MIN_FILTER )
>r300TexParameter( GL_TEXTURE_WRAP_S )
>r300TexParameter( GL_TEXTURE_WRAP_T )
>r300NewTextureObject( 0xd2b9cd0 (target = GL_FALSE) )
>level 0, face 0: rs:256 128x128 at 0
>level 1, face 0: rs:128 64x64 at 32768
>level 2, face 0: rs:64 32x32 at 40960
>level 3, face 0: rs:32 16x16 at 43008
>level 4, face 0: rs:32 8x8 at 43520
>level 5, face 0: rs:32 4x4 at 43776
>level 6, face 0: rs:32 2x2 at 43904
>level 7, face 0: rs:32 1x1 at 43968
>r300TexParameter( GL_TEXTURE_MIN_FILTER )
>r300TexParameter( GL_TEXTURE_WRAP_S )
>r300TexParameter( GL_TEXTURE_WRAP_T )
>r300NewTextureObject( 0xd2bad18 (target = GL_FALSE) )
>level 0, face 0: rs:256 128x128 at 0
>level 1, face 0: rs:128 64x64 at 32768
>level 2, face 0: rs:64 32x32 at 40960
>level 3, face 0: rs:32 16x16 at 43008
>level 4, face 0: rs:32 8x8 at 43520
>level 5, face 0: rs:32 4x4 at 43776
>level 6, face 0: rs:32 2x2 at 43904
>level 7, face 0: rs:32 1x1 at 43968
>r300TexParameter( GL_TEXTURE_MIN_FILTER )
>r300TexParameter( GL_TEXTURE_WRAP_S )
>r300TexParameter( GL_TEXTURE_WRAP_T )
>r300NewTextureObject( 0xd2d9d88 (target = GL_FALSE) )
>level 0, face 0: rs:256 128x128 at 0
>level 1, face 0: rs:128 64x64 at 32768
>level 2, face 0: rs:64 32x32 at 40960
>level 3, face 0: rs:32 16x16 at 43008
>level 4, face 0: rs:32 8x8 at 43520
>level 5, face 0: rs:32 4x4 at 43776
>level 6, face 0: rs:32 2x2 at 43904
>level 7, face 0: rs:32 1x1 at 43968
>r300TexParameter( GL_TEXTURE_MIN_FILTER )
>r300TexParameter( GL_TEXTURE_WRAP_S )
>r300TexParameter( GL_TEXTURE_WRAP_T )
>r300NewTextureObject( 0xd2e5dd8 (target = GL_FALSE) )
>level 0, face 0: rs:256 128x128 at 0
>level 1, face 0: rs:128 64x64 at 32768
>level 2, face 0: rs:64 32x32 at 40960
>level 3, face 0: rs:32 16x16 at 43008
>level 4, face 0: rs:32 8x8 at 43520
>level 5, face 0: rs:32 4x4 at 43776
>level 6, face 0: rs:32 2x2 at 43904
>level 7, face 0: rs:32 1x1 at 43968
>r300TexParameter( GL_TEXTURE_MIN_FILTER )
>r300TexParameter( GL_TEXTURE_WRAP_S )
>r300TexParameter( GL_TEXTURE_WRAP_T )
>r300NewTextureObject( 0xd2e6e20 (target = GL_FALSE) )
>level 0, face 0: rs:256 128x128 at 0
>level 1, face 0: rs:128 64x64 at 32768
>level 2, face 0: rs:64 32x32 at 40960
>level 3, face 0: rs:32 16x16 at 43008
>level 4, face 0: rs:32 8x8 at 43520
>level 5, face 0: rs:32 4x4 at 43776
>level 6, face 0: rs:32 2x2 at 43904
>level 7, face 0: rs:32 1x1 at 43968
>r300TexParameter( GL_TEXTURE_MIN_FILTER )
>r300TexParameter( GL_TEXTURE_WRAP_S )
>r300TexParameter( GL_TEXTURE_WRAP_T )
>r300NewTextureObject( 0xd2e7e68 (target = GL_FALSE) )
>level 0, face 0: rs:256 128x128 at 0
>level 1, face 0: rs:128 64x64 at 32768
>level 2, face 0: rs:64 32x32 at 40960
>level 3, face 0: rs:32 16x16 at 43008
>level 4, face 0: rs:32 8x8 at 43520
>level 5, face 0: rs:32 4x4 at 43776
>level 6, face 0: rs:32 2x2 at 43904
>level 7, face 0: rs:32 1x1 at 43968
>r300TexParameter( GL_TEXTURE_MIN_FILTER )
>r300TexParameter( GL_TEXTURE_WRAP_S )
>r300TexParameter( GL_TEXTURE_WRAP_T )
>r300NewTextureObject( 0xd2e8eb0 (target = GL_FALSE) )
>level 0, face 0: rs:512 256x256 at 0
>level 1, face 0: rs:256 128x128 at 131072
>level 2, face 0: rs:128 64x64 at 163840
>level 3, face 0: rs:64 32x32 at 172032
>level 4, face 0: rs:32 16x16 at 174080
>level 5, face 0: rs:32 8x8 at 174592
>level 6, face 0: rs:32 4x4 at 174848
>level 7, face 0: rs:32 2x2 at 174976
>level 8, face 0: rs:32 1x1 at 175040
>r300TexParameter( GL_TEXTURE_MIN_FILTER )
>r300TexParameter( GL_TEXTURE_WRAP_S )
>r300TexParameter( GL_TEXTURE_WRAP_T )
>r300NewTextureObject( 0xd3e6378 (target = GL_FALSE) )
>level 0, face 0: rs:512 256x256 at 0
>level 1, face 0: rs:256 128x128 at 131072
>level 2, face 0: rs:128 64x64 at 163840
>level 3, face 0: rs:64 32x32 at 172032
>level 4, face 0: rs:32 16x16 at 174080
>level 5, face 0: rs:32 8x8 at 174592
>level 6, face 0: rs:32 4x4 at 174848
>level 7, face 0: rs:32 2x2 at 174976
>level 8, face 0: rs:32 1x1 at 175040
>r300TexParameter( GL_TEXTURE_MIN_FILTER )
>r300TexParameter( GL_TEXTURE_WRAP_S )
>r300TexParameter( GL_TEXTURE_WRAP_T )
>r300NewTextureObject( 0xd3e7450 (target = GL_FALSE) )
>level 0, face 0: rs:512 256x256 at 0
>level 1, face 0: rs:256 128x128 at 131072
>level 2, face 0: rs:128 64x64 at 163840
>level 3, face 0: rs:64 32x32 at 172032
>level 4, face 0: rs:32 16x16 at 174080
>level 5, face 0: rs:32 8x8 at 174592
>level 6, face 0: rs:32 4x4 at 174848
>level 7, face 0: rs:32 2x2 at 174976
>level 8, face 0: rs:32 1x1 at 175040
>r300TexParameter( GL_TEXTURE_MIN_FILTER )
>r300TexParameter( GL_TEXTURE_WRAP_S )
>r300TexParameter( GL_TEXTURE_WRAP_T )
>r300NewTextureObject( 0xd3e8528 (target = GL_FALSE) )
>level 0, face 0: rs:512 256x256 at 0
>level 1, face 0: rs:256 128x128 at 131072
>level 2, face 0: rs:128 64x64 at 163840
>level 3, face 0: rs:64 32x32 at 172032
>level 4, face 0: rs:32 16x16 at 174080
>level 5, face 0: rs:32 8x8 at 174592
>level 6, face 0: rs:32 4x4 at 174848
>level 7, face 0: rs:32 2x2 at 174976
>level 8, face 0: rs:32 1x1 at 175040
>r300TexParameter( GL_TEXTURE_MIN_FILTER )
>r300TexParameter( GL_TEXTURE_WRAP_S )
>r300TexParameter( GL_TEXTURE_WRAP_T )
>r300NewTextureObject( 0xd3e9600 (target = GL_FALSE) )
>level 0, face 0: rs:512 256x256 at 0
>level 1, face 0: rs:256 128x128 at 131072
>level 2, face 0: rs:128 64x64 at 163840
>level 3, face 0: rs:64 32x32 at 172032
>level 4, face 0: rs:32 16x16 at 174080
>level 5, face 0: rs:32 8x8 at 174592
>level 6, face 0: rs:32 4x4 at 174848
>level 7, face 0: rs:32 2x2 at 174976
>level 8, face 0: rs:32 1x1 at 175040
>r300TexParameter( GL_TEXTURE_MIN_FILTER )
>r300TexParameter( GL_TEXTURE_WRAP_S )
>r300TexParameter( GL_TEXTURE_WRAP_T )
>r300NewTextureObject( 0xca63a50 (target = GL_FALSE) )
>level 0, face 0: rs:512 256x256 at 0
>level 1, face 0: rs:256 128x128 at 131072
>level 2, face 0: rs:128 64x64 at 163840
>level 3, face 0: rs:64 32x32 at 172032
>level 4, face 0: rs:32 16x16 at 174080
>level 5, face 0: rs:32 8x8 at 174592
>level 6, face 0: rs:32 4x4 at 174848
>level 7, face 0: rs:32 2x2 at 174976
>level 8, face 0: rs:32 1x1 at 175040
>r300TexParameter( GL_TEXTURE_MIN_FILTER )
>r300TexParameter( GL_TEXTURE_WRAP_S )
>r300TexParameter( GL_TEXTURE_WRAP_T )
>r300NewTextureObject( 0xca64b28 (target = GL_FALSE) )
>level 0, face 0: rs:512 256x256 at 0
>level 1, face 0: rs:256 128x128 at 131072
>level 2, face 0: rs:128 64x64 at 163840
>level 3, face 0: rs:64 32x32 at 172032
>level 4, face 0: rs:32 16x16 at 174080
>level 5, face 0: rs:32 8x8 at 174592
>level 6, face 0: rs:32 4x4 at 174848
>level 7, face 0: rs:32 2x2 at 174976
>level 8, face 0: rs:32 1x1 at 175040
>r300TexParameter( GL_TEXTURE_MIN_FILTER )
>r300TexParameter( GL_TEXTURE_WRAP_S )
>r300TexParameter( GL_TEXTURE_WRAP_T )
>r300NewTextureObject( 0xca65c00 (target = GL_FALSE) )
>level 0, face 0: rs:512 256x256 at 0
>level 1, face 0: rs:256 128x128 at 131072
>level 2, face 0: rs:128 64x64 at 163840
>level 3, face 0: rs:64 32x32 at 172032
>level 4, face 0: rs:32 16x16 at 174080
>level 5, face 0: rs:32 8x8 at 174592
>level 6, face 0: rs:32 4x4 at 174848
>level 7, face 0: rs:32 2x2 at 174976
>level 8, face 0: rs:32 1x1 at 175040
>r300TexParameter( GL_TEXTURE_MIN_FILTER )
>r300TexParameter( GL_TEXTURE_WRAP_S )
>r300TexParameter( GL_TEXTURE_WRAP_T )
>r300Enable( GL_DEPTH_TEST = GL_TRUE )
>r300Enable( GL_STENCIL_TEST = GL_FALSE )
>r300Enable( GL_TEXTURE_2D = GL_FALSE )
>radeonDrawBuffer GL_BACK
>r300Enable( GL_DEPTH_TEST = GL_TRUE )
>r300Enable( GL_STENCIL_TEST = GL_FALSE )
>r300Clear
>Reemit state after flush (from r300EmitClearState)
>radeonEmitState
>Begin reemit state
>BEGIN_BATCH(1) at 0, from cp_wait:185
>BEGIN_BATCH(2) at 1, from r300_vtbl_pre_emit_atoms:234
>BEGIN_BATCH(1) at 3, from end_3d:162
>Begin dirty state
>BEGIN_BATCH(1) at 4, from cp_wait:185
>BEGIN_BATCH(2) at 5, from r300_vtbl_pre_emit_atoms:234
>BEGIN_BATCH(1) at 7, from end_3d:162
>  emit vpt 7/7
>      vpt[0]: cmdpacket0 (first reg=0x1d98, count=6)
>      vpt[1]: 0x1d98 = 43a00000
>      vpt[2]: 0x1d9c = 43a00000
>      vpt[3]: 0x1da0 = c3700000
>      vpt[4]: 0x1da4 = 43700000
>      vpt[5]: 0x1da8 = 3f000000
>      vpt[6]: 0x1dac = 3f000000
>BEGIN_BATCH(7) at 8, from radeonEmitAtoms:996
>  emit vap_cntl 4/4
>      vap_cntl[0]: cmdpacket0 (first reg=0x2284, count=1)
>      vap_cntl[1]: 0x2284 = 00000000
>      vap_cntl[2]: cmdpacket0 (first reg=0x2080, count=1)
>      vap_cntl[3]: 0x2080 = 00b0056a
>BEGIN_BATCH(4) at 15, from radeonEmitAtoms:996
>  emit vap_index_offset 2/2
>      vap_index_offset[0]: cmdpacket0 (first reg=0x208c, count=1)
>      vap_index_offset[1]: 0x208c = 00000000
>BEGIN_BATCH(2) at 19, from radeonEmitAtoms:996
>  emit vte 3/3
>      vte[0]: cmdpacket0 (first reg=0x20b0, count=2)
>      vte[1]: 0x20b0 = 0000043f
>      vte[2]: 0x20b4 = 00000008
>BEGIN_BATCH(3) at 21, from radeonEmitAtoms:996
>  emit vap_vf_max_vtx_indx 3/3
>      vap_vf_max_vtx_indx[0]: cmdpacket0 (first reg=0x2134, count=2)
>      vap_vf_max_vtx_indx[1]: 0x2134 = 00ffffff
>      vap_vf_max_vtx_indx[2]: 0x2138 = 00000000
>BEGIN_BATCH(3) at 24, from radeonEmitAtoms:996
>  emit vap_cntl_status 2/2
>      vap_cntl_status[0]: cmdpacket0 (first reg=0x2140, count=1)
>      vap_cntl_status[1]: 0x2140 = 00000000
>BEGIN_BATCH(2) at 27, from radeonEmitAtoms:996
>  emit vir[0] 2/9
>      vir[0][0]: cmdpacket0 (first reg=0x2150, count=1)
>      vir[0][1]: 0x2150 = 21010002
>BEGIN_BATCH(2) at 29, from radeonEmitAtoms:996
>  emit vir[1] 2/9
>      vir[1][0]: cmdpacket0 (first reg=0x21e0, count=1)
>      vir[1][1]: 0x21e0 = fb08fa88
>BEGIN_BATCH(2) at 31, from radeonEmitAtoms:996
>  emit vic 3/3
>      vic[0]: cmdpacket0 (first reg=0x2180, count=2)
>      vic[1]: 0x2180 = 00005555
>      vic[2]: 0x2184 = 00000401
>BEGIN_BATCH(3) at 33, from radeonEmitAtoms:996
>  emit vap_psc_sgn_norm_cntl 2/2
>      vap_psc_sgn_norm_cntl[0]: cmdpacket0 (first reg=0x21dc, count=1)
>      vap_psc_sgn_norm_cntl[1]: 0x21dc = aaaaaaaa
>BEGIN_BATCH(2) at 36, from radeonEmitAtoms:996
>  emit vap_clip_cntl 2/2
>      vap_clip_cntl[0]: cmdpacket0 (first reg=0x221c, count=1)
>      vap_clip_cntl[1]: 0x221c = 00000000
>BEGIN_BATCH(2) at 38, from radeonEmitAtoms:996
>  emit vap_clip 5/5
>      vap_clip[0]: cmdpacket0 (first reg=0x2220, count=4)
>      vap_clip[1]: 0x2220 = 3f800000
>      vap_clip[2]: 0x2224 = 3f800000
>      vap_clip[3]: 0x2228 = 3f800000
>      vap_clip[4]: 0x222c = 3f800000
>BEGIN_BATCH(5) at 40, from radeonEmitAtoms:996
>  emit vap_pvs_vtx_timeout_reg 2/2
>      vap_pvs_vtx_timeout_reg[0]: cmdpacket0 (first reg=0x2288, count=1)
>      vap_pvs_vtx_timeout_reg[1]: 0x2288 = 0000ffff
>BEGIN_BATCH(2) at 45, from radeonEmitAtoms:996
>  emit vof 3/3
>      vof[0]: cmdpacket0 (first reg=0x2090, count=2)
>      vof[1]: 0x2090 = 00000001
>      vof[2]: 0x2094 = 00000004
>BEGIN_BATCH(3) at 47, from radeonEmitAtoms:996
>  emit pvs 4/4
>      pvs[0]: cmdpacket0 (first reg=0x22d0, count=3)
>      pvs[1]: 0x22d0 = 00401000
>      pvs[2]: 0x22d4 = 00040000
>      pvs[3]: 0x22d8 = 00000004
>BEGIN_BATCH(4) at 50, from radeonEmitAtoms:996
>  emit gb_enable 2/2
>      gb_enable[0]: cmdpacket0 (first reg=0x4008, count=1)
>      gb_enable[1]: 0x4008 = 00000007
>BEGIN_BATCH(2) at 54, from radeonEmitAtoms:996
>  emit gb_misc 4/4
>      gb_misc[0]: cmdpacket0 (first reg=0x4010, count=3)
>      gb_misc[1]: 0x4010 = 66666666
>      gb_misc[2]: 0x4014 = 06666666
>      gb_misc[3]: 0x4018 = 00000011
>BEGIN_BATCH(4) at 56, from emit_gb_misc:382
>  emit gb_misc2 3/3
>      gb_misc2[0]: cmdpacket0 (first reg=0x401c, count=2)
>      gb_misc2[1]: 0x401c = 00000000
>      gb_misc2[2]: 0x4020 = 00000000
>BEGIN_BATCH(3) at 60, from radeonEmitAtoms:996
>  emit txe 2/2
>      txe[0]: cmdpacket0 (first reg=0x4104, count=1)
>      txe[1]: 0x4104 = 00000001
>BEGIN_BATCH(2) at 63, from radeonEmitAtoms:996
>  emit ga_point_s0 5/5
>      ga_point_s0[0]: cmdpacket0 (first reg=0x4200, count=4)
>      ga_point_s0[1]: 0x4200 = 00000000
>      ga_point_s0[2]: 0x4204 = 00000000
>      ga_point_s0[3]: 0x4208 = 3f800000
>      ga_point_s0[4]: 0x420c = 3f800000
>BEGIN_BATCH(5) at 65, from radeonEmitAtoms:996
>  emit ga_triangle_stipple 2/2
>      ga_triangle_stipple[0]: cmdpacket0 (first reg=0x4214, count=1)
>      ga_triangle_stipple[1]: 0x4214 = 00050005
>BEGIN_BATCH(2) at 70, from radeonEmitAtoms:996
>  emit ps 2/2
>      ps[0]: cmdpacket0 (first reg=0x421c, count=1)
>      ps[1]: 0x421c = 00060006
>BEGIN_BATCH(2) at 72, from radeonEmitAtoms:996
>  emit ga_point_minmax 4/4
>      ga_point_minmax[0]: cmdpacket0 (first reg=0x4230, count=3)
>      ga_point_minmax[1]: 0x4230 = 18000006
>      ga_point_minmax[2]: 0x4234 = 00020006
>      ga_point_minmax[3]: 0x4238 = 3baaaaab
>BEGIN_BATCH(4) at 74, from radeonEmitAtoms:996
>  emit lcntl 2/2
>      lcntl[0]: cmdpacket0 (first reg=0x4234, count=1)
>      lcntl[1]: 0x4234 = 00030006
>BEGIN_BATCH(2) at 78, from radeonEmitAtoms:996
>  emit ga_line_stipple 4/4
>      ga_line_stipple[0]: cmdpacket0 (first reg=0x4260, count=3)
>      ga_line_stipple[1]: 0x4260 = 00000000
>      ga_line_stipple[2]: 0x4264 = 00000000
>      ga_line_stipple[3]: 0x4268 = 3f800000
>BEGIN_BATCH(4) at 80, from radeonEmitAtoms:996
>  emit shade 2/2
>      shade[0]: cmdpacket0 (first reg=0x4274, count=1)
>      shade[1]: 0x4274 = 00000002
>BEGIN_BATCH(2) at 84, from emit_shade_misc:410
>  emit shade2 4/4
>      shade2[0]: cmdpacket0 (first reg=0x4278, count=3)
>      shade2[1]: 0x4278 = 0003aaaa
>      shade2[2]: 0x427c = 00000000
>      shade2[3]: 0x4280 = 00000000
>BEGIN_BATCH(4) at 86, from radeonEmitAtoms:996
>  emit polygon_mode 4/4
>      polygon_mode[0]: cmdpacket0 (first reg=0x4288, count=3)
>      polygon_mode[1]: 0x4288 = 00000000
>      polygon_mode[2]: 0x428c = 00000001
>      polygon_mode[3]: 0x4290 = 00000000
>BEGIN_BATCH(4) at 90, from radeonEmitAtoms:996
>  emit fogp 3/3
>      fogp[0]: cmdpacket0 (first reg=0x4294, count=2)
>      fogp[1]: 0x4294 = 00000000
>      fogp[2]: 0x4298 = 00000000
>BEGIN_BATCH(3) at 94, from radeonEmitAtoms:996
>  emit zbias_cntl 2/2
>      zbias_cntl[0]: cmdpacket0 (first reg=0x42a0, count=1)
>      zbias_cntl[1]: 0x42a0 = 00000000
>BEGIN_BATCH(2) at 97, from radeonEmitAtoms:996
>  emit zbs 5/5
>      zbs[0]: cmdpacket0 (first reg=0x42a4, count=4)
>      zbs[1]: 0x42a4 = 00000000
>      zbs[2]: 0x42a8 = 00000000
>      zbs[3]: 0x42ac = 00000000
>      zbs[4]: 0x42b0 = 00000000
>BEGIN_BATCH(5) at 99, from radeonEmitAtoms:996
>  emit occlusion_cntl 2/2
>      occlusion_cntl[0]: cmdpacket0 (first reg=0x42b4, count=1)
>      occlusion_cntl[1]: 0x42b4 = 00000000
>BEGIN_BATCH(2) at 104, from radeonEmitAtoms:996
>  emit cul 2/2
>      cul[0]: cmdpacket0 (first reg=0x42b8, count=1)
>      cul[1]: 0x42b8 = 00000003
>BEGIN_BATCH(2) at 106, from radeonEmitAtoms:996
>  emit su_depth_scale 3/3
>      su_depth_scale[0]: cmdpacket0 (first reg=0x42c0, count=2)
>      su_depth_scale[1]: 0x42c0 = 4b7fffff
>      su_depth_scale[2]: 0x42c4 = 00000000
>BEGIN_BATCH(3) at 108, from radeonEmitAtoms:996
>  emit rc 3/3
>      rc[0]: cmdpacket0 (first reg=0x4300, count=2)
>      rc[1]: 0x4300 = 00040004
>      rc[2]: 0x4304 = 000000c0
>BEGIN_BATCH(3) at 111, from radeonEmitAtoms:996
>  emit ri 2/17
>      ri[0]: cmdpacket0 (first reg=0x4074, count=1)
>      ri[1]: 0x4074 = 000c2040
>BEGIN_BATCH(2) at 114, from radeonEmitAtoms:996
>  emit rr 2/9
>      rr[0]: cmdpacket0 (first reg=0x4320, count=1)
>      rr[1]: 0x4320 = 00000010
>BEGIN_BATCH(2) at 116, from radeonEmitAtoms:996
>  emit sc_hyperz 3/3
>      sc_hyperz[0]: cmdpacket0 (first reg=0x43a4, count=2)
>      sc_hyperz[1]: 0x43a4 = 0000001c
>      sc_hyperz[2]: 0x43a8 = 2da49525
>BEGIN_BATCH(3) at 118, from radeonEmitAtoms:996
>  emit sc_screendoor 2/2
>      sc_screendoor[0]: cmdpacket0 (first reg=0x43e8, count=1)
>      sc_screendoor[1]: 0x43e8 = 00ffffff
>BEGIN_BATCH(2) at 121, from radeonEmitAtoms:996
>  emit us_out_fmt 6/6
>      us_out_fmt[0]: cmdpacket0 (first reg=0x46a4, count=5)
>      us_out_fmt[1]: 0x46a4 = 00001b00
>      us_out_fmt[2]: 0x46a8 = 00001b0f
>      us_out_fmt[3]: 0x46ac = 00001b0f
>      us_out_fmt[4]: 0x46b0 = 00001b0f
>      us_out_fmt[5]: 0x46b4 = 00000000
>BEGIN_BATCH(6) at 123, from radeonEmitAtoms:996
>  emit fp 9/9
>      fp[0]: cmdpacket0 (first reg=0x4600, count=2)
>      fp[1]: 0x4600 = 00000002
>      fp[2]: 0x4604 = 00000001
>      fp[3]: cmdpacket0 (first reg=0x4630, count=3)
>      fp[4]: 0x4630 = 00010000
>      fp[5]: 0x4634 = 00010000
>      fp[6]: 0x4638 = 00000000
>      fp[7]: cmdpacket0 (first reg=0x4624, count=1)
>      fp[8]: 0x4624 = 00000000
>BEGIN_BATCH(9) at 129, from radeonEmitAtoms:996
>  emit r500fp 13/3073
>      r500fp[0]: cmdpacket0 (first reg=0x0000, count=2)
>      r500fp[1]: 0x0000 = 00003807
>      r500fp[2]: 0x0004 = 06c00000
>      r500fp[3]: cmdpacket0 (first reg=0xe401, count=228)
>      r500fp[4]: 0xe401 = 00000000
>      r500fp[5]: 0xe405 = 00000000
>      r500fp[6]: 0xe409 = 00000000
>      r500fp[7]: 0xe40d = 00078005
>      r500fp[8]: 0xe411 = 00040001
>      r500fp[9]: 0xe415 = 00000100
>      r500fp[10]: 0xe419 = 00442220
>      r500fp[11]: 0xe41d = 00c0c000
>      r500fp[12]: 0xe421 = 20490000
>BEGIN_BATCH(13) at 138, from emit_r500fp:131
>  emit r500fp_const 5/1025
>      r500fp_const[0]: cmdpacket0 (first reg=0x0200, count=1)
>      r500fp_const[1]: 0x0200 = 3f800000
>      r500fp_const[2]: cmdpacket0 (first reg=0x3f80, count=0)
>      r500fp_const[3]: cmdpacket0 (first reg=0x3f80, count=0)
>      r500fp_const[4]: cmdpacket0 (first reg=0x3f80, count=0)
>BEGIN_BATCH(5) at 151, from emit_r500fp:131
>  emit fogs 2/2
>      fogs[0]: cmdpacket0 (first reg=0x4bc0, count=1)
>      fogs[1]: 0x4bc0 = 00000000
>BEGIN_BATCH(2) at 156, from radeonEmitAtoms:996
>  emit fogc 4/4
>      fogc[0]: cmdpacket0 (first reg=0x4bc8, count=3)
>      fogc[1]: 0x4bc8 = 00000000
>      fogc[2]: 0x4bcc = 00000000
>      fogc[3]: 0x4bd0 = 00000000
>BEGIN_BATCH(4) at 158, from radeonEmitAtoms:996
>  emit at 3/3
>      at[0]: cmdpacket0 (first reg=0x4bd4, count=2)
>      at[1]: 0x4bd4 = 00000000
>      at[2]: 0x4bd8 = 00000000
>BEGIN_BATCH(3) at 162, from radeonEmitAtoms:996
>  emit fg_depth_src 2/2
>      fg_depth_src[0]: cmdpacket0 (first reg=0x4bd8, count=1)
>      fg_depth_src[1]: 0x4bd8 = 00000000
>BEGIN_BATCH(2) at 165, from radeonEmitAtoms:996
>  emit rb3d_cctl 2/2
>      rb3d_cctl[0]: cmdpacket0 (first reg=0x4e00, count=1)
>      rb3d_cctl[1]: 0x4e00 = 00000000
>BEGIN_BATCH(2) at 167, from radeonEmitAtoms:996
>  emit bld 3/3
>      bld[0]: cmdpacket0 (first reg=0x4e04, count=2)
>      bld[1]: 0x4e04 = 20210007
>      bld[2]: 0x4e08 = 20210000
>BEGIN_BATCH(3) at 169, from radeonEmitAtoms:996
>  emit cmk 2/2
>      cmk[0]: cmdpacket0 (first reg=0x4e0c, count=1)
>      cmk[1]: 0x4e0c = 0000000f
>BEGIN_BATCH(2) at 172, from radeonEmitAtoms:996
>  emit blend_color 3/3
>      blend_color[0]: cmdpacket0 (first reg=0x4ef8, count=2)
>      blend_color[1]: 0x4ef8 = 00000000
>      blend_color[2]: 0x4efc = 00000000
>BEGIN_BATCH(3) at 174, from radeonEmitAtoms:996
>  emit rop 2/2
>      rop[0]: cmdpacket0 (first reg=0x4e18, count=1)
>      rop[1]: 0x4e18 = 00000000
>BEGIN_BATCH(2) at 177, from radeonEmitAtoms:996
>  emit cb 4/4
>      cb[0]: cmdpacket0 (first reg=0x0000, count=0)
>      cb[1]: cmdpacket0 (first reg=0x0000, count=0)
>      cb[2]: cmdpacket0 (first reg=0x0000, count=0)
>      cb[3]: cmdpacket0 (first reg=0x0000, count=0)
>rrb is 0xc917e68 0 640x480
>BEGIN_BATCH(6) at 179, from emit_cb_offset:289
>  emit rb3d_dither_ctl 10/10
>      rb3d_dither_ctl[0]: cmdpacket0 (first reg=0x4e50, count=9)
>      rb3d_dither_ctl[1]: 0x4e50 = 00000000
>      rb3d_dither_ctl[2]: 0x4e54 = 00000000
>      rb3d_dither_ctl[3]: 0x4e58 = 00000000
>      rb3d_dither_ctl[4]: 0x4e5c = 00000000
>      rb3d_dither_ctl[5]: 0x4e60 = 00000000
>      rb3d_dither_ctl[6]: 0x4e64 = 00000000
>      rb3d_dither_ctl[7]: 0x4e68 = 00000000
>      rb3d_dither_ctl[8]: 0x4e6c = 00000000
>      rb3d_dither_ctl[9]: 0x4e70 = 00000000
>BEGIN_BATCH(10) at 183, from radeonEmitAtoms:996
>  emit rb3d_aaresolve_ctl 2/2
>      rb3d_aaresolve_ctl[0]: cmdpacket0 (first reg=0x4e88, count=1)
>      rb3d_aaresolve_ctl[1]: 0x4e88 = 00000000
>BEGIN_BATCH(2) at 193, from radeonEmitAtoms:996
>  emit rb3d_discard_src_pixel_lte_threshold 3/3
>      rb3d_discard_src_pixel_lte_threshold[0]: cmdpacket0 (first reg=0x4ea0, count=2)
>      rb3d_discard_src_pixel_lte_threshold[1]: 0x4ea0 = 00000000
>      rb3d_discard_src_pixel_lte_threshold[2]: 0x4ea4 = ffffffff
>BEGIN_BATCH(3) at 195, from emit_threshold_misc:396
>  emit zs 4/4
>      zs[0]: cmdpacket0 (first reg=0x4f00, count=3)
>      zs[1]: 0x4f00 = 00000016
>      zs[2]: 0x4f04 = 0003803f
>      zs[3]: 0x4f08 = 00ffff80
>BEGIN_BATCH(4) at 198, from radeonEmitAtoms:996
>  emit zstencil_format 5/5
>      zstencil_format[0]: cmdpacket0 (first reg=0x4f10, count=4)
>      zstencil_format[1]: 0x4f10 = 00000002
>      zstencil_format[2]: 0x4f14 = 00000001
>      zstencil_format[3]: 0x4f18 = 00000003
>      zstencil_format[4]: 0x4f1c = 00000000
>  emit zb 3/3
>      zb[0]: cmdpacket0 (first reg=0x0000, count=0)
>      zb[1]: cmdpacket0 (first reg=0x0000, count=0)
>      zb[2]: cmdpacket0 (first reg=0x0000, count=0)
>BEGIN_BATCH(6) at 207, from emit_zb_offset:366
>  emit zb_depthclearvalue 2/2
>      zb_depthclearvalue[0]: cmdpacket0 (first reg=0x4f28, count=1)
>      zb_depthclearvalue[1]: 0x4f28 = 00000000
>BEGIN_BATCH(2) at 211, from radeonEmitAtoms:996
>  emit zb_zmask 3/3
>      zb_zmask[0]: cmdpacket0 (first reg=0x4f30, count=2)
>      zb_zmask[1]: 0x4f30 = 00000000
>      zb_zmask[2]: 0x4f34 = 00000000
>BEGIN_BATCH(3) at 213, from radeonEmitAtoms:996
>  emit zb_hiz_offset 2/2
>      zb_hiz_offset[0]: cmdpacket0 (first reg=0x4f44, count=1)
>      zb_hiz_offset[1]: 0x4f44 = 00000000
>BEGIN_BATCH(2) at 216, from radeonEmitAtoms:996
>  emit zb_hiz_pitch 2/2
>      zb_hiz_pitch[0]: cmdpacket0 (first reg=0x4f54, count=1)
>      zb_hiz_pitch[1]: 0x4f54 = 00000000
>BEGIN_BATCH(2) at 218, from radeonEmitAtoms:996
>  emit vpi 21/1025
>      vpi[0]: cmdpacket0 (first reg=0x0000, count=5)
>      vpi[1]: 0x0000 = 00100201
>      vpi[2]: 0x0004 = 00d10001
>      vpi[3]: 0x0008 = 00d10002
>      vpi[4]: 0x000c = 01248002
>      vpi[5]: 0x0010 = 00200201
>      vpi[6]: cmdpacket0 (first reg=0x00d1, count=0)
>      vpi[7]: cmdpacket0 (first reg=0x00d1, count=0)
>      vpi[8]: cmdpacket0 (first reg=0x0124, count=128)
>      vpi[9]: 0x0124 = 00400201
>      vpi[10]: 0x0128 = 00d10001
>      vpi[11]: 0x012c = 00d10042
>      vpi[12]: 0x0130 = 01248042
>      vpi[13]: 0x0134 = 00800201
>      vpi[14]: 0x0138 = 00d10001
>      vpi[15]: 0x013c = 00d10062
>      vpi[16]: 0x0140 = 01248062
>      vpi[17]: 0x0144 = 00f02203
>      vpi[18]: 0x0148 = 00d10021
>      vpi[19]: 0x014c = 01248021
>      vpi[20]: 0x0150 = 01248021
>BEGIN_BATCH(21) at 220, from emit_vpu:86
>  emit vpp 17/1025
>      vpp[0]: cmdpacket0 (first reg=0x0400, count=4)
>      vpp[1]: 0x0400 = 3b4ccccd
>      vpp[2]: 0x0404 = 00000000
>      vpp[3]: 0x0408 = 00000000
>      vpp[4]: 0x040c = bf800000
>      vpp[5]: cmdpacket0 (first reg=0x0000, count=0)
>      vpp[6]: cmdpacket0 (first reg=0xbb88, count=136)
>      vpp[7]: 0xbb88 = 00000000
>      vpp[8]: 0xbb8c = 3f800000
>      vpp[9]: 0xbb90 = 00000000
>      vpp[10]: 0xbb94 = 00000000
>      vpp[11]: 0xbb98 = c0000000
>      vpp[12]: 0xbb9c = bf800000
>      vpp[13]: 0xbba0 = 00000000
>      vpp[14]: 0xbba4 = 00000000
>      vpp[15]: 0xbba8 = 00000000
>      vpp[16]: 0xbbac = 3f800000
>BEGIN_BATCH(17) at 241, from emit_vpu:86
>  skip state vps
>  emit vpucp[i] 5/5
>      vpucp[i][0]: cmdpacket0 (first reg=0x0600, count=1)
>      vpucp[i][1]: 0x0600 = 00000000
>      vpucp[i][2]: cmdpacket0 (first reg=0x0000, count=0)
>      vpucp[i][3]: cmdpacket0 (first reg=0x0000, count=0)
>      vpucp[i][4]: cmdpacket0 (first reg=0x0000, count=0)
>BEGIN_BATCH(5) at 258, from emit_vpu:86
>  emit vpucp[i] 5/5
>      vpucp[i][0]: cmdpacket0 (first reg=0x0601, count=1)
>      vpucp[i][1]: 0x0601 = 00000000
>      vpucp[i][2]: cmdpacket0 (first reg=0x0000, count=0)
>      vpucp[i][3]: cmdpacket0 (first reg=0x0000, count=0)
>      vpucp[i][4]: cmdpacket0 (first reg=0x0000, count=0)
>BEGIN_BATCH(5) at 263, from emit_vpu:86
>  emit vpucp[i] 5/5
>      vpucp[i][0]: cmdpacket0 (first reg=0x0602, count=1)
>      vpucp[i][1]: 0x0602 = 00000000
>      vpucp[i][2]: cmdpacket0 (first reg=0x0000, count=0)
>      vpucp[i][3]: cmdpacket0 (first reg=0x0000, count=0)
>      vpucp[i][4]: cmdpacket0 (first reg=0x0000, count=0)
>BEGIN_BATCH(5) at 268, from emit_vpu:86
>  emit vpucp[i] 5/5
>      vpucp[i][0]: cmdpacket0 (first reg=0x0603, count=1)
>      vpucp[i][1]: 0x0603 = 00000000
>      vpucp[i][2]: cmdpacket0 (first reg=0x0000, count=0)
>      vpucp[i][3]: cmdpacket0 (first reg=0x0000, count=0)
>      vpucp[i][4]: cmdpacket0 (first reg=0x0000, count=0)
>BEGIN_BATCH(5) at 273, from emit_vpu:86
>  emit vpucp[i] 5/5
>      vpucp[i][0]: cmdpacket0 (first reg=0x0604, count=1)
>      vpucp[i][1]: 0x0604 = 00000000
>      vpucp[i][2]: cmdpacket0 (first reg=0x0000, count=0)
>      vpucp[i][3]: cmdpacket0 (first reg=0x0000, count=0)
>      vpucp[i][4]: cmdpacket0 (first reg=0x0000, count=0)
>BEGIN_BATCH(5) at 278, from emit_vpu:86
>  emit vpucp[i] 5/5
>      vpucp[i][0]: cmdpacket0 (first reg=0x0605, count=1)
>      vpucp[i][1]: 0x0605 = 00000000
>      vpucp[i][2]: cmdpacket0 (first reg=0x0000, count=0)
>      vpucp[i][3]: cmdpacket0 (first reg=0x0000, count=0)
>      vpucp[i][4]: cmdpacket0 (first reg=0x0000, count=0)
>BEGIN_BATCH(5) at 283, from emit_vpu:86
>  emit tex.filter 2/9
>      tex.filter[0]: cmdpacket0 (first reg=0x4400, count=1)
>      tex.filter[1]: 0x4400 = 00001400
>BEGIN_BATCH(2) at 288, from radeonEmitAtoms:996
>  emit tex.filter_1 2/9
>      tex.filter_1[0]: cmdpacket0 (first reg=0x4440, count=1)
>      tex.filter_1[1]: 0x4440 = 00000000
>BEGIN_BATCH(2) at 290, from radeonEmitAtoms:996
>  emit tex.size 2/9
>      tex.size[0]: cmdpacket0 (first reg=0x4480, count=1)
>      tex.size[1]: 0x4480 = 001ffbff
>BEGIN_BATCH(2) at 292, from radeonEmitAtoms:996
>  emit tex.format 2/9
>      tex.format[0]: cmdpacket0 (first reg=0x44c0, count=1)
>      tex.format[1]: 0x44c0 = 0000aa06
>BEGIN_BATCH(2) at 294, from radeonEmitAtoms:996
>  emit tex.pitch 2/9
>      tex.pitch[0]: cmdpacket0 (first reg=0x4500, count=1)
>      tex.pitch[1]: 0x4500 = 00000000
>BEGIN_BATCH(2) at 296, from radeonEmitAtoms:996
>  emit tex.offset 2/1
>      tex.offset[0]: cmdpacket0 (first reg=0x4540, count=1)
>      tex.offset[1]: 0x4540 = 00000000
>BEGIN_BATCH(4) at 298, from emit_tex_offsets:185
>  emit tex.chroma_key 2/9
>      tex.chroma_key[0]: cmdpacket0 (first reg=0x4580, count=1)
>      tex.chroma_key[1]: 0x4580 = 00000000
>BEGIN_BATCH(2) at 300, from radeonEmitAtoms:996
>  emit tex.border_color 2/9
>      tex.border_color[0]: cmdpacket0 (first reg=0x45c0, count=1)
>      tex.border_color[1]: 0x45c0 = 00000000
>BEGIN_BATCH(2) at 302, from radeonEmitAtoms:996
>BEGIN_BATCH(31) at 304, from r300EmitClearState:238
>BEGIN_BATCH(2) at 335, from r300EmitClearState:314
>BEGIN_BATCH(2) at 337, from r300EmitClearState:319
>BEGIN_BATCH(14) at 339, from r300EmitClearState:346
>BEGIN_BATCH(7) at 353, from r300EmitClearState:397
>BEGIN_BATCH(7) at 360, from emit_r500fp:131
>BEGIN_BATCH(2) at 367, from r300EmitClearState:450
>BEGIN_BATCH(2) at 369, from r300EmitClearState:483
>BEGIN_BATCH(4) at 371, from r300EmitClearState:493
>BEGIN_BATCH(9) at 375, from emit_vpu:86
>r300ClearBuffer: buffer 0xc917e68 (0,0 640x480)
>BEGIN_BATCH(1) at 384, from cp_wait:185
>BEGIN_BATCH(1) at 385, from end_3d:162
>BEGIN_BATCH(6) at 386, from r300ClearBuffer:104
>BEGIN_BATCH(6) at 390, from r300ClearBuffer:127
>BEGIN_BATCH(9) at 396, from r300ClearBuffer:174
>BEGIN_BATCH(4) at 405, from r300EmitCacheFlush:166
>BEGIN_BATCH(1) at 409, from cp_wait:185
>radeonDrawBuffer GL_BACK
>r300Enable( GL_DEPTH_TEST = GL_TRUE )
>r300Enable( GL_STENCIL_TEST = GL_FALSE )
>r300Clear
>BEGIN_BATCH(31) at 410, from r300EmitClearState:238
>BEGIN_BATCH(2) at 441, from r300EmitClearState:314
>BEGIN_BATCH(2) at 443, from r300EmitClearState:319
>BEGIN_BATCH(14) at 445, from r300EmitClearState:346
>BEGIN_BATCH(7) at 459, from r300EmitClearState:397
>BEGIN_BATCH(7) at 466, from emit_r500fp:131
>BEGIN_BATCH(2) at 473, from r300EmitClearState:450
>BEGIN_BATCH(2) at 475, from r300EmitClearState:483
>BEGIN_BATCH(4) at 477, from r300EmitClearState:493
>BEGIN_BATCH(9) at 481, from emit_vpu:86
>r300ClearBuffer: buffer 0xc917e68 (0,0 640x480)
>BEGIN_BATCH(1) at 490, from cp_wait:185
>BEGIN_BATCH(1) at 491, from end_3d:162
>BEGIN_BATCH(6) at 492, from r300ClearBuffer:104
>BEGIN_BATCH(6) at 496, from r300ClearBuffer:127
>BEGIN_BATCH(9) at 502, from r300ClearBuffer:174
>BEGIN_BATCH(4) at 511, from r300EmitCacheFlush:166
>BEGIN_BATCH(1) at 515, from cp_wait:185
>r300Enable( GL_DEPTH_TEST = GL_FALSE )
>r300Enable( GL_TEXTURE_COORD_ARRAY = GL_FALSE )
>r300Enable( GL_TEXTURE_COORD_ARRAY = GL_TRUE )
>r300Enable( GL_TEXTURE_2D = GL_TRUE )
>radeonAllocDmaRegion 48
>radeonRefillCurrentDmaRegion
>radeonEmitVec12 count 4 stride 60 out 0xa428e000 data 0x9e5fd008
>radeonAllocDmaRegion 32
>radeonEmitVec8 count 4 stride 60 out 0xa428e040 data 0x9e5fd014
>mtu=8
>Activating texture unit 0
>TX_ENABLE: 00000001  last_hw_tmu=0
>BEGIN_BATCH(4) at 516, from r300EmitCacheFlush:166
>radeonEmitState
>Begin dirty state
>BEGIN_BATCH(1) at 520, from cp_wait:185
>BEGIN_BATCH(2) at 521, from r300_vtbl_pre_emit_atoms:234
>BEGIN_BATCH(1) at 523, from end_3d:162
>  emit vpt 7/7
>      vpt[0]: cmdpacket0 (first reg=0x1d98, count=6)
>      vpt[1]: 0x1d98 = 43a00000
>      vpt[2]: 0x1d9c = 43a00000
>      vpt[3]: 0x1da0 = c3700000
>      vpt[4]: 0x1da4 = 43700000
>      vpt[5]: 0x1da8 = 3f000000
>      vpt[6]: 0x1dac = 3f000000
>BEGIN_BATCH(7) at 524, from radeonEmitAtoms:996
>  emit vap_cntl 4/4
>      vap_cntl[0]: cmdpacket0 (first reg=0x2284, count=1)
>      vap_cntl[1]: 0x2284 = 00000000
>      vap_cntl[2]: cmdpacket0 (first reg=0x2080, count=1)
>      vap_cntl[3]: 0x2080 = 00b0056a
>BEGIN_BATCH(4) at 531, from radeonEmitAtoms:996
>  emit vte 3/3
>      vte[0]: cmdpacket0 (first reg=0x20b0, count=2)
>      vte[1]: 0x20b0 = 0000043f
>      vte[2]: 0x20b4 = 00000008
>BEGIN_BATCH(3) at 535, from radeonEmitAtoms:996
>  emit vir[0] 2/9
>      vir[0][0]: cmdpacket0 (first reg=0x2150, count=1)
>      vir[0][1]: 0x2150 = 21010002
>BEGIN_BATCH(2) at 538, from radeonEmitAtoms:996
>  emit vir[1] 2/9
>      vir[1][0]: cmdpacket0 (first reg=0x21e0, count=1)
>      vir[1][1]: 0x21e0 = fb08fa88
>BEGIN_BATCH(2) at 540, from radeonEmitAtoms:996
>  emit vic 3/3
>      vic[0]: cmdpacket0 (first reg=0x2180, count=2)
>      vic[1]: 0x2180 = 00005555
>      vic[2]: 0x2184 = 00000401
>BEGIN_BATCH(3) at 542, from radeonEmitAtoms:996
>  emit vap_clip_cntl 2/2
>      vap_clip_cntl[0]: cmdpacket0 (first reg=0x221c, count=1)
>      vap_clip_cntl[1]: 0x221c = 00000000
>BEGIN_BATCH(2) at 545, from radeonEmitAtoms:996
>  emit vof 3/3
>      vof[0]: cmdpacket0 (first reg=0x2090, count=2)
>      vof[1]: 0x2090 = 00000001
>      vof[2]: 0x2094 = 00000004
>BEGIN_BATCH(3) at 547, from radeonEmitAtoms:996
>  emit pvs 4/4
>      pvs[0]: cmdpacket0 (first reg=0x22d0, count=3)
>      pvs[1]: 0x22d0 = 00401000
>      pvs[2]: 0x22d4 = 00040000
>      pvs[3]: 0x22d8 = 00000004
>BEGIN_BATCH(4) at 550, from radeonEmitAtoms:996
>  emit txe 2/2
>      txe[0]: cmdpacket0 (first reg=0x4104, count=1)
>      txe[1]: 0x4104 = 00000001
>BEGIN_BATCH(2) at 554, from radeonEmitAtoms:996
>  emit ps 2/2
>      ps[0]: cmdpacket0 (first reg=0x421c, count=1)
>      ps[1]: 0x421c = 00060006
>BEGIN_BATCH(2) at 556, from radeonEmitAtoms:996
>  emit cul 2/2
>      cul[0]: cmdpacket0 (first reg=0x42b8, count=1)
>      cul[1]: 0x42b8 = 00000001
>BEGIN_BATCH(2) at 558, from radeonEmitAtoms:996
>  emit rc 3/3
>      rc[0]: cmdpacket0 (first reg=0x4300, count=2)
>      rc[1]: 0x4300 = 00040004
>      rc[2]: 0x4304 = 000000c0
>BEGIN_BATCH(3) at 560, from radeonEmitAtoms:996
>  emit ri 2/17
>      ri[0]: cmdpacket0 (first reg=0x4074, count=1)
>      ri[1]: 0x4074 = 000c2040
>BEGIN_BATCH(2) at 563, from radeonEmitAtoms:996
>  emit rr 2/9
>      rr[0]: cmdpacket0 (first reg=0x4320, count=1)
>      rr[1]: 0x4320 = 00000010
>BEGIN_BATCH(2) at 565, from radeonEmitAtoms:996
>  emit fp 9/9
>      fp[0]: cmdpacket0 (first reg=0x4600, count=2)
>      fp[1]: 0x4600 = 00000002
>      fp[2]: 0x4604 = 00000001
>      fp[3]: cmdpacket0 (first reg=0x4630, count=3)
>      fp[4]: 0x4630 = 00010000
>      fp[5]: 0x4634 = 00010000
>      fp[6]: 0x4638 = 00000000
>      fp[7]: cmdpacket0 (first reg=0x4624, count=1)
>      fp[8]: 0x4624 = 00000000
>BEGIN_BATCH(9) at 567, from radeonEmitAtoms:996
>  emit r500fp 13/3073
>      r500fp[0]: cmdpacket0 (first reg=0x0000, count=2)
>      r500fp[1]: 0x0000 = 00003807
>      r500fp[2]: 0x0004 = 06c00000
>      r500fp[3]: cmdpacket0 (first reg=0xe401, count=228)
>      r500fp[4]: 0xe401 = 00000000
>      r500fp[5]: 0xe405 = 00000000
>      r500fp[6]: 0xe409 = 00000000
>      r500fp[7]: 0xe40d = 00078005
>      r500fp[8]: 0xe411 = 00040001
>      r500fp[9]: 0xe415 = 00000100
>      r500fp[10]: 0xe419 = 00442220
>      r500fp[11]: 0xe41d = 00c0c000
>      r500fp[12]: 0xe421 = 20490000
>BEGIN_BATCH(13) at 576, from emit_r500fp:131
>  emit r500fp_const 5/1025
>      r500fp_const[0]: cmdpacket0 (first reg=0x0200, count=1)
>      r500fp_const[1]: 0x0200 = 3f800000
>      r500fp_const[2]: cmdpacket0 (first reg=0x3f80, count=0)
>      r500fp_const[3]: cmdpacket0 (first reg=0x3f80, count=0)
>      r500fp_const[4]: cmdpacket0 (first reg=0x3f80, count=0)
>BEGIN_BATCH(5) at 589, from emit_r500fp:131
>  emit fogs 2/2
>      fogs[0]: cmdpacket0 (first reg=0x4bc0, count=1)
>      fogs[1]: 0x4bc0 = 00000000
>BEGIN_BATCH(2) at 594, from radeonEmitAtoms:996
>  emit at 3/3
>      at[0]: cmdpacket0 (first reg=0x4bd4, count=2)
>      at[1]: 0x4bd4 = 00000000
>      at[2]: 0x4bd8 = 00000000
>BEGIN_BATCH(3) at 596, from radeonEmitAtoms:996
>  emit bld 3/3
>      bld[0]: cmdpacket0 (first reg=0x4e04, count=2)
>      bld[1]: 0x4e04 = 20210007
>      bld[2]: 0x4e08 = 20210000
>BEGIN_BATCH(3) at 599, from radeonEmitAtoms:996
>  emit cmk 2/2
>      cmk[0]: cmdpacket0 (first reg=0x4e0c, count=1)
>      cmk[1]: 0x4e0c = 0000000f
>BEGIN_BATCH(2) at 602, from radeonEmitAtoms:996
>  emit cb 4/4
>      cb[0]: cmdpacket0 (first reg=0x0000, count=0)
>      cb[1]: cmdpacket0 (first reg=0x0000, count=0)
>      cb[2]: cmdpacket0 (first reg=0x0000, count=0)
>      cb[3]: cmdpacket0 (first reg=0x0000, count=0)
>rrb is 0xc917e68 0 640x480
>BEGIN_BATCH(6) at 604, from emit_cb_offset:289
>  emit zs 4/4
>      zs[0]: cmdpacket0 (first reg=0x4f00, count=3)
>      zs[1]: 0x4f00 = 00000010
>      zs[2]: 0x4f04 = 00038038
>      zs[3]: 0x4f08 = 00ffff80
>BEGIN_BATCH(4) at 608, from radeonEmitAtoms:996
>  emit vpi 21/1025
>      vpi[0]: cmdpacket0 (first reg=0x0000, count=5)
>      vpi[1]: 0x0000 = 00100201
>      vpi[2]: 0x0004 = 00d10001
>      vpi[3]: 0x0008 = 00d10002
>      vpi[4]: 0x000c = 01248002
>      vpi[5]: 0x0010 = 00200201
>      vpi[6]: cmdpacket0 (first reg=0x00d1, count=0)
>      vpi[7]: cmdpacket0 (first reg=0x00d1, count=0)
>      vpi[8]: cmdpacket0 (first reg=0x0124, count=128)
>      vpi[9]: 0x0124 = 00400201
>      vpi[10]: 0x0128 = 00d10001
>      vpi[11]: 0x012c = 00d10042
>      vpi[12]: 0x0130 = 01248042
>      vpi[13]: 0x0134 = 00800201
>      vpi[14]: 0x0138 = 00d10001
>      vpi[15]: 0x013c = 00d10062
>      vpi[16]: 0x0140 = 01248062
>      vpi[17]: 0x0144 = 00f02203
>      vpi[18]: 0x0148 = 00d10021
>      vpi[19]: 0x014c = 01248021
>      vpi[20]: 0x0150 = 01248021
>BEGIN_BATCH(21) at 612, from emit_vpu:86
>  emit vpp 17/1025
>      vpp[0]: cmdpacket0 (first reg=0x0400, count=4)
>      vpp[1]: 0x0400 = 3b4ccccd
>      vpp[2]: 0x0404 = 00000000
>      vpp[3]: 0x0408 = 00000000
>      vpp[4]: 0x040c = bf800000
>      vpp[5]: cmdpacket0 (first reg=0x0000, count=0)
>      vpp[6]: cmdpacket0 (first reg=0xbb88, count=136)
>      vpp[7]: 0xbb88 = 00000000
>      vpp[8]: 0xbb8c = 3f800000
>      vpp[9]: 0xbb90 = 00000000
>      vpp[10]: 0xbb94 = 00000000
>      vpp[11]: 0xbb98 = c0000000
>      vpp[12]: 0xbb9c = bf800000
>      vpp[13]: 0xbba0 = 00000000
>      vpp[14]: 0xbba4 = 00000000
>      vpp[15]: 0xbba8 = 00000000
>      vpp[16]: 0xbbac = 3f800000
>BEGIN_BATCH(17) at 633, from emit_vpu:86
>  emit tex.filter 2/9
>      tex.filter[0]: cmdpacket0 (first reg=0x4400, count=1)
>      tex.filter[1]: 0x4400 = 00001400
>BEGIN_BATCH(2) at 650, from radeonEmitAtoms:996
>  emit tex.filter_1 2/9
>      tex.filter_1[0]: cmdpacket0 (first reg=0x4440, count=1)
>      tex.filter_1[1]: 0x4440 = 00000000
>BEGIN_BATCH(2) at 652, from radeonEmitAtoms:996
>  emit tex.size 2/9
>      tex.size[0]: cmdpacket0 (first reg=0x4480, count=1)
>      tex.size[1]: 0x4480 = 001ffbff
>BEGIN_BATCH(2) at 654, from radeonEmitAtoms:996
>  emit tex.format 2/9
>      tex.format[0]: cmdpacket0 (first reg=0x44c0, count=1)
>      tex.format[1]: 0x44c0 = 0000aa06
>BEGIN_BATCH(2) at 656, from radeonEmitAtoms:996
>  emit tex.pitch 2/9
>      tex.pitch[0]: cmdpacket0 (first reg=0x4500, count=1)
>      tex.pitch[1]: 0x4500 = 00000000
>BEGIN_BATCH(2) at 658, from radeonEmitAtoms:996
>  emit tex.offset 2/1
>      tex.offset[0]: cmdpacket0 (first reg=0x4540, count=1)
>      tex.offset[1]: 0x4540 = 00000000
>BEGIN_BATCH(4) at 660, from emit_tex_offsets:185
>  emit tex.chroma_key 2/9
>      tex.chroma_key[0]: cmdpacket0 (first reg=0x4580, count=1)
>      tex.chroma_key[1]: 0x4580 = 00000000
>BEGIN_BATCH(2) at 662, from radeonEmitAtoms:996
>  emit tex.border_color 2/9
>      tex.border_color[0]: cmdpacket0 (first reg=0x45c0, count=1)
>      tex.border_color[1]: 0x45c0 = 00000000
>BEGIN_BATCH(2) at 664, from radeonEmitAtoms:996
>radeonAllocDmaRegion 24
>r300EmitAOS: nr=2, ofs=0x00000000
>BEGIN_BATCH(10) at 666, from r300EmitAOS:247
>BEGIN_BATCH(10) at 672, from r300FireEB:199
>BEGIN_BATCH(4) at 680, from r300EmitCacheFlush:166
>r300Enable( GL_STENCIL_TEST = GL_TRUE )
>radeonFlush 684
>radeonEmitState
>Begin dirty state
>BEGIN_BATCH(1) at 684, from cp_wait:185
>BEGIN_BATCH(2) at 685, from r300_vtbl_pre_emit_atoms:234
>BEGIN_BATCH(1) at 687, from end_3d:162
>  emit zs 4/4
>      zs[0]: cmdpacket0 (first reg=0x4f00, count=3)
>      zs[1]: 0x4f00 = 00000011
>      zs[2]: 0x4f04 = 00038038
>      zs[3]: 0x4f08 = 00ffff80
>BEGIN_BATCH(4) at 688, from radeonEmitAtoms:996
>radeonReleaseDmaRegion 0xd2c1938
>rcommonFlushCmdBufLocked from radeonFlush - 1 cliprects
>radeonFlush 0
>
>radeonCopyBuffer( 0xc5e53b8 )
>
>r300NewTextureObject( 0xd2f4338 (target = GL_FALSE) )
>level 0, face 0: rs:32 16x16 at 0
>level 1, face 0: rs:32 8x8 at 512
>level 2, face 0: rs:32 4x4 at 768
>level 3, face 0: rs:32 2x2 at 896
>level 4, face 0: rs:32 1x1 at 960
>r300TexParameter( GL_TEXTURE_MIN_FILTER )
>r300TexParameter( GL_TEXTURE_WRAP_S )
>r300TexParameter( GL_TEXTURE_WRAP_T )
>r300NewTextureObject( 0xd2f6220 (target = GL_FALSE) )
>level 0, face 0: rs:32 16x16 at 0
>level 1, face 0: rs:32 8x8 at 512
>level 2, face 0: rs:32 4x4 at 768
>level 3, face 0: rs:32 2x2 at 896
>level 4, face 0: rs:32 1x1 at 960
>r300TexParameter( GL_TEXTURE_MIN_FILTER )
>r300TexParameter( GL_TEXTURE_WRAP_S )
>r300TexParameter( GL_TEXTURE_WRAP_T )
>r300NewTextureObject( 0xd2f80d0 (target = GL_FALSE) )
>level 0, face 0: rs:32 16x16 at 0
>level 1, face 0: rs:32 8x8 at 512
>level 2, face 0: rs:32 4x4 at 768
>level 3, face 0: rs:32 2x2 at 896
>level 4, face 0: rs:32 1x1 at 960
>r300TexParameter( GL_TEXTURE_MIN_FILTER )
>r300TexParameter( GL_TEXTURE_WRAP_S )
>r300TexParameter( GL_TEXTURE_WRAP_T )
>r300NewTextureObject( 0xd2faab0 (target = GL_FALSE) )
>level 0, face 0: rs:256 128x128 at 0
>level 1, face 0: rs:128 64x64 at 32768
>level 2, face 0: rs:64 32x32 at 40960
>level 3, face 0: rs:32 16x16 at 43008
>level 4, face 0: rs:32 8x8 at 43520
>level 5, face 0: rs:32 4x4 at 43776
>level 6, face 0: rs:32 2x2 at 43904
>level 7, face 0: rs:32 1x1 at 43968
>r300TexParameter( GL_TEXTURE_MIN_FILTER )
>r300TexParameter( GL_TEXTURE_WRAP_S )
>r300TexParameter( GL_TEXTURE_WRAP_T )
>r300NewTextureObject( 0xd2fbb30 (target = GL_FALSE) )
>level 0, face 0: rs:128 64x64 at 0
>level 1, face 0: rs:64 32x32 at 8192
>level 2, face 0: rs:32 16x16 at 10240
>level 3, face 0: rs:32 8x8 at 10752
>level 4, face 0: rs:32 4x4 at 11008
>level 5, face 0: rs:32 2x2 at 11136
>level 6, face 0: rs:32 1x1 at 11200
>r300TexParameter( GL_TEXTURE_MIN_FILTER )
>r300TexParameter( GL_TEXTURE_WRAP_S )
>r300TexParameter( GL_TEXTURE_WRAP_T )
>r300NewTextureObject( 0xd44bb28 (target = GL_FALSE) )
>level 0, face 0: rs:32 16x16 at 0
>level 1, face 0: rs:32 8x8 at 512
>level 2, face 0: rs:32 4x4 at 768
>level 3, face 0: rs:32 2x2 at 896
>level 4, face 0: rs:32 1x1 at 960
>r300TexParameter( GL_TEXTURE_MIN_FILTER )
>r300NewTextureObject( 0xd451738 (target = GL_FALSE) )
>level 0, face 0: rs:32 16x16 at 0
>level 1, face 0: rs:32 8x8 at 512
>level 2, face 0: rs:32 4x4 at 768
>level 3, face 0: rs:32 2x2 at 896
>level 4, face 0: rs:32 1x1 at 960
>r300TexParameter( GL_TEXTURE_MIN_FILTER )
>r300NewTextureObject( 0xd5c54c0 (target = GL_FALSE) )
>level 0, face 0: rs:32 16x16 at 0
>level 1, face 0: rs:32 8x8 at 512
>level 2, face 0: rs:32 4x4 at 768
>level 3, face 0: rs:32 2x2 at 896
>level 4, face 0: rs:32 1x1 at 960
>r300TexParameter( GL_TEXTURE_MIN_FILTER )
>r300NewTextureObject( 0xd5c9208 (target = GL_FALSE) )
>level 0, face 0: rs:32 16x16 at 0
>level 1, face 0: rs:32 8x8 at 512
>level 2, face 0: rs:32 4x4 at 768
>level 3, face 0: rs:32 2x2 at 896
>level 4, face 0: rs:32 1x1 at 960
>r300TexParameter( GL_TEXTURE_MIN_FILTER )
>r300NewTextureObject( 0xd5d0e38 (target = GL_FALSE) )
>level 0, face 0: rs:32 16x16 at 0
>level 1, face 0: rs:32 8x8 at 512
>level 2, face 0: rs:32 4x4 at 768
>level 3, face 0: rs:32 2x2 at 896
>level 4, face 0: rs:32 1x1 at 960
>r300TexParameter( GL_TEXTURE_MIN_FILTER )
>r300NewTextureObject( 0xd5de638 (target = GL_FALSE) )
>level 0, face 0: rs:256 128x64 at 0
>level 1, face 0: rs:128 64x32 at 16384
>level 2, face 0: rs:64 32x16 at 20480
>level 3, face 0: rs:32 16x8 at 21504
>level 4, face 0: rs:32 8x4 at 21760
>level 5, face 0: rs:32 4x2 at 21888
>level 6, face 0: rs:32 2x1 at 21952
>level 7, face 0: rs:32 1x1 at 21984
>r300TexParameter( GL_TEXTURE_MIN_FILTER )
>r300TexParameter( GL_TEXTURE_WRAP_S )
>r300TexParameter( GL_TEXTURE_WRAP_T )
>r300NewTextureObject( 0xd5df328 (target = GL_FALSE) )
>level 0, face 0: rs:256 128x64 at 0
>level 1, face 0: rs:128 64x32 at 16384
>level 2, face 0: rs:64 32x16 at 20480
>level 3, face 0: rs:32 16x8 at 21504
>level 4, face 0: rs:32 8x4 at 21760
>level 5, face 0: rs:32 4x2 at 21888
>level 6, face 0: rs:32 2x1 at 21952
>level 7, face 0: rs:32 1x1 at 21984
>r300TexParameter( GL_TEXTURE_MIN_FILTER )
>r300TexParameter( GL_TEXTURE_WRAP_S )
>r300TexParameter( GL_TEXTURE_WRAP_T )
>r300NewTextureObject( 0xd5d7d00 (target = GL_FALSE) )
>level 0, face 0: rs:32 16x16 at 0
>level 1, face 0: rs:32 8x8 at 512
>level 2, face 0: rs:32 4x4 at 768
>level 3, face 0: rs:32 2x2 at 896
>level 4, face 0: rs:32 1x1 at 960
>r300TexParameter( GL_TEXTURE_MIN_FILTER )
>r300NewTextureObject( 0xd5dacf0 (target = GL_FALSE) )
>level 0, face 0: rs:32 16x16 at 0
>level 1, face 0: rs:32 8x8 at 512
>level 2, face 0: rs:32 4x4 at 768
>level 3, face 0: rs:32 2x2 at 896
>level 4, face 0: rs:32 1x1 at 960
>r300TexParameter( GL_TEXTURE_MIN_FILTER )
>r300NewTextureObject( 0xd5dd570 (target = GL_FALSE) )
>level 0, face 0: rs:32 16x16 at 0
>level 1, face 0: rs:32 8x8 at 512
>level 2, face 0: rs:32 4x4 at 768
>level 3, face 0: rs:32 2x2 at 896
>level 4, face 0: rs:32 1x1 at 960
>r300TexParameter( GL_TEXTURE_MIN_FILTER )
>r300NewTextureObject( 0xd3eb988 (target = GL_FALSE) )
>level 0, face 0: rs:32 16x16 at 0
>level 1, face 0: rs:32 8x8 at 512
>level 2, face 0: rs:32 4x4 at 768
>level 3, face 0: rs:32 2x2 at 896
>level 4, face 0: rs:32 1x1 at 960
>r300TexParameter( GL_TEXTURE_MIN_FILTER )
>r300NewTextureObject( 0xd3ee930 (target = GL_FALSE) )
>level 0, face 0: rs:256 128x128 at 0
>level 1, face 0: rs:128 64x64 at 32768
>level 2, face 0: rs:64 32x32 at 40960
>level 3, face 0: rs:32 16x16 at 43008
>level 4, face 0: rs:32 8x8 at 43520
>level 5, face 0: rs:32 4x4 at 43776
>level 6, face 0: rs:32 2x2 at 43904
>level 7, face 0: rs:32 1x1 at 43968
>r300TexParameter( GL_TEXTURE_MIN_FILTER )
>r300TexParameter( GL_TEXTURE_WRAP_S )
>r300TexParameter( GL_TEXTURE_WRAP_T )
>r300NewTextureObject( 0xd6027d8 (target = GL_FALSE) )
>level 0, face 0: rs:256 128x128 at 0
>level 1, face 0: rs:128 64x64 at 32768
>level 2, face 0: rs:64 32x32 at 40960
>level 3, face 0: rs:32 16x16 at 43008
>level 4, face 0: rs:32 8x8 at 43520
>level 5, face 0: rs:32 4x4 at 43776
>level 6, face 0: rs:32 2x2 at 43904
>level 7, face 0: rs:32 1x1 at 43968
>r300TexParameter( GL_TEXTURE_MIN_FILTER )
>r300TexParameter( GL_TEXTURE_WRAP_S )
>r300TexParameter( GL_TEXTURE_WRAP_T )
>r300NewTextureObject( 0xd610670 (target = GL_FALSE) )
>level 0, face 0: rs:32 16x32 at 0
>level 1, face 0: rs:32 8x16 at 1024
>level 2, face 0: rs:32 4x8 at 1536
>level 3, face 0: rs:32 2x4 at 1792
>level 4, face 0: rs:32 1x2 at 1920
>level 5, face 0: rs:32 1x1 at 1984
>r300TexParameter( GL_TEXTURE_MIN_FILTER )
>r300TexParameter( GL_TEXTURE_WRAP_S )
>r300TexParameter( GL_TEXTURE_WRAP_T )
>r300NewTextureObject( 0xd5facb0 (target = GL_FALSE) )
>level 0, face 0: rs:512 256x32 at 0
>level 1, face 0: rs:256 128x16 at 16384
>level 2, face 0: rs:128 64x8 at 20480
>level 3, face 0: rs:64 32x4 at 21504
>level 4, face 0: rs:32 16x2 at 21760
>level 5, face 0: rs:32 8x1 at 21824
>level 6, face 0: rs:32 4x1 at 21856
>level 7, face 0: rs:32 2x1 at 21888
>level 8, face 0: rs:32 1x1 at 21920
>r300TexParameter( GL_TEXTURE_MIN_FILTER )
>r300TexParameter( GL_TEXTURE_WRAP_S )
>r300TexParameter( GL_TEXTURE_WRAP_T )
>r300NewTextureObject( 0xd601b88 (target = GL_FALSE) )
>level 0, face 0: rs:128 64x128 at 0
>level 1, face 0: rs:64 32x64 at 16384
>level 2, face 0: rs:32 16x32 at 20480
>level 3, face 0: rs:32 8x16 at 21504
>level 4, face 0: rs:32 4x8 at 22016
>level 5, face 0: rs:32 2x4 at 22272
>level 6, face 0: rs:32 1x2 at 22400
>level 7, face 0: rs:32 1x1 at 22464
>r300TexParameter( GL_TEXTURE_MIN_FILTER )
>r300TexParameter( GL_TEXTURE_WRAP_S )
>r300TexParameter( GL_TEXTURE_WRAP_T )
>r300NewTextureObject( 0xd62f350 (target = GL_FALSE) )
>level 0, face 0: rs:128 64x64 at 0
>level 1, face 0: rs:64 32x32 at 8192
>level 2, face 0: rs:32 16x16 at 10240
>level 3, face 0: rs:32 8x8 at 10752
>level 4, face 0: rs:32 4x4 at 11008
>level 5, face 0: rs:32 2x2 at 11136
>level 6, face 0: rs:32 1x1 at 11200
>r300TexParameter( GL_TEXTURE_MIN_FILTER )
>r300TexParameter( GL_TEXTURE_WRAP_S )
>r300TexParameter( GL_TEXTURE_WRAP_T )
>r300NewTextureObject( 0xd6345f8 (target = GL_FALSE) )
>level 0, face 0: rs:32 16x32 at 0
>level 1, face 0: rs:32 8x16 at 1024
>level 2, face 0: rs:32 4x8 at 1536
>level 3, face 0: rs:32 2x4 at 1792
>level 4, face 0: rs:32 1x2 at 1920
>level 5, face 0: rs:32 1x1 at 1984
>r300TexParameter( GL_TEXTURE_MIN_FILTER )
>r300TexParameter( GL_TEXTURE_WRAP_S )
>r300TexParameter( GL_TEXTURE_WRAP_T )
>r300NewTextureObject( 0xd635080 (target = GL_FALSE) )
>level 0, face 0: rs:32 2x32 at 0
>level 1, face 0: rs:32 1x16 at 1024
>level 2, face 0: rs:32 1x8 at 1536
>level 3, face 0: rs:32 1x4 at 1792
>level 4, face 0: rs:32 1x2 at 1920
>level 5, face 0: rs:32 1x1 at 1984
>r300TexParameter( GL_TEXTURE_MIN_FILTER )
>r300TexParameter( GL_TEXTURE_WRAP_S )
>r300TexParameter( GL_TEXTURE_WRAP_T )
>r300NewTextureObject( 0xd63e4e8 (target = GL_FALSE) )
>level 0, face 0: rs:32 16x32 at 0
>level 1, face 0: rs:32 8x16 at 1024
>level 2, face 0: rs:32 4x8 at 1536
>level 3, face 0: rs:32 2x4 at 1792
>level 4, face 0: rs:32 1x2 at 1920
>level 5, face 0: rs:32 1x1 at 1984
>r300TexParameter( GL_TEXTURE_MIN_FILTER )
>r300TexParameter( GL_TEXTURE_WRAP_S )
>r300TexParameter( GL_TEXTURE_WRAP_T )
>r300NewTextureObject( 0xd6403d8 (target = GL_FALSE) )
>level 0, face 0: rs:32 2x32 at 0
>level 1, face 0: rs:32 1x16 at 1024
>level 2, face 0: rs:32 1x8 at 1536
>level 3, face 0: rs:32 1x4 at 1792
>level 4, face 0: rs:32 1x2 at 1920
>level 5, face 0: rs:32 1x1 at 1984
>r300TexParameter( GL_TEXTURE_MIN_FILTER )
>r300TexParameter( GL_TEXTURE_WRAP_S )
>r300TexParameter( GL_TEXTURE_WRAP_T )
>r300NewTextureObject( 0xd64cd18 (target = GL_FALSE) )
>level 0, face 0: rs:128 64x64 at 0
>level 1, face 0: rs:64 32x32 at 8192
>level 2, face 0: rs:32 16x16 at 10240
>level 3, face 0: rs:32 8x8 at 10752
>level 4, face 0: rs:32 4x4 at 11008
>level 5, face 0: rs:32 2x2 at 11136
>level 6, face 0: rs:32 1x1 at 11200
>r300TexParameter( GL_TEXTURE_MIN_FILTER )
>r300TexParameter( GL_TEXTURE_WRAP_S )
>r300TexParameter( GL_TEXTURE_WRAP_T )
>r300NewTextureObject( 0xd651e58 (target = GL_FALSE) )
>level 0, face 0: rs:32 16x32 at 0
>level 1, face 0: rs:32 8x16 at 1024
>level 2, face 0: rs:32 4x8 at 1536
>level 3, face 0: rs:32 2x4 at 1792
>level 4, face 0: rs:32 1x2 at 1920
>level 5, face 0: rs:32 1x1 at 1984
>r300TexParameter( GL_TEXTURE_MIN_FILTER )
>r300TexParameter( GL_TEXTURE_WRAP_S )
>r300TexParameter( GL_TEXTURE_WRAP_T )
>r300NewTextureObject( 0xd653db0 (target = GL_FALSE) )
>level 0, face 0: rs:32 2x32 at 0
>level 1, face 0: rs:32 1x16 at 1024
>level 2, face 0: rs:32 1x8 at 1536
>level 3, face 0: rs:32 1x4 at 1792
>level 4, face 0: rs:32 1x2 at 1920
>level 5, face 0: rs:32 1x1 at 1984
>r300TexParameter( GL_TEXTURE_MIN_FILTER )
>r300TexParameter( GL_TEXTURE_WRAP_S )
>r300TexParameter( GL_TEXTURE_WRAP_T )
>r300NewTextureObject( 0xd5ed258 (target = GL_FALSE) )
>level 0, face 0: rs:32 16x32 at 0
>level 1, face 0: rs:32 8x16 at 1024
>level 2, face 0: rs:32 4x8 at 1536
>level 3, face 0: rs:32 2x4 at 1792
>level 4, face 0: rs:32 1x2 at 1920
>level 5, face 0: rs:32 1x1 at 1984
>r300TexParameter( GL_TEXTURE_MIN_FILTER )
>r300TexParameter( GL_TEXTURE_WRAP_S )
>r300TexParameter( GL_TEXTURE_WRAP_T )
>r300NewTextureObject( 0xd5ef198 (target = GL_FALSE) )
>level 0, face 0: rs:32 2x32 at 0
>level 1, face 0: rs:32 1x16 at 1024
>level 2, face 0: rs:32 1x8 at 1536
>level 3, face 0: rs:32 1x4 at 1792
>level 4, face 0: rs:32 1x2 at 1920
>level 5, face 0: rs:32 1x1 at 1984
>r300TexParameter( GL_TEXTURE_MIN_FILTER )
>r300TexParameter( GL_TEXTURE_WRAP_S )
>r300TexParameter( GL_TEXTURE_WRAP_T )
>r300NewTextureObject( 0xd664598 (target = GL_FALSE) )
>level 0, face 0: rs:128 64x64 at 0
>level 1, face 0: rs:64 32x32 at 8192
>level 2, face 0: rs:32 16x16 at 10240
>level 3, face 0: rs:32 8x8 at 10752
>level 4, face 0: rs:32 4x4 at 11008
>level 5, face 0: rs:32 2x2 at 11136
>level 6, face 0: rs:32 1x1 at 11200
>r300TexParameter( GL_TEXTURE_MIN_FILTER )
>r300TexParameter( GL_TEXTURE_WRAP_S )
>r300TexParameter( GL_TEXTURE_WRAP_T )
>r300NewTextureObject( 0xd6696d8 (target = GL_FALSE) )
>level 0, face 0: rs:32 16x32 at 0
>level 1, face 0: rs:32 8x16 at 1024
>level 2, face 0: rs:32 4x8 at 1536
>level 3, face 0: rs:32 2x4 at 1792
>level 4, face 0: rs:32 1x2 at 1920
>level 5, face 0: rs:32 1x1 at 1984
>r300TexParameter( GL_TEXTURE_MIN_FILTER )
>r300TexParameter( GL_TEXTURE_WRAP_S )
>r300TexParameter( GL_TEXTURE_WRAP_T )
>r300NewTextureObject( 0xd66b630 (target = GL_FALSE) )
>level 0, face 0: rs:32 2x32 at 0
>level 1, face 0: rs:32 1x16 at 1024
>level 2, face 0: rs:32 1x8 at 1536
>level 3, face 0: rs:32 1x4 at 1792
>level 4, face 0: rs:32 1x2 at 1920
>level 5, face 0: rs:32 1x1 at 1984
>r300TexParameter( GL_TEXTURE_MIN_FILTER )
>r300TexParameter( GL_TEXTURE_WRAP_S )
>r300TexParameter( GL_TEXTURE_WRAP_T )
>r300NewTextureObject( 0xd66d5d8 (target = GL_FALSE) )
>level 0, face 0: rs:32 16x32 at 0
>level 1, face 0: rs:32 8x16 at 1024
>level 2, face 0: rs:32 4x8 at 1536
>level 3, face 0: rs:32 2x4 at 1792
>level 4, face 0: rs:32 1x2 at 1920
>level 5, face 0: rs:32 1x1 at 1984
>r300TexParameter( GL_TEXTURE_MIN_FILTER )
>r300TexParameter( GL_TEXTURE_WRAP_S )
>r300TexParameter( GL_TEXTURE_WRAP_T )
>r300NewTextureObject( 0xd66f4c8 (target = GL_FALSE) )
>level 0, face 0: rs:32 2x32 at 0
>level 1, face 0: rs:32 1x16 at 1024
>level 2, face 0: rs:32 1x8 at 1536
>level 3, face 0: rs:32 1x4 at 1792
>level 4, face 0: rs:32 1x2 at 1920
>level 5, face 0: rs:32 1x1 at 1984
>r300TexParameter( GL_TEXTURE_MIN_FILTER )
>r300TexParameter( GL_TEXTURE_WRAP_S )
>r300TexParameter( GL_TEXTURE_WRAP_T )
>r300NewTextureObject( 0xd67a6c8 (target = GL_FALSE) )
>level 0, face 0: rs:128 64x64 at 0
>level 1, face 0: rs:64 32x32 at 8192
>level 2, face 0: rs:32 16x16 at 10240
>level 3, face 0: rs:32 8x8 at 10752
>level 4, face 0: rs:32 4x4 at 11008
>level 5, face 0: rs:32 2x2 at 11136
>level 6, face 0: rs:32 1x1 at 11200
>r300TexParameter( GL_TEXTURE_MIN_FILTER )
>r300TexParameter( GL_TEXTURE_WRAP_S )
>r300TexParameter( GL_TEXTURE_WRAP_T )
>r300NewTextureObject( 0xd67f808 (target = GL_FALSE) )
>level 0, face 0: rs:32 16x32 at 0
>level 1, face 0: rs:32 8x16 at 1024
>level 2, face 0: rs:32 4x8 at 1536
>level 3, face 0: rs:32 2x4 at 1792
>level 4, face 0: rs:32 1x2 at 1920
>level 5, face 0: rs:32 1x1 at 1984
>r300TexParameter( GL_TEXTURE_MIN_FILTER )
>r300TexParameter( GL_TEXTURE_WRAP_S )
>r300TexParameter( GL_TEXTURE_WRAP_T )
>r300NewTextureObject( 0xd681760 (target = GL_FALSE) )
>level 0, face 0: rs:32 2x32 at 0
>level 1, face 0: rs:32 1x16 at 1024
>level 2, face 0: rs:32 1x8 at 1536
>level 3, face 0: rs:32 1x4 at 1792
>level 4, face 0: rs:32 1x2 at 1920
>level 5, face 0: rs:32 1x1 at 1984
>r300TexParameter( GL_TEXTURE_MIN_FILTER )
>r300TexParameter( GL_TEXTURE_WRAP_S )
>r300TexParameter( GL_TEXTURE_WRAP_T )
>r300NewTextureObject( 0xd683708 (target = GL_FALSE) )
>level 0, face 0: rs:32 16x32 at 0
>level 1, face 0: rs:32 8x16 at 1024
>level 2, face 0: rs:32 4x8 at 1536
>level 3, face 0: rs:32 2x4 at 1792
>level 4, face 0: rs:32 1x2 at 1920
>level 5, face 0: rs:32 1x1 at 1984
>r300TexParameter( GL_TEXTURE_MIN_FILTER )
>r300TexParameter( GL_TEXTURE_WRAP_S )
>r300TexParameter( GL_TEXTURE_WRAP_T )
>r300NewTextureObject( 0xd6855f8 (target = GL_FALSE) )
>level 0, face 0: rs:32 2x32 at 0
>level 1, face 0: rs:32 1x16 at 1024
>level 2, face 0: rs:32 1x8 at 1536
>level 3, face 0: rs:32 1x4 at 1792
>level 4, face 0: rs:32 1x2 at 1920
>level 5, face 0: rs:32 1x1 at 1984
>r300TexParameter( GL_TEXTURE_MIN_FILTER )
>r300TexParameter( GL_TEXTURE_WRAP_S )
>r300TexParameter( GL_TEXTURE_WRAP_T )
>r300NewTextureObject( 0xd68d9d0 (target = GL_FALSE) )
>level 0, face 0: rs:128 64x64 at 0
>level 1, face 0: rs:64 32x32 at 8192
>level 2, face 0: rs:32 16x16 at 10240
>level 3, face 0: rs:32 8x8 at 10752
>level 4, face 0: rs:32 4x4 at 11008
>level 5, face 0: rs:32 2x2 at 11136
>level 6, face 0: rs:32 1x1 at 11200
>r300TexParameter( GL_TEXTURE_MIN_FILTER )
>r300TexParameter( GL_TEXTURE_WRAP_S )
>r300TexParameter( GL_TEXTURE_WRAP_T )
>r300NewTextureObject( 0xd692b10 (target = GL_FALSE) )
>level 0, face 0: rs:32 16x32 at 0
>level 1, face 0: rs:32 8x16 at 1024
>level 2, face 0: rs:32 4x8 at 1536
>level 3, face 0: rs:32 2x4 at 1792
>level 4, face 0: rs:32 1x2 at 1920
>level 5, face 0: rs:32 1x1 at 1984
>r300TexParameter( GL_TEXTURE_MIN_FILTER )
>r300TexParameter( GL_TEXTURE_WRAP_S )
>r300TexParameter( GL_TEXTURE_WRAP_T )
>r300NewTextureObject( 0xd694a68 (target = GL_FALSE) )
>level 0, face 0: rs:32 2x32 at 0
>level 1, face 0: rs:32 1x16 at 1024
>level 2, face 0: rs:32 1x8 at 1536
>level 3, face 0: rs:32 1x4 at 1792
>level 4, face 0: rs:32 1x2 at 1920
>level 5, face 0: rs:32 1x1 at 1984
>r300TexParameter( GL_TEXTURE_MIN_FILTER )
>r300TexParameter( GL_TEXTURE_WRAP_S )
>r300TexParameter( GL_TEXTURE_WRAP_T )
>r300NewTextureObject( 0xd696a10 (target = GL_FALSE) )
>level 0, face 0: rs:32 16x32 at 0
>level 1, face 0: rs:32 8x16 at 1024
>level 2, face 0: rs:32 4x8 at 1536
>level 3, face 0: rs:32 2x4 at 1792
>level 4, face 0: rs:32 1x2 at 1920
>level 5, face 0: rs:32 1x1 at 1984
>r300TexParameter( GL_TEXTURE_MIN_FILTER )
>r300TexParameter( GL_TEXTURE_WRAP_S )
>r300TexParameter( GL_TEXTURE_WRAP_T )
>r300NewTextureObject( 0xd655d58 (target = GL_FALSE) )
>level 0, face 0: rs:32 2x32 at 0
>level 1, face 0: rs:32 1x16 at 1024
>level 2, face 0: rs:32 1x8 at 1536
>level 3, face 0: rs:32 1x4 at 1792
>level 4, face 0: rs:32 1x2 at 1920
>level 5, face 0: rs:32 1x1 at 1984
>r300TexParameter( GL_TEXTURE_MIN_FILTER )
>r300TexParameter( GL_TEXTURE_WRAP_S )
>r300TexParameter( GL_TEXTURE_WRAP_T )
>r300NewTextureObject( 0xd6a69e0 (target = GL_FALSE) )
>level 0, face 0: rs:128 64x64 at 0
>level 1, face 0: rs:64 32x32 at 8192
>level 2, face 0: rs:32 16x16 at 10240
>level 3, face 0: rs:32 8x8 at 10752
>level 4, face 0: rs:32 4x4 at 11008
>level 5, face 0: rs:32 2x2 at 11136
>level 6, face 0: rs:32 1x1 at 11200
>r300TexParameter( GL_TEXTURE_MIN_FILTER )
>r300TexParameter( GL_TEXTURE_WRAP_S )
>r300TexParameter( GL_TEXTURE_WRAP_T )
>r300NewTextureObject( 0xd6abb20 (target = GL_FALSE) )
>level 0, face 0: rs:32 16x32 at 0
>level 1, face 0: rs:32 8x16 at 1024
>level 2, face 0: rs:32 4x8 at 1536
>level 3, face 0: rs:32 2x4 at 1792
>level 4, face 0: rs:32 1x2 at 1920
>level 5, face 0: rs:32 1x1 at 1984
>r300TexParameter( GL_TEXTURE_MIN_FILTER )
>r300TexParameter( GL_TEXTURE_WRAP_S )
>r300TexParameter( GL_TEXTURE_WRAP_T )
>r300NewTextureObject( 0xd6ada78 (target = GL_FALSE) )
>level 0, face 0: rs:32 2x32 at 0
>level 1, face 0: rs:32 1x16 at 1024
>level 2, face 0: rs:32 1x8 at 1536
>level 3, face 0: rs:32 1x4 at 1792
>level 4, face 0: rs:32 1x2 at 1920
>level 5, face 0: rs:32 1x1 at 1984
>r300TexParameter( GL_TEXTURE_MIN_FILTER )
>r300TexParameter( GL_TEXTURE_WRAP_S )
>r300TexParameter( GL_TEXTURE_WRAP_T )
>r300NewTextureObject( 0xd6afa20 (target = GL_FALSE) )
>level 0, face 0: rs:32 16x32 at 0
>level 1, face 0: rs:32 8x16 at 1024
>level 2, face 0: rs:32 4x8 at 1536
>level 3, face 0: rs:32 2x4 at 1792
>level 4, face 0: rs:32 1x2 at 1920
>level 5, face 0: rs:32 1x1 at 1984
>r300TexParameter( GL_TEXTURE_MIN_FILTER )
>r300TexParameter( GL_TEXTURE_WRAP_S )
>r300TexParameter( GL_TEXTURE_WRAP_T )
>r300NewTextureObject( 0xd6b1910 (target = GL_FALSE) )
>level 0, face 0: rs:32 2x32 at 0
>level 1, face 0: rs:32 1x16 at 1024
>level 2, face 0: rs:32 1x8 at 1536
>level 3, face 0: rs:32 1x4 at 1792
>level 4, face 0: rs:32 1x2 at 1920
>level 5, face 0: rs:32 1x1 at 1984
>r300TexParameter( GL_TEXTURE_MIN_FILTER )
>r300TexParameter( GL_TEXTURE_WRAP_S )
>r300TexParameter( GL_TEXTURE_WRAP_T )
>r300NewTextureObject( 0xd41bd90 (target = GL_FALSE) )
>level 0, face 0: rs:256 128x128 at 0
>level 1, face 0: rs:128 64x64 at 32768
>level 2, face 0: rs:64 32x32 at 40960
>level 3, face 0: rs:32 16x16 at 43008
>level 4, face 0: rs:32 8x8 at 43520
>level 5, face 0: rs:32 4x4 at 43776
>level 6, face 0: rs:32 2x2 at 43904
>level 7, face 0: rs:32 1x1 at 43968
>r300TexParameter( GL_TEXTURE_MIN_FILTER )
>r300TexParameter( GL_TEXTURE_WRAP_S )
>r300TexParameter( GL_TEXTURE_WRAP_T )
>r300NewTextureObject( 0xd41d048 (target = GL_FALSE) )
>level 0, face 0: rs:256 128x128 at 0
>level 1, face 0: rs:128 64x64 at 32768
>level 2, face 0: rs:64 32x32 at 40960
>level 3, face 0: rs:32 16x16 at 43008
>level 4, face 0: rs:32 8x8 at 43520
>level 5, face 0: rs:32 4x4 at 43776
>level 6, face 0: rs:32 2x2 at 43904
>level 7, face 0: rs:32 1x1 at 43968
>r300TexParameter( GL_TEXTURE_MIN_FILTER )
>r300TexParameter( GL_TEXTURE_WRAP_S )
>r300TexParameter( GL_TEXTURE_WRAP_T )
>r300NewTextureObject( 0xd41e208 (target = GL_FALSE) )
>level 0, face 0: rs:256 128x128 at 0
>level 1, face 0: rs:128 64x64 at 32768
>level 2, face 0: rs:64 32x32 at 40960
>level 3, face 0: rs:32 16x16 at 43008
>level 4, face 0: rs:32 8x8 at 43520
>level 5, face 0: rs:32 4x4 at 43776
>level 6, face 0: rs:32 2x2 at 43904
>level 7, face 0: rs:32 1x1 at 43968
>r300TexParameter( GL_TEXTURE_MIN_FILTER )
>r300TexParameter( GL_TEXTURE_WRAP_S )
>r300TexParameter( GL_TEXTURE_WRAP_T )
>r300NewTextureObject( 0xd42a498 (target = GL_FALSE) )
>level 0, face 0: rs:256 128x128 at 0
>level 1, face 0: rs:128 64x64 at 32768
>level 2, face 0: rs:64 32x32 at 40960
>level 3, face 0: rs:32 16x16 at 43008
>level 4, face 0: rs:32 8x8 at 43520
>level 5, face 0: rs:32 4x4 at 43776
>level 6, face 0: rs:32 2x2 at 43904
>level 7, face 0: rs:32 1x1 at 43968
>r300TexParameter( GL_TEXTURE_MIN_FILTER )
>r300TexParameter( GL_TEXTURE_WRAP_S )
>r300TexParameter( GL_TEXTURE_WRAP_T )
>r300NewTextureObject( 0xd6c1c88 (target = GL_FALSE) )
>level 0, face 0: rs:2048 1024x512 at 0
>level 1, face 0: rs:1024 512x256 at 1048576
>level 2, face 0: rs:512 256x128 at 1310720
>level 3, face 0: rs:256 128x64 at 1376256
>level 4, face 0: rs:128 64x32 at 1392640
>level 5, face 0: rs:64 32x16 at 1396736
>level 6, face 0: rs:32 16x8 at 1397760
>level 7, face 0: rs:32 8x4 at 1398016
>level 8, face 0: rs:32 4x2 at 1398144
>level 9, face 0: rs:32 2x1 at 1398208
>level 10, face 0: rs:32 1x1 at 1398240
>r300TexParameter( GL_TEXTURE_MIN_FILTER )
>r300NewTextureObject( 0xd6c2dc8 (target = GL_FALSE) )
>level 0, face 0: rs:2048 1024x512 at 0
>level 1, face 0: rs:1024 512x256 at 1048576
>level 2, face 0: rs:512 256x128 at 1310720
>level 3, face 0: rs:256 128x64 at 1376256
>level 4, face 0: rs:128 64x32 at 1392640
>level 5, face 0: rs:64 32x16 at 1396736
>level 6, face 0: rs:32 16x8 at 1397760
>level 7, face 0: rs:32 8x4 at 1398016
>level 8, face 0: rs:32 4x2 at 1398144
>level 9, face 0: rs:32 2x1 at 1398208
>level 10, face 0: rs:32 1x1 at 1398240
>r300TexParameter( GL_TEXTURE_MIN_FILTER )
>r300NewTextureObject( 0xd6f52c0 (target = GL_FALSE) )
>level 0, face 0: rs:2048 1024x1024 at 0
>level 1, face 0: rs:1024 512x512 at 2097152
>level 2, face 0: rs:512 256x256 at 2621440
>level 3, face 0: rs:256 128x128 at 2752512
>level 4, face 0: rs:128 64x64 at 2785280
>level 5, face 0: rs:64 32x32 at 2793472
>level 6, face 0: rs:32 16x16 at 2795520
>level 7, face 0: rs:32 8x8 at 2796032
>level 8, face 0: rs:32 4x4 at 2796288
>level 9, face 0: rs:32 2x2 at 2796416
>level 10, face 0: rs:32 1x1 at 2796480
>r300TexParameter( GL_TEXTURE_MIN_FILTER )
>r300TexParameter( GL_TEXTURE_WRAP_S )
>r300TexParameter( GL_TEXTURE_WRAP_T )
>r300NewTextureObject( 0xd706270 (target = GL_FALSE) )
>level 0, face 0: rs:256 128x128 at 0
>level 1, face 0: rs:128 64x64 at 32768
>level 2, face 0: rs:64 32x32 at 40960
>level 3, face 0: rs:32 16x16 at 43008
>level 4, face 0: rs:32 8x8 at 43520
>level 5, face 0: rs:32 4x4 at 43776
>level 6, face 0: rs:32 2x2 at 43904
>level 7, face 0: rs:32 1x1 at 43968
>r300TexParameter( GL_TEXTURE_MIN_FILTER )
>r300TexParameter( GL_TEXTURE_WRAP_S )
>r300TexParameter( GL_TEXTURE_WRAP_T )
>r300NewTextureObject( 0xd706da0 (target = GL_FALSE) )
>level 0, face 0: rs:1024 512x512 at 0
>level 1, face 0: rs:512 256x256 at 524288
>level 2, face 0: rs:256 128x128 at 655360
>level 3, face 0: rs:128 64x64 at 688128
>level 4, face 0: rs:64 32x32 at 696320
>level 5, face 0: rs:32 16x16 at 698368
>level 6, face 0: rs:32 8x8 at 698880
>level 7, face 0: rs:32 4x4 at 699136
>level 8, face 0: rs:32 2x2 at 699264
>level 9, face 0: rs:32 1x1 at 699328
>r300TexParameter( GL_TEXTURE_MIN_FILTER )
>r300TexParameter( GL_TEXTURE_WRAP_S )
>r300TexParameter( GL_TEXTURE_WRAP_T )
>r300NewTextureObject( 0xd7080f0 (target = GL_FALSE) )
>level 0, face 0: rs:32 16x16 at 0
>level 1, face 0: rs:32 8x8 at 512
>level 2, face 0: rs:32 4x4 at 768
>level 3, face 0: rs:32 2x2 at 896
>level 4, face 0: rs:32 1x1 at 960
>r300TexParameter( GL_TEXTURE_MIN_FILTER )
>r300NewTextureObject( 0xd70a180 (target = GL_FALSE) )
>level 0, face 0: rs:2048 1024x1024 at 0
>level 1, face 0: rs:1024 512x512 at 2097152
>level 2, face 0: rs:512 256x256 at 2621440
>level 3, face 0: rs:256 128x128 at 2752512
>level 4, face 0: rs:128 64x64 at 2785280
>level 5, face 0: rs:64 32x32 at 2793472
>level 6, face 0: rs:32 16x16 at 2795520
>level 7, face 0: rs:32 8x8 at 2796032
>level 8, face 0: rs:32 4x4 at 2796288
>level 9, face 0: rs:32 2x2 at 2796416
>level 10, face 0: rs:32 1x1 at 2796480
>r300TexParameter( GL_TEXTURE_MIN_FILTER )
>r300TexParameter( GL_TEXTURE_WRAP_S )
>r300TexParameter( GL_TEXTURE_WRAP_T )
>r300NewTextureObject( 0xd70b590 (target = GL_FALSE) )
>level 0, face 0: rs:2048 1024x512 at 0
>level 1, face 0: rs:1024 512x256 at 1048576
>level 2, face 0: rs:512 256x128 at 1310720
>level 3, face 0: rs:256 128x64 at 1376256
>level 4, face 0: rs:128 64x32 at 1392640
>level 5, face 0: rs:64 32x16 at 1396736
>level 6, face 0: rs:32 16x8 at 1397760
>level 7, face 0: rs:32 8x4 at 1398016
>level 8, face 0: rs:32 4x2 at 1398144
>level 9, face 0: rs:32 2x1 at 1398208
>level 10, face 0: rs:32 1x1 at 1398240
>r300TexParameter( GL_TEXTURE_MIN_FILTER )
>r300TexParameter( GL_TEXTURE_WRAP_S )
>r300TexParameter( GL_TEXTURE_WRAP_T )
>r300NewTextureObject( 0xd7145a8 (target = GL_FALSE) )
>level 0, face 0: rs:1024 512x512 at 0
>level 1, face 0: rs:512 256x256 at 524288
>level 2, face 0: rs:256 128x128 at 655360
>level 3, face 0: rs:128 64x64 at 688128
>level 4, face 0: rs:64 32x32 at 696320
>level 5, face 0: rs:32 16x16 at 698368
>level 6, face 0: rs:32 8x8 at 698880
>level 7, face 0: rs:32 4x4 at 699136
>level 8, face 0: rs:32 2x2 at 699264
>level 9, face 0: rs:32 1x1 at 699328
>r300TexParameter( GL_TEXTURE_MIN_FILTER )
>r300NewTextureObject( 0xd715f70 (target = GL_FALSE) )
>level 0, face 0: rs:1024 512x64 at 0
>level 1, face 0: rs:512 256x32 at 65536
>level 2, face 0: rs:256 128x16 at 81920
>level 3, face 0: rs:128 64x8 at 86016
>level 4, face 0: rs:64 32x4 at 87040
>level 5, face 0: rs:32 16x2 at 87296
>level 6, face 0: rs:32 8x1 at 87360
>level 7, face 0: rs:32 4x1 at 87392
>level 8, face 0: rs:32 2x1 at 87424
>level 9, face 0: rs:32 1x1 at 87456
>r300TexParameter( GL_TEXTURE_MIN_FILTER )
>r300TexParameter( GL_TEXTURE_WRAP_S )
>r300TexParameter( GL_TEXTURE_WRAP_T )
>r300NewTextureObject( 0xd70e228 (target = GL_FALSE) )
>level 0, face 0: rs:512 256x512 at 0
>level 1, face 0: rs:256 128x256 at 262144
>level 2, face 0: rs:128 64x128 at 327680
>level 3, face 0: rs:64 32x64 at 344064
>level 4, face 0: rs:32 16x32 at 348160
>level 5, face 0: rs:32 8x16 at 349184
>level 6, face 0: rs:32 4x8 at 349696
>level 7, face 0: rs:32 2x4 at 349952
>level 8, face 0: rs:32 1x2 at 350080
>level 9, face 0: rs:32 1x1 at 350144
>r300TexParameter( GL_TEXTURE_MIN_FILTER )
>r300TexParameter( GL_TEXTURE_WRAP_S )
>r300TexParameter( GL_TEXTURE_WRAP_T )
>r300NewTextureObject( 0xd70f930 (target = GL_FALSE) )
>level 0, face 0: rs:512 256x32 at 0
>level 1, face 0: rs:256 128x16 at 16384
>level 2, face 0: rs:128 64x8 at 20480
>level 3, face 0: rs:64 32x4 at 21504
>level 4, face 0: rs:32 16x2 at 21760
>level 5, face 0: rs:32 8x1 at 21824
>level 6, face 0: rs:32 4x1 at 21856
>level 7, face 0: rs:32 2x1 at 21888
>level 8, face 0: rs:32 1x1 at 21920
>r300TexParameter( GL_TEXTURE_MIN_FILTER )
>r300TexParameter( GL_TEXTURE_WRAP_S )
>r300TexParameter( GL_TEXTURE_WRAP_T )
>r300NewTextureObject( 0xd7333a8 (target = GL_FALSE) )
>level 0, face 0: rs:256 128x32 at 0
>level 1, face 0: rs:128 64x16 at 8192
>level 2, face 0: rs:64 32x8 at 10240
>level 3, face 0: rs:32 16x4 at 10752
>level 4, face 0: rs:32 8x2 at 10880
>level 5, face 0: rs:32 4x1 at 10944
>level 6, face 0: rs:32 2x1 at 10976
>level 7, face 0: rs:32 1x1 at 11008
>r300TexParameter( GL_TEXTURE_MIN_FILTER )
>r300TexParameter( GL_TEXTURE_WRAP_S )
>r300TexParameter( GL_TEXTURE_WRAP_T )
>r300NewTextureObject( 0xd713880 (target = GL_FALSE) )
>level 0, face 0: rs:256 128x32 at 0
>level 1, face 0: rs:128 64x16 at 8192
>level 2, face 0: rs:64 32x8 at 10240
>level 3, face 0: rs:32 16x4 at 10752
>level 4, face 0: rs:32 8x2 at 10880
>level 5, face 0: rs:32 4x1 at 10944
>level 6, face 0: rs:32 2x1 at 10976
>level 7, face 0: rs:32 1x1 at 11008
>r300TexParameter( GL_TEXTURE_MIN_FILTER )
>r300TexParameter( GL_TEXTURE_WRAP_S )
>r300TexParameter( GL_TEXTURE_WRAP_T )
>r300NewTextureObject( 0xd734890 (target = GL_FALSE) )
>level 0, face 0: rs:512 256x256 at 0
>level 1, face 0: rs:256 128x128 at 131072
>level 2, face 0: rs:128 64x64 at 163840
>level 3, face 0: rs:64 32x32 at 172032
>level 4, face 0: rs:32 16x16 at 174080
>level 5, face 0: rs:32 8x8 at 174592
>level 6, face 0: rs:32 4x4 at 174848
>level 7, face 0: rs:32 2x2 at 174976
>level 8, face 0: rs:32 1x1 at 175040
>r300TexParameter( GL_TEXTURE_MIN_FILTER )
>r300TexParameter( GL_TEXTURE_WRAP_S )
>r300TexParameter( GL_TEXTURE_WRAP_T )
>r300NewTextureObject( 0xd704998 (target = GL_FALSE) )
>level 0, face 0: rs:512 256x256 at 0
>level 1, face 0: rs:256 128x128 at 131072
>level 2, face 0: rs:128 64x64 at 163840
>level 3, face 0: rs:64 32x32 at 172032
>level 4, face 0: rs:32 16x16 at 174080
>level 5, face 0: rs:32 8x8 at 174592
>level 6, face 0: rs:32 4x4 at 174848
>level 7, face 0: rs:32 2x2 at 174976
>level 8, face 0: rs:32 1x1 at 175040
>r300TexParameter( GL_TEXTURE_MIN_FILTER )
>r300TexParameter( GL_TEXTURE_WRAP_S )
>r300TexParameter( GL_TEXTURE_WRAP_T )
>r300NewTextureObject( 0xd7058e0 (target = GL_FALSE) )
>level 0, face 0: rs:512 256x256 at 0
>level 1, face 0: rs:256 128x128 at 131072
>level 2, face 0: rs:128 64x64 at 163840
>level 3, face 0: rs:64 32x32 at 172032
>level 4, face 0: rs:32 16x16 at 174080
>level 5, face 0: rs:32 8x8 at 174592
>level 6, face 0: rs:32 4x4 at 174848
>level 7, face 0: rs:32 2x2 at 174976
>level 8, face 0: rs:32 1x1 at 175040
>r300TexParameter( GL_TEXTURE_MIN_FILTER )
>r300TexParameter( GL_TEXTURE_WRAP_S )
>r300TexParameter( GL_TEXTURE_WRAP_T )
>r300NewTextureObject( 0xd81f360 (target = GL_FALSE) )
>level 0, face 0: rs:512 256x256 at 0
>level 1, face 0: rs:256 128x128 at 131072
>level 2, face 0: rs:128 64x64 at 163840
>level 3, face 0: rs:64 32x32 at 172032
>level 4, face 0: rs:32 16x16 at 174080
>level 5, face 0: rs:32 8x8 at 174592
>level 6, face 0: rs:32 4x4 at 174848
>level 7, face 0: rs:32 2x2 at 174976
>level 8, face 0: rs:32 1x1 at 175040
>r300TexParameter( GL_TEXTURE_MIN_FILTER )
>r300TexParameter( GL_TEXTURE_WRAP_S )
>r300TexParameter( GL_TEXTURE_WRAP_T )
>r300NewTextureObject( 0xd820428 (target = GL_FALSE) )
>level 0, face 0: rs:512 256x256 at 0
>level 1, face 0: rs:256 128x128 at 131072
>level 2, face 0: rs:128 64x64 at 163840
>level 3, face 0: rs:64 32x32 at 172032
>level 4, face 0: rs:32 16x16 at 174080
>level 5, face 0: rs:32 8x8 at 174592
>level 6, face 0: rs:32 4x4 at 174848
>level 7, face 0: rs:32 2x2 at 174976
>level 8, face 0: rs:32 1x1 at 175040
>r300TexParameter( GL_TEXTURE_MIN_FILTER )
>r300TexParameter( GL_TEXTURE_WRAP_S )
>r300TexParameter( GL_TEXTURE_WRAP_T )
>r300NewTextureObject( 0xd698e50 (target = GL_FALSE) )
>level 0, face 0: rs:512 256x256 at 0
>level 1, face 0: rs:256 128x128 at 131072
>level 2, face 0: rs:128 64x64 at 163840
>level 3, face 0: rs:64 32x32 at 172032
>level 4, face 0: rs:32 16x16 at 174080
>level 5, face 0: rs:32 8x8 at 174592
>level 6, face 0: rs:32 4x4 at 174848
>level 7, face 0: rs:32 2x2 at 174976
>level 8, face 0: rs:32 1x1 at 175040
>r300TexParameter( GL_TEXTURE_MIN_FILTER )
>r300TexParameter( GL_TEXTURE_WRAP_S )
>r300TexParameter( GL_TEXTURE_WRAP_T )
>r300NewTextureObject( 0xd699f18 (target = GL_FALSE) )
>level 0, face 0: rs:512 256x256 at 0
>level 1, face 0: rs:256 128x128 at 131072
>level 2, face 0: rs:128 64x64 at 163840
>level 3, face 0: rs:64 32x32 at 172032
>level 4, face 0: rs:32 16x16 at 174080
>level 5, face 0: rs:32 8x8 at 174592
>level 6, face 0: rs:32 4x4 at 174848
>level 7, face 0: rs:32 2x2 at 174976
>level 8, face 0: rs:32 1x1 at 175040
>r300TexParameter( GL_TEXTURE_MIN_FILTER )
>r300TexParameter( GL_TEXTURE_WRAP_S )
>r300TexParameter( GL_TEXTURE_WRAP_T )
>r300NewTextureObject( 0xd69afe0 (target = GL_FALSE) )
>level 0, face 0: rs:512 256x256 at 0
>level 1, face 0: rs:256 128x128 at 131072
>level 2, face 0: rs:128 64x64 at 163840
>level 3, face 0: rs:64 32x32 at 172032
>level 4, face 0: rs:32 16x16 at 174080
>level 5, face 0: rs:32 8x8 at 174592
>level 6, face 0: rs:32 4x4 at 174848
>level 7, face 0: rs:32 2x2 at 174976
>level 8, face 0: rs:32 1x1 at 175040
>r300TexParameter( GL_TEXTURE_MIN_FILTER )
>r300TexParameter( GL_TEXTURE_WRAP_S )
>r300TexParameter( GL_TEXTURE_WRAP_T )
>r300NewTextureObject( 0xca21c58 (target = GL_FALSE) )
>level 0, face 0: rs:512 256x32 at 0
>level 1, face 0: rs:256 128x16 at 16384
>level 2, face 0: rs:128 64x8 at 20480
>level 3, face 0: rs:64 32x4 at 21504
>level 4, face 0: rs:32 16x2 at 21760
>level 5, face 0: rs:32 8x1 at 21824
>level 6, face 0: rs:32 4x1 at 21856
>level 7, face 0: rs:32 2x1 at 21888
>level 8, face 0: rs:32 1x1 at 21920
>r300TexParameter( GL_TEXTURE_MIN_FILTER )
>r300TexParameter( GL_TEXTURE_WRAP_S )
>r300TexParameter( GL_TEXTURE_WRAP_T )
>r300NewTextureObject( 0xd723bd8 (target = GL_FALSE) )
>level 0, face 0: rs:32 16x32 at 0
>level 1, face 0: rs:32 8x16 at 1024
>level 2, face 0: rs:32 4x8 at 1536
>level 3, face 0: rs:32 2x4 at 1792
>level 4, face 0: rs:32 1x2 at 1920
>level 5, face 0: rs:32 1x1 at 1984
>r300TexParameter( GL_TEXTURE_MIN_FILTER )
>r300TexParameter( GL_TEXTURE_WRAP_S )
>r300TexParameter( GL_TEXTURE_WRAP_T )
>r300NewTextureObject( 0xd725b30 (target = GL_FALSE) )
>level 0, face 0: rs:32 2x32 at 0
>level 1, face 0: rs:32 1x16 at 1024
>level 2, face 0: rs:32 1x8 at 1536
>level 3, face 0: rs:32 1x4 at 1792
>level 4, face 0: rs:32 1x2 at 1920
>level 5, face 0: rs:32 1x1 at 1984
>r300TexParameter( GL_TEXTURE_MIN_FILTER )
>r300TexParameter( GL_TEXTURE_WRAP_S )
>r300TexParameter( GL_TEXTURE_WRAP_T )
>r300NewTextureObject( 0xd7281c0 (target = GL_FALSE) )
>level 0, face 0: rs:32 16x32 at 0
>level 1, face 0: rs:32 8x16 at 1024
>level 2, face 0: rs:32 4x8 at 1536
>level 3, face 0: rs:32 2x4 at 1792
>level 4, face 0: rs:32 1x2 at 1920
>level 5, face 0: rs:32 1x1 at 1984
>r300TexParameter( GL_TEXTURE_MIN_FILTER )
>r300TexParameter( GL_TEXTURE_WRAP_S )
>r300TexParameter( GL_TEXTURE_WRAP_T )
>r300NewTextureObject( 0xd8c7438 (target = GL_FALSE) )
>level 0, face 0: rs:256 128x128 at 0
>level 1, face 0: rs:128 64x64 at 32768
>level 2, face 0: rs:64 32x32 at 40960
>level 3, face 0: rs:32 16x16 at 43008
>level 4, face 0: rs:32 8x8 at 43520
>level 5, face 0: rs:32 4x4 at 43776
>level 6, face 0: rs:32 2x2 at 43904
>level 7, face 0: rs:32 1x1 at 43968
>r300TexParameter( GL_TEXTURE_MIN_FILTER )
>r300TexParameter( GL_TEXTURE_WRAP_S )
>r300TexParameter( GL_TEXTURE_WRAP_T )
>r300NewTextureObject( 0xd8c8eb0 (target = GL_FALSE) )
>level 0, face 0: rs:256 128x128 at 0
>level 1, face 0: rs:128 64x64 at 32768
>level 2, face 0: rs:64 32x32 at 40960
>level 3, face 0: rs:32 16x16 at 43008
>level 4, face 0: rs:32 8x8 at 43520
>level 5, face 0: rs:32 4x4 at 43776
>level 6, face 0: rs:32 2x2 at 43904
>level 7, face 0: rs:32 1x1 at 43968
>r300TexParameter( GL_TEXTURE_MIN_FILTER )
>r300TexParameter( GL_TEXTURE_WRAP_S )
>r300TexParameter( GL_TEXTURE_WRAP_T )
>r300NewTextureObject( 0xd8c6158 (target = GL_FALSE) )
>level 0, face 0: rs:64 32x128 at 0
>level 1, face 0: rs:32 16x64 at 8192
>level 2, face 0: rs:32 8x32 at 10240
>level 3, face 0: rs:32 4x16 at 11264
>level 4, face 0: rs:32 2x8 at 11776
>level 5, face 0: rs:32 1x4 at 12032
>level 6, face 0: rs:32 1x2 at 12160
>level 7, face 0: rs:32 1x1 at 12224
>r300TexParameter( GL_TEXTURE_MIN_FILTER )
>r300TexParameter( GL_TEXTURE_WRAP_S )
>r300TexParameter( GL_TEXTURE_WRAP_T )
>r300NewTextureObject( 0xd8c6b18 (target = GL_FALSE) )
>level 0, face 0: rs:512 256x64 at 0
>level 1, face 0: rs:256 128x32 at 32768
>level 2, face 0: rs:128 64x16 at 40960
>level 3, face 0: rs:64 32x8 at 43008
>level 4, face 0: rs:32 16x4 at 43520
>level 5, face 0: rs:32 8x2 at 43648
>level 6, face 0: rs:32 4x1 at 43712
>level 7, face 0: rs:32 2x1 at 43744
>level 8, face 0: rs:32 1x1 at 43776
>r300TexParameter( GL_TEXTURE_MIN_FILTER )
>r300TexParameter( GL_TEXTURE_WRAP_S )
>r300TexParameter( GL_TEXTURE_WRAP_T )
>r300NewTextureObject( 0xd8cd2b8 (target = GL_FALSE) )
>level 0, face 0: rs:64 32x128 at 0
>level 1, face 0: rs:32 16x64 at 8192
>level 2, face 0: rs:32 8x32 at 10240
>level 3, face 0: rs:32 4x16 at 11264
>level 4, face 0: rs:32 2x8 at 11776
>level 5, face 0: rs:32 1x4 at 12032
>level 6, face 0: rs:32 1x2 at 12160
>level 7, face 0: rs:32 1x1 at 12224
>r300TexParameter( GL_TEXTURE_MIN_FILTER )
>r300TexParameter( GL_TEXTURE_WRAP_S )
>r300TexParameter( GL_TEXTURE_WRAP_T )
>r300NewTextureObject( 0xd8d12b8 (target = GL_FALSE) )
>level 0, face 0: rs:512 256x64 at 0
>level 1, face 0: rs:256 128x32 at 32768
>level 2, face 0: rs:128 64x16 at 40960
>level 3, face 0: rs:64 32x8 at 43008
>level 4, face 0: rs:32 16x4 at 43520
>level 5, face 0: rs:32 8x2 at 43648
>level 6, face 0: rs:32 4x1 at 43712
>level 7, face 0: rs:32 2x1 at 43744
>level 8, face 0: rs:32 1x1 at 43776
>r300TexParameter( GL_TEXTURE_MIN_FILTER )
>r300TexParameter( GL_TEXTURE_WRAP_S )
>r300TexParameter( GL_TEXTURE_WRAP_T )
>r300NewTextureObject( 0xd88f800 (target = GL_FALSE) )
>level 0, face 0: rs:64 32x128 at 0
>level 1, face 0: rs:32 16x64 at 8192
>level 2, face 0: rs:32 8x32 at 10240
>level 3, face 0: rs:32 4x16 at 11264
>level 4, face 0: rs:32 2x8 at 11776
>level 5, face 0: rs:32 1x4 at 12032
>level 6, face 0: rs:32 1x2 at 12160
>level 7, face 0: rs:32 1x1 at 12224
>r300TexParameter( GL_TEXTURE_MIN_FILTER )
>r300TexParameter( GL_TEXTURE_WRAP_S )
>r300TexParameter( GL_TEXTURE_WRAP_T )
>r300NewTextureObject( 0xd893878 (target = GL_FALSE) )
>level 0, face 0: rs:64 32x128 at 0
>level 1, face 0: rs:32 16x64 at 8192
>level 2, face 0: rs:32 8x32 at 10240
>level 3, face 0: rs:32 4x16 at 11264
>level 4, face 0: rs:32 2x8 at 11776
>level 5, face 0: rs:32 1x4 at 12032
>level 6, face 0: rs:32 1x2 at 12160
>level 7, face 0: rs:32 1x1 at 12224
>r300TexParameter( GL_TEXTURE_MIN_FILTER )
>r300TexParameter( GL_TEXTURE_WRAP_S )
>r300TexParameter( GL_TEXTURE_WRAP_T )
>r300NewTextureObject( 0xd6ff860 (target = GL_FALSE) )
>level 0, face 0: rs:32 16x4 at 0
>level 1, face 0: rs:32 8x2 at 128
>level 2, face 0: rs:32 4x1 at 192
>level 3, face 0: rs:32 2x1 at 224
>level 4, face 0: rs:32 1x1 at 256
>r300TexParameter( GL_TEXTURE_MIN_FILTER )
>r300TexParameter( GL_TEXTURE_WRAP_S )
>r300TexParameter( GL_TEXTURE_WRAP_T )
>r300NewTextureObject( 0xd702c50 (target = GL_FALSE) )
>level 0, face 0: rs:32 16x16 at 0
>level 1, face 0: rs:32 8x8 at 512
>level 2, face 0: rs:32 4x4 at 768
>level 3, face 0: rs:32 2x2 at 896
>level 4, face 0: rs:32 1x1 at 960
>r300TexParameter( GL_TEXTURE_MIN_FILTER )
>r300TexParameter( GL_TEXTURE_WRAP_S )
>r300TexParameter( GL_TEXTURE_WRAP_T )
>r300NewTextureObject( 0xd704688 (target = GL_FALSE) )
>level 0, face 0: rs:32 16x16 at 0
>level 1, face 0: rs:32 8x8 at 512
>level 2, face 0: rs:32 4x4 at 768
>level 3, face 0: rs:32 2x2 at 896
>level 4, face 0: rs:32 1x1 at 960
>r300TexParameter( GL_TEXTURE_MIN_FILTER )
>r300TexParameter( GL_TEXTURE_WRAP_S )
>r300TexParameter( GL_TEXTURE_WRAP_T )
>r300NewTextureObject( 0xda71330 (target = GL_FALSE) )
>level 0, face 0: rs:512 256x256 at 0
>level 1, face 0: rs:256 128x128 at 131072
>level 2, face 0: rs:128 64x64 at 163840
>level 3, face 0: rs:64 32x32 at 172032
>level 4, face 0: rs:32 16x16 at 174080
>level 5, face 0: rs:32 8x8 at 174592
>level 6, face 0: rs:32 4x4 at 174848
>level 7, face 0: rs:32 2x2 at 174976
>level 8, face 0: rs:32 1x1 at 175040
>r300TexParameter( GL_TEXTURE_MIN_FILTER )
>r300TexParameter( GL_TEXTURE_WRAP_S )
>r300TexParameter( GL_TEXTURE_WRAP_T )
>r300NewTextureObject( 0xda73690 (target = GL_FALSE) )
>level 0, face 0: rs:32 16x32 at 0
>level 1, face 0: rs:32 8x16 at 1024
>level 2, face 0: rs:32 4x8 at 1536
>level 3, face 0: rs:32 2x4 at 1792
>level 4, face 0: rs:32 1x2 at 1920
>level 5, face 0: rs:32 1x1 at 1984
>r300TexParameter( GL_TEXTURE_MIN_FILTER )
>r300TexParameter( GL_TEXTURE_WRAP_S )
>r300TexParameter( GL_TEXTURE_WRAP_T )
>r300NewTextureObject( 0xda890d8 (target = GL_FALSE) )
>level 0, face 0: rs:32 2x32 at 0
>level 1, face 0: rs:32 1x16 at 1024
>level 2, face 0: rs:32 1x8 at 1536
>level 3, face 0: rs:32 1x4 at 1792
>level 4, face 0: rs:32 1x2 at 1920
>level 5, face 0: rs:32 1x1 at 1984
>r300TexParameter( GL_TEXTURE_MIN_FILTER )
>r300TexParameter( GL_TEXTURE_WRAP_S )
>r300TexParameter( GL_TEXTURE_WRAP_T )
>r300NewTextureObject( 0xda93090 (target = GL_FALSE) )
>level 0, face 0: rs:128 64x128 at 0
>level 1, face 0: rs:64 32x64 at 16384
>level 2, face 0: rs:32 16x32 at 20480
>level 3, face 0: rs:32 8x16 at 21504
>level 4, face 0: rs:32 4x8 at 22016
>level 5, face 0: rs:32 2x4 at 22272
>level 6, face 0: rs:32 1x2 at 22400
>level 7, face 0: rs:32 1x1 at 22464
>r300TexParameter( GL_TEXTURE_MIN_FILTER )
>r300TexParameter( GL_TEXTURE_WRAP_S )
>r300TexParameter( GL_TEXTURE_WRAP_T )
>r300NewTextureObject( 0xda93d68 (target = GL_FALSE) )
>level 0, face 0: rs:32 2x32 at 0
>level 1, face 0: rs:32 1x16 at 1024
>level 2, face 0: rs:32 1x8 at 1536
>level 3, face 0: rs:32 1x4 at 1792
>level 4, face 0: rs:32 1x2 at 1920
>level 5, face 0: rs:32 1x1 at 1984
>r300TexParameter( GL_TEXTURE_MIN_FILTER )
>r300TexParameter( GL_TEXTURE_WRAP_S )
>r300TexParameter( GL_TEXTURE_WRAP_T )
>r300NewTextureObject( 0xdaa81e0 (target = GL_FALSE) )
>level 0, face 0: rs:512 256x256 at 0
>level 1, face 0: rs:256 128x128 at 131072
>level 2, face 0: rs:128 64x64 at 163840
>level 3, face 0: rs:64 32x32 at 172032
>level 4, face 0: rs:32 16x16 at 174080
>level 5, face 0: rs:32 8x8 at 174592
>level 6, face 0: rs:32 4x4 at 174848
>level 7, face 0: rs:32 2x2 at 174976
>level 8, face 0: rs:32 1x1 at 175040
>r300TexParameter( GL_TEXTURE_MIN_FILTER )
>r300TexParameter( GL_TEXTURE_WRAP_S )
>r300TexParameter( GL_TEXTURE_WRAP_T )
>r300NewTextureObject( 0xdb15650 (target = GL_FALSE) )
>level 0, face 0: rs:256 128x16 at 0
>level 1, face 0: rs:128 64x8 at 4096
>level 2, face 0: rs:64 32x4 at 5120
>level 3, face 0: rs:32 16x2 at 5376
>level 4, face 0: rs:32 8x1 at 5440
>level 5, face 0: rs:32 4x1 at 5472
>level 6, face 0: rs:32 2x1 at 5504
>level 7, face 0: rs:32 1x1 at 5536
>r300TexParameter( GL_TEXTURE_MIN_FILTER )
>r300TexParameter( GL_TEXTURE_WRAP_S )
>r300TexParameter( GL_TEXTURE_WRAP_T )
>r300NewTextureObject( 0xdb186d8 (target = GL_FALSE) )
>level 0, face 0: rs:128 64x2 at 0
>level 1, face 0: rs:64 32x1 at 256
>level 2, face 0: rs:32 16x1 at 320
>level 3, face 0: rs:32 8x1 at 352
>level 4, face 0: rs:32 4x1 at 384
>level 5, face 0: rs:32 2x1 at 416
>level 6, face 0: rs:32 1x1 at 448
>r300TexParameter( GL_TEXTURE_MIN_FILTER )
>r300TexParameter( GL_TEXTURE_WRAP_S )
>r300TexParameter( GL_TEXTURE_WRAP_T )
>r300NewTextureObject( 0xdb1a6f0 (target = GL_FALSE) )
>level 0, face 0: rs:256 128x16 at 0
>level 1, face 0: rs:128 64x8 at 4096
>level 2, face 0: rs:64 32x4 at 5120
>level 3, face 0: rs:32 16x2 at 5376
>level 4, face 0: rs:32 8x1 at 5440
>level 5, face 0: rs:32 4x1 at 5472
>level 6, face 0: rs:32 2x1 at 5504
>level 7, face 0: rs:32 1x1 at 5536
>r300TexParameter( GL_TEXTURE_MIN_FILTER )
>r300TexParameter( GL_TEXTURE_WRAP_S )
>r300TexParameter( GL_TEXTURE_WRAP_T )
>r300NewTextureObject( 0xdb1d750 (target = GL_FALSE) )
>level 0, face 0: rs:256 128x2 at 0
>level 1, face 0: rs:128 64x1 at 512
>level 2, face 0: rs:64 32x1 at 640
>level 3, face 0: rs:32 16x1 at 704
>level 4, face 0: rs:32 8x1 at 736
>level 5, face 0: rs:32 4x1 at 768
>level 6, face 0: rs:32 2x1 at 800
>level 7, face 0: rs:32 1x1 at 832
>r300TexParameter( GL_TEXTURE_MIN_FILTER )
>r300TexParameter( GL_TEXTURE_WRAP_S )
>r300TexParameter( GL_TEXTURE_WRAP_T )
>r300NewTextureObject( 0xdb1f808 (target = GL_FALSE) )
>level 0, face 0: rs:256 128x16 at 0
>level 1, face 0: rs:128 64x8 at 4096
>level 2, face 0: rs:64 32x4 at 5120
>level 3, face 0: rs:32 16x2 at 5376
>level 4, face 0: rs:32 8x1 at 5440
>level 5, face 0: rs:32 4x1 at 5472
>level 6, face 0: rs:32 2x1 at 5504
>level 7, face 0: rs:32 1x1 at 5536
>r300TexParameter( GL_TEXTURE_MIN_FILTER )
>r300TexParameter( GL_TEXTURE_WRAP_S )
>r300TexParameter( GL_TEXTURE_WRAP_T )
>r300NewTextureObject( 0xdaaa450 (target = GL_FALSE) )
>level 0, face 0: rs:256 128x32 at 0
>level 1, face 0: rs:128 64x16 at 8192
>level 2, face 0: rs:64 32x8 at 10240
>level 3, face 0: rs:32 16x4 at 10752
>level 4, face 0: rs:32 8x2 at 10880
>level 5, face 0: rs:32 4x1 at 10944
>level 6, face 0: rs:32 2x1 at 10976
>level 7, face 0: rs:32 1x1 at 11008
>r300TexParameter( GL_TEXTURE_MIN_FILTER )
>r300TexParameter( GL_TEXTURE_WRAP_S )
>r300TexParameter( GL_TEXTURE_WRAP_T )
>r300NewTextureObject( 0xdb149f0 (target = GL_FALSE) )
>level 0, face 0: rs:128 64x128 at 0
>level 1, face 0: rs:64 32x64 at 16384
>level 2, face 0: rs:32 16x32 at 20480
>level 3, face 0: rs:32 8x16 at 21504
>level 4, face 0: rs:32 4x8 at 22016
>level 5, face 0: rs:32 2x4 at 22272
>level 6, face 0: rs:32 1x2 at 22400
>level 7, face 0: rs:32 1x1 at 22464
>r300TexParameter( GL_TEXTURE_MIN_FILTER )
>r300TexParameter( GL_TEXTURE_WRAP_S )
>r300TexParameter( GL_TEXTURE_WRAP_T )
>r300NewTextureObject( 0xdabcd70 (target = GL_FALSE) )
>level 0, face 0: rs:512 256x32 at 0
>level 1, face 0: rs:256 128x16 at 16384
>level 2, face 0: rs:128 64x8 at 20480
>level 3, face 0: rs:64 32x4 at 21504
>level 4, face 0: rs:32 16x2 at 21760
>level 5, face 0: rs:32 8x1 at 21824
>level 6, face 0: rs:32 4x1 at 21856
>level 7, face 0: rs:32 2x1 at 21888
>level 8, face 0: rs:32 1x1 at 21920
>r300TexParameter( GL_TEXTURE_MIN_FILTER )
>r300TexParameter( GL_TEXTURE_WRAP_S )
>r300TexParameter( GL_TEXTURE_WRAP_T )
>r300NewTextureObject( 0xdac6548 (target = GL_FALSE) )
>level 0, face 0: rs:64 32x32 at 0
>level 1, face 0: rs:32 16x16 at 2048
>level 2, face 0: rs:32 8x8 at 2560
>level 3, face 0: rs:32 4x4 at 2816
>level 4, face 0: rs:32 2x2 at 2944
>level 5, face 0: rs:32 1x1 at 3008
>r300TexParameter( GL_TEXTURE_MIN_FILTER )
>r300TexParameter( GL_TEXTURE_WRAP_S )
>r300TexParameter( GL_TEXTURE_WRAP_T )
>r300NewTextureObject( 0xdac94b8 (target = GL_FALSE) )
>level 0, face 0: rs:64 32x32 at 0
>level 1, face 0: rs:32 16x16 at 2048
>level 2, face 0: rs:32 8x8 at 2560
>level 3, face 0: rs:32 4x4 at 2816
>level 4, face 0: rs:32 2x2 at 2944
>level 5, face 0: rs:32 1x1 at 3008
>r300TexParameter( GL_TEXTURE_MIN_FILTER )
>r300TexParameter( GL_TEXTURE_WRAP_S )
>r300TexParameter( GL_TEXTURE_WRAP_T )
>r300NewTextureObject( 0xdacc0d8 (target = GL_FALSE) )
>level 0, face 0: rs:64 32x32 at 0
>level 1, face 0: rs:32 16x16 at 2048
>level 2, face 0: rs:32 8x8 at 2560
>level 3, face 0: rs:32 4x4 at 2816
>level 4, face 0: rs:32 2x2 at 2944
>level 5, face 0: rs:32 1x1 at 3008
>r300TexParameter( GL_TEXTURE_MIN_FILTER )
>r300TexParameter( GL_TEXTURE_WRAP_S )
>r300TexParameter( GL_TEXTURE_WRAP_T )
>r300NewTextureObject( 0xdad8f08 (target = GL_FALSE) )
>level 0, face 0: rs:64 32x32 at 0
>level 1, face 0: rs:32 16x16 at 2048
>level 2, face 0: rs:32 8x8 at 2560
>level 3, face 0: rs:32 4x4 at 2816
>level 4, face 0: rs:32 2x2 at 2944
>level 5, face 0: rs:32 1x1 at 3008
>r300TexParameter( GL_TEXTURE_MIN_FILTER )
>r300TexParameter( GL_TEXTURE_WRAP_S )
>r300TexParameter( GL_TEXTURE_WRAP_T )
>r300NewTextureObject( 0xdadaec0 (target = GL_FALSE) )
>level 0, face 0: rs:128 64x64 at 0
>level 1, face 0: rs:64 32x32 at 8192
>level 2, face 0: rs:32 16x16 at 10240
>level 3, face 0: rs:32 8x8 at 10752
>level 4, face 0: rs:32 4x4 at 11008
>level 5, face 0: rs:32 2x2 at 11136
>level 6, face 0: rs:32 1x1 at 11200
>r300TexParameter( GL_TEXTURE_MIN_FILTER )
>r300TexParameter( GL_TEXTURE_WRAP_S )
>r300TexParameter( GL_TEXTURE_WRAP_T )
>r300NewTextureObject( 0xdb5c210 (target = GL_FALSE) )
>level 0, face 0: rs:256 128x128 at 0
>level 1, face 0: rs:128 64x64 at 32768
>level 2, face 0: rs:64 32x32 at 40960
>level 3, face 0: rs:32 16x16 at 43008
>level 4, face 0: rs:32 8x8 at 43520
>level 5, face 0: rs:32 4x4 at 43776
>level 6, face 0: rs:32 2x2 at 43904
>level 7, face 0: rs:32 1x1 at 43968
>r300TexParameter( GL_TEXTURE_MIN_FILTER )
>r300TexParameter( GL_TEXTURE_WRAP_S )
>r300TexParameter( GL_TEXTURE_WRAP_T )
>r300NewTextureObject( 0xdb5f7e8 (target = GL_FALSE) )
>level 0, face 0: rs:512 256x256 at 0
>level 1, face 0: rs:256 128x128 at 131072
>level 2, face 0: rs:128 64x64 at 163840
>level 3, face 0: rs:64 32x32 at 172032
>level 4, face 0: rs:32 16x16 at 174080
>level 5, face 0: rs:32 8x8 at 174592
>level 6, face 0: rs:32 4x4 at 174848
>level 7, face 0: rs:32 2x2 at 174976
>level 8, face 0: rs:32 1x1 at 175040
>r300TexParameter( GL_TEXTURE_MIN_FILTER )
>r300TexParameter( GL_TEXTURE_WRAP_S )
>r300TexParameter( GL_TEXTURE_WRAP_T )
>r300NewTextureObject( 0xdbd04f0 (target = GL_FALSE) )
>level 0, face 0: rs:128 64x256 at 0
>level 1, face 0: rs:64 32x128 at 32768
>level 2, face 0: rs:32 16x64 at 40960
>level 3, face 0: rs:32 8x32 at 43008
>level 4, face 0: rs:32 4x16 at 44032
>level 5, face 0: rs:32 2x8 at 44544
>level 6, face 0: rs:32 1x4 at 44800
>level 7, face 0: rs:32 1x2 at 44928
>level 8, face 0: rs:32 1x1 at 44992
>r300TexParameter( GL_TEXTURE_MIN_FILTER )
>r300TexParameter( GL_TEXTURE_WRAP_S )
>r300TexParameter( GL_TEXTURE_WRAP_T )
>r300NewTextureObject( 0xdbec648 (target = GL_FALSE) )
>level 0, face 0: rs:512 256x256 at 0
>level 1, face 0: rs:256 128x128 at 131072
>level 2, face 0: rs:128 64x64 at 163840
>level 3, face 0: rs:64 32x32 at 172032
>level 4, face 0: rs:32 16x16 at 174080
>level 5, face 0: rs:32 8x8 at 174592
>level 6, face 0: rs:32 4x4 at 174848
>level 7, face 0: rs:32 2x2 at 174976
>level 8, face 0: rs:32 1x1 at 175040
>r300TexParameter( GL_TEXTURE_MIN_FILTER )
>r300TexParameter( GL_TEXTURE_WRAP_S )
>r300TexParameter( GL_TEXTURE_WRAP_T )
>r300NewTextureObject( 0xdbed720 (target = GL_FALSE) )
>level 0, face 0: rs:128 64x256 at 0
>level 1, face 0: rs:64 32x128 at 32768
>level 2, face 0: rs:32 16x64 at 40960
>level 3, face 0: rs:32 8x32 at 43008
>level 4, face 0: rs:32 4x16 at 44032
>level 5, face 0: rs:32 2x8 at 44544
>level 6, face 0: rs:32 1x4 at 44800
>level 7, face 0: rs:32 1x2 at 44928
>level 8, face 0: rs:32 1x1 at 44992
>r300TexParameter( GL_TEXTURE_MIN_FILTER )
>r300TexParameter( GL_TEXTURE_WRAP_S )
>r300TexParameter( GL_TEXTURE_WRAP_T )
>r300NewTextureObject( 0xdbf0898 (target = GL_FALSE) )
>level 0, face 0: rs:128 64x64 at 0
>level 1, face 0: rs:64 32x32 at 8192
>level 2, face 0: rs:32 16x16 at 10240
>level 3, face 0: rs:32 8x8 at 10752
>level 4, face 0: rs:32 4x4 at 11008
>level 5, face 0: rs:32 2x2 at 11136
>level 6, face 0: rs:32 1x1 at 11200
>r300TexParameter( GL_TEXTURE_MIN_FILTER )
>r300NewTextureObject( 0xdbf4fd8 (target = GL_FALSE) )
>level 0, face 0: rs:128 64x64 at 0
>level 1, face 0: rs:64 32x32 at 8192
>level 2, face 0: rs:32 16x16 at 10240
>level 3, face 0: rs:32 8x8 at 10752
>level 4, face 0: rs:32 4x4 at 11008
>level 5, face 0: rs:32 2x2 at 11136
>level 6, face 0: rs:32 1x1 at 11200
>r300TexParameter( GL_TEXTURE_MIN_FILTER )
>r300NewTextureObject( 0xdbf6728 (target = GL_FALSE) )
>level 0, face 0: rs:128 64x64 at 0
>level 1, face 0: rs:64 32x32 at 8192
>level 2, face 0: rs:32 16x16 at 10240
>level 3, face 0: rs:32 8x8 at 10752
>level 4, face 0: rs:32 4x4 at 11008
>level 5, face 0: rs:32 2x2 at 11136
>level 6, face 0: rs:32 1x1 at 11200
>r300TexParameter( GL_TEXTURE_MIN_FILTER )
>r300NewTextureObject( 0xdbc6ae0 (target = GL_FALSE) )
>level 0, face 0: rs:128 64x64 at 0
>level 1, face 0: rs:64 32x32 at 8192
>level 2, face 0: rs:32 16x16 at 10240
>level 3, face 0: rs:32 8x8 at 10752
>level 4, face 0: rs:32 4x4 at 11008
>level 5, face 0: rs:32 2x2 at 11136
>level 6, face 0: rs:32 1x1 at 11200
>r300TexParameter( GL_TEXTURE_MIN_FILTER )
>r300NewTextureObject( 0xdbcb210 (target = GL_FALSE) )
>level 0, face 0: rs:128 64x64 at 0
>level 1, face 0: rs:64 32x32 at 8192
>level 2, face 0: rs:32 16x16 at 10240
>level 3, face 0: rs:32 8x8 at 10752
>level 4, face 0: rs:32 4x4 at 11008
>level 5, face 0: rs:32 2x2 at 11136
>level 6, face 0: rs:32 1x1 at 11200
>r300TexParameter( GL_TEXTURE_MIN_FILTER )
>r300NewTextureObject( 0xdbcf958 (target = GL_FALSE) )
>level 0, face 0: rs:128 64x64 at 0
>level 1, face 0: rs:64 32x32 at 8192
>level 2, face 0: rs:32 16x16 at 10240
>level 3, face 0: rs:32 8x8 at 10752
>level 4, face 0: rs:32 4x4 at 11008
>level 5, face 0: rs:32 2x2 at 11136
>level 6, face 0: rs:32 1x1 at 11200
>r300TexParameter( GL_TEXTURE_MIN_FILTER )
>r300NewTextureObject( 0xdbd4318 (target = GL_FALSE) )
>level 0, face 0: rs:128 64x64 at 0
>level 1, face 0: rs:64 32x32 at 8192
>level 2, face 0: rs:32 16x16 at 10240
>level 3, face 0: rs:32 8x8 at 10752
>level 4, face 0: rs:32 4x4 at 11008
>level 5, face 0: rs:32 2x2 at 11136
>level 6, face 0: rs:32 1x1 at 11200
>r300TexParameter( GL_TEXTURE_MIN_FILTER )
>r300NewTextureObject( 0xdbd8a70 (target = GL_FALSE) )
>level 0, face 0: rs:128 64x64 at 0
>level 1, face 0: rs:64 32x32 at 8192
>level 2, face 0: rs:32 16x16 at 10240
>level 3, face 0: rs:32 8x8 at 10752
>level 4, face 0: rs:32 4x4 at 11008
>level 5, face 0: rs:32 2x2 at 11136
>level 6, face 0: rs:32 1x1 at 11200
>r300TexParameter( GL_TEXTURE_MIN_FILTER )
>r300NewTextureObject( 0xdc3ee60 (target = GL_FALSE) )
>level 0, face 0: rs:256 128x32 at 0
>level 1, face 0: rs:128 64x16 at 8192
>level 2, face 0: rs:64 32x8 at 10240
>level 3, face 0: rs:32 16x4 at 10752
>level 4, face 0: rs:32 8x2 at 10880
>level 5, face 0: rs:32 4x1 at 10944
>level 6, face 0: rs:32 2x1 at 10976
>level 7, face 0: rs:32 1x1 at 11008
>r300TexParameter( GL_TEXTURE_MIN_FILTER )
>r300TexParameter( GL_TEXTURE_WRAP_S )
>r300TexParameter( GL_TEXTURE_WRAP_T )
>r300NewTextureObject( 0xdc2f780 (target = GL_FALSE) )
>level 0, face 0: rs:32 16x16 at 0
>level 1, face 0: rs:32 8x8 at 512
>level 2, face 0: rs:32 4x4 at 768
>level 3, face 0: rs:32 2x2 at 896
>level 4, face 0: rs:32 1x1 at 960
>r300TexParameter( GL_TEXTURE_MIN_FILTER )
>r300TexParameter( GL_TEXTURE_WRAP_S )
>r300TexParameter( GL_TEXTURE_WRAP_T )
>r300NewTextureObject( 0xdc6cdc0 (target = GL_FALSE) )
>level 0, face 0: rs:512 256x128 at 0
>level 1, face 0: rs:256 128x64 at 65536
>level 2, face 0: rs:128 64x32 at 81920
>level 3, face 0: rs:64 32x16 at 86016
>level 4, face 0: rs:32 16x8 at 87040
>level 5, face 0: rs:32 8x4 at 87296
>level 6, face 0: rs:32 4x2 at 87424
>level 7, face 0: rs:32 2x1 at 87488
>level 8, face 0: rs:32 1x1 at 87520
>r300TexParameter( GL_TEXTURE_MIN_FILTER )
>r300TexParameter( GL_TEXTURE_WRAP_S )
>r300TexParameter( GL_TEXTURE_WRAP_T )
>r300NewTextureObject( 0xdca0c08 (target = GL_FALSE) )
>level 0, face 0: rs:256 128x128 at 0
>level 1, face 0: rs:128 64x64 at 32768
>level 2, face 0: rs:64 32x32 at 40960
>level 3, face 0: rs:32 16x16 at 43008
>level 4, face 0: rs:32 8x8 at 43520
>level 5, face 0: rs:32 4x4 at 43776
>level 6, face 0: rs:32 2x2 at 43904
>level 7, face 0: rs:32 1x1 at 43968
>r300TexParameter( GL_TEXTURE_MIN_FILTER )
>r300TexParameter( GL_TEXTURE_WRAP_S )
>r300TexParameter( GL_TEXTURE_WRAP_T )
>r300NewTextureObject( 0xdce90d8 (target = GL_FALSE) )
>level 0, face 0: rs:512 256x256 at 0
>level 1, face 0: rs:256 128x128 at 131072
>level 2, face 0: rs:128 64x64 at 163840
>level 3, face 0: rs:64 32x32 at 172032
>level 4, face 0: rs:32 16x16 at 174080
>level 5, face 0: rs:32 8x8 at 174592
>level 6, face 0: rs:32 4x4 at 174848
>level 7, face 0: rs:32 2x2 at 174976
>level 8, face 0: rs:32 1x1 at 175040
>r300TexParameter( GL_TEXTURE_MIN_FILTER )
>r300TexParameter( GL_TEXTURE_WRAP_S )
>r300TexParameter( GL_TEXTURE_WRAP_T )
>r300NewTextureObject( 0xdab75a8 (target = GL_FALSE) )
>level 0, face 0: rs:256 128x64 at 0
>level 1, face 0: rs:128 64x32 at 16384
>level 2, face 0: rs:64 32x16 at 20480
>level 3, face 0: rs:32 16x8 at 21504
>level 4, face 0: rs:32 8x4 at 21760
>level 5, face 0: rs:32 4x2 at 21888
>level 6, face 0: rs:32 2x1 at 21952
>level 7, face 0: rs:32 1x1 at 21984
>r300TexParameter( GL_TEXTURE_MIN_FILTER )
>r300TexParameter( GL_TEXTURE_WRAP_S )
>r300TexParameter( GL_TEXTURE_WRAP_T )
>r300NewTextureObject( 0xdd76c30 (target = GL_FALSE) )
>level 0, face 0: rs:256 128x128 at 0
>level 1, face 0: rs:128 64x64 at 32768
>level 2, face 0: rs:64 32x32 at 40960
>level 3, face 0: rs:32 16x16 at 43008
>level 4, face 0: rs:32 8x8 at 43520
>level 5, face 0: rs:32 4x4 at 43776
>level 6, face 0: rs:32 2x2 at 43904
>level 7, face 0: rs:32 1x1 at 43968
>r300TexParameter( GL_TEXTURE_MIN_FILTER )
>r300TexParameter( GL_TEXTURE_WRAP_S )
>r300TexParameter( GL_TEXTURE_WRAP_T )
>r300NewTextureObject( 0xdd674a0 (target = GL_FALSE) )
>level 0, face 0: rs:32 16x16 at 0
>level 1, face 0: rs:32 8x8 at 512
>level 2, face 0: rs:32 4x4 at 768
>level 3, face 0: rs:32 2x2 at 896
>level 4, face 0: rs:32 1x1 at 960
>r300TexParameter( GL_TEXTURE_MIN_FILTER )
>r300NewTextureObject( 0xdd6b648 (target = GL_FALSE) )
>level 0, face 0: rs:1024 512x512 at 0
>level 1, face 0: rs:512 256x256 at 524288
>level 2, face 0: rs:256 128x128 at 655360
>level 3, face 0: rs:128 64x64 at 688128
>level 4, face 0: rs:64 32x32 at 696320
>level 5, face 0: rs:32 16x16 at 698368
>level 6, face 0: rs:32 8x8 at 698880
>level 7, face 0: rs:32 4x4 at 699136
>level 8, face 0: rs:32 2x2 at 699264
>level 9, face 0: rs:32 1x1 at 699328
>r300TexParameter( GL_TEXTURE_MIN_FILTER )
>r300TexParameter( GL_TEXTURE_WRAP_S )
>r300TexParameter( GL_TEXTURE_WRAP_T )
>r300NewTextureObject( 0xdd71b38 (target = GL_FALSE) )
>level 0, face 0: rs:512 256x256 at 0
>level 1, face 0: rs:256 128x128 at 131072
>level 2, face 0: rs:128 64x64 at 163840
>level 3, face 0: rs:64 32x32 at 172032
>level 4, face 0: rs:32 16x16 at 174080
>level 5, face 0: rs:32 8x8 at 174592
>level 6, face 0: rs:32 4x4 at 174848
>level 7, face 0: rs:32 2x2 at 174976
>level 8, face 0: rs:32 1x1 at 175040
>r300TexParameter( GL_TEXTURE_MIN_FILTER )
>r300TexParameter( GL_TEXTURE_WRAP_S )
>r300TexParameter( GL_TEXTURE_WRAP_T )
>r300NewTextureObject( 0xddb3298 (target = GL_FALSE) )
>level 0, face 0: rs:64 32x32 at 0
>level 1, face 0: rs:32 16x16 at 2048
>level 2, face 0: rs:32 8x8 at 2560
>level 3, face 0: rs:32 4x4 at 2816
>level 4, face 0: rs:32 2x2 at 2944
>level 5, face 0: rs:32 1x1 at 3008
>r300TexParameter( GL_TEXTURE_MIN_FILTER )
>r300TexParameter( GL_TEXTURE_WRAP_S )
>r300TexParameter( GL_TEXTURE_WRAP_T )
>r300NewTextureObject( 0xdc93118 (target = GL_FALSE) )
>level 0, face 0: rs:2048 1024x512 at 0
>level 1, face 0: rs:1024 512x256 at 1048576
>level 2, face 0: rs:512 256x128 at 1310720
>level 3, face 0: rs:256 128x64 at 1376256
>level 4, face 0: rs:128 64x32 at 1392640
>level 5, face 0: rs:64 32x16 at 1396736
>level 6, face 0: rs:32 16x8 at 1397760
>level 7, face 0: rs:32 8x4 at 1398016
>level 8, face 0: rs:32 4x2 at 1398144
>level 9, face 0: rs:32 2x1 at 1398208
>level 10, face 0: rs:32 1x1 at 1398240
>r300TexParameter( GL_TEXTURE_MIN_FILTER )
>r300TexParameter( GL_TEXTURE_WRAP_S )
>r300TexParameter( GL_TEXTURE_WRAP_T )
>r300NewTextureObject( 0xddce4e0 (target = GL_FALSE) )
>level 0, face 0: rs:512 256x64 at 0
>level 1, face 0: rs:256 128x32 at 32768
>level 2, face 0: rs:128 64x16 at 40960
>level 3, face 0: rs:64 32x8 at 43008
>level 4, face 0: rs:32 16x4 at 43520
>level 5, face 0: rs:32 8x2 at 43648
>level 6, face 0: rs:32 4x1 at 43712
>level 7, face 0: rs:32 2x1 at 43744
>level 8, face 0: rs:32 1x1 at 43776
>r300TexParameter( GL_TEXTURE_MIN_FILTER )
>r300TexParameter( GL_TEXTURE_WRAP_S )
>r300TexParameter( GL_TEXTURE_WRAP_T )

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Attachments on bug 22742: 27789 | 27790 | 27883 | 30487

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