Attachment 28807 Details for Bug 23112 – bad

bad

bad (text/plain), 9.05 KB, created by Dag Asheim on 2009-08-19 22:37:15 UTC

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Creator: Dag Asheim

Created: 2009-08-19 22:37:15 UTC

Size: 9.05 KB

patch

obsolete

>(II): DumpRegsBegin
>(II):                  DCC: 0x000f0400 (single channel, XOR randomization: disabled, XOR bit: 11)
>(II):            CHDECMISC: 0x11987820 (XOR bank/rank, ch2 enh disabled, ch1 enh disabled, ch0 enh disabled, flex disabled, ep not present)
>(II):               C0DRB0: 0x000f0400 (0x0400)
>(II):               C0DRB1: 0x0000000f (0x000f)
>(II):               C0DRB2: 0x00000000 (0x0000)
>(II):               C0DRB3: 0x04000000 (0x0000)
>(II):               C1DRB0: 0x05040302 (0x0302)
>(II):               C1DRB1: 0x07060504 (0x0504)
>(II):               C1DRB2: 0x09080706 (0x0706)
>(II):               C1DRB3: 0x0b0a0908 (0x0908)
>(II):              C0DRA01: 0x01000400 (0x0400)
>(II):              C0DRA23: 0x02000100 (0x0100)
>(II):              C1DRA01: 0x0d0c0b0a (0x0b0a)
>(II):              C1DRA23: 0x0f0e0d0c (0x0d0c)
>(II):           PGETBL_CTL: 0x4ffc0001
>(II):    VCLK_DIVISOR_VGA0: 0x00031108 (n = 3, m1 = 17, m2 = 8)
>(II):    VCLK_DIVISOR_VGA1: 0x00031406 (n = 3, m1 = 20, m2 = 6)
>(II):        VCLK_POST_DIV: 0x00800080 (vga0 p1 = 2, p2 = 4, vga1 p1 = 2, p2 = 2)
>(II):            DPLL_TEST: 0x00010001 ()
>(II):         CACHE_MODE_0: 0x00006820
>(II):              D_STATE: 0x00000000
>(II):        DSPCLK_GATE_D: 0x00000000 (clock gates disabled:)
>(II):       RENCLK_GATE_D1: 0x00000000
>(II):       RENCLK_GATE_D2: 0x00000000
>(II):                SDVOB: 0x00300000 (disabled, pipe A, stall disabled, not detected, SDVO mult 1)
>(II):                SDVOC: 0x00300000 (disabled, pipe A, stall disabled, not detected, SDVO mult 1)
>(II):              SDVOUDI: 0x000000fb
>(II):               DSPARB: 0x00001d9c
>(II):               DSPFW1: 0x00000000
>(II):               DSPFW2: 0x00000000
>(II):               DSPFW3: 0x00000000
>(II):                 ADPA: 0x80000018 (enabled, pipe A, +hsync, +vsync)
>(II):                 LVDS: 0xc0300300 (enabled, pipe B, 18 bit, 1 channel)
>(II):                 DVOA: 0x00000000 (disabled, pipe A, no stall, -hsync, -vsync)
>(II):                 DVOB: 0x00300000 (disabled, pipe A, no stall, -hsync, -vsync)
>(II):                 DVOC: 0x00300000 (disabled, pipe A, no stall, -hsync, -vsync)
>(II):          DVOA_SRCDIM: 0x00000000
>(II):          DVOB_SRCDIM: 0x00000000
>(II):          DVOC_SRCDIM: 0x00000000
>(II):           PP_CONTROL: 0x00000001 (power target: on)
>(II):            PP_STATUS: 0xc0000008 (on, ready, sequencing idle)
>(II):         PP_ON_DELAYS: 0x012c0fa0
>(II):        PP_OFF_DELAYS: 0x01c20fa0
>(II):           PP_DIVISOR: 0x001daf09
>(II):         PFIT_CONTROL: 0x00000008
>(II):      PFIT_PGM_RATIOS: 0x00000000
>(II):      PORT_HOTPLUG_EN: 0x00000000
>(II):    PORT_HOTPLUG_STAT: 0x00000000
>(II):             DSPACNTR: 0xd8000000 (enabled, pipe A)
>(II):           DSPASTRIDE: 0x00004000 (16384 bytes)
>(II):              DSPAPOS: 0x00000000 (0, 0)
>(II):             DSPASIZE: 0x04af063f (1600, 1200)
>(II):             DSPABASE: 0x06001400
>(II):             DSPASURF: 0x00000000
>(II):          DSPATILEOFF: 0x00000000
>(II):            PIPEACONF: 0x80000000 (enabled, single-wide)
>(II):             PIPEASRC: 0x063f04af (1600, 1200)
>(II):            PIPEASTAT: 0x80000303 (status: FIFO_UNDERRUN VSYNC_INT_STATUS DLINE_COMPARE_STATUS VBLANK_INT_STATUS OREG_UPDATE_STATUS)
>(II):    PIPEA_GMCH_DATA_M: 0x00000000
>(II):    PIPEA_GMCH_DATA_N: 0x00000000
>(II):      PIPEA_DP_LINK_M: 0x00000000
>(II):      PIPEA_DP_LINK_N: 0x00000000
>(II):                 FPA0: 0x00051406 (n = 5, m1 = 20, m2 = 6)
>(II):                 FPA1: 0x00031108 (n = 3, m1 = 17, m2 = 8)
>(II):               DPLL_A: 0x94010000 (enabled, non-dvo, default clock, DAC/serial mode, p1 = 1, p2 = 10)
>(II):            DPLL_A_MD: 0x00000000
>(II):             HTOTAL_A: 0x086f063f (1600 active, 2160 total)
>(II):             HBLANK_A: 0x086f063f (1600 start, 2160 end)
>(II):              HSYNC_A: 0x073f067f (1664 start, 1856 end)
>(II):             VTOTAL_A: 0x04e104af (1200 active, 1250 total)
>(II):             VBLANK_A: 0x04e104af (1200 start, 1250 end)
>(II):              VSYNC_A: 0x04b304b0 (1201 start, 1204 end)
>(II):            BCLRPAT_A: 0x00000000
>(II):         VSYNCSHIFT_A: 0x00000000
>(II):             DSPBCNTR: 0xd9000000 (enabled, pipe B)
>(II):           DSPBSTRIDE: 0x00004000 (16384 bytes)
>(II):              DSPBPOS: 0x00000000 (0, 0)
>(II):             DSPBSIZE: 0x02ff04ff (1280, 768)
>(II):             DSPBBASE: 0x06000000
>(II):             DSPBSURF: 0x00000000
>(II):          DSPBTILEOFF: 0x00000000
>(II):            PIPEBCONF: 0x80000000 (enabled, single-wide)
>(II):             PIPEBSRC: 0x04ff02ff (1280, 768)
>(II):            PIPEBSTAT: 0x00000302 (status: VSYNC_INT_STATUS DLINE_COMPARE_STATUS VBLANK_INT_STATUS)
>(II):    PIPEB_GMCH_DATA_M: 0x00000000
>(II):    PIPEB_GMCH_DATA_N: 0x00000000
>(II):      PIPEB_DP_LINK_M: 0x00000000
>(II):      PIPEB_DP_LINK_N: 0x00000000
>(II):                 FPB0: 0x00031309 (n = 3, m1 = 19, m2 = 9)
>(II):                 FPB1: 0x00031108 (n = 3, m1 = 17, m2 = 8)
>(II):               DPLL_B: 0x98026000 (enabled, non-dvo, spread spectrum clock, LVDS mode, p1 = 2, p2 = 14)
>(II):            DPLL_B_MD: 0x00000000
>(II):             HTOTAL_B: 0x067f04ff (1280 active, 1664 total)
>(II):             HBLANK_B: 0x067f04ff (1280 start, 1664 end)
>(II):              HSYNC_B: 0x05bf053f (1344 start, 1472 end)
>(II):             VTOTAL_B: 0x031d02ff (768 active, 798 total)
>(II):             VBLANK_B: 0x031d02ff (768 start, 798 end)
>(II):              VSYNC_B: 0x03090302 (771 start, 778 end)
>(II):            BCLRPAT_B: 0x00000000
>(II):         VSYNCSHIFT_B: 0x00000000
>(II):    VCLK_DIVISOR_VGA0: 0x00031108
>(II):    VCLK_DIVISOR_VGA1: 0x00031406
>(II):        VCLK_POST_DIV: 0x00800080
>(II):             VGACNTRL: 0x80000000 (disabled)
>(II):               TV_CTL: 0x00000000
>(II):               TV_DAC: 0x70000000
>(II):             TV_CSC_Y: 0x00000000
>(II):            TV_CSC_Y2: 0x00000000
>(II):             TV_CSC_U: 0x00000000
>(II):            TV_CSC_U2: 0x00000000
>(II):             TV_CSC_V: 0x00000000
>(II):            TV_CSC_V2: 0x00000000
>(II):         TV_CLR_KNOBS: 0x00000000
>(II):         TV_CLR_LEVEL: 0x00000000
>(II):           TV_H_CTL_1: 0x00000000
>(II):           TV_H_CTL_2: 0x00000000
>(II):           TV_H_CTL_3: 0x00000000
>(II):           TV_V_CTL_1: 0x00000000
>(II):           TV_V_CTL_2: 0x00000000
>(II):           TV_V_CTL_3: 0x00000000
>(II):           TV_V_CTL_4: 0x00000000
>(II):           TV_V_CTL_5: 0x00000000
>(II):           TV_V_CTL_6: 0x00000000
>(II):           TV_V_CTL_7: 0x00000000
>(II):          TV_SC_CTL_1: 0x00000000
>(II):          TV_SC_CTL_2: 0x00000000
>(II):          TV_SC_CTL_3: 0x00000000
>(II):           TV_WIN_POS: 0x00000000
>(II):          TV_WIN_SIZE: 0x00000000
>(II):      TV_FILTER_CTL_1: 0x00000000
>(II):      TV_FILTER_CTL_2: 0x00000000
>(II):      TV_FILTER_CTL_3: 0x00000000
>(II):        TV_CC_CONTROL: 0x00000000
>(II):           TV_CC_DATA: 0x00000000
>(II):          TV_H_LUMA_0: 0x00000000
>(II):         TV_H_LUMA_59: 0x00000000
>(II):        TV_H_CHROMA_0: 0x00000000
>(II):       TV_H_CHROMA_59: 0x00000000
>(II):         FBC_CFB_BASE: 0x00000000
>(II):          FBC_LL_BASE: 0x00000000
>(II):          FBC_CONTROL: 0x00000000
>(II):          FBC_COMMAND: 0x00000000
>(II):           FBC_STATUS: 0x20000000
>(II):         FBC_CONTROL2: 0x00000000
>(II):        FBC_FENCE_OFF: 0x00000000
>(II):          FBC_MOD_NUM: 0x00000000
>(II):              MI_MODE: 0x00000200
>(II):         MI_ARB_STATE: 0x00000040
>(II):       MI_RDRET_STATE: 0x00000000
>(II):              ECOSKPD: 0x00000307
>(II):                 DP_B: 0x00000000
>(II):       DPB_AUX_CH_CTL: 0x00000000
>(II):     DPB_AUX_CH_DATA1: 0x00000000
>(II):     DPB_AUX_CH_DATA2: 0x00000000
>(II):     DPB_AUX_CH_DATA3: 0x00000000
>(II):     DPB_AUX_CH_DATA4: 0x00000000
>(II):     DPB_AUX_CH_DATA5: 0x00000000
>(II):                 DP_C: 0x00000000
>(II):       DPC_AUX_CH_CTL: 0x00000000
>(II):     DPC_AUX_CH_DATA1: 0x00000000
>(II):     DPC_AUX_CH_DATA2: 0x00000000
>(II):     DPC_AUX_CH_DATA3: 0x00000000
>(II):     DPC_AUX_CH_DATA4: 0x00000000
>(II):     DPC_AUX_CH_DATA5: 0x00000000
>(II):                 DP_D: 0x00000000
>(II):       DPD_AUX_CH_CTL: 0x00000000
>(II):     DPD_AUX_CH_DATA1: 0x00000000
>(II):     DPD_AUX_CH_DATA2: 0x00000000
>(II):     DPD_AUX_CH_DATA3: 0x00000000
>(II):     DPD_AUX_CH_DATA4: 0x00000000
>(II):     DPD_AUX_CH_DATA5: 0x00000000
>(II):             FENCE  0: 0x00000000 (disabled, X tiled,    0 pitch, 0x00000000 - 0x00000000 (0kb))
>(II):             FENCE  1: 0x00000000 (disabled, X tiled,    0 pitch, 0x00000000 - 0x00000000 (0kb))
>(II):             FENCE  2: 0x00000000 (disabled, X tiled,    0 pitch, 0x00000000 - 0x00000000 (0kb))
>(II):             FENCE  3: 0x08000551 ( enabled, X tiled,   64 pitch, 0x08000000 - 0x09000000 (16384kb))
>(II):             FENCE  4: 0x0a000551 ( enabled, X tiled,   64 pitch, 0x0a000000 - 0x0b000000 (16384kb))
>(II):             FENCE  5: 0x00000000 (disabled, X tiled,    0 pitch, 0x00000000 - 0x00000000 (0kb))
>(II):             FENCE  6: 0x00000000 (disabled, X tiled,    0 pitch, 0x00000000 - 0x00000000 (0kb))
>(II):             FENCE  7: 0x00000000 (disabled, X tiled,    0 pitch, 0x00000000 - 0x00000000 (0kb))
>(II): pipe A dot 161828 n 5 m1 20 m2 6 p1 1 p2 10
>(II): pipe B dot 82857 n 3 m1 19 m2 9 p1 2 p2 14
>(II): DumpRegsEnd

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Attachments on bug 23112: 28307 | 28308 | 28309 | 28310 | 28806 | 28807 | 28808 | 28915 | 28936 | 28937 | 28938 | 28939 | 28940 | 28942

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