Attachment 29124 Details for Bug 22977 – intel_reg_dumper run with external monitor on Karmic.

intel_reg_dumper run with external monitor on Karmic.

intel_reg_dumper.txt (text/plain), 9.73 KB, created by Benedikt Kristinsson on 2009-09-02 14:32:44 UTC

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Creator: Benedikt Kristinsson

Created: 2009-09-02 14:32:44 UTC

Size: 9.73 KB

patch

obsolete

>(II): DumpRegsBegin
>(II):                  DCC: 0x00000000 (single channel, XOR randomization: enabled, XOR bit: 11)
>(II):            CHDECMISC: 0x00000000 (none, ch2 enh disabled, ch1 enh disabled, ch0 enh disabled, flex disabled, ep not present)
>(II):               C0DRB0: 0x00000000 (0x0000)
>(II):               C0DRB1: 0x00000000 (0x0000)
>(II):               C0DRB2: 0x00000000 (0x0000)
>(II):               C0DRB3: 0x00000000 (0x0000)
>(II):               C1DRB0: 0x00000000 (0x0000)
>(II):               C1DRB1: 0x00000000 (0x0000)
>(II):               C1DRB2: 0x00000000 (0x0000)
>(II):               C1DRB3: 0x00000000 (0x0000)
>(II):              C0DRA01: 0x00000000 (0x0000)
>(II):              C0DRA23: 0x00000000 (0x0000)
>(II):              C1DRA01: 0x00000000 (0x0000)
>(II):              C1DRA23: 0x00000000 (0x0000)
>(II):           PGETBL_CTL: 0x5ffe0001
>(II):    VCLK_DIVISOR_VGA0: 0x00021207 (n = 2, m1 = 18, m2 = 7)
>(II):    VCLK_DIVISOR_VGA1: 0x00031406 (n = 3, m1 = 20, m2 = 6)
>(II):        VCLK_POST_DIV: 0x0000888b (vga0 p1 = 13, p2 = 4, vga1 p1 = 10, p2 = 4)
>(II):            DPLL_TEST: 0x00000000 (, DPLLA input buffer disabled, DPLLB input buffer disabled)
>(II):         CACHE_MODE_0: 0x00000000
>(II):              D_STATE: 0x0000030f
>(II):        DSPCLK_GATE_D: 0x00000000 (clock gates disabled:)
>(II):       RENCLK_GATE_D1: 0x00000000
>(II):       RENCLK_GATE_D2: 0x00000000
>(II):                SDVOB: 0x00000000 (disabled, pipe A, stall disabled, not detected)
>(II):                SDVOC: 0x00000000 (disabled, pipe A, stall disabled, not detected)
>(II):              SDVOUDI: 0x00000000
>(II):               DSPARB: 0x00015455
>(II):               DSPFW1: 0x00000000
>(II):               DSPFW2: 0x00000000
>(II):               DSPFW3: 0x00000000
>(II):                 ADPA: 0x80000000 (enabled, pipe A, -hsync, -vsync)
>(II):                 LVDS: 0xc0300300 (enabled, pipe B, 18 bit, 1 channel)
>(II):                 DVOA: 0x00000000 (disabled, pipe A, no stall, -hsync, -vsync)
>(II):                 DVOB: 0x00000000 (disabled, pipe A, no stall, -hsync, -vsync)
>(II):                 DVOC: 0x00000000 (disabled, pipe A, no stall, -hsync, -vsync)
>(II):          DVOA_SRCDIM: 0x00000000
>(II):          DVOB_SRCDIM: 0x00000000
>(II):          DVOC_SRCDIM: 0x00000000
>(II):           PP_CONTROL: 0x00000001 (power target: on)
>(II):            PP_STATUS: 0xc0000008 (on, ready, sequencing idle)
>(II):         PP_ON_DELAYS: 0x01f407d0
>(II):        PP_OFF_DELAYS: 0x01f407d0
>(II):           PP_DIVISOR: 0x0030d304
>(II):         PFIT_CONTROL: 0x80000668
>(II):      PFIT_PGM_RATIOS: 0x00000000
>(II):      PORT_HOTPLUG_EN: 0x00000000
>(II):    PORT_HOTPLUG_STAT: 0x00000000
>(II):             DSPACNTR: 0xd8000000 (enabled, pipe A)
>(II):           DSPASTRIDE: 0x00001000 (4096 bytes)
>(II):              DSPAPOS: 0x00000000 (0, 0)
>(II):             DSPASIZE: 0x02ff03ff (1024, 768)
>(II):             DSPABASE: 0x00c00000
>(II):             DSPASURF: 0x00000000
>(II):          DSPATILEOFF: 0x00000000
>(II):            PIPEACONF: 0x80000000 (enabled, single-wide)
>(II):             PIPEASRC: 0x03ff02ff (1024, 768)
>(II):            PIPEASTAT: 0x00000000 (status:)
>(II):    PIPEA_GMCH_DATA_M: 0x00000000
>(II):    PIPEA_GMCH_DATA_N: 0x00000000
>(II):      PIPEA_DP_LINK_M: 0x00000000
>(II):      PIPEA_DP_LINK_N: 0x00000000
>(II):                 FPA0: 0x0004150d (n = 4, m1 = 21, m2 = 13)
>(II):                 FPA1: 0x00021207 (n = 2, m1 = 18, m2 = 7)
>(II):               DPLL_A: 0x90820000 (enabled, non-dvo, default clock, DAC/serial mode, p1 = 4, p2 = 4)
>(II):            DPLL_A_MD: 0x00000000
>(II):             HTOTAL_A: 0x053f03ff (1024 active, 1344 total)
>(II):             HBLANK_A: 0x053f03ff (1024 start, 1344 end)
>(II):              HSYNC_A: 0x049f0417 (1048 start, 1184 end)
>(II):             VTOTAL_A: 0x032502ff (768 active, 806 total)
>(II):             VBLANK_A: 0x032502ff (768 start, 806 end)
>(II):              VSYNC_A: 0x03080302 (771 start, 777 end)
>(II):            BCLRPAT_A: 0x00000000
>(II):         VSYNCSHIFT_A: 0x00000000
>(II):             DSPBCNTR: 0xd9000000 (enabled, pipe B)
>(II):           DSPBSTRIDE: 0x00001000 (4096 bytes)
>(II):              DSPBPOS: 0x00000000 (0, 0)
>(II):             DSPBSIZE: 0x02ff03ff (1024, 768)
>(II):             DSPBBASE: 0x00c00000
>(II):             DSPBSURF: 0x00000000
>(II):          DSPBTILEOFF: 0x00000000
>(II):            PIPEBCONF: 0x80000000 (enabled, single-wide)
>(II):             PIPEBSRC: 0x03ff02ff (1024, 768)
>(II):            PIPEBSTAT: 0x00000000 (status:)
>(II):    PIPEB_GMCH_DATA_M: 0x00000000
>(II):    PIPEB_GMCH_DATA_N: 0x00000000
>(II):      PIPEB_DP_LINK_M: 0x00000000
>(II):      PIPEB_DP_LINK_N: 0x00000000
>(II):                 FPB0: 0x0004140f (n = 4, m1 = 20, m2 = 15)
>(II):                 FPB1: 0x00021207 (n = 2, m1 = 18, m2 = 7)
>(II):               DPLL_B: 0x90016000 (enabled, non-dvo, spread spectrum clock, LVDS mode, p1 = 1, p2 = 14)
>(II):            DPLL_B_MD: 0x00000000
>(II):             HTOTAL_B: 0x068f0577 (1400 active, 1680 total)
>(II):             HBLANK_B: 0x068f0577 (1400 start, 1680 end)
>(II):              HSYNC_B: 0x0617059f (1440 start, 1560 end)
>(II):             VTOTAL_B: 0x042e0419 (1050 active, 1071 total)
>(II):             VBLANK_B: 0x042e0419 (1050 start, 1071 end)
>(II):              VSYNC_B: 0x0425041c (1053 start, 1062 end)
>(II):            BCLRPAT_B: 0x00000000
>(II):         VSYNCSHIFT_B: 0x00000000
>(II):    VCLK_DIVISOR_VGA0: 0x00021207
>(II):    VCLK_DIVISOR_VGA1: 0x00031406
>(II):        VCLK_POST_DIV: 0x0000888b
>(II):             VGACNTRL: 0x80000000 (disabled)
>(II):               TV_CTL: 0x00000000
>(II):               TV_DAC: 0x00000000
>(II):             TV_CSC_Y: 0x00000000
>(II):            TV_CSC_Y2: 0x00000000
>(II):             TV_CSC_U: 0x00000000
>(II):            TV_CSC_U2: 0x00000000
>(II):             TV_CSC_V: 0x00000000
>(II):            TV_CSC_V2: 0x00000000
>(II):         TV_CLR_KNOBS: 0x00000000
>(II):         TV_CLR_LEVEL: 0x00000000
>(II):           TV_H_CTL_1: 0x00000000
>(II):           TV_H_CTL_2: 0x00000000
>(II):           TV_H_CTL_3: 0x00000000
>(II):           TV_V_CTL_1: 0x00000000
>(II):           TV_V_CTL_2: 0x00000000
>(II):           TV_V_CTL_3: 0x00000000
>(II):           TV_V_CTL_4: 0x00000000
>(II):           TV_V_CTL_5: 0x00000000
>(II):           TV_V_CTL_6: 0x00000000
>(II):           TV_V_CTL_7: 0x00000000
>(II):          TV_SC_CTL_1: 0x00000000
>(II):          TV_SC_CTL_2: 0x00000000
>(II):          TV_SC_CTL_3: 0x00000000
>(II):           TV_WIN_POS: 0x00000000
>(II):          TV_WIN_SIZE: 0x00000000
>(II):      TV_FILTER_CTL_1: 0x00000000
>(II):      TV_FILTER_CTL_2: 0x00000000
>(II):      TV_FILTER_CTL_3: 0x00000000
>(II):        TV_CC_CONTROL: 0x00000000
>(II):           TV_CC_DATA: 0x00000000
>(II):          TV_H_LUMA_0: 0x00000000
>(II):         TV_H_LUMA_59: 0x00000000
>(II):        TV_H_CHROMA_0: 0x00000000
>(II):       TV_H_CHROMA_59: 0x00000000
>(II):         FBC_CFB_BASE: 0x00000000
>(II):          FBC_LL_BASE: 0x00000000
>(II):          FBC_CONTROL: 0x00000000
>(II):          FBC_COMMAND: 0x00000000
>(II):           FBC_STATUS: 0x20000000
>(II):         FBC_CONTROL2: 0x00000000
>(II):        FBC_FENCE_OFF: 0x00000000
>(II):          FBC_MOD_NUM: 0x00000000
>(II):              MI_MODE: 0x00000000
>(II):         MI_ARB_STATE: 0x00000000
>(II):       MI_RDRET_STATE: 0x00000000
>(II):              ECOSKPD: 0x00000307
>(II):                 DP_B: 0x00000000
>(II):       DPB_AUX_CH_CTL: 0x00000000
>(II):     DPB_AUX_CH_DATA1: 0x00000000
>(II):     DPB_AUX_CH_DATA2: 0x00000000
>(II):     DPB_AUX_CH_DATA3: 0x00000000
>(II):     DPB_AUX_CH_DATA4: 0x00000000
>(II):     DPB_AUX_CH_DATA5: 0x00000000
>(II):                 DP_C: 0x00000000
>(II):       DPC_AUX_CH_CTL: 0x00000000
>(II):     DPC_AUX_CH_DATA1: 0x00000000
>(II):     DPC_AUX_CH_DATA2: 0x00000000
>(II):     DPC_AUX_CH_DATA3: 0x00000000
>(II):     DPC_AUX_CH_DATA4: 0x00000000
>(II):     DPC_AUX_CH_DATA5: 0x00000000
>(II):                 DP_D: 0x00000000
>(II):       DPD_AUX_CH_CTL: 0x00000000
>(II):     DPD_AUX_CH_DATA1: 0x00000000
>(II):     DPD_AUX_CH_DATA2: 0x00000000
>(II):     DPD_AUX_CH_DATA3: 0x00000000
>(II):     DPD_AUX_CH_DATA4: 0x00000000
>(II):     DPD_AUX_CH_DATA5: 0x00000000
>(II):             FENCE  0: 0x00000000 (disabled, X tiled,    0 pitch, 0x00000000 - 0x00000000 (0kb))
>(II):             FENCE  1: 0x00000000 (disabled, X tiled,    0 pitch, 0x00000000 - 0x00000000 (0kb))
>(II):             FENCE  2: 0x00000000 (disabled, X tiled,    0 pitch, 0x00000000 - 0x00000000 (0kb))
>(II):             FENCE  3: 0x00c00351 ( enabled, X tiled,   64 pitch, 0x00c00000 - 0x01000000 (4096kb))
>(II):             FENCE  4: 0x01800351 ( enabled, X tiled,   64 pitch, 0x01800000 - 0x01c00000 (4096kb))
>(II):             FENCE  5: 0x01c00351 ( enabled, X tiled,   64 pitch, 0x01c00000 - 0x02000000 (4096kb))
>(II):             FENCE  6: 0x00000000 (disabled, X tiled,    0 pitch, 0x00000000 - 0x00000000 (0kb))
>(II):             FENCE  7: 0x00000000 (disabled, X tiled,    0 pitch, 0x00000000 - 0x00000000 (0kb))
>(II):             FENCE  8: 0x00000000 (disabled, X tiled,    0 pitch, 0x00000000 - 0x00000000 (0kb))
>(II):             FENCE  9: 0x00000000 (disabled, X tiled,    0 pitch, 0x00000000 - 0x00000000 (0kb))
>(II):            FENCE  10: 0x00000000 (disabled, X tiled,    0 pitch, 0x00000000 - 0x00000000 (0kb))
>(II):            FENCE  11: 0x00000000 (disabled, X tiled,    0 pitch, 0x00000000 - 0x00000000 (0kb))
>(II):            FENCE  12: 0x00000000 (disabled, X tiled,    0 pitch, 0x00000000 - 0x00000000 (0kb))
>(II):            FENCE  13: 0x00000000 (disabled, X tiled,    0 pitch, 0x00000000 - 0x00000000 (0kb))
>(II):            FENCE  14: 0x00000000 (disabled, X tiled,    0 pitch, 0x00000000 - 0x00000000 (0kb))
>(II):            FENCE  15: 0x00000000 (disabled, X tiled,    0 pitch, 0x00000000 - 0x00000000 (0kb))
>(II): pipe A dot 65000 n 4 m1 21 m2 13 p1 4 p2 4
>(II): pipe B dot 99785 n 4 m1 20 m2 15 p1 1 p2 14
>(II): DumpRegsEnd

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Attachments on bug 22977: 28054 | 28055 | 29084 | 29124 | 29279 | 29282

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