Attachment 29251 Details for Bug 23626 – Output of RADEON_DEBUG=all with 64bit version progs/samples/stencil

Output of RADEON_DEBUG=all with 64bit version progs/samples/stencil

RADEON_DEBUG_ALL_64bit_stencil.log (text/x-log), 24.67 KB, created by Krzysztof A. Sobiecki on 2009-09-05 07:58:44 UTC

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Filename:

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Creator: Krzysztof A. Sobiecki

Created: 2009-09-05 07:58:44 UTC

Size: 24.67 KB

patch

obsolete

>r300NewTextureObject( 0x16ae180 (target = GL_TEXTURE_2D_ARRAY_EXT) )
>r300NewTextureObject( 0x16ae560 (target = GL_TEXTURE_1D_ARRAY_EXT) )
>r300NewTextureObject( 0x16ae940 (target = GL_TEXTURE_CUBE_MAP) )
>r300NewTextureObject( 0x16aed20 (target = GL_TEXTURE_3D) )
>r300NewTextureObject( 0x16af100 (target = GL_TEXTURE_RECTANGLE_ARB) )
>r300NewTextureObject( 0x16eb940 (target = GL_TEXTURE_2D) )
>r300NewTextureObject( 0x16ebd20 (target = GL_TEXTURE_1D) )
>r300NewTextureObject( 0x1703880 (target = GL_TEXTURE_1D) )
>r300NewTextureObject( 0x1703c60 (target = GL_TEXTURE_2D) )
>r300NewTextureObject( 0x1704040 (target = GL_TEXTURE_3D) )
>r300NewTextureObject( 0x1704420 (target = GL_TEXTURE_CUBE_MAP) )
>r300NewTextureObject( 0x1704800 (target = GL_TEXTURE_RECTANGLE_ARB) )
>r300NewTextureObject( 0x1704be0 (target = GL_TEXTURE_1D_ARRAY_EXT) )
>r300NewTextureObject( 0x1704fc0 (target = GL_TEXTURE_2D_ARRAY_EXT) )
>Using 8 maximum texture units..
>sizeof(drm_r300_cmd_header_t)=4
>sizeof(drm_radeon_cmd_buffer_t)=32
>Allocating 65536 bytes command buffer (max state is 25968 bytes)
>r300ResetHwState
>r300Enable( GL_DEPTH_TEST = GL_FALSE )
>r300Enable( GL_STENCIL_TEST = GL_FALSE )
>r300Enable( GL_ALPHA_TEST = GL_FALSE )
>r300Enable( GL_POLYGON_OFFSET_POINT = GL_FALSE )
>r300Enable( GL_POLYGON_OFFSET_LINE = GL_FALSE )
>r300Enable( GL_POLYGON_OFFSET_FILL = GL_FALSE )
>enter radeon_update_renderbuffers, drawable 0x1a26330
>attaching buffer dri2 depth / stencil buffer, 3, at 9, cpp 4, pitch 1216
>attaching buffer dri2 fake front buffer, 4, at 7, cpp 4, pitch 1216
>radeonMakeCurrent ctx 0x16c1320 dfb 0x1a263d0 rfb 0x1a263d0
>enter radeon_update_renderbuffers, drawable 0x1a26330
>r300Enable( GL_DEPTH_TEST = GL_FALSE )
>r300Enable( GL_STENCIL_TEST = GL_FALSE )
>r300Enable( GL_DEPTH_TEST = GL_FALSE )
>r300Enable( GL_STENCIL_TEST = GL_FALSE )
>End radeonMakeCurrent
>radeonDrawBuffer GL_FRONT
>enter radeon_update_renderbuffers, drawable 0x1a26330
>r300Enable( GL_DEPTH_TEST = GL_FALSE )
>r300Enable( GL_STENCIL_TEST = GL_FALSE )
>enter radeon_update_renderbuffers, drawable 0x1a26330
>r300Enable( GL_DEPTH_TEST = GL_FALSE )
>r300Enable( GL_STENCIL_TEST = GL_FALSE )
>r300Enable( GL_STENCIL_TEST = GL_TRUE )
>enter radeon_update_renderbuffers, drawable 0x1a26330
>radeonMakeCurrent ctx 0x16c1320 dfb 0x1a263d0 rfb 0x1a263d0
>r300Enable( GL_DEPTH_TEST = GL_FALSE )
>r300Enable( GL_STENCIL_TEST = GL_TRUE )
>End radeonMakeCurrent
>radeonFlush 0
>enter radeon_update_renderbuffers, drawable 0x1a26330
>r300Enable( GL_DEPTH_TEST = GL_FALSE )
>r300Enable( GL_STENCIL_TEST = GL_TRUE )
>enter radeon_update_renderbuffers, drawable 0x1a26330
>radeonMakeCurrent ctx 0x16c1320 dfb 0x1a263d0 rfb 0x1a263d0
>r300Enable( GL_DEPTH_TEST = GL_FALSE )
>r300Enable( GL_STENCIL_TEST = GL_TRUE )
>End radeonMakeCurrent
>r300Clear
>r300Enable( GL_STENCIL_TEST = GL_FALSE )
>r300Enable( GL_VERTEX_ARRAY = GL_TRUE )
>r300Enable( GL_COLOR_ARRAY = GL_TRUE )
>r300Enable( GL_STENCIL_TEST = GL_TRUE )
>r300TryDrawPrims: 1 (0-3) cs begin at 0
>Fragment Program: Initial program:
># Fragment Program/Shader
>  0: MOV OUTPUT[1], INPUT[1];
>  1: END
>Fragment Program: After native rewrite:
># Radeon Compiler Program
>  1: MOV OUTPUT[1], INPUT[1];
>Compiler: after NqSSA-DCE:
># Radeon Compiler Program
>  1: MOV OUTPUT[1], INPUT[1];
>Emit paired program
>       RGB:    Src0 = TEMP[0]
>       Alpha:  Src0 = TEMP[0]
>  MAD COLOR.xyz, Src0.xyz, Src0.111, Src0.000
>  MAD COLOR.w, Src0.w, Src0.1, Src0.0
> END
>R500 Fragment Program:
>--------
>0	0:CMN_INST   0x00078005:OUT TEX_WAIT    wmask: NONE omask: ARGB
>	1:RGB_ADDR   0x00000000:Addr0: 0t, Addr1: 0t, Addr2: 0t, srcp:0
>	2:ALPHA_ADDR 0x00000000:Addr0: 0t, Addr1: 0t, Addr2: 0t, srcp:0
>	3 RGB_INST:  0x00db0220:rgb_A_src:0 R/G/B 0 rgb_B_src:0 1/1/1 0
>	4 ALPHA_INST:0x00c0c000:MAD dest:0 alp_A_src:0 A 0 alp_B_src:0 1 0 w:0
>	5 RGBA_INST: 0x20490000:MAD dest:0 rgb_C_src:0 0/0/0 0 alp_C_src:0 0 0
>
>Initial vertex program:
># Vertex Program/Shader
>  0: DP4 OUTPUT[0].x, INPUT[0], STATE[0];
>  1: DP4 OUTPUT[0].y, INPUT[0], STATE[1];
>  2: DP4 OUTPUT[0].z, INPUT[0], STATE[2];
>  3: DP4 OUTPUT[0].w, INPUT[0], STATE[3];
>  4: MOV OUTPUT[1], INPUT[3];
>  5: END
>Vertex program after native rewrite:
># Radeon Compiler Program
>  1: DP4 OUTPUT[0].x, INPUT[0], STATE[0];
>  2: DP4 OUTPUT[0].y, INPUT[0], STATE[1];
>  3: DP4 OUTPUT[0].z, INPUT[0], STATE[2];
>  4: DP4 OUTPUT[0].w, INPUT[0], STATE[3];
>  5: MOV OUTPUT[1], INPUT[3];
>Vertex program after source conflict resolve:
># Radeon Compiler Program
>  1: DP4 OUTPUT[0].x, INPUT[0], STATE[0];
>  2: DP4 OUTPUT[0].y, INPUT[0], STATE[1];
>  3: DP4 OUTPUT[0].z, INPUT[0], STATE[2];
>  4: DP4 OUTPUT[0].w, INPUT[0], STATE[3];
>  5: MOV OUTPUT[1], INPUT[3];
>Vertex program after NQSSADCE:
># Radeon Compiler Program
>  1: DP4 OUTPUT[0].x, INPUT[0], STATE[0];
>  2: DP4 OUTPUT[0].y, INPUT[0], STATE[1];
>  3: DP4 OUTPUT[0].z, INPUT[0], STATE[2];
>  4: DP4 OUTPUT[0].w, INPUT[0], STATE[3];
>  5: MOV OUTPUT[1], INPUT[3];
>Final vertex program code:
>0: op: 0x00100201 dst: 0o op:            VE_DOT_PRODUCT
> src0: 0x00d10001 reg: 0i swiz:  X/ Y/ Z/ W
> src1: 0x00d10002 reg: 0c swiz:  X/ Y/ Z/ W
> src2: 0x01248002 reg: 0c swiz:  0/ 0/ 0/ 0
>1: op: 0x00200201 dst: 0o op:            VE_DOT_PRODUCT
> src0: 0x00d10001 reg: 0i swiz:  X/ Y/ Z/ W
> src1: 0x00d10022 reg: 1c swiz:  X/ Y/ Z/ W
> src2: 0x01248022 reg: 1c swiz:  0/ 0/ 0/ 0
>2: op: 0x00400201 dst: 0o op:            VE_DOT_PRODUCT
> src0: 0x00d10001 reg: 0i swiz:  X/ Y/ Z/ W
> src1: 0x00d10042 reg: 2c swiz:  X/ Y/ Z/ W
> src2: 0x01248042 reg: 2c swiz:  0/ 0/ 0/ 0
>3: op: 0x00800201 dst: 0o op:            VE_DOT_PRODUCT
> src0: 0x00d10001 reg: 0i swiz:  X/ Y/ Z/ W
> src1: 0x00d10062 reg: 3c swiz:  X/ Y/ Z/ W
> src2: 0x01248062 reg: 3c swiz:  0/ 0/ 0/ 0
>4: op: 0x00f02203 dst: 1o op:                    VE_ADD
> src0: 0x00d10021 reg: 1i swiz:  X/ Y/ Z/ W
> src1: 0x01248021 reg: 1i swiz:  0/ 0/ 0/ 0
> src2: 0x01248021 reg: 1i swiz:  0/ 0/ 0/ 0
>r300SetVertexFormat
>mtu=8
>TX_ENABLE: 00000000  last_hw_tmu=-1
>radeonCountStateEmitSize 334
>r300PredictTryDrawPrimsSize: total prediction size is 373.
>r300AllocDmaRegions: count 4 num_attribs 2
>BEGIN_BATCH(4) at 0, from r300EmitCacheFlush:131
>radeonEmitState
>Begin dirty state
>BEGIN_BATCH(2) at 4, from cp_wait:212
>BEGIN_BATCH(2) at 6, from r300_vtbl_pre_emit_atoms:222
>  emit vpt 7/7
>BEGIN_BATCH(7) at 8, from radeon_emit_atom:1038
>  emit vap_cntl 4/4
>BEGIN_BATCH(4) at 15, from radeon_emit_atom:1038
>  emit vte 3/3
>BEGIN_BATCH(3) at 19, from radeon_emit_atom:1038
>  emit vap_vf_max_vtx_indx 3/3
>BEGIN_BATCH(3) at 22, from radeon_emit_atom:1038
>  emit vap_cntl_status 2/2
>BEGIN_BATCH(2) at 25, from radeon_emit_atom:1038
>  emit vir[0] 3/9
>BEGIN_BATCH(3) at 27, from radeon_emit_atom:1038
>  emit vir[1] 3/9
>BEGIN_BATCH(3) at 30, from radeon_emit_atom:1038
>  emit vic 3/3
>BEGIN_BATCH(3) at 33, from radeon_emit_atom:1038
>  emit vap_psc_sgn_norm_cntl 2/2
>BEGIN_BATCH(2) at 36, from radeon_emit_atom:1038
>  emit vap_clip_cntl 2/2
>BEGIN_BATCH(2) at 38, from radeon_emit_atom:1038
>  emit vap_clip 5/5
>BEGIN_BATCH(5) at 40, from radeon_emit_atom:1038
>  emit vap_pvs_vtx_timeout_reg 2/2
>BEGIN_BATCH(2) at 45, from radeon_emit_atom:1038
>  emit vof 3/3
>BEGIN_BATCH(3) at 47, from radeon_emit_atom:1038
>  emit pvs 4/4
>BEGIN_BATCH(4) at 50, from radeon_emit_atom:1038
>  emit gb_enable 2/2
>BEGIN_BATCH(2) at 54, from radeon_emit_atom:1038
>  skip state gb_misc
>  emit gb_misc2 3/3
>BEGIN_BATCH(3) at 56, from radeon_emit_atom:1038
>  emit txe 2/2
>BEGIN_BATCH(2) at 59, from radeon_emit_atom:1038
>  emit ga_point_s0 5/5
>BEGIN_BATCH(5) at 61, from radeon_emit_atom:1038
>  emit ga_triangle_stipple 2/2
>BEGIN_BATCH(2) at 66, from radeon_emit_atom:1038
>  emit ps 2/2
>BEGIN_BATCH(2) at 68, from radeon_emit_atom:1038
>  emit ga_point_minmax 4/4
>BEGIN_BATCH(4) at 70, from radeon_emit_atom:1038
>  emit lcntl 2/2
>BEGIN_BATCH(2) at 74, from radeon_emit_atom:1038
>  emit ga_line_stipple 4/4
>BEGIN_BATCH(4) at 76, from radeon_emit_atom:1038
>  skip state shade
>  emit shade2 4/4
>BEGIN_BATCH(4) at 80, from radeon_emit_atom:1038
>  emit polygon_mode 4/4
>BEGIN_BATCH(4) at 84, from radeon_emit_atom:1038
>  emit fogp 3/3
>BEGIN_BATCH(3) at 88, from radeon_emit_atom:1038
>  emit zbias_cntl 2/2
>BEGIN_BATCH(2) at 91, from radeon_emit_atom:1038
>  emit zbs 5/5
>BEGIN_BATCH(5) at 93, from radeon_emit_atom:1038
>  emit occlusion_cntl 2/2
>BEGIN_BATCH(2) at 98, from radeon_emit_atom:1038
>  emit cul 2/2
>BEGIN_BATCH(2) at 100, from radeon_emit_atom:1038
>  emit su_depth_scale 3/3
>BEGIN_BATCH(3) at 102, from radeon_emit_atom:1038
>  emit rc 3/3
>BEGIN_BATCH(3) at 105, from radeon_emit_atom:1038
>  emit ri 2/17
>BEGIN_BATCH(2) at 108, from radeon_emit_atom:1038
>  emit rr 2/9
>BEGIN_BATCH(2) at 110, from radeon_emit_atom:1038
>  emit sc_hyperz 3/3
>BEGIN_BATCH(3) at 112, from radeon_emit_atom:1038
>  emit sc_screendoor 2/2
>BEGIN_BATCH(2) at 115, from radeon_emit_atom:1038
>  emit us_out_fmt 6/6
>BEGIN_BATCH(6) at 117, from radeon_emit_atom:1038
>  emit fp 9/9
>BEGIN_BATCH(9) at 123, from radeon_emit_atom:1038
>  emit r500fp 9/3073
>BEGIN_BATCH(9) at 132, from emit_r500fp:132
>  skip state r500fp_const
>  emit fogs 2/2
>BEGIN_BATCH(2) at 141, from radeon_emit_atom:1038
>  emit fogc 4/4
>BEGIN_BATCH(4) at 143, from radeon_emit_atom:1038
>  emit at 3/3
>BEGIN_BATCH(3) at 147, from radeon_emit_atom:1038
>  emit fg_depth_src 2/2
>BEGIN_BATCH(2) at 150, from radeon_emit_atom:1038
>  emit rb3d_cctl 2/2
>BEGIN_BATCH(2) at 152, from radeon_emit_atom:1038
>  emit bld 3/3
>BEGIN_BATCH(3) at 154, from radeon_emit_atom:1038
>  emit cmk 2/2
>BEGIN_BATCH(2) at 157, from radeon_emit_atom:1038
>  emit blend_color 3/3
>BEGIN_BATCH(3) at 159, from radeon_emit_atom:1038
>  emit rop 2/2
>BEGIN_BATCH(2) at 162, from radeon_emit_atom:1038
>  emit cb 27/4
>rrb is 0x1a26850 0 300x300
>BEGIN_BATCH(8) at 164, from emit_cb_offset:299
>BEGIN_BATCH(3) at 172, from emit_cb_offset:310
>BEGIN_BATCH(16) at 175, from emit_cb_offset:316
>  emit rb3d_dither_ctl 10/10
>BEGIN_BATCH(10) at 191, from radeon_emit_atom:1038
>  emit rb3d_aaresolve_ctl 2/2
>BEGIN_BATCH(2) at 201, from radeon_emit_atom:1038
>  emit rb3d_discard_src_pixel_lte_threshold 3/3
>BEGIN_BATCH(3) at 203, from radeon_emit_atom:1038
>  emit zs 4/4
>BEGIN_BATCH(4) at 206, from radeon_emit_atom:1038
>  emit zstencil_format 5/5
>BEGIN_BATCH(5) at 210, from emit_zstencil_format:411
>  emit zb 8/3
>BEGIN_BATCH(8) at 215, from emit_zb_offset:383
>  emit zb_depthclearvalue 2/2
>BEGIN_BATCH(2) at 223, from radeon_emit_atom:1038
>  emit zb_zmask 3/3
>BEGIN_BATCH(3) at 225, from radeon_emit_atom:1038
>  emit zb_hiz_offset 2/2
>BEGIN_BATCH(2) at 228, from radeon_emit_atom:1038
>  emit zb_hiz_pitch 2/2
>BEGIN_BATCH(2) at 230, from radeon_emit_atom:1038
>  emit vap_flush 10/10
>BEGIN_BATCH(10) at 232, from radeon_emit_atom:1038
>  emit vpi 25/1025
>BEGIN_BATCH(25) at 242, from emit_vpu:103
>  emit vpp 21/1025
>BEGIN_BATCH(21) at 267, from emit_vpu:103
>  skip state vps
>  emit vpucp[i] 9/5
>BEGIN_BATCH(9) at 288, from emit_vpu:103
>  emit vpucp[i] 9/5
>BEGIN_BATCH(9) at 297, from emit_vpu:103
>  emit vpucp[i] 9/5
>BEGIN_BATCH(9) at 306, from emit_vpu:103
>  emit vpucp[i] 9/5
>BEGIN_BATCH(9) at 315, from emit_vpu:103
>  emit vpucp[i] 9/5
>BEGIN_BATCH(9) at 324, from emit_vpu:103
>  emit vpucp[i] 9/5
>BEGIN_BATCH(9) at 333, from emit_vpu:103
>  skip state tex.filter
>  skip state tex.filter_1
>  skip state tex.size
>  skip state tex.format
>  skip state tex.pitch
>  skip state tex.offset
>  skip state tex.chroma_key
>  skip state tex.border_color
>  skip state queryobj
>BEGIN_BATCH(3) at 342, from r300_emit_scissor:243
>r300EmitAOS: nr=2, ofs=0x00000000
>BEGIN_BATCH(10) at 345, from r300EmitAOS:269
>BEGIN_BATCH(3) at 354, from r300_emit_scissor:243
>BEGIN_BATCH(3) at 357, from r300FireAOS:326
>BEGIN_BATCH(4) at 359, from r300EmitCacheFlush:131
>r300FreeData
>r300TryDrawPrims: 1 (0-3) cs ending at 363
>WARNING! Falling back to software for two-sided stencil
>radeonFlush 363
>radeonEmitState
>radeonReleaseDmaRegions: free 0, wait 0, reserved 0, minimum_size: 65536
>rcommonFlushCmdBufLocked from radeonFlush - 1 cliprects
>r300TryDrawPrims: 1 (0-2) cs begin at 0
>Fragment Program: Initial program:
># Fragment Program/Shader
>  0: MOV OUTPUT[1], STATE[0];
>  1: END
>Fragment Program: After native rewrite:
># Radeon Compiler Program
>  1: MOV OUTPUT[1], STATE[0];
>Compiler: after NqSSA-DCE:
># Radeon Compiler Program
>  1: MOV OUTPUT[1], STATE[0];
>Emit paired program
>       RGB:    Src0 = CNST[0]
>       Alpha:  Src0 = CNST[0]
>  MAD COLOR.xyz, Src0.xyz, Src0.111, Src0.000
>  MAD COLOR.w, Src0.w, Src0.1, Src0.0
> END
>R500 Fragment Program:
>--------
>0	0:CMN_INST   0x00078005:OUT TEX_WAIT    wmask: NONE omask: ARGB
>	1:RGB_ADDR   0x00000100:Addr0: 0c, Addr1: 0t, Addr2: 0t, srcp:0
>	2:ALPHA_ADDR 0x00000100:Addr0: 0c, Addr1: 0t, Addr2: 0t, srcp:0
>	3 RGB_INST:  0x00db0220:rgb_A_src:0 R/G/B 0 rgb_B_src:0 1/1/1 0
>	4 ALPHA_INST:0x00c0c000:MAD dest:0 alp_A_src:0 A 0 alp_B_src:0 1 0 w:0
>	5 RGBA_INST: 0x20490000:MAD dest:0 rgb_C_src:0 0/0/0 0 alp_C_src:0 0 0
>
>Initial vertex program:
># Vertex Program/Shader
>  0: DP4 OUTPUT[0].x, INPUT[0], STATE[0];
>  1: DP4 OUTPUT[0].y, INPUT[0], STATE[1];
>  2: DP4 OUTPUT[0].z, INPUT[0], STATE[2];
>  3: DP4 OUTPUT[0].w, INPUT[0], STATE[3];
>  4: END
>Vertex program after native rewrite:
># Radeon Compiler Program
>  1: DP4 OUTPUT[0].x, INPUT[0], STATE[0];
>  2: DP4 OUTPUT[0].y, INPUT[0], STATE[1];
>  3: DP4 OUTPUT[0].z, INPUT[0], STATE[2];
>  4: DP4 OUTPUT[0].w, INPUT[0], STATE[3];
>Vertex program after source conflict resolve:
># Radeon Compiler Program
>  1: DP4 OUTPUT[0].x, INPUT[0], STATE[0];
>  2: DP4 OUTPUT[0].y, INPUT[0], STATE[1];
>  3: DP4 OUTPUT[0].z, INPUT[0], STATE[2];
>  4: DP4 OUTPUT[0].w, INPUT[0], STATE[3];
>Vertex program after NQSSADCE:
># Radeon Compiler Program
>  1: DP4 OUTPUT[0].x, INPUT[0], STATE[0];
>  2: DP4 OUTPUT[0].y, INPUT[0], STATE[1];
>  3: DP4 OUTPUT[0].z, INPUT[0], STATE[2];
>  4: DP4 OUTPUT[0].w, INPUT[0], STATE[3];
>Final vertex program code:
>0: op: 0x00100201 dst: 0o op:            VE_DOT_PRODUCT
> src0: 0x00d10001 reg: 0i swiz:  X/ Y/ Z/ W
> src1: 0x00d10002 reg: 0c swiz:  X/ Y/ Z/ W
> src2: 0x01248002 reg: 0c swiz:  0/ 0/ 0/ 0
>1: op: 0x00200201 dst: 0o op:            VE_DOT_PRODUCT
> src0: 0x00d10001 reg: 0i swiz:  X/ Y/ Z/ W
> src1: 0x00d10022 reg: 1c swiz:  X/ Y/ Z/ W
> src2: 0x01248022 reg: 1c swiz:  0/ 0/ 0/ 0
>2: op: 0x00400201 dst: 0o op:            VE_DOT_PRODUCT
> src0: 0x00d10001 reg: 0i swiz:  X/ Y/ Z/ W
> src1: 0x00d10042 reg: 2c swiz:  X/ Y/ Z/ W
> src2: 0x01248042 reg: 2c swiz:  0/ 0/ 0/ 0
>3: op: 0x00800201 dst: 0o op:            VE_DOT_PRODUCT
> src0: 0x00d10001 reg: 0i swiz:  X/ Y/ Z/ W
> src1: 0x00d10062 reg: 3c swiz:  X/ Y/ Z/ W
> src2: 0x01248062 reg: 3c swiz:  0/ 0/ 0/ 0
>r300SetVertexFormat
>mtu=8
>TX_ENABLE: 00000000  last_hw_tmu=-1
>radeonCountStateEmitSize 337
>r300PredictTryDrawPrimsSize: total prediction size is 373.
>r300AllocDmaRegions: count 3 num_attribs 1
>radeonAllocDmaRegion 36
>radeonRefillCurrentDmaRegion size 36 minimum_size 65536
>radeonEmitVec12 count 3 stride 12 out 0x7fd6f803c000 data 0x1711040
>BEGIN_BATCH(4) at 0, from r300EmitCacheFlush:131
>radeonEmitState
>Begin dirty state
>BEGIN_BATCH(2) at 4, from cp_wait:212
>BEGIN_BATCH(2) at 6, from r300_vtbl_pre_emit_atoms:222
>  emit vpt 7/7
>BEGIN_BATCH(7) at 8, from radeon_emit_atom:1038
>  emit vap_cntl 4/4
>BEGIN_BATCH(4) at 15, from radeon_emit_atom:1038
>  emit vte 3/3
>BEGIN_BATCH(3) at 19, from radeon_emit_atom:1038
>  emit vap_vf_max_vtx_indx 3/3
>BEGIN_BATCH(3) at 22, from radeon_emit_atom:1038
>  emit vap_cntl_status 2/2
>BEGIN_BATCH(2) at 25, from radeon_emit_atom:1038
>  emit vir[0] 3/9
>BEGIN_BATCH(3) at 27, from radeon_emit_atom:1038
>  emit vir[1] 3/9
>BEGIN_BATCH(3) at 30, from radeon_emit_atom:1038
>  emit vic 3/3
>BEGIN_BATCH(3) at 33, from radeon_emit_atom:1038
>  emit vap_psc_sgn_norm_cntl 2/2
>BEGIN_BATCH(2) at 36, from radeon_emit_atom:1038
>  emit vap_clip_cntl 2/2
>BEGIN_BATCH(2) at 38, from radeon_emit_atom:1038
>  emit vap_clip 5/5
>BEGIN_BATCH(5) at 40, from radeon_emit_atom:1038
>  emit vap_pvs_vtx_timeout_reg 2/2
>BEGIN_BATCH(2) at 45, from radeon_emit_atom:1038
>  emit vof 3/3
>BEGIN_BATCH(3) at 47, from radeon_emit_atom:1038
>  emit pvs 4/4
>BEGIN_BATCH(4) at 50, from radeon_emit_atom:1038
>  emit gb_enable 2/2
>BEGIN_BATCH(2) at 54, from radeon_emit_atom:1038
>  skip state gb_misc
>  emit gb_misc2 3/3
>BEGIN_BATCH(3) at 56, from radeon_emit_atom:1038
>  emit txe 2/2
>BEGIN_BATCH(2) at 59, from radeon_emit_atom:1038
>  emit ga_point_s0 5/5
>BEGIN_BATCH(5) at 61, from radeon_emit_atom:1038
>  emit ga_triangle_stipple 2/2
>BEGIN_BATCH(2) at 66, from radeon_emit_atom:1038
>  emit ps 2/2
>BEGIN_BATCH(2) at 68, from radeon_emit_atom:1038
>  emit ga_point_minmax 4/4
>BEGIN_BATCH(4) at 70, from radeon_emit_atom:1038
>  emit lcntl 2/2
>BEGIN_BATCH(2) at 74, from radeon_emit_atom:1038
>  emit ga_line_stipple 4/4
>BEGIN_BATCH(4) at 76, from radeon_emit_atom:1038
>  skip state shade
>  emit shade2 4/4
>BEGIN_BATCH(4) at 80, from radeon_emit_atom:1038
>  emit polygon_mode 4/4
>BEGIN_BATCH(4) at 84, from radeon_emit_atom:1038
>  emit fogp 3/3
>BEGIN_BATCH(3) at 88, from radeon_emit_atom:1038
>  emit zbias_cntl 2/2
>BEGIN_BATCH(2) at 91, from radeon_emit_atom:1038
>  emit zbs 5/5
>BEGIN_BATCH(5) at 93, from radeon_emit_atom:1038
>  emit occlusion_cntl 2/2
>BEGIN_BATCH(2) at 98, from radeon_emit_atom:1038
>  emit cul 2/2
>BEGIN_BATCH(2) at 100, from radeon_emit_atom:1038
>  emit su_depth_scale 3/3
>BEGIN_BATCH(3) at 102, from radeon_emit_atom:1038
>  emit rc 3/3
>BEGIN_BATCH(3) at 105, from radeon_emit_atom:1038
>  emit ri 2/17
>BEGIN_BATCH(2) at 108, from radeon_emit_atom:1038
>  emit rr 2/9
>BEGIN_BATCH(2) at 110, from radeon_emit_atom:1038
>  emit sc_hyperz 3/3
>BEGIN_BATCH(3) at 112, from radeon_emit_atom:1038
>  emit sc_screendoor 2/2
>BEGIN_BATCH(2) at 115, from radeon_emit_atom:1038
>  emit us_out_fmt 6/6
>BEGIN_BATCH(6) at 117, from radeon_emit_atom:1038
>  emit fp 9/9
>BEGIN_BATCH(9) at 123, from radeon_emit_atom:1038
>  emit r500fp 9/3073
>BEGIN_BATCH(9) at 132, from emit_r500fp:132
>  emit r500fp_const 7/1025
>BEGIN_BATCH(7) at 141, from emit_r500fp:132
>  emit fogs 2/2
>BEGIN_BATCH(2) at 148, from radeon_emit_atom:1038
>  emit fogc 4/4
>BEGIN_BATCH(4) at 150, from radeon_emit_atom:1038
>  emit at 3/3
>BEGIN_BATCH(3) at 154, from radeon_emit_atom:1038
>  emit fg_depth_src 2/2
>BEGIN_BATCH(2) at 157, from radeon_emit_atom:1038
>  emit rb3d_cctl 2/2
>BEGIN_BATCH(2) at 159, from radeon_emit_atom:1038
>  emit bld 3/3
>BEGIN_BATCH(3) at 161, from radeon_emit_atom:1038
>  emit cmk 2/2
>BEGIN_BATCH(2) at 164, from radeon_emit_atom:1038
>  emit blend_color 3/3
>BEGIN_BATCH(3) at 166, from radeon_emit_atom:1038
>  emit rop 2/2
>BEGIN_BATCH(2) at 169, from radeon_emit_atom:1038
>  emit cb 27/4
>rrb is 0x1a26850 0 300x300
>BEGIN_BATCH(8) at 171, from emit_cb_offset:299
>BEGIN_BATCH(3) at 179, from emit_cb_offset:310
>BEGIN_BATCH(16) at 182, from emit_cb_offset:316
>  emit rb3d_dither_ctl 10/10
>BEGIN_BATCH(10) at 198, from radeon_emit_atom:1038
>  emit rb3d_aaresolve_ctl 2/2
>BEGIN_BATCH(2) at 208, from radeon_emit_atom:1038
>  emit rb3d_discard_src_pixel_lte_threshold 3/3
>BEGIN_BATCH(3) at 210, from radeon_emit_atom:1038
>  emit zs 4/4
>BEGIN_BATCH(4) at 213, from radeon_emit_atom:1038
>  emit zstencil_format 5/5
>BEGIN_BATCH(5) at 217, from emit_zstencil_format:411
>  emit zb 8/3
>BEGIN_BATCH(8) at 222, from emit_zb_offset:383
>  emit zb_depthclearvalue 2/2
>BEGIN_BATCH(2) at 230, from radeon_emit_atom:1038
>  emit zb_zmask 3/3
>BEGIN_BATCH(3) at 232, from radeon_emit_atom:1038
>  emit zb_hiz_offset 2/2
>BEGIN_BATCH(2) at 235, from radeon_emit_atom:1038
>  emit zb_hiz_pitch 2/2
>BEGIN_BATCH(2) at 237, from radeon_emit_atom:1038
>  emit vap_flush 10/10
>BEGIN_BATCH(10) at 239, from radeon_emit_atom:1038
>  emit vpi 21/1025
>BEGIN_BATCH(21) at 249, from emit_vpu:103
>  emit vpp 21/1025
>BEGIN_BATCH(21) at 270, from emit_vpu:103
>  skip state vps
>  emit vpucp[i] 9/5
>BEGIN_BATCH(9) at 291, from emit_vpu:103
>  emit vpucp[i] 9/5
>BEGIN_BATCH(9) at 300, from emit_vpu:103
>  emit vpucp[i] 9/5
>BEGIN_BATCH(9) at 309, from emit_vpu:103
>  emit vpucp[i] 9/5
>BEGIN_BATCH(9) at 318, from emit_vpu:103
>  emit vpucp[i] 9/5
>BEGIN_BATCH(9) at 327, from emit_vpu:103
>  emit vpucp[i] 9/5
>BEGIN_BATCH(9) at 336, from emit_vpu:103
>  skip state tex.filter
>  skip state tex.filter_1
>  skip state tex.size
>  skip state tex.format
>  skip state tex.pitch
>  skip state tex.offset
>  skip state tex.chroma_key
>  skip state tex.border_color
>  skip state queryobj
>BEGIN_BATCH(3) at 345, from r300_emit_scissor:243
>r300EmitAOS: nr=1, ofs=0x00000000
>BEGIN_BATCH(7) at 348, from r300EmitAOS:269
>BEGIN_BATCH(3) at 354, from r300_emit_scissor:243
>BEGIN_BATCH(3) at 357, from r300FireAOS:326
>BEGIN_BATCH(4) at 359, from r300EmitCacheFlush:131
>r300FreeData
>r300TryDrawPrims: 1 (0-2) cs ending at 363
>r300TryDrawPrims: 1 (0-3) cs begin at 363
>r300SetVertexFormat
>mtu=8
>TX_ENABLE: 00000000  last_hw_tmu=-1
>radeonCountStateEmitSize 110
>r300PredictTryDrawPrimsSize: total prediction size is 146.
>r300AllocDmaRegions: count 4 num_attribs 1
>radeonAllocDmaRegion 48
>radeonEmitVec12 count 4 stride 12 out 0x7fd6f803c040 data 0x1711040
>BEGIN_BATCH(4) at 363, from r300EmitCacheFlush:131
>radeonEmitState
>Begin dirty state
>BEGIN_BATCH(2) at 367, from cp_wait:212
>BEGIN_BATCH(2) at 369, from r300_vtbl_pre_emit_atoms:222
>  emit vap_cntl 4/4
>BEGIN_BATCH(4) at 371, from radeon_emit_atom:1038
>  emit vir[0] 3/9
>BEGIN_BATCH(3) at 375, from radeon_emit_atom:1038
>  emit vir[1] 3/9
>BEGIN_BATCH(3) at 378, from radeon_emit_atom:1038
>  emit vic 3/3
>BEGIN_BATCH(3) at 381, from radeon_emit_atom:1038
>  emit vof 3/3
>BEGIN_BATCH(3) at 384, from radeon_emit_atom:1038
>  emit pvs 4/4
>BEGIN_BATCH(4) at 387, from radeon_emit_atom:1038
>  emit txe 2/2
>BEGIN_BATCH(2) at 391, from radeon_emit_atom:1038
>  emit rc 3/3
>BEGIN_BATCH(3) at 393, from radeon_emit_atom:1038
>  emit ri 2/17
>BEGIN_BATCH(2) at 396, from radeon_emit_atom:1038
>  emit rr 2/9
>BEGIN_BATCH(2) at 398, from radeon_emit_atom:1038
>  emit fp 9/9
>BEGIN_BATCH(9) at 400, from radeon_emit_atom:1038
>  emit r500fp 9/3073
>BEGIN_BATCH(9) at 409, from emit_r500fp:132
>  emit r500fp_const 7/1025
>BEGIN_BATCH(7) at 418, from emit_r500fp:132
>  emit zs 4/4
>BEGIN_BATCH(4) at 425, from radeon_emit_atom:1038
>  emit vap_flush 10/10
>BEGIN_BATCH(10) at 429, from radeon_emit_atom:1038
>  emit vpi 21/1025
>BEGIN_BATCH(21) at 439, from emit_vpu:103
>  emit vpp 21/1025
>BEGIN_BATCH(21) at 460, from emit_vpu:103
>  skip state tex.filter
>  skip state tex.filter_1
>  skip state tex.size
>  skip state tex.format
>  skip state tex.pitch
>  skip state tex.offset
>  skip state tex.chroma_key
>  skip state tex.border_color
>BEGIN_BATCH(3) at 481, from r300_emit_scissor:243
>r300EmitAOS: nr=1, ofs=0x00000000
>BEGIN_BATCH(7) at 484, from r300EmitAOS:269
>BEGIN_BATCH(3) at 490, from r300_emit_scissor:243
>BEGIN_BATCH(3) at 493, from r300FireAOS:326
>BEGIN_BATCH(4) at 495, from r300EmitCacheFlush:131
>r300FreeData
>r300TryDrawPrims: 1 (0-3) cs ending at 499
>r300TryDrawPrims: 1 (0-3) cs begin at 499
>r300SetVertexFormat
>mtu=8
>TX_ENABLE: 00000000  last_hw_tmu=-1
>radeonCountStateEmitSize 110
>r300PredictTryDrawPrimsSize: total prediction size is 146.
>r300AllocDmaRegions: count 4 num_attribs 1
>radeonAllocDmaRegion 48
>radeonEmitVec12 count 4 stride 12 out 0x7fd6f803c080 data 0x1711040
>BEGIN_BATCH(4) at 499, from r300EmitCacheFlush:131
>radeonEmitState
>Begin dirty state
>BEGIN_BATCH(2) at 503, from cp_wait:212
>BEGIN_BATCH(2) at 505, from r300_vtbl_pre_emit_atoms:222
>  emit vap_cntl 4/4
>BEGIN_BATCH(4) at 507, from radeon_emit_atom:1038
>  emit vir[0] 3/9
>BEGIN_BATCH(3) at 511, from radeon_emit_atom:1038
>  emit vir[1] 3/9
>BEGIN_BATCH(3) at 514, from radeon_emit_atom:1038
>  emit vic 3/3
>BEGIN_BATCH(3) at 517, from radeon_emit_atom:1038
>  emit vof 3/3
>BEGIN_BATCH(3) at 520, from radeon_emit_atom:1038
>  emit pvs 4/4
>BEGIN_BATCH(4) at 523, from radeon_emit_atom:1038
>  emit txe 2/2
>BEGIN_BATCH(2) at 527, from radeon_emit_atom:1038
>  emit rc 3/3
>BEGIN_BATCH(3) at 529, from radeon_emit_atom:1038
>  emit ri 2/17
>BEGIN_BATCH(2) at 532, from radeon_emit_atom:1038
>  emit rr 2/9
>BEGIN_BATCH(2) at 534, from radeon_emit_atom:1038
>  emit fp 9/9
>BEGIN_BATCH(9) at 536, from radeon_emit_atom:1038
>  emit r500fp 9/3073
>BEGIN_BATCH(9) at 545, from emit_r500fp:132
>  emit r500fp_const 7/1025
>BEGIN_BATCH(7) at 554, from emit_r500fp:132
>  emit zs 4/4
>BEGIN_BATCH(4) at 561, from radeon_emit_atom:1038
>  emit vap_flush 10/10
>BEGIN_BATCH(10) at 565, from radeon_emit_atom:1038
>  emit vpi 21/1025
>BEGIN_BATCH(21) at 575, from emit_vpu:103
>  emit vpp 21/1025
>BEGIN_BATCH(21) at 596, from emit_vpu:103
>  skip state tex.filter
>  skip state tex.filter_1
>  skip state tex.size
>  skip state tex.format
>  skip state tex.pitch
>  skip state tex.offset
>  skip state tex.chroma_key
>  skip state tex.border_color
>BEGIN_BATCH(3) at 617, from r300_emit_scissor:243
>r300EmitAOS: nr=1, ofs=0x00000000
>BEGIN_BATCH(7) at 620, from r300EmitAOS:269
>BEGIN_BATCH(3) at 626, from r300_emit_scissor:243
>BEGIN_BATCH(3) at 629, from r300FireAOS:326
>BEGIN_BATCH(4) at 631, from r300EmitCacheFlush:131
>r300FreeData
>r300TryDrawPrims: 1 (0-3) cs ending at 635
>radeonFlush 635
>radeonEmitState
>radeonReleaseDmaRegions: free 0, wait 0, reserved 1, minimum_size: 65536
>rcommonFlushCmdBufLocked from radeonFlush - 1 cliprects
>enter radeon_update_renderbuffers, drawable 0x1a26330
>radeonMakeCurrent ctx 0x16c1320 dfb 0x1a263d0 rfb 0x1a263d0
>r300Enable( GL_DEPTH_TEST = GL_FALSE )
>r300Enable( GL_STENCIL_TEST = GL_TRUE )
>End radeonMakeCurrent

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Attachments on bug 23626: 29068 | 29069 | 29070 | 29071 | 29072 | 29251 | 29511

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