Attachment 30390 Details for Bug 24522 – Xorg log - system w/o KMS

Xorg log - system w/o KMS

Xorg.0.log.nokms (text/plain), 75.28 KB, created by Marius Orcsik on 2009-10-14 06:32:17 UTC

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Creator: Marius Orcsik

Created: 2009-10-14 06:32:17 UTC

Size: 75.28 KB

patch

obsolete

>
>This is a pre-release version of the X server from The X.Org Foundation.
>It is not supported in any way.
>Bugs may be filed in the bugzilla at http://bugs.freedesktop.org/.
>Select the "xorg" product for bugs you find in this release.
>Before reporting bugs in pre-release versions please check the
>latest version in the X.Org Foundation git repository.
>See http://wiki.x.org/wiki/GitPage for git access instructions.
>
>X.Org X Server 1.7.0.901 (1.7.1 RC 1)
>Release Date: 2009-10-12
>X Protocol Version 11, Revision 0
>Build Operating System: Linux 2.6.31-ARCH i686 
>Current Operating System: Linux COST-D-040 2.6.31-ARCH #1 SMP PREEMPT Tue Oct 13 13:36:23 CEST 2009 i686
>Kernel command line: BOOT_IMAGE=/vmlinuz26 root=/dev/disk/by-uuid/c68c3820-a2ff-433d-b169-245b87a512df resume=/dev/disk/by-uuid/784a10ff-bd34-4171-8ae1-a5b6b1abb15d
>Build Date: 13 October 2009  10:20:35PM
> 
>Current version of pixman: 0.16.2
>	Before reporting problems, check http://wiki.x.org
>	to make sure that you have the latest version.
>Markers: (--) probed, (**) from config file, (==) default setting,
>	(++) from command line, (!!) notice, (II) informational,
>	(WW) warning, (EE) error, (NI) not implemented, (??) unknown.
>(==) Log file: "/var/log/Xorg.0.log", Time: Wed Oct 14 15:13:57 2009
>(==) Using config file: "/etc/X11/xorg.conf"
>(==) No Layout section.  Using the first Screen section.
>(**) |-->Screen "Screen[0]" (0)
>(**) |   |-->Monitor "Monitor[0]"
>(**) |   |-->Device "Device[0]"
>(==) Automatically adding devices
>(==) Automatically enabling devices
>(==) FontPath set to:
>	/usr/share/fonts/misc,
>	/usr/share/fonts/100dpi:unscaled,
>	/usr/share/fonts/75dpi:unscaled,
>	/usr/share/fonts/TTF,
>	/usr/share/fonts/Type1
>(==) ModulePath set to "/usr/lib/xorg/modules"
>(II) Cannot locate a core pointer device.
>(II) Cannot locate a core keyboard device.
>(II) The server relies on HAL to provide the list of input devices.
>	If no devices become available, reconfigure HAL or disable AllowEmptyInput.
>(II) Loader magic: 0x81e5ec0
>(II) Module ABI versions:
>	X.Org ANSI C Emulation: 0.4
>	X.Org Video Driver: 6.0
>	X.Org XInput driver : 7.0
>	X.Org Server Extension : 2.0
>(++) using VT number 7
>
>(--) PCI:*(0:0:2:0) 8086:29b2:17aa:3037 Intel Corporation 82Q35 Express Integrated Graphics Controller rev 2, Mem @ 0xd0100000/524288, 0xc0000000/268435456, 0xd0000000/1048576, I/O @ 0x00001c70/8
>(--) PCI: (0:0:2:1) 8086:29b3:17aa:3037 Intel Corporation 82Q35 Express Integrated Graphics Controller rev 2, Mem @ 0x80000000/524288
>(WW) Open ACPI failed (/var/run/acpid.socket) (No such file or directory)
>(II) LoadModule: "extmod"
>(II) Loading /usr/lib/xorg/modules/extensions/libextmod.so
>(II) Module extmod: vendor="X.Org Foundation"
>	compiled for 1.7.0.901, module version = 1.0.0
>	Module class: X.Org Server Extension
>	ABI class: X.Org Server Extension, version 2.0
>(II) Loading extension MIT-SCREEN-SAVER
>(II) Loading extension XFree86-VidModeExtension
>(II) Loading extension XFree86-DGA
>(II) Loading extension DPMS
>(II) Loading extension XVideo
>(II) Loading extension XVideo-MotionCompensation
>(II) Loading extension X-Resource
>(II) LoadModule: "dbe"
>(II) Loading /usr/lib/xorg/modules/extensions/libdbe.so
>(II) Module dbe: vendor="X.Org Foundation"
>	compiled for 1.7.0.901, module version = 1.0.0
>	Module class: X.Org Server Extension
>	ABI class: X.Org Server Extension, version 2.0
>(II) Loading extension DOUBLE-BUFFER
>(II) LoadModule: "glx"
>(II) Loading /usr/lib/xorg/modules/extensions/libglx.so
>(II) Module glx: vendor="X.Org Foundation"
>	compiled for 1.7.0.901, module version = 1.0.0
>	ABI class: X.Org Server Extension, version 2.0
>(==) AIGLX enabled
>(II) Loading extension GLX
>(II) LoadModule: "record"
>(II) Loading /usr/lib/xorg/modules/extensions/librecord.so
>(II) Module record: vendor="X.Org Foundation"
>	compiled for 1.7.0.901, module version = 1.13.0
>	Module class: X.Org Server Extension
>	ABI class: X.Org Server Extension, version 2.0
>(II) Loading extension RECORD
>(II) LoadModule: "dri"
>(II) Loading /usr/lib/xorg/modules/extensions/libdri.so
>(II) Module dri: vendor="X.Org Foundation"
>	compiled for 1.7.0.901, module version = 1.0.0
>	ABI class: X.Org Server Extension, version 2.0
>(II) Loading extension XFree86-DRI
>(II) LoadModule: "dri2"
>(II) Loading /usr/lib/xorg/modules/extensions/libdri2.so
>(II) Module dri2: vendor="X.Org Foundation"
>	compiled for 1.7.0.901, module version = 1.1.0
>	ABI class: X.Org Server Extension, version 2.0
>(II) Loading extension DRI2
>(II) LoadModule: "intel"
>(II) Loading /usr/lib/xorg/modules/drivers/intel_drv.so
>(II) Module intel: vendor="X.Org Foundation"
>	compiled for 1.7.0.901, module version = 2.9.0
>	Module class: X.Org Video Driver
>	ABI class: X.Org Video Driver, version 6.0
>(II) intel: Driver for Intel Integrated Graphics Chipsets: i810,
>	i810-dc100, i810e, i815, i830M, 845G, 852GM/855GM, 865G, 915G,
>	E7221 (i915), 915GM, 945G, 945GM, 945GME, Pineview GM, Pineview G,
>	965G, G35, 965Q, 946GZ, 965GM, 965GME/GLE, G33, Q35, Q33, GM45,
>	4 Series, G45/G43, Q45/Q43, G41, B43, Clarkdale, Arrandale
>(II) Primary Device is: PCI 00@00:02:0
>(WW) VGA arbiter: cannot open kernel arbiter, no multi-card support
>(II) Loading sub module "vgahw"
>(II) LoadModule: "vgahw"
>(II) Loading /usr/lib/xorg/modules/libvgahw.so
>(II) Module vgahw: vendor="X.Org Foundation"
>	compiled for 1.7.0.901, module version = 0.1.0
>	ABI class: X.Org Video Driver, version 6.0
>(II) Loading sub module "ramdac"
>(II) LoadModule: "ramdac"
>(II) Module "ramdac" already built-in
>drmOpenDevice: node name is /dev/dri/card0
>drmOpenDevice: open result is 7, (OK)
>drmOpenByBusid: Searching for BusID pci:0000:00:02.0
>drmOpenDevice: node name is /dev/dri/card0
>drmOpenDevice: open result is 7, (OK)
>drmOpenByBusid: drmOpenMinor returns 7
>drmOpenByBusid: drmGetBusid reports pci:0000:00:02.0
>(**) intel(0): Depth 16, (--) framebuffer bpp 16
>(==) intel(0): RGB weight 565
>(==) intel(0): Default visual is TrueColor
>(**) intel(0): Option "ModeDebug" "true"
>(II) intel(0): Integrated Graphics Chipset: Intel(R) Q35
>(--) intel(0): Chipset: "Q35"
>(--) intel(0): Linear framebuffer at 0xC0000000
>(--) intel(0): IO registers at addr 0xD0100000 size 524288
>(WW) intel(0): libpciaccess reported 0 rom size, guessing 64kB
>(II) intel(0): the SDVO device with slave addr 70 is found on DVO 1 port
>(II) intel(0): the SDVO device with slave addr 70 is found on DVO 1 port
>(WW) intel(0): One DVO port is shared by two slave address. Maybe it can't be handled
>(II) intel(0): Hardware state on X startup:
>(II) intel(0): DumpRegsBegin
>(II) intel(0):            CHDECMISC: 0x0000006d (XOR bank, ch2 enh disabled, ch1 enh enabled, ch0 enh enabled, flex disabled, ep present)
>(II) intel(0):               C0DRB0: 0x00100010 (0x0010)
>(II) intel(0):               C0DRB1: 0x00100010 (0x0010)
>(II) intel(0):               C0DRB2: 0x00100010 (0x0010)
>(II) intel(0):               C0DRB3: 0x00860010 (0x0010)
>(II) intel(0):               C1DRB0: 0x00100010 (0x0010)
>(II) intel(0):               C1DRB1: 0x00100010 (0x0010)
>(II) intel(0):               C1DRB2: 0x00100010 (0x0010)
>(II) intel(0):               C1DRB3: 0x00860010 (0x0010)
>(II) intel(0):              C0DRA01: 0x00000086 (0x0086)
>(II) intel(0):              C0DRA23: 0x00000000 (0x0000)
>(II) intel(0):              C1DRA01: 0x00000086 (0x0086)
>(II) intel(0):              C1DRA23: 0x00000000 (0x0000)
>(II) intel(0):           PGETBL_CTL: 0x00000001
>(II) intel(0):    VCLK_DIVISOR_VGA0: 0x00031108 (n = 3, m1 = 17, m2 = 8)
>(II) intel(0):    VCLK_DIVISOR_VGA1: 0x00031406 (n = 3, m1 = 20, m2 = 6)
>(II) intel(0):        VCLK_POST_DIV: 0x00020002 (vga0 p1 = 4, p2 = 2, vga1 p1 = 2, p2 = 2)
>(II) intel(0):            DPLL_TEST: 0x00010001 ()
>(II) intel(0):         CACHE_MODE_0: 0x00006820
>(II) intel(0):              D_STATE: 0x00000000
>(II) intel(0):        DSPCLK_GATE_D: 0x00000000 (clock gates disabled:)
>(II) intel(0):       RENCLK_GATE_D1: 0x00000000
>(II) intel(0):       RENCLK_GATE_D2: 0x00000000
>(II) intel(0):                SDVOB: 0x8030000c (enabled, pipe A, stall disabled, detected)
>(II) intel(0):                SDVOC: 0x00300000 (disabled, pipe A, stall disabled, not detected)
>(II) intel(0):              SDVOUDI: 0x00000000
>(II) intel(0):               DSPARB: 0x00001d9c
>(II) intel(0):               DSPFW1: 0x00000000
>(II) intel(0):               DSPFW2: 0x00000000
>(II) intel(0):               DSPFW3: 0x00000000
>(II) intel(0):                 ADPA: 0x80000000 (enabled, pipe A, -hsync, -vsync)
>(II) intel(0):                 LVDS: 0x00000000 (disabled, pipe A, 18 bit, 1 channel)
>(II) intel(0):                 DVOA: 0x00000000 (disabled, pipe A, no stall, -hsync, -vsync)
>(II) intel(0):                 DVOB: 0x8030000c (enabled, pipe A, no stall, +hsync, -vsync)
>(II) intel(0):                 DVOC: 0x00300000 (disabled, pipe A, no stall, -hsync, -vsync)
>(II) intel(0):          DVOA_SRCDIM: 0x00000000
>(II) intel(0):          DVOB_SRCDIM: 0x00000000
>(II) intel(0):          DVOC_SRCDIM: 0x00000000
>(II) intel(0):           PP_CONTROL: 0x00000000 (power target: off)
>(II) intel(0):            PP_STATUS: 0x00000000 (off, not ready, sequencing idle)
>(II) intel(0):         PP_ON_DELAYS: 0x00000000
>(II) intel(0):        PP_OFF_DELAYS: 0x00000000
>(II) intel(0):           PP_DIVISOR: 0x00000000
>(II) intel(0):         PFIT_CONTROL: 0x00000000
>(II) intel(0):      PFIT_PGM_RATIOS: 0x00000000
>(II) intel(0):      PORT_HOTPLUG_EN: 0x00000020
>(II) intel(0):    PORT_HOTPLUG_STAT: 0x00000b00
>(II) intel(0):             DSPACNTR: 0x18000000 (disabled, pipe A)
>(II) intel(0):           DSPASTRIDE: 0x00001400 (5120 bytes)
>(II) intel(0):              DSPAPOS: 0x00000000 (0, 0)
>(II) intel(0):             DSPASIZE: 0x018f02cf (720, 400)
>(II) intel(0):             DSPABASE: 0x00000000
>(II) intel(0):             DSPASURF: 0x00000000
>(II) intel(0):          DSPATILEOFF: 0x00000000
>(II) intel(0):            PIPEACONF: 0x80000000 (enabled, single-wide)
>(II) intel(0):             PIPEASRC: 0x027f01df (640, 480)
>(II) intel(0):            PIPEASTAT: 0x00000203 (status: VSYNC_INT_STATUS VBLANK_INT_STATUS OREG_UPDATE_STATUS)
>(II) intel(0):    PIPEA_GMCH_DATA_M: 0x00000000
>(II) intel(0):    PIPEA_GMCH_DATA_N: 0x00000000
>(II) intel(0):      PIPEA_DP_LINK_M: 0x00000000
>(II) intel(0):      PIPEA_DP_LINK_N: 0x00000000
>(II) intel(0):        CURSOR_A_BASE: 0x00000000
>(II) intel(0):     CURSOR_A_CONTROL: 0x00000000
>(II) intel(0):    CURSOR_A_POSITION: 0x00000000
>(II) intel(0):                 FPA0: 0x00021509 (n = 2, m1 = 21, m2 = 9)
>(II) intel(0):                 FPA1: 0x00031108 (n = 3, m1 = 17, m2 = 8)
>(II) intel(0):               DPLL_A: 0xd4040033 (enabled, dvo, default clock, DAC/serial mode, p1 = 3, p2 = 10, SDVO mult 4)
>(II) intel(0):            DPLL_A_MD: 0x00000000
>(II) intel(0):             HTOTAL_A: 0x031f027f (640 active, 800 total)
>(II) intel(0):             HBLANK_A: 0x031f027f (640 start, 800 end)
>(II) intel(0):              HSYNC_A: 0x02ef028f (656 start, 752 end)
>(II) intel(0):             VTOTAL_A: 0x020c01df (480 active, 525 total)
>(II) intel(0):             VBLANK_A: 0x020c01df (480 start, 525 end)
>(II) intel(0):              VSYNC_A: 0x01eb01e9 (490 start, 492 end)
>(II) intel(0):            BCLRPAT_A: 0x00000000
>(II) intel(0):         VSYNCSHIFT_A: 0x00000000
>(II) intel(0):             DSPBCNTR: 0x01000000 (disabled, pipe B)
>(II) intel(0):           DSPBSTRIDE: 0x00000000 (0 bytes)
>(II) intel(0):              DSPBPOS: 0x00000000 (0, 0)
>(II) intel(0):             DSPBSIZE: 0x00000000 (1, 1)
>(II) intel(0):             DSPBBASE: 0x00000000
>(II) intel(0):             DSPBSURF: 0x00000000
>(II) intel(0):          DSPBTILEOFF: 0x00000000
>(II) intel(0):            PIPEBCONF: 0x00000000 (disabled, single-wide)
>(II) intel(0):             PIPEBSRC: 0x027f01df (640, 480)
>(II) intel(0):            PIPEBSTAT: 0x00000000 (status:)
>(II) intel(0):    PIPEB_GMCH_DATA_M: 0x00000000
>(II) intel(0):    PIPEB_GMCH_DATA_N: 0x00000000
>(II) intel(0):      PIPEB_DP_LINK_M: 0x00000000
>(II) intel(0):      PIPEB_DP_LINK_N: 0x00000000
>(II) intel(0):        CURSOR_B_BASE: 0x00000000
>(II) intel(0):     CURSOR_B_CONTROL: 0x00000000
>(II) intel(0):    CURSOR_B_POSITION: 0x00000000
>(II) intel(0):                 FPB0: 0x00031108 (n = 3, m1 = 17, m2 = 8)
>(II) intel(0):                 FPB1: 0x00031108 (n = 3, m1 = 17, m2 = 8)
>(II) intel(0):               DPLL_B: 0x04800003 (disabled, non-dvo, VGA, default clock, DAC/serial mode, p1 = 8, p2 = 10, SDVO mult 1)
>(II) intel(0):            DPLL_B_MD: 0x00000000
>(II) intel(0):             HTOTAL_B: 0x031f027f (640 active, 800 total)
>(II) intel(0):             HBLANK_B: 0x03170287 (648 start, 792 end)
>(II) intel(0):              HSYNC_B: 0x02ef028f (656 start, 752 end)
>(II) intel(0):             VTOTAL_B: 0x020c01df (480 active, 525 total)
>(II) intel(0):             VBLANK_B: 0x020401e7 (488 start, 517 end)
>(II) intel(0):              VSYNC_B: 0x01eb01e9 (490 start, 492 end)
>(II) intel(0):            BCLRPAT_B: 0x00000000
>(II) intel(0):         VSYNCSHIFT_B: 0x00000000
>(II) intel(0):    VCLK_DIVISOR_VGA0: 0x00031108
>(II) intel(0):    VCLK_DIVISOR_VGA1: 0x00031406
>(II) intel(0):        VCLK_POST_DIV: 0x00020002
>(II) intel(0):             VGACNTRL: 0x0124008e (enabled)
>(II) intel(0):               TV_CTL: 0x00000000
>(II) intel(0):               TV_DAC: 0x00000000
>(II) intel(0):             TV_CSC_Y: 0x00000000
>(II) intel(0):            TV_CSC_Y2: 0x00000000
>(II) intel(0):             TV_CSC_U: 0x00000000
>(II) intel(0):            TV_CSC_U2: 0x00000000
>(II) intel(0):             TV_CSC_V: 0x00000000
>(II) intel(0):            TV_CSC_V2: 0x00000000
>(II) intel(0):         TV_CLR_KNOBS: 0x00000000
>(II) intel(0):         TV_CLR_LEVEL: 0x00000000
>(II) intel(0):           TV_H_CTL_1: 0x00000000
>(II) intel(0):           TV_H_CTL_2: 0x00000000
>(II) intel(0):           TV_H_CTL_3: 0x00000000
>(II) intel(0):           TV_V_CTL_1: 0x00000000
>(II) intel(0):           TV_V_CTL_2: 0x00000000
>(II) intel(0):           TV_V_CTL_3: 0x00000000
>(II) intel(0):           TV_V_CTL_4: 0x00000000
>(II) intel(0):           TV_V_CTL_5: 0x00000000
>(II) intel(0):           TV_V_CTL_6: 0x00000000
>(II) intel(0):           TV_V_CTL_7: 0x00000000
>(II) intel(0):          TV_SC_CTL_1: 0x00000000
>(II) intel(0):          TV_SC_CTL_2: 0x00000000
>(II) intel(0):          TV_SC_CTL_3: 0x00000000
>(II) intel(0):           TV_WIN_POS: 0x00000000
>(II) intel(0):          TV_WIN_SIZE: 0x00000000
>(II) intel(0):      TV_FILTER_CTL_1: 0x00000000
>(II) intel(0):      TV_FILTER_CTL_2: 0x00000000
>(II) intel(0):      TV_FILTER_CTL_3: 0x00000000
>(II) intel(0):        TV_CC_CONTROL: 0x00000000
>(II) intel(0):           TV_CC_DATA: 0x00000000
>(II) intel(0):          TV_H_LUMA_0: 0x00000000
>(II) intel(0):         TV_H_LUMA_59: 0x00000000
>(II) intel(0):        TV_H_CHROMA_0: 0x00000000
>(II) intel(0):       TV_H_CHROMA_59: 0x00000000
>(II) intel(0):         FBC_CFB_BASE: 0xffffffff
>(II) intel(0):          FBC_LL_BASE: 0xffffffff
>(II) intel(0):          FBC_CONTROL: 0xffffffff
>(II) intel(0):          FBC_COMMAND: 0xffffffff
>(II) intel(0):           FBC_STATUS: 0xffffffff
>(II) intel(0):         FBC_CONTROL2: 0xffffffff
>(II) intel(0):        FBC_FENCE_OFF: 0xffffffff
>(II) intel(0):          FBC_MOD_NUM: 0xffffffff
>(II) intel(0):              MI_MODE: 0x00000200
>(II) intel(0):         MI_ARB_STATE: 0x00000040
>(II) intel(0):       MI_RDRET_STATE: 0x00000000
>(II) intel(0):              ECOSKPD: 0x00000307
>(II) intel(0):                 DP_B: 0x00000000
>(II) intel(0):       DPB_AUX_CH_CTL: 0x00000000
>(II) intel(0):     DPB_AUX_CH_DATA1: 0x00000000
>(II) intel(0):     DPB_AUX_CH_DATA2: 0x00000000
>(II) intel(0):     DPB_AUX_CH_DATA3: 0x00000000
>(II) intel(0):     DPB_AUX_CH_DATA4: 0x00000000
>(II) intel(0):     DPB_AUX_CH_DATA5: 0x00000000
>(II) intel(0):                 DP_C: 0x00000000
>(II) intel(0):       DPC_AUX_CH_CTL: 0x00000000
>(II) intel(0):     DPC_AUX_CH_DATA1: 0x00000000
>(II) intel(0):     DPC_AUX_CH_DATA2: 0x00000000
>(II) intel(0):     DPC_AUX_CH_DATA3: 0x00000000
>(II) intel(0):     DPC_AUX_CH_DATA4: 0x00000000
>(II) intel(0):     DPC_AUX_CH_DATA5: 0x00000000
>(II) intel(0):                 DP_D: 0x00000000
>(II) intel(0):       DPD_AUX_CH_CTL: 0x00000000
>(II) intel(0):     DPD_AUX_CH_DATA1: 0x00000000
>(II) intel(0):     DPD_AUX_CH_DATA2: 0x00000000
>(II) intel(0):     DPD_AUX_CH_DATA3: 0x00000000
>(II) intel(0):     DPD_AUX_CH_DATA4: 0x00000000
>(II) intel(0):     DPD_AUX_CH_DATA5: 0x00000000
>(II) intel(0):           AUD_CONFIG: 0x00000000
>(II) intel(0):     AUD_HDMIW_STATUS: 0x00000000
>(II) intel(0):       AUD_CONV_CHCNT: 0x00000000
>(II) intel(0):        VIDEO_DIP_CTL: 0x00000000
>(II) intel(0):        AUD_PINW_CNTR: 0x00000000
>(II) intel(0):          AUD_CNTL_ST: 0x00000000
>(II) intel(0):          AUD_PIN_CAP: 0x00000000
>(II) intel(0):         AUD_PINW_CAP: 0x00000000
>(II) intel(0):   AUD_PINW_UNSOLRESP: 0x00000000
>(II) intel(0):     AUD_OUT_DIG_CNVT: 0x00000000
>(II) intel(0):        AUD_OUT_CWCAP: 0x00000000
>(II) intel(0):          AUD_GRP_CAP: 0x00000000
>(II) intel(0):             FENCE  0: 0x00000000 (disabled, X tiled,    0 pitch, 0x00000000 - 0x00000000 (0kb))
>(II) intel(0):             FENCE  1: 0x00000000 (disabled, X tiled,    0 pitch, 0x00000000 - 0x00000000 (0kb))
>(II) intel(0):             FENCE  2: 0x00000000 (disabled, X tiled,    0 pitch, 0x00000000 - 0x00000000 (0kb))
>(II) intel(0):             FENCE  3: 0x00000000 (disabled, X tiled,    0 pitch, 0x00000000 - 0x00000000 (0kb))
>(II) intel(0):             FENCE  4: 0x00000000 (disabled, X tiled,    0 pitch, 0x00000000 - 0x00000000 (0kb))
>(II) intel(0):             FENCE  5: 0x00000000 (disabled, X tiled,    0 pitch, 0x00000000 - 0x00000000 (0kb))
>(II) intel(0):             FENCE  6: 0x00000000 (disabled, X tiled,    0 pitch, 0x00000000 - 0x00000000 (0kb))
>(II) intel(0):             FENCE  7: 0x00000000 (disabled, X tiled,    0 pitch, 0x00000000 - 0x00000000 (0kb))
>(II) intel(0):             FENCE  8: 0x00000000 (disabled, X tiled,    0 pitch, 0x00000000 - 0x00000000 (0kb))
>(II) intel(0):             FENCE  9: 0x00000000 (disabled, X tiled,    0 pitch, 0x00000000 - 0x00000000 (0kb))
>(II) intel(0):            FENCE  10: 0x00000000 (disabled, X tiled,    0 pitch, 0x00000000 - 0x00000000 (0kb))
>(II) intel(0):            FENCE  11: 0x00000000 (disabled, X tiled,    0 pitch, 0x00000000 - 0x00000000 (0kb))
>(II) intel(0):            FENCE  12: 0x00000000 (disabled, X tiled,    0 pitch, 0x00000000 - 0x00000000 (0kb))
>(II) intel(0):            FENCE  13: 0x00000000 (disabled, X tiled,    0 pitch, 0x00000000 - 0x00000000 (0kb))
>(II) intel(0):            FENCE  14: 0x00000000 (disabled, X tiled,    0 pitch, 0x00000000 - 0x00000000 (0kb))
>(II) intel(0):            FENCE  15: 0x00000000 (disabled, X tiled,    0 pitch, 0x00000000 - 0x00000000 (0kb))
>(II) intel(0): pipe A dot 100800 n 2 m1 21 m2 9 p1 3 p2 10
>(II) intel(0): pipe B dot 25200 n 3 m1 17 m2 8 p1 8 p2 10
>(II) intel(0): DumpRegsEnd
>(II) intel(0): 2 display pipes available.
>(II) Loading sub module "ddc"
>(II) LoadModule: "ddc"
>(II) Module "ddc" already built-in
>(II) Loading sub module "i2c"
>(II) LoadModule: "i2c"
>(II) Module "i2c" already built-in
>(II) intel(0): Output VGA using monitor section Monitor[0]
>(**) intel(0): Option "PreferredMode" "1280x1024"
>(**) intel(0): Option "Position" "0 0"
>xf86TokenToOptinfo: table is NULL
>(II) intel(0): I2C bus "SDVOCTRL_E for SDVOB" initialized.
>(II) intel(0): I2C device "SDVOCTRL_E for SDVOB:SDVO Controller B" registered at address 0x70.
>(II) intel(0): I2C bus "SDVOB DDC Bus" initialized.
>(II) intel(0): SDVOB: W: 02                         (SDVO_CMD_GET_DEVICE_CAPS)
>(II) intel(0): SDVOB: R: 03 94 02 01 01 02 1F 00 (Success)
>(II) intel(0): SDVOB: W: 9D                         (SDVO_CMD_GET_SUPP_ENCODE)
>(II) intel(0): SDVOB: R: 03 94                   (Not supported)
>(II) intel(0): Output TMDS-1 using monitor section Monitor[1]
>(**) intel(0): Option "PreferredMode" "1280x1024"
>(**) intel(0): Option "Position" "1280 0"
>(**) intel(0): Option "RightOf" "Monitor[0]"
>(II) intel(0): SDVOB: W: 10 00                      (SDVO_CMD_SET_TARGET_INPUT)
>(II) intel(0): SDVOB: R:                         (Success)
>(II) intel(0): SDVOB: W: 1D                         (SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE)
>(II) intel(0): SDVOB: R: C4 09 74 40             (Success)
>(II) intel(0): SDVOB: device VID/DID: 03:94.02, clock range 25.0MHz - 165.0MHz
>(II) intel(0): SDVOB: 2 input channels
>(II) intel(0): SDVOB: TMDS0 output reported
>(II) intel(0): SDVOB: RGB0 output reported
>(II) intel(0): SDVOB: CVBS0 output reported
>(II) intel(0): SDVOB: SVID0 output reported
>(II) intel(0): SDVOB: YPRPB0 output reported
>xf86TokenToOptinfo: table is NULL
>(II) intel(0): I2C bus "SDVOCTRL_E for SDVOC" initialized.
>(II) intel(0): I2C device "SDVOCTRL_E for SDVOC:SDVO Controller C" registered at address 0x72.
>(II) intel(0): No SDVO device found on SDVOC
>(II) intel(0): I2C device "SDVOCTRL_E for SDVOC:SDVO Controller C" removed.
>(II) intel(0): I2C bus "SDVOCTRL_E for SDVOC" removed.
>(II) intel(0): SDVOB: W: 20                         (SDVO_CMD_GET_CLOCK_RATE_MULT)
>(II) intel(0): SDVOB: R: 08                      (Success)
>(II) intel(0): Current clock rate multiplier: 8
>(II) intel(0): SDVOB: W: 04                         (SDVO_CMD_GET_ACTIVE_OUTPUTS)
>(II) intel(0): SDVOB: R: 01 00                   (Success)
>(II) intel(0): SDVOB: W: 10 00                      (SDVO_CMD_SET_TARGET_INPUT)
>(II) intel(0): SDVOB: R:                         (Success)
>(II) intel(0): SDVOB: W: 12                         (SDVO_CMD_GET_INPUT_TIMINGS_PART1)
>(II) intel(0): SDVOB: R: D6 09 80 A0 20 E0 2D 10 (Success)
>(II) intel(0): SDVOB: W: 13                         (SDVO_CMD_GET_INPUT_TIMINGS_PART2)
>(II) intel(0): SDVOB: R: 10 60 A2 00 18 00 00 00 (Success)
>(II) intel(0): SDVOB: W: 10 01                      (SDVO_CMD_SET_TARGET_INPUT)
>(II) intel(0): SDVOB: R:                         (Success)
>(II) intel(0): SDVOB: W: 12                         (SDVO_CMD_GET_INPUT_TIMINGS_PART1)
>(II) intel(0): SDVOB: R: 10 00 60 02 0A 5F D1 CA (Invalid arg)
>(II) intel(0): SDVOB: W: 11 01 00                   (SDVO_CMD_SET_TARGET_OUTPUT)
>(II) intel(0): SDVOB: R:                         (Success)
>(II) intel(0): SDVOB: W: 18                         (SDVO_CMD_GET_OUTPUT_TIMINGS_PART1)
>(II) intel(0): SDVOB: R: D6 09 80 A0 20 E0 2D 10 (Success)
>(II) intel(0): SDVOB: W: 19                         (SDVO_CMD_GET_OUTPUT_TIMINGS_PART2)
>(II) intel(0): SDVOB: R: 10 60 A2 00 1C 00 00 00 (Success)
>(II) intel(0): SDVOB: W: 11 02 00                   (SDVO_CMD_SET_TARGET_OUTPUT)
>(II) intel(0): SDVOB: R:                         (Success)
>(II) intel(0): SDVOB: W: 18                         (SDVO_CMD_GET_OUTPUT_TIMINGS_PART1)
>(II) intel(0): SDVOB: R: 95 AE 97 51 BB 52 B5 EB (Success)
>(II) intel(0): SDVOB: W: 19                         (SDVO_CMD_GET_OUTPUT_TIMINGS_PART2)
>(II) intel(0): SDVOB: R: 5C F5 C4 AD AA 00 00 00 (Success)
>(II) intel(0): SDVOB: W: 11 04 00                   (SDVO_CMD_SET_TARGET_OUTPUT)
>(II) intel(0): SDVOB: R:                         (Success)
>(II) intel(0): SDVOB: W: 18                         (SDVO_CMD_GET_OUTPUT_TIMINGS_PART1)
>(II) intel(0): SDVOB: R: 55 AE 56 55 AA 4F 55 BB (Success)
>(II) intel(0): SDVOB: W: 19                         (SDVO_CMD_GET_OUTPUT_TIMINGS_PART2)
>(II) intel(0): SDVOB: R: 55 14 A4 B9 3F 00 00 00 (Success)
>(II) intel(0): SDVOB: W: 11 08 00                   (SDVO_CMD_SET_TARGET_OUTPUT)
>(II) intel(0): SDVOB: R:                         (Success)
>(II) intel(0): SDVOB: W: 18                         (SDVO_CMD_GET_OUTPUT_TIMINGS_PART1)
>(II) intel(0): SDVOB: R: 55 AE 56 55 AA 4F 55 BB (Success)
>(II) intel(0): SDVOB: W: 19                         (SDVO_CMD_GET_OUTPUT_TIMINGS_PART2)
>(II) intel(0): SDVOB: R: 55 14 A4 B9 3F 00 00 00 (Success)
>(II) intel(0): SDVOB: W: 11 10 00                   (SDVO_CMD_SET_TARGET_OUTPUT)
>(II) intel(0): SDVOB: R:                         (Success)
>(II) intel(0): SDVOB: W: 18                         (SDVO_CMD_GET_OUTPUT_TIMINGS_PART1)
>(II) intel(0): SDVOB: R: 55 AE 56 55 AA 4F 55 BB (Success)
>(II) intel(0): SDVOB: W: 19                         (SDVO_CMD_GET_OUTPUT_TIMINGS_PART2)
>(II) intel(0): SDVOB: R: 55 14 A4 B9 3F 00 00 00 (Success)
>(II) intel(0): I2C bus "CRTDDC_A" initialized.
>(II) intel(0): I2C device "CRTDDC_A:ddc2" registered at address 0xA0.
>(II) intel(0): I2C device "CRTDDC_A:DDC control interface" registered at address 0x6E.
>(II) intel(0): I2C device "CRTDDC_A:DDC control interface" removed.
>(II) intel(0): I2C device "CRTDDC_A:ddc2" removed.
>(II) intel(0): I2C bus "CRTDDC_A" removed.
>(II) intel(0): EDID for output VGA
>(II) intel(0): Manufacturer: LEN  Model: 114f  Serial#: 16843009
>(II) intel(0): Year: 2008  Week: 13
>(II) intel(0): EDID Version: 1.3
>(II) intel(0): Analog Display Input,  Input Voltage Level: 0.700/0.700 V
>(II) intel(0): Sync:  Separate  Composite  SyncOnGreen
>(II) intel(0): Max Image Size [cm]: horiz.: 40  vert.: 32
>(II) intel(0): Gamma: 2.20
>(II) intel(0): DPMS capabilities: StandBy Suspend Off; RGB/Color Display
>(II) intel(0): Default color space is primary color space
>(II) intel(0): First detailed timing is preferred mode
>(II) intel(0): redX: 0.640 redY: 0.329   greenX: 0.300 greenY: 0.600
>(II) intel(0): blueX: 0.150 blueY: 0.060   whiteX: 0.313 whiteY: 0.329
>(II) intel(0): Supported established timings:
>(II) intel(0): 720x400@70Hz
>(II) intel(0): 640x480@60Hz
>(II) intel(0): 640x480@67Hz
>(II) intel(0): 640x480@72Hz
>(II) intel(0): 640x480@75Hz
>(II) intel(0): 800x600@60Hz
>(II) intel(0): 800x600@72Hz
>(II) intel(0): 800x600@75Hz
>(II) intel(0): 832x624@75Hz
>(II) intel(0): 1024x768@60Hz
>(II) intel(0): 1024x768@70Hz
>(II) intel(0): 1024x768@75Hz
>(II) intel(0): 1280x1024@75Hz
>(II) intel(0): 1152x864@75Hz
>(II) intel(0): Manufacturer's mask: 0
>(II) intel(0): Supported standard timings:
>(II) intel(0): #0: hsize: 1280  vsize 1024  refresh: 60  vid: 32897
>(II) intel(0): #1: hsize: 1280  vsize 1024  refresh: 70  vid: 35457
>(II) intel(0): #2: hsize: 1280  vsize 1024  refresh: 72  vid: 35969
>(II) intel(0): #3: hsize: 1280  vsize 1024  refresh: 76  vid: 36993
>(II) intel(0): #4: hsize: 1152  vsize 864  refresh: 75  vid: 20337
>(II) intel(0): Supported detailed timing:
>(II) intel(0): clock: 108.0 MHz   Image Size:  376 x 301 mm
>(II) intel(0): h_active: 1280  h_sync: 1328  h_sync_end 1440 h_blank_end 1688 h_border: 0
>(II) intel(0): v_active: 1024  v_sync: 1025  v_sync_end 1028 v_blanking: 1066 v_border: 0
>(II) intel(0): Ranges: V min: 56 V max: 76 Hz, H min: 30 H max: 81 kHz, PixClock max 140 MHz
>(II) intel(0): Monitor name: LEN L193pC
>(II) intel(0): Serial No: VL-DYB06
>(II) intel(0): EDID (in hex):
>(II) intel(0): 	00ffffffffffff0030ae4f1101010101
>(II) intel(0): 	0d1201036e282078eede95a3544c9926
>(II) intel(0): 	0f5054bdef808180818a818c8190714f
>(II) intel(0): 	010101010101302a009851002a403070
>(II) intel(0): 	1300782d1100001e000000fd00384c1e
>(II) intel(0): 	510e000a202020202020000000fc004c
>(II) intel(0): 	454e204c31393370430a2020000000ff
>(II) intel(0): 	00564c2d44594230360a2020202000c7
>(II) intel(0): EDID vendor "LEN", prod id 4431
>(II) intel(0): Using hsync ranges from config file
>(II) intel(0): Using vrefresh ranges from config file
>(II) intel(0): Printing DDC gathered Modelines:
>(II) intel(0): Modeline "1280x1024"x0.0  108.00  1280 1328 1440 1688  1024 1025 1028 1066 +hsync +vsync (64.0 kHz)
>(II) intel(0): Modeline "800x600"x0.0   40.00  800 840 968 1056  600 601 605 628 +hsync +vsync (37.9 kHz)
>(II) intel(0): Modeline "640x480"x0.0   31.50  640 656 720 840  480 481 484 500 -hsync -vsync (37.5 kHz)
>(II) intel(0): Modeline "640x480"x0.0   31.50  640 664 704 832  480 489 492 520 -hsync -vsync (37.9 kHz)
>(II) intel(0): Modeline "640x480"x0.0   30.24  640 704 768 864  480 483 486 525 -hsync -vsync (35.0 kHz)
>(II) intel(0): Modeline "640x480"x0.0   25.18  640 656 752 800  480 490 492 525 -hsync -vsync (31.5 kHz)
>(II) intel(0): Modeline "720x400"x0.0   28.32  720 738 846 900  400 412 414 449 -hsync +vsync (31.5 kHz)
>(II) intel(0): Modeline "1280x1024"x0.0  135.00  1280 1296 1440 1688  1024 1025 1028 1066 +hsync +vsync (80.0 kHz)
>(II) intel(0): Modeline "1024x768"x0.0   78.75  1024 1040 1136 1312  768 769 772 800 +hsync +vsync (60.0 kHz)
>(II) intel(0): Modeline "1024x768"x0.0   75.00  1024 1048 1184 1328  768 771 777 806 -hsync -vsync (56.5 kHz)
>(II) intel(0): Modeline "1024x768"x0.0   65.00  1024 1048 1184 1344  768 771 777 806 -hsync -vsync (48.4 kHz)
>(II) intel(0): Modeline "832x624"x0.0   57.28  832 864 928 1152  624 625 628 667 -hsync -vsync (49.7 kHz)
>(II) intel(0): Modeline "800x600"x0.0   49.50  800 816 896 1056  600 601 604 625 +hsync +vsync (46.9 kHz)
>(II) intel(0): Modeline "800x600"x0.0   50.00  800 856 976 1040  600 637 643 666 +hsync +vsync (48.1 kHz)
>(II) intel(0): Modeline "1152x864"x0.0  108.00  1152 1216 1344 1600  864 865 868 900 +hsync +vsync (67.5 kHz)
>(II) intel(0): Modeline "1280x1024"x0.0  108.00  1280 1328 1440 1688  1024 1025 1028 1066 +hsync +vsync (64.0 kHz)
>(II) intel(0): Modeline "1280x1024"x70.0  128.94  1280 1368 1504 1728  1024 1025 1028 1066 -hsync +vsync (74.6 kHz)
>(II) intel(0): Modeline "1280x1024"x72.0  132.75  1280 1368 1504 1728  1024 1025 1028 1067 -hsync +vsync (76.8 kHz)
>(II) intel(0): Modeline "1280x1024"x76.0  141.82  1280 1376 1512 1744  1024 1025 1028 1070 -hsync +vsync (81.3 kHz)
>(II) intel(0): Modeline "1152x864"x0.0  108.00  1152 1216 1344 1600  864 865 868 900 +hsync +vsync (67.5 kHz)
>(II) intel(0): EDID vendor "LEN", prod id 4431
>(II) intel(0): Not using mode "1280x1024" (bad mode clock/interlace/doublescan)
>(II) intel(0): Printing probed modes for output VGA
>(II) intel(0): Modeline "1280x1024"x60.0  108.00  1280 1328 1440 1688  1024 1025 1028 1066 +hsync +vsync (64.0 kHz)
>(II) intel(0): Modeline "1280x1024"x75.0  135.00  1280 1296 1440 1688  1024 1025 1028 1066 +hsync +vsync (80.0 kHz)
>(II) intel(0): Modeline "1280x1024"x72.0  132.75  1280 1368 1504 1728  1024 1025 1028 1067 -hsync +vsync (76.8 kHz)
>(II) intel(0): Modeline "1280x1024"x70.0  128.94  1280 1368 1504 1728  1024 1025 1028 1066 -hsync +vsync (74.6 kHz)
>(II) intel(0): Modeline "1280x1024"x60.0  108.00  1280 1328 1440 1688  1024 1025 1028 1066 +hsync +vsync (64.0 kHz)
>(II) intel(0): Modeline "1152x864"x75.0  108.00  1152 1216 1344 1600  864 865 868 900 +hsync +vsync (67.5 kHz)
>(II) intel(0): Modeline "1024x768"x75.0   78.75  1024 1040 1136 1312  768 769 772 800 +hsync +vsync (60.0 kHz)
>(II) intel(0): Modeline "1024x768"x70.1   75.00  1024 1048 1184 1328  768 771 777 806 -hsync -vsync (56.5 kHz)
>(II) intel(0): Modeline "1024x768"x60.0   65.00  1024 1048 1184 1344  768 771 777 806 -hsync -vsync (48.4 kHz)
>(II) intel(0): Modeline "832x624"x74.6   57.28  832 864 928 1152  624 625 628 667 -hsync -vsync (49.7 kHz)
>(II) intel(0): Modeline "800x600"x72.2   50.00  800 856 976 1040  600 637 643 666 +hsync +vsync (48.1 kHz)
>(II) intel(0): Modeline "800x600"x75.0   49.50  800 816 896 1056  600 601 604 625 +hsync +vsync (46.9 kHz)
>(II) intel(0): Modeline "800x600"x60.3   40.00  800 840 968 1056  600 601 605 628 +hsync +vsync (37.9 kHz)
>(II) intel(0): Modeline "640x480"x75.0   31.50  640 656 720 840  480 481 484 500 -hsync -vsync (37.5 kHz)
>(II) intel(0): Modeline "640x480"x72.8   31.50  640 664 704 832  480 489 492 520 -hsync -vsync (37.9 kHz)
>(II) intel(0): Modeline "640x480"x66.7   30.24  640 704 768 864  480 483 486 525 -hsync -vsync (35.0 kHz)
>(II) intel(0): Modeline "640x480"x59.9   25.18  640 656 752 800  480 490 492 525 -hsync -vsync (31.5 kHz)
>(II) intel(0): Modeline "720x400"x70.1   28.32  720 738 846 900  400 412 414 449 -hsync +vsync (31.5 kHz)
>(II) intel(0): SDVOB: W: 0B                         (SDVO_CMD_GET_ATTACHED_DISPLAYS)
>(II) intel(0): SDVOB: R: 03 14                   (Success)
>(II) intel(0): SDVOB: W: 9D                         (SDVO_CMD_GET_SUPP_ENCODE)
>(II) intel(0): SDVOB: R: 03 14                   (Not supported)
>(II) intel(0): Output TMDS-1 using monitor section Monitor[1]
>(II) intel(0): I2C device "SDVOB DDC Bus:ddc2" registered at address 0xA0.
>(II) intel(0): SDVOB: W: 7A 04                      (SDVO_CMD_SET_CONTROL_BUS_SWITCH)
>(II) intel(0): SDVOB: W: 7A 04                      (SDVO_CMD_SET_CONTROL_BUS_SWITCH)
>(II) intel(0): SDVOB: W: 7A 04                      (SDVO_CMD_SET_CONTROL_BUS_SWITCH)
>(II) intel(0): SDVOB: W: 7A 04                      (SDVO_CMD_SET_CONTROL_BUS_SWITCH)
>(II) intel(0): SDVOB: W: 7A 04                      (SDVO_CMD_SET_CONTROL_BUS_SWITCH)
>(II) intel(0): SDVOB: W: 7A 04                      (SDVO_CMD_SET_CONTROL_BUS_SWITCH)
>(II) intel(0): SDVOB: W: 7A 04                      (SDVO_CMD_SET_CONTROL_BUS_SWITCH)
>(II) intel(0): EDID for output TMDS-1
>(II) intel(0): Output VGA connected
>(II) intel(0): Output TMDS-1 disconnected
>(II) intel(0): Using user preference for initial modes
>(II) intel(0): Output VGA using initial mode 1280x1024
>(II) intel(0): Using default gamma of (1.0, 1.0, 1.0) unless otherwise stated.
>(II) intel(0): SDVOB: W: 05 00 00                   (SDVO_CMD_SET_ACTIVE_OUTPUTS)
>(II) intel(0): SDVOB: R:                         (Success)
>(II) intel(0): SDVOB: W: 05 00 00                   (SDVO_CMD_SET_ACTIVE_OUTPUTS)
>(II) intel(0): SDVOB: R:                         (Success)
>(II) intel(0): SDVOB: W: 11 01 00                   (SDVO_CMD_SET_TARGET_OUTPUT)
>(II) intel(0): SDVOB: R:                         (Success)
>(II) intel(0): SDVOB: W: 16 D6 09 80 A0 20 E0 2D 10 (SDVO_CMD_SET_OUTPUT_TIMINGS_PART1)
>(II) intel(0): SDVOB: R:                         (Success)
>(II) intel(0): SDVOB: W: 17 10 60 A2 00 1C 00 00 00 (SDVO_CMD_SET_OUTPUT_TIMINGS_PART2)
>(II) intel(0): SDVOB: R:                         (Success)
>(II) intel(0): SDVOB: W: 11 02 00                   (SDVO_CMD_SET_TARGET_OUTPUT)
>(II) intel(0): SDVOB: R:                         (Success)
>(II) intel(0): SDVOB: W: 16 95 AE 97 51 BB 52 B5 EB (SDVO_CMD_SET_OUTPUT_TIMINGS_PART1)
>(II) intel(0): SDVOB: R:                         (Success)
>(II) intel(0): SDVOB: W: 17 5C F5 C4 AD AA 00 00 00 (SDVO_CMD_SET_OUTPUT_TIMINGS_PART2)
>(II) intel(0): SDVOB: R:                         (Success)
>(II) intel(0): SDVOB: W: 11 04 00                   (SDVO_CMD_SET_TARGET_OUTPUT)
>(II) intel(0): SDVOB: R:                         (Success)
>(II) intel(0): SDVOB: W: 16 55 AE 56 55 AA 4F 55 BB (SDVO_CMD_SET_OUTPUT_TIMINGS_PART1)
>(II) intel(0): SDVOB: R:                         (Invalid arg)
>(II) intel(0): SDVOB: W: 11 08 00                   (SDVO_CMD_SET_TARGET_OUTPUT)
>(II) intel(0): SDVOB: R:                         (Success)
>(II) intel(0): SDVOB: W: 16 55 AE 56 55 AA 4F 55 BB (SDVO_CMD_SET_OUTPUT_TIMINGS_PART1)
>(II) intel(0): SDVOB: R:                         (Invalid arg)
>(II) intel(0): SDVOB: W: 11 10 00                   (SDVO_CMD_SET_TARGET_OUTPUT)
>(II) intel(0): SDVOB: R:                         (Success)
>(II) intel(0): SDVOB: W: 16 55 AE 56 55 AA 4F 55 BB (SDVO_CMD_SET_OUTPUT_TIMINGS_PART1)
>(II) intel(0): SDVOB: R:                         (Invalid arg)
>(II) intel(0): SDVOB: W: 10 00                      (SDVO_CMD_SET_TARGET_INPUT)
>(II) intel(0): SDVOB: R:                         (Success)
>(II) intel(0): SDVOB: W: 14 D6 09 80 A0 20 E0 2D 10 (SDVO_CMD_SET_INPUT_TIMINGS_PART1)
>(II) intel(0): SDVOB: R:                         (Success)
>(II) intel(0): SDVOB: W: 15 10 60 A2 00 18 00 00 00 (SDVO_CMD_SET_INPUT_TIMINGS_PART2)
>(II) intel(0): SDVOB: R:                         (Success)
>(II) intel(0): SDVOB: W: 10 01                      (SDVO_CMD_SET_TARGET_INPUT)
>(II) intel(0): SDVOB: R:                         (Success)
>(II) intel(0): SDVOB: W: 14 10 00 60 02 0A 5F D1 CA (SDVO_CMD_SET_INPUT_TIMINGS_PART1)
>(II) intel(0): SDVOB: R:                         (Invalid arg)
>(II) intel(0): SDVOB: W: 21 08                      (SDVO_CMD_SET_CLOCK_RATE_MULT)
>(II) intel(0): SDVOB: R:                         (Success)
>(II) intel(0): SDVOB: W: 03                         (SDVO_CMD_GET_TRAINED_INPUTS)
>(II) intel(0): SDVOB: R: 01                      (Success)
>(II) intel(0): SDVOB: W: 05 01 00                   (SDVO_CMD_SET_ACTIVE_OUTPUTS)
>(II) intel(0): SDVOB: R:                         (Success)
>(II) intel(0): detected 1024 kB GTT.
>(II) intel(0): detected 7164 kB stolen memory.
>(==) intel(0): video overlay key set to 0x83e
>(**) intel(0): Display dimensions: (400, 320) mm
>(**) intel(0): DPI set to (162, 81)
>(II) Loading sub module "fb"
>(II) LoadModule: "fb"
>(II) Loading /usr/lib/xorg/modules/libfb.so
>(II) Module fb: vendor="X.Org Foundation"
>	compiled for 1.7.0.901, module version = 1.0.0
>	ABI class: X.Org ANSI C Emulation, version 0.4
>(II) intel(0): Comparing regs from server start up to After PreInit
>(WW) intel(0): Register 0x70024 (PIPEASTAT) changed from 0x00000203 to 0x80000203
>(WW) intel(0): PIPEASTAT before: status: VSYNC_INT_STATUS VBLANK_INT_STATUS OREG_UPDATE_STATUS
>(WW) intel(0): PIPEASTAT after: status: FIFO_UNDERRUN VSYNC_INT_STATUS VBLANK_INT_STATUS OREG_UPDATE_STATUS
>(II) intel(0): Kernel reported 480768 total, 1 used
>(II) intel(0): I830CheckAvailableMemory: 1923068 kB available
>(EE) intel(0): Cannot support DRI with frame buffer width > 2048.
>(**) intel(0): Framebuffer compression disabled
>(**) intel(0): Tiling enabled
>(**) intel(0): SwapBuffers wait enabled
>(==) intel(0): VideoRam: 262144 KB
>(II) intel(0): Attempting memory allocation with tiled buffers.
>(II) intel(0): Tiled allocation successful.
>(II) intel(0): vgaHWGetIOBase: hwp->IOBase is 0x03d0, hwp->PIOOffset is 0x0000
>(II) UXA(0): Driver registered support for the following operations:
>(II)         solid
>(II)         copy
>(II)         composite (RENDER acceleration)
>(==) intel(0): Backing store disabled
>(==) intel(0): Silken mouse enabled
>(II) intel(0): Initializing HW Cursor
>(II) intel(0): SDVOB: W: 20                         (SDVO_CMD_GET_CLOCK_RATE_MULT)
>(II) intel(0): SDVOB: R: 08                      (Success)
>(II) intel(0): Current clock rate multiplier: 8
>(II) intel(0): SDVOB: W: 04                         (SDVO_CMD_GET_ACTIVE_OUTPUTS)
>(II) intel(0): SDVOB: R: 01 00                   (Success)
>(II) intel(0): SDVOB: W: 10 00                      (SDVO_CMD_SET_TARGET_INPUT)
>(II) intel(0): SDVOB: R:                         (Success)
>(II) intel(0): SDVOB: W: 12                         (SDVO_CMD_GET_INPUT_TIMINGS_PART1)
>(II) intel(0): SDVOB: R: D6 09 80 A0 20 E0 2D 10 (Success)
>(II) intel(0): SDVOB: W: 13                         (SDVO_CMD_GET_INPUT_TIMINGS_PART2)
>(II) intel(0): SDVOB: R: 10 60 A2 00 18 00 00 00 (Success)
>(II) intel(0): SDVOB: W: 10 01                      (SDVO_CMD_SET_TARGET_INPUT)
>(II) intel(0): SDVOB: R:                         (Success)
>(II) intel(0): SDVOB: W: 12                         (SDVO_CMD_GET_INPUT_TIMINGS_PART1)
>(II) intel(0): SDVOB: R: 10 00 60 02 0A 5F D1 CA (Invalid arg)
>(II) intel(0): SDVOB: W: 11 01 00                   (SDVO_CMD_SET_TARGET_OUTPUT)
>(II) intel(0): SDVOB: R:                         (Success)
>(II) intel(0): SDVOB: W: 18                         (SDVO_CMD_GET_OUTPUT_TIMINGS_PART1)
>(II) intel(0): SDVOB: R: D6 09 80 A0 20 E0 2D 10 (Success)
>(II) intel(0): SDVOB: W: 19                         (SDVO_CMD_GET_OUTPUT_TIMINGS_PART2)
>(II) intel(0): SDVOB: R: 10 60 A2 00 1C 00 00 00 (Success)
>(II) intel(0): SDVOB: W: 11 02 00                   (SDVO_CMD_SET_TARGET_OUTPUT)
>(II) intel(0): SDVOB: R:                         (Success)
>(II) intel(0): SDVOB: W: 18                         (SDVO_CMD_GET_OUTPUT_TIMINGS_PART1)
>(II) intel(0): SDVOB: R: 95 AE 97 51 BB 52 B5 EB (Success)
>(II) intel(0): SDVOB: W: 19                         (SDVO_CMD_GET_OUTPUT_TIMINGS_PART2)
>(II) intel(0): SDVOB: R: 5C F5 C4 AD AA 00 00 00 (Success)
>(II) intel(0): SDVOB: W: 11 04 00                   (SDVO_CMD_SET_TARGET_OUTPUT)
>(II) intel(0): SDVOB: R:                         (Success)
>(II) intel(0): SDVOB: W: 18                         (SDVO_CMD_GET_OUTPUT_TIMINGS_PART1)
>(II) intel(0): SDVOB: R: 55 AE 56 55 AA 4F 55 BB (Success)
>(II) intel(0): SDVOB: W: 19                         (SDVO_CMD_GET_OUTPUT_TIMINGS_PART2)
>(II) intel(0): SDVOB: R: 55 14 A4 B9 3F 00 00 00 (Success)
>(II) intel(0): SDVOB: W: 11 08 00                   (SDVO_CMD_SET_TARGET_OUTPUT)
>(II) intel(0): SDVOB: R:                         (Success)
>(II) intel(0): SDVOB: W: 18                         (SDVO_CMD_GET_OUTPUT_TIMINGS_PART1)
>(II) intel(0): SDVOB: R: 55 AE 56 55 AA 4F 55 BB (Success)
>(II) intel(0): SDVOB: W: 19                         (SDVO_CMD_GET_OUTPUT_TIMINGS_PART2)
>(II) intel(0): SDVOB: R: 55 14 A4 B9 3F 00 00 00 (Success)
>(II) intel(0): SDVOB: W: 11 10 00                   (SDVO_CMD_SET_TARGET_OUTPUT)
>(II) intel(0): SDVOB: R:                         (Success)
>(II) intel(0): SDVOB: W: 18                         (SDVO_CMD_GET_OUTPUT_TIMINGS_PART1)
>(II) intel(0): SDVOB: R: 55 AE 56 55 AA 4F 55 BB (Success)
>(II) intel(0): SDVOB: W: 19                         (SDVO_CMD_GET_OUTPUT_TIMINGS_PART2)
>(II) intel(0): SDVOB: R: 55 14 A4 B9 3F 00 00 00 (Success)
>(II) intel(0): SDVOB: W: 05 00 00                   (SDVO_CMD_SET_ACTIVE_OUTPUTS)
>(II) intel(0): SDVOB: R:                         (Success)
>(II) intel(0): Fixed memory allocation layout:
>(II) intel(0): 0x006ff000:            end of stolen memory
>(II) intel(0): 0x006ff000-0x0fffffff: DRI memory manager (254980 kB)
>(II) intel(0): 0x10000000:            end of aperture
>(II) intel(0): BO memory allocation layout:
>(II) intel(0): 0x006ff000:            start of memory manager
>(II) intel(0): 0x00800000-0x00ffffff: front buffer (8192 kB) X tiled
>(II) intel(0): 0x01000000-0x01000fff: overlay registers (4 kB)
>(II) intel(0): 0x01100000-0x01109fff: HW cursors (40 kB)
>(II) intel(0): 0x10000000:            end of memory manager
>(WW) intel(0): ESR is 0x00000001, instruction error
>(WW) intel(0): Existing errors found in hardware state.
>(II) intel(0): SDVOB: W: 05 00 00                   (SDVO_CMD_SET_ACTIVE_OUTPUTS)
>(II) intel(0): SDVOB: R:                         (Success)
>(II) intel(0): Mode for pipe A:
>(II) intel(0): Modeline "1280x1024"x60.0  108.00  1280 1328 1440 1688  1024 1025 1028 1066 +hsync +vsync (64.0 kHz)
>(II) intel(0): chosen: dotclock 108000 vco 2160000 ((m 90, m1 14, m2 8), n 2, (p 20, p1 2, p2 10))
>(II) intel(0): SDVOB: W: 05 00 00                   (SDVO_CMD_SET_ACTIVE_OUTPUTS)
>(II) intel(0): SDVOB: R:                         (Success)
>(II) intel(0): Hardware state at EnterVT:
>(II) intel(0): DumpRegsBegin
>(II) intel(0):            CHDECMISC: 0x0000006d (XOR bank, ch2 enh disabled, ch1 enh enabled, ch0 enh enabled, flex disabled, ep present)
>(II) intel(0):               C0DRB0: 0x00100010 (0x0010)
>(II) intel(0):               C0DRB1: 0x00100010 (0x0010)
>(II) intel(0):               C0DRB2: 0x00100010 (0x0010)
>(II) intel(0):               C0DRB3: 0x00860010 (0x0010)
>(II) intel(0):               C1DRB0: 0x00100010 (0x0010)
>(II) intel(0):               C1DRB1: 0x00100010 (0x0010)
>(II) intel(0):               C1DRB2: 0x00100010 (0x0010)
>(II) intel(0):               C1DRB3: 0x00860010 (0x0010)
>(II) intel(0):              C0DRA01: 0x00000086 (0x0086)
>(II) intel(0):              C0DRA23: 0x00000000 (0x0000)
>(II) intel(0):              C1DRA01: 0x00000086 (0x0086)
>(II) intel(0):              C1DRA23: 0x00000000 (0x0000)
>(II) intel(0):           PGETBL_CTL: 0x00000001
>(II) intel(0):    VCLK_DIVISOR_VGA0: 0x00031108 (n = 3, m1 = 17, m2 = 8)
>(II) intel(0):    VCLK_DIVISOR_VGA1: 0x00031406 (n = 3, m1 = 20, m2 = 6)
>(II) intel(0):        VCLK_POST_DIV: 0x00020002 (vga0 p1 = 4, p2 = 2, vga1 p1 = 2, p2 = 2)
>(II) intel(0):            DPLL_TEST: 0x00010001 ()
>(II) intel(0):         CACHE_MODE_0: 0x00006820
>(II) intel(0):              D_STATE: 0x00000000
>(II) intel(0):        DSPCLK_GATE_D: 0x00000000 (clock gates disabled:)
>(II) intel(0):       RENCLK_GATE_D1: 0x00000000
>(II) intel(0):       RENCLK_GATE_D2: 0x00000000
>(II) intel(0):                SDVOB: 0x0030000c (disabled, pipe A, stall disabled, detected)
>(II) intel(0):                SDVOC: 0x00300000 (disabled, pipe A, stall disabled, not detected)
>(II) intel(0):              SDVOUDI: 0x00000000
>(II) intel(0):               DSPARB: 0x00002fdf
>(II) intel(0):               DSPFW1: 0x00000000
>(II) intel(0):               DSPFW2: 0x00000000
>(II) intel(0):               DSPFW3: 0x00000000
>(II) intel(0):                 ADPA: 0x80000018 (enabled, pipe A, +hsync, +vsync)
>(II) intel(0):                 LVDS: 0x00000000 (disabled, pipe A, 18 bit, 1 channel)
>(II) intel(0):                 DVOA: 0x00000000 (disabled, pipe A, no stall, -hsync, -vsync)
>(II) intel(0):                 DVOB: 0x0030000c (disabled, pipe A, no stall, +hsync, -vsync)
>(II) intel(0):                 DVOC: 0x00300000 (disabled, pipe A, no stall, -hsync, -vsync)
>(II) intel(0):          DVOA_SRCDIM: 0x00000000
>(II) intel(0):          DVOB_SRCDIM: 0x00000000
>(II) intel(0):          DVOC_SRCDIM: 0x00000000
>(II) intel(0):           PP_CONTROL: 0x00000000 (power target: off)
>(II) intel(0):            PP_STATUS: 0x00000000 (off, not ready, sequencing idle)
>(II) intel(0):         PP_ON_DELAYS: 0x00000000
>(II) intel(0):        PP_OFF_DELAYS: 0x00000000
>(II) intel(0):           PP_DIVISOR: 0x00000000
>(II) intel(0):         PFIT_CONTROL: 0x00000000
>(II) intel(0):      PFIT_PGM_RATIOS: 0x00000000
>(II) intel(0):      PORT_HOTPLUG_EN: 0x00000020
>(II) intel(0):    PORT_HOTPLUG_STAT: 0x00000b00
>(II) intel(0):             DSPACNTR: 0xd4000000 (enabled, pipe A)
>(II) intel(0):           DSPASTRIDE: 0x00002000 (8192 bytes)
>(II) intel(0):              DSPAPOS: 0x00000000 (0, 0)
>(II) intel(0):             DSPASIZE: 0x03ff04ff (1280, 1024)
>(II) intel(0):             DSPABASE: 0x00800000
>(II) intel(0):             DSPASURF: 0x00000000
>(II) intel(0):          DSPATILEOFF: 0x00000000
>(II) intel(0):            PIPEACONF: 0x80000000 (enabled, single-wide)
>(II) intel(0):             PIPEASRC: 0x04ff03ff (1280, 1024)
>(II) intel(0):            PIPEASTAT: 0x00000203 (status: VSYNC_INT_STATUS VBLANK_INT_STATUS OREG_UPDATE_STATUS)
>(II) intel(0):    PIPEA_GMCH_DATA_M: 0x00000000
>(II) intel(0):    PIPEA_GMCH_DATA_N: 0x00000000
>(II) intel(0):      PIPEA_DP_LINK_M: 0x00000000
>(II) intel(0):      PIPEA_DP_LINK_N: 0x00000000
>(II) intel(0):        CURSOR_A_BASE: 0x01104000
>(II) intel(0):     CURSOR_A_CONTROL: 0x00000000
>(II) intel(0):    CURSOR_A_POSITION: 0x00000000
>(II) intel(0):                 FPA0: 0x00020e08 (n = 2, m1 = 14, m2 = 8)
>(II) intel(0):                 FPA1: 0x00031108 (n = 3, m1 = 17, m2 = 8)
>(II) intel(0):               DPLL_A: 0x94020000 (enabled, non-dvo, default clock, DAC/serial mode, p1 = 2, p2 = 10, SDVO mult 1)
>(II) intel(0):            DPLL_A_MD: 0x00000000
>(II) intel(0):             HTOTAL_A: 0x069704ff (1280 active, 1688 total)
>(II) intel(0):             HBLANK_A: 0x069704ff (1280 start, 1688 end)
>(II) intel(0):              HSYNC_A: 0x059f052f (1328 start, 1440 end)
>(II) intel(0):             VTOTAL_A: 0x042903ff (1024 active, 1066 total)
>(II) intel(0):             VBLANK_A: 0x042903ff (1024 start, 1066 end)
>(II) intel(0):              VSYNC_A: 0x04030400 (1025 start, 1028 end)
>(II) intel(0):            BCLRPAT_A: 0x00000000
>(II) intel(0):         VSYNCSHIFT_A: 0x00000000
>(II) intel(0):             DSPBCNTR: 0x01000000 (disabled, pipe B)
>(II) intel(0):           DSPBSTRIDE: 0x00000000 (0 bytes)
>(II) intel(0):              DSPBPOS: 0x00000000 (0, 0)
>(II) intel(0):             DSPBSIZE: 0x00000000 (1, 1)
>(II) intel(0):             DSPBBASE: 0x00000000
>(II) intel(0):             DSPBSURF: 0x00000000
>(II) intel(0):          DSPBTILEOFF: 0x00000000
>(II) intel(0):            PIPEBCONF: 0x00000000 (disabled, single-wide)
>(II) intel(0):             PIPEBSRC: 0x027f01df (640, 480)
>(II) intel(0):            PIPEBSTAT: 0x00000000 (status:)
>(II) intel(0):    PIPEB_GMCH_DATA_M: 0x00000000
>(II) intel(0):    PIPEB_GMCH_DATA_N: 0x00000000
>(II) intel(0):      PIPEB_DP_LINK_M: 0x00000000
>(II) intel(0):      PIPEB_DP_LINK_N: 0x00000000
>(II) intel(0):        CURSOR_B_BASE: 0x01109000
>(II) intel(0):     CURSOR_B_CONTROL: 0x10000000
>(II) intel(0):    CURSOR_B_POSITION: 0x00000000
>(II) intel(0):                 FPB0: 0x00031108 (n = 3, m1 = 17, m2 = 8)
>(II) intel(0):                 FPB1: 0x00031108 (n = 3, m1 = 17, m2 = 8)
>(II) intel(0):               DPLL_B: 0x04800003 (disabled, non-dvo, VGA, default clock, DAC/serial mode, p1 = 8, p2 = 10, SDVO mult 1)
>(II) intel(0):            DPLL_B_MD: 0x00000000
>(II) intel(0):             HTOTAL_B: 0x031f027f (640 active, 800 total)
>(II) intel(0):             HBLANK_B: 0x03170287 (648 start, 792 end)
>(II) intel(0):              HSYNC_B: 0x02ef028f (656 start, 752 end)
>(II) intel(0):             VTOTAL_B: 0x020c01df (480 active, 525 total)
>(II) intel(0):             VBLANK_B: 0x020401e7 (488 start, 517 end)
>(II) intel(0):              VSYNC_B: 0x01eb01e9 (490 start, 492 end)
>(II) intel(0):            BCLRPAT_B: 0x00000000
>(II) intel(0):         VSYNCSHIFT_B: 0x00000000
>(II) intel(0):    VCLK_DIVISOR_VGA0: 0x00031108
>(II) intel(0):    VCLK_DIVISOR_VGA1: 0x00031406
>(II) intel(0):        VCLK_POST_DIV: 0x00020002
>(II) intel(0):             VGACNTRL: 0x80000000 (disabled)
>(II) intel(0):               TV_CTL: 0x00000000
>(II) intel(0):               TV_DAC: 0x00000000
>(II) intel(0):             TV_CSC_Y: 0x00000000
>(II) intel(0):            TV_CSC_Y2: 0x00000000
>(II) intel(0):             TV_CSC_U: 0x00000000
>(II) intel(0):            TV_CSC_U2: 0x00000000
>(II) intel(0):             TV_CSC_V: 0x00000000
>(II) intel(0):            TV_CSC_V2: 0x00000000
>(II) intel(0):         TV_CLR_KNOBS: 0x00000000
>(II) intel(0):         TV_CLR_LEVEL: 0x00000000
>(II) intel(0):           TV_H_CTL_1: 0x00000000
>(II) intel(0):           TV_H_CTL_2: 0x00000000
>(II) intel(0):           TV_H_CTL_3: 0x00000000
>(II) intel(0):           TV_V_CTL_1: 0x00000000
>(II) intel(0):           TV_V_CTL_2: 0x00000000
>(II) intel(0):           TV_V_CTL_3: 0x00000000
>(II) intel(0):           TV_V_CTL_4: 0x00000000
>(II) intel(0):           TV_V_CTL_5: 0x00000000
>(II) intel(0):           TV_V_CTL_6: 0x00000000
>(II) intel(0):           TV_V_CTL_7: 0x00000000
>(II) intel(0):          TV_SC_CTL_1: 0x00000000
>(II) intel(0):          TV_SC_CTL_2: 0x00000000
>(II) intel(0):          TV_SC_CTL_3: 0x00000000
>(II) intel(0):           TV_WIN_POS: 0x00000000
>(II) intel(0):          TV_WIN_SIZE: 0x00000000
>(II) intel(0):      TV_FILTER_CTL_1: 0x00000000
>(II) intel(0):      TV_FILTER_CTL_2: 0x00000000
>(II) intel(0):      TV_FILTER_CTL_3: 0x00000000
>(II) intel(0):        TV_CC_CONTROL: 0x00000000
>(II) intel(0):           TV_CC_DATA: 0x00000000
>(II) intel(0):          TV_H_LUMA_0: 0x00000000
>(II) intel(0):         TV_H_LUMA_59: 0x00000000
>(II) intel(0):        TV_H_CHROMA_0: 0x00000000
>(II) intel(0):       TV_H_CHROMA_59: 0x00000000
>(II) intel(0):         FBC_CFB_BASE: 0xffffffff
>(II) intel(0):          FBC_LL_BASE: 0xffffffff
>(II) intel(0):          FBC_CONTROL: 0xffffffff
>(II) intel(0):          FBC_COMMAND: 0xffffffff
>(II) intel(0):           FBC_STATUS: 0xffffffff
>(II) intel(0):         FBC_CONTROL2: 0xffffffff
>(II) intel(0):        FBC_FENCE_OFF: 0xffffffff
>(II) intel(0):          FBC_MOD_NUM: 0xffffffff
>(II) intel(0):              MI_MODE: 0x00000200
>(II) intel(0):         MI_ARB_STATE: 0x00000040
>(II) intel(0):       MI_RDRET_STATE: 0x00000000
>(II) intel(0):              ECOSKPD: 0x00000307
>(II) intel(0):                 DP_B: 0x00000000
>(II) intel(0):       DPB_AUX_CH_CTL: 0x00000000
>(II) intel(0):     DPB_AUX_CH_DATA1: 0x00000000
>(II) intel(0):     DPB_AUX_CH_DATA2: 0x00000000
>(II) intel(0):     DPB_AUX_CH_DATA3: 0x00000000
>(II) intel(0):     DPB_AUX_CH_DATA4: 0x00000000
>(II) intel(0):     DPB_AUX_CH_DATA5: 0x00000000
>(II) intel(0):                 DP_C: 0x00000000
>(II) intel(0):       DPC_AUX_CH_CTL: 0x00000000
>(II) intel(0):     DPC_AUX_CH_DATA1: 0x00000000
>(II) intel(0):     DPC_AUX_CH_DATA2: 0x00000000
>(II) intel(0):     DPC_AUX_CH_DATA3: 0x00000000
>(II) intel(0):     DPC_AUX_CH_DATA4: 0x00000000
>(II) intel(0):     DPC_AUX_CH_DATA5: 0x00000000
>(II) intel(0):                 DP_D: 0x00000000
>(II) intel(0):       DPD_AUX_CH_CTL: 0x00000000
>(II) intel(0):     DPD_AUX_CH_DATA1: 0x00000000
>(II) intel(0):     DPD_AUX_CH_DATA2: 0x00000000
>(II) intel(0):     DPD_AUX_CH_DATA3: 0x00000000
>(II) intel(0):     DPD_AUX_CH_DATA4: 0x00000000
>(II) intel(0):     DPD_AUX_CH_DATA5: 0x00000000
>(II) intel(0):           AUD_CONFIG: 0x00000000
>(II) intel(0):     AUD_HDMIW_STATUS: 0x00000000
>(II) intel(0):       AUD_CONV_CHCNT: 0x00000000
>(II) intel(0):        VIDEO_DIP_CTL: 0x00000000
>(II) intel(0):        AUD_PINW_CNTR: 0x00000000
>(II) intel(0):          AUD_CNTL_ST: 0x00000000
>(II) intel(0):          AUD_PIN_CAP: 0x00000000
>(II) intel(0):         AUD_PINW_CAP: 0x00000000
>(II) intel(0):   AUD_PINW_UNSOLRESP: 0x00000000
>(II) intel(0):     AUD_OUT_DIG_CNVT: 0x00000000
>(II) intel(0):        AUD_OUT_CWCAP: 0x00000000
>(II) intel(0):          AUD_GRP_CAP: 0x00000000
>(II) intel(0):             FENCE  0: 0x00800341 ( enabled, X tiled,   32 pitch, 0x00800000 - 0x00c00000 (4096kb))
>(II) intel(0):             FENCE  1: 0x00000000 (disabled, X tiled,    0 pitch, 0x00000000 - 0x00000000 (0kb))
>(II) intel(0):             FENCE  2: 0x00000000 (disabled, X tiled,    0 pitch, 0x00000000 - 0x00000000 (0kb))
>(II) intel(0):             FENCE  3: 0x00000000 (disabled, X tiled,    0 pitch, 0x00000000 - 0x00000000 (0kb))
>(II) intel(0):             FENCE  4: 0x00000000 (disabled, X tiled,    0 pitch, 0x00000000 - 0x00000000 (0kb))
>(II) intel(0):             FENCE  5: 0x00000000 (disabled, X tiled,    0 pitch, 0x00000000 - 0x00000000 (0kb))
>(II) intel(0):             FENCE  6: 0x00000000 (disabled, X tiled,    0 pitch, 0x00000000 - 0x00000000 (0kb))
>(II) intel(0):             FENCE  7: 0x00000000 (disabled, X tiled,    0 pitch, 0x00000000 - 0x00000000 (0kb))
>(II) intel(0):             FENCE  8: 0x00000000 (disabled, X tiled,    0 pitch, 0x00000000 - 0x00000000 (0kb))
>(II) intel(0):             FENCE  9: 0x00000000 (disabled, X tiled,    0 pitch, 0x00000000 - 0x00000000 (0kb))
>(II) intel(0):            FENCE  10: 0x00000000 (disabled, X tiled,    0 pitch, 0x00000000 - 0x00000000 (0kb))
>(II) intel(0):            FENCE  11: 0x00000000 (disabled, X tiled,    0 pitch, 0x00000000 - 0x00000000 (0kb))
>(II) intel(0):            FENCE  12: 0x00000000 (disabled, X tiled,    0 pitch, 0x00000000 - 0x00000000 (0kb))
>(II) intel(0):            FENCE  13: 0x00000000 (disabled, X tiled,    0 pitch, 0x00000000 - 0x00000000 (0kb))
>(II) intel(0):            FENCE  14: 0x00000000 (disabled, X tiled,    0 pitch, 0x00000000 - 0x00000000 (0kb))
>(II) intel(0):            FENCE  15: 0x00000000 (disabled, X tiled,    0 pitch, 0x00000000 - 0x00000000 (0kb))
>(II) intel(0): pipe A dot 108000 n 2 m1 14 m2 8 p1 2 p2 10
>(II) intel(0): pipe B dot 25200 n 3 m1 17 m2 8 p1 8 p2 10
>(II) intel(0): DumpRegsEnd
>(II) intel(0): Output configuration:
>(II) intel(0):   Pipe A is on
>(II) intel(0):   Display plane A is now enabled and connected to pipe A.
>(II) intel(0):   Pipe B is off
>(II) intel(0):   Display plane B is now disabled and connected to pipe B.
>(II) intel(0):   Output VGA is connected to pipe A
>(II) intel(0):   Output TMDS-1 is connected to pipe none
>(II) intel(0): RandR 1.2 enabled, ignore the following RandR disabled message.
>(**) intel(0): DPMS enabled
>(==) intel(0): Intel XvMC decoder disabled
>(II) intel(0): Set up overlay video
>(II) intel(0): direct rendering: Disabled
>(WW) intel(0): Option "PreferredMode" is not used
>(WW) intel(0): Option "Position" is not used
>(--) RandR disabled
>(II) Initializing built-in extension Generic Event Extension
>(II) Initializing built-in extension SHAPE
>(II) Initializing built-in extension MIT-SHM
>(II) Initializing built-in extension XInputExtension
>(II) Initializing built-in extension XTEST
>(II) Initializing built-in extension BIG-REQUESTS
>(II) Initializing built-in extension SYNC
>(II) Initializing built-in extension XKEYBOARD
>(II) Initializing built-in extension XC-MISC
>(II) Initializing built-in extension SECURITY
>(II) Initializing built-in extension XINERAMA
>(II) Initializing built-in extension XFIXES
>(II) Initializing built-in extension RENDER
>(II) Initializing built-in extension RANDR
>(II) Initializing built-in extension COMPOSITE
>(II) Initializing built-in extension DAMAGE
>record: RECORD extension enabled at configure time.
>record: This extension is known to be broken, disabling extension now..
>record: http://bugs.freedesktop.org/show_bug.cgi?id=20500
>(II) AIGLX: Screen 0 is not DRI2 capable
>(II) AIGLX: Screen 0 is not DRI capable
>(II) AIGLX: Loaded and initialized /usr/lib/xorg/modules/dri/swrast_dri.so
>(II) GLX: Initialized DRISWRAST GL provider for screen 0
>(II) intel(0): Setting screen physical size to 338 x 270
>(II) intel(0): Allocate new frame buffer 1280x1024 stride 2048
>(II) intel(0): New front buffer at 0x1400000
>(II) config/hal: Adding input device Macintosh mouse button emulation
>(II) LoadModule: "evdev"
>(II) Loading /usr/lib/xorg/modules/input/evdev_drv.so
>(II) Module evdev: vendor="X.Org Foundation"
>	compiled for 1.7.0.901, module version = 2.2.99
>	Module class: X.Org XInput Driver
>	ABI class: X.Org XInput driver, version 7.0
>(**) Macintosh mouse button emulation: always reports core events
>(**) Macintosh mouse button emulation: Device: "/dev/input/event0"
>(II) Macintosh mouse button emulation: Found 3 mouse buttons
>(II) Macintosh mouse button emulation: found relative axes
>(II) Macintosh mouse button emulation: Found x and y relative axes
>(II) Macintosh mouse button emulation: Configuring as mouse
>(**) Macintosh mouse button emulation: YAxisMapping: buttons 4 and 5
>(**) Macintosh mouse button emulation: EmulateWheelButton: 4, EmulateWheelInertia: 10, EmulateWheelTimeout: 200
>(II) XINPUT: Adding extended input device "Macintosh mouse button emulation" (type: MOUSE)
>(**) Macintosh mouse button emulation: (accel) keeping acceleration scheme 1
>(**) Macintosh mouse button emulation: (accel) acceleration profile 0
>(II) Macintosh mouse button emulation: initialized for relative axes.
>(II) config/hal: Adding input device USB Optical Mouse
>(**) USB Optical Mouse: always reports core events
>(**) USB Optical Mouse: Device: "/dev/input/event5"
>(II) USB Optical Mouse: Found 3 mouse buttons
>(II) USB Optical Mouse: Found scroll wheel(s)
>(II) USB Optical Mouse: found relative axes
>(II) USB Optical Mouse: Found x and y relative axes
>(II) USB Optical Mouse: Configuring as mouse
>(**) USB Optical Mouse: YAxisMapping: buttons 4 and 5
>(**) USB Optical Mouse: EmulateWheelButton: 4, EmulateWheelInertia: 10, EmulateWheelTimeout: 200
>(II) XINPUT: Adding extended input device "USB Optical Mouse" (type: MOUSE)
>(**) USB Optical Mouse: (accel) keeping acceleration scheme 1
>(**) USB Optical Mouse: (accel) acceleration profile 0
>(II) USB Optical Mouse: initialized for relative axes.
>(II) config/hal: Adding input device UVC Camera (046d:0990)
>(**) UVC Camera (046d:0990): always reports core events
>(**) UVC Camera (046d:0990): Device: "/dev/input/event4"
>(II) UVC Camera (046d:0990): Found keys
>(II) UVC Camera (046d:0990): Configuring as keyboard
>(II) XINPUT: Adding extended input device "UVC Camera (046d:0990)" (type: KEYBOARD)
>(**) Option "xkb_rules" "evdev"
>(**) Option "xkb_model" "evdev"
>(**) Option "xkb_layout" "us,ro"
>(**) Option "xkb_variant" ",std"
>(**) Option "xkb_options" "grp:alt_shift_toggle"
>(II) config/hal: Adding input device LITE-ON Technology USB NetVista Full Width Keyboard.
>(**) LITE-ON Technology USB NetVista Full Width Keyboard.: always reports core events
>(**) LITE-ON Technology USB NetVista Full Width Keyboard.: Device: "/dev/input/event6"
>(II) LITE-ON Technology USB NetVista Full Width Keyboard.: Found keys
>(II) LITE-ON Technology USB NetVista Full Width Keyboard.: Configuring as keyboard
>(II) XINPUT: Adding extended input device "LITE-ON Technology USB NetVista Full Width Keyboard." (type: KEYBOARD)
>(**) Option "xkb_rules" "evdev"
>(**) Option "xkb_model" "evdev"
>(**) Option "xkb_layout" "us,ro"
>(**) Option "xkb_variant" ",std"
>(**) Option "xkb_options" "grp:alt_shift_toggle"
>(II) config/hal: Adding input device Power Button
>(**) Power Button: always reports core events
>(**) Power Button: Device: "/dev/input/event2"
>(II) Power Button: Found keys
>(II) Power Button: Configuring as keyboard
>(II) XINPUT: Adding extended input device "Power Button" (type: KEYBOARD)
>(**) Option "xkb_rules" "evdev"
>(**) Option "xkb_model" "evdev"
>(**) Option "xkb_layout" "us,ro"
>(**) Option "xkb_variant" ",std"
>(**) Option "xkb_options" "grp:alt_shift_toggle"
>(II) config/hal: Adding input device Power Button
>(**) Power Button: always reports core events
>(**) Power Button: Device: "/dev/input/event1"
>(II) Power Button: Found keys
>(II) Power Button: Configuring as keyboard
>(II) XINPUT: Adding extended input device "Power Button" (type: KEYBOARD)
>(**) Option "xkb_rules" "evdev"
>(**) Option "xkb_model" "evdev"
>(**) Option "xkb_layout" "us,ro"
>(**) Option "xkb_variant" ",std"
>(**) Option "xkb_options" "grp:alt_shift_toggle"
>(II) intel(0): SDVOB: W: 05 00 00                   (SDVO_CMD_SET_ACTIVE_OUTPUTS)
>(II) intel(0): SDVOB: R:                         (Success)
>(II) intel(0): SDVOB: W: 05 00 00                   (SDVO_CMD_SET_ACTIVE_OUTPUTS)
>(II) intel(0): SDVOB: R:                         (Success)
>(II) intel(0): SDVOB: W: 11 01 00                   (SDVO_CMD_SET_TARGET_OUTPUT)
>(II) intel(0): SDVOB: R:                         (Success)
>(II) intel(0): SDVOB: W: 16 D6 09 80 A0 20 E0 2D 10 (SDVO_CMD_SET_OUTPUT_TIMINGS_PART1)
>(II) intel(0): SDVOB: R:                         (Success)
>(II) intel(0): SDVOB: W: 17 10 60 A2 00 1C 00 00 00 (SDVO_CMD_SET_OUTPUT_TIMINGS_PART2)
>(II) intel(0): SDVOB: R:                         (Success)
>(II) intel(0): SDVOB: W: 11 02 00                   (SDVO_CMD_SET_TARGET_OUTPUT)
>(II) intel(0): SDVOB: R:                         (Success)
>(II) intel(0): SDVOB: W: 16 95 AE 97 51 BB 52 B5 EB (SDVO_CMD_SET_OUTPUT_TIMINGS_PART1)
>(II) intel(0): SDVOB: R:                         (Success)
>(II) intel(0): SDVOB: W: 17 5C F5 C4 AD AA 00 00 00 (SDVO_CMD_SET_OUTPUT_TIMINGS_PART2)
>(II) intel(0): SDVOB: R:                         (Success)
>(II) intel(0): SDVOB: W: 11 04 00                   (SDVO_CMD_SET_TARGET_OUTPUT)
>(II) intel(0): SDVOB: R:                         (Success)
>(II) intel(0): SDVOB: W: 16 55 AE 56 55 AA 4F 55 BB (SDVO_CMD_SET_OUTPUT_TIMINGS_PART1)
>(II) intel(0): SDVOB: R:                         (Invalid arg)
>(II) intel(0): SDVOB: W: 11 08 00                   (SDVO_CMD_SET_TARGET_OUTPUT)
>(II) intel(0): SDVOB: R:                         (Success)
>(II) intel(0): SDVOB: W: 16 55 AE 56 55 AA 4F 55 BB (SDVO_CMD_SET_OUTPUT_TIMINGS_PART1)
>(II) intel(0): SDVOB: R:                         (Invalid arg)
>(II) intel(0): SDVOB: W: 11 10 00                   (SDVO_CMD_SET_TARGET_OUTPUT)
>(II) intel(0): SDVOB: R:                         (Success)
>(II) intel(0): SDVOB: W: 16 55 AE 56 55 AA 4F 55 BB (SDVO_CMD_SET_OUTPUT_TIMINGS_PART1)
>(II) intel(0): SDVOB: R:                         (Invalid arg)
>(II) intel(0): SDVOB: W: 10 00                      (SDVO_CMD_SET_TARGET_INPUT)
>(II) intel(0): SDVOB: R:                         (Success)
>(II) intel(0): SDVOB: W: 14 D6 09 80 A0 20 E0 2D 10 (SDVO_CMD_SET_INPUT_TIMINGS_PART1)
>(II) intel(0): SDVOB: R:                         (Success)
>(II) intel(0): SDVOB: W: 15 10 60 A2 00 18 00 00 00 (SDVO_CMD_SET_INPUT_TIMINGS_PART2)
>(II) intel(0): SDVOB: R:                         (Success)
>(II) intel(0): SDVOB: W: 10 01                      (SDVO_CMD_SET_TARGET_INPUT)
>(II) intel(0): SDVOB: R:                         (Success)
>(II) intel(0): SDVOB: W: 14 10 00 60 02 0A 5F D1 CA (SDVO_CMD_SET_INPUT_TIMINGS_PART1)
>(II) intel(0): SDVOB: R:                         (Invalid arg)
>(II) intel(0): SDVOB: W: 21 08                      (SDVO_CMD_SET_CLOCK_RATE_MULT)
>(II) intel(0): SDVOB: R:                         (Success)
>(II) intel(0): SDVOB: W: 03                         (SDVO_CMD_GET_TRAINED_INPUTS)
>(II) intel(0): SDVOB: R: 01                      (Success)
>(II) intel(0): SDVOB: W: 05 01 00                   (SDVO_CMD_SET_ACTIVE_OUTPUTS)
>(II) intel(0): SDVOB: R:                         (Success)
>(II) intel(0): Comparing regs from server start up to After LeaveVT
>(WW) intel(0): Register 0x70024 (PIPEASTAT) changed from 0x00000203 to 0x80000203
>(WW) intel(0): PIPEASTAT before: status: VSYNC_INT_STATUS VBLANK_INT_STATUS OREG_UPDATE_STATUS
>(WW) intel(0): PIPEASTAT after: status: FIFO_UNDERRUN VSYNC_INT_STATUS VBLANK_INT_STATUS OREG_UPDATE_STATUS
>(WW) intel(0): Register 0x2004 (FENCE  1) changed from 0x00000000 to 0x01400231
>(WW) intel(0): FENCE  1 before: disabled, X tiled,    0 pitch, 0x00000000 - 0x00000000 (0kb)
>(WW) intel(0): FENCE  1 after:  enabled, X tiled,   16 pitch, 0x01400000 - 0x01600000 (2048kb)
>(II) intel(0): DumpRegsBegin
>(II) intel(0):            CHDECMISC: 0x0000006d (XOR bank, ch2 enh disabled, ch1 enh enabled, ch0 enh enabled, flex disabled, ep present)
>(II) intel(0):               C0DRB0: 0x00100010 (0x0010)
>(II) intel(0):               C0DRB1: 0x00100010 (0x0010)
>(II) intel(0):               C0DRB2: 0x00100010 (0x0010)
>(II) intel(0):               C0DRB3: 0x00860010 (0x0010)
>(II) intel(0):               C1DRB0: 0x00100010 (0x0010)
>(II) intel(0):               C1DRB1: 0x00100010 (0x0010)
>(II) intel(0):               C1DRB2: 0x00100010 (0x0010)
>(II) intel(0):               C1DRB3: 0x00860010 (0x0010)
>(II) intel(0):              C0DRA01: 0x00000086 (0x0086)
>(II) intel(0):              C0DRA23: 0x00000000 (0x0000)
>(II) intel(0):              C1DRA01: 0x00000086 (0x0086)
>(II) intel(0):              C1DRA23: 0x00000000 (0x0000)
>(II) intel(0):           PGETBL_CTL: 0x00000001
>(II) intel(0):    VCLK_DIVISOR_VGA0: 0x00031108 (n = 3, m1 = 17, m2 = 8)
>(II) intel(0):    VCLK_DIVISOR_VGA1: 0x00031406 (n = 3, m1 = 20, m2 = 6)
>(II) intel(0):        VCLK_POST_DIV: 0x00020002 (vga0 p1 = 4, p2 = 2, vga1 p1 = 2, p2 = 2)
>(II) intel(0):            DPLL_TEST: 0x00010001 ()
>(II) intel(0):         CACHE_MODE_0: 0x00006820
>(II) intel(0):              D_STATE: 0x00000000
>(II) intel(0):        DSPCLK_GATE_D: 0x00000000 (clock gates disabled:)
>(II) intel(0):       RENCLK_GATE_D1: 0x00000000
>(II) intel(0):       RENCLK_GATE_D2: 0x00000000
>(II) intel(0):                SDVOB: 0x8030000c (enabled, pipe A, stall disabled, detected)
>(II) intel(0):                SDVOC: 0x00300000 (disabled, pipe A, stall disabled, not detected)
>(II) intel(0):              SDVOUDI: 0x00000000
>(II) intel(0):               DSPARB: 0x00001d9c
>(II) intel(0):               DSPFW1: 0x00000000
>(II) intel(0):               DSPFW2: 0x00000000
>(II) intel(0):               DSPFW3: 0x00000000
>(II) intel(0):                 ADPA: 0x80000000 (enabled, pipe A, -hsync, -vsync)
>(II) intel(0):                 LVDS: 0x00000000 (disabled, pipe A, 18 bit, 1 channel)
>(II) intel(0):                 DVOA: 0x00000000 (disabled, pipe A, no stall, -hsync, -vsync)
>(II) intel(0):                 DVOB: 0x8030000c (enabled, pipe A, no stall, +hsync, -vsync)
>(II) intel(0):                 DVOC: 0x00300000 (disabled, pipe A, no stall, -hsync, -vsync)
>(II) intel(0):          DVOA_SRCDIM: 0x00000000
>(II) intel(0):          DVOB_SRCDIM: 0x00000000
>(II) intel(0):          DVOC_SRCDIM: 0x00000000
>(II) intel(0):           PP_CONTROL: 0x00000000 (power target: off)
>(II) intel(0):            PP_STATUS: 0x00000000 (off, not ready, sequencing idle)
>(II) intel(0):         PP_ON_DELAYS: 0x00000000
>(II) intel(0):        PP_OFF_DELAYS: 0x00000000
>(II) intel(0):           PP_DIVISOR: 0x00000000
>(II) intel(0):         PFIT_CONTROL: 0x00000000
>(II) intel(0):      PFIT_PGM_RATIOS: 0x00000000
>(II) intel(0):      PORT_HOTPLUG_EN: 0x00000020
>(II) intel(0):    PORT_HOTPLUG_STAT: 0x00000b00
>(II) intel(0):             DSPACNTR: 0x18000000 (disabled, pipe A)
>(II) intel(0):           DSPASTRIDE: 0x00001400 (5120 bytes)
>(II) intel(0):              DSPAPOS: 0x00000000 (0, 0)
>(II) intel(0):             DSPASIZE: 0x018f02cf (720, 400)
>(II) intel(0):             DSPABASE: 0x00000000
>(II) intel(0):             DSPASURF: 0x00000000
>(II) intel(0):          DSPATILEOFF: 0x00000000
>(II) intel(0):            PIPEACONF: 0x80000000 (enabled, single-wide)
>(II) intel(0):             PIPEASRC: 0x027f01df (640, 480)
>(II) intel(0):            PIPEASTAT: 0x80000203 (status: FIFO_UNDERRUN VSYNC_INT_STATUS VBLANK_INT_STATUS OREG_UPDATE_STATUS)
>(II) intel(0):    PIPEA_GMCH_DATA_M: 0x00000000
>(II) intel(0):    PIPEA_GMCH_DATA_N: 0x00000000
>(II) intel(0):      PIPEA_DP_LINK_M: 0x00000000
>(II) intel(0):      PIPEA_DP_LINK_N: 0x00000000
>(II) intel(0):        CURSOR_A_BASE: 0x00000000
>(II) intel(0):     CURSOR_A_CONTROL: 0x00000000
>(II) intel(0):    CURSOR_A_POSITION: 0x00000000
>(II) intel(0):                 FPA0: 0x00021509 (n = 2, m1 = 21, m2 = 9)
>(II) intel(0):                 FPA1: 0x00031108 (n = 3, m1 = 17, m2 = 8)
>(II) intel(0):               DPLL_A: 0xd4040033 (enabled, dvo, default clock, DAC/serial mode, p1 = 3, p2 = 10, SDVO mult 4)
>(II) intel(0):            DPLL_A_MD: 0x00000000
>(II) intel(0):             HTOTAL_A: 0x031f027f (640 active, 800 total)
>(II) intel(0):             HBLANK_A: 0x031f027f (640 start, 800 end)
>(II) intel(0):              HSYNC_A: 0x02ef028f (656 start, 752 end)
>(II) intel(0):             VTOTAL_A: 0x020c01df (480 active, 525 total)
>(II) intel(0):             VBLANK_A: 0x020c01df (480 start, 525 end)
>(II) intel(0):              VSYNC_A: 0x01eb01e9 (490 start, 492 end)
>(II) intel(0):            BCLRPAT_A: 0x00000000
>(II) intel(0):         VSYNCSHIFT_A: 0x00000000
>(II) intel(0):             DSPBCNTR: 0x01000000 (disabled, pipe B)
>(II) intel(0):           DSPBSTRIDE: 0x00000000 (0 bytes)
>(II) intel(0):              DSPBPOS: 0x00000000 (0, 0)
>(II) intel(0):             DSPBSIZE: 0x00000000 (1, 1)
>(II) intel(0):             DSPBBASE: 0x00000000
>(II) intel(0):             DSPBSURF: 0x00000000
>(II) intel(0):          DSPBTILEOFF: 0x00000000
>(II) intel(0):            PIPEBCONF: 0x00000000 (disabled, single-wide)
>(II) intel(0):             PIPEBSRC: 0x027f01df (640, 480)
>(II) intel(0):            PIPEBSTAT: 0x00000000 (status:)
>(II) intel(0):    PIPEB_GMCH_DATA_M: 0x00000000
>(II) intel(0):    PIPEB_GMCH_DATA_N: 0x00000000
>(II) intel(0):      PIPEB_DP_LINK_M: 0x00000000
>(II) intel(0):      PIPEB_DP_LINK_N: 0x00000000
>(II) intel(0):        CURSOR_B_BASE: 0x00000000
>(II) intel(0):     CURSOR_B_CONTROL: 0x00000000
>(II) intel(0):    CURSOR_B_POSITION: 0x00000000
>(II) intel(0):                 FPB0: 0x00031108 (n = 3, m1 = 17, m2 = 8)
>(II) intel(0):                 FPB1: 0x00031108 (n = 3, m1 = 17, m2 = 8)
>(II) intel(0):               DPLL_B: 0x04800003 (disabled, non-dvo, VGA, default clock, DAC/serial mode, p1 = 8, p2 = 10, SDVO mult 1)
>(II) intel(0):            DPLL_B_MD: 0x00000000
>(II) intel(0):             HTOTAL_B: 0x031f027f (640 active, 800 total)
>(II) intel(0):             HBLANK_B: 0x03170287 (648 start, 792 end)
>(II) intel(0):              HSYNC_B: 0x02ef028f (656 start, 752 end)
>(II) intel(0):             VTOTAL_B: 0x020c01df (480 active, 525 total)
>(II) intel(0):             VBLANK_B: 0x020401e7 (488 start, 517 end)
>(II) intel(0):              VSYNC_B: 0x01eb01e9 (490 start, 492 end)
>(II) intel(0):            BCLRPAT_B: 0x00000000
>(II) intel(0):         VSYNCSHIFT_B: 0x00000000
>(II) intel(0):    VCLK_DIVISOR_VGA0: 0x00031108
>(II) intel(0):    VCLK_DIVISOR_VGA1: 0x00031406
>(II) intel(0):        VCLK_POST_DIV: 0x00020002
>(II) intel(0):             VGACNTRL: 0x0124008e (enabled)
>(II) intel(0):               TV_CTL: 0x00000000
>(II) intel(0):               TV_DAC: 0x00000000
>(II) intel(0):             TV_CSC_Y: 0x00000000
>(II) intel(0):            TV_CSC_Y2: 0x00000000
>(II) intel(0):             TV_CSC_U: 0x00000000
>(II) intel(0):            TV_CSC_U2: 0x00000000
>(II) intel(0):             TV_CSC_V: 0x00000000
>(II) intel(0):            TV_CSC_V2: 0x00000000
>(II) intel(0):         TV_CLR_KNOBS: 0x00000000
>(II) intel(0):         TV_CLR_LEVEL: 0x00000000
>(II) intel(0):           TV_H_CTL_1: 0x00000000
>(II) intel(0):           TV_H_CTL_2: 0x00000000
>(II) intel(0):           TV_H_CTL_3: 0x00000000
>(II) intel(0):           TV_V_CTL_1: 0x00000000
>(II) intel(0):           TV_V_CTL_2: 0x00000000
>(II) intel(0):           TV_V_CTL_3: 0x00000000
>(II) intel(0):           TV_V_CTL_4: 0x00000000
>(II) intel(0):           TV_V_CTL_5: 0x00000000
>(II) intel(0):           TV_V_CTL_6: 0x00000000
>(II) intel(0):           TV_V_CTL_7: 0x00000000
>(II) intel(0):          TV_SC_CTL_1: 0x00000000
>(II) intel(0):          TV_SC_CTL_2: 0x00000000
>(II) intel(0):          TV_SC_CTL_3: 0x00000000
>(II) intel(0):           TV_WIN_POS: 0x00000000
>(II) intel(0):          TV_WIN_SIZE: 0x00000000
>(II) intel(0):      TV_FILTER_CTL_1: 0x00000000
>(II) intel(0):      TV_FILTER_CTL_2: 0x00000000
>(II) intel(0):      TV_FILTER_CTL_3: 0x00000000
>(II) intel(0):        TV_CC_CONTROL: 0x00000000
>(II) intel(0):           TV_CC_DATA: 0x00000000
>(II) intel(0):          TV_H_LUMA_0: 0x00000000
>(II) intel(0):         TV_H_LUMA_59: 0x00000000
>(II) intel(0):        TV_H_CHROMA_0: 0x00000000
>(II) intel(0):       TV_H_CHROMA_59: 0x00000000
>(II) intel(0):         FBC_CFB_BASE: 0xffffffff
>(II) intel(0):          FBC_LL_BASE: 0xffffffff
>(II) intel(0):          FBC_CONTROL: 0xffffffff
>(II) intel(0):          FBC_COMMAND: 0xffffffff
>(II) intel(0):           FBC_STATUS: 0xffffffff
>(II) intel(0):         FBC_CONTROL2: 0xffffffff
>(II) intel(0):        FBC_FENCE_OFF: 0xffffffff
>(II) intel(0):          FBC_MOD_NUM: 0xffffffff
>(II) intel(0):              MI_MODE: 0x00000200
>(II) intel(0):         MI_ARB_STATE: 0x00000040
>(II) intel(0):       MI_RDRET_STATE: 0x00000000
>(II) intel(0):              ECOSKPD: 0x00000307
>(II) intel(0):                 DP_B: 0x00000000
>(II) intel(0):       DPB_AUX_CH_CTL: 0x00000000
>(II) intel(0):     DPB_AUX_CH_DATA1: 0x00000000
>(II) intel(0):     DPB_AUX_CH_DATA2: 0x00000000
>(II) intel(0):     DPB_AUX_CH_DATA3: 0x00000000
>(II) intel(0):     DPB_AUX_CH_DATA4: 0x00000000
>(II) intel(0):     DPB_AUX_CH_DATA5: 0x00000000
>(II) intel(0):                 DP_C: 0x00000000
>(II) intel(0):       DPC_AUX_CH_CTL: 0x00000000
>(II) intel(0):     DPC_AUX_CH_DATA1: 0x00000000
>(II) intel(0):     DPC_AUX_CH_DATA2: 0x00000000
>(II) intel(0):     DPC_AUX_CH_DATA3: 0x00000000
>(II) intel(0):     DPC_AUX_CH_DATA4: 0x00000000
>(II) intel(0):     DPC_AUX_CH_DATA5: 0x00000000
>(II) intel(0):                 DP_D: 0x00000000
>(II) intel(0):       DPD_AUX_CH_CTL: 0x00000000
>(II) intel(0):     DPD_AUX_CH_DATA1: 0x00000000
>(II) intel(0):     DPD_AUX_CH_DATA2: 0x00000000
>(II) intel(0):     DPD_AUX_CH_DATA3: 0x00000000
>(II) intel(0):     DPD_AUX_CH_DATA4: 0x00000000
>(II) intel(0):     DPD_AUX_CH_DATA5: 0x00000000
>(II) intel(0):           AUD_CONFIG: 0x00000000
>(II) intel(0):     AUD_HDMIW_STATUS: 0x00000000
>(II) intel(0):       AUD_CONV_CHCNT: 0x00000000
>(II) intel(0):        VIDEO_DIP_CTL: 0x00000000
>(II) intel(0):        AUD_PINW_CNTR: 0x00000000
>(II) intel(0):          AUD_CNTL_ST: 0x00000000
>(II) intel(0):          AUD_PIN_CAP: 0x00000000
>(II) intel(0):         AUD_PINW_CAP: 0x00000000
>(II) intel(0):   AUD_PINW_UNSOLRESP: 0x00000000
>(II) intel(0):     AUD_OUT_DIG_CNVT: 0x00000000
>(II) intel(0):        AUD_OUT_CWCAP: 0x00000000
>(II) intel(0):          AUD_GRP_CAP: 0x00000000
>(II) intel(0):             FENCE  0: 0x00000000 (disabled, X tiled,    0 pitch, 0x00000000 - 0x00000000 (0kb))
>(II) intel(0):             FENCE  1: 0x01400231 ( enabled, X tiled,   16 pitch, 0x01400000 - 0x01600000 (2048kb))
>(II) intel(0):             FENCE  2: 0x00000000 (disabled, X tiled,    0 pitch, 0x00000000 - 0x00000000 (0kb))
>(II) intel(0):             FENCE  3: 0x00000000 (disabled, X tiled,    0 pitch, 0x00000000 - 0x00000000 (0kb))
>(II) intel(0):             FENCE  4: 0x00000000 (disabled, X tiled,    0 pitch, 0x00000000 - 0x00000000 (0kb))
>(II) intel(0):             FENCE  5: 0x00000000 (disabled, X tiled,    0 pitch, 0x00000000 - 0x00000000 (0kb))
>(II) intel(0):             FENCE  6: 0x00000000 (disabled, X tiled,    0 pitch, 0x00000000 - 0x00000000 (0kb))
>(II) intel(0):             FENCE  7: 0x00000000 (disabled, X tiled,    0 pitch, 0x00000000 - 0x00000000 (0kb))
>(II) intel(0):             FENCE  8: 0x00000000 (disabled, X tiled,    0 pitch, 0x00000000 - 0x00000000 (0kb))
>(II) intel(0):             FENCE  9: 0x00000000 (disabled, X tiled,    0 pitch, 0x00000000 - 0x00000000 (0kb))
>(II) intel(0):            FENCE  10: 0x00000000 (disabled, X tiled,    0 pitch, 0x00000000 - 0x00000000 (0kb))
>(II) intel(0):            FENCE  11: 0x00000000 (disabled, X tiled,    0 pitch, 0x00000000 - 0x00000000 (0kb))
>(II) intel(0):            FENCE  12: 0x00000000 (disabled, X tiled,    0 pitch, 0x00000000 - 0x00000000 (0kb))
>(II) intel(0):            FENCE  13: 0x00000000 (disabled, X tiled,    0 pitch, 0x00000000 - 0x00000000 (0kb))
>(II) intel(0):            FENCE  14: 0x00000000 (disabled, X tiled,    0 pitch, 0x00000000 - 0x00000000 (0kb))
>(II) intel(0):            FENCE  15: 0x00000000 (disabled, X tiled,    0 pitch, 0x00000000 - 0x00000000 (0kb))
>(II) intel(0): pipe A dot 100800 n 2 m1 21 m2 9 p1 3 p2 10
>(II) intel(0): pipe B dot 25200 n 3 m1 17 m2 8 p1 8 p2 10
>(II) intel(0): DumpRegsEnd

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Attachments on bug 24522: 30385 | 30386 | 30387 | 30388 | 30390 | 30391 | 30392 | 30393 | 30395 | 30409 | 30442 | 30443 | 30444 | 30475

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