Attachment 30621 Details for Bug 24668 – Hardcode PLL limits when v4.0 limits table found

[patch] Hardcode PLL limits when v4.0 limits table found

pll40.diff (text/plain), 2.64 KB, created by Ben Skeggs on 2009-10-22 04:14:04 UTC

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Creator: Ben Skeggs

Created: 2009-10-22 04:14:04 UTC

Size: 2.64 KB

patch

obsolete

>diff --git a/drivers/gpu/drm/nouveau/nouveau_bios.c b/drivers/gpu/drm/nouveau/nouveau_bios.c
>index e5138ca..db288a0 100644
>--- a/drivers/gpu/drm/nouveau/nouveau_bios.c
>+++ b/drivers/gpu/drm/nouveau/nouveau_bios.c
>@@ -3994,6 +3994,7 @@ int get_pll_limits(struct drm_device *dev, uint32_t limit_match, struct pll_lims
> 	case 0x20:
> 	case 0x21:
> 	case 0x30:
>+	case 0x40:
> 		headerlen = bios->data[bios->pll_limit_tbl_ptr + 1];
> 		recordlen = bios->data[bios->pll_limit_tbl_ptr + 2];
> 		entries = bios->data[bios->pll_limit_tbl_ptr + 3];
>@@ -4142,7 +4143,7 @@ int get_pll_limits(struct drm_device *dev, uint32_t limit_match, struct pll_lims
> 					pll_lim->refclk = 25000;
> 			}
> 		}
>-	} else if (pll_lim_ver) { /* ver 0x30 */
>+	} else if (pll_lim_ver == 0x30) { /* ver 0x30 */
> 		uint8_t *entry = &bios->data[bios->pll_limit_tbl_ptr + headerlen];
> 		uint8_t *record = NULL;
> 		int i;
>@@ -4182,6 +4183,22 @@ int get_pll_limits(struct drm_device *dev, uint32_t limit_match, struct pll_lims
> 		pll_lim->max_usable_log2p = pll_lim->max_log2p = record[25];
> 		pll_lim->log2p_bias = record[27];
> 		pll_lim->refclk = ROM32(record[28]);
>+	} else { /* ver 0x40 */
>+		NV_WARN(dev, "PLL limits table 4.0 not supported\n");
>+		if (reg != 0x614100 && reg != 0x614900)
>+			return -EINVAL;
>+
>+		NV_WARN(dev, "Using hardcoded PLL limits for CRTC\n");
>+		pll_lim->vco1.minfreq = 500000;
>+		pll_lim->vco1.maxfreq = 1000000;
>+		pll_lim->vco1.min_inputfreq = 25000;
>+		pll_lim->vco1.max_inputfreq = 50000;
>+		pll_lim->vco1.min_n = 8;
>+		pll_lim->vco1.max_n = 255;
>+		pll_lim->vco1.min_m = 1;
>+		pll_lim->vco1.max_m = 255;
>+		pll_lim->max_usable_log2p = pll_lim->max_log2p = 6;
>+		pll_lim->refclk = 27000;
> 	}
> 
> 	/*
>diff --git a/drivers/gpu/drm/nouveau/nv50_crtc.c b/drivers/gpu/drm/nouveau/nv50_crtc.c
>index 2bf1a12..980798c 100644
>--- a/drivers/gpu/drm/nouveau/nv50_crtc.c
>+++ b/drivers/gpu/drm/nouveau/nv50_crtc.c
>@@ -274,23 +274,6 @@ nv50_crtc_set_clock(struct drm_device *dev, int head, int pclk)
> 	if (ret)
> 		return ret;
> 
>-	/*XXX: need a vbios image from one of these cards to look at
>-	 *     rather than just guessing.  P isn't log2P on these
>-	 *     cards, it's uncertain at this stage what the PLL
>-	 *     limits tables have to say about these chips.
>-	 *
>-	 *     getPLL_single will need some modifications to calculate
>-	 *     this properly too.
>-	 *
>-	 *     for the moment, hacking up the PLL limits table with
>-	 *     a log2 value matching nv's maximum.
>-	 */
>-	if (!limits.vco2.maxfreq) {
>-		NV_ERROR(dev, "single-stage PLL, please report: %d!!\n",
>-			 limits.max_usable_log2p);
>-		limits.max_usable_log2p = 6;
>-	}
>-
> 	ret = nouveau_calc_pll_mnp(dev, &limits, pclk, &pll);
> 	if (ret <= 0)
> 		return ret;

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Attachments on bug 24668: 30607 | 30609 | 30621 | 30623 | 30711 | 30712 | 31326

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