Attachment 31852 Details for Bug 25506 – manually force SS off except LVDS

[patch] manually force SS off except LVDS

0001-drm-radeon-kms-manually-force-spread-spectrum-off-e.patch (text/plain), 3.13 KB, created by Alex Deucher on 2009-12-08 14:50:14 UTC

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Creator: Alex Deucher

Created: 2009-12-08 14:50:14 UTC

Size: 3.13 KB

patch

obsolete

>From 24213534bc25cd5c98720d03cf0083515feeac35 Mon Sep 17 00:00:00 2001
>From: Alex Deucher <alexdeucher@gmail.com>
>Date: Tue, 8 Dec 2009 17:46:34 -0500
>Subject: [PATCH] drm/radeon/kms: manually force spread spectrum off except LVDS
>
>Just manually force it off unless we are using LVDS, in that case,
>use the atom table.
>
>Should fix fdo bug 25506
>
>Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
>---
> drivers/gpu/drm/radeon/atombios_crtc.c |   36 +++++++++++++++++++++++++++++++-
> drivers/gpu/drm/radeon/radeon_reg.h    |    3 ++
> 2 files changed, 38 insertions(+), 1 deletions(-)
>
>diff --git a/drivers/gpu/drm/radeon/atombios_crtc.c b/drivers/gpu/drm/radeon/atombios_crtc.c
>index 7a8cd93..3b8d079 100644
>--- a/drivers/gpu/drm/radeon/atombios_crtc.c
>+++ b/drivers/gpu/drm/radeon/atombios_crtc.c
>@@ -351,6 +351,38 @@ static void atombios_crtc_set_timing(struct drm_crtc *crtc,
> 	atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
> }
> 
>+static void radeon_disable_ss(struct drm_crtc *crtc)
>+{
>+	struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
>+	struct drm_device *dev = crtc->dev;
>+	struct radeon_device *rdev = dev->dev_private;
>+	u32 ss_cntl, lvds_ss_cntl;
>+
>+	if (ASIC_IS_AVIVO(rdev)) {
>+		if (radeon_crtc->crtc_id == 0) {
>+			ss_cntl = RREG32(AVIVO_P1PLL_INT_SS_CNTL);
>+			WREG32(AVIVO_P1PLL_INT_SS_CNTL, ss_cntl & ~1);
>+		} else {
>+			ss_cntl = RREG32(AVIVO_P2PLL_INT_SS_CNTL);
>+			WREG32(AVIVO_P2PLL_INT_SS_CNTL, ss_cntl & ~1);
>+		}
>+	} else {
>+		ss_cntl = RREG32_PLL(RADEON_SS_INT_CNTL);
>+		lvds_ss_cntl = RREG32(RADEON_LVDS_SS_GEN_CNTL);
>+		if (radeon_crtc->crtc_id == 0) {
>+			if (!(ss_cntl & RADEON_SS_INT_SEL))
>+				WREG32_PLL(RADEON_SS_INT_CNTL, ss_cntl & ~1);
>+			if (!(lvds_ss_cntl & RADEON_SS_EXT_SEL))
>+				WREG32(RADEON_LVDS_SS_GEN_CNTL, lvds_ss_cntl & ~2);
>+		} else {
>+			if (ss_cntl & RADEON_SS_INT_SEL)
>+				WREG32_PLL(RADEON_SS_INT_CNTL, ss_cntl & ~1);
>+			if (lvds_ss_cntl & RADEON_SS_EXT_SEL)
>+				WREG32(RADEON_LVDS_SS_GEN_CNTL, lvds_ss_cntl & ~2);
>+		}
>+	}
>+}
>+
> static void atombios_set_ss(struct drm_crtc *crtc, int enable)
> {
> 	struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
>@@ -379,8 +411,10 @@ static void atombios_set_ss(struct drm_crtc *crtc, int enable)
> 					range = dig->ss->range;
> 				} else if (enable)
> 					return;
>-			} else if (enable)
>+			} else {
>+				radeon_disable_ss(crtc);
> 				return;
>+			}
> 			break;
> 		}
> 	}
>diff --git a/drivers/gpu/drm/radeon/radeon_reg.h b/drivers/gpu/drm/radeon/radeon_reg.h
>index ee93a9c..f0f54a5 100644
>--- a/drivers/gpu/drm/radeon/radeon_reg.h
>+++ b/drivers/gpu/drm/radeon/radeon_reg.h
>@@ -1129,8 +1129,11 @@
> #       define R300_LVDS_SRC_SEL_CRTC2      (1   << 18)
> #       define R300_LVDS_SRC_SEL_RMX        (2   << 18)
> #define RADEON_LVDS_SS_GEN_CNTL             0x02ec
>+#       define RADEON_SS_EXT_SEL            (1   << 2)
> #       define RADEON_LVDS_PWRSEQ_DELAY1_SHIFT     16
> #       define RADEON_LVDS_PWRSEQ_DELAY2_SHIFT     20
>+#define RADEON_SS_INT_CNTL                  0x0033 /* PLL */
>+#       define RADEON_SS_INT_SEL            (1   << 1)
> 
> #define RADEON_MAX_LATENCY                  0x0f3f /* PCI */
> #define RADEON_DISPLAY_BASE_ADDR            0x23c
>-- 
>1.5.6.3
>

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