Attachment 33009 Details for Bug 26358 – 1/2 add pll algo selection rework

[patch] 1/2 add pll algo selection rework

0001-drm-radeon-kms-rework-pll-algo-selection.patch (text/plain), 8.14 KB, created by Alex Deucher on 2010-02-02 09:25:36 UTC

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Creator: Alex Deucher

Created: 2010-02-02 09:25:36 UTC

Size: 8.14 KB

patch

obsolete

>From f86887d68b8f732edc9d9519c957a04b174a82b8 Mon Sep 17 00:00:00 2001
>From: Alex Deucher <alexdeucher@gmail.com>
>Date: Tue, 2 Feb 2010 12:05:01 -0500
>Subject: [PATCH] drm/radeon/kms: rework pll algo selection
>
>Rework the pll algo selection so that the pll algo
>in use can be selected more easily.  This allows
>us to select different pll divider selection algos
>for specific monitors that work better with one algo
>or the other.  This is needed for the next patch which
>adds an LVDS pll quirk for a specific notebook.
>
>Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
>---
> drivers/gpu/drm/radeon/atombios_crtc.c      |   28 +++++++++------
> drivers/gpu/drm/radeon/radeon_atombios.c    |    8 ++++
> drivers/gpu/drm/radeon/radeon_display.c     |   49 +++++++++++++++++++--------
> drivers/gpu/drm/radeon/radeon_legacy_crtc.c |    1 +
> drivers/gpu/drm/radeon/radeon_mode.h        |   18 +++++----
> 5 files changed, 70 insertions(+), 34 deletions(-)
>
>diff --git a/drivers/gpu/drm/radeon/atombios_crtc.c b/drivers/gpu/drm/radeon/atombios_crtc.c
>index 35bdb08..bb45517 100644
>--- a/drivers/gpu/drm/radeon/atombios_crtc.c
>+++ b/drivers/gpu/drm/radeon/atombios_crtc.c
>@@ -426,6 +426,15 @@ static u32 atombios_adjust_pll(struct drm_crtc *crtc,
> 	/* reset the pll flags */
> 	pll->flags = 0;
> 
>+	/* select the PLL algo */
>+	if (ASIC_IS_AVIVO(rdev)) {
>+		if (radeon_new_pll)
>+			pll->algo = PLL_ALGO_AVIVO;
>+		else
>+			pll->algo = PLL_ALGO_LEGACY;
>+	} else
>+		pll->algo = PLL_ALGO_LEGACY;
>+
> 	if (ASIC_IS_AVIVO(rdev)) {
> 		if ((rdev->family == CHIP_RS600) ||
> 		    (rdev->family == CHIP_RS690) ||
>@@ -454,6 +463,11 @@ static u32 atombios_adjust_pll(struct drm_crtc *crtc,
> 				/* DVO wants 2x pixel clock if the DVO chip is in 12 bit mode */
> 				if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1)
> 					adjusted_clock = mode->clock * 2;
>+				/* LVDS PLL quirks */
>+				if (encoder->encoder_type == DRM_MODE_ENCODER_LVDS) {
>+					struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
>+					pll->algo = dig->pll_algo;
>+				}
> 			} else {
> 				if (encoder->encoder_type != DRM_MODE_ENCODER_DAC)
> 					pll->flags |= RADEON_PLL_NO_ODD_POST_DIV;
>@@ -552,18 +566,8 @@ void atombios_crtc_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode)
> 	/* adjust pixel clock as needed */
> 	adjusted_clock = atombios_adjust_pll(crtc, mode, pll);
> 
>-	if (ASIC_IS_AVIVO(rdev)) {
>-		if (radeon_new_pll)
>-			radeon_compute_pll_avivo(pll, adjusted_clock, &pll_clock,
>-						 &fb_div, &frac_fb_div,
>-						 &ref_div, &post_div);
>-		else
>-			radeon_compute_pll(pll, adjusted_clock, &pll_clock,
>-					   &fb_div, &frac_fb_div,
>-					   &ref_div, &post_div);
>-	} else
>-		radeon_compute_pll(pll, adjusted_clock, &pll_clock, &fb_div, &frac_fb_div,
>-				   &ref_div, &post_div);
>+	radeon_compute_pll(pll, adjusted_clock, &pll_clock, &fb_div, &frac_fb_div,
>+			   &ref_div, &post_div);
> 
> 	index = GetIndexIntoMasterTable(COMMAND, SetPixelClock);
> 	atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev,
>diff --git a/drivers/gpu/drm/radeon/radeon_atombios.c b/drivers/gpu/drm/radeon/radeon_atombios.c
>index fa82ca7..667f099 100644
>--- a/drivers/gpu/drm/radeon/radeon_atombios.c
>+++ b/drivers/gpu/drm/radeon/radeon_atombios.c
>@@ -1143,6 +1143,14 @@ struct radeon_encoder_atom_dig *radeon_atombios_get_lvds_info(struct
> 
> 		lvds->ss = radeon_atombios_get_ss_info(encoder, lvds_info->info.ucSS_Id);
> 
>+		if (ASIC_IS_AVIVO(rdev)) {
>+			if (radeon_new_pll)
>+				lvds->pll_algo = PLL_ALGO_AVIVO;
>+			else
>+				lvds->pll_algo = PLL_ALGO_LEGACY;
>+		} else
>+			lvds->pll_algo = PLL_ALGO_LEGACY;
>+
> 		encoder->native_mode = lvds->native_mode;
> 	}
> 	return lvds;
>diff --git a/drivers/gpu/drm/radeon/radeon_display.c b/drivers/gpu/drm/radeon/radeon_display.c
>index e874c05..627510e 100644
>--- a/drivers/gpu/drm/radeon/radeon_display.c
>+++ b/drivers/gpu/drm/radeon/radeon_display.c
>@@ -405,13 +405,13 @@ static inline uint32_t radeon_div(uint64_t n, uint32_t d)
> 	return n;
> }
> 
>-void radeon_compute_pll(struct radeon_pll *pll,
>-			uint64_t freq,
>-			uint32_t *dot_clock_p,
>-			uint32_t *fb_div_p,
>-			uint32_t *frac_fb_div_p,
>-			uint32_t *ref_div_p,
>-			uint32_t *post_div_p)
>+static void radeon_compute_pll_legacy(struct radeon_pll *pll,
>+				      uint64_t freq,
>+				      uint32_t *dot_clock_p,
>+				      uint32_t *fb_div_p,
>+				      uint32_t *frac_fb_div_p,
>+				      uint32_t *ref_div_p,
>+				      uint32_t *post_div_p)
> {
> 	uint32_t min_ref_div = pll->min_ref_div;
> 	uint32_t max_ref_div = pll->max_ref_div;
>@@ -571,13 +571,13 @@ void radeon_compute_pll(struct radeon_pll *pll,
> 	*post_div_p = best_post_div;
> }
> 
>-void radeon_compute_pll_avivo(struct radeon_pll *pll,
>-			      uint64_t freq,
>-			      uint32_t *dot_clock_p,
>-			      uint32_t *fb_div_p,
>-			      uint32_t *frac_fb_div_p,
>-			      uint32_t *ref_div_p,
>-			      uint32_t *post_div_p)
>+static void radeon_compute_pll_avivo(struct radeon_pll *pll,
>+				     uint64_t freq,
>+				     uint32_t *dot_clock_p,
>+				     uint32_t *fb_div_p,
>+				     uint32_t *frac_fb_div_p,
>+				     uint32_t *ref_div_p,
>+				     uint32_t *post_div_p)
> {
> 	fixed20_12 m, n, frac_n, p, f_vco, f_pclk, best_freq;
> 	fixed20_12 pll_out_max, pll_out_min;
>@@ -662,6 +662,27 @@ void radeon_compute_pll_avivo(struct radeon_pll *pll,
> 	DRM_DEBUG("%u %d.%d, %d, %d\n", *dot_clock_p * 10, *fb_div_p, *frac_fb_div_p, *ref_div_p, *post_div_p);
> }
> 
>+void radeon_compute_pll(struct radeon_pll *pll,
>+			uint64_t freq,
>+			uint32_t *dot_clock_p,
>+			uint32_t *fb_div_p,
>+			uint32_t *frac_fb_div_p,
>+			uint32_t *ref_div_p,
>+			uint32_t *post_div_p)
>+{
>+	switch (pll->algo) {
>+	case PLL_ALGO_AVIVO:
>+		radeon_compute_pll_avivo(pll, freq, dot_clock_p, fb_div_p,
>+					 frac_fb_div_p, ref_div_p, post_div_p);
>+		break;
>+	case PLL_ALGO_LEGACY:
>+	default:
>+		radeon_compute_pll_legacy(pll, freq, dot_clock_p, fb_div_p,
>+					  frac_fb_div_p, ref_div_p, post_div_p);
>+		break;
>+	}
>+}
>+
> static void radeon_user_framebuffer_destroy(struct drm_framebuffer *fb)
> {
> 	struct radeon_framebuffer *radeon_fb = to_radeon_framebuffer(fb);
>diff --git a/drivers/gpu/drm/radeon/radeon_legacy_crtc.c b/drivers/gpu/drm/radeon/radeon_legacy_crtc.c
>index b6d8081..376e697 100644
>--- a/drivers/gpu/drm/radeon/radeon_legacy_crtc.c
>+++ b/drivers/gpu/drm/radeon/radeon_legacy_crtc.c
>@@ -726,6 +726,7 @@ static void radeon_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode)
> 		pll = &rdev->clock.p1pll;
> 
> 	pll->flags = RADEON_PLL_LEGACY;
>+	pll->algo = PLL_ALGO_LEGACY;
> 
> 	if (mode->clock > 200000) /* range limits??? */
> 		pll->flags |= RADEON_PLL_PREFER_HIGH_FB_DIV;
>diff --git a/drivers/gpu/drm/radeon/radeon_mode.h b/drivers/gpu/drm/radeon/radeon_mode.h
>index e81b2ae..410cb94 100644
>--- a/drivers/gpu/drm/radeon/radeon_mode.h
>+++ b/drivers/gpu/drm/radeon/radeon_mode.h
>@@ -113,6 +113,7 @@ struct radeon_tmds_pll {
> 
> #define RADEON_MAX_BIOS_CONNECTOR 16
> 
>+/* pll flags */
> #define RADEON_PLL_USE_BIOS_DIVS        (1 << 0)
> #define RADEON_PLL_NO_ODD_POST_DIV      (1 << 1)
> #define RADEON_PLL_USE_REF_DIV          (1 << 2)
>@@ -127,6 +128,12 @@ struct radeon_tmds_pll {
> #define RADEON_PLL_PREFER_CLOSEST_LOWER (1 << 11)
> #define RADEON_PLL_USE_POST_DIV         (1 << 12)
> 
>+/* pll algo */
>+enum radeon_pll_algo {
>+	PLL_ALGO_LEGACY,
>+	PLL_ALGO_AVIVO
>+};
>+
> struct radeon_pll {
> 	/* reference frequency */
> 	uint32_t reference_freq;
>@@ -157,6 +164,8 @@ struct radeon_pll {
> 
> 	/* pll id */
> 	uint32_t id;
>+	/* pll algo */
>+	enum radeon_pll_algo algo;
> };
> 
> struct radeon_i2c_chan {
>@@ -303,6 +312,7 @@ struct radeon_encoder_atom_dig {
> 	/* atom lvds */
> 	uint32_t lvds_misc;
> 	uint16_t panel_pwr_delay;
>+	enum radeon_pll_algo pll_algo;
> 	struct radeon_atom_ss *ss;
> 	/* panel mode */
> 	struct drm_display_mode native_mode;
>@@ -432,14 +442,6 @@ extern void radeon_compute_pll(struct radeon_pll *pll,
> 			       uint32_t *ref_div_p,
> 			       uint32_t *post_div_p);
> 
>-extern void radeon_compute_pll_avivo(struct radeon_pll *pll,
>-				     uint64_t freq,
>-				     uint32_t *dot_clock_p,
>-				     uint32_t *fb_div_p,
>-				     uint32_t *frac_fb_div_p,
>-				     uint32_t *ref_div_p,
>-				     uint32_t *post_div_p);
>-
> extern void radeon_setup_encoder_clones(struct drm_device *dev);
> 
> struct drm_encoder *radeon_encoder_legacy_lvds_add(struct drm_device *dev, int bios_index);
>-- 
>1.5.6.3
>

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