Attachment 33232 Details for Bug 26513 – Add mime-type for Verilog document + a test file

[patch] Add mime-type for Verilog document + a test file

0001-Add-mime-type-for-Verilog-documents-a-test-file.patch (text/plain), 1.80 KB, created by Antti Kaijanmäki on 2010-02-10 23:55:32 UTC

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Creator: Antti Kaijanmäki

Created: 2010-02-10 23:55:32 UTC

Size: 1.80 KB

patch

obsolete

>From ec8d1a08a9bf018047babc1b544fa747d2f8ddd3 Mon Sep 17 00:00:00 2001
>From: =?utf-8?q?Antti=20Kaijanm=C3=A4ki?= <antti@kaijanmaki.net>
>Date: Thu, 11 Feb 2010 09:42:27 +0200
>Subject: [PATCH] Add mime-type for Verilog documents + a test file.
>MIME-Version: 1.0
>Content-Type: text/plain; charset=utf-8
>Content-Transfer-Encoding: 8bit
>
>
>Signed-off-by: Antti KaijanmÃ¤ki <antti@kaijanmaki.net>
>---
> freedesktop.org.xml.in |    5 +++++
> tests/list             |    1 +
> tests/test.v           |   10 ++++++++++
> 3 files changed, 16 insertions(+), 0 deletions(-)
> create mode 100644 tests/test.v
>
>diff --git a/freedesktop.org.xml.in b/freedesktop.org.xml.in
>index 1620aaf..d97ec09 100644
>--- a/freedesktop.org.xml.in
>+++ b/freedesktop.org.xml.in
>@@ -4266,6 +4266,11 @@ command to generate the output files.
>     </magic>
>     <glob pattern="*.t2t"/>
>   </mime-type>
>+  <mime-type type="text/x-verilog">
>+    <_comment>Verilog document</_comment>
>+    <sub-class-of type="text/plain"/>
>+    <glob pattern="*.v"/>
>+  </mime-type>
>   <mime-type type="text/x-vhdl">
>     <_comment>VHDL document</_comment>
>     <acronym>VHDL</acronym>
>diff --git a/tests/list b/tests/list
>index d7449d0..ac6830e 100644
>--- a/tests/list
>+++ b/tests/list
>@@ -194,6 +194,7 @@ tb-saved.eml message/rfc822
> test.url application/x-mswinurl xox
> # Copied from http://www.digitalmars.com/d/
> test.d text/x-dsrc ox
>+test.v text/x-verilog ox
> 
> # xml subtypes
> test.ttx application/x-font-ttx
>diff --git a/tests/test.v b/tests/test.v
>new file mode 100644
>index 0000000..a0e0689
>--- /dev/null
>+++ b/tests/test.v
>@@ -0,0 +1,10 @@
>+module main;
>+  initial 
>+    begin
>+      $display("Hello world!");
>+      $finish;
>+    end
>+endmodule
>+
>+// from http://en.wikipedia.org/wiki/Verilog#Example
>+// Text is available under the Creative Commons Attribution-ShareAlike License
>-- 
>1.6.3.3
>

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