Attachment 33817 Details for Bug 25741 – possible fix

[patch] possible fix

0001-drm-radeon-kms-atom-spread-spectrum-fix.patch (text/plain), 3.82 KB, created by Alex Deucher on 2010-03-06 08:06:50 UTC

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Creator: Alex Deucher

Created: 2010-03-06 08:06:50 UTC

Size: 3.82 KB

patch

obsolete

>From 1c1c332f0482b8b728ec63af92bc316fa41302a1 Mon Sep 17 00:00:00 2001
>From: Alex Deucher <alexdeucher@gmail.com>
>Date: Sat, 6 Mar 2010 10:57:30 -0500
>Subject: [PATCH] drm/radeon/kms/atom: spread spectrum fix
>
>The atom spread spectrum table does not always
>disable ss.  Explicitly disable it and then use
>the atom table to enable later if needed (currently
>only used for LVDS).
>
>Fixes display issues on some systems.
>
>Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
>---
> drivers/gpu/drm/radeon/atombios_crtc.c |   57 ++++++++++++++++++++++++++++----
> 1 files changed, 50 insertions(+), 7 deletions(-)
>
>diff --git a/drivers/gpu/drm/radeon/atombios_crtc.c b/drivers/gpu/drm/radeon/atombios_crtc.c
>index dd9fdf5..0c67669 100644
>--- a/drivers/gpu/drm/radeon/atombios_crtc.c
>+++ b/drivers/gpu/drm/radeon/atombios_crtc.c
>@@ -353,12 +353,55 @@ static void atombios_crtc_set_timing(struct drm_crtc *crtc,
> 	atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
> }
> 
>+static void atombios_disable_ss(struct drm_crtc *crtc)
>+{
>+	struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
>+	struct drm_device *dev = crtc->dev;
>+	struct radeon_device *rdev = dev->dev_private;
>+	u32 ss_cntl;
>+
>+	if (ASIC_IS_DCE4(rdev)) {
>+		switch (radeon_crtc->pll_id) {
>+		case ATOM_PPLL1:
>+			ss_cntl = RREG32(EVERGREEN_P1PLL_SS_CNTL);
>+			ss_cntl &= ~EVERGREEN_PxPLL_SS_EN;
>+			WREG32(EVERGREEN_P1PLL_SS_CNTL, ss_cntl);
>+			break;
>+		case ATOM_PPLL2:
>+			ss_cntl = RREG32(EVERGREEN_P2PLL_SS_CNTL);
>+			ss_cntl &= ~EVERGREEN_PxPLL_SS_EN;
>+			WREG32(EVERGREEN_P2PLL_SS_CNTL, ss_cntl);
>+			break;
>+		case ATOM_DCPLL:
>+		case ATOM_PPLL_INVALID:
>+			return;
>+		}
>+	} else if (ASIC_IS_AVIVO(rdev)) {
>+		switch (radeon_crtc->pll_id) {
>+		case ATOM_PPLL1:
>+			ss_cntl = RREG32(AVIVO_P1PLL_INT_SS_CNTL);
>+			ss_cntl &= ~1;
>+			WREG32(AVIVO_P1PLL_INT_SS_CNTL, ss_cntl);
>+			break;
>+		case ATOM_PPLL2:
>+			ss_cntl = RREG32(AVIVO_P2PLL_INT_SS_CNTL);
>+			ss_cntl &= ~1;
>+			WREG32(AVIVO_P2PLL_INT_SS_CNTL, ss_cntl);
>+			break;
>+		case ATOM_DCPLL:
>+		case ATOM_PPLL_INVALID:
>+			return;
>+		}
>+	}
>+}
>+
>+
> union atom_enable_ss {
> 	ENABLE_LVDS_SS_PARAMETERS legacy;
> 	ENABLE_SPREAD_SPECTRUM_ON_PPLL_PS_ALLOCATION v1;
> };
> 
>-static void atombios_set_ss(struct drm_crtc *crtc, int enable)
>+static void atombios_enable_ss(struct drm_crtc *crtc)
> {
> 	struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
> 	struct drm_device *dev = crtc->dev;
>@@ -387,9 +430,9 @@ static void atombios_set_ss(struct drm_crtc *crtc, int enable)
> 					step = dig->ss->step;
> 					delay = dig->ss->delay;
> 					range = dig->ss->range;
>-				} else if (enable)
>+				} else
> 					return;
>-			} else if (enable)
>+			} else
> 				return;
> 			break;
> 		}
>@@ -406,13 +449,13 @@ static void atombios_set_ss(struct drm_crtc *crtc, int enable)
> 		args.v1.ucSpreadSpectrumDelay = delay;
> 		args.v1.ucSpreadSpectrumRange = range;
> 		args.v1.ucPpll = radeon_crtc->crtc_id ? ATOM_PPLL2 : ATOM_PPLL1;
>-		args.v1.ucEnable = enable;
>+		args.v1.ucEnable = ATOM_ENABLE;
> 	} else {
> 		args.legacy.usSpreadSpectrumPercentage = cpu_to_le16(percentage);
> 		args.legacy.ucSpreadSpectrumType = type;
> 		args.legacy.ucSpreadSpectrumStepSize_Delay = (step & 3) << 2;
> 		args.legacy.ucSpreadSpectrumStepSize_Delay |= (delay & 7) << 4;
>-		args.legacy.ucEnable = enable;
>+		args.legacy.ucEnable = ATOM_ENABLE;
> 	}
> 	atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
> }
>@@ -1086,12 +1129,12 @@ int atombios_crtc_mode_set(struct drm_crtc *crtc,
> 	/* pick pll */
> 	radeon_crtc->pll_id = radeon_atom_pick_pll(crtc);
> 
>-	atombios_set_ss(crtc, 0);
>+	atombios_disable_ss(crtc);
> 	/* always set DCPLL */
> 	if (ASIC_IS_DCE4(rdev))
> 		atombios_crtc_set_dcpll(crtc);
> 	atombios_crtc_set_pll(crtc, adjusted_mode);
>-	atombios_set_ss(crtc, 1);
>+	atombios_enable_ss(crtc);
> 
> 	if (ASIC_IS_DCE4(rdev))
> 		atombios_set_crtc_dtd_timing(crtc, adjusted_mode);
>-- 
>1.5.6.3
>

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Attachments on bug 25741: 32218 | 32219 | 32220 | 32221 | 32222 | 32223 | 32230 | 32336 | 32509 | 33815 | 33816 | 33817 | 33870

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