Attachment 34974 Details for Bug 21561 – untested patch

[patch] untested patch

bug21561.diff (text/plain), 10.87 KB, created by Alex Deucher on 2010-04-13 11:38:37 UTC

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Creator: Alex Deucher

Created: 2010-04-13 11:38:37 UTC

Size: 10.87 KB

patch

obsolete

>diff --git a/src/r600_exa.c b/src/r600_exa.c
>index 26b59d8..53ec1cc 100644
>--- a/src/r600_exa.c
>+++ b/src/r600_exa.c
>@@ -175,7 +175,7 @@ R600SetAccelState(ScrnInfoPtr pScrn,
> 		  struct r600_accel_object *src1,
> 		  struct r600_accel_object *dst,
> 		  uint32_t vs_offset, uint32_t ps_offset,
>-		  int rop, Pixel planemask)
>+		  int rop, Pixel planemask, Pixel fg)
> {
>     RADEONInfoPtr info = RADEONPTR(pScrn);
>     struct radeon_accel_state *accel_state = info->accel_state;
>@@ -207,6 +207,7 @@ R600SetAccelState(ScrnInfoPtr pScrn,
> 
>     accel_state->rop = rop;
>     accel_state->planemask = planemask;
>+    accel_state->fg = fg;
> 
>     /* bad pitch */
>     if (accel_state->src_obj[0].pitch & 7)
>@@ -280,11 +281,9 @@ R600DoneSolid(PixmapPtr pPix);
> static void
> R600DoneComposite(PixmapPtr pDst);
> 
>-
>-static Bool
>-R600PrepareSolid(PixmapPtr pPix, int alu, Pixel pm, Pixel fg)
>+void
>+R600EmitSolidState(ScrnInfoPtr pScrn)
> {
>-    ScrnInfoPtr pScrn = xf86Screens[pPix->drawable.pScreen->myNum];
>     RADEONInfoPtr info = RADEONPTR(pScrn);
>     struct radeon_accel_state *accel_state = info->accel_state;
>     cb_config_t     cb_conf;
>@@ -292,45 +291,11 @@ R600PrepareSolid(PixmapPtr pPix, int alu, Pixel pm, Pixel fg)
>     int pmask = 0;
>     uint32_t a, r, g, b;
>     float ps_alu_consts[4];
>-    struct r600_accel_object dst;
>-
>-    if (!R600CheckBPP(pPix->drawable.bitsPerPixel))
>-	RADEON_FALLBACK(("R600CheckDatatype failed\n"));
>-    if (!R600ValidPM(pm, pPix->drawable.bitsPerPixel))
>-	RADEON_FALLBACK(("invalid planemask\n"));
>-
>-#if defined(XF86DRM_MODE)
>-    if (info->cs) {
>-	dst.offset = 0;
>-	dst.bo = radeon_get_pixmap_bo(pPix);
>-    } else
>-#endif
>-    {
>-	dst.offset = exaGetPixmapOffset(pPix) + info->fbLocation + pScrn->fbOffset;
>-	dst.bo = NULL;
>-    }
>-
>-    dst.pitch = exaGetPixmapPitch(pPix) / (pPix->drawable.bitsPerPixel / 8);
>-    dst.width = pPix->drawable.width;
>-    dst.height = pPix->drawable.height;
>-    dst.bpp = pPix->drawable.bitsPerPixel;
>-    dst.domain = RADEON_GEM_DOMAIN_VRAM;
>-	
>-    if (!R600SetAccelState(pScrn,
>-			   NULL,
>-			   NULL,
>-			   &dst,
>-			   accel_state->solid_vs_offset, accel_state->solid_ps_offset,
>-			   alu, pm))
>-	return FALSE;
> 
>     CLEAR (cb_conf);
>     CLEAR (vs_conf);
>     CLEAR (ps_conf);
> 
>-    radeon_vbo_check(pScrn, 16);
>-    r600_cp_start(pScrn);
>-
>     set_default_state(pScrn, accel_state->ib);
> 
>     set_generic_scissor(pScrn, accel_state->ib, 0, 0, accel_state->dst_obj.width, accel_state->dst_obj.height);
>@@ -419,24 +384,24 @@ R600PrepareSolid(PixmapPtr pPix, int alu, Pixel pm, Pixel fg)
> 
>     /* PS alu constants */
>     if (accel_state->dst_obj.bpp == 16) {
>-	r = (fg >> 11) & 0x1f;
>-	g = (fg >> 5) & 0x3f;
>-	b = (fg >> 0) & 0x1f;
>+	r = (accel_state->fg >> 11) & 0x1f;
>+	g = (accel_state->fg >> 5) & 0x3f;
>+	b = (accel_state->fg >> 0) & 0x1f;
> 	ps_alu_consts[0] = (float)r / 31; /* R */
> 	ps_alu_consts[1] = (float)g / 63; /* G */
> 	ps_alu_consts[2] = (float)b / 31; /* B */
> 	ps_alu_consts[3] = 1.0; /* A */
>     } else if (accel_state->dst_obj.bpp == 8) {
>-	a = (fg >> 0) & 0xff;
>+	a = (accel_state->fg >> 0) & 0xff;
> 	ps_alu_consts[0] = 0.0; /* R */
> 	ps_alu_consts[1] = 0.0; /* G */
> 	ps_alu_consts[2] = 0.0; /* B */
> 	ps_alu_consts[3] = (float)a / 255; /* A */
>     } else {
>-	a = (fg >> 24) & 0xff;
>-	r = (fg >> 16) & 0xff;
>-	g = (fg >> 8) & 0xff;
>-	b = (fg >> 0) & 0xff;
>+	a = (accel_state->fg >> 24) & 0xff;
>+	r = (accel_state->fg >> 16) & 0xff;
>+	g = (accel_state->fg >> 8) & 0xff;
>+	b = (accel_state->fg >> 0) & 0xff;
> 	ps_alu_consts[0] = (float)r / 255; /* R */
> 	ps_alu_consts[1] = (float)g / 255; /* G */
> 	ps_alu_consts[2] = (float)b / 255; /* B */
>@@ -445,6 +410,53 @@ R600PrepareSolid(PixmapPtr pPix, int alu, Pixel pm, Pixel fg)
>     set_alu_consts(pScrn, accel_state->ib, SQ_ALU_CONSTANT_ps,
> 		   sizeof(ps_alu_consts) / SQ_ALU_CONSTANT_offset, ps_alu_consts);
> 
>+}
>+
>+static Bool
>+R600PrepareSolid(PixmapPtr pPix, int alu, Pixel pm, Pixel fg)
>+{
>+    ScrnInfoPtr pScrn = xf86Screens[pPix->drawable.pScreen->myNum];
>+    RADEONInfoPtr info = RADEONPTR(pScrn);
>+    struct radeon_accel_state *accel_state = info->accel_state;
>+    struct r600_accel_object dst;
>+
>+    if (!R600CheckBPP(pPix->drawable.bitsPerPixel))
>+	RADEON_FALLBACK(("R600CheckDatatype failed\n"));
>+    if (!R600ValidPM(pm, pPix->drawable.bitsPerPixel))
>+	RADEON_FALLBACK(("invalid planemask\n"));
>+
>+#if defined(XF86DRM_MODE)
>+    if (info->cs) {
>+	dst.offset = 0;
>+	dst.bo = radeon_get_pixmap_bo(pPix);
>+    } else
>+#endif
>+    {
>+	dst.offset = exaGetPixmapOffset(pPix) + info->fbLocation + pScrn->fbOffset;
>+	dst.bo = NULL;
>+    }
>+
>+    dst.pitch = exaGetPixmapPitch(pPix) / (pPix->drawable.bitsPerPixel / 8);
>+    dst.width = pPix->drawable.width;
>+    dst.height = pPix->drawable.height;
>+    dst.bpp = pPix->drawable.bitsPerPixel;
>+    dst.domain = RADEON_GEM_DOMAIN_VRAM;
>+
>+    if (!R600SetAccelState(pScrn,
>+			   NULL,
>+			   NULL,
>+			   &dst,
>+			   accel_state->solid_vs_offset, accel_state->solid_ps_offset,
>+			   alu, pm, fg))
>+	return FALSE;
>+
>+    accel_state->current_op = RADEON_SOLID_OP;
>+
>+    radeon_vbo_check(pScrn, 16);
>+    r600_cp_start(pScrn);
>+
>+    R600EmitSolidState(pScrn);
>+
>     if (accel_state->vsync)
> 	R600VlineHelperClear(pScrn);
> 
>@@ -493,8 +505,8 @@ R600DoneSolid(PixmapPtr pPix)
>     r600_finish_op(pScrn, 8);
> }
> 
>-static void
>-R600DoPrepareCopy(ScrnInfoPtr pScrn)
>+void
>+R600EmitCopyState(ScrnInfoPtr pScrn)
> {
>     RADEONInfoPtr info = RADEONPTR(pScrn);
>     struct radeon_accel_state *accel_state = info->accel_state;
>@@ -510,9 +522,6 @@ R600DoPrepareCopy(ScrnInfoPtr pScrn)
>     CLEAR (vs_conf);
>     CLEAR (ps_conf);
> 
>-    radeon_vbo_check(pScrn, 16);
>-    r600_cp_start(pScrn);
>-
>     set_default_state(pScrn, accel_state->ib);
> 
>     set_generic_scissor(pScrn, accel_state->ib, 0, 0, accel_state->dst_obj.width, accel_state->dst_obj.height);
>@@ -653,6 +662,16 @@ R600DoPrepareCopy(ScrnInfoPtr pScrn)
> }
> 
> static void
>+R600DoPrepareCopy(ScrnInfoPtr pScrn)
>+{
>+
>+    radeon_vbo_check(pScrn, 16);
>+    r600_cp_start(pScrn);
>+    R600EmitCopyState(pScrn);
>+
>+}
>+
>+static void
> R600DoCopy(ScrnInfoPtr pScrn)
> {
>     r600_finish_op(pScrn, 16);
>@@ -759,9 +778,11 @@ R600PrepareCopy(PixmapPtr pSrc,   PixmapPtr pDst,
> 			   NULL,
> 			   &dst_obj,
> 			   accel_state->copy_vs_offset, accel_state->copy_ps_offset,
>-			   rop, planemask))
>+			   rop, planemask, 0))
> 	return FALSE;
> 
>+    accel_state->current_op = RADEON_COPY_OP;
>+
>     if (accel_state->same_surface == TRUE) {
> 	unsigned long size = pDst->drawable.height * accel_state->dst_obj.pitch * pDst->drawable.bitsPerPixel/8;
> 
>@@ -1431,7 +1452,7 @@ static Bool R600PrepareComposite(int op, PicturePtr pSrcPicture,
> 			       &mask_obj,
> 			       &dst_obj,
> 			       accel_state->comp_vs_offset, accel_state->comp_mask_ps_offset,
>-			       3, 0xffffffff))
>+			       3, 0xffffffff, 0))
> 	    return FALSE;
> 
> 	accel_state->msk_pic = pMaskPicture;
>@@ -1451,7 +1472,7 @@ static Bool R600PrepareComposite(int op, PicturePtr pSrcPicture,
> 			       NULL,
> 			       &dst_obj,
> 			       accel_state->comp_vs_offset, accel_state->comp_ps_offset,
>-			       3, 0xffffffff))
>+			       3, 0xffffffff, 0))
> 	    return FALSE;
> 
> 	accel_state->msk_pic = NULL;
>@@ -1466,6 +1487,8 @@ static Bool R600PrepareComposite(int op, PicturePtr pSrcPicture,
>     CLEAR (vs_conf);
>     CLEAR (ps_conf);
> 
>+    accel_state->current_op = RADEON_COMPOSITE_OP;
>+
>     if (pMask)
>         radeon_vbo_check(pScrn, 24);
>     else
>@@ -1754,7 +1777,7 @@ R600CopyToVRAM(ScrnInfoPtr pScrn,
> 			   NULL,
> 			   &dst_obj,
> 			   accel_state->copy_vs_offset, accel_state->copy_ps_offset,
>-			   3, 0xffffffff))
>+			   3, 0xffffffff, 0))
> 	return FALSE;
> 
>     /* memcopy from sys to scratch */
>@@ -1870,7 +1893,7 @@ R600DownloadFromScreen(PixmapPtr pSrc, int x, int y, int w, int h,
> 			   NULL,
> 			   &scratch_obj,
> 			   accel_state->copy_vs_offset, accel_state->copy_ps_offset,
>-			   3, 0xffffffff))
>+			   3, 0xffffffff, 0))
> 	return FALSE;
> 
>     /* blit from vram to scratch */
>@@ -1970,7 +1993,7 @@ R600UploadToScreenCS(PixmapPtr pDst, int x, int y, int w, int h,
> 			   NULL,
> 			   &dst_obj,
> 			   accel_state->copy_vs_offset, accel_state->copy_ps_offset,
>-			   3, 0xffffffff)) {
>+			   3, 0xffffffff, 0)) {
>         r = FALSE;
>         goto out;
>     }
>@@ -2077,7 +2100,7 @@ R600DownloadFromScreenCS(PixmapPtr pSrc, int x, int y, int w,
> 			   NULL,
> 			   &dst_obj,
> 			   accel_state->copy_vs_offset, accel_state->copy_ps_offset,
>-			   3, 0xffffffff)) {
>+			   3, 0xffffffff, 0)) {
>         r = FALSE;
>         goto out;
>     }
>diff --git a/src/r600_state.h b/src/r600_state.h
>index e9bfa10..eca8304 100644
>--- a/src/r600_state.h
>+++ b/src/r600_state.h
>@@ -334,7 +334,11 @@ R600SetAccelState(ScrnInfoPtr pScrn,
> 		  struct r600_accel_object *src1,
> 		  struct r600_accel_object *dst,
> 		  uint32_t vs_offset, uint32_t ps_offset,
>-		  int rop, Pixel planemask);
>+		  int rop, Pixel planemask, Pixel fg);
>+void
>+R600EmitSolidState(ScrnInfoPtr pScrn);
>+void
>+R600EmitCopyState(ScrnInfoPtr pScrn);
> 
> extern Bool RADEONPrepareAccess_CS(PixmapPtr pPix, int index);
> extern void RADEONFinishAccess_CS(PixmapPtr pPix, int index);
>diff --git a/src/r600_textured_videofuncs.c b/src/r600_textured_videofuncs.c
>index 2a86df3..3a1a85d 100644
>--- a/src/r600_textured_videofuncs.c
>+++ b/src/r600_textured_videofuncs.c
>@@ -194,7 +194,7 @@ R600DisplayTexturedVideo(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
> 			   NULL,
> 			   &dst_obj,
> 			   accel_state->xv_vs_offset, accel_state->xv_ps_offset,
>-			   3, 0xffffffff))
>+			   3, 0xffffffff, 0))
> 	return;
> 
> #ifdef COMPOSITE
>@@ -205,6 +205,8 @@ R600DisplayTexturedVideo(ScrnInfoPtr pScrn, RADEONPortPrivPtr pPriv)
>     dstyoff = 0;
> #endif
> 
>+    accel_state->current_op = RADEON_XV_OP;
>+
>     radeon_vbo_check(pScrn, 16);
>     r600_cp_start(pScrn);
> 
>diff --git a/src/r6xx_accel.c b/src/r6xx_accel.c
>index a835d71..5f8af10 100644
>--- a/src/r6xx_accel.c
>+++ b/src/r6xx_accel.c
>@@ -1320,8 +1320,16 @@ void r600_vb_no_space(ScrnInfoPtr pScrn, int vert_size)
> 	radeon_vbo_get(pScrn);
> 	return;
>     }
>-#endif 
>+#endif
> 
>     r600_finish_op(pScrn, vert_size);
>     r600_cp_start(pScrn);
>+
>+    if (!info->cs) {
>+	if (accel_state->current_op == RADEON_SOLID_OP)
>+	    R600EmitSolidState(pScrn);
>+	else if (accel_state->current_op == RADEON_COPY_OP)
>+	    R600EmitCopyState(pScrn);
>+	/* XXX todo composite, Xv */
>+    }
> }
>diff --git a/src/radeon.h b/src/radeon.h
>index 388422a..29beab3 100644
>--- a/src/radeon.h
>+++ b/src/radeon.h
>@@ -683,6 +683,13 @@ struct r600_accel_object {
>     struct radeon_bo *bo;
> };
> 
>+enum radeon_op {
>+    RADEON_SOLID_OP,
>+    RADEON_COPY_OP,
>+    RADEON_COMPOSITE_OP,
>+    RADEON_XV_OP
>+};
>+
> struct radeon_accel_state {
>     /* common accel data */
>     int               fifo_slots;       /* Free slots in the FIFO (64 max)   */
>@@ -784,6 +791,8 @@ struct radeon_accel_state {
>     Bool              same_surface;
>     int               rop;
>     uint32_t          planemask;
>+    uint32_t          fg;
>+    enum radeon_op    current_op;
> 
>     // composite
>     Bool              component_alpha;

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