Attachment 35871 Details for Bug 27008 – possible fix

[patch] possible fix

0001-drm-radeon-kms-modesetting-fix-for-rs4xx.patch (text/plain), 2.22 KB, created by Alex Deucher on 2010-05-26 08:23:08 UTC

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Creator: Alex Deucher

Created: 2010-05-26 08:23:08 UTC

Size: 2.22 KB

patch

obsolete

>From 6cf729630bedf51f6452e2c61f4c0d7fcf363741 Mon Sep 17 00:00:00 2001
>From: Alex Deucher <alexdeucher@gmail.com>
>Date: Wed, 26 May 2010 11:11:26 -0400
>Subject: [PATCH] drm/radeon/kms: modesetting fix for rs4xx
>
>Disable crtc after setting up the timing.
>https://bugs.freedesktop.org/show_bug.cgi?id=27008
>
>Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
>---
> drivers/gpu/drm/radeon/radeon_legacy_crtc.c |   14 ++++++++++++--
> 1 files changed, 12 insertions(+), 2 deletions(-)
>
>diff --git a/drivers/gpu/drm/radeon/radeon_legacy_crtc.c b/drivers/gpu/drm/radeon/radeon_legacy_crtc.c
>index e1e5255..3e5be6b 100644
>--- a/drivers/gpu/drm/radeon/radeon_legacy_crtc.c
>+++ b/drivers/gpu/drm/radeon/radeon_legacy_crtc.c
>@@ -526,6 +526,7 @@ static bool radeon_set_crtc_timing(struct drm_crtc *crtc, struct drm_display_mod
> 	uint32_t crtc_h_sync_strt_wid;
> 	uint32_t crtc_v_total_disp;
> 	uint32_t crtc_v_sync_strt_wid;
>+	uint32_t crtc2_gen_cntl = 0, crtc_gen_cntl = 0;
> 	bool is_tv = false;
> 
> 	DRM_DEBUG("\n");
>@@ -589,7 +590,6 @@ static bool radeon_set_crtc_timing(struct drm_crtc *crtc, struct drm_display_mod
> 				   : 0));
> 
> 	if (radeon_crtc->crtc_id) {
>-		uint32_t crtc2_gen_cntl;
> 		uint32_t disp2_merge_cntl;
> 
> 		/* if TV DAC is enabled for another crtc and keep it enabled */
>@@ -622,7 +622,6 @@ static bool radeon_set_crtc_timing(struct drm_crtc *crtc, struct drm_display_mod
> 		WREG32(RADEON_FP_H2_SYNC_STRT_WID, crtc_h_sync_strt_wid);
> 		WREG32(RADEON_FP_V2_SYNC_STRT_WID, crtc_v_sync_strt_wid);
> 	} else {
>-		uint32_t crtc_gen_cntl;
> 		uint32_t crtc_ext_cntl;
> 		uint32_t disp_merge_cntl;
> 
>@@ -668,6 +667,17 @@ static bool radeon_set_crtc_timing(struct drm_crtc *crtc, struct drm_display_mod
> 	WREG32(RADEON_CRTC_V_TOTAL_DISP + radeon_crtc->crtc_offset, crtc_v_total_disp);
> 	WREG32(RADEON_CRTC_V_SYNC_STRT_WID + radeon_crtc->crtc_offset, crtc_v_sync_strt_wid);
> 
>+	/* clear enable after timing set to avoid flicker after modeset */
>+	if ((rdev->family == CHIP_RS400) || (rdev->family == CHIP_RS480)) {
>+		if (radeon_crtc->crtc_id) {
>+			crtc2_gen_cntl &= ~RADEON_CRTC2_EN;
>+			WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl);
>+		} else {
>+			crtc_gen_cntl &= ~RADEON_CRTC_EN;
>+			WREG32(RADEON_CRTC_GEN_CNTL, crtc_gen_cntl);
>+		}
>+	}
>+
> 	return true;
> }
> 
>-- 
>1.5.6.3
>

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