Attachment 36474 Details for Bug 28746 – output of intel_reg_dumper

output of intel_reg_dumper

reg_dumper.out (text/plain), 7.10 KB, created by BenG on 2010-06-24 12:41:41 UTC

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Creator: BenG

Created: 2010-06-24 12:41:41 UTC

Size: 7.10 KB

patch

obsolete

>          PGETBL_CTL: 0x00000001
>     GEN6_INSTDONE_1: 0xfffffffe
>     GEN6_INSTDONE_2: 0xffffffff
>        CPU_VGACNTRL: 0x80000000 (disabled)
>DIGITAL_PORT_HOTPLUG: 0x00000000
>           RR_HW_CTL: 0x00000000 (low 0, high 0)
>      FDI_PLL_BIOS_0: 0x082b3019
>      FDI_PLL_BIOS_1: 0x00000000
>      FDI_PLL_BIOS_2: 0x00000000
>DISPLAY_PORT_PLL_BIO: 0x0807012b
>DISPLAY_PORT_PLL_BIO: 0x00000000
>DISPLAY_PORT_PLL_BIO: 0x00000000
>    FDI_PLL_FREQ_CTL: 0x00053687
>           PIPEACONF: 0xc0000000 (enabled, active, 8bpc)
>            HTOTAL_A: 0x08bf068f (1680 active, 2240 total)
>            HBLANK_A: 0x08bf068f (1680 start, 2240 end)
>             HSYNC_A: 0x07a706f7 (1784 start, 1960 end)
>            VTOTAL_A: 0x04400419 (1050 active, 1089 total)
>            VBLANK_A: 0x04400419 (1050 start, 1089 end)
>             VSYNC_A: 0x0422041c (1053 start, 1059 end)
>        VSYNCSHIFT_A: 0x00000000
>            PIPEASRC: 0x068f0419 (1680, 1050)
>       PIPEA_DATA_M1: 0x7e67d27d (TU 64, val 0x67d27d 6804093)
>       PIPEA_DATA_N1: 0x00800000 (val 0x800000 8388608)
>       PIPEA_DATA_M2: 0x00000000 (TU 1, val 0x0 0)
>       PIPEA_DATA_N2: 0x00000000 (val 0x0 0)
>       PIPEA_LINK_M1: 0x0004536f (val 0x4536f 283503)
>       PIPEA_LINK_N1: 0x00080000 (val 0x80000 524288)
>       PIPEA_LINK_M2: 0x00000000 (val 0x0 0)
>       PIPEA_LINK_N2: 0x00000000 (val 0x0 0)
>            DSPACNTR: 0xd8004400 (enabled)
>            DSPABASE: 0x00000000
>          DSPASTRIDE: 0x00001c00 (112)
>            DSPASURF: 0x0270b000
>         DSPATILEOFF: 0x00000000 (0, 0)
>           PIPEBCONF: 0x00000000 (disabled, inactive, 8bpc)
>            HTOTAL_B: 0x00000000 (1 active, 1 total)
>            HBLANK_B: 0x00000000 (1 start, 1 end)
>             HSYNC_B: 0x00000000 (1 start, 1 end)
>            VTOTAL_B: 0x00000000 (1 active, 1 total)
>            VBLANK_B: 0x00000000 (1 start, 1 end)
>             VSYNC_B: 0x00000000 (1 start, 1 end)
>        VSYNCSHIFT_B: 0x00000000
>            DSPBCNTR: 0x00000000 (disabled)
>            DSPBBASE: 0x00000000
>          DSPBSTRIDE: 0x00000000 (0)
>            DSPBSURF: 0x00000000
>         DSPBTILEOFF: 0x00000000 (0, 0)
>            PIPEBSRC: 0x00000000 (1, 1)
>       PIPEB_DATA_M1: 0x00000000 (TU 1, val 0x0 0)
>       PIPEB_DATA_N1: 0x00000000 (val 0x0 0)
>       PIPEB_DATA_M2: 0x00000000 (TU 1, val 0x0 0)
>       PIPEB_DATA_N2: 0x00000000 (val 0x0 0)
>       PIPEB_LINK_M1: 0x00000000 (val 0x0 0)
>       PIPEB_LINK_N1: 0x00000000 (val 0x0 0)
>       PIPEB_LINK_M2: 0x00000000 (val 0x0 0)
>       PIPEB_LINK_N2: 0x00000000 (val 0x0 0)
>           PFA_CTL_1: 0x00000000 (disable, auto_scale yes, auto_scale_cal no, v_filter enable, vadapt disable, mode least, filter_sel programmed,chroma pre-filter disable, vert3tap auto, v_inter_invert field 1)
>           PFB_CTL_1: 0x00000000 (disable, auto_scale yes, auto_scale_cal no, v_filter enable, vadapt disable, mode least, filter_sel programmed,chroma pre-filter disable, vert3tap auto, v_inter_invert field 1)
>         PFA_WIN_POS: 0x00000000 (0, 0)
>         PFB_WIN_POS: 0x00000000 (0, 0)
>        PFA_WIN_SIZE: 0x00000000 (0, 0)
>        PFB_WIN_SIZE: 0x00000000 (0, 0)
>    PCH_DREF_CONTROL: 0x00001400 (cpu source disable, ssc_source enable, nonspread_source enable, superspread_source disable, ssc4_mode downspread, ssc1 disable, ssc4 disable)
>     PCH_RAWCLK_FREQ: 0x0000007d (FDL_TP1 timer 0.5us, FDL_TP2 timer 1.5us, freq 125)
>    PCH_DPLL_TMR_CFG: 0x0271186a
>      PCH_SSC4_PARMS: 0x00000000
>  PCH_SSC4_AUX_PARMS: 0x00000000
>          PCH_DPLL_A: 0x84020002 (enable, sdvo high speed no, mode (null), p2 (null), FPA0 P1 2, FPA1 P1 2, refclk default 120Mhz, sdvo/hdmi mul 1)
>          PCH_DPLL_B: 0x04800080 (disable, sdvo high speed no, mode (null), p2 (null), FPA0 P1 8, FPA1 P1 8, refclk default 120Mhz, sdvo/hdmi mul 1)
>            PCH_FPA0: 0x00021005 (n = 2, m1 = 16, m2 = 5)
>            PCH_FPA1: 0x00021005 (n = 2, m1 = 16, m2 = 5)
>            PCH_FPB0: 0x00030d07 (n = 3, m1 = 13, m2 = 7)
>            PCH_FPB1: 0x00030d07 (n = 3, m1 = 13, m2 = 7)
>      TRANS_HTOTAL_A: 0x08bf068f (1680 active, 2240 total)
>      TRANS_HBLANK_A: 0x08bf068f (1680 start, 2240 end)
>       TRANS_HSYNC_A: 0x07a706f7 (1784 start, 1960 end)
>      TRANS_VTOTAL_A: 0x04400419 (1050 active, 1089 total)
>      TRANS_VBLANK_A: 0x04400419 (1050 start, 1089 end)
>       TRANS_VSYNC_A: 0x0422041c (1053 start, 1059 end)
>      TRANSA_DATA_M1: 0x00000000 (TU 1, val 0x0 0)
>      TRANSA_DATA_N1: 0x00000000 (val 0x0 0)
>      TRANSA_DATA_M2: 0x00000000 (TU 1, val 0x0 0)
>      TRANSA_DATA_N2: 0x00000000 (val 0x0 0)
>   TRANSA_DP_LINK_M1: 0x00000000 (val 0x0 0)
>   TRANSA_DP_LINK_N1: 0x00000000 (val 0x0 0)
>   TRANSA_DP_LINK_M2: 0x00000000 (val 0x0 0)
>   TRANSA_DP_LINK_N2: 0x00000000 (val 0x0 0)
>      TRANS_HTOTAL_B: 0x00000000 (1 active, 1 total)
>      TRANS_HBLANK_B: 0x00000000 (1 start, 1 end)
>       TRANS_HSYNC_B: 0x00000000 (1 start, 1 end)
>      TRANS_VTOTAL_B: 0x00000000 (1 active, 1 total)
>      TRANS_VBLANK_B: 0x00000000 (1 start, 1 end)
>       TRANS_VSYNC_B: 0x00000000 (1 start, 1 end)
>      TRANSB_DATA_M1: 0x00000000 (TU 1, val 0x0 0)
>      TRANSB_DATA_N1: 0x00000000 (val 0x0 0)
>      TRANSB_DATA_M2: 0x00000000 (TU 1, val 0x0 0)
>      TRANSB_DATA_N2: 0x00000000 (val 0x0 0)
>   TRANSB_DP_LINK_M1: 0x00000000 (val 0x0 0)
>   TRANSB_DP_LINK_N1: 0x00000000 (val 0x0 0)
>   TRANSB_DP_LINK_M2: 0x00000000 (val 0x0 0)
>   TRANSB_DP_LINK_N2: 0x00000000 (val 0x0 0)
>          TRANSACONF: 0xc0000000 (enable, active)
>          TRANSBCONF: 0x00000000 (disable, inactive)
>         FDI_TXA_CTL: 0xb00c4000 (enable, train pattern not train, voltage swing 0.4V,pre-emphasis none, port width X2, enhanced framing enable, FDI PLL enable, scrambing enable, master mode disable)
>         FDI_TXB_CTL: 0x00044000 (disable, train pattern pattern_1, voltage swing 0.4V,pre-emphasis none, port width X1, enhanced framing enable, FDI PLL enable, scrambing enable, master mode disable)
>         FDI_RXA_CTL: 0xb0082050 (enable, train pattern not train, port width X2, 8bpc,link_reverse_strap_overwrite no, dmi_link_reverse no, FDI PLL enable,FS ecc disable, FE ecc disable, FS err report disable, FE err report disable,scrambing enable, enhanced framing enable, PCDClk)
>         FDI_RXB_CTL: 0x00000040 (disable, train pattern pattern_1, port width X1, 8bpc,link_reverse_strap_overwrite no, dmi_link_reverse no, FDI PLL disable,FS ecc disable, FE ecc disable, FS err report disable, FE err report disable,scrambing enable, enhanced framing enable, RawClk)
>        FDI_RXA_MISC: 0x00000080 (FDI Delay 128)
>        FDI_RXB_MISC: 0x00000080 (FDI Delay 128)
>     FDI_RXA_TUSIZE1: 0x7e000000
>     FDI_RXA_TUSIZE2: 0x7e000000
>     FDI_RXB_TUSIZE1: 0x7e000000
>     FDI_RXB_TUSIZE2: 0x7e000000
>       FDI_PLL_CTL_1: 0x33505248
>       FDI_PLL_CTL_2: 0x00000000
>         FDI_RXA_IIR: 0x00000000
>         FDI_RXA_IMR: 0x000000ff
>         FDI_RXB_IIR: 0x00000000
>         FDI_RXB_IMR: 0x000000ff
>            PCH_ADPA: 0x83f40010 (enabled, transcoder A, -hsync, +vsync)
>               HDMIB: 0x0000001c
>               HDMIC: 0x0000001c
>               HDMID: 0x00000018
>            PCH_LVDS: 0x40000000 (disabled, pipe B, 18 bit, 1 channel)
>           PCH_eDP_A: 0x0000001c
>            PCH_DP_B: 0x0000001c
>            PCH_DP_C: 0x0000001c
>            PCH_DP_D: 0x00000018

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Attachments on bug 28746: 36472 | 36473 | 36474 | 36475 | 36476 | 36580

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