Attachment 37349 Details for Bug 25284 – dmesg with drm.debug=4

dmesg with drm.debug=4

dmesg (text/plain), 122.96 KB, created by Sebastian Keller on 2010-07-24 04:52:07 UTC

(hide)

Description:

Filename:

MIME Type:

Creator: Sebastian Keller

Created: 2010-07-24 04:52:07 UTC

Size: 122.96 KB

patch

obsolete

>[   29.564049] [drm:intel_update_watermarks], plane B (pipe 0) clock: 107520
>[   29.564053] [drm:intel_update_watermarks], plane A (pipe 1) clock: 65000
>[   29.564057] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[   29.564061] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[   29.564065] [drm:intel_calculate_wm], FIFO entries required for mode: 20
>[   29.564068] [drm:intel_calculate_wm], FIFO watermark level: 6
>[   29.564071] [drm:intel_calculate_wm], FIFO entries required for mode: 33
>[   29.564074] [drm:intel_calculate_wm], FIFO watermark level: -4
>[   29.564078] [drm:i9xx_update_wm], FIFO watermarks - A: 6, B: 1
>[   29.564081] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 6, B: 1, C: 2, SR 1
>[   29.636020] [drm:intel_tv_detect_type], No TV connection detected
>[   29.636026] [drm:intel_update_watermarks], plane A (pipe 1) clock: 65000
>[   29.636030] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[   29.636034] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[   29.636038] [drm:intel_calculate_wm], FIFO entries required for mode: 20
>[   29.636041] [drm:intel_calculate_wm], FIFO watermark level: 6
>[   29.636045] [drm:intel_calculate_wm], FIFO entries required for mode: 0
>[   29.636048] [drm:intel_calculate_wm], FIFO watermark level: 29
>[   29.636051] [drm:i9xx_update_wm], FIFO watermarks - A: 6, B: 29
>[   29.636054] [drm:i9xx_update_wm], self-refresh entries: 25
>[   29.636058] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 6, B: 29, C: 2, SR 70
>[   29.660183] [drm:drm_helper_probe_single_connector_modes], SVIDEO-1 is disconnected
>[   29.694539] [drm:drm_crtc_helper_set_config], 
>[   29.694543] [drm:drm_crtc_helper_set_config], crtc: f4b3f000 4 fb: f3c8e500 connectors: f4855968 num_connectors: 1 (x, y) (0, 0)
>[   29.694555] [drm:drm_crtc_helper_set_config], setting connector 7 crtc to f4b3f000
>[   29.701355] [drm:intel_pipe_set_base], Writing base 00C00000 00000000 0 0 4096
>[   29.742308] psmouse serio2: ID: 10 00 64
>[   29.988345] BUG: unable to handle kernel paging request at 0001000c
>[   29.988352] IP: [<c0385e05>] fb_release+0x25/0x60
>[   29.988363] *pde = 5f004067 
>[   29.988366] Oops: 0000 [#1] SMP 
>[   29.988370] last sysfs file: /sys/devices/virtual/vtconsole/vtcon1/uevent
>[   29.988374] Modules linked in: binfmt_misc joydev snd_intel8x0 snd_ac97_codec ac97_bus i915 snd_pcm thinkpad_acpi snd_seq_midi pcmcia snd_rawmidi drm_kms_helper snd_seq_midi_event ipw2200 snd_seq sbp2 libipw snd_timer snd_seq_device drm ppdev cfg80211 snd psmouse ieee1394 parport_pc serio_raw yenta_socket led_class nvram intel_agp pcmcia_rsrc pcmcia_core soundcore i2c_algo_bit video lib80211 agpgart snd_page_alloc output lp parport firewire_ohci tg3 firewire_core crc_itu_t
>[   29.988415] 
>[   29.988420] Pid: 271, comm: plymouthd Not tainted 2.6.35-10-generic #15-Ubuntu 185869G/185869G
>[   29.988424] EIP: 0060:[<c0385e05>] EFLAGS: 00210286 CPU: 0
>[   29.988428] EIP is at fb_release+0x25/0x60
>[   29.988431] EAX: 00010004 EBX: f71e9000 ECX: c0385de0 EDX: f4b23d80
>[   29.988435] ESI: f71e9008 EDI: f6e05220 EBP: f71edf44 ESP: f71edf3c
>[   29.988439]  DS: 007b ES: 007b FS: 00d8 GS: 00e0 SS: 0068
>[   29.988443] Process plymouthd (pid: 271, ti=f71ec000 task=f69c4c20 task.ti=f71ec000)
>[   29.988445] Stack:
>[   29.988448]  f4b23d80 00000008 f71edf74 c0219614 00000003 00000000 00000000 f6824060
>[   29.988455] <0> f6e05220 f71f1980 f6824060 f4b23d80 f6a91300 00000000 f71edf7c c021972d
>[   29.988462] <0> f71edf94 c021609c b786f000 f6a91300 f4b23d80 0000000b f71edfac c0216145
>[   29.988471] Call Trace:
>[   29.988479]  [<c0219614>] ? __fput+0xe4/0x1e0
>[   29.988483]  [<c021972d>] ? fput+0x1d/0x30
>[   29.988487]  [<c021609c>] ? filp_close+0x4c/0x80
>[   29.988491]  [<c0216145>] ? sys_close+0x75/0xc0
>[   29.988497]  [<c05c9c14>] ? syscall_call+0x7/0xb
>[   29.988499] Code: bc 27 00 00 00 00 55 89 e5 83 ec 08 89 1c 24 89 74 24 04 0f 1f 44 00 00 8b 5a 70 8d 73 08 89 f0 e8 d1 26 24 00 8b 83 0c 03 00 00 <8b> 48 08 85 c9 74 0f ba 01 00 00 00 89 d8 ff d1 8b 83 0c 03 00 
>[   29.988541] EIP: [<c0385e05>] fb_release+0x25/0x60 SS:ESP 0068:f71edf3c
>[   29.988547] CR2: 000000000001000c
>[   29.988551] ---[ end trace 612cd1c452b08f44 ]---
>[   30.203550] tg3 0000:02:00.0: eth0: Link is up at 10 Mbps, half duplex
>[   30.203556] tg3 0000:02:00.0: eth0: Flow control is off for TX and off for RX
>[   30.203775] ADDRCONF(NETDEV_CHANGE): eth0: link becomes ready
>[   32.831159] IBM TrackPoint firmware: 0x0e, buttons: 3/3
>[   33.028034] input: TPPS/2 IBM TrackPoint as /devices/platform/i8042/serio1/serio2/input/input7
>[   34.652153] [drm:drm_mode_getconnector], connector id 5:
>[   34.652165] [drm:drm_helper_probe_single_connector_modes], VGA-1
>[   34.657339] [drm:intel_update_watermarks], plane B (pipe 0) clock: 31500
>[   34.657344] [drm:intel_update_watermarks], plane A (pipe 1) clock: 65000
>[   34.657349] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[   34.657353] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[   34.657357] [drm:intel_calculate_wm], FIFO entries required for mode: 20
>[   34.657361] [drm:intel_calculate_wm], FIFO watermark level: 6
>[   34.657364] [drm:intel_calculate_wm], FIFO entries required for mode: 9
>[   34.657367] [drm:intel_calculate_wm], FIFO watermark level: 20
>[   34.657371] [drm:i9xx_update_wm], FIFO watermarks - A: 6, B: 20
>[   34.657374] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 6, B: 20, C: 2, SR 1
>[   34.680499] [drm:intel_crtc_mode_set], Mode for pipe A:
>[   34.680504] [drm:drm_mode_debug_printmodeline], Modeline 0:"640x480" 0 31500 640 664 704 832 480 489 491 520 0x10 0xa
>[   34.704029] [drm:intel_pipe_set_base], No FB bound
>[   34.704033] [drm:intel_update_watermarks], plane B (pipe 0) clock: 31500
>[   34.704037] [drm:intel_update_watermarks], plane A (pipe 1) clock: 65000
>[   34.704041] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[   34.704045] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[   34.704049] [drm:intel_calculate_wm], FIFO entries required for mode: 20
>[   34.704052] [drm:intel_calculate_wm], FIFO watermark level: 6
>[   34.704056] [drm:intel_calculate_wm], FIFO entries required for mode: 9
>[   34.704059] [drm:intel_calculate_wm], FIFO watermark level: 20
>[   34.704062] [drm:i9xx_update_wm], FIFO watermarks - A: 6, B: 20
>[   34.704066] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 6, B: 20, C: 2, SR 1
>[   34.704071] [drm:intel_update_watermarks], plane B (pipe 0) clock: 31500
>[   34.704075] [drm:intel_update_watermarks], plane A (pipe 1) clock: 65000
>[   34.704079] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[   34.704083] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[   34.704086] [drm:intel_calculate_wm], FIFO entries required for mode: 20
>[   34.704090] [drm:intel_calculate_wm], FIFO watermark level: 6
>[   34.704093] [drm:intel_calculate_wm], FIFO entries required for mode: 9
>[   34.704096] [drm:intel_calculate_wm], FIFO watermark level: 20
>[   34.704099] [drm:i9xx_update_wm], FIFO watermarks - A: 6, B: 20
>[   34.704103] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 6, B: 20, C: 2, SR 1
>[   34.752073] [drm:intel_update_watermarks], plane A (pipe 1) clock: 65000
>[   34.752082] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[   34.752086] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[   34.752090] [drm:intel_calculate_wm], FIFO entries required for mode: 20
>[   34.752094] [drm:intel_calculate_wm], FIFO watermark level: 6
>[   34.752097] [drm:intel_calculate_wm], FIFO entries required for mode: 0
>[   34.752101] [drm:intel_calculate_wm], FIFO watermark level: 29
>[   34.752104] [drm:i9xx_update_wm], FIFO watermarks - A: 6, B: 29
>[   34.752107] [drm:i9xx_update_wm], self-refresh entries: 25
>[   34.752111] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 6, B: 29, C: 2, SR 70
>[   34.776214] [drm:drm_helper_probe_single_connector_modes], VGA-1 is disconnected
>[   34.776240] [drm:drm_mode_getconnector], connector id 5:
>[   34.776245] [drm:drm_helper_probe_single_connector_modes], VGA-1
>[   34.780834] [drm:intel_update_watermarks], plane B (pipe 0) clock: 31500
>[   34.780838] [drm:intel_update_watermarks], plane A (pipe 1) clock: 65000
>[   34.780842] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[   34.780846] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[   34.780850] [drm:intel_calculate_wm], FIFO entries required for mode: 20
>[   34.780853] [drm:intel_calculate_wm], FIFO watermark level: 6
>[   34.780856] [drm:intel_calculate_wm], FIFO entries required for mode: 9
>[   34.780860] [drm:intel_calculate_wm], FIFO watermark level: 20
>[   34.780863] [drm:i9xx_update_wm], FIFO watermarks - A: 6, B: 20
>[   34.780866] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 6, B: 20, C: 2, SR 1
>[   34.804502] [drm:intel_crtc_mode_set], Mode for pipe A:
>[   34.804506] [drm:drm_mode_debug_printmodeline], Modeline 0:"640x480" 0 31500 640 664 704 832 480 489 491 520 0x10 0xa
>[   34.828070] [drm:intel_pipe_set_base], No FB bound
>[   34.828074] [drm:intel_update_watermarks], plane B (pipe 0) clock: 31500
>[   34.828078] [drm:intel_update_watermarks], plane A (pipe 1) clock: 65000
>[   34.828082] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[   34.828086] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[   34.828089] [drm:intel_calculate_wm], FIFO entries required for mode: 20
>[   34.828093] [drm:intel_calculate_wm], FIFO watermark level: 6
>[   34.828096] [drm:intel_calculate_wm], FIFO entries required for mode: 9
>[   34.828099] [drm:intel_calculate_wm], FIFO watermark level: 20
>[   34.828102] [drm:i9xx_update_wm], FIFO watermarks - A: 6, B: 20
>[   34.828106] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 6, B: 20, C: 2, SR 1
>[   34.828111] [drm:intel_update_watermarks], plane B (pipe 0) clock: 31500
>[   34.828115] [drm:intel_update_watermarks], plane A (pipe 1) clock: 65000
>[   34.828119] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[   34.828123] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[   34.828126] [drm:intel_calculate_wm], FIFO entries required for mode: 20
>[   34.828129] [drm:intel_calculate_wm], FIFO watermark level: 6
>[   34.828133] [drm:intel_calculate_wm], FIFO entries required for mode: 9
>[   34.828136] [drm:intel_calculate_wm], FIFO watermark level: 20
>[   34.828139] [drm:i9xx_update_wm], FIFO watermarks - A: 6, B: 20
>[   34.828143] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 6, B: 20, C: 2, SR 1
>[   34.876064] [drm:intel_update_watermarks], plane A (pipe 1) clock: 65000
>[   34.876069] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[   34.876073] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[   34.876076] [drm:intel_calculate_wm], FIFO entries required for mode: 20
>[   34.876080] [drm:intel_calculate_wm], FIFO watermark level: 6
>[   34.876083] [drm:intel_calculate_wm], FIFO entries required for mode: 0
>[   34.876086] [drm:intel_calculate_wm], FIFO watermark level: 29
>[   34.876090] [drm:i9xx_update_wm], FIFO watermarks - A: 6, B: 29
>[   34.876093] [drm:i9xx_update_wm], self-refresh entries: 25
>[   34.876097] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 6, B: 29, C: 2, SR 70
>[   34.900175] [drm:drm_helper_probe_single_connector_modes], VGA-1 is disconnected
>[   34.900205] [drm:drm_mode_getconnector], connector id 7:
>[   34.900210] [drm:drm_helper_probe_single_connector_modes], LVDS-1
>[   34.900217] [drm:drm_helper_probe_single_connector_modes], Probed modes for LVDS-1
>[   34.900221] [drm:drm_mode_debug_printmodeline], Modeline 26:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x8 0xa
>[   34.900230] [drm:drm_mode_getconnector], connector id 7:
>[   34.900704] [drm:drm_mode_getconnector], connector id 11:
>[   34.900709] [drm:drm_helper_probe_single_connector_modes], SVIDEO-1
>[   34.900716] [drm:intel_update_watermarks], plane B (pipe 0) clock: 107520
>[   34.900720] [drm:intel_update_watermarks], plane A (pipe 1) clock: 65000
>[   34.900723] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[   34.900727] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[   34.900731] [drm:intel_calculate_wm], FIFO entries required for mode: 20
>[   34.900734] [drm:intel_calculate_wm], FIFO watermark level: 6
>[   34.900738] [drm:intel_calculate_wm], FIFO entries required for mode: 33
>[   34.900741] [drm:intel_calculate_wm], FIFO watermark level: -4
>[   34.900744] [drm:i9xx_update_wm], FIFO watermarks - A: 6, B: 1
>[   34.900748] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 6, B: 1, C: 2, SR 1
>[   34.924495] [drm:intel_crtc_mode_set], Mode for pipe A:
>[   34.924498] [drm:drm_mode_debug_printmodeline], Modeline 0:"NTSC 480i" 0 107520 1280 1368 1496 1712 1024 1027 1034 1104 0x40 0x0
>[   34.948029] [drm:intel_pipe_set_base], No FB bound
>[   34.948033] [drm:intel_update_watermarks], plane B (pipe 0) clock: 107520
>[   34.948037] [drm:intel_update_watermarks], plane A (pipe 1) clock: 65000
>[   34.948041] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[   34.948045] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[   34.948049] [drm:intel_calculate_wm], FIFO entries required for mode: 20
>[   34.948052] [drm:intel_calculate_wm], FIFO watermark level: 6
>[   34.948055] [drm:intel_calculate_wm], FIFO entries required for mode: 33
>[   34.948059] [drm:intel_calculate_wm], FIFO watermark level: -4
>[   34.948062] [drm:i9xx_update_wm], FIFO watermarks - A: 6, B: 1
>[   34.948065] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 6, B: 1, C: 2, SR 1
>[   34.972057] [drm:intel_update_watermarks], plane B (pipe 0) clock: 107520
>[   34.972061] [drm:intel_update_watermarks], plane A (pipe 1) clock: 65000
>[   34.972065] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[   34.972069] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[   34.972073] [drm:intel_calculate_wm], FIFO entries required for mode: 20
>[   34.972076] [drm:intel_calculate_wm], FIFO watermark level: 6
>[   34.972080] [drm:intel_calculate_wm], FIFO entries required for mode: 33
>[   34.972083] [drm:intel_calculate_wm], FIFO watermark level: -4
>[   34.972086] [drm:i9xx_update_wm], FIFO watermarks - A: 6, B: 1
>[   34.972090] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 6, B: 1, C: 2, SR 1
>[   35.044068] [drm:intel_tv_detect_type], No TV connection detected
>[   35.044078] [drm:intel_update_watermarks], plane A (pipe 1) clock: 65000
>[   35.044082] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[   35.044086] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[   35.044090] [drm:intel_calculate_wm], FIFO entries required for mode: 20
>[   35.044093] [drm:intel_calculate_wm], FIFO watermark level: 6
>[   35.044097] [drm:intel_calculate_wm], FIFO entries required for mode: 0
>[   35.044100] [drm:intel_calculate_wm], FIFO watermark level: 29
>[   35.044103] [drm:i9xx_update_wm], FIFO watermarks - A: 6, B: 29
>[   35.044107] [drm:i9xx_update_wm], self-refresh entries: 25
>[   35.044111] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 6, B: 29, C: 2, SR 70
>[   35.068217] [drm:drm_helper_probe_single_connector_modes], SVIDEO-1 is disconnected
>[   35.068240] [drm:drm_mode_getconnector], connector id 11:
>[   35.068245] [drm:drm_helper_probe_single_connector_modes], SVIDEO-1
>[   35.068255] [drm:intel_update_watermarks], plane B (pipe 0) clock: 107520
>[   35.068259] [drm:intel_update_watermarks], plane A (pipe 1) clock: 65000
>[   35.068263] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[   35.068267] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[   35.068271] [drm:intel_calculate_wm], FIFO entries required for mode: 20
>[   35.068274] [drm:intel_calculate_wm], FIFO watermark level: 6
>[   35.068277] [drm:intel_calculate_wm], FIFO entries required for mode: 33
>[   35.068280] [drm:intel_calculate_wm], FIFO watermark level: -4
>[   35.068284] [drm:i9xx_update_wm], FIFO watermarks - A: 6, B: 1
>[   35.068287] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 6, B: 1, C: 2, SR 1
>[   35.092466] [drm:intel_crtc_mode_set], Mode for pipe A:
>[   35.092470] [drm:drm_mode_debug_printmodeline], Modeline 0:"NTSC 480i" 0 107520 1280 1368 1496 1712 1024 1027 1034 1104 0x40 0x0
>[   35.116028] [drm:intel_pipe_set_base], No FB bound
>[   35.116032] [drm:intel_update_watermarks], plane B (pipe 0) clock: 107520
>[   35.116036] [drm:intel_update_watermarks], plane A (pipe 1) clock: 65000
>[   35.116040] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[   35.116044] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[   35.116047] [drm:intel_calculate_wm], FIFO entries required for mode: 20
>[   35.116051] [drm:intel_calculate_wm], FIFO watermark level: 6
>[   35.116054] [drm:intel_calculate_wm], FIFO entries required for mode: 33
>[   35.116057] [drm:intel_calculate_wm], FIFO watermark level: -4
>[   35.116061] [drm:i9xx_update_wm], FIFO watermarks - A: 6, B: 1
>[   35.116064] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 6, B: 1, C: 2, SR 1
>[   35.140051] [drm:intel_update_watermarks], plane B (pipe 0) clock: 107520
>[   35.140056] [drm:intel_update_watermarks], plane A (pipe 1) clock: 65000
>[   35.140060] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[   35.140064] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[   35.140068] [drm:intel_calculate_wm], FIFO entries required for mode: 20
>[   35.140071] [drm:intel_calculate_wm], FIFO watermark level: 6
>[   35.140074] [drm:intel_calculate_wm], FIFO entries required for mode: 33
>[   35.140078] [drm:intel_calculate_wm], FIFO watermark level: -4
>[   35.140081] [drm:i9xx_update_wm], FIFO watermarks - A: 6, B: 1
>[   35.140085] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 6, B: 1, C: 2, SR 1
>[   35.212021] [drm:intel_tv_detect_type], No TV connection detected
>[   35.212028] [drm:intel_update_watermarks], plane A (pipe 1) clock: 65000
>[   35.212032] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[   35.212037] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[   35.212040] [drm:intel_calculate_wm], FIFO entries required for mode: 20
>[   35.212044] [drm:intel_calculate_wm], FIFO watermark level: 6
>[   35.212047] [drm:intel_calculate_wm], FIFO entries required for mode: 0
>[   35.212050] [drm:intel_calculate_wm], FIFO watermark level: 29
>[   35.212054] [drm:i9xx_update_wm], FIFO watermarks - A: 6, B: 29
>[   35.212057] [drm:i9xx_update_wm], self-refresh entries: 25
>[   35.212061] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 6, B: 29, C: 2, SR 70
>[   35.236216] [drm:drm_helper_probe_single_connector_modes], SVIDEO-1 is disconnected
>[   35.238060] [drm:drm_mode_getconnector], connector id 5:
>[   35.238067] [drm:drm_helper_probe_single_connector_modes], VGA-1
>[   35.242767] [drm:intel_update_watermarks], plane B (pipe 0) clock: 31500
>[   35.242772] [drm:intel_update_watermarks], plane A (pipe 1) clock: 65000
>[   35.242776] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[   35.242780] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[   35.242784] [drm:intel_calculate_wm], FIFO entries required for mode: 20
>[   35.242788] [drm:intel_calculate_wm], FIFO watermark level: 6
>[   35.242791] [drm:intel_calculate_wm], FIFO entries required for mode: 9
>[   35.242794] [drm:intel_calculate_wm], FIFO watermark level: 20
>[   35.242797] [drm:i9xx_update_wm], FIFO watermarks - A: 6, B: 20
>[   35.242801] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 6, B: 20, C: 2, SR 1
>[   35.264499] [drm:intel_crtc_mode_set], Mode for pipe A:
>[   35.264504] [drm:drm_mode_debug_printmodeline], Modeline 0:"640x480" 0 31500 640 664 704 832 480 489 491 520 0x10 0xa
>[   35.288033] [drm:intel_pipe_set_base], No FB bound
>[   35.288041] [drm:intel_update_watermarks], plane B (pipe 0) clock: 31500
>[   35.288045] [drm:intel_update_watermarks], plane A (pipe 1) clock: 65000
>[   35.288050] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[   35.288054] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[   35.288058] [drm:intel_calculate_wm], FIFO entries required for mode: 20
>[   35.288062] [drm:intel_calculate_wm], FIFO watermark level: 6
>[   35.288065] [drm:intel_calculate_wm], FIFO entries required for mode: 9
>[   35.288068] [drm:intel_calculate_wm], FIFO watermark level: 20
>[   35.288071] [drm:i9xx_update_wm], FIFO watermarks - A: 6, B: 20
>[   35.288075] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 6, B: 20, C: 2, SR 1
>[   35.288083] [drm:intel_update_watermarks], plane B (pipe 0) clock: 31500
>[   35.288086] [drm:intel_update_watermarks], plane A (pipe 1) clock: 65000
>[   35.288090] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[   35.288094] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[   35.288097] [drm:intel_calculate_wm], FIFO entries required for mode: 20
>[   35.288101] [drm:intel_calculate_wm], FIFO watermark level: 6
>[   35.288104] [drm:intel_calculate_wm], FIFO entries required for mode: 9
>[   35.288107] [drm:intel_calculate_wm], FIFO watermark level: 20
>[   35.288110] [drm:i9xx_update_wm], FIFO watermarks - A: 6, B: 20
>[   35.288114] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 6, B: 20, C: 2, SR 1
>[   35.336032] [drm:intel_update_watermarks], plane A (pipe 1) clock: 65000
>[   35.336038] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[   35.336042] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[   35.336046] [drm:intel_calculate_wm], FIFO entries required for mode: 20
>[   35.336049] [drm:intel_calculate_wm], FIFO watermark level: 6
>[   35.336052] [drm:intel_calculate_wm], FIFO entries required for mode: 0
>[   35.336056] [drm:intel_calculate_wm], FIFO watermark level: 29
>[   35.336059] [drm:i9xx_update_wm], FIFO watermarks - A: 6, B: 29
>[   35.336062] [drm:i9xx_update_wm], self-refresh entries: 25
>[   35.336066] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 6, B: 29, C: 2, SR 70
>[   35.360179] [drm:drm_helper_probe_single_connector_modes], VGA-1 is disconnected
>[   35.360204] [drm:drm_mode_getconnector], connector id 5:
>[   35.360209] [drm:drm_helper_probe_single_connector_modes], VGA-1
>[   35.365663] [drm:intel_update_watermarks], plane B (pipe 0) clock: 31500
>[   35.365668] [drm:intel_update_watermarks], plane A (pipe 1) clock: 65000
>[   35.365672] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[   35.365676] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[   35.365680] [drm:intel_calculate_wm], FIFO entries required for mode: 20
>[   35.365684] [drm:intel_calculate_wm], FIFO watermark level: 6
>[   35.365687] [drm:intel_calculate_wm], FIFO entries required for mode: 9
>[   35.365690] [drm:intel_calculate_wm], FIFO watermark level: 20
>[   35.365693] [drm:i9xx_update_wm], FIFO watermarks - A: 6, B: 20
>[   35.365697] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 6, B: 20, C: 2, SR 1
>[   35.388464] [drm:intel_crtc_mode_set], Mode for pipe A:
>[   35.388470] [drm:drm_mode_debug_printmodeline], Modeline 0:"640x480" 0 31500 640 664 704 832 480 489 491 520 0x10 0xa
>[   35.412022] [drm:intel_pipe_set_base], No FB bound
>[   35.412027] [drm:intel_update_watermarks], plane B (pipe 0) clock: 31500
>[   35.412031] [drm:intel_update_watermarks], plane A (pipe 1) clock: 65000
>[   35.412035] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[   35.412039] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[   35.412043] [drm:intel_calculate_wm], FIFO entries required for mode: 20
>[   35.412046] [drm:intel_calculate_wm], FIFO watermark level: 6
>[   35.412049] [drm:intel_calculate_wm], FIFO entries required for mode: 9
>[   35.412053] [drm:intel_calculate_wm], FIFO watermark level: 20
>[   35.412056] [drm:i9xx_update_wm], FIFO watermarks - A: 6, B: 20
>[   35.412060] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 6, B: 20, C: 2, SR 1
>[   35.412065] [drm:intel_update_watermarks], plane B (pipe 0) clock: 31500
>[   35.412069] [drm:intel_update_watermarks], plane A (pipe 1) clock: 65000
>[   35.412073] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[   35.412076] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[   35.412080] [drm:intel_calculate_wm], FIFO entries required for mode: 20
>[   35.412083] [drm:intel_calculate_wm], FIFO watermark level: 6
>[   35.412086] [drm:intel_calculate_wm], FIFO entries required for mode: 9
>[   35.412090] [drm:intel_calculate_wm], FIFO watermark level: 20
>[   35.412093] [drm:i9xx_update_wm], FIFO watermarks - A: 6, B: 20
>[   35.412097] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 6, B: 20, C: 2, SR 1
>[   35.460069] [drm:intel_update_watermarks], plane A (pipe 1) clock: 65000
>[   35.460077] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[   35.460082] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[   35.460086] [drm:intel_calculate_wm], FIFO entries required for mode: 20
>[   35.460090] [drm:intel_calculate_wm], FIFO watermark level: 6
>[   35.460093] [drm:intel_calculate_wm], FIFO entries required for mode: 0
>[   35.460096] [drm:intel_calculate_wm], FIFO watermark level: 29
>[   35.460099] [drm:i9xx_update_wm], FIFO watermarks - A: 6, B: 29
>[   35.460103] [drm:i9xx_update_wm], self-refresh entries: 25
>[   35.460107] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 6, B: 29, C: 2, SR 70
>[   35.484181] [drm:drm_helper_probe_single_connector_modes], VGA-1 is disconnected
>[   35.484227] [drm:drm_mode_getconnector], connector id 7:
>[   35.484232] [drm:drm_helper_probe_single_connector_modes], LVDS-1
>[   35.484243] [drm:drm_helper_probe_single_connector_modes], Probed modes for LVDS-1
>[   35.484247] [drm:drm_mode_debug_printmodeline], Modeline 26:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x8 0xa
>[   35.484255] [drm:drm_mode_getconnector], connector id 7:
>[   35.484743] [drm:drm_mode_getconnector], connector id 11:
>[   35.484748] [drm:drm_helper_probe_single_connector_modes], SVIDEO-1
>[   35.484757] [drm:intel_update_watermarks], plane B (pipe 0) clock: 107520
>[   35.484760] [drm:intel_update_watermarks], plane A (pipe 1) clock: 65000
>[   35.484764] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[   35.484768] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[   35.484772] [drm:intel_calculate_wm], FIFO entries required for mode: 20
>[   35.484775] [drm:intel_calculate_wm], FIFO watermark level: 6
>[   35.484779] [drm:intel_calculate_wm], FIFO entries required for mode: 33
>[   35.484782] [drm:intel_calculate_wm], FIFO watermark level: -4
>[   35.484785] [drm:i9xx_update_wm], FIFO watermarks - A: 6, B: 1
>[   35.484789] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 6, B: 1, C: 2, SR 1
>[   35.508464] [drm:intel_crtc_mode_set], Mode for pipe A:
>[   35.508468] [drm:drm_mode_debug_printmodeline], Modeline 0:"NTSC 480i" 0 107520 1280 1368 1496 1712 1024 1027 1034 1104 0x40 0x0
>[   35.532032] [drm:intel_pipe_set_base], No FB bound
>[   35.532038] [drm:intel_update_watermarks], plane B (pipe 0) clock: 107520
>[   35.532042] [drm:intel_update_watermarks], plane A (pipe 1) clock: 65000
>[   35.532046] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[   35.532051] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[   35.532054] [drm:intel_calculate_wm], FIFO entries required for mode: 20
>[   35.532058] [drm:intel_calculate_wm], FIFO watermark level: 6
>[   35.532061] [drm:intel_calculate_wm], FIFO entries required for mode: 33
>[   35.532065] [drm:intel_calculate_wm], FIFO watermark level: -4
>[   35.532068] [drm:i9xx_update_wm], FIFO watermarks - A: 6, B: 1
>[   35.532071] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 6, B: 1, C: 2, SR 1
>[   35.556090] [drm:intel_update_watermarks], plane B (pipe 0) clock: 107520
>[   35.556095] [drm:intel_update_watermarks], plane A (pipe 1) clock: 65000
>[   35.556099] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[   35.556103] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[   35.556107] [drm:intel_calculate_wm], FIFO entries required for mode: 20
>[   35.556111] [drm:intel_calculate_wm], FIFO watermark level: 6
>[   35.556114] [drm:intel_calculate_wm], FIFO entries required for mode: 33
>[   35.556117] [drm:intel_calculate_wm], FIFO watermark level: -4
>[   35.556120] [drm:i9xx_update_wm], FIFO watermarks - A: 6, B: 1
>[   35.556124] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 6, B: 1, C: 2, SR 1
>[   35.628063] [drm:intel_tv_detect_type], No TV connection detected
>[   35.628070] [drm:intel_update_watermarks], plane A (pipe 1) clock: 65000
>[   35.628074] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[   35.628078] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[   35.628082] [drm:intel_calculate_wm], FIFO entries required for mode: 20
>[   35.628085] [drm:intel_calculate_wm], FIFO watermark level: 6
>[   35.628089] [drm:intel_calculate_wm], FIFO entries required for mode: 0
>[   35.628092] [drm:intel_calculate_wm], FIFO watermark level: 29
>[   35.628095] [drm:i9xx_update_wm], FIFO watermarks - A: 6, B: 29
>[   35.628099] [drm:i9xx_update_wm], self-refresh entries: 25
>[   35.628102] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 6, B: 29, C: 2, SR 70
>[   35.652213] [drm:drm_helper_probe_single_connector_modes], SVIDEO-1 is disconnected
>[   35.652236] [drm:drm_mode_getconnector], connector id 11:
>[   35.652240] [drm:drm_helper_probe_single_connector_modes], SVIDEO-1
>[   35.652249] [drm:intel_update_watermarks], plane B (pipe 0) clock: 107520
>[   35.652252] [drm:intel_update_watermarks], plane A (pipe 1) clock: 65000
>[   35.652256] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[   35.652260] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[   35.652264] [drm:intel_calculate_wm], FIFO entries required for mode: 20
>[   35.652267] [drm:intel_calculate_wm], FIFO watermark level: 6
>[   35.652271] [drm:intel_calculate_wm], FIFO entries required for mode: 33
>[   35.652274] [drm:intel_calculate_wm], FIFO watermark level: -4
>[   35.652277] [drm:i9xx_update_wm], FIFO watermarks - A: 6, B: 1
>[   35.652281] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 6, B: 1, C: 2, SR 1
>[   35.676497] [drm:intel_crtc_mode_set], Mode for pipe A:
>[   35.676501] [drm:drm_mode_debug_printmodeline], Modeline 0:"NTSC 480i" 0 107520 1280 1368 1496 1712 1024 1027 1034 1104 0x40 0x0
>[   35.700023] [drm:intel_pipe_set_base], No FB bound
>[   35.700027] [drm:intel_update_watermarks], plane B (pipe 0) clock: 107520
>[   35.700031] [drm:intel_update_watermarks], plane A (pipe 1) clock: 65000
>[   35.700035] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[   35.700039] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[   35.700043] [drm:intel_calculate_wm], FIFO entries required for mode: 20
>[   35.700046] [drm:intel_calculate_wm], FIFO watermark level: 6
>[   35.700049] [drm:intel_calculate_wm], FIFO entries required for mode: 33
>[   35.700053] [drm:intel_calculate_wm], FIFO watermark level: -4
>[   35.700056] [drm:i9xx_update_wm], FIFO watermarks - A: 6, B: 1
>[   35.700060] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 6, B: 1, C: 2, SR 1
>[   35.724091] [drm:intel_update_watermarks], plane B (pipe 0) clock: 107520
>[   35.724095] [drm:intel_update_watermarks], plane A (pipe 1) clock: 65000
>[   35.724099] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[   35.724103] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[   35.724107] [drm:intel_calculate_wm], FIFO entries required for mode: 20
>[   35.724110] [drm:intel_calculate_wm], FIFO watermark level: 6
>[   35.724114] [drm:intel_calculate_wm], FIFO entries required for mode: 33
>[   35.724117] [drm:intel_calculate_wm], FIFO watermark level: -4
>[   35.724120] [drm:i9xx_update_wm], FIFO watermarks - A: 6, B: 1
>[   35.724124] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 6, B: 1, C: 2, SR 1
>[   35.796058] [drm:intel_tv_detect_type], No TV connection detected
>[   35.796064] [drm:intel_update_watermarks], plane A (pipe 1) clock: 65000
>[   35.796068] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[   35.796072] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[   35.796076] [drm:intel_calculate_wm], FIFO entries required for mode: 20
>[   35.796079] [drm:intel_calculate_wm], FIFO watermark level: 6
>[   35.796083] [drm:intel_calculate_wm], FIFO entries required for mode: 0
>[   35.796086] [drm:intel_calculate_wm], FIFO watermark level: 29
>[   35.796089] [drm:i9xx_update_wm], FIFO watermarks - A: 6, B: 29
>[   35.796093] [drm:i9xx_update_wm], self-refresh entries: 25
>[   35.796096] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 6, B: 29, C: 2, SR 70
>[   35.820209] [drm:drm_helper_probe_single_connector_modes], SVIDEO-1 is disconnected
>[   35.844206] [drm:drm_mode_getconnector], connector id 5:
>[   35.844212] [drm:drm_helper_probe_single_connector_modes], VGA-1
>[   35.848741] [drm:intel_update_watermarks], plane B (pipe 0) clock: 31500
>[   35.848745] [drm:intel_update_watermarks], plane A (pipe 1) clock: 65000
>[   35.848749] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[   35.848754] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[   35.848757] [drm:intel_calculate_wm], FIFO entries required for mode: 20
>[   35.848761] [drm:intel_calculate_wm], FIFO watermark level: 6
>[   35.848764] [drm:intel_calculate_wm], FIFO entries required for mode: 9
>[   35.848767] [drm:intel_calculate_wm], FIFO watermark level: 20
>[   35.848770] [drm:i9xx_update_wm], FIFO watermarks - A: 6, B: 20
>[   35.848774] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 6, B: 20, C: 2, SR 1
>[   35.872457] [drm:intel_crtc_mode_set], Mode for pipe A:
>[   35.872502] [drm:drm_mode_debug_printmodeline], Modeline 0:"640x480" 0 31500 640 664 704 832 480 489 491 520 0x10 0xa
>[   35.896024] [drm:intel_pipe_set_base], No FB bound
>[   35.896028] [drm:intel_update_watermarks], plane B (pipe 0) clock: 31500
>[   35.896032] [drm:intel_update_watermarks], plane A (pipe 1) clock: 65000
>[   35.896036] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[   35.896040] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[   35.896044] [drm:intel_calculate_wm], FIFO entries required for mode: 20
>[   35.896047] [drm:intel_calculate_wm], FIFO watermark level: 6
>[   35.896050] [drm:intel_calculate_wm], FIFO entries required for mode: 9
>[   35.896054] [drm:intel_calculate_wm], FIFO watermark level: 20
>[   35.896057] [drm:i9xx_update_wm], FIFO watermarks - A: 6, B: 20
>[   35.896060] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 6, B: 20, C: 2, SR 1
>[   35.896066] [drm:intel_update_watermarks], plane B (pipe 0) clock: 31500
>[   35.896069] [drm:intel_update_watermarks], plane A (pipe 1) clock: 65000
>[   35.896073] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[   35.896077] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[   35.896081] [drm:intel_calculate_wm], FIFO entries required for mode: 20
>[   35.896084] [drm:intel_calculate_wm], FIFO watermark level: 6
>[   35.896087] [drm:intel_calculate_wm], FIFO entries required for mode: 9
>[   35.896090] [drm:intel_calculate_wm], FIFO watermark level: 20
>[   35.896094] [drm:i9xx_update_wm], FIFO watermarks - A: 6, B: 20
>[   35.896097] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 6, B: 20, C: 2, SR 1
>[   35.944028] [drm:intel_update_watermarks], plane A (pipe 1) clock: 65000
>[   35.944034] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[   35.944039] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[   35.944042] [drm:intel_calculate_wm], FIFO entries required for mode: 20
>[   35.944046] [drm:intel_calculate_wm], FIFO watermark level: 6
>[   35.944049] [drm:intel_calculate_wm], FIFO entries required for mode: 0
>[   35.944053] [drm:intel_calculate_wm], FIFO watermark level: 29
>[   35.944056] [drm:i9xx_update_wm], FIFO watermarks - A: 6, B: 29
>[   35.944059] [drm:i9xx_update_wm], self-refresh entries: 25
>[   35.944063] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 6, B: 29, C: 2, SR 70
>[   35.968212] [drm:drm_helper_probe_single_connector_modes], VGA-1 is disconnected
>[   35.968230] [drm:drm_mode_getconnector], connector id 5:
>[   35.968235] [drm:drm_helper_probe_single_connector_modes], VGA-1
>[   35.972827] [drm:intel_update_watermarks], plane B (pipe 0) clock: 31500
>[   35.972832] [drm:intel_update_watermarks], plane A (pipe 1) clock: 65000
>[   35.972836] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[   35.972840] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[   35.972843] [drm:intel_calculate_wm], FIFO entries required for mode: 20
>[   35.972847] [drm:intel_calculate_wm], FIFO watermark level: 6
>[   35.972850] [drm:intel_calculate_wm], FIFO entries required for mode: 9
>[   35.972853] [drm:intel_calculate_wm], FIFO watermark level: 20
>[   35.972856] [drm:i9xx_update_wm], FIFO watermarks - A: 6, B: 20
>[   35.972860] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 6, B: 20, C: 2, SR 1
>[   35.996512] [drm:intel_crtc_mode_set], Mode for pipe A:
>[   35.996516] [drm:drm_mode_debug_printmodeline], Modeline 0:"640x480" 0 31500 640 664 704 832 480 489 491 520 0x10 0xa
>[   36.020063] [drm:intel_pipe_set_base], No FB bound
>[   36.020067] [drm:intel_update_watermarks], plane B (pipe 0) clock: 31500
>[   36.020071] [drm:intel_update_watermarks], plane A (pipe 1) clock: 65000
>[   36.020074] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[   36.020079] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[   36.020082] [drm:intel_calculate_wm], FIFO entries required for mode: 20
>[   36.020086] [drm:intel_calculate_wm], FIFO watermark level: 6
>[   36.020089] [drm:intel_calculate_wm], FIFO entries required for mode: 9
>[   36.020092] [drm:intel_calculate_wm], FIFO watermark level: 20
>[   36.020095] [drm:i9xx_update_wm], FIFO watermarks - A: 6, B: 20
>[   36.020099] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 6, B: 20, C: 2, SR 1
>[   36.020104] [drm:intel_update_watermarks], plane B (pipe 0) clock: 31500
>[   36.020108] [drm:intel_update_watermarks], plane A (pipe 1) clock: 65000
>[   36.020111] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[   36.020115] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[   36.020119] [drm:intel_calculate_wm], FIFO entries required for mode: 20
>[   36.020122] [drm:intel_calculate_wm], FIFO watermark level: 6
>[   36.020125] [drm:intel_calculate_wm], FIFO entries required for mode: 9
>[   36.020128] [drm:intel_calculate_wm], FIFO watermark level: 20
>[   36.020131] [drm:i9xx_update_wm], FIFO watermarks - A: 6, B: 20
>[   36.020135] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 6, B: 20, C: 2, SR 1
>[   36.068065] [drm:intel_update_watermarks], plane A (pipe 1) clock: 65000
>[   36.068070] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[   36.068074] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[   36.068078] [drm:intel_calculate_wm], FIFO entries required for mode: 20
>[   36.068081] [drm:intel_calculate_wm], FIFO watermark level: 6
>[   36.068085] [drm:intel_calculate_wm], FIFO entries required for mode: 0
>[   36.068088] [drm:intel_calculate_wm], FIFO watermark level: 29
>[   36.068091] [drm:i9xx_update_wm], FIFO watermarks - A: 6, B: 29
>[   36.068095] [drm:i9xx_update_wm], self-refresh entries: 25
>[   36.068098] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 6, B: 29, C: 2, SR 70
>[   36.092226] [drm:drm_helper_probe_single_connector_modes], VGA-1 is disconnected
>[   36.092257] [drm:drm_mode_getconnector], connector id 7:
>[   36.092261] [drm:drm_helper_probe_single_connector_modes], LVDS-1
>[   36.092270] [drm:drm_helper_probe_single_connector_modes], Probed modes for LVDS-1
>[   36.092274] [drm:drm_mode_debug_printmodeline], Modeline 26:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x8 0xa
>[   36.092282] [drm:drm_mode_getconnector], connector id 7:
>[   36.092755] [drm:drm_mode_getconnector], connector id 11:
>[   36.092760] [drm:drm_helper_probe_single_connector_modes], SVIDEO-1
>[   36.092767] [drm:intel_update_watermarks], plane B (pipe 0) clock: 107520
>[   36.092771] [drm:intel_update_watermarks], plane A (pipe 1) clock: 65000
>[   36.092774] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[   36.092778] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[   36.092782] [drm:intel_calculate_wm], FIFO entries required for mode: 20
>[   36.092785] [drm:intel_calculate_wm], FIFO watermark level: 6
>[   36.092789] [drm:intel_calculate_wm], FIFO entries required for mode: 33
>[   36.092792] [drm:intel_calculate_wm], FIFO watermark level: -4
>[   36.092795] [drm:i9xx_update_wm], FIFO watermarks - A: 6, B: 1
>[   36.092799] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 6, B: 1, C: 2, SR 1
>[   36.116499] [drm:intel_crtc_mode_set], Mode for pipe A:
>[   36.116503] [drm:drm_mode_debug_printmodeline], Modeline 0:"NTSC 480i" 0 107520 1280 1368 1496 1712 1024 1027 1034 1104 0x40 0x0
>[   36.140072] [drm:intel_pipe_set_base], No FB bound
>[   36.140076] [drm:intel_update_watermarks], plane B (pipe 0) clock: 107520
>[   36.140080] [drm:intel_update_watermarks], plane A (pipe 1) clock: 65000
>[   36.140084] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[   36.140088] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[   36.140091] [drm:intel_calculate_wm], FIFO entries required for mode: 20
>[   36.140095] [drm:intel_calculate_wm], FIFO watermark level: 6
>[   36.140098] [drm:intel_calculate_wm], FIFO entries required for mode: 33
>[   36.140101] [drm:intel_calculate_wm], FIFO watermark level: -4
>[   36.140105] [drm:i9xx_update_wm], FIFO watermarks - A: 6, B: 1
>[   36.140108] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 6, B: 1, C: 2, SR 1
>[   36.164094] [drm:intel_update_watermarks], plane B (pipe 0) clock: 107520
>[   36.164099] [drm:intel_update_watermarks], plane A (pipe 1) clock: 65000
>[   36.164103] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[   36.164107] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[   36.164111] [drm:intel_calculate_wm], FIFO entries required for mode: 20
>[   36.164114] [drm:intel_calculate_wm], FIFO watermark level: 6
>[   36.164117] [drm:intel_calculate_wm], FIFO entries required for mode: 33
>[   36.164121] [drm:intel_calculate_wm], FIFO watermark level: -4
>[   36.164124] [drm:i9xx_update_wm], FIFO watermarks - A: 6, B: 1
>[   36.164127] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 6, B: 1, C: 2, SR 1
>[   36.236028] [drm:intel_tv_detect_type], No TV connection detected
>[   36.236034] [drm:intel_update_watermarks], plane A (pipe 1) clock: 65000
>[   36.236038] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[   36.236043] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[   36.236046] [drm:intel_calculate_wm], FIFO entries required for mode: 20
>[   36.236050] [drm:intel_calculate_wm], FIFO watermark level: 6
>[   36.236053] [drm:intel_calculate_wm], FIFO entries required for mode: 0
>[   36.236056] [drm:intel_calculate_wm], FIFO watermark level: 29
>[   36.236059] [drm:i9xx_update_wm], FIFO watermarks - A: 6, B: 29
>[   36.236063] [drm:i9xx_update_wm], self-refresh entries: 25
>[   36.236066] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 6, B: 29, C: 2, SR 70
>[   36.260226] [drm:drm_helper_probe_single_connector_modes], SVIDEO-1 is disconnected
>[   36.260239] [drm:drm_mode_getconnector], connector id 11:
>[   36.260243] [drm:drm_helper_probe_single_connector_modes], SVIDEO-1
>[   36.260250] [drm:intel_update_watermarks], plane B (pipe 0) clock: 107520
>[   36.260253] [drm:intel_update_watermarks], plane A (pipe 1) clock: 65000
>[   36.260257] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[   36.260261] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[   36.260265] [drm:intel_calculate_wm], FIFO entries required for mode: 20
>[   36.260268] [drm:intel_calculate_wm], FIFO watermark level: 6
>[   36.260271] [drm:intel_calculate_wm], FIFO entries required for mode: 33
>[   36.260275] [drm:intel_calculate_wm], FIFO watermark level: -4
>[   36.260278] [drm:i9xx_update_wm], FIFO watermarks - A: 6, B: 1
>[   36.260281] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 6, B: 1, C: 2, SR 1
>[   36.284492] [drm:intel_crtc_mode_set], Mode for pipe A:
>[   36.284497] [drm:drm_mode_debug_printmodeline], Modeline 0:"NTSC 480i" 0 107520 1280 1368 1496 1712 1024 1027 1034 1104 0x40 0x0
>[   36.308059] [drm:intel_pipe_set_base], No FB bound
>[   36.308062] [drm:intel_update_watermarks], plane B (pipe 0) clock: 107520
>[   36.308066] [drm:intel_update_watermarks], plane A (pipe 1) clock: 65000
>[   36.308070] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[   36.308074] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[   36.308078] [drm:intel_calculate_wm], FIFO entries required for mode: 20
>[   36.308081] [drm:intel_calculate_wm], FIFO watermark level: 6
>[   36.308084] [drm:intel_calculate_wm], FIFO entries required for mode: 33
>[   36.308088] [drm:intel_calculate_wm], FIFO watermark level: -4
>[   36.308091] [drm:i9xx_update_wm], FIFO watermarks - A: 6, B: 1
>[   36.308095] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 6, B: 1, C: 2, SR 1
>[   36.332087] [drm:intel_update_watermarks], plane B (pipe 0) clock: 107520
>[   36.332091] [drm:intel_update_watermarks], plane A (pipe 1) clock: 65000
>[   36.332095] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[   36.332100] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[   36.332103] [drm:intel_calculate_wm], FIFO entries required for mode: 20
>[   36.332107] [drm:intel_calculate_wm], FIFO watermark level: 6
>[   36.332110] [drm:intel_calculate_wm], FIFO entries required for mode: 33
>[   36.332113] [drm:intel_calculate_wm], FIFO watermark level: -4
>[   36.332116] [drm:i9xx_update_wm], FIFO watermarks - A: 6, B: 1
>[   36.332120] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 6, B: 1, C: 2, SR 1
>[   36.404066] [drm:intel_tv_detect_type], No TV connection detected
>[   36.404072] [drm:intel_update_watermarks], plane A (pipe 1) clock: 65000
>[   36.404076] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[   36.404080] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[   36.404084] [drm:intel_calculate_wm], FIFO entries required for mode: 20
>[   36.404087] [drm:intel_calculate_wm], FIFO watermark level: 6
>[   36.404091] [drm:intel_calculate_wm], FIFO entries required for mode: 0
>[   36.404094] [drm:intel_calculate_wm], FIFO watermark level: 29
>[   36.404097] [drm:i9xx_update_wm], FIFO watermarks - A: 6, B: 29
>[   36.404101] [drm:i9xx_update_wm], self-refresh entries: 25
>[   36.404104] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 6, B: 29, C: 2, SR 70
>[   36.428187] [drm:drm_helper_probe_single_connector_modes], SVIDEO-1 is disconnected
>[   36.780817] [drm:intel_crtc_cursor_set], 
>[   37.732468] [drm:intel_update_watermarks], plane B (pipe 0) clock: 31500
>[   37.732478] [drm:intel_update_watermarks], plane A (pipe 1) clock: 65000
>[   37.732482] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[   37.732487] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[   37.732491] [drm:intel_calculate_wm], FIFO entries required for mode: 20
>[   37.732494] [drm:intel_calculate_wm], FIFO watermark level: 6
>[   37.732497] [drm:intel_calculate_wm], FIFO entries required for mode: 9
>[   37.732501] [drm:intel_calculate_wm], FIFO watermark level: 20
>[   37.732504] [drm:i9xx_update_wm], FIFO watermarks - A: 6, B: 20
>[   37.732508] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 6, B: 20, C: 2, SR 1
>[   37.757739] [drm:intel_crtc_mode_set], Mode for pipe A:
>[   37.757747] [drm:drm_mode_debug_printmodeline], Modeline 0:"640x480" 0 31500 640 664 704 832 480 489 491 520 0x10 0xa
>[   37.780031] [drm:intel_pipe_set_base], No FB bound
>[   37.780038] [drm:intel_update_watermarks], plane B (pipe 0) clock: 31500
>[   37.780042] [drm:intel_update_watermarks], plane A (pipe 1) clock: 65000
>[   37.780047] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[   37.780051] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[   37.780055] [drm:intel_calculate_wm], FIFO entries required for mode: 20
>[   37.780059] [drm:intel_calculate_wm], FIFO watermark level: 6
>[   37.780062] [drm:intel_calculate_wm], FIFO entries required for mode: 9
>[   37.780065] [drm:intel_calculate_wm], FIFO watermark level: 20
>[   37.780068] [drm:i9xx_update_wm], FIFO watermarks - A: 6, B: 20
>[   37.780072] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 6, B: 20, C: 2, SR 1
>[   37.780080] [drm:intel_update_watermarks], plane B (pipe 0) clock: 31500
>[   37.780083] [drm:intel_update_watermarks], plane A (pipe 1) clock: 65000
>[   37.780087] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[   37.780091] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[   37.780095] [drm:intel_calculate_wm], FIFO entries required for mode: 20
>[   37.780098] [drm:intel_calculate_wm], FIFO watermark level: 6
>[   37.780101] [drm:intel_calculate_wm], FIFO entries required for mode: 9
>[   37.780104] [drm:intel_calculate_wm], FIFO watermark level: 20
>[   37.780107] [drm:i9xx_update_wm], FIFO watermarks - A: 6, B: 20
>[   37.780111] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 6, B: 20, C: 2, SR 1
>[   37.828041] [drm:intel_update_watermarks], plane A (pipe 1) clock: 65000
>[   37.828052] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[   37.828057] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[   37.828061] [drm:intel_calculate_wm], FIFO entries required for mode: 20
>[   37.828065] [drm:intel_calculate_wm], FIFO watermark level: 6
>[   37.828068] [drm:intel_calculate_wm], FIFO entries required for mode: 0
>[   37.828071] [drm:intel_calculate_wm], FIFO watermark level: 29
>[   37.828074] [drm:i9xx_update_wm], FIFO watermarks - A: 6, B: 29
>[   37.828078] [drm:i9xx_update_wm], self-refresh entries: 25
>[   37.828082] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 6, B: 29, C: 2, SR 70
>[   38.984098] eth1: no IPv6 routers present
>[   39.200624] EXT4-fs (sda1): re-mounted. Opts: errors=remount-ro,commit=0
>[   41.791997] [drm:intel_crtc_cursor_set], 
>[   41.792028] [drm:intel_crtc_cursor_set], cursor off
>[   41.866715] [drm:intel_crtc_cursor_set], 
>[   43.072758] [drm:drm_mode_getconnector], connector id 5:
>[   43.072769] [drm:drm_helper_probe_single_connector_modes], VGA-1
>[   43.079211] [drm:intel_update_watermarks], plane B (pipe 0) clock: 31500
>[   43.079218] [drm:intel_update_watermarks], plane A (pipe 1) clock: 65000
>[   43.079222] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[   43.079227] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[   43.079231] [drm:intel_calculate_wm], FIFO entries required for mode: 20
>[   43.079234] [drm:intel_calculate_wm], FIFO watermark level: 6
>[   43.079237] [drm:intel_calculate_wm], FIFO entries required for mode: 9
>[   43.079240] [drm:intel_calculate_wm], FIFO watermark level: 20
>[   43.079244] [drm:i9xx_update_wm], FIFO watermarks - A: 6, B: 20
>[   43.079248] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 6, B: 20, C: 2, SR 1
>[   43.100515] [drm:intel_crtc_mode_set], Mode for pipe A:
>[   43.100522] [drm:drm_mode_debug_printmodeline], Modeline 0:"640x480" 0 31500 640 664 704 832 480 489 491 520 0x10 0xa
>[   43.124028] [drm:intel_pipe_set_base], No FB bound
>[   43.124032] [drm:intel_update_watermarks], plane B (pipe 0) clock: 31500
>[   43.124036] [drm:intel_update_watermarks], plane A (pipe 1) clock: 65000
>[   43.124040] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[   43.124044] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[   43.124048] [drm:intel_calculate_wm], FIFO entries required for mode: 20
>[   43.124051] [drm:intel_calculate_wm], FIFO watermark level: 6
>[   43.124055] [drm:intel_calculate_wm], FIFO entries required for mode: 9
>[   43.124058] [drm:intel_calculate_wm], FIFO watermark level: 20
>[   43.124061] [drm:i9xx_update_wm], FIFO watermarks - A: 6, B: 20
>[   43.124065] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 6, B: 20, C: 2, SR 1
>[   43.124071] [drm:intel_update_watermarks], plane B (pipe 0) clock: 31500
>[   43.124074] [drm:intel_update_watermarks], plane A (pipe 1) clock: 65000
>[   43.124078] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[   43.124082] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[   43.124085] [drm:intel_calculate_wm], FIFO entries required for mode: 20
>[   43.124089] [drm:intel_calculate_wm], FIFO watermark level: 6
>[   43.124092] [drm:intel_calculate_wm], FIFO entries required for mode: 9
>[   43.124095] [drm:intel_calculate_wm], FIFO watermark level: 20
>[   43.124098] [drm:i9xx_update_wm], FIFO watermarks - A: 6, B: 20
>[   43.124102] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 6, B: 20, C: 2, SR 1
>[   43.172074] [drm:intel_update_watermarks], plane A (pipe 1) clock: 65000
>[   43.172078] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[   43.172083] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[   43.172086] [drm:intel_calculate_wm], FIFO entries required for mode: 20
>[   43.172090] [drm:intel_calculate_wm], FIFO watermark level: 6
>[   43.172093] [drm:intel_calculate_wm], FIFO entries required for mode: 0
>[   43.172096] [drm:intel_calculate_wm], FIFO watermark level: 29
>[   43.172099] [drm:i9xx_update_wm], FIFO watermarks - A: 6, B: 29
>[   43.172103] [drm:i9xx_update_wm], self-refresh entries: 25
>[   43.172106] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 6, B: 29, C: 2, SR 70
>[   43.196226] [drm:drm_helper_probe_single_connector_modes], VGA-1 is disconnected
>[   43.196252] [drm:drm_mode_getconnector], connector id 5:
>[   43.196257] [drm:drm_helper_probe_single_connector_modes], VGA-1
>[   43.200871] [drm:intel_update_watermarks], plane B (pipe 0) clock: 31500
>[   43.200875] [drm:intel_update_watermarks], plane A (pipe 1) clock: 65000
>[   43.200879] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[   43.200883] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[   43.200887] [drm:intel_calculate_wm], FIFO entries required for mode: 20
>[   43.200890] [drm:intel_calculate_wm], FIFO watermark level: 6
>[   43.200893] [drm:intel_calculate_wm], FIFO entries required for mode: 9
>[   43.200897] [drm:intel_calculate_wm], FIFO watermark level: 20
>[   43.200900] [drm:i9xx_update_wm], FIFO watermarks - A: 6, B: 20
>[   43.200903] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 6, B: 20, C: 2, SR 1
>[   43.224499] [drm:intel_crtc_mode_set], Mode for pipe A:
>[   43.224503] [drm:drm_mode_debug_printmodeline], Modeline 0:"640x480" 0 31500 640 664 704 832 480 489 491 520 0x10 0xa
>[   43.248071] [drm:intel_pipe_set_base], No FB bound
>[   43.248075] [drm:intel_update_watermarks], plane B (pipe 0) clock: 31500
>[   43.248078] [drm:intel_update_watermarks], plane A (pipe 1) clock: 65000
>[   43.248082] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[   43.248086] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[   43.248090] [drm:intel_calculate_wm], FIFO entries required for mode: 20
>[   43.248093] [drm:intel_calculate_wm], FIFO watermark level: 6
>[   43.248096] [drm:intel_calculate_wm], FIFO entries required for mode: 9
>[   43.248100] [drm:intel_calculate_wm], FIFO watermark level: 20
>[   43.248103] [drm:i9xx_update_wm], FIFO watermarks - A: 6, B: 20
>[   43.248107] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 6, B: 20, C: 2, SR 1
>[   43.248112] [drm:intel_update_watermarks], plane B (pipe 0) clock: 31500
>[   43.248115] [drm:intel_update_watermarks], plane A (pipe 1) clock: 65000
>[   43.248119] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[   43.248123] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[   43.248126] [drm:intel_calculate_wm], FIFO entries required for mode: 20
>[   43.248130] [drm:intel_calculate_wm], FIFO watermark level: 6
>[   43.248133] [drm:intel_calculate_wm], FIFO entries required for mode: 9
>[   43.248136] [drm:intel_calculate_wm], FIFO watermark level: 20
>[   43.248139] [drm:i9xx_update_wm], FIFO watermarks - A: 6, B: 20
>[   43.248143] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 6, B: 20, C: 2, SR 1
>[   43.296073] [drm:intel_update_watermarks], plane A (pipe 1) clock: 65000
>[   43.296078] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[   43.296082] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[   43.296085] [drm:intel_calculate_wm], FIFO entries required for mode: 20
>[   43.296089] [drm:intel_calculate_wm], FIFO watermark level: 6
>[   43.296092] [drm:intel_calculate_wm], FIFO entries required for mode: 0
>[   43.296095] [drm:intel_calculate_wm], FIFO watermark level: 29
>[   43.296098] [drm:i9xx_update_wm], FIFO watermarks - A: 6, B: 29
>[   43.296102] [drm:i9xx_update_wm], self-refresh entries: 25
>[   43.296105] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 6, B: 29, C: 2, SR 70
>[   43.320222] [drm:drm_helper_probe_single_connector_modes], VGA-1 is disconnected
>[   43.320255] [drm:drm_mode_getconnector], connector id 7:
>[   43.320260] [drm:drm_helper_probe_single_connector_modes], LVDS-1
>[   43.320268] [drm:drm_helper_probe_single_connector_modes], Probed modes for LVDS-1
>[   43.320271] [drm:drm_mode_debug_printmodeline], Modeline 26:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x8 0xa
>[   43.320279] [drm:drm_mode_getconnector], connector id 7:
>[   43.320769] [drm:drm_mode_getconnector], connector id 11:
>[   43.320774] [drm:drm_helper_probe_single_connector_modes], SVIDEO-1
>[   43.320781] [drm:intel_update_watermarks], plane B (pipe 0) clock: 107520
>[   43.320785] [drm:intel_update_watermarks], plane A (pipe 1) clock: 65000
>[   43.320789] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[   43.320793] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[   43.320796] [drm:intel_calculate_wm], FIFO entries required for mode: 20
>[   43.320800] [drm:intel_calculate_wm], FIFO watermark level: 6
>[   43.320803] [drm:intel_calculate_wm], FIFO entries required for mode: 33
>[   43.320806] [drm:intel_calculate_wm], FIFO watermark level: -4
>[   43.320809] [drm:i9xx_update_wm], FIFO watermarks - A: 6, B: 1
>[   43.320813] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 6, B: 1, C: 2, SR 1
>[   43.344498] [drm:intel_crtc_mode_set], Mode for pipe A:
>[   43.344501] [drm:drm_mode_debug_printmodeline], Modeline 0:"NTSC 480i" 0 107520 1280 1368 1496 1712 1024 1027 1034 1104 0x40 0x0
>[   43.368074] [drm:intel_pipe_set_base], No FB bound
>[   43.368077] [drm:intel_update_watermarks], plane B (pipe 0) clock: 107520
>[   43.368081] [drm:intel_update_watermarks], plane A (pipe 1) clock: 65000
>[   43.368085] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[   43.368089] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[   43.368092] [drm:intel_calculate_wm], FIFO entries required for mode: 20
>[   43.368096] [drm:intel_calculate_wm], FIFO watermark level: 6
>[   43.368099] [drm:intel_calculate_wm], FIFO entries required for mode: 33
>[   43.368102] [drm:intel_calculate_wm], FIFO watermark level: -4
>[   43.368105] [drm:i9xx_update_wm], FIFO watermarks - A: 6, B: 1
>[   43.368109] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 6, B: 1, C: 2, SR 1
>[   43.392102] [drm:intel_update_watermarks], plane B (pipe 0) clock: 107520
>[   43.392106] [drm:intel_update_watermarks], plane A (pipe 1) clock: 65000
>[   43.392110] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[   43.392114] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[   43.392118] [drm:intel_calculate_wm], FIFO entries required for mode: 20
>[   43.392121] [drm:intel_calculate_wm], FIFO watermark level: 6
>[   43.392124] [drm:intel_calculate_wm], FIFO entries required for mode: 33
>[   43.392127] [drm:intel_calculate_wm], FIFO watermark level: -4
>[   43.392131] [drm:i9xx_update_wm], FIFO watermarks - A: 6, B: 1
>[   43.392134] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 6, B: 1, C: 2, SR 1
>[   43.464071] [drm:intel_tv_detect_type], No TV connection detected
>[   43.464077] [drm:intel_update_watermarks], plane A (pipe 1) clock: 65000
>[   43.464081] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[   43.464085] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[   43.464088] [drm:intel_calculate_wm], FIFO entries required for mode: 20
>[   43.464092] [drm:intel_calculate_wm], FIFO watermark level: 6
>[   43.464095] [drm:intel_calculate_wm], FIFO entries required for mode: 0
>[   43.464098] [drm:intel_calculate_wm], FIFO watermark level: 29
>[   43.464101] [drm:i9xx_update_wm], FIFO watermarks - A: 6, B: 29
>[   43.464105] [drm:i9xx_update_wm], self-refresh entries: 25
>[   43.464108] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 6, B: 29, C: 2, SR 70
>[   43.488222] [drm:drm_helper_probe_single_connector_modes], SVIDEO-1 is disconnected
>[   43.488234] [drm:drm_mode_getconnector], connector id 11:
>[   43.488238] [drm:drm_helper_probe_single_connector_modes], SVIDEO-1
>[   43.488244] [drm:intel_update_watermarks], plane B (pipe 0) clock: 107520
>[   43.488248] [drm:intel_update_watermarks], plane A (pipe 1) clock: 65000
>[   43.488252] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[   43.488256] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[   43.488259] [drm:intel_calculate_wm], FIFO entries required for mode: 20
>[   43.488263] [drm:intel_calculate_wm], FIFO watermark level: 6
>[   43.488266] [drm:intel_calculate_wm], FIFO entries required for mode: 33
>[   43.488269] [drm:intel_calculate_wm], FIFO watermark level: -4
>[   43.488272] [drm:i9xx_update_wm], FIFO watermarks - A: 6, B: 1
>[   43.488276] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 6, B: 1, C: 2, SR 1
>[   43.512501] [drm:intel_crtc_mode_set], Mode for pipe A:
>[   43.512505] [drm:drm_mode_debug_printmodeline], Modeline 0:"NTSC 480i" 0 107520 1280 1368 1496 1712 1024 1027 1034 1104 0x40 0x0
>[   43.536073] [drm:intel_pipe_set_base], No FB bound
>[   43.536077] [drm:intel_update_watermarks], plane B (pipe 0) clock: 107520
>[   43.536081] [drm:intel_update_watermarks], plane A (pipe 1) clock: 65000
>[   43.536084] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[   43.536088] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[   43.536092] [drm:intel_calculate_wm], FIFO entries required for mode: 20
>[   43.536095] [drm:intel_calculate_wm], FIFO watermark level: 6
>[   43.536099] [drm:intel_calculate_wm], FIFO entries required for mode: 33
>[   43.536102] [drm:intel_calculate_wm], FIFO watermark level: -4
>[   43.536105] [drm:i9xx_update_wm], FIFO watermarks - A: 6, B: 1
>[   43.536109] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 6, B: 1, C: 2, SR 1
>[   43.560102] [drm:intel_update_watermarks], plane B (pipe 0) clock: 107520
>[   43.560106] [drm:intel_update_watermarks], plane A (pipe 1) clock: 65000
>[   43.560110] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[   43.560114] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[   43.560117] [drm:intel_calculate_wm], FIFO entries required for mode: 20
>[   43.560121] [drm:intel_calculate_wm], FIFO watermark level: 6
>[   43.560124] [drm:intel_calculate_wm], FIFO entries required for mode: 33
>[   43.560127] [drm:intel_calculate_wm], FIFO watermark level: -4
>[   43.560130] [drm:i9xx_update_wm], FIFO watermarks - A: 6, B: 1
>[   43.560134] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 6, B: 1, C: 2, SR 1
>[   43.632071] [drm:intel_tv_detect_type], No TV connection detected
>[   43.632076] [drm:intel_update_watermarks], plane A (pipe 1) clock: 65000
>[   43.632080] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[   43.632084] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[   43.632088] [drm:intel_calculate_wm], FIFO entries required for mode: 20
>[   43.632091] [drm:intel_calculate_wm], FIFO watermark level: 6
>[   43.632095] [drm:intel_calculate_wm], FIFO entries required for mode: 0
>[   43.632098] [drm:intel_calculate_wm], FIFO watermark level: 29
>[   43.632101] [drm:i9xx_update_wm], FIFO watermarks - A: 6, B: 29
>[   43.632104] [drm:i9xx_update_wm], self-refresh entries: 25
>[   43.632108] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 6, B: 29, C: 2, SR 70
>[   43.656222] [drm:drm_helper_probe_single_connector_modes], SVIDEO-1 is disconnected
>[   43.660165] [drm:drm_mode_getconnector], connector id 5:
>[   43.660173] [drm:drm_helper_probe_single_connector_modes], VGA-1
>[   43.664726] [drm:intel_update_watermarks], plane B (pipe 0) clock: 31500
>[   43.664730] [drm:intel_update_watermarks], plane A (pipe 1) clock: 65000
>[   43.664735] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[   43.664739] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[   43.664743] [drm:intel_calculate_wm], FIFO entries required for mode: 20
>[   43.664746] [drm:intel_calculate_wm], FIFO watermark level: 6
>[   43.664749] [drm:intel_calculate_wm], FIFO entries required for mode: 9
>[   43.664753] [drm:intel_calculate_wm], FIFO watermark level: 20
>[   43.664756] [drm:i9xx_update_wm], FIFO watermarks - A: 6, B: 20
>[   43.664759] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 6, B: 20, C: 2, SR 1
>[   43.688505] [drm:intel_crtc_mode_set], Mode for pipe A:
>[   43.688509] [drm:drm_mode_debug_printmodeline], Modeline 0:"640x480" 0 31500 640 664 704 832 480 489 491 520 0x10 0xa
>[   43.712073] [drm:intel_pipe_set_base], No FB bound
>[   43.712077] [drm:intel_update_watermarks], plane B (pipe 0) clock: 31500
>[   43.712080] [drm:intel_update_watermarks], plane A (pipe 1) clock: 65000
>[   43.712084] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[   43.712088] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[   43.712092] [drm:intel_calculate_wm], FIFO entries required for mode: 20
>[   43.712095] [drm:intel_calculate_wm], FIFO watermark level: 6
>[   43.712098] [drm:intel_calculate_wm], FIFO entries required for mode: 9
>[   43.712102] [drm:intel_calculate_wm], FIFO watermark level: 20
>[   43.712105] [drm:i9xx_update_wm], FIFO watermarks - A: 6, B: 20
>[   43.712108] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 6, B: 20, C: 2, SR 1
>[   43.712114] [drm:intel_update_watermarks], plane B (pipe 0) clock: 31500
>[   43.712117] [drm:intel_update_watermarks], plane A (pipe 1) clock: 65000
>[   43.712121] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[   43.712125] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[   43.712128] [drm:intel_calculate_wm], FIFO entries required for mode: 20
>[   43.712131] [drm:intel_calculate_wm], FIFO watermark level: 6
>[   43.712135] [drm:intel_calculate_wm], FIFO entries required for mode: 9
>[   43.712138] [drm:intel_calculate_wm], FIFO watermark level: 20
>[   43.712141] [drm:i9xx_update_wm], FIFO watermarks - A: 6, B: 20
>[   43.712145] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 6, B: 20, C: 2, SR 1
>[   43.760059] [drm:intel_update_watermarks], plane A (pipe 1) clock: 65000
>[   43.760064] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[   43.760068] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[   43.760072] [drm:intel_calculate_wm], FIFO entries required for mode: 20
>[   43.760075] [drm:intel_calculate_wm], FIFO watermark level: 6
>[   43.760078] [drm:intel_calculate_wm], FIFO entries required for mode: 0
>[   43.760082] [drm:intel_calculate_wm], FIFO watermark level: 29
>[   43.760085] [drm:i9xx_update_wm], FIFO watermarks - A: 6, B: 29
>[   43.760088] [drm:i9xx_update_wm], self-refresh entries: 25
>[   43.760092] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 6, B: 29, C: 2, SR 70
>[   43.784224] [drm:drm_helper_probe_single_connector_modes], VGA-1 is disconnected
>[   43.784238] [drm:drm_mode_getconnector], connector id 5:
>[   43.784242] [drm:drm_helper_probe_single_connector_modes], VGA-1
>[   43.788823] [drm:intel_update_watermarks], plane B (pipe 0) clock: 31500
>[   43.788827] [drm:intel_update_watermarks], plane A (pipe 1) clock: 65000
>[   43.788831] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[   43.788835] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[   43.788838] [drm:intel_calculate_wm], FIFO entries required for mode: 20
>[   43.788842] [drm:intel_calculate_wm], FIFO watermark level: 6
>[   43.788845] [drm:intel_calculate_wm], FIFO entries required for mode: 9
>[   43.788848] [drm:intel_calculate_wm], FIFO watermark level: 20
>[   43.788851] [drm:i9xx_update_wm], FIFO watermarks - A: 6, B: 20
>[   43.788855] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 6, B: 20, C: 2, SR 1
>[   43.812500] [drm:intel_crtc_mode_set], Mode for pipe A:
>[   43.812503] [drm:drm_mode_debug_printmodeline], Modeline 0:"640x480" 0 31500 640 664 704 832 480 489 491 520 0x10 0xa
>[   43.836073] [drm:intel_pipe_set_base], No FB bound
>[   43.836076] [drm:intel_update_watermarks], plane B (pipe 0) clock: 31500
>[   43.836080] [drm:intel_update_watermarks], plane A (pipe 1) clock: 65000
>[   43.836084] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[   43.836088] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[   43.836091] [drm:intel_calculate_wm], FIFO entries required for mode: 20
>[   43.836095] [drm:intel_calculate_wm], FIFO watermark level: 6
>[   43.836098] [drm:intel_calculate_wm], FIFO entries required for mode: 9
>[   43.836101] [drm:intel_calculate_wm], FIFO watermark level: 20
>[   43.836104] [drm:i9xx_update_wm], FIFO watermarks - A: 6, B: 20
>[   43.836108] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 6, B: 20, C: 2, SR 1
>[   43.836113] [drm:intel_update_watermarks], plane B (pipe 0) clock: 31500
>[   43.836116] [drm:intel_update_watermarks], plane A (pipe 1) clock: 65000
>[   43.836120] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[   43.836124] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[   43.836128] [drm:intel_calculate_wm], FIFO entries required for mode: 20
>[   43.836131] [drm:intel_calculate_wm], FIFO watermark level: 6
>[   43.836134] [drm:intel_calculate_wm], FIFO entries required for mode: 9
>[   43.836137] [drm:intel_calculate_wm], FIFO watermark level: 20
>[   43.836140] [drm:i9xx_update_wm], FIFO watermarks - A: 6, B: 20
>[   43.836144] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 6, B: 20, C: 2, SR 1
>[   43.884075] [drm:intel_update_watermarks], plane A (pipe 1) clock: 65000
>[   43.884079] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[   43.884083] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[   43.884087] [drm:intel_calculate_wm], FIFO entries required for mode: 20
>[   43.884090] [drm:intel_calculate_wm], FIFO watermark level: 6
>[   43.884093] [drm:intel_calculate_wm], FIFO entries required for mode: 0
>[   43.884097] [drm:intel_calculate_wm], FIFO watermark level: 29
>[   43.884100] [drm:i9xx_update_wm], FIFO watermarks - A: 6, B: 29
>[   43.884103] [drm:i9xx_update_wm], self-refresh entries: 25
>[   43.884107] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 6, B: 29, C: 2, SR 70
>[   43.908224] [drm:drm_helper_probe_single_connector_modes], VGA-1 is disconnected
>[   43.908245] [drm:drm_mode_getconnector], connector id 7:
>[   43.908250] [drm:drm_helper_probe_single_connector_modes], LVDS-1
>[   43.908257] [drm:drm_helper_probe_single_connector_modes], Probed modes for LVDS-1
>[   43.908261] [drm:drm_mode_debug_printmodeline], Modeline 26:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x8 0xa
>[   43.908270] [drm:drm_mode_getconnector], connector id 7:
>[   43.908745] [drm:drm_mode_getconnector], connector id 11:
>[   43.908749] [drm:drm_helper_probe_single_connector_modes], SVIDEO-1
>[   43.908756] [drm:intel_update_watermarks], plane B (pipe 0) clock: 107520
>[   43.908760] [drm:intel_update_watermarks], plane A (pipe 1) clock: 65000
>[   43.908764] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[   43.908768] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[   43.908771] [drm:intel_calculate_wm], FIFO entries required for mode: 20
>[   43.908774] [drm:intel_calculate_wm], FIFO watermark level: 6
>[   43.908778] [drm:intel_calculate_wm], FIFO entries required for mode: 33
>[   43.908781] [drm:intel_calculate_wm], FIFO watermark level: -4
>[   43.908784] [drm:i9xx_update_wm], FIFO watermarks - A: 6, B: 1
>[   43.908788] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 6, B: 1, C: 2, SR 1
>[   43.932496] [drm:intel_crtc_mode_set], Mode for pipe A:
>[   43.932500] [drm:drm_mode_debug_printmodeline], Modeline 0:"NTSC 480i" 0 107520 1280 1368 1496 1712 1024 1027 1034 1104 0x40 0x0
>[   43.956071] [drm:intel_pipe_set_base], No FB bound
>[   43.956075] [drm:intel_update_watermarks], plane B (pipe 0) clock: 107520
>[   43.956079] [drm:intel_update_watermarks], plane A (pipe 1) clock: 65000
>[   43.956082] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[   43.956086] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[   43.956090] [drm:intel_calculate_wm], FIFO entries required for mode: 20
>[   43.956093] [drm:intel_calculate_wm], FIFO watermark level: 6
>[   43.956097] [drm:intel_calculate_wm], FIFO entries required for mode: 33
>[   43.956100] [drm:intel_calculate_wm], FIFO watermark level: -4
>[   43.956103] [drm:i9xx_update_wm], FIFO watermarks - A: 6, B: 1
>[   43.956107] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 6, B: 1, C: 2, SR 1
>[   43.980104] [drm:intel_update_watermarks], plane B (pipe 0) clock: 107520
>[   43.980108] [drm:intel_update_watermarks], plane A (pipe 1) clock: 65000
>[   43.980112] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[   43.980116] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[   43.980119] [drm:intel_calculate_wm], FIFO entries required for mode: 20
>[   43.980123] [drm:intel_calculate_wm], FIFO watermark level: 6
>[   43.980126] [drm:intel_calculate_wm], FIFO entries required for mode: 33
>[   43.980129] [drm:intel_calculate_wm], FIFO watermark level: -4
>[   43.980132] [drm:i9xx_update_wm], FIFO watermarks - A: 6, B: 1
>[   43.980136] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 6, B: 1, C: 2, SR 1
>[   44.052072] [drm:intel_tv_detect_type], No TV connection detected
>[   44.052078] [drm:intel_update_watermarks], plane A (pipe 1) clock: 65000
>[   44.052082] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[   44.052086] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[   44.052090] [drm:intel_calculate_wm], FIFO entries required for mode: 20
>[   44.052093] [drm:intel_calculate_wm], FIFO watermark level: 6
>[   44.052096] [drm:intel_calculate_wm], FIFO entries required for mode: 0
>[   44.052099] [drm:intel_calculate_wm], FIFO watermark level: 29
>[   44.052103] [drm:i9xx_update_wm], FIFO watermarks - A: 6, B: 29
>[   44.052106] [drm:i9xx_update_wm], self-refresh entries: 25
>[   44.052109] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 6, B: 29, C: 2, SR 70
>[   44.076222] [drm:drm_helper_probe_single_connector_modes], SVIDEO-1 is disconnected
>[   44.076235] [drm:drm_mode_getconnector], connector id 11:
>[   44.076239] [drm:drm_helper_probe_single_connector_modes], SVIDEO-1
>[   44.076246] [drm:intel_update_watermarks], plane B (pipe 0) clock: 107520
>[   44.076250] [drm:intel_update_watermarks], plane A (pipe 1) clock: 65000
>[   44.076253] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[   44.076257] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[   44.076261] [drm:intel_calculate_wm], FIFO entries required for mode: 20
>[   44.076264] [drm:intel_calculate_wm], FIFO watermark level: 6
>[   44.076267] [drm:intel_calculate_wm], FIFO entries required for mode: 33
>[   44.076271] [drm:intel_calculate_wm], FIFO watermark level: -4
>[   44.076274] [drm:i9xx_update_wm], FIFO watermarks - A: 6, B: 1
>[   44.076277] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 6, B: 1, C: 2, SR 1
>[   44.100504] [drm:intel_crtc_mode_set], Mode for pipe A:
>[   44.100508] [drm:drm_mode_debug_printmodeline], Modeline 0:"NTSC 480i" 0 107520 1280 1368 1496 1712 1024 1027 1034 1104 0x40 0x0
>[   44.124071] [drm:intel_pipe_set_base], No FB bound
>[   44.124075] [drm:intel_update_watermarks], plane B (pipe 0) clock: 107520
>[   44.124079] [drm:intel_update_watermarks], plane A (pipe 1) clock: 65000
>[   44.124082] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[   44.124086] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[   44.124090] [drm:intel_calculate_wm], FIFO entries required for mode: 20
>[   44.124094] [drm:intel_calculate_wm], FIFO watermark level: 6
>[   44.124097] [drm:intel_calculate_wm], FIFO entries required for mode: 33
>[   44.124100] [drm:intel_calculate_wm], FIFO watermark level: -4
>[   44.124103] [drm:i9xx_update_wm], FIFO watermarks - A: 6, B: 1
>[   44.124107] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 6, B: 1, C: 2, SR 1
>[   44.148103] [drm:intel_update_watermarks], plane B (pipe 0) clock: 107520
>[   44.148108] [drm:intel_update_watermarks], plane A (pipe 1) clock: 65000
>[   44.148112] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[   44.148116] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[   44.148119] [drm:intel_calculate_wm], FIFO entries required for mode: 20
>[   44.148123] [drm:intel_calculate_wm], FIFO watermark level: 6
>[   44.148126] [drm:intel_calculate_wm], FIFO entries required for mode: 33
>[   44.148129] [drm:intel_calculate_wm], FIFO watermark level: -4
>[   44.148132] [drm:i9xx_update_wm], FIFO watermarks - A: 6, B: 1
>[   44.148136] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 6, B: 1, C: 2, SR 1
>[   44.220072] [drm:intel_tv_detect_type], No TV connection detected
>[   44.220078] [drm:intel_update_watermarks], plane A (pipe 1) clock: 65000
>[   44.220082] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[   44.220086] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[   44.220090] [drm:intel_calculate_wm], FIFO entries required for mode: 20
>[   44.220093] [drm:intel_calculate_wm], FIFO watermark level: 6
>[   44.220096] [drm:intel_calculate_wm], FIFO entries required for mode: 0
>[   44.220099] [drm:intel_calculate_wm], FIFO watermark level: 29
>[   44.220102] [drm:i9xx_update_wm], FIFO watermarks - A: 6, B: 29
>[   44.220106] [drm:i9xx_update_wm], self-refresh entries: 25
>[   44.220109] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 6, B: 29, C: 2, SR 70
>[   44.244224] [drm:drm_helper_probe_single_connector_modes], SVIDEO-1 is disconnected
>[   44.245516] [drm:drm_mode_getconnector], connector id 5:
>[   44.245521] [drm:drm_helper_probe_single_connector_modes], VGA-1
>[   44.250124] [drm:intel_update_watermarks], plane B (pipe 0) clock: 31500
>[   44.250129] [drm:intel_update_watermarks], plane A (pipe 1) clock: 65000
>[   44.250133] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[   44.250137] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[   44.250141] [drm:intel_calculate_wm], FIFO entries required for mode: 20
>[   44.250144] [drm:intel_calculate_wm], FIFO watermark level: 6
>[   44.250147] [drm:intel_calculate_wm], FIFO entries required for mode: 9
>[   44.250151] [drm:intel_calculate_wm], FIFO watermark level: 20
>[   44.250154] [drm:i9xx_update_wm], FIFO watermarks - A: 6, B: 20
>[   44.250157] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 6, B: 20, C: 2, SR 1
>[   44.272501] [drm:intel_crtc_mode_set], Mode for pipe A:
>[   44.272505] [drm:drm_mode_debug_printmodeline], Modeline 0:"640x480" 0 31500 640 664 704 832 480 489 491 520 0x10 0xa
>[   44.296065] [drm:intel_pipe_set_base], No FB bound
>[   44.296068] [drm:intel_update_watermarks], plane B (pipe 0) clock: 31500
>[   44.296072] [drm:intel_update_watermarks], plane A (pipe 1) clock: 65000
>[   44.296076] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[   44.296080] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[   44.296084] [drm:intel_calculate_wm], FIFO entries required for mode: 20
>[   44.296087] [drm:intel_calculate_wm], FIFO watermark level: 6
>[   44.296090] [drm:intel_calculate_wm], FIFO entries required for mode: 9
>[   44.296094] [drm:intel_calculate_wm], FIFO watermark level: 20
>[   44.296097] [drm:i9xx_update_wm], FIFO watermarks - A: 6, B: 20
>[   44.296101] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 6, B: 20, C: 2, SR 1
>[   44.296106] [drm:intel_update_watermarks], plane B (pipe 0) clock: 31500
>[   44.296109] [drm:intel_update_watermarks], plane A (pipe 1) clock: 65000
>[   44.296113] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[   44.296117] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[   44.296120] [drm:intel_calculate_wm], FIFO entries required for mode: 20
>[   44.296124] [drm:intel_calculate_wm], FIFO watermark level: 6
>[   44.296127] [drm:intel_calculate_wm], FIFO entries required for mode: 9
>[   44.296130] [drm:intel_calculate_wm], FIFO watermark level: 20
>[   44.296133] [drm:i9xx_update_wm], FIFO watermarks - A: 6, B: 20
>[   44.296137] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 6, B: 20, C: 2, SR 1
>[   44.344075] [drm:intel_update_watermarks], plane A (pipe 1) clock: 65000
>[   44.344080] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[   44.344084] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[   44.344088] [drm:intel_calculate_wm], FIFO entries required for mode: 20
>[   44.344091] [drm:intel_calculate_wm], FIFO watermark level: 6
>[   44.344094] [drm:intel_calculate_wm], FIFO entries required for mode: 0
>[   44.344097] [drm:intel_calculate_wm], FIFO watermark level: 29
>[   44.344101] [drm:i9xx_update_wm], FIFO watermarks - A: 6, B: 29
>[   44.344104] [drm:i9xx_update_wm], self-refresh entries: 25
>[   44.344108] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 6, B: 29, C: 2, SR 70
>[   44.368224] [drm:drm_helper_probe_single_connector_modes], VGA-1 is disconnected
>[   44.368236] [drm:drm_mode_getconnector], connector id 5:
>[   44.368239] [drm:drm_helper_probe_single_connector_modes], VGA-1
>[   44.372822] [drm:intel_update_watermarks], plane B (pipe 0) clock: 31500
>[   44.372826] [drm:intel_update_watermarks], plane A (pipe 1) clock: 65000
>[   44.372830] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[   44.372834] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[   44.372838] [drm:intel_calculate_wm], FIFO entries required for mode: 20
>[   44.372841] [drm:intel_calculate_wm], FIFO watermark level: 6
>[   44.372844] [drm:intel_calculate_wm], FIFO entries required for mode: 9
>[   44.372847] [drm:intel_calculate_wm], FIFO watermark level: 20
>[   44.372850] [drm:i9xx_update_wm], FIFO watermarks - A: 6, B: 20
>[   44.372854] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 6, B: 20, C: 2, SR 1
>[   44.396501] [drm:intel_crtc_mode_set], Mode for pipe A:
>[   44.396504] [drm:drm_mode_debug_printmodeline], Modeline 0:"640x480" 0 31500 640 664 704 832 480 489 491 520 0x10 0xa
>[   44.420073] [drm:intel_pipe_set_base], No FB bound
>[   44.420076] [drm:intel_update_watermarks], plane B (pipe 0) clock: 31500
>[   44.420080] [drm:intel_update_watermarks], plane A (pipe 1) clock: 65000
>[   44.420084] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[   44.420088] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[   44.420091] [drm:intel_calculate_wm], FIFO entries required for mode: 20
>[   44.420095] [drm:intel_calculate_wm], FIFO watermark level: 6
>[   44.420098] [drm:intel_calculate_wm], FIFO entries required for mode: 9
>[   44.420101] [drm:intel_calculate_wm], FIFO watermark level: 20
>[   44.420104] [drm:i9xx_update_wm], FIFO watermarks - A: 6, B: 20
>[   44.420108] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 6, B: 20, C: 2, SR 1
>[   44.420113] [drm:intel_update_watermarks], plane B (pipe 0) clock: 31500
>[   44.420116] [drm:intel_update_watermarks], plane A (pipe 1) clock: 65000
>[   44.420120] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[   44.420124] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[   44.420128] [drm:intel_calculate_wm], FIFO entries required for mode: 20
>[   44.420131] [drm:intel_calculate_wm], FIFO watermark level: 6
>[   44.420134] [drm:intel_calculate_wm], FIFO entries required for mode: 9
>[   44.420137] [drm:intel_calculate_wm], FIFO watermark level: 20
>[   44.420140] [drm:i9xx_update_wm], FIFO watermarks - A: 6, B: 20
>[   44.420144] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 6, B: 20, C: 2, SR 1
>[   44.468074] [drm:intel_update_watermarks], plane A (pipe 1) clock: 65000
>[   44.468079] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[   44.468083] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[   44.468086] [drm:intel_calculate_wm], FIFO entries required for mode: 20
>[   44.468090] [drm:intel_calculate_wm], FIFO watermark level: 6
>[   44.468093] [drm:intel_calculate_wm], FIFO entries required for mode: 0
>[   44.468096] [drm:intel_calculate_wm], FIFO watermark level: 29
>[   44.468099] [drm:i9xx_update_wm], FIFO watermarks - A: 6, B: 29
>[   44.468103] [drm:i9xx_update_wm], self-refresh entries: 25
>[   44.468106] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 6, B: 29, C: 2, SR 70
>[   44.492223] [drm:drm_helper_probe_single_connector_modes], VGA-1 is disconnected
>[   44.492240] [drm:drm_mode_getconnector], connector id 7:
>[   44.492245] [drm:drm_helper_probe_single_connector_modes], LVDS-1
>[   44.492251] [drm:drm_helper_probe_single_connector_modes], Probed modes for LVDS-1
>[   44.492255] [drm:drm_mode_debug_printmodeline], Modeline 26:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x8 0xa
>[   44.492263] [drm:drm_mode_getconnector], connector id 7:
>[   44.492728] [drm:drm_mode_getconnector], connector id 11:
>[   44.492732] [drm:drm_helper_probe_single_connector_modes], SVIDEO-1
>[   44.492739] [drm:intel_update_watermarks], plane B (pipe 0) clock: 107520
>[   44.492742] [drm:intel_update_watermarks], plane A (pipe 1) clock: 65000
>[   44.492746] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[   44.492750] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[   44.492754] [drm:intel_calculate_wm], FIFO entries required for mode: 20
>[   44.492757] [drm:intel_calculate_wm], FIFO watermark level: 6
>[   44.492760] [drm:intel_calculate_wm], FIFO entries required for mode: 33
>[   44.492764] [drm:intel_calculate_wm], FIFO watermark level: -4
>[   44.492767] [drm:i9xx_update_wm], FIFO watermarks - A: 6, B: 1
>[   44.492770] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 6, B: 1, C: 2, SR 1
>[   44.516499] [drm:intel_crtc_mode_set], Mode for pipe A:
>[   44.516503] [drm:drm_mode_debug_printmodeline], Modeline 0:"NTSC 480i" 0 107520 1280 1368 1496 1712 1024 1027 1034 1104 0x40 0x0
>[   44.540067] [drm:intel_pipe_set_base], No FB bound
>[   44.540071] [drm:intel_update_watermarks], plane B (pipe 0) clock: 107520
>[   44.540074] [drm:intel_update_watermarks], plane A (pipe 1) clock: 65000
>[   44.540078] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[   44.540082] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[   44.540086] [drm:intel_calculate_wm], FIFO entries required for mode: 20
>[   44.540089] [drm:intel_calculate_wm], FIFO watermark level: 6
>[   44.540093] [drm:intel_calculate_wm], FIFO entries required for mode: 33
>[   44.540096] [drm:intel_calculate_wm], FIFO watermark level: -4
>[   44.540099] [drm:i9xx_update_wm], FIFO watermarks - A: 6, B: 1
>[   44.540103] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 6, B: 1, C: 2, SR 1
>[   44.564104] [drm:intel_update_watermarks], plane B (pipe 0) clock: 107520
>[   44.564108] [drm:intel_update_watermarks], plane A (pipe 1) clock: 65000
>[   44.564112] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[   44.564116] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[   44.564119] [drm:intel_calculate_wm], FIFO entries required for mode: 20
>[   44.564123] [drm:intel_calculate_wm], FIFO watermark level: 6
>[   44.564126] [drm:intel_calculate_wm], FIFO entries required for mode: 33
>[   44.564129] [drm:intel_calculate_wm], FIFO watermark level: -4
>[   44.564132] [drm:i9xx_update_wm], FIFO watermarks - A: 6, B: 1
>[   44.564136] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 6, B: 1, C: 2, SR 1
>[   44.636072] [drm:intel_tv_detect_type], No TV connection detected
>[   44.636078] [drm:intel_update_watermarks], plane A (pipe 1) clock: 65000
>[   44.636082] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[   44.636086] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[   44.636090] [drm:intel_calculate_wm], FIFO entries required for mode: 20
>[   44.636093] [drm:intel_calculate_wm], FIFO watermark level: 6
>[   44.636096] [drm:intel_calculate_wm], FIFO entries required for mode: 0
>[   44.636100] [drm:intel_calculate_wm], FIFO watermark level: 29
>[   44.636103] [drm:i9xx_update_wm], FIFO watermarks - A: 6, B: 29
>[   44.636106] [drm:i9xx_update_wm], self-refresh entries: 25
>[   44.636110] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 6, B: 29, C: 2, SR 70
>[   44.660224] [drm:drm_helper_probe_single_connector_modes], SVIDEO-1 is disconnected
>[   44.660235] [drm:drm_mode_getconnector], connector id 11:
>[   44.660239] [drm:drm_helper_probe_single_connector_modes], SVIDEO-1
>[   44.660246] [drm:intel_update_watermarks], plane B (pipe 0) clock: 107520
>[   44.660249] [drm:intel_update_watermarks], plane A (pipe 1) clock: 65000
>[   44.660253] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[   44.660257] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[   44.660261] [drm:intel_calculate_wm], FIFO entries required for mode: 20
>[   44.660264] [drm:intel_calculate_wm], FIFO watermark level: 6
>[   44.660267] [drm:intel_calculate_wm], FIFO entries required for mode: 33
>[   44.660271] [drm:intel_calculate_wm], FIFO watermark level: -4
>[   44.660274] [drm:i9xx_update_wm], FIFO watermarks - A: 6, B: 1
>[   44.660277] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 6, B: 1, C: 2, SR 1
>[   44.684503] [drm:intel_crtc_mode_set], Mode for pipe A:
>[   44.684506] [drm:drm_mode_debug_printmodeline], Modeline 0:"NTSC 480i" 0 107520 1280 1368 1496 1712 1024 1027 1034 1104 0x40 0x0
>[   44.708070] [drm:intel_pipe_set_base], No FB bound
>[   44.708074] [drm:intel_update_watermarks], plane B (pipe 0) clock: 107520
>[   44.708078] [drm:intel_update_watermarks], plane A (pipe 1) clock: 65000
>[   44.708081] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[   44.708085] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[   44.708089] [drm:intel_calculate_wm], FIFO entries required for mode: 20
>[   44.708092] [drm:intel_calculate_wm], FIFO watermark level: 6
>[   44.708096] [drm:intel_calculate_wm], FIFO entries required for mode: 33
>[   44.708099] [drm:intel_calculate_wm], FIFO watermark level: -4
>[   44.708102] [drm:i9xx_update_wm], FIFO watermarks - A: 6, B: 1
>[   44.708106] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 6, B: 1, C: 2, SR 1
>[   44.732103] [drm:intel_update_watermarks], plane B (pipe 0) clock: 107520
>[   44.732108] [drm:intel_update_watermarks], plane A (pipe 1) clock: 65000
>[   44.732111] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[   44.732115] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[   44.732119] [drm:intel_calculate_wm], FIFO entries required for mode: 20
>[   44.732122] [drm:intel_calculate_wm], FIFO watermark level: 6
>[   44.732125] [drm:intel_calculate_wm], FIFO entries required for mode: 33
>[   44.732129] [drm:intel_calculate_wm], FIFO watermark level: -4
>[   44.732132] [drm:i9xx_update_wm], FIFO watermarks - A: 6, B: 1
>[   44.732135] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 6, B: 1, C: 2, SR 1
>[   44.804072] [drm:intel_tv_detect_type], No TV connection detected
>[   44.804078] [drm:intel_update_watermarks], plane A (pipe 1) clock: 65000
>[   44.804082] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[   44.804086] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[   44.804089] [drm:intel_calculate_wm], FIFO entries required for mode: 20
>[   44.804092] [drm:intel_calculate_wm], FIFO watermark level: 6
>[   44.804096] [drm:intel_calculate_wm], FIFO entries required for mode: 0
>[   44.804099] [drm:intel_calculate_wm], FIFO watermark level: 29
>[   44.804102] [drm:i9xx_update_wm], FIFO watermarks - A: 6, B: 29
>[   44.804105] [drm:i9xx_update_wm], self-refresh entries: 25
>[   44.804109] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 6, B: 29, C: 2, SR 70
>[   44.828229] [drm:drm_helper_probe_single_connector_modes], SVIDEO-1 is disconnected
>[   44.830156] [drm:intel_crtc_cursor_set], 
>[   44.830160] [drm:intel_crtc_cursor_set], cursor off
>[   44.830752] [drm:intel_crtc_cursor_set], 
>[   47.876468] [drm:intel_update_watermarks], plane B (pipe 0) clock: 31500
>[   47.876477] [drm:intel_update_watermarks], plane A (pipe 1) clock: 65000
>[   47.876482] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[   47.876486] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[   47.876490] [drm:intel_calculate_wm], FIFO entries required for mode: 20
>[   47.876494] [drm:intel_calculate_wm], FIFO watermark level: 6
>[   47.876497] [drm:intel_calculate_wm], FIFO entries required for mode: 9
>[   47.876500] [drm:intel_calculate_wm], FIFO watermark level: 20
>[   47.876504] [drm:i9xx_update_wm], FIFO watermarks - A: 6, B: 20
>[   47.876507] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 6, B: 20, C: 2, SR 1
>[   47.901383] [drm:intel_crtc_mode_set], Mode for pipe A:
>[   47.901389] [drm:drm_mode_debug_printmodeline], Modeline 0:"640x480" 0 31500 640 664 704 832 480 489 491 520 0x10 0xa
>[   47.924032] [drm:intel_pipe_set_base], No FB bound
>[   47.924036] [drm:intel_update_watermarks], plane B (pipe 0) clock: 31500
>[   47.924040] [drm:intel_update_watermarks], plane A (pipe 1) clock: 65000
>[   47.924044] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[   47.924048] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[   47.924052] [drm:intel_calculate_wm], FIFO entries required for mode: 20
>[   47.924055] [drm:intel_calculate_wm], FIFO watermark level: 6
>[   47.924059] [drm:intel_calculate_wm], FIFO entries required for mode: 9
>[   47.924062] [drm:intel_calculate_wm], FIFO watermark level: 20
>[   47.924065] [drm:i9xx_update_wm], FIFO watermarks - A: 6, B: 20
>[   47.924069] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 6, B: 20, C: 2, SR 1
>[   47.924075] [drm:intel_update_watermarks], plane B (pipe 0) clock: 31500
>[   47.924079] [drm:intel_update_watermarks], plane A (pipe 1) clock: 65000
>[   47.924082] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[   47.924086] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[   47.924090] [drm:intel_calculate_wm], FIFO entries required for mode: 20
>[   47.924093] [drm:intel_calculate_wm], FIFO watermark level: 6
>[   47.924096] [drm:intel_calculate_wm], FIFO entries required for mode: 9
>[   47.924100] [drm:intel_calculate_wm], FIFO watermark level: 20
>[   47.924103] [drm:i9xx_update_wm], FIFO watermarks - A: 6, B: 20
>[   47.924106] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 6, B: 20, C: 2, SR 1
>[   47.972038] [drm:intel_update_watermarks], plane A (pipe 1) clock: 65000
>[   47.972045] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[   47.972049] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[   47.972052] [drm:intel_calculate_wm], FIFO entries required for mode: 20
>[   47.972056] [drm:intel_calculate_wm], FIFO watermark level: 6
>[   47.972059] [drm:intel_calculate_wm], FIFO entries required for mode: 0
>[   47.972062] [drm:intel_calculate_wm], FIFO watermark level: 29
>[   47.972066] [drm:i9xx_update_wm], FIFO watermarks - A: 6, B: 29
>[   47.972069] [drm:i9xx_update_wm], self-refresh entries: 25
>[   47.972073] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 6, B: 29, C: 2, SR 70
>[   50.574842] [drm:drm_mode_getconnector], connector id 5:
>[   50.574852] [drm:drm_helper_probe_single_connector_modes], VGA-1
>[   50.579503] [drm:intel_update_watermarks], plane B (pipe 0) clock: 31500
>[   50.579508] [drm:intel_update_watermarks], plane A (pipe 1) clock: 65000
>[   50.579512] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[   50.579517] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[   50.579521] [drm:intel_calculate_wm], FIFO entries required for mode: 20
>[   50.579524] [drm:intel_calculate_wm], FIFO watermark level: 6
>[   50.579527] [drm:intel_calculate_wm], FIFO entries required for mode: 9
>[   50.579531] [drm:intel_calculate_wm], FIFO watermark level: 20
>[   50.579534] [drm:i9xx_update_wm], FIFO watermarks - A: 6, B: 20
>[   50.579538] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 6, B: 20, C: 2, SR 1
>[   50.600467] [drm:intel_crtc_mode_set], Mode for pipe A:
>[   50.600471] [drm:drm_mode_debug_printmodeline], Modeline 0:"640x480" 0 31500 640 664 704 832 480 489 491 520 0x10 0xa
>[   50.624037] [drm:intel_pipe_set_base], No FB bound
>[   50.624040] [drm:intel_update_watermarks], plane B (pipe 0) clock: 31500
>[   50.624044] [drm:intel_update_watermarks], plane A (pipe 1) clock: 65000
>[   50.624048] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[   50.624052] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[   50.624056] [drm:intel_calculate_wm], FIFO entries required for mode: 20
>[   50.624059] [drm:intel_calculate_wm], FIFO watermark level: 6
>[   50.624063] [drm:intel_calculate_wm], FIFO entries required for mode: 9
>[   50.624066] [drm:intel_calculate_wm], FIFO watermark level: 20
>[   50.624069] [drm:i9xx_update_wm], FIFO watermarks - A: 6, B: 20
>[   50.624073] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 6, B: 20, C: 2, SR 1
>[   50.624078] [drm:intel_update_watermarks], plane B (pipe 0) clock: 31500
>[   50.624082] [drm:intel_update_watermarks], plane A (pipe 1) clock: 65000
>[   50.624086] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[   50.624089] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[   50.624093] [drm:intel_calculate_wm], FIFO entries required for mode: 20
>[   50.624096] [drm:intel_calculate_wm], FIFO watermark level: 6
>[   50.624099] [drm:intel_calculate_wm], FIFO entries required for mode: 9
>[   50.624103] [drm:intel_calculate_wm], FIFO watermark level: 20
>[   50.624106] [drm:i9xx_update_wm], FIFO watermarks - A: 6, B: 20
>[   50.624110] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 6, B: 20, C: 2, SR 1
>[   50.672027] [drm:intel_update_watermarks], plane A (pipe 1) clock: 65000
>[   50.672033] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[   50.672038] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[   50.672041] [drm:intel_calculate_wm], FIFO entries required for mode: 20
>[   50.672045] [drm:intel_calculate_wm], FIFO watermark level: 6
>[   50.672048] [drm:intel_calculate_wm], FIFO entries required for mode: 0
>[   50.672051] [drm:intel_calculate_wm], FIFO watermark level: 29
>[   50.672055] [drm:i9xx_update_wm], FIFO watermarks - A: 6, B: 29
>[   50.672058] [drm:i9xx_update_wm], self-refresh entries: 25
>[   50.672062] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 6, B: 29, C: 2, SR 70
>[   50.696172] [drm:drm_helper_probe_single_connector_modes], VGA-1 is disconnected
>[   50.696196] [drm:drm_mode_getconnector], connector id 5:
>[   50.696201] [drm:drm_helper_probe_single_connector_modes], VGA-1
>[   50.700810] [drm:intel_update_watermarks], plane B (pipe 0) clock: 31500
>[   50.700814] [drm:intel_update_watermarks], plane A (pipe 1) clock: 65000
>[   50.700818] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[   50.700822] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[   50.700826] [drm:intel_calculate_wm], FIFO entries required for mode: 20
>[   50.700829] [drm:intel_calculate_wm], FIFO watermark level: 6
>[   50.700832] [drm:intel_calculate_wm], FIFO entries required for mode: 9
>[   50.700836] [drm:intel_calculate_wm], FIFO watermark level: 20
>[   50.700839] [drm:i9xx_update_wm], FIFO watermarks - A: 6, B: 20
>[   50.700843] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 6, B: 20, C: 2, SR 1
>[   50.724471] [drm:intel_crtc_mode_set], Mode for pipe A:
>[   50.724476] [drm:drm_mode_debug_printmodeline], Modeline 0:"640x480" 0 31500 640 664 704 832 480 489 491 520 0x10 0xa
>[   50.748039] [drm:intel_pipe_set_base], No FB bound
>[   50.748042] [drm:intel_update_watermarks], plane B (pipe 0) clock: 31500
>[   50.748046] [drm:intel_update_watermarks], plane A (pipe 1) clock: 65000
>[   50.748050] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[   50.748054] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[   50.748058] [drm:intel_calculate_wm], FIFO entries required for mode: 20
>[   50.748061] [drm:intel_calculate_wm], FIFO watermark level: 6
>[   50.748064] [drm:intel_calculate_wm], FIFO entries required for mode: 9
>[   50.748068] [drm:intel_calculate_wm], FIFO watermark level: 20
>[   50.748071] [drm:i9xx_update_wm], FIFO watermarks - A: 6, B: 20
>[   50.748074] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 6, B: 20, C: 2, SR 1
>[   50.748080] [drm:intel_update_watermarks], plane B (pipe 0) clock: 31500
>[   50.748083] [drm:intel_update_watermarks], plane A (pipe 1) clock: 65000
>[   50.748087] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[   50.748091] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[   50.748095] [drm:intel_calculate_wm], FIFO entries required for mode: 20
>[   50.748098] [drm:intel_calculate_wm], FIFO watermark level: 6
>[   50.748101] [drm:intel_calculate_wm], FIFO entries required for mode: 9
>[   50.748104] [drm:intel_calculate_wm], FIFO watermark level: 20
>[   50.748107] [drm:i9xx_update_wm], FIFO watermarks - A: 6, B: 20
>[   50.748111] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 6, B: 20, C: 2, SR 1
>[   50.796046] [drm:intel_update_watermarks], plane A (pipe 1) clock: 65000
>[   50.796053] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[   50.796058] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[   50.796061] [drm:intel_calculate_wm], FIFO entries required for mode: 20
>[   50.796065] [drm:intel_calculate_wm], FIFO watermark level: 6
>[   50.796068] [drm:intel_calculate_wm], FIFO entries required for mode: 0
>[   50.796071] [drm:intel_calculate_wm], FIFO watermark level: 29
>[   50.796075] [drm:i9xx_update_wm], FIFO watermarks - A: 6, B: 29
>[   50.796078] [drm:i9xx_update_wm], self-refresh entries: 25
>[   50.796082] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 6, B: 29, C: 2, SR 70
>[   50.820213] [drm:drm_helper_probe_single_connector_modes], VGA-1 is disconnected
>[   50.820264] [drm:drm_mode_getconnector], connector id 7:
>[   50.820270] [drm:drm_helper_probe_single_connector_modes], LVDS-1
>[   50.820281] [drm:drm_helper_probe_single_connector_modes], Probed modes for LVDS-1
>[   50.820286] [drm:drm_mode_debug_printmodeline], Modeline 26:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x8 0xa
>[   50.820294] [drm:drm_mode_getconnector], connector id 7:
>[   50.820774] [drm:drm_mode_getconnector], connector id 11:
>[   50.820779] [drm:drm_helper_probe_single_connector_modes], SVIDEO-1
>[   50.820789] [drm:intel_update_watermarks], plane B (pipe 0) clock: 107520
>[   50.820793] [drm:intel_update_watermarks], plane A (pipe 1) clock: 65000
>[   50.820797] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[   50.820802] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[   50.820805] [drm:intel_calculate_wm], FIFO entries required for mode: 20
>[   50.820809] [drm:intel_calculate_wm], FIFO watermark level: 6
>[   50.820812] [drm:intel_calculate_wm], FIFO entries required for mode: 33
>[   50.820815] [drm:intel_calculate_wm], FIFO watermark level: -4
>[   50.820819] [drm:i9xx_update_wm], FIFO watermarks - A: 6, B: 1
>[   50.820822] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 6, B: 1, C: 2, SR 1
>[   50.844478] [drm:intel_crtc_mode_set], Mode for pipe A:
>[   50.844485] [drm:drm_mode_debug_printmodeline], Modeline 0:"NTSC 480i" 0 107520 1280 1368 1496 1712 1024 1027 1034 1104 0x40 0x0
>[   50.868039] [drm:intel_pipe_set_base], No FB bound
>[   50.868043] [drm:intel_update_watermarks], plane B (pipe 0) clock: 107520
>[   50.868048] [drm:intel_update_watermarks], plane A (pipe 1) clock: 65000
>[   50.868052] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[   50.868057] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[   50.868060] [drm:intel_calculate_wm], FIFO entries required for mode: 20
>[   50.868064] [drm:intel_calculate_wm], FIFO watermark level: 6
>[   50.868067] [drm:intel_calculate_wm], FIFO entries required for mode: 33
>[   50.868070] [drm:intel_calculate_wm], FIFO watermark level: -4
>[   50.868074] [drm:i9xx_update_wm], FIFO watermarks - A: 6, B: 1
>[   50.868077] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 6, B: 1, C: 2, SR 1
>[   50.892069] [drm:intel_update_watermarks], plane B (pipe 0) clock: 107520
>[   50.892074] [drm:intel_update_watermarks], plane A (pipe 1) clock: 65000
>[   50.892078] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[   50.892082] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[   50.892086] [drm:intel_calculate_wm], FIFO entries required for mode: 20
>[   50.892089] [drm:intel_calculate_wm], FIFO watermark level: 6
>[   50.892092] [drm:intel_calculate_wm], FIFO entries required for mode: 33
>[   50.892096] [drm:intel_calculate_wm], FIFO watermark level: -4
>[   50.892099] [drm:i9xx_update_wm], FIFO watermarks - A: 6, B: 1
>[   50.892102] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 6, B: 1, C: 2, SR 1
>[   50.964030] [drm:intel_tv_detect_type], No TV connection detected
>[   50.964043] [drm:intel_update_watermarks], plane A (pipe 1) clock: 65000
>[   50.964048] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[   50.964052] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[   50.964056] [drm:intel_calculate_wm], FIFO entries required for mode: 20
>[   50.964060] [drm:intel_calculate_wm], FIFO watermark level: 6
>[   50.964063] [drm:intel_calculate_wm], FIFO entries required for mode: 0
>[   50.964066] [drm:intel_calculate_wm], FIFO watermark level: 29
>[   50.964070] [drm:i9xx_update_wm], FIFO watermarks - A: 6, B: 29
>[   50.964073] [drm:i9xx_update_wm], self-refresh entries: 25
>[   50.964077] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 6, B: 29, C: 2, SR 70
>[   50.988183] [drm:drm_helper_probe_single_connector_modes], SVIDEO-1 is disconnected
>[   50.988214] [drm:drm_mode_getconnector], connector id 11:
>[   50.988219] [drm:drm_helper_probe_single_connector_modes], SVIDEO-1
>[   50.988231] [drm:intel_update_watermarks], plane B (pipe 0) clock: 107520
>[   50.988235] [drm:intel_update_watermarks], plane A (pipe 1) clock: 65000
>[   50.988239] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[   50.988243] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[   50.988247] [drm:intel_calculate_wm], FIFO entries required for mode: 20
>[   50.988250] [drm:intel_calculate_wm], FIFO watermark level: 6
>[   50.988253] [drm:intel_calculate_wm], FIFO entries required for mode: 33
>[   50.988257] [drm:intel_calculate_wm], FIFO watermark level: -4
>[   50.988260] [drm:i9xx_update_wm], FIFO watermarks - A: 6, B: 1
>[   50.988264] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 6, B: 1, C: 2, SR 1
>[   51.012469] [drm:intel_crtc_mode_set], Mode for pipe A:
>[   51.012473] [drm:drm_mode_debug_printmodeline], Modeline 0:"NTSC 480i" 0 107520 1280 1368 1496 1712 1024 1027 1034 1104 0x40 0x0
>[   51.036032] [drm:intel_pipe_set_base], No FB bound
>[   51.036038] [drm:intel_update_watermarks], plane B (pipe 0) clock: 107520
>[   51.036042] [drm:intel_update_watermarks], plane A (pipe 1) clock: 65000
>[   51.036047] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[   51.036051] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[   51.036055] [drm:intel_calculate_wm], FIFO entries required for mode: 20
>[   51.036058] [drm:intel_calculate_wm], FIFO watermark level: 6
>[   51.036062] [drm:intel_calculate_wm], FIFO entries required for mode: 33
>[   51.036065] [drm:intel_calculate_wm], FIFO watermark level: -4
>[   51.036068] [drm:i9xx_update_wm], FIFO watermarks - A: 6, B: 1
>[   51.036072] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 6, B: 1, C: 2, SR 1
>[   51.060051] [drm:intel_update_watermarks], plane B (pipe 0) clock: 107520
>[   51.060057] [drm:intel_update_watermarks], plane A (pipe 1) clock: 65000
>[   51.060061] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[   51.060065] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[   51.060069] [drm:intel_calculate_wm], FIFO entries required for mode: 20
>[   51.060073] [drm:intel_calculate_wm], FIFO watermark level: 6
>[   51.060076] [drm:intel_calculate_wm], FIFO entries required for mode: 33
>[   51.060079] [drm:intel_calculate_wm], FIFO watermark level: -4
>[   51.060082] [drm:i9xx_update_wm], FIFO watermarks - A: 6, B: 1
>[   51.060086] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 6, B: 1, C: 2, SR 1
>[   51.132043] [drm:intel_tv_detect_type], No TV connection detected
>[   51.132056] [drm:intel_update_watermarks], plane A (pipe 1) clock: 65000
>[   51.132061] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[   51.132065] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[   51.132069] [drm:intel_calculate_wm], FIFO entries required for mode: 20
>[   51.132072] [drm:intel_calculate_wm], FIFO watermark level: 6
>[   51.132076] [drm:intel_calculate_wm], FIFO entries required for mode: 0
>[   51.132079] [drm:intel_calculate_wm], FIFO watermark level: 29
>[   51.132082] [drm:i9xx_update_wm], FIFO watermarks - A: 6, B: 29
>[   51.132086] [drm:i9xx_update_wm], self-refresh entries: 25
>[   51.132089] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 6, B: 29, C: 2, SR 70
>[   51.156228] [drm:drm_helper_probe_single_connector_modes], SVIDEO-1 is disconnected
>[   58.021278] [drm:intel_update_watermarks], plane B (pipe 0) clock: 31500
>[   58.021287] [drm:intel_update_watermarks], plane A (pipe 1) clock: 65000
>[   58.021292] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[   58.021296] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[   58.021300] [drm:intel_calculate_wm], FIFO entries required for mode: 20
>[   58.021303] [drm:intel_calculate_wm], FIFO watermark level: 6
>[   58.021306] [drm:intel_calculate_wm], FIFO entries required for mode: 9
>[   58.021310] [drm:intel_calculate_wm], FIFO watermark level: 20
>[   58.021313] [drm:i9xx_update_wm], FIFO watermarks - A: 6, B: 20
>[   58.021317] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 6, B: 20, C: 2, SR 1
>[   58.044460] [drm:intel_crtc_mode_set], Mode for pipe A:
>[   58.044466] [drm:drm_mode_debug_printmodeline], Modeline 0:"640x480" 0 31500 640 664 704 832 480 489 491 520 0x10 0xa
>[   58.068026] [drm:intel_pipe_set_base], No FB bound
>[   58.068032] [drm:intel_update_watermarks], plane B (pipe 0) clock: 31500
>[   58.068036] [drm:intel_update_watermarks], plane A (pipe 1) clock: 65000
>[   58.068041] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[   58.068045] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[   58.068049] [drm:intel_calculate_wm], FIFO entries required for mode: 20
>[   58.068052] [drm:intel_calculate_wm], FIFO watermark level: 6
>[   58.068055] [drm:intel_calculate_wm], FIFO entries required for mode: 9
>[   58.068059] [drm:intel_calculate_wm], FIFO watermark level: 20
>[   58.068062] [drm:i9xx_update_wm], FIFO watermarks - A: 6, B: 20
>[   58.068065] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 6, B: 20, C: 2, SR 1
>[   58.068072] [drm:intel_update_watermarks], plane B (pipe 0) clock: 31500
>[   58.068075] [drm:intel_update_watermarks], plane A (pipe 1) clock: 65000
>[   58.068079] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[   58.068083] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[   58.068086] [drm:intel_calculate_wm], FIFO entries required for mode: 20
>[   58.068090] [drm:intel_calculate_wm], FIFO watermark level: 6
>[   58.068093] [drm:intel_calculate_wm], FIFO entries required for mode: 9
>[   58.068096] [drm:intel_calculate_wm], FIFO watermark level: 20
>[   58.068099] [drm:i9xx_update_wm], FIFO watermarks - A: 6, B: 20
>[   58.068103] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 6, B: 20, C: 2, SR 1
>[   58.116029] [drm:intel_update_watermarks], plane A (pipe 1) clock: 65000
>[   58.116034] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[   58.116038] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[   58.116042] [drm:intel_calculate_wm], FIFO entries required for mode: 20
>[   58.116046] [drm:intel_calculate_wm], FIFO watermark level: 6
>[   58.116049] [drm:intel_calculate_wm], FIFO entries required for mode: 0
>[   58.116052] [drm:intel_calculate_wm], FIFO watermark level: 29
>[   58.116055] [drm:i9xx_update_wm], FIFO watermarks - A: 6, B: 29
>[   58.116059] [drm:i9xx_update_wm], self-refresh entries: 25
>[   58.116062] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 6, B: 29, C: 2, SR 70
>[   68.164467] [drm:intel_update_watermarks], plane B (pipe 0) clock: 31500
>[   68.164476] [drm:intel_update_watermarks], plane A (pipe 1) clock: 65000
>[   68.164481] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[   68.164485] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[   68.164489] [drm:intel_calculate_wm], FIFO entries required for mode: 20
>[   68.164492] [drm:intel_calculate_wm], FIFO watermark level: 6
>[   68.164495] [drm:intel_calculate_wm], FIFO entries required for mode: 9
>[   68.164499] [drm:intel_calculate_wm], FIFO watermark level: 20
>[   68.164502] [drm:i9xx_update_wm], FIFO watermarks - A: 6, B: 20
>[   68.164506] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 6, B: 20, C: 2, SR 1
>[   68.188467] [drm:intel_crtc_mode_set], Mode for pipe A:
>[   68.188474] [drm:drm_mode_debug_printmodeline], Modeline 0:"640x480" 0 31500 640 664 704 832 480 489 491 520 0x10 0xa
>[   68.212045] [drm:intel_pipe_set_base], No FB bound
>[   68.212051] [drm:intel_update_watermarks], plane B (pipe 0) clock: 31500
>[   68.212055] [drm:intel_update_watermarks], plane A (pipe 1) clock: 65000
>[   68.212060] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[   68.212064] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[   68.212068] [drm:intel_calculate_wm], FIFO entries required for mode: 20
>[   68.212071] [drm:intel_calculate_wm], FIFO watermark level: 6
>[   68.212074] [drm:intel_calculate_wm], FIFO entries required for mode: 9
>[   68.212078] [drm:intel_calculate_wm], FIFO watermark level: 20
>[   68.212081] [drm:i9xx_update_wm], FIFO watermarks - A: 6, B: 20
>[   68.212084] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 6, B: 20, C: 2, SR 1
>[   68.212091] [drm:intel_update_watermarks], plane B (pipe 0) clock: 31500
>[   68.212094] [drm:intel_update_watermarks], plane A (pipe 1) clock: 65000
>[   68.212098] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[   68.212102] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[   68.212105] [drm:intel_calculate_wm], FIFO entries required for mode: 20
>[   68.212109] [drm:intel_calculate_wm], FIFO watermark level: 6
>[   68.212112] [drm:intel_calculate_wm], FIFO entries required for mode: 9
>[   68.212115] [drm:intel_calculate_wm], FIFO watermark level: 20
>[   68.212118] [drm:i9xx_update_wm], FIFO watermarks - A: 6, B: 20
>[   68.212122] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 6, B: 20, C: 2, SR 1
>[   68.260046] [drm:intel_update_watermarks], plane A (pipe 1) clock: 65000
>[   68.260053] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[   68.260057] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[   68.260061] [drm:intel_calculate_wm], FIFO entries required for mode: 20
>[   68.260064] [drm:intel_calculate_wm], FIFO watermark level: 6
>[   68.260067] [drm:intel_calculate_wm], FIFO entries required for mode: 0
>[   68.260071] [drm:intel_calculate_wm], FIFO watermark level: 29
>[   68.260074] [drm:i9xx_update_wm], FIFO watermarks - A: 6, B: 29
>[   68.260078] [drm:i9xx_update_wm], self-refresh entries: 25
>[   68.260081] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 6, B: 29, C: 2, SR 70
>[   73.813705] [drm:intel_crtc_cursor_set], 
>[   73.813713] [drm:intel_crtc_cursor_set], cursor off
>[   73.829625] [drm:intel_crtc_cursor_set], 
>[   76.807845] [drm:intel_crtc_cursor_set], 
>[   76.807852] [drm:intel_crtc_cursor_set], cursor off
>[   78.308495] [drm:intel_update_watermarks], plane B (pipe 0) clock: 31500
>[   78.308504] [drm:intel_update_watermarks], plane A (pipe 1) clock: 65000
>[   78.308509] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[   78.308513] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[   78.308517] [drm:intel_calculate_wm], FIFO entries required for mode: 20
>[   78.308520] [drm:intel_calculate_wm], FIFO watermark level: 6
>[   78.308524] [drm:intel_calculate_wm], FIFO entries required for mode: 9
>[   78.308527] [drm:intel_calculate_wm], FIFO watermark level: 20
>[   78.308530] [drm:i9xx_update_wm], FIFO watermarks - A: 6, B: 20
>[   78.308534] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 6, B: 20, C: 2, SR 1
>[   78.332464] [drm:intel_crtc_mode_set], Mode for pipe A:
>[   78.332468] [drm:drm_mode_debug_printmodeline], Modeline 0:"640x480" 0 31500 640 664 704 832 480 489 491 520 0x10 0xa
>[   78.356070] [drm:intel_pipe_set_base], No FB bound
>[   78.356074] [drm:intel_update_watermarks], plane B (pipe 0) clock: 31500
>[   78.356078] [drm:intel_update_watermarks], plane A (pipe 1) clock: 65000
>[   78.356082] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[   78.356086] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[   78.356090] [drm:intel_calculate_wm], FIFO entries required for mode: 20
>[   78.356093] [drm:intel_calculate_wm], FIFO watermark level: 6
>[   78.356096] [drm:intel_calculate_wm], FIFO entries required for mode: 9
>[   78.356100] [drm:intel_calculate_wm], FIFO watermark level: 20
>[   78.356103] [drm:i9xx_update_wm], FIFO watermarks - A: 6, B: 20
>[   78.356106] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 6, B: 20, C: 2, SR 1
>[   78.356112] [drm:intel_update_watermarks], plane B (pipe 0) clock: 31500
>[   78.356116] [drm:intel_update_watermarks], plane A (pipe 1) clock: 65000
>[   78.356119] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[   78.356123] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[   78.356127] [drm:intel_calculate_wm], FIFO entries required for mode: 20
>[   78.356130] [drm:intel_calculate_wm], FIFO watermark level: 6
>[   78.356133] [drm:intel_calculate_wm], FIFO entries required for mode: 9
>[   78.356137] [drm:intel_calculate_wm], FIFO watermark level: 20
>[   78.356140] [drm:i9xx_update_wm], FIFO watermarks - A: 6, B: 20
>[   78.356143] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 6, B: 20, C: 2, SR 1
>[   78.404066] [drm:intel_update_watermarks], plane A (pipe 1) clock: 65000
>[   78.404072] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[   78.404077] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[   78.404080] [drm:intel_calculate_wm], FIFO entries required for mode: 20
>[   78.404084] [drm:intel_calculate_wm], FIFO watermark level: 6
>[   78.404087] [drm:intel_calculate_wm], FIFO entries required for mode: 0
>[   78.404091] [drm:intel_calculate_wm], FIFO watermark level: 29
>[   78.404094] [drm:i9xx_update_wm], FIFO watermarks - A: 6, B: 29
>[   78.404097] [drm:i9xx_update_wm], self-refresh entries: 25
>[   78.404101] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 6, B: 29, C: 2, SR 70
>[   81.539831] [drm:intel_crtc_cursor_set], 
>[   88.452507] [drm:intel_update_watermarks], plane B (pipe 0) clock: 31500
>[   88.452515] [drm:intel_update_watermarks], plane A (pipe 1) clock: 65000
>[   88.452519] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[   88.452523] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[   88.452527] [drm:intel_calculate_wm], FIFO entries required for mode: 20
>[   88.452531] [drm:intel_calculate_wm], FIFO watermark level: 6
>[   88.452534] [drm:intel_calculate_wm], FIFO entries required for mode: 9
>[   88.452537] [drm:intel_calculate_wm], FIFO watermark level: 20
>[   88.452541] [drm:i9xx_update_wm], FIFO watermarks - A: 6, B: 20
>[   88.452544] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 6, B: 20, C: 2, SR 1
>[   88.476511] [drm:intel_crtc_mode_set], Mode for pipe A:
>[   88.476516] [drm:drm_mode_debug_printmodeline], Modeline 0:"640x480" 0 31500 640 664 704 832 480 489 491 520 0x10 0xa
>[   88.500074] [drm:intel_pipe_set_base], No FB bound
>[   88.500077] [drm:intel_update_watermarks], plane B (pipe 0) clock: 31500
>[   88.500081] [drm:intel_update_watermarks], plane A (pipe 1) clock: 65000
>[   88.500085] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[   88.500089] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[   88.500093] [drm:intel_calculate_wm], FIFO entries required for mode: 20
>[   88.500096] [drm:intel_calculate_wm], FIFO watermark level: 6
>[   88.500099] [drm:intel_calculate_wm], FIFO entries required for mode: 9
>[   88.500103] [drm:intel_calculate_wm], FIFO watermark level: 20
>[   88.500106] [drm:i9xx_update_wm], FIFO watermarks - A: 6, B: 20
>[   88.500109] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 6, B: 20, C: 2, SR 1
>[   88.500115] [drm:intel_update_watermarks], plane B (pipe 0) clock: 31500
>[   88.500119] [drm:intel_update_watermarks], plane A (pipe 1) clock: 65000
>[   88.500122] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[   88.500126] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[   88.500130] [drm:intel_calculate_wm], FIFO entries required for mode: 20
>[   88.500133] [drm:intel_calculate_wm], FIFO watermark level: 6
>[   88.500136] [drm:intel_calculate_wm], FIFO entries required for mode: 9
>[   88.500139] [drm:intel_calculate_wm], FIFO watermark level: 20
>[   88.500143] [drm:i9xx_update_wm], FIFO watermarks - A: 6, B: 20
>[   88.500146] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 6, B: 20, C: 2, SR 1
>[   88.548075] [drm:intel_update_watermarks], plane A (pipe 1) clock: 65000
>[   88.548080] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[   88.548084] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[   88.548087] [drm:intel_calculate_wm], FIFO entries required for mode: 20
>[   88.548091] [drm:intel_calculate_wm], FIFO watermark level: 6
>[   88.548094] [drm:intel_calculate_wm], FIFO entries required for mode: 0
>[   88.548097] [drm:intel_calculate_wm], FIFO watermark level: 29
>[   88.548100] [drm:i9xx_update_wm], FIFO watermarks - A: 6, B: 29
>[   88.548104] [drm:i9xx_update_wm], self-refresh entries: 25
>[   88.548107] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 6, B: 29, C: 2, SR 70
>[   95.166109] [drm:intel_crtc_cursor_set], 
>[   95.166118] [drm:intel_crtc_cursor_set], cursor off
>[   95.179619] [drm:intel_crtc_cursor_set], 
>[   98.596454] [drm:intel_update_watermarks], plane B (pipe 0) clock: 31500
>[   98.596463] [drm:intel_update_watermarks], plane A (pipe 1) clock: 65000
>[   98.596467] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[   98.596472] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[   98.596475] [drm:intel_calculate_wm], FIFO entries required for mode: 20
>[   98.596479] [drm:intel_calculate_wm], FIFO watermark level: 6
>[   98.596482] [drm:intel_calculate_wm], FIFO entries required for mode: 9
>[   98.596485] [drm:intel_calculate_wm], FIFO watermark level: 20
>[   98.596489] [drm:i9xx_update_wm], FIFO watermarks - A: 6, B: 20
>[   98.596492] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 6, B: 20, C: 2, SR 1
>[   98.624508] [drm:intel_crtc_mode_set], Mode for pipe A:
>[   98.624514] [drm:drm_mode_debug_printmodeline], Modeline 0:"640x480" 0 31500 640 664 704 832 480 489 491 520 0x10 0xa
>[   98.648062] [drm:intel_pipe_set_base], No FB bound
>[   98.648065] [drm:intel_update_watermarks], plane B (pipe 0) clock: 31500
>[   98.648069] [drm:intel_update_watermarks], plane A (pipe 1) clock: 65000
>[   98.648073] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[   98.648077] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[   98.648081] [drm:intel_calculate_wm], FIFO entries required for mode: 20
>[   98.648084] [drm:intel_calculate_wm], FIFO watermark level: 6
>[   98.648088] [drm:intel_calculate_wm], FIFO entries required for mode: 9
>[   98.648091] [drm:intel_calculate_wm], FIFO watermark level: 20
>[   98.648094] [drm:i9xx_update_wm], FIFO watermarks - A: 6, B: 20
>[   98.648098] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 6, B: 20, C: 2, SR 1
>[   98.648104] [drm:intel_update_watermarks], plane B (pipe 0) clock: 31500
>[   98.648107] [drm:intel_update_watermarks], plane A (pipe 1) clock: 65000
>[   98.648111] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[   98.648115] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[   98.648118] [drm:intel_calculate_wm], FIFO entries required for mode: 20
>[   98.648122] [drm:intel_calculate_wm], FIFO watermark level: 6
>[   98.648125] [drm:intel_calculate_wm], FIFO entries required for mode: 9
>[   98.648128] [drm:intel_calculate_wm], FIFO watermark level: 20
>[   98.648131] [drm:i9xx_update_wm], FIFO watermarks - A: 6, B: 20
>[   98.648135] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 6, B: 20, C: 2, SR 1
>[   98.700067] [drm:intel_update_watermarks], plane A (pipe 1) clock: 65000
>[   98.700072] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[   98.700076] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[   98.700080] [drm:intel_calculate_wm], FIFO entries required for mode: 20
>[   98.700083] [drm:intel_calculate_wm], FIFO watermark level: 6
>[   98.700086] [drm:intel_calculate_wm], FIFO entries required for mode: 0
>[   98.700089] [drm:intel_calculate_wm], FIFO watermark level: 29
>[   98.700093] [drm:i9xx_update_wm], FIFO watermarks - A: 6, B: 29
>[   98.700096] [drm:i9xx_update_wm], self-refresh entries: 25
>[   98.700100] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 6, B: 29, C: 2, SR 70
>[  102.005758] [drm:intel_crtc_cursor_set], 
>[  102.005770] [drm:intel_crtc_cursor_set], cursor off
>[  102.010474] [drm:intel_crtc_cursor_set], 
>[  102.752919] [drm:intel_crtc_cursor_set], 
>[  102.752930] [drm:intel_crtc_cursor_set], cursor off

Actions: View

Attachments on bug 25284: 37349

Use of freedesktop.org services, including Bugzilla, is subject to our Code of Conduct. How we collect and use information is described in our Privacy Policy.