Attachment 37381 Details for Bug 26744 – dmesg (normal suspend to memory and resume), 2.6.36-rc6 with drm.debug=0x4

dmesg (normal suspend to memory and resume), 2.6.36-rc6 with drm.debug=0x4

dmesg_20100725_2.6.35-rc6_drm.debug=0x4 (text/plain), 198.14 KB, created by Tobias Diedrich on 2010-07-25 14:50:29 UTC

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Creator: Tobias Diedrich

Created: 2010-07-25 14:50:29 UTC

Size: 198.14 KB

patch

obsolete

>[    0.000000] Linux version 2.6.35-rc6 (ranma@navi) (gcc version 4.3.4 (Debian 4.3.4-6) ) #39 PREEMPT Sun Jul 25 23:26:35 CEST 2010
>[    0.000000] BIOS-provided physical RAM map:
>[    0.000000]  BIOS-e820: 0000000000000000 - 000000000009f000 (usable)
>[    0.000000]  BIOS-e820: 000000000009f000 - 00000000000a0000 (reserved)
>[    0.000000]  BIOS-e820: 00000000000dc000 - 0000000000100000 (reserved)
>[    0.000000]  BIOS-e820: 0000000000100000 - 000000005f6e0000 (usable)
>[    0.000000]  BIOS-e820: 000000005f6e0000 - 000000005f6f5000 (ACPI data)
>[    0.000000]  BIOS-e820: 000000005f6f5000 - 000000005f700000 (ACPI NVS)
>[    0.000000]  BIOS-e820: 000000005f700000 - 0000000060000000 (reserved)
>[    0.000000]  BIOS-e820: 00000000e0000000 - 00000000f0000000 (reserved)
>[    0.000000]  BIOS-e820: 00000000f0008000 - 00000000f000c000 (reserved)
>[    0.000000]  BIOS-e820: 00000000fec00000 - 00000000fec10000 (reserved)
>[    0.000000]  BIOS-e820: 00000000fed14000 - 00000000fed1a000 (reserved)
>[    0.000000]  BIOS-e820: 00000000fed20000 - 00000000fed90000 (reserved)
>[    0.000000]  BIOS-e820: 00000000fee00000 - 00000000fee01000 (reserved)
>[    0.000000]  BIOS-e820: 00000000ff000000 - 0000000100000000 (reserved)
>[    0.000000] Notice: NX (Execute Disable) protection cannot be enabled: non-PAE kernel!
>[    0.000000] DMI present.
>[    0.000000] e820 update range: 0000000000000000 - 0000000000001000 (usable) ==> (reserved)
>[    0.000000] e820 remove range: 00000000000a0000 - 0000000000100000 (usable)
>[    0.000000] last_pfn = 0x5f6e0 max_arch_pfn = 0x100000
>[    0.000000] MTRR default type: uncachable
>[    0.000000] MTRR fixed ranges enabled:
>[    0.000000]   00000-9FFFF write-back
>[    0.000000]   A0000-BFFFF uncachable
>[    0.000000]   C0000-CFFFF write-protect
>[    0.000000]   D0000-DBFFF uncachable
>[    0.000000]   DC000-DFFFF write-back
>[    0.000000]   E0000-FFFFF write-protect
>[    0.000000] MTRR variable ranges enabled:
>[    0.000000]   0 base 000000000 mask FC0000000 write-back
>[    0.000000]   1 base 040000000 mask FE0000000 write-back
>[    0.000000]   2 base 05F700000 mask FFFF00000 uncachable
>[    0.000000]   3 base 05F800000 mask FFF800000 uncachable
>[    0.000000]   4 disabled
>[    0.000000]   5 disabled
>[    0.000000]   6 disabled
>[    0.000000]   7 disabled
>[    0.000000] PAT not supported by CPU.
>[    0.000000] initial memory mapped : 0 - 01c00000
>[    0.000000] init_memory_mapping: 0000000000000000-00000000377fe000
>[    0.000000]  0000000000 - 0000400000 page 4k
>[    0.000000]  0000400000 - 0037400000 page 2M
>[    0.000000]  0037400000 - 00377fe000 page 4k
>[    0.000000] kernel direct mapping tables up to 377fe000 @ 7000-c000
>[    0.000000] ACPI: RSDP 000f6c80 00024 (v02 IBM   )
>[    0.000000] ACPI: XSDT 5f6e5c43 0005C (v01 IBM    TP-75    00002060  LTP 00000000)
>[    0.000000] ACPI: FACP 5f6e5d00 000F4 (v03 IBM    TP-75    00002060 IBM  00000001)
>[    0.000000] ACPI Warning: 32/64X length mismatch in Gpe1Block: 0/32 (20100428/tbfadt-526)
>[    0.000000] ACPI Warning: Optional field Gpe1Block has zero address or length: 0x000000000000102C/0x0 (20100428/tbfadt-557)
>[    0.000000] ACPI: DSDT 5f6e5ee7 0EEB9 (v01 IBM    TP-75    00002060 MSFT 0100000E)
>[    0.000000] ACPI: FACS 5f6f6000 00040
>[    0.000000] ACPI: SSDT 5f6e5eb4 00033 (v01 IBM    TP-75    00002060 MSFT 0100000E)
>[    0.000000] ACPI: ECDT 5f6f4da0 00052 (v01 IBM    TP-75    00002060 IBM  00000001)
>[    0.000000] ACPI: TCPA 5f6f4df2 00032 (v01 IBM    TP-75    00002060 PTL  00000001)
>[    0.000000] ACPI: APIC 5f6f4e24 0005A (v01 IBM    TP-75    00002060 IBM  00000001)
>[    0.000000] ACPI: MCFG 5f6f4e7e 0003C (v01 IBM    TP-75    00002060 IBM  00000001)
>[    0.000000] ACPI: BOOT 5f6f4fd8 00028 (v01 IBM    TP-75    00002060  LTP 00000001)
>[    0.000000] ACPI: Local APIC address 0xfee00000
>[    0.000000] 638MB HIGHMEM available.
>[    0.000000] 887MB LOWMEM available.
>[    0.000000]   mapped low ram: 0 - 377fe000
>[    0.000000]   low ram: 0 - 377fe000
>[    0.000000] Zone PFN ranges:
>[    0.000000]   DMA      0x00000001 -> 0x00001000
>[    0.000000]   Normal   0x00001000 -> 0x000377fe
>[    0.000000]   HighMem  0x000377fe -> 0x0005f6e0
>[    0.000000] Movable zone start PFN for each node
>[    0.000000] early_node_map[2] active PFN ranges
>[    0.000000]     0: 0x00000001 -> 0x0000009f
>[    0.000000]     0: 0x00000100 -> 0x0005f6e0
>[    0.000000] On node 0 totalpages: 390782
>[    0.000000] free_area_init_node: node 0, pgdat c18080d8, node_mem_map c1988020
>[    0.000000]   DMA zone: 32 pages used for memmap
>[    0.000000]   DMA zone: 0 pages reserved
>[    0.000000]   DMA zone: 3966 pages, LIFO batch:0
>[    0.000000]   Normal zone: 1744 pages used for memmap
>[    0.000000]   Normal zone: 221486 pages, LIFO batch:31
>[    0.000000]   HighMem zone: 1278 pages used for memmap
>[    0.000000]   HighMem zone: 162276 pages, LIFO batch:31
>[    0.000000] Using APIC driver default
>[    0.000000] ACPI: PM-Timer IO Port: 0x1008
>[    0.000000] ACPI: Local APIC address 0xfee00000
>[    0.000000] ACPI: LAPIC (acpi_id[0x01] lapic_id[0x00] enabled)
>[    0.000000] ACPI: LAPIC_NMI (acpi_id[0x01] high edge lint[0x1])
>[    0.000000] ACPI: IOAPIC (id[0x01] address[0xfec00000] gsi_base[0])
>[    0.000000] IOAPIC[0]: apic_id 1, version 32, address 0xfec00000, GSI 0-23
>[    0.000000] ACPI: INT_SRC_OVR (bus 0 bus_irq 0 global_irq 2 dfl dfl)
>[    0.000000] ACPI: INT_SRC_OVR (bus 0 bus_irq 9 global_irq 9 high level)
>[    0.000000] ACPI: IRQ0 used by override.
>[    0.000000] ACPI: IRQ2 used by override.
>[    0.000000] ACPI: IRQ9 used by override.
>[    0.000000] Using ACPI (MADT) for SMP configuration information
>[    0.000000] nr_irqs_gsi: 40
>[    0.000000] early_res array is doubled to 64 at [5000 - 57ff]
>[    0.000000] PM: Registered nosave memory: 000000000009f000 - 00000000000a0000
>[    0.000000] PM: Registered nosave memory: 00000000000a0000 - 00000000000dc000
>[    0.000000] PM: Registered nosave memory: 00000000000dc000 - 0000000000100000
>[    0.000000] Allocating PCI resources starting at 60000000 (gap: 60000000:80000000)
>[    0.000000] Built 1 zonelists in Zone order, mobility grouping on.  Total pages: 387728
>[    0.000000] Kernel command line: BOOT_IMAGE=/vmlinuz root=/dev/sda5 ro quirks.ich_force_ahci=0 resume=/dev/sda7 notsc i915.modeset=1 no_console_suspend usb_storage.delay_use=0 drm.debug=0x4
>[    0.000000] notsc: Kernel compiled with CONFIG_X86_TSC, cannot disable TSC completely.
>[    0.000000] PID hash table entries: 4096 (order: 2, 16384 bytes)
>[    0.000000] Dentry cache hash table entries: 131072 (order: 7, 524288 bytes)
>[    0.000000] Inode-cache hash table entries: 65536 (order: 6, 262144 bytes)
>[    0.000000] Enabling fast FPU save and restore... done.
>[    0.000000] Enabling unmasked SIMD FPU exception support... done.
>[    0.000000] Initializing CPU#0
>[    0.000000] Subtract (36 early reservations)
>[    0.000000]   #1 [0001000000 - 000197e8d0]   TEXT DATA BSS
>[    0.000000]   #2 [000009f000 - 0000100000]   BIOS reserved
>[    0.000000]   #3 [000197f000 - 000198612c]             BRK
>[    0.000000]   #4 [0000001000 - 0000005000]     ACPI WAKEUP
>[    0.000000]   #5 [0000007000 - 0000008000]         PGTABLE
>[    0.000000]   #6 [0001987000 - 0001988000]         BOOTMEM
>[    0.000000]   #7 [0001988000 - 0002578000]         BOOTMEM
>[    0.000000]   #8 [000197e900 - 000197e904]         BOOTMEM
>[    0.000000]   #9 [000197e940 - 000197e9c0]         BOOTMEM
>[    0.000000]   #10 [000197e9c0 - 000197ea14]         BOOTMEM
>[    0.000000]   #11 [0002578000 - 000257a000]         BOOTMEM
>[    0.000000]   #12 [000197ea40 - 000197ea7c]         BOOTMEM
>[    0.000000]   #13 [000257a000 - 000257c000]         BOOTMEM
>[    0.000000]   #14 [000197ea80 - 000197eaa7]         BOOTMEM
>[    0.000000]   #15 [000197eac0 - 000197ec64]         BOOTMEM
>[    0.000000]   #16 [000197ec80 - 000197ecc0]         BOOTMEM
>[    0.000000]   #17 [000197ecc0 - 000197ed00]         BOOTMEM
>[    0.000000]   #18 [000197ed00 - 000197ed40]         BOOTMEM
>[    0.000000]   #19 [000197ed40 - 000197ed80]         BOOTMEM
>[    0.000000]   #20 [000197ed80 - 000197edc0]         BOOTMEM
>[    0.000000]   #21 [000197edc0 - 000197ee00]         BOOTMEM
>[    0.000000]   #22 [000197ee00 - 000197ee40]         BOOTMEM
>[    0.000000]   #23 [000197ee40 - 000197ee80]         BOOTMEM
>[    0.000000]   #24 [000197ee80 - 000197eec0]         BOOTMEM
>[    0.000000]   #25 [000197eec0 - 000197ef00]         BOOTMEM
>[    0.000000]   #26 [000197ef00 - 000197ef40]         BOOTMEM
>[    0.000000]   #27 [000197ef40 - 000197ef80]         BOOTMEM
>[    0.000000]   #28 [000197ef80 - 000197efc0]         BOOTMEM
>[    0.000000]   #29 [000197efc0 - 000197f000]         BOOTMEM
>[    0.000000]   #30 [0001986140 - 0001986150]         BOOTMEM
>[    0.000000]   #31 [0001986180 - 000198621d]         BOOTMEM
>[    0.000000]   #32 [0001986240 - 00019862dd]         BOOTMEM
>[    0.000000]   #33 [000257c000 - 0002580000]         BOOTMEM
>[    0.000000]   #34 [0002580000 - 0002600000]         BOOTMEM
>[    0.000000]   #35 [0002600000 - 0002640000]         BOOTMEM
>[    0.000000] Initializing HighMem for node 0 (000377fe:0005f6e0)
>[    0.000000] Memory: 1540324k/1563520k available (5661k kernel code, 22804k reserved, 2663k data, 472k init, 654216k highmem)
>[    0.000000] virtual kernel memory layout:
>[    0.000000]     fixmap  : 0xfffa3000 - 0xfffff000   ( 368 kB)
>[    0.000000]     pkmap   : 0xff800000 - 0xffc00000   (4096 kB)
>[    0.000000]     vmalloc : 0xf7ffe000 - 0xff7fe000   ( 120 MB)
>[    0.000000]     lowmem  : 0xc0000000 - 0xf77fe000   ( 887 MB)
>[    0.000000]       .init : 0xc1822000 - 0xc1898000   ( 472 kB)
>[    0.000000]       .data : 0xc1587526 - 0xc182150c   (2663 kB)
>[    0.000000]       .text : 0xc1000000 - 0xc1587526   (5661 kB)
>[    0.000000] Checking if this processor honours the WP bit even in supervisor mode...Ok.
>[    0.000000] Hierarchical RCU implementation.
>[    0.000000] 	RCU-based detection of stalled CPUs is disabled.
>[    0.000000] 	Verbose stalled-CPUs detection is disabled.
>[    0.000000] NR_IRQS:288
>[    0.000000] CPU 0 irqstacks, hard=c17b8000 soft=c17b9000
>[    0.000000] Extended CMOS year: 2000
>[    0.000000] Console: colour VGA+ 80x25
>[    0.000000] console [tty0] enabled
>[    0.000000] Fast TSC calibration using PIT
>[    0.000000] Detected 1496.264 MHz processor.
>[    0.012000] Calibrating delay loop... 2981.88 BogoMIPS (lpj=5963776)
>[    0.104000] pid_max: default: 32768 minimum: 301
>[    0.104000] Mount-cache hash table entries: 512
>[    0.104000] Initializing cgroup subsys debug
>[    0.104000] Initializing cgroup subsys ns
>[    0.104000] mce: CPU supports 5 MCE banks
>[    0.104000] CPU0: Thermal monitoring enabled (TM2)
>[    0.104000] Performance Events: p6 PMU driver.
>[    0.104000] ... version:                0
>[    0.104000] ... bit width:              32
>[    0.104000] ... generic registers:      2
>[    0.104000] ... value mask:             00000000ffffffff
>[    0.104000] ... max period:             000000007fffffff
>[    0.104000] ... fixed-purpose events:   0
>[    0.104000] ... event mask:             0000000000000003
>[    0.104000] CPU: Intel(R) Pentium(R) M processor 1.50GHz stepping 08
>[    0.104000] ACPI: Core revision 20100428
>[    0.132000] ftrace: converting mcount calls to 0f 1f 44 00 00
>[    0.132000] ftrace: allocating 24294 entries in 48 pages
>[    0.136000] Enabling APIC mode:  Flat.  Using 1 I/O APICs
>[    0.136000] ..TIMER: vector=0x30 apic1=0 pin1=2 apic2=-1 pin2=-1
>[    0.176000] devtmpfs: initialized
>[    0.176000] NET: Registered protocol family 16
>[    0.176000] ACPI: bus type pci registered
>[    0.176000] PCI: MMCONFIG for domain 0000 [bus 00-ff] at [mem 0xe0000000-0xefffffff] (base 0xe0000000)
>[    0.176000] PCI: MMCONFIG at [mem 0xe0000000-0xefffffff] reserved in E820
>[    0.176000] PCI: Using MMCONFIG for extended config space
>[    0.176000] PCI: Using configuration type 1 for base access
>[    0.184000] bio: create slab <bio-0> at 0
>[    0.188000] ACPI: EC: EC description table is found, configuring boot EC
>[    0.332000] ACPI: Interpreter enabled
>[    0.332000] ACPI: (supports S0 S3 S4 S5)
>[    0.332000] ACPI: Using IOAPIC for interrupt routing
>[    0.344000] ACPI: EC: GPE = 0x1c, I/O: command/status = 0x66, data = 0x62
>[    0.344000] ACPI: Power Resource [PUBS] (on)
>[    0.348000] ACPI: ACPI Dock Station Driver: 3 docks/bays found
>[    0.348000] PCI: Ignoring host bridge windows from ACPI; if necessary, use "pci=use_crs" and report a bug
>[    0.348000] ACPI: PCI Root Bridge [PCI0] (domain 0000 [bus 00-ff])
>[    0.348000] pci_root PNP0A08:00: host bridge window [io  0x0000-0x0cf7] (ignored)
>[    0.348000] pci_root PNP0A08:00: host bridge window [io  0x0d00-0xffff] (ignored)
>[    0.348000] pci_root PNP0A08:00: host bridge window [mem 0x000a0000-0x000bffff] (ignored)
>[    0.348000] pci_root PNP0A08:00: host bridge window [mem 0x000d0000-0x000d3fff] (ignored)
>[    0.348000] pci_root PNP0A08:00: host bridge window [mem 0x000d4000-0x000d7fff] (ignored)
>[    0.348000] pci_root PNP0A08:00: host bridge window [mem 0x000d8000-0x000dbfff] (ignored)
>[    0.348000] pci_root PNP0A08:00: host bridge window [mem 0x60000000-0xfebfffff] (ignored)
>[    0.348000] pci 0000:00:02.0: reg 10: [mem 0xa0080000-0xa00fffff]
>[    0.348000] pci 0000:00:02.0: reg 14: [io  0x1800-0x1807]
>[    0.348000] pci 0000:00:02.0: reg 18: [mem 0xc0000000-0xcfffffff pref]
>[    0.348000] pci 0000:00:02.0: reg 1c: [mem 0xa0000000-0xa003ffff]
>[    0.348000] pci 0000:00:02.1: reg 10: [mem 0x00000000-0x0007ffff]
>[    0.348000] pci 0000:00:1c.0: PME# supported from D0 D3hot D3cold
>[    0.348000] pci 0000:00:1c.0: PME# disabled
>[    0.348000] pci 0000:00:1d.0: reg 20: [io  0x1820-0x183f]
>[    0.348000] pci 0000:00:1d.1: reg 20: [io  0x1840-0x185f]
>[    0.348000] pci 0000:00:1d.2: reg 20: [io  0x1860-0x187f]
>[    0.348000] pci 0000:00:1d.3: reg 20: [io  0x1880-0x189f]
>[    0.348000] pci 0000:00:1d.7: reg 10: [mem 0xa0040000-0xa00403ff]
>[    0.348000] pci 0000:00:1d.7: PME# supported from D0 D3hot D3cold
>[    0.348000] pci 0000:00:1d.7: PME# disabled
>[    0.348000] pci 0000:00:1e.2: reg 10: [io  0x1c00-0x1cff]
>[    0.348000] pci 0000:00:1e.2: reg 14: [io  0x18c0-0x18ff]
>[    0.348000] pci 0000:00:1e.2: reg 18: [mem 0xa0040800-0xa00409ff]
>[    0.348000] pci 0000:00:1e.2: reg 1c: [mem 0xa0040400-0xa00404ff]
>[    0.348000] pci 0000:00:1e.2: PME# supported from D0 D3hot D3cold
>[    0.348000] pci 0000:00:1e.2: PME# disabled
>[    0.348000] pci 0000:00:1e.3: reg 10: [io  0x2400-0x24ff]
>[    0.348000] pci 0000:00:1e.3: reg 14: [io  0x2000-0x207f]
>[    0.348000] pci 0000:00:1e.3: PME# supported from D0 D3hot D3cold
>[    0.348000] pci 0000:00:1e.3: PME# disabled
>[    0.348000] pci 0000:00:1f.0: Force enabled HPET at 0xfed00000
>[    0.348000] pci 0000:00:1f.0: quirk: [io  0x1000-0x107f] claimed by ICH6 ACPI/GPIO/TCO
>[    0.352000] pci 0000:00:1f.0: quirk: [io  0x1180-0x11bf] claimed by ICH6 GPIO
>[    0.352000] pci 0000:00:1f.0: LPC Generic IO decode 1 PIO at 1600-167f
>[    0.352000] pci 0000:00:1f.0: LPC Generic IO decode 2 PIO at 15c0-15cf
>[    0.352000] pci 0000:00:1f.2: reg 10: [io  0x0000-0x0007]
>[    0.352000] pci 0000:00:1f.2: reg 14: [io  0x0000-0x0003]
>[    0.352000] pci 0000:00:1f.2: reg 18: [io  0x0000-0x0007]
>[    0.352000] pci 0000:00:1f.2: reg 1c: [io  0x0000-0x0003]
>[    0.352000] pci 0000:00:1f.2: reg 20: [io  0x1810-0x181f]
>[    0.352000] pci 0000:00:1f.2: PME# supported from D3hot
>[    0.352000] pci 0000:00:1f.2: PME# disabled
>[    0.352000] pci 0000:00:1f.3: reg 20: [io  0x18a0-0x18bf]
>[    0.352000] pci 0000:02:00.0: reg 10: [mem 0xa0100000-0xa010ffff 64bit]
>[    0.352000] pci 0000:02:00.0: PME# supported from D3hot D3cold
>[    0.352000] pci 0000:02:00.0: PME# disabled
>[    0.352000] pci 0000:02:00.0: disabling ASPM on pre-1.1 PCIe device.  You can enable it with 'pcie_aspm=force'
>[    0.352000] pci 0000:00:1c.0: PCI bridge to [bus 02-02]
>[    0.352000] pci 0000:00:1c.0:   bridge window [io  0xf000-0x0000] (disabled)
>[    0.352000] pci 0000:00:1c.0:   bridge window [mem 0xa0100000-0xa01fffff]
>[    0.352000] pci 0000:00:1c.0:   bridge window [mem 0xfff00000-0x000fffff pref] (disabled)
>[    0.352000] pci 0000:04:00.0: reg 10: [mem 0xa0200000-0xa0200fff]
>[    0.352000] pci 0000:04:00.0: supports D1 D2
>[    0.352000] pci 0000:04:00.0: PME# supported from D0 D1 D2 D3hot D3cold
>[    0.352000] pci 0000:04:00.0: PME# disabled
>[    0.352000] pci 0000:04:00.1: reg 10: [mem 0xa0201000-0xa02010ff]
>[    0.352000] pci 0000:04:00.1: supports D1 D2
>[    0.352000] pci 0000:04:00.1: PME# supported from D0 D1 D2 D3hot D3cold
>[    0.352000] pci 0000:04:00.1: PME# disabled
>[    0.352000] pci 0000:04:02.0: reg 10: [mem 0xa0202000-0xa0202fff]
>[    0.352000] pci 0000:04:02.0: PME# supported from D0 D3hot D3cold
>[    0.352000] pci 0000:04:02.0: PME# disabled
>[    0.352000] pci 0000:00:1e.0: PCI bridge to [bus 04-07] (subtractive decode)
>[    0.352000] pci 0000:00:1e.0:   bridge window [io  0x3000-0x6fff]
>[    0.352000] pci 0000:00:1e.0:   bridge window [mem 0xa0200000-0xafffffff]
>[    0.352000] pci 0000:00:1e.0:   bridge window [mem 0xd0000000-0xd7ffffff 64bit pref]
>[    0.352000] pci 0000:00:1e.0:   bridge window [io  0x0000-0xffff] (subtractive decode)
>[    0.352000] pci 0000:00:1e.0:   bridge window [mem 0x00000000-0xffffffff] (subtractive decode)
>[    0.352000] pci_bus 0000:00: on NUMA node 0
>[    0.352000] ACPI: PCI Interrupt Routing Table [\_SB_.PCI0._PRT]
>[    0.352000] ACPI: PCI Interrupt Routing Table [\_SB_.PCI0.EXP0._PRT]
>[    0.352000] ACPI: PCI Interrupt Routing Table [\_SB_.PCI0.PCI1._PRT]
>[    0.360000] ACPI: PCI Interrupt Link [LNKA] (IRQs 3 4 5 6 7 9 10 *11)
>[    0.360000] ACPI: PCI Interrupt Link [LNKB] (IRQs 3 4 5 6 7 9 10 *11)
>[    0.360000] ACPI: PCI Interrupt Link [LNKC] (IRQs 3 4 5 6 7 9 10 *11)
>[    0.360000] ACPI: PCI Interrupt Link [LNKD] (IRQs 3 4 5 6 7 9 10 *11)
>[    0.360000] ACPI: PCI Interrupt Link [LNKE] (IRQs 3 4 5 6 7 9 10 *11)
>[    0.360000] ACPI: PCI Interrupt Link [LNKF] (IRQs 3 4 5 6 7 9 10 *11)
>[    0.360000] ACPI: PCI Interrupt Link [LNKG] (IRQs 3 4 5 6 7 9 10 *11)
>[    0.364000] ACPI: PCI Interrupt Link [LNKH] (IRQs 3 4 5 6 7 9 10 *11)
>[    0.364000] vgaarb: device added: PCI:0000:00:02.0,decodes=io+mem,owns=io+mem,locks=none
>[    0.368000] vgaarb: loaded
>[    0.368000] SCSI subsystem initialized
>[    0.368000] libata version 3.00 loaded.
>[    0.368000] usbcore: registered new interface driver usbfs
>[    0.368000] usbcore: registered new interface driver hub
>[    0.368000] usbcore: registered new device driver usb
>[    0.368000] Advanced Linux Sound Architecture Driver Version 1.0.23.
>[    0.368000] PCI: Using ACPI for IRQ routing
>[    0.368000] PCI: pci_cache_line_size set to 64 bytes
>[    0.368000] reserve RAM buffer: 000000000009f000 - 000000000009ffff 
>[    0.368000] reserve RAM buffer: 000000005f6e0000 - 000000005fffffff 
>[    0.368000] Bluetooth: Core ver 2.15
>[    0.368000] NET: Registered protocol family 31
>[    0.368000] Bluetooth: HCI device and connection manager initialized
>[    0.368000] Bluetooth: HCI socket layer initialized
>[    0.368000] cfg80211: Calling CRDA to update world regulatory domain
>[    0.368000] hpet clockevent registered
>[    0.368000] HPET: 3 timers in total, 0 timers will be used for per-cpu timer
>[    0.368000] hpet0: at MMIO 0xfed00000, IRQs 2, 8, 0
>[    0.368000] hpet0: 3 comparators, 64-bit 14.318180 MHz counter
>[    0.376000] Switching to clocksource hpet
>[    0.388010] pnp: PnP ACPI init
>[    0.388010] ACPI: bus type pnp registered
>[    0.396011] pnp: PnP ACPI: found 12 devices
>[    0.396011] ACPI: ACPI bus type pnp unregistered
>[    0.396011] system 00:00: [mem 0x00000000-0x0009ffff] could not be reserved
>[    0.396011] system 00:00: [mem 0x000c0000-0x000c3fff] could not be reserved
>[    0.396011] system 00:00: [mem 0x000c4000-0x000c7fff] could not be reserved
>[    0.396011] system 00:00: [mem 0x000c8000-0x000cbfff] has been reserved
>[    0.396011] system 00:00: [mem 0x000cc000-0x000cffff] has been reserved
>[    0.396011] system 00:00: [mem 0x000dc000-0x000dffff] could not be reserved
>[    0.396011] system 00:00: [mem 0x000e0000-0x000e3fff] could not be reserved
>[    0.396011] system 00:00: [mem 0x000e4000-0x000e7fff] could not be reserved
>[    0.396011] system 00:00: [mem 0x000e8000-0x000ebfff] could not be reserved
>[    0.396011] system 00:00: [mem 0x000ec000-0x000effff] could not be reserved
>[    0.396011] system 00:00: [mem 0x000f0000-0x000fffff] could not be reserved
>[    0.396011] system 00:00: [mem 0x00100000-0x5fffffff] could not be reserved
>[    0.396011] system 00:00: [mem 0xfec00000-0xffffffff] could not be reserved
>[    0.396011] system 00:02: [io  0x1000-0x107f] has been reserved
>[    0.396011] system 00:02: [io  0x1180-0x11bf] has been reserved
>[    0.396011] system 00:02: [io  0x15e0-0x15ef] has been reserved
>[    0.396011] system 00:02: [io  0x1600-0x162f] has been reserved
>[    0.396011] system 00:02: [io  0x1632-0x167f] has been reserved
>[    0.396011] system 00:02: [io  0x15c0-0x15df] has been reserved
>[    0.396011] system 00:02: [mem 0xe0000000-0xefffffff] has been reserved
>[    0.396011] system 00:02: [mem 0xf0008000-0xf000bfff] has been reserved
>[    0.396011] system 00:02: [mem 0xfed14000-0xfed17fff] has been reserved
>[    0.396011] system 00:02: [mem 0xfed18000-0xfed18fff] has been reserved
>[    0.400043] system 00:02: [mem 0xfed19000-0xfed19fff] has been reserved
>[    0.432004] pci 0000:00:1c.0: BAR 9: assigned [mem 0x60000000-0x601fffff 64bit pref]
>[    0.432004] pci 0000:00:02.1: BAR 0: assigned [mem 0x60200000-0x6027ffff]
>[    0.432004] pci 0000:00:02.1: BAR 0: set to [mem 0x60200000-0x6027ffff] (PCI address [0x60200000-0x6027ffff]
>[    0.432004] pci 0000:00:1c.0: BAR 7: assigned [io  0x7000-0x7fff]
>[    0.436119] pci 0000:00:1c.0: PCI bridge to [bus 02-02]
>[    0.436119] pci 0000:00:1c.0:   bridge window [io  0x7000-0x7fff]
>[    0.436119] pci 0000:00:1c.0:   bridge window [mem 0xa0100000-0xa01fffff]
>[    0.436119] pci 0000:00:1c.0:   bridge window [mem 0x60000000-0x601fffff 64bit pref]
>[    0.436119] pci 0000:04:00.0: BAR 9: assigned [mem 0xd0000000-0xd3ffffff pref]
>[    0.436119] pci 0000:04:00.0: BAR 10: assigned [mem 0xa4000000-0xa7ffffff]
>[    0.436119] pci 0000:04:00.0: BAR 7: assigned [io  0x3000-0x30ff]
>[    0.436119] pci 0000:04:00.0: BAR 8: assigned [io  0x3400-0x34ff]
>[    0.436119] pci 0000:04:00.0: CardBus bridge to [bus 05-06]
>[    0.436119] pci 0000:04:00.0:   bridge window [io  0x3000-0x30ff]
>[    0.436119] pci 0000:04:00.0:   bridge window [io  0x3400-0x34ff]
>[    0.436119] pci 0000:04:00.0:   bridge window [mem 0xd0000000-0xd3ffffff pref]
>[    0.436119] pci 0000:04:00.0:   bridge window [mem 0xa4000000-0xa7ffffff]
>[    0.436119] pci 0000:00:1e.0: PCI bridge to [bus 04-07]
>[    0.436119] pci 0000:00:1e.0:   bridge window [io  0x3000-0x6fff]
>[    0.436119] pci 0000:00:1e.0:   bridge window [mem 0xa0200000-0xafffffff]
>[    0.436119] pci 0000:00:1e.0:   bridge window [mem 0xd0000000-0xd7ffffff 64bit pref]
>[    0.436119] pci 0000:00:1c.0: PCI INT A -> GSI 20 (level, low) -> IRQ 20
>[    0.436119] pci 0000:00:1c.0: setting latency timer to 64
>[    0.436119] pci 0000:00:1e.0: setting latency timer to 64
>[    0.436119] pci 0000:04:00.0: PCI INT A -> GSI 16 (level, low) -> IRQ 16
>[    0.436119] pci_bus 0000:00: resource 0 [io  0x0000-0xffff]
>[    0.436119] pci_bus 0000:00: resource 1 [mem 0x00000000-0xffffffff]
>[    0.436119] pci_bus 0000:02: resource 0 [io  0x7000-0x7fff]
>[    0.436119] pci_bus 0000:02: resource 1 [mem 0xa0100000-0xa01fffff]
>[    0.436119] pci_bus 0000:02: resource 2 [mem 0x60000000-0x601fffff 64bit pref]
>[    0.436119] pci_bus 0000:04: resource 0 [io  0x3000-0x6fff]
>[    0.436119] pci_bus 0000:04: resource 1 [mem 0xa0200000-0xafffffff]
>[    0.436119] pci_bus 0000:04: resource 2 [mem 0xd0000000-0xd7ffffff 64bit pref]
>[    0.436119] pci_bus 0000:04: resource 4 [io  0x0000-0xffff]
>[    0.436119] pci_bus 0000:04: resource 5 [mem 0x00000000-0xffffffff]
>[    0.436119] pci_bus 0000:05: resource 0 [io  0x3000-0x30ff]
>[    0.436119] pci_bus 0000:05: resource 1 [io  0x3400-0x34ff]
>[    0.436119] pci_bus 0000:05: resource 2 [mem 0xd0000000-0xd3ffffff pref]
>[    0.436119] pci_bus 0000:05: resource 3 [mem 0xa4000000-0xa7ffffff]
>[    0.436119] NET: Registered protocol family 2
>[    0.436119] IP route cache hash table entries: 32768 (order: 5, 131072 bytes)
>[    0.436119] TCP established hash table entries: 131072 (order: 8, 1048576 bytes)
>[    0.440119] TCP bind hash table entries: 65536 (order: 6, 262144 bytes)
>[    0.440119] TCP: Hash tables configured (established 131072 bind 65536)
>[    0.440119] TCP reno registered
>[    0.440119] UDP hash table entries: 512 (order: 1, 8192 bytes)
>[    0.440119] UDP-Lite hash table entries: 512 (order: 1, 8192 bytes)
>[    0.440119] NET: Registered protocol family 1
>[    0.440119] RPC: Registered udp transport module.
>[    0.440119] RPC: Registered tcp transport module.
>[    0.440119] RPC: Registered tcp NFSv4.1 backchannel transport module.
>[    0.440119] pci 0000:00:02.0: Boot video device
>[    0.440119] PCI: CLS 32 bytes, default 64
>[    0.440119] Simple Boot Flag at 0x35 set to 0x1
>[    0.444013] highmem bounce pool size: 64 pages
>[    0.444013] squashfs: version 4.0 (2009/01/31) Phillip Lougher
>[    0.444013] Installing knfsd (copyright (C) 1996 okir@monad.swb.de).
>[    0.444013] Slow work thread pool: Starting up
>[    0.444013] Slow work thread pool: Ready
>[    0.444013] NTFS driver 2.1.29 [Flags: R/W].
>[    0.444013] JFFS2 version 2.2. (NAND) (SUMMARY)  Â© 2001-2006 Red Hat, Inc.
>[    0.444013] fuse init (API version 7.14)
>[    0.444013] Btrfs loaded
>[    0.444013] msgmni has been set to 1730
>[    0.448016] alg: No test for stdrng (krng)
>[    0.448016] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 254)
>[    0.448016] io scheduler noop registered
>[    0.448016] io scheduler deadline registered
>[    0.448016] io scheduler cfq registered (default)
>[    0.448016] pcieport 0000:00:1c.0: setting latency timer to 64
>[    0.448016] pcieport 0000:00:1c.0: irq 40 for MSI/MSI-X
>[    0.448016] pci_hotplug: PCI Hot Plug PCI Core version: 0.5
>[    0.448016] ibmphpd: IBM Hot Plug PCI Controller Driver version: 0.6
>[    0.448016] acpiphp: ACPI Hot Plug PCI Controller Driver version: 0.5
>[    0.453665] acpiphp_ibm: ibm_acpiphp_init: acpi_walk_namespace failed
>[    0.456361] ACPI: AC Adapter [AC] (on-line)
>[    0.456361] input: Lid Switch as /devices/LNXSYSTM:00/LNXSYBUS:00/PNP0C0D:00/input/input0
>[    0.457160] ACPI: Lid Switch [LID]
>[    0.457160] input: Sleep Button as /devices/LNXSYSTM:00/LNXSYBUS:00/PNP0C0E:00/input/input1
>[    0.457160] ACPI: Sleep Button [SLPB]
>[    0.457160] input: Power Button as /devices/LNXSYSTM:00/LNXPWRBN:00/input/input2
>[    0.457160] ACPI: Power Button [PWRF]
>[    0.457160] input: Video Bus as /devices/LNXSYSTM:00/LNXSYBUS:00/PNP0A08:00/LNXVIDEO:00/input/input3
>[    0.457160] ACPI: Video Device [VID] (multi-head: yes  rom: no  post: no)
>[    0.457160] ACPI: acpi_idle registered with cpuidle
>[    0.459825] Marking TSC unstable due to TSC halts in idle
>[    0.461292] thermal LNXTHERM:01: registered as thermal_zone0
>[    0.461292] ACPI: Thermal Zone [THM0] (57 C)
>[    0.464007] Non-volatile memory driver v1.3
>[    0.464007] Linux agpgart interface v0.103
>[    0.468012] agpgart-intel 0000:00:00.0: Intel 915GM Chipset
>[    0.468012] agpgart-intel 0000:00:00.0: detected 7932K stolen memory
>[    0.472015] agpgart-intel 0000:00:00.0: AGP aperture is 256M @ 0xc0000000
>[    0.472015] [drm] Initialized drm 1.1.0 20060810
>[    0.472015] i915 0000:00:02.0: power state changed by ACPI to D0
>[    0.472015] i915 0000:00:02.0: power state changed by ACPI to D0
>[    0.472015] i915 0000:00:02.0: PCI INT A -> GSI 16 (level, low) -> IRQ 16
>[    0.472015] i915 0000:00:02.0: setting latency timer to 64
>[    0.476014] [drm] set up 7M of stolen space
>[    0.476014] [drm:parse_general_definitions], crt_ddc_bus_pin: 2
>[    0.476014] [drm:parse_lfp_panel_data], Found panel mode in BIOS VBT tables:
>[    0.476014] [drm:drm_mode_debug_printmodeline], Modeline 0:"1024x768" 0 65000 1024 1048 1184 1344 768 771 777 806 0x8 0xa
>[    0.476014] [drm:parse_sdvo_device_mapping], No SDVO device info is found in VBT
>[    0.476014] [drm:intel_modeset_init], 2 display pipes available.
>[    0.476014] [drm:intel_crtc_init], swapping pipes & planes for FBC
>[    0.476014] [drm:intel_crtc_init], swapping pipes & planes for FBC
>[    0.488005] ACPI: Battery Slot [BAT0] (battery present)
>[    0.492060] [drm] initialized overlay support
>[    0.796007] [drm:drm_helper_probe_single_connector_modes], VGA-1
>[    0.800004] [drm:intel_update_watermarks], plane B (pipe 0) clock: 31500
>[    0.800004] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[    0.800004] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[    0.800004] [drm:intel_calculate_wm], FIFO entries required for mode: 0
>[    0.800004] [drm:intel_calculate_wm], FIFO watermark level: 26
>[    0.800004] [drm:intel_calculate_wm], FIFO entries required for mode: 9
>[    0.800004] [drm:intel_calculate_wm], FIFO watermark level: 20
>[    0.800004] [drm:i9xx_update_wm], FIFO watermarks - A: 26, B: 20
>[    0.800004] [drm:i9xx_update_wm], self-refresh entries: 12
>[    0.800004] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 26, B: 20, C: 2, SR 83
>[    0.824006] [drm:intel_crtc_mode_set], Mode for pipe A:
>[    0.824006] [drm:drm_mode_debug_printmodeline], Modeline 0:"640x480" 0 31500 640 664 704 832 480 489 491 520 0x10 0xa
>[    0.848006] [drm:intel_pipe_set_base], No FB bound
>[    0.848006] [drm:intel_update_watermarks], plane B (pipe 0) clock: 31500
>[    0.848006] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[    0.848006] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[    0.848006] [drm:intel_calculate_wm], FIFO entries required for mode: 0
>[    0.848006] [drm:intel_calculate_wm], FIFO watermark level: 26
>[    0.848006] [drm:intel_calculate_wm], FIFO entries required for mode: 9
>[    0.848006] [drm:intel_calculate_wm], FIFO watermark level: 20
>[    0.848006] [drm:i9xx_update_wm], FIFO watermarks - A: 26, B: 20
>[    0.848006] [drm:i9xx_update_wm], self-refresh entries: 12
>[    0.848006] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 26, B: 20, C: 2, SR 83
>[    0.848006] [drm:intel_update_watermarks], plane B (pipe 0) clock: 31500
>[    0.848006] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[    0.848006] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[    0.848006] [drm:intel_calculate_wm], FIFO entries required for mode: 0
>[    0.848006] [drm:intel_calculate_wm], FIFO watermark level: 26
>[    0.848006] [drm:intel_calculate_wm], FIFO entries required for mode: 9
>[    0.848006] [drm:intel_calculate_wm], FIFO watermark level: 20
>[    0.848006] [drm:i9xx_update_wm], FIFO watermarks - A: 26, B: 20
>[    0.848006] [drm:i9xx_update_wm], self-refresh entries: 12
>[    0.848006] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 26, B: 20, C: 2, SR 83
>[    0.944006] [drm:drm_helper_probe_single_connector_modes], VGA-1 is disconnected
>[    0.944006] [drm:drm_helper_probe_single_connector_modes], LVDS-1
>[    0.944006] [drm:drm_helper_probe_single_connector_modes], Probed modes for LVDS-1
>[    0.944006] [drm:drm_mode_debug_printmodeline], Modeline 26:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x8 0xa
>[    0.944006] [drm:drm_helper_probe_single_connector_modes], SVIDEO-1
>[    0.944006] [drm:intel_update_watermarks], plane B (pipe 0) clock: 107520
>[    0.944006] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[    0.944006] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[    0.944006] [drm:intel_calculate_wm], FIFO entries required for mode: 0
>[    0.944006] [drm:intel_calculate_wm], FIFO watermark level: 26
>[    0.944006] [drm:intel_calculate_wm], FIFO entries required for mode: 33
>[    0.944006] [drm:intel_calculate_wm], FIFO watermark level: -4
>[    0.944006] [drm:i9xx_update_wm], FIFO watermarks - A: 26, B: 1
>[    0.944006] [drm:i9xx_update_wm], self-refresh entries: 43
>[    0.944006] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 26, B: 1, C: 2, SR 52
>[    0.968007] [drm:intel_crtc_mode_set], Mode for pipe A:
>[    0.968007] [drm:drm_mode_debug_printmodeline], Modeline 0:"NTSC 480i" 0 107520 1280 1368 1496 1712 1024 1027 1034 1104 0x40 0x0
>[    0.992007] [drm:intel_pipe_set_base], No FB bound
>[    0.992007] [drm:intel_update_watermarks], plane B (pipe 0) clock: 107520
>[    0.992007] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[    0.992007] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[    0.992007] [drm:intel_calculate_wm], FIFO entries required for mode: 0
>[    0.992007] [drm:intel_calculate_wm], FIFO watermark level: 26
>[    0.992007] [drm:intel_calculate_wm], FIFO entries required for mode: 33
>[    0.992007] [drm:intel_calculate_wm], FIFO watermark level: -4
>[    0.992007] [drm:i9xx_update_wm], FIFO watermarks - A: 26, B: 1
>[    0.992007] [drm:i9xx_update_wm], self-refresh entries: 43
>[    0.992007] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 26, B: 1, C: 2, SR 52
>[    1.016007] [drm:intel_update_watermarks], plane B (pipe 0) clock: 107520
>[    1.016007] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[    1.016007] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[    1.016007] [drm:intel_calculate_wm], FIFO entries required for mode: 0
>[    1.016007] [drm:intel_calculate_wm], FIFO watermark level: 26
>[    1.016007] [drm:intel_calculate_wm], FIFO entries required for mode: 33
>[    1.016007] [drm:intel_calculate_wm], FIFO watermark level: -4
>[    1.016007] [drm:i9xx_update_wm], FIFO watermarks - A: 26, B: 1
>[    1.016007] [drm:i9xx_update_wm], self-refresh entries: 43
>[    1.016007] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 26, B: 1, C: 2, SR 52
>[    1.088006] [drm:intel_tv_detect_type], No TV connection detected
>[    1.136006] [drm:drm_helper_probe_single_connector_modes], SVIDEO-1 is disconnected
>[    1.136006] [drm:drm_setup_crtcs], 
>[    1.136006] [drm:drm_enable_connectors], connector 5 enabled? no
>[    1.136006] [drm:drm_enable_connectors], connector 7 enabled? yes
>[    1.136006] [drm:drm_enable_connectors], connector 11 enabled? no
>[    1.136006] [drm:drm_target_preferred], looking for cmdline mode on connector 7
>[    1.136006] [drm:drm_target_preferred], looking for preferred mode on connector 7
>[    1.136006] [drm:drm_target_preferred], found mode 1024x768
>[    1.136006] [drm:drm_setup_crtcs], picking CRTCs for 4096x4096 config
>[    1.136006] [drm:drm_setup_crtcs], desired mode 1024x768 set on crtc 4
>[    1.140015] [drm:intelfb_create], allocated 1024x768 fb: 0x007e0000, bo f68a1200
>[    1.144006] [drm:drm_crtc_helper_set_config], 
>[    1.144006] [drm:drm_crtc_helper_set_config], crtc: f6874000 3 fb: f6844c38 connectors: f6897900 num_connectors: 0 (x, y) (0, 0)
>[    1.144006] [drm:drm_crtc_helper_set_config], crtc has no fb, full mode set
>[    1.192007] [drm:drm_crtc_helper_set_config], 
>[    1.192007] [drm:drm_crtc_helper_set_config], crtc: f68aa000 4 fb: f6844c38 connectors: f68978e0 num_connectors: 1 (x, y) (0, 0)
>[    1.192007] [drm:drm_crtc_helper_set_config], crtc has no fb, full mode set
>[    1.192007] [drm:drm_crtc_helper_set_config], modes are different, full mode set
>[    1.192007] [drm:drm_mode_debug_printmodeline], Modeline 0:"" 0 0 0 0 0 0 0 0 0 0 0x0 0x0
>[    1.192007] [drm:drm_mode_debug_printmodeline], Modeline 27:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x8 0xa
>[    1.192007] [drm:drm_crtc_helper_set_config], encoder changed, full mode switch
>[    1.192007] [drm:drm_crtc_helper_set_config], crtc changed, full mode switch
>[    1.192007] [drm:drm_crtc_helper_set_config], setting connector 7 crtc to f68aa000
>[    1.192007] [drm:drm_crtc_helper_set_config], attempting to set mode from userspace
>[    1.192007] [drm:drm_mode_debug_printmodeline], Modeline 27:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x8 0xa
>[    1.192007] [drm:intel_update_watermarks], plane A (pipe 1) clock: 65000
>[    1.192007] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[    1.192007] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[    1.192007] [drm:intel_calculate_wm], FIFO entries required for mode: 20
>[    1.192007] [drm:intel_calculate_wm], FIFO watermark level: 6
>[    1.192007] [drm:intel_calculate_wm], FIFO entries required for mode: 0
>[    1.192007] [drm:intel_calculate_wm], FIFO watermark level: 29
>[    1.192007] [drm:i9xx_update_wm], FIFO watermarks - A: 6, B: 29
>[    1.192007] [drm:i9xx_update_wm], self-refresh entries: 25
>[    1.192007] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 6, B: 29, C: 2, SR 70
>[    1.216007] [drm:intel_crtc_mode_set], using SSC reference clock of 100 MHz
>[    1.216007] [drm:intel_crtc_mode_set], Mode for pipe B:
>[    1.216007] [drm:drm_mode_debug_printmodeline], Modeline 27:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x8 0xa
>[    1.240007] [drm:intel_pipe_set_base], Writing base 007E0000 00000000 0 0 4096
>[    1.264006] [drm:intel_update_watermarks], plane A (pipe 1) clock: 65000
>[    1.264006] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[    1.264006] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[    1.264006] [drm:intel_calculate_wm], FIFO entries required for mode: 20
>[    1.264006] [drm:intel_calculate_wm], FIFO watermark level: 6
>[    1.264006] [drm:intel_calculate_wm], FIFO entries required for mode: 0
>[    1.264006] [drm:intel_calculate_wm], FIFO watermark level: 29
>[    1.264006] [drm:i9xx_update_wm], FIFO watermarks - A: 6, B: 29
>[    1.264006] [drm:i9xx_update_wm], self-refresh entries: 25
>[    1.264006] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 6, B: 29, C: 2, SR 70
>[    1.264006] [drm:intel_update_watermarks], plane A (pipe 1) clock: 65000
>[    1.264006] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[    1.264006] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[    1.264006] [drm:intel_calculate_wm], FIFO entries required for mode: 20
>[    1.264006] [drm:intel_calculate_wm], FIFO watermark level: 6
>[    1.264006] [drm:intel_calculate_wm], FIFO entries required for mode: 0
>[    1.264006] [drm:intel_calculate_wm], FIFO watermark level: 29
>[    1.264006] [drm:i9xx_update_wm], FIFO watermarks - A: 6, B: 29
>[    1.264006] [drm:i9xx_update_wm], self-refresh entries: 25
>[    1.264006] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 6, B: 29, C: 2, SR 70
>[    1.264006] [drm:intel_update_watermarks], plane A (pipe 1) clock: 65000
>[    1.264006] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[    1.264006] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[    1.264006] [drm:intel_calculate_wm], FIFO entries required for mode: 20
>[    1.264006] [drm:intel_calculate_wm], FIFO watermark level: 6
>[    1.264006] [drm:intel_calculate_wm], FIFO entries required for mode: 0
>[    1.264006] [drm:intel_calculate_wm], FIFO watermark level: 29
>[    1.264006] [drm:i9xx_update_wm], FIFO watermarks - A: 6, B: 29
>[    1.264006] [drm:i9xx_update_wm], self-refresh entries: 25
>[    1.264006] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 6, B: 29, C: 2, SR 70
>[    1.288007] [drm:drm_crtc_helper_set_config], 
>[    1.288007] [drm:drm_crtc_helper_set_config], crtc: f68aa000 4 fb: f6844c38 connectors: f68978e0 num_connectors: 1 (x, y) (0, 0)
>[    1.288007] [drm:drm_crtc_helper_set_config], setting connector 7 crtc to f68aa000
>[    1.296005] [drm:drm_crtc_helper_set_config], 
>[    1.296005] [drm:drm_crtc_helper_set_config], crtc: f68aa000 4 fb: f6844c38 connectors: f68978e0 num_connectors: 1 (x, y) (0, 0)
>[    1.296005] [drm:drm_crtc_helper_set_config], setting connector 7 crtc to f68aa000
>[    1.304005] Console: switching to colour frame buffer device 170x69
>[    1.304005] [drm:drm_crtc_helper_set_config], 
>[    1.304005] [drm:drm_crtc_helper_set_config], crtc: f68aa000 4 fb: f6844c38 connectors: f68978e0 num_connectors: 1 (x, y) (0, 0)
>[    1.304005] [drm:drm_crtc_helper_set_config], setting connector 7 crtc to f68aa000
>[    1.312005] fb0: inteldrmfb frame buffer device
>[    1.312005] drm: registered panic notifier
>[    1.312005] [drm] Initialized i915 1.6.0 20080730 for 0000:00:02.0 on minor 0
>[    1.312005] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled
>[    1.312005] serial8250: ttyS1 at I/O 0x2f8 (irq = 3) is a NS16550A
>[    1.312005] 00:0a: ttyS0 at I/O 0x200 (irq = 5) is a NS16550A
>[    1.312005] serial 0000:00:1e.3: PCI INT B -> GSI 23 (level, low) -> IRQ 23
>[    1.312005] serial 0000:00:1e.3: PCI INT B disabled
>[    1.312005] loop: module loaded
>[    1.312005] ahci 0000:00:1f.2: version 3.0
>[    1.312005] ahci: probe of 0000:00:1f.2 failed with error -22
>[    1.312005] ata_piix 0000:00:1f.2: version 2.13
>[    1.312005] ata_piix 0000:00:1f.2: MAP [ P0 P2 IDE IDE ]
>[    1.468006] ata_piix 0000:00:1f.2: setting latency timer to 64
>[    1.468006] scsi0 : ata_piix
>[    1.468006] scsi1 : ata_piix
>[    1.468006] ata1: SATA max UDMA/133 cmd 0x1f0 ctl 0x3f6 bmdma 0x1810 irq 14
>[    1.468006] ata2: PATA max UDMA/100 cmd 0x170 ctl 0x376 bmdma 0x1818 irq 15
>[    1.468006] tg3.c:v3.110 (April 9, 2010)
>[    1.468006] tg3 0000:02:00.0: PCI INT A -> GSI 16 (level, low) -> IRQ 16
>[    1.468006] tg3 0000:02:00.0: setting latency timer to 64
>[    1.508004] tg3 0000:02:00.0: eth0: Tigon3 [partno(BCM95751M) rev 4101] (PCI Express) MAC address 00:16:d3:2f:fc:d1
>[    1.508004] tg3 0000:02:00.0: eth0: attached PHY is 5750 (10/100/1000Base-T Ethernet) (WireSpeed[1])
>[    1.508004] tg3 0000:02:00.0: eth0: RXcsums[1] LinkChgREG[0] MIirq[0] ASF[0] TSOcap[1]
>[    1.508004] tg3 0000:02:00.0: eth0: dma_rwctrl[76180000] dma_mask[64-bit]
>[    1.508004] PPP generic driver version 2.4.2
>[    1.508004] NET: Registered protocol family 24
>[    1.508004] tun: Universal TUN/TAP device driver, 1.6
>[    1.508004] tun: (C) 1999-2004 Max Krasnyansky <maxk@qualcomm.com>
>[    1.508004] usbcore: registered new interface driver asix
>[    1.508004] usbcore: registered new interface driver cdc_ether
>[    1.512005] usbcore: registered new interface driver cdc_eem
>[    1.512005] usbcore: registered new interface driver net1080
>[    1.512005] usbcore: registered new interface driver rndis_host
>[    1.512005] usbcore: registered new interface driver cdc_subset
>[    1.512005] usbcore: registered new interface driver zaurus
>[    1.512005] console [netcon0] enabled
>[    1.512005] netconsole: network logging started
>[    1.512005] yenta_cardbus 0000:04:00.0: CardBus bridge found [1014:0555]
>[    1.632282] ata1.00: ATA-6: HTC426040G9AT00, 00P4A0L2, max UDMA/100
>[    1.632282] ata1.00: 78140160 sectors, multi 16: LBA 
>[    1.632282] ata1.00: applying bridge limits
>[    1.648273] ata1.00: configured for UDMA/100
>[    1.648273] scsi 0:0:0:0: Direct-Access     ATA      HTC426040G9AT00  00P4 PQ: 0 ANSI: 5
>[    1.648273] sd 0:0:0:0: [sda] 78140160 512-byte logical blocks: (40.0 GB/37.2 GiB)
>[    1.648273] sd 0:0:0:0: [sda] Write Protect is off
>[    1.648273] sd 0:0:0:0: [sda] Mode Sense: 00 3a 00 00
>[    1.648273] sd 0:0:0:0: [sda] Write cache: enabled, read cache: enabled, doesn't support DPO or FUA
>[    1.648273]  sda:
>[    1.648273] sd 0:0:0:0: Attached scsi generic sg0 type 0
>[    1.753675]  sda3 sda4 < sda5 sda6 sda7 >
>[    1.804975] sd 0:0:0:0: [sda] Attached SCSI disk
>[    1.932006] yenta_cardbus 0000:04:00.0: ISA IRQ mask 0x0cb8, PCI irq 16
>[    1.932006] yenta_cardbus 0000:04:00.0: Socket status: 30000006
>[    1.936684] yenta_cardbus 0000:04:00.0: pcmcia: parent PCI bridge window: [io  0x3000-0x6fff]
>[    1.936684] yenta_cardbus 0000:04:00.0: pcmcia: parent PCI bridge window: [mem 0xa0200000-0xafffffff]
>[    1.940687] pcmcia_socket pcmcia_socket0: cs: memory probe 0xa0200000-0xafffffff: excluding 0xa0200000-0xa09fffff 0xa3a00000-0xa81fffff 0xafa00000-0xb01fffff
>[    1.940687] yenta_cardbus 0000:04:00.0: pcmcia: parent PCI bridge window: [mem 0xd0000000-0xd7ffffff 64bit pref]
>[    1.945117] pcmcia_socket pcmcia_socket0: cs: memory probe 0xd0000000-0xd7ffffff: excluding 0xd0000000-0xd7ffffff
>[    1.945117] ehci_hcd: USB 2.0 'Enhanced' Host Controller (EHCI) Driver
>[    1.950251] ehci_hcd 0000:00:1d.7: power state changed by ACPI to D0
>[    1.952842] ehci_hcd 0000:00:1d.7: power state changed by ACPI to D0
>[    1.952842] ehci_hcd 0000:00:1d.7: PCI INT D -> GSI 19 (level, low) -> IRQ 19
>[    1.957733] ehci_hcd 0000:00:1d.7: setting latency timer to 64
>[    1.957733] ehci_hcd 0000:00:1d.7: EHCI Host Controller
>[    1.960191] ehci_hcd 0000:00:1d.7: new USB bus registered, assigned bus number 1
>[    1.960191] ehci_hcd 0000:00:1d.7: debug port 1
>[    1.968004] ehci_hcd 0000:00:1d.7: cache line size of 32 is not supported
>[    1.968004] ehci_hcd 0000:00:1d.7: irq 19, io mem 0xa0040000
>[    1.984006] ehci_hcd 0000:00:1d.7: USB 2.0 started, EHCI 1.00
>[    1.984006] usb usb1: New USB device found, idVendor=1d6b, idProduct=0002
>[    1.989228] usb usb1: New USB device strings: Mfr=3, Product=2, SerialNumber=1
>[    1.989228] usb usb1: Product: EHCI Host Controller
>[    1.994540] usb usb1: Manufacturer: Linux 2.6.35-rc6 ehci_hcd
>[    1.997242] usb usb1: SerialNumber: 0000:00:1d.7
>[    2.000005] hub 1-0:1.0: USB hub found
>[    2.000005] hub 1-0:1.0: 8 ports detected
>[    2.005391] uhci_hcd: USB Universal Host Controller Interface driver
>[    2.008319] uhci_hcd 0000:00:1d.0: power state changed by ACPI to D0
>[    2.011218] uhci_hcd 0000:00:1d.0: power state changed by ACPI to D0
>[    2.013931] uhci_hcd 0000:00:1d.0: PCI INT A -> GSI 16 (level, low) -> IRQ 16
>[    2.016570] uhci_hcd 0000:00:1d.0: setting latency timer to 64
>[    2.016570] uhci_hcd 0000:00:1d.0: UHCI Host Controller
>[    2.016570] uhci_hcd 0000:00:1d.0: new USB bus registered, assigned bus number 2
>[    2.021873] uhci_hcd 0000:00:1d.0: irq 16, io base 0x00001820
>[    2.024533] usb usb2: New USB device found, idVendor=1d6b, idProduct=0001
>[    2.024533] usb usb2: New USB device strings: Mfr=3, Product=2, SerialNumber=1
>[    2.029875] usb usb2: Product: UHCI Host Controller
>[    2.032504] usb usb2: Manufacturer: Linux 2.6.35-rc6 uhci_hcd
>[    2.032504] usb usb2: SerialNumber: 0000:00:1d.0
>[    2.037798] hub 2-0:1.0: USB hub found
>[    2.040624] hub 2-0:1.0: 2 ports detected
>[    2.043404] uhci_hcd 0000:00:1d.1: power state changed by ACPI to D0
>[    2.046237] uhci_hcd 0000:00:1d.1: power state changed by ACPI to D0
>[    2.048903] uhci_hcd 0000:00:1d.1: PCI INT B -> GSI 17 (level, low) -> IRQ 17
>[    2.048903] uhci_hcd 0000:00:1d.1: setting latency timer to 64
>[    2.048903] uhci_hcd 0000:00:1d.1: UHCI Host Controller
>[    2.054020] uhci_hcd 0000:00:1d.1: new USB bus registered, assigned bus number 3
>[    2.056646] uhci_hcd 0000:00:1d.1: irq 17, io base 0x00001840
>[    2.056646] usb usb3: New USB device found, idVendor=1d6b, idProduct=0001
>[    2.061836] usb usb3: New USB device strings: Mfr=3, Product=2, SerialNumber=1
>[    2.064419] usb usb3: Product: UHCI Host Controller
>[    2.064419] usb usb3: Manufacturer: Linux 2.6.35-rc6 uhci_hcd
>[    2.069547] usb usb3: SerialNumber: 0000:00:1d.1
>[    2.072122] hub 3-0:1.0: USB hub found
>[    2.072122] hub 3-0:1.0: 2 ports detected
>[    2.077487] uhci_hcd 0000:00:1d.2: PCI INT C -> GSI 18 (level, low) -> IRQ 18
>[    2.080228] uhci_hcd 0000:00:1d.2: setting latency timer to 64
>[    2.080228] uhci_hcd 0000:00:1d.2: UHCI Host Controller
>[    2.080228] uhci_hcd 0000:00:1d.2: new USB bus registered, assigned bus number 4
>[    2.085703] uhci_hcd 0000:00:1d.2: irq 18, io base 0x00001860
>[    2.088464] usb usb4: New USB device found, idVendor=1d6b, idProduct=0001
>[    2.088464] usb usb4: New USB device strings: Mfr=3, Product=2, SerialNumber=1
>[    2.093997] usb usb4: Product: UHCI Host Controller
>[    2.096713] usb usb4: Manufacturer: Linux 2.6.35-rc6 uhci_hcd
>[    2.096713] usb usb4: SerialNumber: 0000:00:1d.2
>[    2.102133] hub 4-0:1.0: USB hub found
>[    2.105012] hub 4-0:1.0: 2 ports detected
>[    2.105012] uhci_hcd 0000:00:1d.3: PCI INT D -> GSI 19 (level, low) -> IRQ 19
>[    2.110466] uhci_hcd 0000:00:1d.3: setting latency timer to 64
>[    2.110466] uhci_hcd 0000:00:1d.3: UHCI Host Controller
>[    2.113162] uhci_hcd 0000:00:1d.3: new USB bus registered, assigned bus number 5
>[    2.113162] uhci_hcd 0000:00:1d.3: irq 19, io base 0x00001880
>[    2.118620] usb usb5: New USB device found, idVendor=1d6b, idProduct=0001
>[    2.121342] usb usb5: New USB device strings: Mfr=3, Product=2, SerialNumber=1
>[    2.124017] usb usb5: Product: UHCI Host Controller
>[    2.124017] usb usb5: Manufacturer: Linux 2.6.35-rc6 uhci_hcd
>[    2.129329] usb usb5: SerialNumber: 0000:00:1d.3
>[    2.132005] hub 5-0:1.0: USB hub found
>[    2.132005] hub 5-0:1.0: 2 ports detected
>[    2.137393] usbcore: registered new interface driver cdc_acm
>[    2.140163] cdc_acm: v0.26:USB Abstract Control Model driver for USB modems and ISDN adapters
>[    2.140163] usbcore: registered new interface driver usblp
>[    2.145314] Initializing USB Mass Storage driver...
>[    2.145314] usbcore: registered new interface driver usb-storage
>[    2.150370] USB Mass Storage support registered.
>[    2.152890] usbcore: registered new interface driver libusual
>[    2.152890] PNP: PS/2 Controller [PNP0303:KBD,PNP0f13:MOU] at 0x60,0x64 irq 1,12
>[    2.165240] serio: i8042 KBD port at 0x60,0x64 irq 1
>[    2.170067] serio: i8042 AUX port at 0x60,0x64 irq 12
>[    2.172604] mice: PS/2 mouse device common for all mice
>[    2.172604] i801_smbus 0000:00:1f.3: PCI INT A -> GSI 23 (level, low) -> IRQ 23
>[    2.178332] md: linear personality registered for level -1
>[    2.181051] md: raid1 personality registered for level 1
>[    2.181051] device-mapper: ioctl: 4.17.0-ioctl (2010-03-05) initialised: dm-devel@redhat.com
>[    2.186415] cpuidle: using governor ladder
>[    2.189260] cpuidle: using governor menu
>[    2.192129] usbcore: registered new interface driver usbhid
>[    2.196052] usbhid: USB HID core driver
>[    2.196052] Intel ICH 0000:00:1e.2: PCI INT A -> GSI 22 (level, low) -> IRQ 22
>[    2.201721] Intel ICH 0000:00:1e.2: setting latency timer to 64
>[    2.201721] input: AT Translated Set 2 keyboard as /devices/platform/i8042/serio0/input/input4
>[    2.324051] usb 1-5: new high speed USB device using ehci_hcd and address 2
>[    2.456919] usb 1-5: New USB device found, idVendor=0781, idProduct=5406
>[    2.456919] usb 1-5: New USB device strings: Mfr=1, Product=2, SerialNumber=3
>[    2.462424] usb 1-5: Product: U3 Cruzer Micro
>[    2.466180] usb 1-5: Manufacturer: SanDisk
>[    2.468942] usb 1-5: SerialNumber: 0266810A225084E6
>[    2.472005] scsi2 : usb-storage 1-5:1.0
>[    2.475414] scsi 2:0:0:0: Direct-Access     SanDisk  U3 Cruzer Micro  8.02 PQ: 0 ANSI: 0 CCS
>[    2.478214] sd 2:0:0:0: Attached scsi generic sg1 type 0
>[    2.482415] sd 2:0:0:0: [sdb] 31825919 512-byte logical blocks: (16.2 GB/15.1 GiB)
>[    2.485790] sd 2:0:0:0: [sdb] Write Protect is off
>[    2.488589] sd 2:0:0:0: [sdb] Mode Sense: 45 00 00 08
>[    2.488589] sd 2:0:0:0: [sdb] Assuming drive cache: write through
>[    2.493415] sd 2:0:0:0: [sdb] Assuming drive cache: write through
>[    2.496203]  sdb: unknown partition table
>[    2.501165] sd 2:0:0:0: [sdb] Assuming drive cache: write through
>[    2.501165] sd 2:0:0:0: [sdb] Attached SCSI removable disk
>[    2.766327] IBM TrackPoint firmware: 0x0e, buttons: 3/3
>[    2.792751] input: TPPS/2 IBM TrackPoint as /devices/platform/i8042/serio1/input/input5
>[    3.136017] intel8x0_measure_ac97_clock: measured 55881 usecs (11 samples)
>[    3.136017] intel8x0: measured clock 196 rejected
>[    3.500017] intel8x0_measure_ac97_clock: measured 55926 usecs (2694 samples)
>[    3.500017] intel8x0: clocking to 48000
>[    3.505701] ALSA device list:
>[    3.509054]   #0: Intel ICH6 with AD1981B at irq 22
>[    3.509054] netem: version 1.2
>[    3.514756] u32 classifier
>[    3.517561] Netfilter messages via NETLINK v0.30.
>[    3.520377] nf_conntrack version 0.5.0 (16384 buckets, 65536 max)
>[    3.520377] IPv4 over IPv4 tunneling driver
>[    3.526190] ip_tables: (C) 2000-2006 Netfilter Core Team
>[    3.529260] TCP bic registered
>[    3.532137] TCP cubic registered
>[    3.532137] TCP westwood registered
>[    3.537667] TCP highspeed registered
>[    3.540424] TCP hybla registered
>[    3.540424] TCP vegas registered
>[    3.545894] TCP veno registered
>[    3.548596] TCP illinois registered
>[    3.548596] NET: Registered protocol family 10
>[    3.554038] IPv6 over IPv4 tunneling driver
>[    3.556958] NET: Registered protocol family 17
>[    3.556958] Bridge firewalling registered
>[    3.562563] Bluetooth: L2CAP ver 2.14
>[    3.565214] Bluetooth: L2CAP socket layer initialized
>[    3.565214] Bluetooth: SCO (Voice Link) ver 0.6
>[    3.570465] Bluetooth: SCO socket layer initialized
>[    3.573079] Bluetooth: RFCOMM TTY layer initialized
>[    3.573079] Bluetooth: RFCOMM socket layer initialized
>[    3.578300] Bluetooth: RFCOMM ver 1.11
>[    3.580840] Bluetooth: BNEP (Ethernet Emulation) ver 1.3
>[    3.580840] Bluetooth: BNEP filters: protocol multicast
>[    3.585864] Bluetooth: HIDP (Human Interface Emulation) ver 1.2
>[    3.588370] 802.1Q VLAN Support v1.8 Ben Greear <greearb@candelatech.com>
>[    3.588370] All bugs added by David S. Miller <davem@redhat.com>
>[    3.593458] lib80211: common routines for IEEE802.11 drivers
>[    3.593458] lib80211_crypt: registered algorithm 'NULL'
>[    3.596787] Using IPI Shortcut mode
>[    3.600095] md: Waiting for all devices to be available before autodetect
>[    3.600095] md: If you don't use raid, use raid=noautodetect
>[    3.605948] md: Autodetecting RAID arrays.
>[    3.608684] md: Scanned 0 and added 0 devices.
>[    3.608684] md: autorun ...
>[    3.613635] md: ... autorun DONE.
>[    3.616271] EXT3-fs (sda5): error: couldn't mount because of unsupported optional features (40)
>[    3.618919] EXT2-fs (sda5): error: couldn't mount because of unsupported optional features (40)
>[    3.756211] EXT4-fs (sda5): mounted filesystem with ordered data mode. Opts: (null)
>[    3.756211] VFS: Mounted root (ext4 filesystem) readonly on device 8:5.
>[    3.778566] devtmpfs: mounted
>[    3.778566] Freeing unused kernel memory: 472k freed
>[    3.778566] Write protecting the kernel text: 5664k
>[    3.782177] Write protecting the kernel read-only data: 2228k
>[    6.712806] udev: starting version 154
>[    7.572009] udev: renamed network interface eth0 to lan0
>[    8.548007] sdhci: Secure Digital Host Controller Interface driver
>[    8.557078] sdhci: Copyright(c) Pierre Ossman
>[    8.580006] thinkpad_acpi: ThinkPad ACPI Extras v0.24
>[    8.587645] thinkpad_acpi: http://ibm-acpi.sf.net/
>[    8.593200] thinkpad_acpi: ThinkPad BIOS 75ET60WW (2.06 ), EC 75HT20WW-1.02
>[    8.636009] thinkpad_acpi: IBM ThinkPad X41 Tablet, model 1866CTO
>[    8.676008] thinkpad_acpi: detected a 8-level brightness capable ThinkPad
>[    8.712010] thinkpad_acpi: possible tablet mode switch found; ThinkPad in laptop mode
>[    8.752009] sdhci-pci 0000:04:00.1: SDHCI controller found [1180:0822] (rev 13)
>[    8.768010] Registered led device: tpacpi::thinklight
>[    8.768010] Registered led device: tpacpi::power
>[    8.768010] Registered led device: tpacpi::standby
>[    8.772011] sdhci-pci 0000:04:00.1: PCI INT B -> GSI 17 (level, low) -> IRQ 17
>[    8.788010] mmc0: Controller vendor_ver=02 sdhci_ver=00.
>[    8.796009] thinkpad_acpi: Console audio control enabled, mode: monitor (read only)
>[    8.812010] mmc0: Controller caps=018021a1.
>[    8.824009] input: ThinkPad Extra Buttons as /devices/platform/thinkpad_acpi/input/input6
>[    8.836007] SDHCI_INT_ENABLE: Can toggle bits e1ff01ff
>[    8.840267] SDHCI_HOST_CONTROL: Can toggle bits 06
>[    8.840267] DMA forced on (host quirk)
>[    8.852010] sdhci-pci 0000:04:00.1: Will use DMA mode even though HW doesn't fully claim to support it.
>[    8.852010] host->max_clk: 33000000
>[    8.864008] HISPD forced on (host quirk)
>[    8.864008] Verified that HOST_CONTROL bit SDHCI_CTRL_HISPD can be toggled
>[    8.869343] Could not set SDHCI_CTRL_LED to 1!
>[    8.874595] mmc0: SDHCI controller on PCI [0000:04:00.1] using DMA
>[   11.332007] [drm:intel_update_watermarks], plane B (pipe 0) clock: 31500
>[   11.332007] [drm:intel_update_watermarks], plane A (pipe 1) clock: 65000
>[   11.332007] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[   11.332007] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[   11.332007] [drm:intel_calculate_wm], FIFO entries required for mode: 20
>[   11.332007] [drm:intel_calculate_wm], FIFO watermark level: 6
>[   11.332007] [drm:intel_calculate_wm], FIFO entries required for mode: 9
>[   11.332007] [drm:intel_calculate_wm], FIFO watermark level: 20
>[   11.332007] [drm:i9xx_update_wm], FIFO watermarks - A: 6, B: 20
>[   11.332007] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 6, B: 20, C: 2, SR 1
>[   11.356020] [drm:intel_crtc_mode_set], Mode for pipe A:
>[   11.356020] [drm:drm_mode_debug_printmodeline], Modeline 0:"640x480" 0 31500 640 664 704 832 480 489 491 520 0x10 0xa
>[   11.380019] [drm:intel_pipe_set_base], No FB bound
>[   11.380019] [drm:intel_update_watermarks], plane B (pipe 0) clock: 31500
>[   11.380019] [drm:intel_update_watermarks], plane A (pipe 1) clock: 65000
>[   11.380019] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[   11.380019] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[   11.380019] [drm:intel_calculate_wm], FIFO entries required for mode: 20
>[   11.380019] [drm:intel_calculate_wm], FIFO watermark level: 6
>[   11.380019] [drm:intel_calculate_wm], FIFO entries required for mode: 9
>[   11.380019] [drm:intel_calculate_wm], FIFO watermark level: 20
>[   11.380019] [drm:i9xx_update_wm], FIFO watermarks - A: 6, B: 20
>[   11.380019] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 6, B: 20, C: 2, SR 1
>[   11.380019] [drm:intel_update_watermarks], plane B (pipe 0) clock: 31500
>[   11.380019] [drm:intel_update_watermarks], plane A (pipe 1) clock: 65000
>[   11.380019] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[   11.380019] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[   11.380019] [drm:intel_calculate_wm], FIFO entries required for mode: 20
>[   11.380019] [drm:intel_calculate_wm], FIFO watermark level: 6
>[   11.380019] [drm:intel_calculate_wm], FIFO entries required for mode: 9
>[   11.380019] [drm:intel_calculate_wm], FIFO watermark level: 20
>[   11.380019] [drm:i9xx_update_wm], FIFO watermarks - A: 6, B: 20
>[   11.380019] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 6, B: 20, C: 2, SR 1
>[   11.428022] [drm:intel_update_watermarks], plane A (pipe 1) clock: 65000
>[   11.428022] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[   11.428022] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[   11.428022] [drm:intel_calculate_wm], FIFO entries required for mode: 20
>[   11.428022] [drm:intel_calculate_wm], FIFO watermark level: 6
>[   11.428022] [drm:intel_calculate_wm], FIFO entries required for mode: 0
>[   11.428022] [drm:intel_calculate_wm], FIFO watermark level: 29
>[   11.428022] [drm:i9xx_update_wm], FIFO watermarks - A: 6, B: 29
>[   11.428022] [drm:i9xx_update_wm], self-refresh entries: 25
>[   11.428022] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 6, B: 29, C: 2, SR 70
>[   12.028907] Adding 1068284k swap on /dev/sda7.  Priority:10 extents:1 across:1068284k 
>[   12.068010] EXT4-fs (sda5): re-mounted. Opts: (null)
>[   12.597739] EXT4-fs (sda5): re-mounted. Opts: (null)
>[   12.860012] libipw: 802.11 data/management/control stack, git-1.1.13
>[   12.892010] libipw: Copyright (C) 2004-2005 Intel Corporation <jketreno@linux.intel.com>
>[   12.968010] ipw2200: Intel(R) PRO/Wireless 2200/2915 Network Driver, 1.2.2kmprq
>[   12.968010] ipw2200: Copyright(c) 2003-2006 Intel Corporation
>[   12.968010] ipw2200 0000:04:02.0: PCI INT A -> GSI 21 (level, low) -> IRQ 21
>[   12.972011] ipw2200: Detected Intel PRO/Wireless 2915ABG Network Connection
>[   13.292009] ipw2200: Detected geography ZZA (11 802.11bg channels, 13 802.11a channels)
>[   13.348010] udev: renamed network interface eth0 to wlan0
>[   15.137398] EXT4-fs (sda3): mounted filesystem with ordered data mode. Opts: (null)
>[   15.193808] EXT4-fs (sda6): mounted filesystem with ordered data mode. Opts: (null)
>[   18.805568] lib80211_crypt: registered algorithm 'CCMP'
>[   18.812009] lib80211_crypt: registered algorithm 'TKIP'
>[   21.476007] [drm:intel_update_watermarks], plane B (pipe 0) clock: 31500
>[   21.476007] [drm:intel_update_watermarks], plane A (pipe 1) clock: 65000
>[   21.476007] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[   21.476007] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[   21.476007] [drm:intel_calculate_wm], FIFO entries required for mode: 20
>[   21.476007] [drm:intel_calculate_wm], FIFO watermark level: 6
>[   21.476007] [drm:intel_calculate_wm], FIFO entries required for mode: 9
>[   21.476007] [drm:intel_calculate_wm], FIFO watermark level: 20
>[   21.476007] [drm:i9xx_update_wm], FIFO watermarks - A: 6, B: 20
>[   21.476007] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 6, B: 20, C: 2, SR 1
>[   21.500022] [drm:intel_crtc_mode_set], Mode for pipe A:
>[   21.500022] [drm:drm_mode_debug_printmodeline], Modeline 0:"640x480" 0 31500 640 664 704 832 480 489 491 520 0x10 0xa
>[   21.527152] [drm:intel_pipe_set_base], No FB bound
>[   21.527152] [drm:intel_update_watermarks], plane B (pipe 0) clock: 31500
>[   21.527152] [drm:intel_update_watermarks], plane A (pipe 1) clock: 65000
>[   21.527152] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[   21.527152] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[   21.527152] [drm:intel_calculate_wm], FIFO entries required for mode: 20
>[   21.527152] [drm:intel_calculate_wm], FIFO watermark level: 6
>[   21.527152] [drm:intel_calculate_wm], FIFO entries required for mode: 9
>[   21.527152] [drm:intel_calculate_wm], FIFO watermark level: 20
>[   21.527152] [drm:i9xx_update_wm], FIFO watermarks - A: 6, B: 20
>[   21.527152] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 6, B: 20, C: 2, SR 1
>[   21.527152] [drm:intel_update_watermarks], plane B (pipe 0) clock: 31500
>[   21.527152] [drm:intel_update_watermarks], plane A (pipe 1) clock: 65000
>[   21.527152] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[   21.527152] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[   21.527152] [drm:intel_calculate_wm], FIFO entries required for mode: 20
>[   21.527152] [drm:intel_calculate_wm], FIFO watermark level: 6
>[   21.527152] [drm:intel_calculate_wm], FIFO entries required for mode: 9
>[   21.527152] [drm:intel_calculate_wm], FIFO watermark level: 20
>[   21.527152] [drm:i9xx_update_wm], FIFO watermarks - A: 6, B: 20
>[   21.527152] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 6, B: 20, C: 2, SR 1
>[   21.572022] [drm:intel_update_watermarks], plane A (pipe 1) clock: 65000
>[   21.572022] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[   21.572022] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[   21.572022] [drm:intel_calculate_wm], FIFO entries required for mode: 20
>[   21.572022] [drm:intel_calculate_wm], FIFO watermark level: 6
>[   21.572022] [drm:intel_calculate_wm], FIFO entries required for mode: 0
>[   21.572022] [drm:intel_calculate_wm], FIFO watermark level: 29
>[   21.572022] [drm:i9xx_update_wm], FIFO watermarks - A: 6, B: 29
>[   21.572022] [drm:i9xx_update_wm], self-refresh entries: 25
>[   21.572022] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 6, B: 29, C: 2, SR 70
>[   23.277561] ADDRCONF(NETDEV_UP): lan0: link is not ready
>[   28.432019] wlan0: no IPv6 routers present
>[   31.620008] [drm:intel_update_watermarks], plane B (pipe 0) clock: 31500
>[   31.620008] [drm:intel_update_watermarks], plane A (pipe 1) clock: 65000
>[   31.620008] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[   31.620008] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[   31.620008] [drm:intel_calculate_wm], FIFO entries required for mode: 20
>[   31.620008] [drm:intel_calculate_wm], FIFO watermark level: 6
>[   31.620008] [drm:intel_calculate_wm], FIFO entries required for mode: 9
>[   31.620008] [drm:intel_calculate_wm], FIFO watermark level: 20
>[   31.620008] [drm:i9xx_update_wm], FIFO watermarks - A: 6, B: 20
>[   31.620008] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 6, B: 20, C: 2, SR 1
>[   31.644025] [drm:intel_crtc_mode_set], Mode for pipe A:
>[   31.644025] [drm:drm_mode_debug_printmodeline], Modeline 0:"640x480" 0 31500 640 664 704 832 480 489 491 520 0x10 0xa
>[   31.668020] [drm:intel_pipe_set_base], No FB bound
>[   31.668020] [drm:intel_update_watermarks], plane B (pipe 0) clock: 31500
>[   31.668020] [drm:intel_update_watermarks], plane A (pipe 1) clock: 65000
>[   31.668020] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[   31.668020] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[   31.668020] [drm:intel_calculate_wm], FIFO entries required for mode: 20
>[   31.668020] [drm:intel_calculate_wm], FIFO watermark level: 6
>[   31.668020] [drm:intel_calculate_wm], FIFO entries required for mode: 9
>[   31.668020] [drm:intel_calculate_wm], FIFO watermark level: 20
>[   31.668020] [drm:i9xx_update_wm], FIFO watermarks - A: 6, B: 20
>[   31.668020] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 6, B: 20, C: 2, SR 1
>[   31.668020] [drm:intel_update_watermarks], plane B (pipe 0) clock: 31500
>[   31.668020] [drm:intel_update_watermarks], plane A (pipe 1) clock: 65000
>[   31.668020] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[   31.668020] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[   31.668020] [drm:intel_calculate_wm], FIFO entries required for mode: 20
>[   31.668020] [drm:intel_calculate_wm], FIFO watermark level: 6
>[   31.668020] [drm:intel_calculate_wm], FIFO entries required for mode: 9
>[   31.668020] [drm:intel_calculate_wm], FIFO watermark level: 20
>[   31.668020] [drm:i9xx_update_wm], FIFO watermarks - A: 6, B: 20
>[   31.668020] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 6, B: 20, C: 2, SR 1
>[   31.716023] [drm:intel_update_watermarks], plane A (pipe 1) clock: 65000
>[   31.716023] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[   31.716023] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[   31.716023] [drm:intel_calculate_wm], FIFO entries required for mode: 20
>[   31.716023] [drm:intel_calculate_wm], FIFO watermark level: 6
>[   31.716023] [drm:intel_calculate_wm], FIFO entries required for mode: 0
>[   31.716023] [drm:intel_calculate_wm], FIFO watermark level: 29
>[   31.716023] [drm:i9xx_update_wm], FIFO watermarks - A: 6, B: 29
>[   31.716023] [drm:i9xx_update_wm], self-refresh entries: 25
>[   31.716023] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 6, B: 29, C: 2, SR 70
>[   41.764007] [drm:intel_update_watermarks], plane B (pipe 0) clock: 31500
>[   41.764007] [drm:intel_update_watermarks], plane A (pipe 1) clock: 65000
>[   41.764007] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[   41.764007] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[   41.764007] [drm:intel_calculate_wm], FIFO entries required for mode: 20
>[   41.764007] [drm:intel_calculate_wm], FIFO watermark level: 6
>[   41.764007] [drm:intel_calculate_wm], FIFO entries required for mode: 9
>[   41.764007] [drm:intel_calculate_wm], FIFO watermark level: 20
>[   41.764007] [drm:i9xx_update_wm], FIFO watermarks - A: 6, B: 20
>[   41.764007] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 6, B: 20, C: 2, SR 1
>[   41.788061] [drm:intel_crtc_mode_set], Mode for pipe A:
>[   41.788061] [drm:drm_mode_debug_printmodeline], Modeline 0:"640x480" 0 31500 640 664 704 832 480 489 491 520 0x10 0xa
>[   41.812061] [drm:intel_pipe_set_base], No FB bound
>[   41.812061] [drm:intel_update_watermarks], plane B (pipe 0) clock: 31500
>[   41.812061] [drm:intel_update_watermarks], plane A (pipe 1) clock: 65000
>[   41.812061] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[   41.812061] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[   41.812061] [drm:intel_calculate_wm], FIFO entries required for mode: 20
>[   41.812061] [drm:intel_calculate_wm], FIFO watermark level: 6
>[   41.812061] [drm:intel_calculate_wm], FIFO entries required for mode: 9
>[   41.812061] [drm:intel_calculate_wm], FIFO watermark level: 20
>[   41.812061] [drm:i9xx_update_wm], FIFO watermarks - A: 6, B: 20
>[   41.812061] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 6, B: 20, C: 2, SR 1
>[   41.812061] [drm:intel_update_watermarks], plane B (pipe 0) clock: 31500
>[   41.812061] [drm:intel_update_watermarks], plane A (pipe 1) clock: 65000
>[   41.812061] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[   41.812061] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[   41.812061] [drm:intel_calculate_wm], FIFO entries required for mode: 20
>[   41.812061] [drm:intel_calculate_wm], FIFO watermark level: 6
>[   41.812061] [drm:intel_calculate_wm], FIFO entries required for mode: 9
>[   41.812061] [drm:intel_calculate_wm], FIFO watermark level: 20
>[   41.812061] [drm:i9xx_update_wm], FIFO watermarks - A: 6, B: 20
>[   41.812061] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 6, B: 20, C: 2, SR 1
>[   41.861914] [drm:intel_update_watermarks], plane A (pipe 1) clock: 65000
>[   41.861914] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[   41.861914] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[   41.861914] [drm:intel_calculate_wm], FIFO entries required for mode: 20
>[   41.861914] [drm:intel_calculate_wm], FIFO watermark level: 6
>[   41.861914] [drm:intel_calculate_wm], FIFO entries required for mode: 0
>[   41.861914] [drm:intel_calculate_wm], FIFO watermark level: 29
>[   41.861914] [drm:i9xx_update_wm], FIFO watermarks - A: 6, B: 29
>[   41.861914] [drm:i9xx_update_wm], self-refresh entries: 25
>[   41.861914] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 6, B: 29, C: 2, SR 70
>[   51.908007] [drm:intel_update_watermarks], plane B (pipe 0) clock: 31500
>[   51.908007] [drm:intel_update_watermarks], plane A (pipe 1) clock: 65000
>[   51.908007] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[   51.908007] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[   51.908007] [drm:intel_calculate_wm], FIFO entries required for mode: 20
>[   51.908007] [drm:intel_calculate_wm], FIFO watermark level: 6
>[   51.908007] [drm:intel_calculate_wm], FIFO entries required for mode: 9
>[   51.908007] [drm:intel_calculate_wm], FIFO watermark level: 20
>[   51.908007] [drm:i9xx_update_wm], FIFO watermarks - A: 6, B: 20
>[   51.908007] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 6, B: 20, C: 2, SR 1
>[   51.932059] [drm:intel_crtc_mode_set], Mode for pipe A:
>[   51.932059] [drm:drm_mode_debug_printmodeline], Modeline 0:"640x480" 0 31500 640 664 704 832 480 489 491 520 0x10 0xa
>[   51.956059] [drm:intel_pipe_set_base], No FB bound
>[   51.956059] [drm:intel_update_watermarks], plane B (pipe 0) clock: 31500
>[   51.956059] [drm:intel_update_watermarks], plane A (pipe 1) clock: 65000
>[   51.956059] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[   51.956059] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[   51.956059] [drm:intel_calculate_wm], FIFO entries required for mode: 20
>[   51.956059] [drm:intel_calculate_wm], FIFO watermark level: 6
>[   51.956059] [drm:intel_calculate_wm], FIFO entries required for mode: 9
>[   51.956059] [drm:intel_calculate_wm], FIFO watermark level: 20
>[   51.956059] [drm:i9xx_update_wm], FIFO watermarks - A: 6, B: 20
>[   51.956059] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 6, B: 20, C: 2, SR 1
>[   51.956059] [drm:intel_update_watermarks], plane B (pipe 0) clock: 31500
>[   51.956059] [drm:intel_update_watermarks], plane A (pipe 1) clock: 65000
>[   51.956059] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[   51.956059] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[   51.956059] [drm:intel_calculate_wm], FIFO entries required for mode: 20
>[   51.956059] [drm:intel_calculate_wm], FIFO watermark level: 6
>[   51.956059] [drm:intel_calculate_wm], FIFO entries required for mode: 9
>[   51.956059] [drm:intel_calculate_wm], FIFO watermark level: 20
>[   51.956059] [drm:i9xx_update_wm], FIFO watermarks - A: 6, B: 20
>[   51.956059] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 6, B: 20, C: 2, SR 1
>[   52.004061] [drm:intel_update_watermarks], plane A (pipe 1) clock: 65000
>[   52.004061] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[   52.004061] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[   52.004061] [drm:intel_calculate_wm], FIFO entries required for mode: 20
>[   52.004061] [drm:intel_calculate_wm], FIFO watermark level: 6
>[   52.004061] [drm:intel_calculate_wm], FIFO entries required for mode: 0
>[   52.004061] [drm:intel_calculate_wm], FIFO watermark level: 29
>[   52.004061] [drm:i9xx_update_wm], FIFO watermarks - A: 6, B: 29
>[   52.004061] [drm:i9xx_update_wm], self-refresh entries: 25
>[   52.004061] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 6, B: 29, C: 2, SR 70
>[   62.052007] [drm:intel_update_watermarks], plane B (pipe 0) clock: 31500
>[   62.052007] [drm:intel_update_watermarks], plane A (pipe 1) clock: 65000
>[   62.052007] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[   62.052007] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[   62.052007] [drm:intel_calculate_wm], FIFO entries required for mode: 20
>[   62.052007] [drm:intel_calculate_wm], FIFO watermark level: 6
>[   62.052007] [drm:intel_calculate_wm], FIFO entries required for mode: 9
>[   62.052007] [drm:intel_calculate_wm], FIFO watermark level: 20
>[   62.052007] [drm:i9xx_update_wm], FIFO watermarks - A: 6, B: 20
>[   62.052007] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 6, B: 20, C: 2, SR 1
>[   62.076055] [drm:intel_crtc_mode_set], Mode for pipe A:
>[   62.076055] [drm:drm_mode_debug_printmodeline], Modeline 0:"640x480" 0 31500 640 664 704 832 480 489 491 520 0x10 0xa
>[   62.100058] [drm:intel_pipe_set_base], No FB bound
>[   62.100058] [drm:intel_update_watermarks], plane B (pipe 0) clock: 31500
>[   62.100058] [drm:intel_update_watermarks], plane A (pipe 1) clock: 65000
>[   62.100058] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[   62.100058] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[   62.100058] [drm:intel_calculate_wm], FIFO entries required for mode: 20
>[   62.100058] [drm:intel_calculate_wm], FIFO watermark level: 6
>[   62.100058] [drm:intel_calculate_wm], FIFO entries required for mode: 9
>[   62.100058] [drm:intel_calculate_wm], FIFO watermark level: 20
>[   62.100058] [drm:i9xx_update_wm], FIFO watermarks - A: 6, B: 20
>[   62.100058] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 6, B: 20, C: 2, SR 1
>[   62.100058] [drm:intel_update_watermarks], plane B (pipe 0) clock: 31500
>[   62.100058] [drm:intel_update_watermarks], plane A (pipe 1) clock: 65000
>[   62.100058] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[   62.100058] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[   62.100058] [drm:intel_calculate_wm], FIFO entries required for mode: 20
>[   62.100058] [drm:intel_calculate_wm], FIFO watermark level: 6
>[   62.100058] [drm:intel_calculate_wm], FIFO entries required for mode: 9
>[   62.100058] [drm:intel_calculate_wm], FIFO watermark level: 20
>[   62.100058] [drm:i9xx_update_wm], FIFO watermarks - A: 6, B: 20
>[   62.100058] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 6, B: 20, C: 2, SR 1
>[   62.148055] [drm:intel_update_watermarks], plane A (pipe 1) clock: 65000
>[   62.148055] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[   62.148055] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[   62.148055] [drm:intel_calculate_wm], FIFO entries required for mode: 20
>[   62.148055] [drm:intel_calculate_wm], FIFO watermark level: 6
>[   62.148055] [drm:intel_calculate_wm], FIFO entries required for mode: 0
>[   62.148055] [drm:intel_calculate_wm], FIFO watermark level: 29
>[   62.148055] [drm:i9xx_update_wm], FIFO watermarks - A: 6, B: 29
>[   62.148055] [drm:i9xx_update_wm], self-refresh entries: 25
>[   62.148055] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 6, B: 29, C: 2, SR 70
>[   72.196007] [drm:intel_update_watermarks], plane B (pipe 0) clock: 31500
>[   72.196007] [drm:intel_update_watermarks], plane A (pipe 1) clock: 65000
>[   72.196007] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[   72.196007] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[   72.196007] [drm:intel_calculate_wm], FIFO entries required for mode: 20
>[   72.196007] [drm:intel_calculate_wm], FIFO watermark level: 6
>[   72.196007] [drm:intel_calculate_wm], FIFO entries required for mode: 9
>[   72.196007] [drm:intel_calculate_wm], FIFO watermark level: 20
>[   72.196007] [drm:i9xx_update_wm], FIFO watermarks - A: 6, B: 20
>[   72.196007] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 6, B: 20, C: 2, SR 1
>[   72.220059] [drm:intel_crtc_mode_set], Mode for pipe A:
>[   72.220059] [drm:drm_mode_debug_printmodeline], Modeline 0:"640x480" 0 31500 640 664 704 832 480 489 491 520 0x10 0xa
>[   72.244059] [drm:intel_pipe_set_base], No FB bound
>[   72.244059] [drm:intel_update_watermarks], plane B (pipe 0) clock: 31500
>[   72.244059] [drm:intel_update_watermarks], plane A (pipe 1) clock: 65000
>[   72.244059] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[   72.244059] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[   72.244059] [drm:intel_calculate_wm], FIFO entries required for mode: 20
>[   72.244059] [drm:intel_calculate_wm], FIFO watermark level: 6
>[   72.244059] [drm:intel_calculate_wm], FIFO entries required for mode: 9
>[   72.244059] [drm:intel_calculate_wm], FIFO watermark level: 20
>[   72.244059] [drm:i9xx_update_wm], FIFO watermarks - A: 6, B: 20
>[   72.244059] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 6, B: 20, C: 2, SR 1
>[   72.244059] [drm:intel_update_watermarks], plane B (pipe 0) clock: 31500
>[   72.244059] [drm:intel_update_watermarks], plane A (pipe 1) clock: 65000
>[   72.244059] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[   72.244059] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[   72.244059] [drm:intel_calculate_wm], FIFO entries required for mode: 20
>[   72.244059] [drm:intel_calculate_wm], FIFO watermark level: 6
>[   72.244059] [drm:intel_calculate_wm], FIFO entries required for mode: 9
>[   72.244059] [drm:intel_calculate_wm], FIFO watermark level: 20
>[   72.244059] [drm:i9xx_update_wm], FIFO watermarks - A: 6, B: 20
>[   72.244059] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 6, B: 20, C: 2, SR 1
>[   72.292060] [drm:intel_update_watermarks], plane A (pipe 1) clock: 65000
>[   72.292060] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[   72.292060] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[   72.292060] [drm:intel_calculate_wm], FIFO entries required for mode: 20
>[   72.292060] [drm:intel_calculate_wm], FIFO watermark level: 6
>[   72.292060] [drm:intel_calculate_wm], FIFO entries required for mode: 0
>[   72.292060] [drm:intel_calculate_wm], FIFO watermark level: 29
>[   72.292060] [drm:i9xx_update_wm], FIFO watermarks - A: 6, B: 29
>[   72.292060] [drm:i9xx_update_wm], self-refresh entries: 25
>[   72.292060] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 6, B: 29, C: 2, SR 70
>[   77.733474] [drm:drm_crtc_helper_set_config], 
>[   77.733474] [drm:drm_crtc_helper_set_config], crtc: f68aa000 4 fb: f6844c38 connectors: f68978e0 num_connectors: 1 (x, y) (0, 0)
>[   77.733474] [drm:drm_crtc_helper_set_config], setting connector 7 crtc to f68aa000
>[   78.219549] [drm:drm_crtc_helper_set_config], 
>[   78.219549] [drm:drm_crtc_helper_set_config], crtc: f68aa000 4 fb: f6844c38 connectors: f68978e0 num_connectors: 1 (x, y) (0, 0)
>[   78.219549] [drm:drm_crtc_helper_set_config], setting connector 7 crtc to f68aa000
>[   82.340007] [drm:intel_update_watermarks], plane B (pipe 0) clock: 31500
>[   82.340007] [drm:intel_update_watermarks], plane A (pipe 1) clock: 65000
>[   82.340007] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[   82.340007] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[   82.340007] [drm:intel_calculate_wm], FIFO entries required for mode: 20
>[   82.340007] [drm:intel_calculate_wm], FIFO watermark level: 6
>[   82.340007] [drm:intel_calculate_wm], FIFO entries required for mode: 9
>[   82.340007] [drm:intel_calculate_wm], FIFO watermark level: 20
>[   82.340007] [drm:i9xx_update_wm], FIFO watermarks - A: 6, B: 20
>[   82.340007] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 6, B: 20, C: 2, SR 1
>[   82.364060] [drm:intel_crtc_mode_set], Mode for pipe A:
>[   82.364060] [drm:drm_mode_debug_printmodeline], Modeline 0:"640x480" 0 31500 640 664 704 832 480 489 491 520 0x10 0xa
>[   82.388058] [drm:intel_pipe_set_base], No FB bound
>[   82.388058] [drm:intel_update_watermarks], plane B (pipe 0) clock: 31500
>[   82.388058] [drm:intel_update_watermarks], plane A (pipe 1) clock: 65000
>[   82.388058] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[   82.388058] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[   82.388058] [drm:intel_calculate_wm], FIFO entries required for mode: 20
>[   82.388058] [drm:intel_calculate_wm], FIFO watermark level: 6
>[   82.388058] [drm:intel_calculate_wm], FIFO entries required for mode: 9
>[   82.388058] [drm:intel_calculate_wm], FIFO watermark level: 20
>[   82.388058] [drm:i9xx_update_wm], FIFO watermarks - A: 6, B: 20
>[   82.388058] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 6, B: 20, C: 2, SR 1
>[   82.388058] [drm:intel_update_watermarks], plane B (pipe 0) clock: 31500
>[   82.388058] [drm:intel_update_watermarks], plane A (pipe 1) clock: 65000
>[   82.388058] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[   82.388058] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[   82.388058] [drm:intel_calculate_wm], FIFO entries required for mode: 20
>[   82.388058] [drm:intel_calculate_wm], FIFO watermark level: 6
>[   82.388058] [drm:intel_calculate_wm], FIFO entries required for mode: 9
>[   82.388058] [drm:intel_calculate_wm], FIFO watermark level: 20
>[   82.388058] [drm:i9xx_update_wm], FIFO watermarks - A: 6, B: 20
>[   82.388058] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 6, B: 20, C: 2, SR 1
>[   82.436057] [drm:intel_update_watermarks], plane A (pipe 1) clock: 65000
>[   82.436057] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[   82.436057] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[   82.436057] [drm:intel_calculate_wm], FIFO entries required for mode: 20
>[   82.436057] [drm:intel_calculate_wm], FIFO watermark level: 6
>[   82.436057] [drm:intel_calculate_wm], FIFO entries required for mode: 0
>[   82.436057] [drm:intel_calculate_wm], FIFO watermark level: 29
>[   82.436057] [drm:i9xx_update_wm], FIFO watermarks - A: 6, B: 29
>[   82.436057] [drm:i9xx_update_wm], self-refresh entries: 25
>[   82.436057] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 6, B: 29, C: 2, SR 70
>[   85.499088] [drm:drm_crtc_helper_set_config], 
>[   85.499088] [drm:drm_crtc_helper_set_config], crtc: f68aa000 4 fb: f6844c38 connectors: f68978e0 num_connectors: 1 (x, y) (0, 0)
>[   85.499088] [drm:drm_crtc_helper_set_config], setting connector 7 crtc to f68aa000
>[   92.484008] [drm:intel_update_watermarks], plane B (pipe 0) clock: 31500
>[   92.484008] [drm:intel_update_watermarks], plane A (pipe 1) clock: 65000
>[   92.484008] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[   92.484008] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[   92.484008] [drm:intel_calculate_wm], FIFO entries required for mode: 20
>[   92.484008] [drm:intel_calculate_wm], FIFO watermark level: 6
>[   92.484008] [drm:intel_calculate_wm], FIFO entries required for mode: 9
>[   92.484008] [drm:intel_calculate_wm], FIFO watermark level: 20
>[   92.484008] [drm:i9xx_update_wm], FIFO watermarks - A: 6, B: 20
>[   92.484008] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 6, B: 20, C: 2, SR 1
>[   92.508061] [drm:intel_crtc_mode_set], Mode for pipe A:
>[   92.508061] [drm:drm_mode_debug_printmodeline], Modeline 0:"640x480" 0 31500 640 664 704 832 480 489 491 520 0x10 0xa
>[   92.532061] [drm:intel_pipe_set_base], No FB bound
>[   92.532061] [drm:intel_update_watermarks], plane B (pipe 0) clock: 31500
>[   92.532061] [drm:intel_update_watermarks], plane A (pipe 1) clock: 65000
>[   92.532061] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[   92.532061] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[   92.532061] [drm:intel_calculate_wm], FIFO entries required for mode: 20
>[   92.532061] [drm:intel_calculate_wm], FIFO watermark level: 6
>[   92.532061] [drm:intel_calculate_wm], FIFO entries required for mode: 9
>[   92.532061] [drm:intel_calculate_wm], FIFO watermark level: 20
>[   92.532061] [drm:i9xx_update_wm], FIFO watermarks - A: 6, B: 20
>[   92.532061] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 6, B: 20, C: 2, SR 1
>[   92.532061] [drm:intel_update_watermarks], plane B (pipe 0) clock: 31500
>[   92.532061] [drm:intel_update_watermarks], plane A (pipe 1) clock: 65000
>[   92.532061] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[   92.532061] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[   92.532061] [drm:intel_calculate_wm], FIFO entries required for mode: 20
>[   92.532061] [drm:intel_calculate_wm], FIFO watermark level: 6
>[   92.532061] [drm:intel_calculate_wm], FIFO entries required for mode: 9
>[   92.532061] [drm:intel_calculate_wm], FIFO watermark level: 20
>[   92.532061] [drm:i9xx_update_wm], FIFO watermarks - A: 6, B: 20
>[   92.532061] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 6, B: 20, C: 2, SR 1
>[   92.580060] [drm:intel_update_watermarks], plane A (pipe 1) clock: 65000
>[   92.580060] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[   92.580060] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[   92.580060] [drm:intel_calculate_wm], FIFO entries required for mode: 20
>[   92.580060] [drm:intel_calculate_wm], FIFO watermark level: 6
>[   92.580060] [drm:intel_calculate_wm], FIFO entries required for mode: 0
>[   92.580060] [drm:intel_calculate_wm], FIFO watermark level: 29
>[   92.580060] [drm:i9xx_update_wm], FIFO watermarks - A: 6, B: 29
>[   92.580060] [drm:i9xx_update_wm], self-refresh entries: 25
>[   92.580060] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 6, B: 29, C: 2, SR 70
>[   95.400372] [drm:drm_crtc_helper_set_config], 
>[   95.400372] [drm:drm_crtc_helper_set_config], crtc: f68aa000 4 fb: f6844c38 connectors: f68978e0 num_connectors: 1 (x, y) (0, 0)
>[   95.400372] [drm:drm_crtc_helper_set_config], setting connector 7 crtc to f68aa000
>[   95.830752] [drm:drm_crtc_helper_set_config], 
>[   95.830752] [drm:drm_crtc_helper_set_config], crtc: f68aa000 4 fb: f6844c38 connectors: f68978e0 num_connectors: 1 (x, y) (0, 0)
>[   95.830752] [drm:drm_crtc_helper_set_config], setting connector 7 crtc to f68aa000
>[   98.581360] [drm:drm_crtc_helper_set_config], 
>[   98.581360] [drm:drm_crtc_helper_set_config], crtc: f68aa000 4 fb: f6844c38 connectors: f68978e0 num_connectors: 1 (x, y) (0, 0)
>[   98.581360] [drm:drm_crtc_helper_set_config], setting connector 7 crtc to f68aa000
>[  102.628007] [drm:intel_update_watermarks], plane B (pipe 0) clock: 31500
>[  102.628007] [drm:intel_update_watermarks], plane A (pipe 1) clock: 65000
>[  102.628007] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[  102.628007] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[  102.628007] [drm:intel_calculate_wm], FIFO entries required for mode: 20
>[  102.628007] [drm:intel_calculate_wm], FIFO watermark level: 6
>[  102.628007] [drm:intel_calculate_wm], FIFO entries required for mode: 9
>[  102.628007] [drm:intel_calculate_wm], FIFO watermark level: 20
>[  102.628007] [drm:i9xx_update_wm], FIFO watermarks - A: 6, B: 20
>[  102.628007] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 6, B: 20, C: 2, SR 1
>[  102.652059] [drm:intel_crtc_mode_set], Mode for pipe A:
>[  102.652059] [drm:drm_mode_debug_printmodeline], Modeline 0:"640x480" 0 31500 640 664 704 832 480 489 491 520 0x10 0xa
>[  102.676056] [drm:intel_pipe_set_base], No FB bound
>[  102.676056] [drm:intel_update_watermarks], plane B (pipe 0) clock: 31500
>[  102.676056] [drm:intel_update_watermarks], plane A (pipe 1) clock: 65000
>[  102.676056] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[  102.676056] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[  102.676056] [drm:intel_calculate_wm], FIFO entries required for mode: 20
>[  102.676056] [drm:intel_calculate_wm], FIFO watermark level: 6
>[  102.676056] [drm:intel_calculate_wm], FIFO entries required for mode: 9
>[  102.676056] [drm:intel_calculate_wm], FIFO watermark level: 20
>[  102.676056] [drm:i9xx_update_wm], FIFO watermarks - A: 6, B: 20
>[  102.676056] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 6, B: 20, C: 2, SR 1
>[  102.676056] [drm:intel_update_watermarks], plane B (pipe 0) clock: 31500
>[  102.676056] [drm:intel_update_watermarks], plane A (pipe 1) clock: 65000
>[  102.676056] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[  102.676056] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[  102.676056] [drm:intel_calculate_wm], FIFO entries required for mode: 20
>[  102.676056] [drm:intel_calculate_wm], FIFO watermark level: 6
>[  102.676056] [drm:intel_calculate_wm], FIFO entries required for mode: 9
>[  102.676056] [drm:intel_calculate_wm], FIFO watermark level: 20
>[  102.676056] [drm:i9xx_update_wm], FIFO watermarks - A: 6, B: 20
>[  102.676056] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 6, B: 20, C: 2, SR 1
>[  102.725890] [drm:intel_update_watermarks], plane A (pipe 1) clock: 65000
>[  102.725890] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[  102.725890] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[  102.725890] [drm:intel_calculate_wm], FIFO entries required for mode: 20
>[  102.725890] [drm:intel_calculate_wm], FIFO watermark level: 6
>[  102.725890] [drm:intel_calculate_wm], FIFO entries required for mode: 0
>[  102.725890] [drm:intel_calculate_wm], FIFO watermark level: 29
>[  102.725890] [drm:i9xx_update_wm], FIFO watermarks - A: 6, B: 29
>[  102.725890] [drm:i9xx_update_wm], self-refresh entries: 25
>[  102.725890] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 6, B: 29, C: 2, SR 70
>[  112.772008] [drm:intel_update_watermarks], plane B (pipe 0) clock: 31500
>[  112.772008] [drm:intel_update_watermarks], plane A (pipe 1) clock: 65000
>[  112.772008] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[  112.772008] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[  112.772008] [drm:intel_calculate_wm], FIFO entries required for mode: 20
>[  112.772008] [drm:intel_calculate_wm], FIFO watermark level: 6
>[  112.772008] [drm:intel_calculate_wm], FIFO entries required for mode: 9
>[  112.772008] [drm:intel_calculate_wm], FIFO watermark level: 20
>[  112.772008] [drm:i9xx_update_wm], FIFO watermarks - A: 6, B: 20
>[  112.772008] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 6, B: 20, C: 2, SR 1
>[  112.796062] [drm:intel_crtc_mode_set], Mode for pipe A:
>[  112.796062] [drm:drm_mode_debug_printmodeline], Modeline 0:"640x480" 0 31500 640 664 704 832 480 489 491 520 0x10 0xa
>[  112.820060] [drm:intel_pipe_set_base], No FB bound
>[  112.820060] [drm:intel_update_watermarks], plane B (pipe 0) clock: 31500
>[  112.820060] [drm:intel_update_watermarks], plane A (pipe 1) clock: 65000
>[  112.820060] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[  112.820060] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[  112.820060] [drm:intel_calculate_wm], FIFO entries required for mode: 20
>[  112.820060] [drm:intel_calculate_wm], FIFO watermark level: 6
>[  112.820060] [drm:intel_calculate_wm], FIFO entries required for mode: 9
>[  112.820060] [drm:intel_calculate_wm], FIFO watermark level: 20
>[  112.820060] [drm:i9xx_update_wm], FIFO watermarks - A: 6, B: 20
>[  112.820060] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 6, B: 20, C: 2, SR 1
>[  112.820060] [drm:intel_update_watermarks], plane B (pipe 0) clock: 31500
>[  112.820060] [drm:intel_update_watermarks], plane A (pipe 1) clock: 65000
>[  112.820060] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[  112.820060] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[  112.820060] [drm:intel_calculate_wm], FIFO entries required for mode: 20
>[  112.820060] [drm:intel_calculate_wm], FIFO watermark level: 6
>[  112.820060] [drm:intel_calculate_wm], FIFO entries required for mode: 9
>[  112.820060] [drm:intel_calculate_wm], FIFO watermark level: 20
>[  112.820060] [drm:i9xx_update_wm], FIFO watermarks - A: 6, B: 20
>[  112.820060] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 6, B: 20, C: 2, SR 1
>[  112.868019] [drm:intel_update_watermarks], plane A (pipe 1) clock: 65000
>[  112.868019] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[  112.868019] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[  112.868019] [drm:intel_calculate_wm], FIFO entries required for mode: 20
>[  112.868019] [drm:intel_calculate_wm], FIFO watermark level: 6
>[  112.868019] [drm:intel_calculate_wm], FIFO entries required for mode: 0
>[  112.868019] [drm:intel_calculate_wm], FIFO watermark level: 29
>[  112.868019] [drm:i9xx_update_wm], FIFO watermarks - A: 6, B: 29
>[  112.868019] [drm:i9xx_update_wm], self-refresh entries: 25
>[  112.868019] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 6, B: 29, C: 2, SR 70
>[  122.916007] [drm:intel_update_watermarks], plane B (pipe 0) clock: 31500
>[  122.916007] [drm:intel_update_watermarks], plane A (pipe 1) clock: 65000
>[  122.916007] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[  122.916007] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[  122.916007] [drm:intel_calculate_wm], FIFO entries required for mode: 20
>[  122.916007] [drm:intel_calculate_wm], FIFO watermark level: 6
>[  122.916007] [drm:intel_calculate_wm], FIFO entries required for mode: 9
>[  122.916007] [drm:intel_calculate_wm], FIFO watermark level: 20
>[  122.916007] [drm:i9xx_update_wm], FIFO watermarks - A: 6, B: 20
>[  122.916007] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 6, B: 20, C: 2, SR 1
>[  122.940062] [drm:intel_crtc_mode_set], Mode for pipe A:
>[  122.940062] [drm:drm_mode_debug_printmodeline], Modeline 0:"640x480" 0 31500 640 664 704 832 480 489 491 520 0x10 0xa
>[  122.964061] [drm:intel_pipe_set_base], No FB bound
>[  122.964061] [drm:intel_update_watermarks], plane B (pipe 0) clock: 31500
>[  122.964061] [drm:intel_update_watermarks], plane A (pipe 1) clock: 65000
>[  122.964061] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[  122.964061] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[  122.964061] [drm:intel_calculate_wm], FIFO entries required for mode: 20
>[  122.964061] [drm:intel_calculate_wm], FIFO watermark level: 6
>[  122.964061] [drm:intel_calculate_wm], FIFO entries required for mode: 9
>[  122.964061] [drm:intel_calculate_wm], FIFO watermark level: 20
>[  122.964061] [drm:i9xx_update_wm], FIFO watermarks - A: 6, B: 20
>[  122.964061] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 6, B: 20, C: 2, SR 1
>[  122.964061] [drm:intel_update_watermarks], plane B (pipe 0) clock: 31500
>[  122.964061] [drm:intel_update_watermarks], plane A (pipe 1) clock: 65000
>[  122.964061] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[  122.964061] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[  122.964061] [drm:intel_calculate_wm], FIFO entries required for mode: 20
>[  122.964061] [drm:intel_calculate_wm], FIFO watermark level: 6
>[  122.964061] [drm:intel_calculate_wm], FIFO entries required for mode: 9
>[  122.964061] [drm:intel_calculate_wm], FIFO watermark level: 20
>[  122.964061] [drm:i9xx_update_wm], FIFO watermarks - A: 6, B: 20
>[  122.964061] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 6, B: 20, C: 2, SR 1
>[  123.012019] [drm:intel_update_watermarks], plane A (pipe 1) clock: 65000
>[  123.012019] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[  123.012019] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[  123.012019] [drm:intel_calculate_wm], FIFO entries required for mode: 20
>[  123.012019] [drm:intel_calculate_wm], FIFO watermark level: 6
>[  123.012019] [drm:intel_calculate_wm], FIFO entries required for mode: 0
>[  123.012019] [drm:intel_calculate_wm], FIFO watermark level: 29
>[  123.012019] [drm:i9xx_update_wm], FIFO watermarks - A: 6, B: 29
>[  123.012019] [drm:i9xx_update_wm], self-refresh entries: 25
>[  123.012019] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 6, B: 29, C: 2, SR 70
>[  133.060008] [drm:intel_update_watermarks], plane B (pipe 0) clock: 31500
>[  133.060008] [drm:intel_update_watermarks], plane A (pipe 1) clock: 65000
>[  133.060008] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[  133.060008] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[  133.060008] [drm:intel_calculate_wm], FIFO entries required for mode: 20
>[  133.060008] [drm:intel_calculate_wm], FIFO watermark level: 6
>[  133.060008] [drm:intel_calculate_wm], FIFO entries required for mode: 9
>[  133.060008] [drm:intel_calculate_wm], FIFO watermark level: 20
>[  133.060008] [drm:i9xx_update_wm], FIFO watermarks - A: 6, B: 20
>[  133.060008] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 6, B: 20, C: 2, SR 1
>[  133.084058] [drm:intel_crtc_mode_set], Mode for pipe A:
>[  133.084058] [drm:drm_mode_debug_printmodeline], Modeline 0:"640x480" 0 31500 640 664 704 832 480 489 491 520 0x10 0xa
>[  133.108058] [drm:intel_pipe_set_base], No FB bound
>[  133.108058] [drm:intel_update_watermarks], plane B (pipe 0) clock: 31500
>[  133.108058] [drm:intel_update_watermarks], plane A (pipe 1) clock: 65000
>[  133.108058] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[  133.108058] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[  133.108058] [drm:intel_calculate_wm], FIFO entries required for mode: 20
>[  133.108058] [drm:intel_calculate_wm], FIFO watermark level: 6
>[  133.108058] [drm:intel_calculate_wm], FIFO entries required for mode: 9
>[  133.108058] [drm:intel_calculate_wm], FIFO watermark level: 20
>[  133.108058] [drm:i9xx_update_wm], FIFO watermarks - A: 6, B: 20
>[  133.108058] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 6, B: 20, C: 2, SR 1
>[  133.108058] [drm:intel_update_watermarks], plane B (pipe 0) clock: 31500
>[  133.108058] [drm:intel_update_watermarks], plane A (pipe 1) clock: 65000
>[  133.108058] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[  133.108058] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[  133.108058] [drm:intel_calculate_wm], FIFO entries required for mode: 20
>[  133.108058] [drm:intel_calculate_wm], FIFO watermark level: 6
>[  133.108058] [drm:intel_calculate_wm], FIFO entries required for mode: 9
>[  133.108058] [drm:intel_calculate_wm], FIFO watermark level: 20
>[  133.108058] [drm:i9xx_update_wm], FIFO watermarks - A: 6, B: 20
>[  133.108058] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 6, B: 20, C: 2, SR 1
>[  133.156056] [drm:intel_update_watermarks], plane A (pipe 1) clock: 65000
>[  133.156056] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[  133.156056] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[  133.156056] [drm:intel_calculate_wm], FIFO entries required for mode: 20
>[  133.156056] [drm:intel_calculate_wm], FIFO watermark level: 6
>[  133.156056] [drm:intel_calculate_wm], FIFO entries required for mode: 0
>[  133.156056] [drm:intel_calculate_wm], FIFO watermark level: 29
>[  133.156056] [drm:i9xx_update_wm], FIFO watermarks - A: 6, B: 29
>[  133.156056] [drm:i9xx_update_wm], self-refresh entries: 25
>[  133.156056] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 6, B: 29, C: 2, SR 70
>[  143.204007] [drm:intel_update_watermarks], plane B (pipe 0) clock: 31500
>[  143.204007] [drm:intel_update_watermarks], plane A (pipe 1) clock: 65000
>[  143.204007] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[  143.204007] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[  143.204007] [drm:intel_calculate_wm], FIFO entries required for mode: 20
>[  143.204007] [drm:intel_calculate_wm], FIFO watermark level: 6
>[  143.204007] [drm:intel_calculate_wm], FIFO entries required for mode: 9
>[  143.204007] [drm:intel_calculate_wm], FIFO watermark level: 20
>[  143.204007] [drm:i9xx_update_wm], FIFO watermarks - A: 6, B: 20
>[  143.204007] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 6, B: 20, C: 2, SR 1
>[  143.228060] [drm:intel_crtc_mode_set], Mode for pipe A:
>[  143.228060] [drm:drm_mode_debug_printmodeline], Modeline 0:"640x480" 0 31500 640 664 704 832 480 489 491 520 0x10 0xa
>[  143.252060] [drm:intel_pipe_set_base], No FB bound
>[  143.252060] [drm:intel_update_watermarks], plane B (pipe 0) clock: 31500
>[  143.252060] [drm:intel_update_watermarks], plane A (pipe 1) clock: 65000
>[  143.252060] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[  143.252060] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[  143.252060] [drm:intel_calculate_wm], FIFO entries required for mode: 20
>[  143.252060] [drm:intel_calculate_wm], FIFO watermark level: 6
>[  143.252060] [drm:intel_calculate_wm], FIFO entries required for mode: 9
>[  143.252060] [drm:intel_calculate_wm], FIFO watermark level: 20
>[  143.252060] [drm:i9xx_update_wm], FIFO watermarks - A: 6, B: 20
>[  143.252060] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 6, B: 20, C: 2, SR 1
>[  143.252060] [drm:intel_update_watermarks], plane B (pipe 0) clock: 31500
>[  143.252060] [drm:intel_update_watermarks], plane A (pipe 1) clock: 65000
>[  143.252060] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[  143.252060] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[  143.252060] [drm:intel_calculate_wm], FIFO entries required for mode: 20
>[  143.252060] [drm:intel_calculate_wm], FIFO watermark level: 6
>[  143.252060] [drm:intel_calculate_wm], FIFO entries required for mode: 9
>[  143.252060] [drm:intel_calculate_wm], FIFO watermark level: 20
>[  143.252060] [drm:i9xx_update_wm], FIFO watermarks - A: 6, B: 20
>[  143.252060] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 6, B: 20, C: 2, SR 1
>[  143.300058] [drm:intel_update_watermarks], plane A (pipe 1) clock: 65000
>[  143.300058] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[  143.300058] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[  143.300058] [drm:intel_calculate_wm], FIFO entries required for mode: 20
>[  143.300058] [drm:intel_calculate_wm], FIFO watermark level: 6
>[  143.300058] [drm:intel_calculate_wm], FIFO entries required for mode: 0
>[  143.300058] [drm:intel_calculate_wm], FIFO watermark level: 29
>[  143.300058] [drm:i9xx_update_wm], FIFO watermarks - A: 6, B: 29
>[  143.300058] [drm:i9xx_update_wm], self-refresh entries: 25
>[  143.300058] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 6, B: 29, C: 2, SR 70
>[  148.452947] [drm:drm_crtc_helper_set_config], 
>[  148.452947] [drm:drm_crtc_helper_set_config], crtc: f68aa000 4 fb: f6844c38 connectors: f68978e0 num_connectors: 1 (x, y) (0, 0)
>[  148.452947] [drm:drm_crtc_helper_set_config], setting connector 7 crtc to f68aa000
>[  153.348007] [drm:intel_update_watermarks], plane B (pipe 0) clock: 31500
>[  153.348007] [drm:intel_update_watermarks], plane A (pipe 1) clock: 65000
>[  153.348007] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[  153.348007] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[  153.348007] [drm:intel_calculate_wm], FIFO entries required for mode: 20
>[  153.348007] [drm:intel_calculate_wm], FIFO watermark level: 6
>[  153.348007] [drm:intel_calculate_wm], FIFO entries required for mode: 9
>[  153.348007] [drm:intel_calculate_wm], FIFO watermark level: 20
>[  153.348007] [drm:i9xx_update_wm], FIFO watermarks - A: 6, B: 20
>[  153.348007] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 6, B: 20, C: 2, SR 1
>[  153.372062] [drm:intel_crtc_mode_set], Mode for pipe A:
>[  153.372062] [drm:drm_mode_debug_printmodeline], Modeline 0:"640x480" 0 31500 640 664 704 832 480 489 491 520 0x10 0xa
>[  153.396061] [drm:intel_pipe_set_base], No FB bound
>[  153.396061] [drm:intel_update_watermarks], plane B (pipe 0) clock: 31500
>[  153.396061] [drm:intel_update_watermarks], plane A (pipe 1) clock: 65000
>[  153.396061] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[  153.396061] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[  153.396061] [drm:intel_calculate_wm], FIFO entries required for mode: 20
>[  153.396061] [drm:intel_calculate_wm], FIFO watermark level: 6
>[  153.396061] [drm:intel_calculate_wm], FIFO entries required for mode: 9
>[  153.396061] [drm:intel_calculate_wm], FIFO watermark level: 20
>[  153.396061] [drm:i9xx_update_wm], FIFO watermarks - A: 6, B: 20
>[  153.396061] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 6, B: 20, C: 2, SR 1
>[  153.396061] [drm:intel_update_watermarks], plane B (pipe 0) clock: 31500
>[  153.396061] [drm:intel_update_watermarks], plane A (pipe 1) clock: 65000
>[  153.396061] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[  153.396061] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[  153.396061] [drm:intel_calculate_wm], FIFO entries required for mode: 20
>[  153.396061] [drm:intel_calculate_wm], FIFO watermark level: 6
>[  153.396061] [drm:intel_calculate_wm], FIFO entries required for mode: 9
>[  153.396061] [drm:intel_calculate_wm], FIFO watermark level: 20
>[  153.396061] [drm:i9xx_update_wm], FIFO watermarks - A: 6, B: 20
>[  153.396061] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 6, B: 20, C: 2, SR 1
>[  153.444058] [drm:intel_update_watermarks], plane A (pipe 1) clock: 65000
>[  153.444058] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[  153.444058] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[  153.444058] [drm:intel_calculate_wm], FIFO entries required for mode: 20
>[  153.444058] [drm:intel_calculate_wm], FIFO watermark level: 6
>[  153.444058] [drm:intel_calculate_wm], FIFO entries required for mode: 0
>[  153.444058] [drm:intel_calculate_wm], FIFO watermark level: 29
>[  153.444058] [drm:i9xx_update_wm], FIFO watermarks - A: 6, B: 29
>[  153.444058] [drm:i9xx_update_wm], self-refresh entries: 25
>[  153.444058] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 6, B: 29, C: 2, SR 70
>[  155.603360] [drm:drm_crtc_helper_set_config], 
>[  155.603360] [drm:drm_crtc_helper_set_config], crtc: f68aa000 4 fb: f6844c38 connectors: f68978e0 num_connectors: 1 (x, y) (0, 0)
>[  155.603360] [drm:drm_crtc_helper_set_config], setting connector 7 crtc to f68aa000
>[  163.492010] [drm:intel_update_watermarks], plane B (pipe 0) clock: 31500
>[  163.492010] [drm:intel_update_watermarks], plane A (pipe 1) clock: 65000
>[  163.492010] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[  163.492010] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[  163.492010] [drm:intel_calculate_wm], FIFO entries required for mode: 20
>[  163.492010] [drm:intel_calculate_wm], FIFO watermark level: 6
>[  163.492010] [drm:intel_calculate_wm], FIFO entries required for mode: 9
>[  163.492010] [drm:intel_calculate_wm], FIFO watermark level: 20
>[  163.492010] [drm:i9xx_update_wm], FIFO watermarks - A: 6, B: 20
>[  163.492010] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 6, B: 20, C: 2, SR 1
>[  163.518907] [drm:intel_crtc_mode_set], Mode for pipe A:
>[  163.518907] [drm:drm_mode_debug_printmodeline], Modeline 0:"640x480" 0 31500 640 664 704 832 480 489 491 520 0x10 0xa
>[  163.540059] [drm:intel_pipe_set_base], No FB bound
>[  163.540059] [drm:intel_update_watermarks], plane B (pipe 0) clock: 31500
>[  163.540059] [drm:intel_update_watermarks], plane A (pipe 1) clock: 65000
>[  163.540059] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[  163.540059] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[  163.540059] [drm:intel_calculate_wm], FIFO entries required for mode: 20
>[  163.540059] [drm:intel_calculate_wm], FIFO watermark level: 6
>[  163.540059] [drm:intel_calculate_wm], FIFO entries required for mode: 9
>[  163.540059] [drm:intel_calculate_wm], FIFO watermark level: 20
>[  163.540059] [drm:i9xx_update_wm], FIFO watermarks - A: 6, B: 20
>[  163.540059] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 6, B: 20, C: 2, SR 1
>[  163.540059] [drm:intel_update_watermarks], plane B (pipe 0) clock: 31500
>[  163.540059] [drm:intel_update_watermarks], plane A (pipe 1) clock: 65000
>[  163.540059] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[  163.540059] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[  163.540059] [drm:intel_calculate_wm], FIFO entries required for mode: 20
>[  163.540059] [drm:intel_calculate_wm], FIFO watermark level: 6
>[  163.540059] [drm:intel_calculate_wm], FIFO entries required for mode: 9
>[  163.540059] [drm:intel_calculate_wm], FIFO watermark level: 20
>[  163.540059] [drm:i9xx_update_wm], FIFO watermarks - A: 6, B: 20
>[  163.540059] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 6, B: 20, C: 2, SR 1
>[  163.588060] [drm:intel_update_watermarks], plane A (pipe 1) clock: 65000
>[  163.588060] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[  163.588060] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[  163.588060] [drm:intel_calculate_wm], FIFO entries required for mode: 20
>[  163.588060] [drm:intel_calculate_wm], FIFO watermark level: 6
>[  163.588060] [drm:intel_calculate_wm], FIFO entries required for mode: 0
>[  163.588060] [drm:intel_calculate_wm], FIFO watermark level: 29
>[  163.588060] [drm:i9xx_update_wm], FIFO watermarks - A: 6, B: 29
>[  163.588060] [drm:i9xx_update_wm], self-refresh entries: 25
>[  163.588060] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 6, B: 29, C: 2, SR 70
>[  173.636007] [drm:intel_update_watermarks], plane B (pipe 0) clock: 31500
>[  173.636007] [drm:intel_update_watermarks], plane A (pipe 1) clock: 65000
>[  173.636007] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[  173.636007] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[  173.636007] [drm:intel_calculate_wm], FIFO entries required for mode: 20
>[  173.636007] [drm:intel_calculate_wm], FIFO watermark level: 6
>[  173.636007] [drm:intel_calculate_wm], FIFO entries required for mode: 9
>[  173.636007] [drm:intel_calculate_wm], FIFO watermark level: 20
>[  173.636007] [drm:i9xx_update_wm], FIFO watermarks - A: 6, B: 20
>[  173.636007] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 6, B: 20, C: 2, SR 1
>[  173.660009] [drm:intel_crtc_mode_set], Mode for pipe A:
>[  173.660009] [drm:drm_mode_debug_printmodeline], Modeline 0:"640x480" 0 31500 640 664 704 832 480 489 491 520 0x10 0xa
>[  173.684007] [drm:intel_pipe_set_base], No FB bound
>[  173.684007] [drm:intel_update_watermarks], plane B (pipe 0) clock: 31500
>[  173.684007] [drm:intel_update_watermarks], plane A (pipe 1) clock: 65000
>[  173.684007] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[  173.684007] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[  173.684007] [drm:intel_calculate_wm], FIFO entries required for mode: 20
>[  173.684007] [drm:intel_calculate_wm], FIFO watermark level: 6
>[  173.684007] [drm:intel_calculate_wm], FIFO entries required for mode: 9
>[  173.684007] [drm:intel_calculate_wm], FIFO watermark level: 20
>[  173.684007] [drm:i9xx_update_wm], FIFO watermarks - A: 6, B: 20
>[  173.684007] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 6, B: 20, C: 2, SR 1
>[  173.684007] [drm:intel_update_watermarks], plane B (pipe 0) clock: 31500
>[  173.684007] [drm:intel_update_watermarks], plane A (pipe 1) clock: 65000
>[  173.684007] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[  173.684007] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[  173.684007] [drm:intel_calculate_wm], FIFO entries required for mode: 20
>[  173.684007] [drm:intel_calculate_wm], FIFO watermark level: 6
>[  173.684007] [drm:intel_calculate_wm], FIFO entries required for mode: 9
>[  173.684007] [drm:intel_calculate_wm], FIFO watermark level: 20
>[  173.684007] [drm:i9xx_update_wm], FIFO watermarks - A: 6, B: 20
>[  173.684007] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 6, B: 20, C: 2, SR 1
>[  173.732007] [drm:intel_update_watermarks], plane A (pipe 1) clock: 65000
>[  173.732007] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[  173.732007] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[  173.732007] [drm:intel_calculate_wm], FIFO entries required for mode: 20
>[  173.732007] [drm:intel_calculate_wm], FIFO watermark level: 6
>[  173.732007] [drm:intel_calculate_wm], FIFO entries required for mode: 0
>[  173.732007] [drm:intel_calculate_wm], FIFO watermark level: 29
>[  173.732007] [drm:i9xx_update_wm], FIFO watermarks - A: 6, B: 29
>[  173.732007] [drm:i9xx_update_wm], self-refresh entries: 25
>[  173.732007] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 6, B: 29, C: 2, SR 70
>[  179.000010] [drm:drm_crtc_helper_set_config], 
>[  179.000010] [drm:drm_crtc_helper_set_config], crtc: f68aa000 4 fb: f6844c38 connectors: f68978e0 num_connectors: 1 (x, y) (0, 0)
>[  179.000010] [drm:drm_crtc_helper_set_config], setting connector 7 crtc to f68aa000
>[  179.956613] [drm:drm_crtc_helper_set_config], 
>[  179.956613] [drm:drm_crtc_helper_set_config], crtc: f6874000 3 fb: f6844c38 connectors: f6897900 num_connectors: 0 (x, y) (0, 0)
>[  179.956613] [drm:drm_crtc_helper_set_config], crtc has no fb, full mode set
>[  179.956613] [drm:drm_crtc_helper_set_config], setting connector 7 crtc to f68aa000
>[  179.956613] [drm:intel_update_watermarks], plane A (pipe 1) clock: 65000
>[  179.956613] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[  179.956613] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[  179.956613] [drm:intel_calculate_wm], FIFO entries required for mode: 20
>[  179.956613] [drm:intel_calculate_wm], FIFO watermark level: 6
>[  179.956613] [drm:intel_calculate_wm], FIFO entries required for mode: 0
>[  179.956613] [drm:intel_calculate_wm], FIFO watermark level: 29
>[  179.956613] [drm:i9xx_update_wm], FIFO watermarks - A: 6, B: 29
>[  179.956613] [drm:i9xx_update_wm], self-refresh entries: 25
>[  179.956613] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 6, B: 29, C: 2, SR 70
>[  179.980056] [drm:drm_crtc_helper_set_config], 
>[  179.980056] [drm:drm_crtc_helper_set_config], crtc: f68aa000 4 fb: f6844c38 connectors: f68978e0 num_connectors: 1 (x, y) (0, 0)
>[  179.980056] [drm:drm_crtc_helper_set_config], setting connector 7 crtc to f68aa000
>[  179.980056] [drm:drm_mode_getresources], Counted 2 3 3
>[  179.980056] [drm:drm_mode_getresources], Counted 2 3 3
>[  179.980056] [drm:drm_mode_getconnector], connector id 5:
>[  179.980056] [drm:drm_helper_probe_single_connector_modes], VGA-1
>[  179.984056] [drm:intel_update_watermarks], plane B (pipe 0) clock: 31500
>[  179.984056] [drm:intel_update_watermarks], plane A (pipe 1) clock: 65000
>[  179.984056] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[  179.984056] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[  179.984056] [drm:intel_calculate_wm], FIFO entries required for mode: 20
>[  179.984056] [drm:intel_calculate_wm], FIFO watermark level: 6
>[  179.984056] [drm:intel_calculate_wm], FIFO entries required for mode: 9
>[  179.984056] [drm:intel_calculate_wm], FIFO watermark level: 20
>[  179.984056] [drm:i9xx_update_wm], FIFO watermarks - A: 6, B: 20
>[  179.984056] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 6, B: 20, C: 2, SR 1
>[  180.008059] [drm:intel_crtc_mode_set], Mode for pipe A:
>[  180.008059] [drm:drm_mode_debug_printmodeline], Modeline 0:"640x480" 0 31500 640 664 704 832 480 489 491 520 0x10 0xa
>[  180.032062] [drm:intel_pipe_set_base], No FB bound
>[  180.032062] [drm:intel_update_watermarks], plane B (pipe 0) clock: 31500
>[  180.032062] [drm:intel_update_watermarks], plane A (pipe 1) clock: 65000
>[  180.032062] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[  180.032062] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[  180.032062] [drm:intel_calculate_wm], FIFO entries required for mode: 20
>[  180.032062] [drm:intel_calculate_wm], FIFO watermark level: 6
>[  180.032062] [drm:intel_calculate_wm], FIFO entries required for mode: 9
>[  180.032062] [drm:intel_calculate_wm], FIFO watermark level: 20
>[  180.032062] [drm:i9xx_update_wm], FIFO watermarks - A: 6, B: 20
>[  180.032062] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 6, B: 20, C: 2, SR 1
>[  180.032062] [drm:intel_update_watermarks], plane B (pipe 0) clock: 31500
>[  180.032062] [drm:intel_update_watermarks], plane A (pipe 1) clock: 65000
>[  180.032062] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[  180.032062] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[  180.032062] [drm:intel_calculate_wm], FIFO entries required for mode: 20
>[  180.032062] [drm:intel_calculate_wm], FIFO watermark level: 6
>[  180.032062] [drm:intel_calculate_wm], FIFO entries required for mode: 9
>[  180.032062] [drm:intel_calculate_wm], FIFO watermark level: 20
>[  180.032062] [drm:i9xx_update_wm], FIFO watermarks - A: 6, B: 20
>[  180.032062] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 6, B: 20, C: 2, SR 1
>[  180.080060] [drm:intel_update_watermarks], plane A (pipe 1) clock: 65000
>[  180.080060] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[  180.080060] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[  180.080060] [drm:intel_calculate_wm], FIFO entries required for mode: 20
>[  180.080060] [drm:intel_calculate_wm], FIFO watermark level: 6
>[  180.080060] [drm:intel_calculate_wm], FIFO entries required for mode: 0
>[  180.080060] [drm:intel_calculate_wm], FIFO watermark level: 29
>[  180.080060] [drm:i9xx_update_wm], FIFO watermarks - A: 6, B: 29
>[  180.080060] [drm:i9xx_update_wm], self-refresh entries: 25
>[  180.080060] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 6, B: 29, C: 2, SR 70
>[  180.104062] [drm:drm_helper_probe_single_connector_modes], VGA-1 is disconnected
>[  180.104062] [drm:drm_mode_getconnector], connector id 5:
>[  180.104062] [drm:drm_helper_probe_single_connector_modes], VGA-1
>[  180.108062] [drm:intel_update_watermarks], plane B (pipe 0) clock: 31500
>[  180.108062] [drm:intel_update_watermarks], plane A (pipe 1) clock: 65000
>[  180.108062] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[  180.108062] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[  180.108062] [drm:intel_calculate_wm], FIFO entries required for mode: 20
>[  180.108062] [drm:intel_calculate_wm], FIFO watermark level: 6
>[  180.108062] [drm:intel_calculate_wm], FIFO entries required for mode: 9
>[  180.108062] [drm:intel_calculate_wm], FIFO watermark level: 20
>[  180.108062] [drm:i9xx_update_wm], FIFO watermarks - A: 6, B: 20
>[  180.108062] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 6, B: 20, C: 2, SR 1
>[  180.132061] [drm:intel_crtc_mode_set], Mode for pipe A:
>[  180.132061] [drm:drm_mode_debug_printmodeline], Modeline 0:"640x480" 0 31500 640 664 704 832 480 489 491 520 0x10 0xa
>[  180.156019] [drm:intel_pipe_set_base], No FB bound
>[  180.156019] [drm:intel_update_watermarks], plane B (pipe 0) clock: 31500
>[  180.156019] [drm:intel_update_watermarks], plane A (pipe 1) clock: 65000
>[  180.156019] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[  180.156019] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[  180.156019] [drm:intel_calculate_wm], FIFO entries required for mode: 20
>[  180.156019] [drm:intel_calculate_wm], FIFO watermark level: 6
>[  180.156019] [drm:intel_calculate_wm], FIFO entries required for mode: 9
>[  180.156019] [drm:intel_calculate_wm], FIFO watermark level: 20
>[  180.156019] [drm:i9xx_update_wm], FIFO watermarks - A: 6, B: 20
>[  180.156019] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 6, B: 20, C: 2, SR 1
>[  180.156019] [drm:intel_update_watermarks], plane B (pipe 0) clock: 31500
>[  180.156019] [drm:intel_update_watermarks], plane A (pipe 1) clock: 65000
>[  180.156019] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[  180.156019] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[  180.156019] [drm:intel_calculate_wm], FIFO entries required for mode: 20
>[  180.156019] [drm:intel_calculate_wm], FIFO watermark level: 6
>[  180.156019] [drm:intel_calculate_wm], FIFO entries required for mode: 9
>[  180.156019] [drm:intel_calculate_wm], FIFO watermark level: 20
>[  180.156019] [drm:i9xx_update_wm], FIFO watermarks - A: 6, B: 20
>[  180.156019] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 6, B: 20, C: 2, SR 1
>[  180.204059] [drm:intel_update_watermarks], plane A (pipe 1) clock: 65000
>[  180.204059] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[  180.204059] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[  180.204059] [drm:intel_calculate_wm], FIFO entries required for mode: 20
>[  180.204059] [drm:intel_calculate_wm], FIFO watermark level: 6
>[  180.204059] [drm:intel_calculate_wm], FIFO entries required for mode: 0
>[  180.204059] [drm:intel_calculate_wm], FIFO watermark level: 29
>[  180.204059] [drm:i9xx_update_wm], FIFO watermarks - A: 6, B: 29
>[  180.204059] [drm:i9xx_update_wm], self-refresh entries: 25
>[  180.204059] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 6, B: 29, C: 2, SR 70
>[  180.228061] [drm:drm_helper_probe_single_connector_modes], VGA-1 is disconnected
>[  180.228061] [drm:drm_mode_getconnector], connector id 7:
>[  180.228061] [drm:drm_helper_probe_single_connector_modes], LVDS-1
>[  180.228061] [drm:drm_helper_probe_single_connector_modes], Probed modes for LVDS-1
>[  180.228061] [drm:drm_mode_debug_printmodeline], Modeline 26:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x8 0xa
>[  180.228061] [drm:drm_mode_getconnector], connector id 7:
>[  180.228061] [drm:drm_mode_getconnector], connector id 11:
>[  180.228061] [drm:drm_helper_probe_single_connector_modes], SVIDEO-1
>[  180.228061] [drm:intel_update_watermarks], plane B (pipe 0) clock: 107520
>[  180.228061] [drm:intel_update_watermarks], plane A (pipe 1) clock: 65000
>[  180.228061] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[  180.228061] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[  180.228061] [drm:intel_calculate_wm], FIFO entries required for mode: 20
>[  180.228061] [drm:intel_calculate_wm], FIFO watermark level: 6
>[  180.228061] [drm:intel_calculate_wm], FIFO entries required for mode: 33
>[  180.228061] [drm:intel_calculate_wm], FIFO watermark level: -4
>[  180.228061] [drm:i9xx_update_wm], FIFO watermarks - A: 6, B: 1
>[  180.228061] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 6, B: 1, C: 2, SR 1
>[  180.252058] [drm:intel_crtc_mode_set], Mode for pipe A:
>[  180.252058] [drm:drm_mode_debug_printmodeline], Modeline 0:"NTSC 480i" 0 107520 1280 1368 1496 1712 1024 1027 1034 1104 0x40 0x0
>[  180.276057] [drm:intel_pipe_set_base], No FB bound
>[  180.276057] [drm:intel_update_watermarks], plane B (pipe 0) clock: 107520
>[  180.276057] [drm:intel_update_watermarks], plane A (pipe 1) clock: 65000
>[  180.276057] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[  180.276057] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[  180.276057] [drm:intel_calculate_wm], FIFO entries required for mode: 20
>[  180.276057] [drm:intel_calculate_wm], FIFO watermark level: 6
>[  180.276057] [drm:intel_calculate_wm], FIFO entries required for mode: 33
>[  180.276057] [drm:intel_calculate_wm], FIFO watermark level: -4
>[  180.276057] [drm:i9xx_update_wm], FIFO watermarks - A: 6, B: 1
>[  180.276057] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 6, B: 1, C: 2, SR 1
>[  180.300060] [drm:intel_update_watermarks], plane B (pipe 0) clock: 107520
>[  180.300060] [drm:intel_update_watermarks], plane A (pipe 1) clock: 65000
>[  180.300060] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[  180.300060] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[  180.300060] [drm:intel_calculate_wm], FIFO entries required for mode: 20
>[  180.300060] [drm:intel_calculate_wm], FIFO watermark level: 6
>[  180.300060] [drm:intel_calculate_wm], FIFO entries required for mode: 33
>[  180.300060] [drm:intel_calculate_wm], FIFO watermark level: -4
>[  180.300060] [drm:i9xx_update_wm], FIFO watermarks - A: 6, B: 1
>[  180.300060] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 6, B: 1, C: 2, SR 1
>[  180.372057] [drm:intel_tv_detect_type], No TV connection detected
>[  180.372057] [drm:intel_update_watermarks], plane A (pipe 1) clock: 65000
>[  180.372057] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[  180.372057] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[  180.372057] [drm:intel_calculate_wm], FIFO entries required for mode: 20
>[  180.372057] [drm:intel_calculate_wm], FIFO watermark level: 6
>[  180.372057] [drm:intel_calculate_wm], FIFO entries required for mode: 0
>[  180.372057] [drm:intel_calculate_wm], FIFO watermark level: 29
>[  180.372057] [drm:i9xx_update_wm], FIFO watermarks - A: 6, B: 29
>[  180.372057] [drm:i9xx_update_wm], self-refresh entries: 25
>[  180.372057] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 6, B: 29, C: 2, SR 70
>[  180.396059] [drm:drm_helper_probe_single_connector_modes], SVIDEO-1 is disconnected
>[  180.396059] [drm:drm_mode_getconnector], connector id 11:
>[  180.396059] [drm:drm_helper_probe_single_connector_modes], SVIDEO-1
>[  180.396059] [drm:intel_update_watermarks], plane B (pipe 0) clock: 107520
>[  180.396059] [drm:intel_update_watermarks], plane A (pipe 1) clock: 65000
>[  180.396059] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[  180.396059] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[  180.396059] [drm:intel_calculate_wm], FIFO entries required for mode: 20
>[  180.396059] [drm:intel_calculate_wm], FIFO watermark level: 6
>[  180.396059] [drm:intel_calculate_wm], FIFO entries required for mode: 33
>[  180.396059] [drm:intel_calculate_wm], FIFO watermark level: -4
>[  180.396059] [drm:i9xx_update_wm], FIFO watermarks - A: 6, B: 1
>[  180.396059] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 6, B: 1, C: 2, SR 1
>[  180.420059] [drm:intel_crtc_mode_set], Mode for pipe A:
>[  180.420059] [drm:drm_mode_debug_printmodeline], Modeline 0:"NTSC 480i" 0 107520 1280 1368 1496 1712 1024 1027 1034 1104 0x40 0x0
>[  180.444058] [drm:intel_pipe_set_base], No FB bound
>[  180.444058] [drm:intel_update_watermarks], plane B (pipe 0) clock: 107520
>[  180.444058] [drm:intel_update_watermarks], plane A (pipe 1) clock: 65000
>[  180.444058] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[  180.444058] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[  180.444058] [drm:intel_calculate_wm], FIFO entries required for mode: 20
>[  180.444058] [drm:intel_calculate_wm], FIFO watermark level: 6
>[  180.444058] [drm:intel_calculate_wm], FIFO entries required for mode: 33
>[  180.444058] [drm:intel_calculate_wm], FIFO watermark level: -4
>[  180.444058] [drm:i9xx_update_wm], FIFO watermarks - A: 6, B: 1
>[  180.444058] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 6, B: 1, C: 2, SR 1
>[  180.468021] [drm:intel_update_watermarks], plane B (pipe 0) clock: 107520
>[  180.468021] [drm:intel_update_watermarks], plane A (pipe 1) clock: 65000
>[  180.468021] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[  180.468021] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[  180.468021] [drm:intel_calculate_wm], FIFO entries required for mode: 20
>[  180.468021] [drm:intel_calculate_wm], FIFO watermark level: 6
>[  180.468021] [drm:intel_calculate_wm], FIFO entries required for mode: 33
>[  180.468021] [drm:intel_calculate_wm], FIFO watermark level: -4
>[  180.468021] [drm:i9xx_update_wm], FIFO watermarks - A: 6, B: 1
>[  180.468021] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 6, B: 1, C: 2, SR 1
>[  180.540059] [drm:intel_tv_detect_type], No TV connection detected
>[  180.540059] [drm:intel_update_watermarks], plane A (pipe 1) clock: 65000
>[  180.540059] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[  180.540059] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[  180.540059] [drm:intel_calculate_wm], FIFO entries required for mode: 20
>[  180.540059] [drm:intel_calculate_wm], FIFO watermark level: 6
>[  180.540059] [drm:intel_calculate_wm], FIFO entries required for mode: 0
>[  180.540059] [drm:intel_calculate_wm], FIFO watermark level: 29
>[  180.540059] [drm:i9xx_update_wm], FIFO watermarks - A: 6, B: 29
>[  180.540059] [drm:i9xx_update_wm], self-refresh entries: 25
>[  180.540059] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 6, B: 29, C: 2, SR 70
>[  180.564062] [drm:drm_helper_probe_single_connector_modes], SVIDEO-1 is disconnected
>[  180.564062] [drm:drm_mode_getconnector], connector id 5:
>[  180.564062] [drm:drm_helper_probe_single_connector_modes], VGA-1
>[  180.568062] [drm:intel_update_watermarks], plane B (pipe 0) clock: 31500
>[  180.568062] [drm:intel_update_watermarks], plane A (pipe 1) clock: 65000
>[  180.568062] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[  180.568062] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[  180.568062] [drm:intel_calculate_wm], FIFO entries required for mode: 20
>[  180.568062] [drm:intel_calculate_wm], FIFO watermark level: 6
>[  180.568062] [drm:intel_calculate_wm], FIFO entries required for mode: 9
>[  180.568062] [drm:intel_calculate_wm], FIFO watermark level: 20
>[  180.568062] [drm:i9xx_update_wm], FIFO watermarks - A: 6, B: 20
>[  180.568062] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 6, B: 20, C: 2, SR 1
>[  180.592062] [drm:intel_crtc_mode_set], Mode for pipe A:
>[  180.592062] [drm:drm_mode_debug_printmodeline], Modeline 0:"640x480" 0 31500 640 664 704 832 480 489 491 520 0x10 0xa
>[  180.616061] [drm:intel_pipe_set_base], No FB bound
>[  180.616061] [drm:intel_update_watermarks], plane B (pipe 0) clock: 31500
>[  180.616061] [drm:intel_update_watermarks], plane A (pipe 1) clock: 65000
>[  180.616061] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[  180.616061] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[  180.616061] [drm:intel_calculate_wm], FIFO entries required for mode: 20
>[  180.616061] [drm:intel_calculate_wm], FIFO watermark level: 6
>[  180.616061] [drm:intel_calculate_wm], FIFO entries required for mode: 9
>[  180.616061] [drm:intel_calculate_wm], FIFO watermark level: 20
>[  180.616061] [drm:i9xx_update_wm], FIFO watermarks - A: 6, B: 20
>[  180.616061] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 6, B: 20, C: 2, SR 1
>[  180.616061] [drm:intel_update_watermarks], plane B (pipe 0) clock: 31500
>[  180.616061] [drm:intel_update_watermarks], plane A (pipe 1) clock: 65000
>[  180.616061] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[  180.616061] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[  180.616061] [drm:intel_calculate_wm], FIFO entries required for mode: 20
>[  180.616061] [drm:intel_calculate_wm], FIFO watermark level: 6
>[  180.616061] [drm:intel_calculate_wm], FIFO entries required for mode: 9
>[  180.616061] [drm:intel_calculate_wm], FIFO watermark level: 20
>[  180.616061] [drm:i9xx_update_wm], FIFO watermarks - A: 6, B: 20
>[  180.616061] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 6, B: 20, C: 2, SR 1
>[  180.664060] [drm:intel_update_watermarks], plane A (pipe 1) clock: 65000
>[  180.664060] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[  180.664060] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[  180.664060] [drm:intel_calculate_wm], FIFO entries required for mode: 20
>[  180.664060] [drm:intel_calculate_wm], FIFO watermark level: 6
>[  180.664060] [drm:intel_calculate_wm], FIFO entries required for mode: 0
>[  180.664060] [drm:intel_calculate_wm], FIFO watermark level: 29
>[  180.664060] [drm:i9xx_update_wm], FIFO watermarks - A: 6, B: 29
>[  180.664060] [drm:i9xx_update_wm], self-refresh entries: 25
>[  180.664060] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 6, B: 29, C: 2, SR 70
>[  180.688061] [drm:drm_helper_probe_single_connector_modes], VGA-1 is disconnected
>[  180.688061] [drm:drm_mode_getconnector], connector id 5:
>[  180.688061] [drm:drm_helper_probe_single_connector_modes], VGA-1
>[  180.692061] [drm:intel_update_watermarks], plane B (pipe 0) clock: 31500
>[  180.692061] [drm:intel_update_watermarks], plane A (pipe 1) clock: 65000
>[  180.692061] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[  180.692061] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[  180.692061] [drm:intel_calculate_wm], FIFO entries required for mode: 20
>[  180.692061] [drm:intel_calculate_wm], FIFO watermark level: 6
>[  180.692061] [drm:intel_calculate_wm], FIFO entries required for mode: 9
>[  180.692061] [drm:intel_calculate_wm], FIFO watermark level: 20
>[  180.692061] [drm:i9xx_update_wm], FIFO watermarks - A: 6, B: 20
>[  180.692061] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 6, B: 20, C: 2, SR 1
>[  180.716061] [drm:intel_crtc_mode_set], Mode for pipe A:
>[  180.716061] [drm:drm_mode_debug_printmodeline], Modeline 0:"640x480" 0 31500 640 664 704 832 480 489 491 520 0x10 0xa
>[  180.740060] [drm:intel_pipe_set_base], No FB bound
>[  180.740060] [drm:intel_update_watermarks], plane B (pipe 0) clock: 31500
>[  180.740060] [drm:intel_update_watermarks], plane A (pipe 1) clock: 65000
>[  180.740060] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[  180.740060] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[  180.740060] [drm:intel_calculate_wm], FIFO entries required for mode: 20
>[  180.740060] [drm:intel_calculate_wm], FIFO watermark level: 6
>[  180.740060] [drm:intel_calculate_wm], FIFO entries required for mode: 9
>[  180.740060] [drm:intel_calculate_wm], FIFO watermark level: 20
>[  180.740060] [drm:i9xx_update_wm], FIFO watermarks - A: 6, B: 20
>[  180.740060] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 6, B: 20, C: 2, SR 1
>[  180.740060] [drm:intel_update_watermarks], plane B (pipe 0) clock: 31500
>[  180.740060] [drm:intel_update_watermarks], plane A (pipe 1) clock: 65000
>[  180.740060] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[  180.740060] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[  180.740060] [drm:intel_calculate_wm], FIFO entries required for mode: 20
>[  180.740060] [drm:intel_calculate_wm], FIFO watermark level: 6
>[  180.740060] [drm:intel_calculate_wm], FIFO entries required for mode: 9
>[  180.740060] [drm:intel_calculate_wm], FIFO watermark level: 20
>[  180.740060] [drm:i9xx_update_wm], FIFO watermarks - A: 6, B: 20
>[  180.740060] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 6, B: 20, C: 2, SR 1
>[  180.788058] [drm:intel_update_watermarks], plane A (pipe 1) clock: 65000
>[  180.788058] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[  180.788058] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[  180.788058] [drm:intel_calculate_wm], FIFO entries required for mode: 20
>[  180.788058] [drm:intel_calculate_wm], FIFO watermark level: 6
>[  180.788058] [drm:intel_calculate_wm], FIFO entries required for mode: 0
>[  180.788058] [drm:intel_calculate_wm], FIFO watermark level: 29
>[  180.788058] [drm:i9xx_update_wm], FIFO watermarks - A: 6, B: 29
>[  180.788058] [drm:i9xx_update_wm], self-refresh entries: 25
>[  180.788058] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 6, B: 29, C: 2, SR 70
>[  180.812059] [drm:drm_helper_probe_single_connector_modes], VGA-1 is disconnected
>[  180.812059] [drm:drm_mode_getconnector], connector id 7:
>[  180.812059] [drm:drm_helper_probe_single_connector_modes], LVDS-1
>[  180.812059] [drm:drm_helper_probe_single_connector_modes], Probed modes for LVDS-1
>[  180.812059] [drm:drm_mode_debug_printmodeline], Modeline 26:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x8 0xa
>[  180.812059] [drm:drm_mode_getconnector], connector id 7:
>[  180.816059] [drm:drm_mode_getconnector], connector id 11:
>[  180.816059] [drm:drm_helper_probe_single_connector_modes], SVIDEO-1
>[  180.816059] [drm:intel_update_watermarks], plane B (pipe 0) clock: 107520
>[  180.816059] [drm:intel_update_watermarks], plane A (pipe 1) clock: 65000
>[  180.816059] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[  180.816059] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[  180.816059] [drm:intel_calculate_wm], FIFO entries required for mode: 20
>[  180.816059] [drm:intel_calculate_wm], FIFO watermark level: 6
>[  180.816059] [drm:intel_calculate_wm], FIFO entries required for mode: 33
>[  180.816059] [drm:intel_calculate_wm], FIFO watermark level: -4
>[  180.816059] [drm:i9xx_update_wm], FIFO watermarks - A: 6, B: 1
>[  180.816059] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 6, B: 1, C: 2, SR 1
>[  180.840059] [drm:intel_crtc_mode_set], Mode for pipe A:
>[  180.840059] [drm:drm_mode_debug_printmodeline], Modeline 0:"NTSC 480i" 0 107520 1280 1368 1496 1712 1024 1027 1034 1104 0x40 0x0
>[  180.864059] [drm:intel_pipe_set_base], No FB bound
>[  180.864059] [drm:intel_update_watermarks], plane B (pipe 0) clock: 107520
>[  180.864059] [drm:intel_update_watermarks], plane A (pipe 1) clock: 65000
>[  180.864059] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[  180.864059] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[  180.864059] [drm:intel_calculate_wm], FIFO entries required for mode: 20
>[  180.864059] [drm:intel_calculate_wm], FIFO watermark level: 6
>[  180.864059] [drm:intel_calculate_wm], FIFO entries required for mode: 33
>[  180.864059] [drm:intel_calculate_wm], FIFO watermark level: -4
>[  180.864059] [drm:i9xx_update_wm], FIFO watermarks - A: 6, B: 1
>[  180.864059] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 6, B: 1, C: 2, SR 1
>[  180.888060] [drm:intel_update_watermarks], plane B (pipe 0) clock: 107520
>[  180.888060] [drm:intel_update_watermarks], plane A (pipe 1) clock: 65000
>[  180.888060] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[  180.888060] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[  180.888060] [drm:intel_calculate_wm], FIFO entries required for mode: 20
>[  180.888060] [drm:intel_calculate_wm], FIFO watermark level: 6
>[  180.888060] [drm:intel_calculate_wm], FIFO entries required for mode: 33
>[  180.888060] [drm:intel_calculate_wm], FIFO watermark level: -4
>[  180.888060] [drm:i9xx_update_wm], FIFO watermarks - A: 6, B: 1
>[  180.888060] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 6, B: 1, C: 2, SR 1
>[  180.960061] [drm:intel_tv_detect_type], No TV connection detected
>[  180.960061] [drm:intel_update_watermarks], plane A (pipe 1) clock: 65000
>[  180.960061] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[  180.960061] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[  180.960061] [drm:intel_calculate_wm], FIFO entries required for mode: 20
>[  180.960061] [drm:intel_calculate_wm], FIFO watermark level: 6
>[  180.960061] [drm:intel_calculate_wm], FIFO entries required for mode: 0
>[  180.960061] [drm:intel_calculate_wm], FIFO watermark level: 29
>[  180.960061] [drm:i9xx_update_wm], FIFO watermarks - A: 6, B: 29
>[  180.960061] [drm:i9xx_update_wm], self-refresh entries: 25
>[  180.960061] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 6, B: 29, C: 2, SR 70
>[  180.984063] [drm:drm_helper_probe_single_connector_modes], SVIDEO-1 is disconnected
>[  180.984063] [drm:drm_mode_getconnector], connector id 11:
>[  180.984063] [drm:drm_helper_probe_single_connector_modes], SVIDEO-1
>[  180.984063] [drm:intel_update_watermarks], plane B (pipe 0) clock: 107520
>[  180.984063] [drm:intel_update_watermarks], plane A (pipe 1) clock: 65000
>[  180.984063] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[  180.984063] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[  180.984063] [drm:intel_calculate_wm], FIFO entries required for mode: 20
>[  180.984063] [drm:intel_calculate_wm], FIFO watermark level: 6
>[  180.984063] [drm:intel_calculate_wm], FIFO entries required for mode: 33
>[  180.984063] [drm:intel_calculate_wm], FIFO watermark level: -4
>[  180.984063] [drm:i9xx_update_wm], FIFO watermarks - A: 6, B: 1
>[  180.984063] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 6, B: 1, C: 2, SR 1
>[  181.008062] [drm:intel_crtc_mode_set], Mode for pipe A:
>[  181.008062] [drm:drm_mode_debug_printmodeline], Modeline 0:"NTSC 480i" 0 107520 1280 1368 1496 1712 1024 1027 1034 1104 0x40 0x0
>[  181.032062] [drm:intel_pipe_set_base], No FB bound
>[  181.032062] [drm:intel_update_watermarks], plane B (pipe 0) clock: 107520
>[  181.032062] [drm:intel_update_watermarks], plane A (pipe 1) clock: 65000
>[  181.032062] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[  181.032062] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[  181.032062] [drm:intel_calculate_wm], FIFO entries required for mode: 20
>[  181.032062] [drm:intel_calculate_wm], FIFO watermark level: 6
>[  181.032062] [drm:intel_calculate_wm], FIFO entries required for mode: 33
>[  181.032062] [drm:intel_calculate_wm], FIFO watermark level: -4
>[  181.032062] [drm:i9xx_update_wm], FIFO watermarks - A: 6, B: 1
>[  181.032062] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 6, B: 1, C: 2, SR 1
>[  181.056061] [drm:intel_update_watermarks], plane B (pipe 0) clock: 107520
>[  181.056061] [drm:intel_update_watermarks], plane A (pipe 1) clock: 65000
>[  181.056061] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[  181.056061] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[  181.056061] [drm:intel_calculate_wm], FIFO entries required for mode: 20
>[  181.056061] [drm:intel_calculate_wm], FIFO watermark level: 6
>[  181.056061] [drm:intel_calculate_wm], FIFO entries required for mode: 33
>[  181.056061] [drm:intel_calculate_wm], FIFO watermark level: -4
>[  181.056061] [drm:i9xx_update_wm], FIFO watermarks - A: 6, B: 1
>[  181.056061] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 6, B: 1, C: 2, SR 1
>[  181.128058] [drm:intel_tv_detect_type], No TV connection detected
>[  181.128058] [drm:intel_update_watermarks], plane A (pipe 1) clock: 65000
>[  181.128058] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[  181.128058] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[  181.128058] [drm:intel_calculate_wm], FIFO entries required for mode: 20
>[  181.128058] [drm:intel_calculate_wm], FIFO watermark level: 6
>[  181.128058] [drm:intel_calculate_wm], FIFO entries required for mode: 0
>[  181.128058] [drm:intel_calculate_wm], FIFO watermark level: 29
>[  181.128058] [drm:i9xx_update_wm], FIFO watermarks - A: 6, B: 29
>[  181.128058] [drm:i9xx_update_wm], self-refresh entries: 25
>[  181.128058] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 6, B: 29, C: 2, SR 70
>[  181.152061] [drm:drm_helper_probe_single_connector_modes], SVIDEO-1 is disconnected
>[  181.245878] [drm:drm_crtc_helper_set_config], 
>[  181.245878] [drm:drm_crtc_helper_set_config], crtc: f68aa000 4 fb: f61b42c0 connectors: f6111a40 num_connectors: 1 (x, y) (0, 0)
>[  181.245878] [drm:drm_crtc_helper_set_config], setting connector 7 crtc to f68aa000
>[  181.252013] [drm:intel_pipe_set_base], Writing base 00C00000 00000000 0 0 4096
>[  182.748010] [drm:intel_crtc_cursor_set], 
>[  183.780008] [drm:intel_update_watermarks], plane B (pipe 0) clock: 31500
>[  183.780008] [drm:intel_update_watermarks], plane A (pipe 1) clock: 65000
>[  183.780008] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[  183.780008] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[  183.780008] [drm:intel_calculate_wm], FIFO entries required for mode: 20
>[  183.780008] [drm:intel_calculate_wm], FIFO watermark level: 6
>[  183.780008] [drm:intel_calculate_wm], FIFO entries required for mode: 9
>[  183.780008] [drm:intel_calculate_wm], FIFO watermark level: 20
>[  183.780008] [drm:i9xx_update_wm], FIFO watermarks - A: 6, B: 20
>[  183.780008] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 6, B: 20, C: 2, SR 1
>[  183.804063] [drm:intel_crtc_mode_set], Mode for pipe A:
>[  183.804063] [drm:drm_mode_debug_printmodeline], Modeline 0:"640x480" 0 31500 640 664 704 832 480 489 491 520 0x10 0xa
>[  183.830225] [drm:intel_pipe_set_base], No FB bound
>[  183.830225] [drm:intel_update_watermarks], plane B (pipe 0) clock: 31500
>[  183.830225] [drm:intel_update_watermarks], plane A (pipe 1) clock: 65000
>[  183.830225] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[  183.830225] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[  183.830225] [drm:intel_calculate_wm], FIFO entries required for mode: 20
>[  183.830225] [drm:intel_calculate_wm], FIFO watermark level: 6
>[  183.830225] [drm:intel_calculate_wm], FIFO entries required for mode: 9
>[  183.830225] [drm:intel_calculate_wm], FIFO watermark level: 20
>[  183.830225] [drm:i9xx_update_wm], FIFO watermarks - A: 6, B: 20
>[  183.830225] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 6, B: 20, C: 2, SR 1
>[  183.830225] [drm:intel_update_watermarks], plane B (pipe 0) clock: 31500
>[  183.830225] [drm:intel_update_watermarks], plane A (pipe 1) clock: 65000
>[  183.830225] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[  183.830225] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[  183.830225] [drm:intel_calculate_wm], FIFO entries required for mode: 20
>[  183.830225] [drm:intel_calculate_wm], FIFO watermark level: 6
>[  183.830225] [drm:intel_calculate_wm], FIFO entries required for mode: 9
>[  183.830225] [drm:intel_calculate_wm], FIFO watermark level: 20
>[  183.830225] [drm:i9xx_update_wm], FIFO watermarks - A: 6, B: 20
>[  183.830225] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 6, B: 20, C: 2, SR 1
>[  183.876059] [drm:intel_update_watermarks], plane A (pipe 1) clock: 65000
>[  183.876059] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[  183.876059] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[  183.876059] [drm:intel_calculate_wm], FIFO entries required for mode: 20
>[  183.876059] [drm:intel_calculate_wm], FIFO watermark level: 6
>[  183.876059] [drm:intel_calculate_wm], FIFO entries required for mode: 0
>[  183.876059] [drm:intel_calculate_wm], FIFO watermark level: 29
>[  183.876059] [drm:i9xx_update_wm], FIFO watermarks - A: 6, B: 29
>[  183.876059] [drm:i9xx_update_wm], self-refresh entries: 25
>[  183.876059] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 6, B: 29, C: 2, SR 70
>[  193.924008] [drm:intel_update_watermarks], plane B (pipe 0) clock: 31500
>[  193.924008] [drm:intel_update_watermarks], plane A (pipe 1) clock: 65000
>[  193.924008] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[  193.924008] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[  193.924008] [drm:intel_calculate_wm], FIFO entries required for mode: 20
>[  193.924008] [drm:intel_calculate_wm], FIFO watermark level: 6
>[  193.924008] [drm:intel_calculate_wm], FIFO entries required for mode: 9
>[  193.924008] [drm:intel_calculate_wm], FIFO watermark level: 20
>[  193.924008] [drm:i9xx_update_wm], FIFO watermarks - A: 6, B: 20
>[  193.924008] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 6, B: 20, C: 2, SR 1
>[  193.948026] [drm:intel_crtc_mode_set], Mode for pipe A:
>[  193.948026] [drm:drm_mode_debug_printmodeline], Modeline 0:"640x480" 0 31500 640 664 704 832 480 489 491 520 0x10 0xa
>[  193.972528] [drm:intel_pipe_set_base], No FB bound
>[  193.972528] [drm:intel_update_watermarks], plane B (pipe 0) clock: 31500
>[  193.972528] [drm:intel_update_watermarks], plane A (pipe 1) clock: 65000
>[  193.972528] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[  193.972528] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[  193.972528] [drm:intel_calculate_wm], FIFO entries required for mode: 20
>[  193.972528] [drm:intel_calculate_wm], FIFO watermark level: 6
>[  193.972528] [drm:intel_calculate_wm], FIFO entries required for mode: 9
>[  193.972528] [drm:intel_calculate_wm], FIFO watermark level: 20
>[  193.972528] [drm:i9xx_update_wm], FIFO watermarks - A: 6, B: 20
>[  193.972528] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 6, B: 20, C: 2, SR 1
>[  193.972528] [drm:intel_update_watermarks], plane B (pipe 0) clock: 31500
>[  193.972528] [drm:intel_update_watermarks], plane A (pipe 1) clock: 65000
>[  193.972528] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[  193.972528] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[  193.972528] [drm:intel_calculate_wm], FIFO entries required for mode: 20
>[  193.972528] [drm:intel_calculate_wm], FIFO watermark level: 6
>[  193.972528] [drm:intel_calculate_wm], FIFO entries required for mode: 9
>[  193.972528] [drm:intel_calculate_wm], FIFO watermark level: 20
>[  193.972528] [drm:i9xx_update_wm], FIFO watermarks - A: 6, B: 20
>[  193.972528] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 6, B: 20, C: 2, SR 1
>[  194.020023] [drm:intel_update_watermarks], plane A (pipe 1) clock: 65000
>[  194.020023] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[  194.020023] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[  194.020023] [drm:intel_calculate_wm], FIFO entries required for mode: 20
>[  194.020023] [drm:intel_calculate_wm], FIFO watermark level: 6
>[  194.020023] [drm:intel_calculate_wm], FIFO entries required for mode: 0
>[  194.020023] [drm:intel_calculate_wm], FIFO watermark level: 29
>[  194.020023] [drm:i9xx_update_wm], FIFO watermarks - A: 6, B: 29
>[  194.020023] [drm:i9xx_update_wm], self-refresh entries: 25
>[  194.020023] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 6, B: 29, C: 2, SR 70
>[  194.615977] [drm:drm_mode_getconnector], connector id 5:
>[  194.615977] [drm:drm_helper_probe_single_connector_modes], VGA-1
>[  194.616012] [drm:intel_update_watermarks], plane B (pipe 0) clock: 31500
>[  194.616012] [drm:intel_update_watermarks], plane A (pipe 1) clock: 65000
>[  194.616012] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[  194.616012] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[  194.616012] [drm:intel_calculate_wm], FIFO entries required for mode: 20
>[  194.616012] [drm:intel_calculate_wm], FIFO watermark level: 6
>[  194.616012] [drm:intel_calculate_wm], FIFO entries required for mode: 9
>[  194.616012] [drm:intel_calculate_wm], FIFO watermark level: 20
>[  194.616012] [drm:i9xx_update_wm], FIFO watermarks - A: 6, B: 20
>[  194.616012] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 6, B: 20, C: 2, SR 1
>[  194.640023] [drm:intel_crtc_mode_set], Mode for pipe A:
>[  194.640023] [drm:drm_mode_debug_printmodeline], Modeline 0:"640x480" 0 31500 640 664 704 832 480 489 491 520 0x10 0xa
>[  194.664023] [drm:intel_pipe_set_base], No FB bound
>[  194.664023] [drm:intel_update_watermarks], plane B (pipe 0) clock: 31500
>[  194.664023] [drm:intel_update_watermarks], plane A (pipe 1) clock: 65000
>[  194.664023] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[  194.664023] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[  194.664023] [drm:intel_calculate_wm], FIFO entries required for mode: 20
>[  194.664023] [drm:intel_calculate_wm], FIFO watermark level: 6
>[  194.664023] [drm:intel_calculate_wm], FIFO entries required for mode: 9
>[  194.664023] [drm:intel_calculate_wm], FIFO watermark level: 20
>[  194.664023] [drm:i9xx_update_wm], FIFO watermarks - A: 6, B: 20
>[  194.664023] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 6, B: 20, C: 2, SR 1
>[  194.664023] [drm:intel_update_watermarks], plane B (pipe 0) clock: 31500
>[  194.664023] [drm:intel_update_watermarks], plane A (pipe 1) clock: 65000
>[  194.664023] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[  194.664023] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[  194.664023] [drm:intel_calculate_wm], FIFO entries required for mode: 20
>[  194.664023] [drm:intel_calculate_wm], FIFO watermark level: 6
>[  194.664023] [drm:intel_calculate_wm], FIFO entries required for mode: 9
>[  194.664023] [drm:intel_calculate_wm], FIFO watermark level: 20
>[  194.664023] [drm:i9xx_update_wm], FIFO watermarks - A: 6, B: 20
>[  194.664023] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 6, B: 20, C: 2, SR 1
>[  194.712027] [drm:intel_update_watermarks], plane A (pipe 1) clock: 65000
>[  194.712027] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[  194.712027] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[  194.712027] [drm:intel_calculate_wm], FIFO entries required for mode: 20
>[  194.712027] [drm:intel_calculate_wm], FIFO watermark level: 6
>[  194.712027] [drm:intel_calculate_wm], FIFO entries required for mode: 0
>[  194.712027] [drm:intel_calculate_wm], FIFO watermark level: 29
>[  194.712027] [drm:i9xx_update_wm], FIFO watermarks - A: 6, B: 29
>[  194.712027] [drm:i9xx_update_wm], self-refresh entries: 25
>[  194.712027] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 6, B: 29, C: 2, SR 70
>[  194.736026] [drm:drm_helper_probe_single_connector_modes], VGA-1 is disconnected
>[  194.736026] [drm:drm_mode_getconnector], connector id 5:
>[  194.736026] [drm:drm_helper_probe_single_connector_modes], VGA-1
>[  194.740026] [drm:intel_update_watermarks], plane B (pipe 0) clock: 31500
>[  194.740026] [drm:intel_update_watermarks], plane A (pipe 1) clock: 65000
>[  194.740026] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[  194.740026] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[  194.740026] [drm:intel_calculate_wm], FIFO entries required for mode: 20
>[  194.740026] [drm:intel_calculate_wm], FIFO watermark level: 6
>[  194.740026] [drm:intel_calculate_wm], FIFO entries required for mode: 9
>[  194.740026] [drm:intel_calculate_wm], FIFO watermark level: 20
>[  194.740026] [drm:i9xx_update_wm], FIFO watermarks - A: 6, B: 20
>[  194.740026] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 6, B: 20, C: 2, SR 1
>[  194.764026] [drm:intel_crtc_mode_set], Mode for pipe A:
>[  194.764026] [drm:drm_mode_debug_printmodeline], Modeline 0:"640x480" 0 31500 640 664 704 832 480 489 491 520 0x10 0xa
>[  194.788026] [drm:intel_pipe_set_base], No FB bound
>[  194.788026] [drm:intel_update_watermarks], plane B (pipe 0) clock: 31500
>[  194.788026] [drm:intel_update_watermarks], plane A (pipe 1) clock: 65000
>[  194.788026] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[  194.788026] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[  194.788026] [drm:intel_calculate_wm], FIFO entries required for mode: 20
>[  194.788026] [drm:intel_calculate_wm], FIFO watermark level: 6
>[  194.788026] [drm:intel_calculate_wm], FIFO entries required for mode: 9
>[  194.788026] [drm:intel_calculate_wm], FIFO watermark level: 20
>[  194.788026] [drm:i9xx_update_wm], FIFO watermarks - A: 6, B: 20
>[  194.788026] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 6, B: 20, C: 2, SR 1
>[  194.788026] [drm:intel_update_watermarks], plane B (pipe 0) clock: 31500
>[  194.788026] [drm:intel_update_watermarks], plane A (pipe 1) clock: 65000
>[  194.788026] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[  194.788026] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[  194.788026] [drm:intel_calculate_wm], FIFO entries required for mode: 20
>[  194.788026] [drm:intel_calculate_wm], FIFO watermark level: 6
>[  194.788026] [drm:intel_calculate_wm], FIFO entries required for mode: 9
>[  194.788026] [drm:intel_calculate_wm], FIFO watermark level: 20
>[  194.788026] [drm:i9xx_update_wm], FIFO watermarks - A: 6, B: 20
>[  194.788026] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 6, B: 20, C: 2, SR 1
>[  194.839460] [drm:intel_update_watermarks], plane A (pipe 1) clock: 65000
>[  194.839460] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[  194.839460] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[  194.839460] [drm:intel_calculate_wm], FIFO entries required for mode: 20
>[  194.839460] [drm:intel_calculate_wm], FIFO watermark level: 6
>[  194.839460] [drm:intel_calculate_wm], FIFO entries required for mode: 0
>[  194.839460] [drm:intel_calculate_wm], FIFO watermark level: 29
>[  194.839460] [drm:i9xx_update_wm], FIFO watermarks - A: 6, B: 29
>[  194.839460] [drm:i9xx_update_wm], self-refresh entries: 25
>[  194.839460] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 6, B: 29, C: 2, SR 70
>[  194.860022] [drm:drm_helper_probe_single_connector_modes], VGA-1 is disconnected
>[  194.860022] [drm:drm_mode_getconnector], connector id 7:
>[  194.860022] [drm:drm_helper_probe_single_connector_modes], LVDS-1
>[  194.860022] [drm:drm_helper_probe_single_connector_modes], Probed modes for LVDS-1
>[  194.860022] [drm:drm_mode_debug_printmodeline], Modeline 26:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x8 0xa
>[  194.860022] [drm:drm_mode_getconnector], connector id 7:
>[  194.860022] [drm:drm_mode_getconnector], connector id 11:
>[  194.860022] [drm:drm_helper_probe_single_connector_modes], SVIDEO-1
>[  194.860022] [drm:intel_update_watermarks], plane B (pipe 0) clock: 107520
>[  194.860022] [drm:intel_update_watermarks], plane A (pipe 1) clock: 65000
>[  194.860022] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[  194.860022] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[  194.860022] [drm:intel_calculate_wm], FIFO entries required for mode: 20
>[  194.860022] [drm:intel_calculate_wm], FIFO watermark level: 6
>[  194.860022] [drm:intel_calculate_wm], FIFO entries required for mode: 33
>[  194.860022] [drm:intel_calculate_wm], FIFO watermark level: -4
>[  194.860022] [drm:i9xx_update_wm], FIFO watermarks - A: 6, B: 1
>[  194.860022] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 6, B: 1, C: 2, SR 1
>[  194.884944] [drm:intel_crtc_mode_set], Mode for pipe A:
>[  194.884944] [drm:drm_mode_debug_printmodeline], Modeline 0:"NTSC 480i" 0 107520 1280 1368 1496 1712 1024 1027 1034 1104 0x40 0x0
>[  194.908022] [drm:intel_pipe_set_base], No FB bound
>[  194.908022] [drm:intel_update_watermarks], plane B (pipe 0) clock: 107520
>[  194.908022] [drm:intel_update_watermarks], plane A (pipe 1) clock: 65000
>[  194.908022] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[  194.908022] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[  194.908022] [drm:intel_calculate_wm], FIFO entries required for mode: 20
>[  194.908022] [drm:intel_calculate_wm], FIFO watermark level: 6
>[  194.908022] [drm:intel_calculate_wm], FIFO entries required for mode: 33
>[  194.908022] [drm:intel_calculate_wm], FIFO watermark level: -4
>[  194.908022] [drm:i9xx_update_wm], FIFO watermarks - A: 6, B: 1
>[  194.908022] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 6, B: 1, C: 2, SR 1
>[  194.932025] [drm:intel_update_watermarks], plane B (pipe 0) clock: 107520
>[  194.932025] [drm:intel_update_watermarks], plane A (pipe 1) clock: 65000
>[  194.932025] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[  194.932025] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[  194.932025] [drm:intel_calculate_wm], FIFO entries required for mode: 20
>[  194.932025] [drm:intel_calculate_wm], FIFO watermark level: 6
>[  194.932025] [drm:intel_calculate_wm], FIFO entries required for mode: 33
>[  194.932025] [drm:intel_calculate_wm], FIFO watermark level: -4
>[  194.932025] [drm:i9xx_update_wm], FIFO watermarks - A: 6, B: 1
>[  194.932025] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 6, B: 1, C: 2, SR 1
>[  195.004025] [drm:intel_tv_detect_type], No TV connection detected
>[  195.004025] [drm:intel_update_watermarks], plane A (pipe 1) clock: 65000
>[  195.004025] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[  195.004025] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[  195.004025] [drm:intel_calculate_wm], FIFO entries required for mode: 20
>[  195.004025] [drm:intel_calculate_wm], FIFO watermark level: 6
>[  195.004025] [drm:intel_calculate_wm], FIFO entries required for mode: 0
>[  195.004025] [drm:intel_calculate_wm], FIFO watermark level: 29
>[  195.004025] [drm:i9xx_update_wm], FIFO watermarks - A: 6, B: 29
>[  195.004025] [drm:i9xx_update_wm], self-refresh entries: 25
>[  195.004025] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 6, B: 29, C: 2, SR 70
>[  195.030992] [drm:drm_helper_probe_single_connector_modes], SVIDEO-1 is disconnected
>[  195.030992] [drm:drm_mode_getconnector], connector id 11:
>[  195.030992] [drm:drm_helper_probe_single_connector_modes], SVIDEO-1
>[  195.030992] [drm:intel_update_watermarks], plane B (pipe 0) clock: 107520
>[  195.030992] [drm:intel_update_watermarks], plane A (pipe 1) clock: 65000
>[  195.030992] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[  195.030992] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[  195.030992] [drm:intel_calculate_wm], FIFO entries required for mode: 20
>[  195.030992] [drm:intel_calculate_wm], FIFO watermark level: 6
>[  195.030992] [drm:intel_calculate_wm], FIFO entries required for mode: 33
>[  195.030992] [drm:intel_calculate_wm], FIFO watermark level: -4
>[  195.030992] [drm:i9xx_update_wm], FIFO watermarks - A: 6, B: 1
>[  195.030992] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 6, B: 1, C: 2, SR 1
>[  195.052061] [drm:intel_crtc_mode_set], Mode for pipe A:
>[  195.052061] [drm:drm_mode_debug_printmodeline], Modeline 0:"NTSC 480i" 0 107520 1280 1368 1496 1712 1024 1027 1034 1104 0x40 0x0
>[  195.076061] [drm:intel_pipe_set_base], No FB bound
>[  195.076061] [drm:intel_update_watermarks], plane B (pipe 0) clock: 107520
>[  195.076061] [drm:intel_update_watermarks], plane A (pipe 1) clock: 65000
>[  195.076061] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[  195.076061] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[  195.076061] [drm:intel_calculate_wm], FIFO entries required for mode: 20
>[  195.076061] [drm:intel_calculate_wm], FIFO watermark level: 6
>[  195.076061] [drm:intel_calculate_wm], FIFO entries required for mode: 33
>[  195.076061] [drm:intel_calculate_wm], FIFO watermark level: -4
>[  195.076061] [drm:i9xx_update_wm], FIFO watermarks - A: 6, B: 1
>[  195.076061] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 6, B: 1, C: 2, SR 1
>[  195.101934] [drm:intel_update_watermarks], plane B (pipe 0) clock: 107520
>[  195.101934] [drm:intel_update_watermarks], plane A (pipe 1) clock: 65000
>[  195.101934] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[  195.101934] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[  195.101934] [drm:intel_calculate_wm], FIFO entries required for mode: 20
>[  195.101934] [drm:intel_calculate_wm], FIFO watermark level: 6
>[  195.101934] [drm:intel_calculate_wm], FIFO entries required for mode: 33
>[  195.101934] [drm:intel_calculate_wm], FIFO watermark level: -4
>[  195.101934] [drm:i9xx_update_wm], FIFO watermarks - A: 6, B: 1
>[  195.101934] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 6, B: 1, C: 2, SR 1
>[  195.172059] [drm:intel_tv_detect_type], No TV connection detected
>[  195.172059] [drm:intel_update_watermarks], plane A (pipe 1) clock: 65000
>[  195.172059] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[  195.172059] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[  195.172059] [drm:intel_calculate_wm], FIFO entries required for mode: 20
>[  195.172059] [drm:intel_calculate_wm], FIFO watermark level: 6
>[  195.172059] [drm:intel_calculate_wm], FIFO entries required for mode: 0
>[  195.172059] [drm:intel_calculate_wm], FIFO watermark level: 29
>[  195.172059] [drm:i9xx_update_wm], FIFO watermarks - A: 6, B: 29
>[  195.172059] [drm:i9xx_update_wm], self-refresh entries: 25
>[  195.172059] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 6, B: 29, C: 2, SR 70
>[  195.198515] [drm:drm_helper_probe_single_connector_modes], SVIDEO-1 is disconnected
>[  203.749844] [drm:intel_crtc_cursor_set], 
>[  203.749844] [drm:intel_crtc_cursor_set], cursor off
>[  203.868768] [drm:intel_crtc_cursor_set], 
>[  204.068008] [drm:intel_update_watermarks], plane B (pipe 0) clock: 31500
>[  204.068008] [drm:intel_update_watermarks], plane A (pipe 1) clock: 65000
>[  204.068008] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[  204.068008] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[  204.068008] [drm:intel_calculate_wm], FIFO entries required for mode: 20
>[  204.068008] [drm:intel_calculate_wm], FIFO watermark level: 6
>[  204.068008] [drm:intel_calculate_wm], FIFO entries required for mode: 9
>[  204.068008] [drm:intel_calculate_wm], FIFO watermark level: 20
>[  204.068008] [drm:i9xx_update_wm], FIFO watermarks - A: 6, B: 20
>[  204.068008] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 6, B: 20, C: 2, SR 1
>[  204.092059] [drm:intel_crtc_mode_set], Mode for pipe A:
>[  204.092059] [drm:drm_mode_debug_printmodeline], Modeline 0:"640x480" 0 31500 640 664 704 832 480 489 491 520 0x10 0xa
>[  204.116018] [drm:intel_pipe_set_base], No FB bound
>[  204.116018] [drm:intel_update_watermarks], plane B (pipe 0) clock: 31500
>[  204.116018] [drm:intel_update_watermarks], plane A (pipe 1) clock: 65000
>[  204.116018] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[  204.116018] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[  204.116018] [drm:intel_calculate_wm], FIFO entries required for mode: 20
>[  204.116018] [drm:intel_calculate_wm], FIFO watermark level: 6
>[  204.116018] [drm:intel_calculate_wm], FIFO entries required for mode: 9
>[  204.116018] [drm:intel_calculate_wm], FIFO watermark level: 20
>[  204.116018] [drm:i9xx_update_wm], FIFO watermarks - A: 6, B: 20
>[  204.116018] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 6, B: 20, C: 2, SR 1
>[  204.116018] [drm:intel_update_watermarks], plane B (pipe 0) clock: 31500
>[  204.116018] [drm:intel_update_watermarks], plane A (pipe 1) clock: 65000
>[  204.116018] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[  204.116018] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[  204.116018] [drm:intel_calculate_wm], FIFO entries required for mode: 20
>[  204.116018] [drm:intel_calculate_wm], FIFO watermark level: 6
>[  204.116018] [drm:intel_calculate_wm], FIFO entries required for mode: 9
>[  204.116018] [drm:intel_calculate_wm], FIFO watermark level: 20
>[  204.116018] [drm:i9xx_update_wm], FIFO watermarks - A: 6, B: 20
>[  204.116018] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 6, B: 20, C: 2, SR 1
>[  204.164058] [drm:intel_update_watermarks], plane A (pipe 1) clock: 65000
>[  204.164058] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[  204.164058] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[  204.164058] [drm:intel_calculate_wm], FIFO entries required for mode: 20
>[  204.164058] [drm:intel_calculate_wm], FIFO watermark level: 6
>[  204.164058] [drm:intel_calculate_wm], FIFO entries required for mode: 0
>[  204.164058] [drm:intel_calculate_wm], FIFO watermark level: 29
>[  204.164058] [drm:i9xx_update_wm], FIFO watermarks - A: 6, B: 29
>[  204.164058] [drm:i9xx_update_wm], self-refresh entries: 25
>[  204.164058] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 6, B: 29, C: 2, SR 70
>[  204.300669] [drm:intel_crtc_cursor_set], 
>[  204.300669] [drm:intel_crtc_cursor_set], cursor off
>[  208.526117] PM: Syncing filesystems ... done.
>[  208.536011] [drm:drm_crtc_helper_set_config], 
>[  208.536011] [drm:drm_crtc_helper_set_config], crtc: f68aa000 4 fb: f6844c38 connectors: f68978e0 num_connectors: 1 (x, y) (0, 0)
>[  208.536011] [drm:drm_crtc_helper_set_config], setting connector 7 crtc to f68aa000
>[  208.536011] [drm:intel_pipe_set_base], Writing base 007E0000 00000000 0 0 4096
>[  208.576007] [drm:drm_crtc_helper_set_config], 
>[  208.576007] [drm:drm_crtc_helper_set_config], crtc: f6874000 3 fb: f6844c38 connectors: f6897900 num_connectors: 0 (x, y) (0, 0)
>[  208.576007] [drm:drm_crtc_helper_set_config], crtc has no fb, full mode set
>[  208.576007] [drm:drm_crtc_helper_set_config], setting connector 7 crtc to f68aa000
>[  208.576007] [drm:intel_update_watermarks], plane A (pipe 1) clock: 65000
>[  208.576007] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[  208.576007] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[  208.576007] [drm:intel_calculate_wm], FIFO entries required for mode: 20
>[  208.576007] [drm:intel_calculate_wm], FIFO watermark level: 6
>[  208.576007] [drm:intel_calculate_wm], FIFO entries required for mode: 0
>[  208.576007] [drm:intel_calculate_wm], FIFO watermark level: 29
>[  208.576007] [drm:i9xx_update_wm], FIFO watermarks - A: 6, B: 29
>[  208.576007] [drm:i9xx_update_wm], self-refresh entries: 25
>[  208.576007] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 6, B: 29, C: 2, SR 70
>[  208.600057] [drm:drm_crtc_helper_set_config], 
>[  208.600057] [drm:drm_crtc_helper_set_config], crtc: f68aa000 4 fb: f6844c38 connectors: f68978e0 num_connectors: 1 (x, y) (0, 0)
>[  208.600057] [drm:drm_crtc_helper_set_config], setting connector 7 crtc to f68aa000
>[  208.600057] [drm:drm_crtc_helper_set_config], 
>[  208.600057] [drm:drm_crtc_helper_set_config], crtc: f68aa000 4 fb: f6844c38 connectors: f68978e0 num_connectors: 1 (x, y) (0, 0)
>[  208.600057] [drm:drm_crtc_helper_set_config], setting connector 7 crtc to f68aa000
>[  208.600057] [drm:drm_crtc_helper_set_config], 
>[  208.600057] [drm:drm_crtc_helper_set_config], crtc: f68aa000 4 fb: f6844c38 connectors: f68978e0 num_connectors: 1 (x, y) (0, 0)
>[  208.600057] [drm:drm_crtc_helper_set_config], setting connector 7 crtc to f68aa000
>[  208.620007] Freezing user space processes ... (elapsed 0.01 seconds) done.
>[  208.636056] Freezing remaining freezable tasks ... (elapsed 0.01 seconds) done.
>[  208.673865] serial 00:0a: disabled
>[  208.673865] sd 0:0:0:0: [sda] Synchronizing SCSI cache
>[  208.673865] wlan0: Going into suspend...
>[  208.677783] sd 0:0:0:0: [sda] Stopping disk
>[  208.677783] ACPI handle has no context!
>[  208.677783] sdhci-pci 0000:04:00.1: PCI INT B disabled
>[  208.677783] ACPI handle has no context!
>[  208.824475] Intel ICH 0000:00:1e.2: PCI INT A disabled
>[  208.824475] ehci_hcd 0000:00:1d.7: PCI INT D disabled
>[  208.824475] uhci_hcd 0000:00:1d.3: PCI INT D disabled
>[  208.824475] uhci_hcd 0000:00:1d.2: PCI INT C disabled
>[  208.824475] uhci_hcd 0000:00:1d.1: PCI INT B disabled
>[  208.824475] uhci_hcd 0000:00:1d.0: PCI INT A disabled
>[  208.824475] i915_save_display(): BLC_PWM_CTL:6c676c66
>[  208.824475] i915 0000:00:02.0: PCI INT A disabled
>[  208.840006] i915 0000:00:02.0: power state changed by ACPI to D3
>[  209.008009] tg3 0000:02:00.0: PME# enabled
>[  209.008009] pcieport 0000:00:1c.0: wake-up capability enabled by ACPI
>[  209.350926] ipw2200: Firmware error detected.  Restarting.
>[  209.350926] ipw2200 0000:04:02.0: PCI INT A disabled
>[  209.350926] ACPI handle has no context!
>[  209.364007] PM: suspend of devices complete after 711.703 msecs
>[  209.388007] ipw2200: Unable to load ucode: -22
>[  209.392191] ipw2200: Unable to load firmware: -22
>[  209.392191] ipw2200: Failed to up device
>[  209.508009] ehci_hcd 0000:00:1d.7: power state changed by ACPI to D3
>[  209.532009] uhci_hcd 0000:00:1d.1: power state changed by ACPI to D3
>[  209.556009] uhci_hcd 0000:00:1d.0: power state changed by ACPI to D3
>[  209.556009] PM: late suspend of devices complete after 192.255 msecs
>[  209.596009] ACPI: Preparing to enter system sleep state S3
>[  209.796009] PM: Saving platform NVS memory
>[  209.804007] Extended CMOS year: 2000
>[  209.804007] Back to C!
>[  209.804007] PM: Restoring platform NVS memory
>[  209.804007] Extended CMOS year: 2000
>[  209.804007] Force enabled HPET at resume
>[  209.804007] ACPI: Waking up from system sleep state S3
>[  210.316009] agpgart-intel 0000:00:00.0: restoring config space at offset 0x1 (was 0x900106, writing 0x20900106)
>[  210.316009] i915 0000:00:02.0: restoring config space at offset 0x1 (was 0x900003, writing 0x900007)
>[  210.316009] pci 0000:00:02.1: restoring config space at offset 0x4 (was 0x0, writing 0x60200000)
>[  210.316009] pcieport 0000:00:1c.0: restoring config space at offset 0x9 (was 0x1fff1, writing 0x60116001)
>[  210.316009] pcieport 0000:00:1c.0: restoring config space at offset 0x7 (was 0xf0, writing 0x7070)
>[  210.316009] pcieport 0000:00:1c.0: restoring config space at offset 0x1 (was 0x100107, writing 0x100507)
>[  210.360008] uhci_hcd 0000:00:1d.0: power state changed by ACPI to D0
>[  210.368010] uhci_hcd 0000:00:1d.0: power state changed by ACPI to D0
>[  210.368010] uhci_hcd 0000:00:1d.0: restoring config space at offset 0xf (was 0x100, writing 0x10b)
>[  210.368010] uhci_hcd 0000:00:1d.0: restoring config space at offset 0x8 (was 0x1, writing 0x1821)
>[  210.368010] uhci_hcd 0000:00:1d.0: restoring config space at offset 0x1 (was 0x2800000, writing 0x2800001)
>[  210.376009] uhci_hcd 0000:00:1d.0: power state changed by ACPI to D0
>[  210.384009] uhci_hcd 0000:00:1d.0: power state changed by ACPI to D0
>[  210.392009] uhci_hcd 0000:00:1d.1: power state changed by ACPI to D0
>[  210.400008] uhci_hcd 0000:00:1d.1: power state changed by ACPI to D0
>[  210.400008] uhci_hcd 0000:00:1d.1: restoring config space at offset 0xf (was 0x200, writing 0x20b)
>[  210.400008] uhci_hcd 0000:00:1d.1: restoring config space at offset 0x8 (was 0x1, writing 0x1841)
>[  210.400008] uhci_hcd 0000:00:1d.1: restoring config space at offset 0x1 (was 0x2800000, writing 0x2800001)
>[  210.408009] uhci_hcd 0000:00:1d.1: power state changed by ACPI to D0
>[  210.416009] uhci_hcd 0000:00:1d.1: power state changed by ACPI to D0
>[  210.416009] uhci_hcd 0000:00:1d.2: restoring config space at offset 0xf (was 0x300, writing 0x30b)
>[  210.416009] uhci_hcd 0000:00:1d.2: restoring config space at offset 0x8 (was 0x1, writing 0x1861)
>[  210.416009] uhci_hcd 0000:00:1d.2: restoring config space at offset 0x1 (was 0x2800000, writing 0x2800001)
>[  210.416009] uhci_hcd 0000:00:1d.3: restoring config space at offset 0xf (was 0x400, writing 0x40b)
>[  210.416009] uhci_hcd 0000:00:1d.3: restoring config space at offset 0x8 (was 0x1, writing 0x1881)
>[  210.416009] uhci_hcd 0000:00:1d.3: restoring config space at offset 0x1 (was 0x2800000, writing 0x2800001)
>[  210.416009] ehci_hcd 0000:00:1d.7: restoring config space at offset 0xf (was 0x400, writing 0x40b)
>[  210.416009] ehci_hcd 0000:00:1d.7: restoring config space at offset 0x4 (was 0x0, writing 0xa0040000)
>[  210.416009] ehci_hcd 0000:00:1d.7: restoring config space at offset 0x1 (was 0x2900000, writing 0x2900102)
>[  210.424009] ehci_hcd 0000:00:1d.7: power state changed by ACPI to D0
>[  210.432009] ehci_hcd 0000:00:1d.7: power state changed by ACPI to D0
>[  210.432009] Intel ICH 0000:00:1e.2: restoring config space at offset 0x1 (was 0x2900007, writing 0x2900003)
>[  210.432009] pci 0000:00:1e.3: restoring config space at offset 0x1 (was 0x2900005, writing 0x2900001)
>[  210.432009] tg3 0000:02:00.0: restoring config space at offset 0xc (was 0x0, writing 0xfcbe0000)
>[  210.432009] tg3 0000:02:00.0: restoring config space at offset 0x1 (was 0x100102, writing 0x100106)
>[  210.448011] sdhci-pci 0000:04:00.1: BAR 0: set to [mem 0xa0201000-0xa02010ff] (PCI address [0xa0201000-0xa02010ff]
>[  210.448011] sdhci-pci 0000:04:00.1: restoring config space at offset 0x3 (was 0x800000, writing 0x804000)
>[  210.448011] sdhci-pci 0000:04:00.1: restoring config space at offset 0x1 (was 0x2100000, writing 0x2100106)
>[  210.448011] PM: early resume of devices complete after 132.308 msecs
>[  210.452028] i915 0000:00:02.0: power state changed by ACPI to D0
>[  210.452028] i915 0000:00:02.0: power state changed by ACPI to D0
>[  210.452028] i915 0000:00:02.0: PCI INT A -> GSI 16 (level, low) -> IRQ 16
>[  210.452028] i915 0000:00:02.0: setting latency timer to 64
>[  210.452028] i915_restore_display(): BLC_PWM_CTL=6c676c66
>[  210.452028] i915_restore_display(): BLC_PWM_CTL:6c676c66
>[  210.452028] render error detected, EIR: 0x00000010
>[  210.452028] page table error
>[  210.452028]   PGTBL_ER: 0x00000001
>[  210.452028] [drm:i915_report_and_clear_eir] *ERROR* EIR stuck: 0x00000010, masking
>[  210.452028] render error detected, EIR: 0x00000010
>[  210.452028] page table error
>[  210.452028]   PGTBL_ER: 0x00000001
>[  210.461022] uhci_hcd 0000:00:1d.2: PCI INT C -> GSI 18 (level, low) -> IRQ 18
>[  210.461022] uhci_hcd 0000:00:1d.2: setting latency timer to 64
>[  210.461022] usb usb4: root hub lost power or was reset
>[  210.461022] uhci_hcd 0000:00:1d.3: PCI INT D -> GSI 19 (level, low) -> IRQ 19
>[  210.461022] uhci_hcd 0000:00:1d.3: setting latency timer to 64
>[  210.461022] usb usb5: root hub lost power or was reset
>[  210.461022] pci 0000:00:1e.0: setting latency timer to 64
>[  210.461022] Intel ICH 0000:00:1e.2: PCI INT A -> GSI 22 (level, low) -> IRQ 22
>[  210.461022] Intel ICH 0000:00:1e.2: setting latency timer to 64
>[  210.461022] ata_piix 0000:00:1f.2: setting latency timer to 64
>[  210.464227] pcieport 0000:00:1c.0: wake-up capability disabled by ACPI
>[  210.464227] tg3 0000:02:00.0: PME# disabled
>[  210.620007] uhci_hcd 0000:00:1d.0: power state changed by ACPI to D0
>[  210.620007] uhci_hcd 0000:00:1d.1: power state changed by ACPI to D0
>[  210.620007] ehci_hcd 0000:00:1d.7: power state changed by ACPI to D0
>[  210.624017] sdhci-pci 0000:04:00.1: PCI INT B -> GSI 17 (level, low) -> IRQ 17
>[  210.624017] sdhci-pci 0000:04:00.1: Will use DMA mode even though HW doesn't fully claim to support it.
>[  210.624017] wlan0: Coming out of suspend...
>[  210.630723] uhci_hcd 0000:00:1d.0: power state changed by ACPI to D0
>[  210.636151] uhci_hcd 0000:00:1d.1: power state changed by ACPI to D0
>[  210.644008] sd 0:0:0:0: [sda] Starting disk
>[  210.648851] ehci_hcd 0000:00:1d.7: power state changed by ACPI to D0
>[  210.654539] uhci_hcd 0000:00:1d.1: PCI INT B -> GSI 17 (level, low) -> IRQ 17
>[  210.741512] uhci_hcd 0000:00:1d.0: PCI INT A -> GSI 16 (level, low) -> IRQ 16
>[  210.936176] ipw2200 0000:04:02.0: PCI INT A -> GSI 21 (level, low) -> IRQ 21
>[  210.967901] uhci_hcd 0000:00:1d.1: setting latency timer to 64
>[  211.040009] ehci_hcd 0000:00:1d.7: PCI INT D -> GSI 19 (level, low) -> IRQ 19
>[  211.048046] serial 00:0a: activated
>[  211.054841] usb usb3: root hub lost power or was reset
>[  211.060029] uhci_hcd 0000:00:1d.0: setting latency timer to 64
>[  211.060029] usb usb2: root hub lost power or was reset
>[  211.065218] ehci_hcd 0000:00:1d.7: setting latency timer to 64
>[  211.065218] [drm:intel_update_watermarks], plane A (pipe 1) clock: 65000
>[  211.065218] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[  211.065218] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[  211.065218] [drm:intel_calculate_wm], FIFO entries required for mode: 20
>[  211.065218] [drm:intel_calculate_wm], FIFO watermark level: 6
>[  211.065218] [drm:intel_calculate_wm], FIFO entries required for mode: 0
>[  211.065218] [drm:intel_calculate_wm], FIFO watermark level: 29
>[  211.065218] [drm:i9xx_update_wm], FIFO watermarks - A: 6, B: 29
>[  211.065218] [drm:i9xx_update_wm], self-refresh entries: 25
>[  211.065218] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 6, B: 29, C: 2, SR 70
>[  211.088040] [drm:intel_crtc_mode_set], using SSC reference clock of 100 MHz
>[  211.088040] [drm:intel_crtc_mode_set], Mode for pipe B:
>[  211.088040] [drm:drm_mode_debug_printmodeline], Modeline 27:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x8 0xa
>[  211.112029] [drm:intel_pipe_set_base], Writing base 007E0000 00000000 0 0 4096
>[  211.136029] [drm:intel_update_watermarks], plane A (pipe 1) clock: 65000
>[  211.136029] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[  211.136029] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[  211.136029] [drm:intel_calculate_wm], FIFO entries required for mode: 20
>[  211.136029] [drm:intel_calculate_wm], FIFO watermark level: 6
>[  211.136029] [drm:intel_calculate_wm], FIFO entries required for mode: 0
>[  211.136029] [drm:intel_calculate_wm], FIFO watermark level: 29
>[  211.136029] [drm:i9xx_update_wm], FIFO watermarks - A: 6, B: 29
>[  211.136029] [drm:i9xx_update_wm], self-refresh entries: 25
>[  211.136029] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 6, B: 29, C: 2, SR 70
>[  211.136029] [drm:intel_update_watermarks], plane A (pipe 1) clock: 65000
>[  211.136029] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[  211.136029] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[  211.136029] [drm:intel_calculate_wm], FIFO entries required for mode: 20
>[  211.136029] [drm:intel_calculate_wm], FIFO watermark level: 6
>[  211.136029] [drm:intel_calculate_wm], FIFO entries required for mode: 0
>[  211.136029] [drm:intel_calculate_wm], FIFO watermark level: 29
>[  211.136029] [drm:i9xx_update_wm], FIFO watermarks - A: 6, B: 29
>[  211.136029] [drm:i9xx_update_wm], self-refresh entries: 25
>[  211.136029] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 6, B: 29, C: 2, SR 70
>[  211.136029] [drm:intel_update_watermarks], plane A (pipe 1) clock: 65000
>[  211.136029] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[  211.136029] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[  211.136029] [drm:intel_calculate_wm], FIFO entries required for mode: 20
>[  211.136029] [drm:intel_calculate_wm], FIFO watermark level: 6
>[  211.136029] [drm:intel_calculate_wm], FIFO entries required for mode: 0
>[  211.136029] [drm:intel_calculate_wm], FIFO watermark level: 29
>[  211.136029] [drm:i9xx_update_wm], FIFO watermarks - A: 6, B: 29
>[  211.136029] [drm:i9xx_update_wm], self-refresh entries: 25
>[  211.136029] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 6, B: 29, C: 2, SR 70
>[  212.672586] ata1.00: ACPI cmd ef/02:00:00:00:00:a0 (SET FEATURES) succeeded
>[  212.672586] ata1.00: ACPI cmd f5/00:00:00:00:00:a0 (SECURITY FREEZE LOCK) filtered out
>[  212.677902] ata1.00: ACPI cmd ef/03:45:00:00:00:a0 (SET FEATURES) filtered out
>[  212.683180] ata1.00: ACPI cmd ef/03:0c:00:00:00:a0 (SET FEATURES) filtered out
>[  212.688590] ata1.00: ACPI cmd ef/5f:00:00:00:00:a0 (SET FEATURES) succeeded
>[  212.712420] ata1.00: configured for UDMA/100
>[  212.740409] ata1.00: configured for UDMA/100
>[  212.745595] ata1: EH complete
>[  212.910739] PM: resume of devices complete after 2462.020 msecs
>[  212.916006] Restarting tasks ... done.
>[  212.964009] video LNXVIDEO:00: Restoring backlight state
>[  213.040006] [drm:drm_crtc_helper_set_config], 
>[  213.040006] [drm:drm_crtc_helper_set_config], crtc: f68aa000 4 fb: f61b42c0 connectors: f6375e40 num_connectors: 1 (x, y) (0, 0)
>[  213.040006] [drm:drm_crtc_helper_set_config], setting connector 7 crtc to f68aa000
>[  213.040006] [drm:intel_pipe_set_base], Writing base 00C00000 00000000 0 0 4096
>[  213.064010] [drm:drm_mode_getconnector], connector id 5:
>[  213.064010] [drm:drm_helper_probe_single_connector_modes], VGA-1
>[  213.072009] [drm:intel_update_watermarks], plane B (pipe 0) clock: 31500
>[  213.072009] [drm:intel_update_watermarks], plane A (pipe 1) clock: 65000
>[  213.072009] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[  213.072009] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[  213.072009] [drm:intel_calculate_wm], FIFO entries required for mode: 20
>[  213.072009] [drm:intel_calculate_wm], FIFO watermark level: 6
>[  213.072009] [drm:intel_calculate_wm], FIFO entries required for mode: 9
>[  213.072009] [drm:intel_calculate_wm], FIFO watermark level: 20
>[  213.072009] [drm:i9xx_update_wm], FIFO watermarks - A: 6, B: 20
>[  213.072009] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 6, B: 20, C: 2, SR 1
>[  213.096006] [drm:intel_crtc_mode_set], Mode for pipe A:
>[  213.096006] [drm:drm_mode_debug_printmodeline], Modeline 0:"640x480" 0 31500 640 664 704 832 480 489 491 520 0x10 0xa
>[  213.120006] [drm:intel_pipe_set_base], No FB bound
>[  213.120006] [drm:intel_update_watermarks], plane B (pipe 0) clock: 31500
>[  213.120006] [drm:intel_update_watermarks], plane A (pipe 1) clock: 65000
>[  213.120006] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[  213.120006] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[  213.120006] [drm:intel_calculate_wm], FIFO entries required for mode: 20
>[  213.120006] [drm:intel_calculate_wm], FIFO watermark level: 6
>[  213.120006] [drm:intel_calculate_wm], FIFO entries required for mode: 9
>[  213.120006] [drm:intel_calculate_wm], FIFO watermark level: 20
>[  213.120006] [drm:i9xx_update_wm], FIFO watermarks - A: 6, B: 20
>[  213.120006] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 6, B: 20, C: 2, SR 1
>[  213.120006] [drm:intel_update_watermarks], plane B (pipe 0) clock: 31500
>[  213.120006] [drm:intel_update_watermarks], plane A (pipe 1) clock: 65000
>[  213.120006] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[  213.120006] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[  213.120006] [drm:intel_calculate_wm], FIFO entries required for mode: 20
>[  213.120006] [drm:intel_calculate_wm], FIFO watermark level: 6
>[  213.120006] [drm:intel_calculate_wm], FIFO entries required for mode: 9
>[  213.120006] [drm:intel_calculate_wm], FIFO watermark level: 20
>[  213.120006] [drm:i9xx_update_wm], FIFO watermarks - A: 6, B: 20
>[  213.120006] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 6, B: 20, C: 2, SR 1
>[  213.168008] [drm:intel_update_watermarks], plane A (pipe 1) clock: 65000
>[  213.168008] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[  213.168008] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[  213.168008] [drm:intel_calculate_wm], FIFO entries required for mode: 20
>[  213.168008] [drm:intel_calculate_wm], FIFO watermark level: 6
>[  213.168008] [drm:intel_calculate_wm], FIFO entries required for mode: 0
>[  213.168008] [drm:intel_calculate_wm], FIFO watermark level: 29
>[  213.168008] [drm:i9xx_update_wm], FIFO watermarks - A: 6, B: 29
>[  213.168008] [drm:i9xx_update_wm], self-refresh entries: 25
>[  213.168008] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 6, B: 29, C: 2, SR 70
>[  213.192008] [drm:drm_helper_probe_single_connector_modes], VGA-1 is disconnected
>[  213.192008] [drm:drm_mode_getconnector], connector id 5:
>[  213.192008] [drm:drm_helper_probe_single_connector_modes], VGA-1
>[  213.200009] [drm:intel_update_watermarks], plane B (pipe 0) clock: 31500
>[  213.200009] [drm:intel_update_watermarks], plane A (pipe 1) clock: 65000
>[  213.200009] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[  213.200009] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[  213.200009] [drm:intel_calculate_wm], FIFO entries required for mode: 20
>[  213.200009] [drm:intel_calculate_wm], FIFO watermark level: 6
>[  213.200009] [drm:intel_calculate_wm], FIFO entries required for mode: 9
>[  213.200009] [drm:intel_calculate_wm], FIFO watermark level: 20
>[  213.200009] [drm:i9xx_update_wm], FIFO watermarks - A: 6, B: 20
>[  213.200009] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 6, B: 20, C: 2, SR 1
>[  213.224007] [drm:intel_crtc_mode_set], Mode for pipe A:
>[  213.224007] [drm:drm_mode_debug_printmodeline], Modeline 0:"640x480" 0 31500 640 664 704 832 480 489 491 520 0x10 0xa
>[  213.248007] [drm:intel_pipe_set_base], No FB bound
>[  213.248007] [drm:intel_update_watermarks], plane B (pipe 0) clock: 31500
>[  213.248007] [drm:intel_update_watermarks], plane A (pipe 1) clock: 65000
>[  213.248007] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[  213.248007] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[  213.248007] [drm:intel_calculate_wm], FIFO entries required for mode: 20
>[  213.248007] [drm:intel_calculate_wm], FIFO watermark level: 6
>[  213.248007] [drm:intel_calculate_wm], FIFO entries required for mode: 9
>[  213.248007] [drm:intel_calculate_wm], FIFO watermark level: 20
>[  213.248007] [drm:i9xx_update_wm], FIFO watermarks - A: 6, B: 20
>[  213.248007] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 6, B: 20, C: 2, SR 1
>[  213.248007] [drm:intel_update_watermarks], plane B (pipe 0) clock: 31500
>[  213.248007] [drm:intel_update_watermarks], plane A (pipe 1) clock: 65000
>[  213.248007] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[  213.248007] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[  213.248007] [drm:intel_calculate_wm], FIFO entries required for mode: 20
>[  213.248007] [drm:intel_calculate_wm], FIFO watermark level: 6
>[  213.248007] [drm:intel_calculate_wm], FIFO entries required for mode: 9
>[  213.248007] [drm:intel_calculate_wm], FIFO watermark level: 20
>[  213.248007] [drm:i9xx_update_wm], FIFO watermarks - A: 6, B: 20
>[  213.248007] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 6, B: 20, C: 2, SR 1
>[  213.296007] [drm:intel_update_watermarks], plane A (pipe 1) clock: 65000
>[  213.296007] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[  213.296007] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[  213.296007] [drm:intel_calculate_wm], FIFO entries required for mode: 20
>[  213.296007] [drm:intel_calculate_wm], FIFO watermark level: 6
>[  213.296007] [drm:intel_calculate_wm], FIFO entries required for mode: 0
>[  213.296007] [drm:intel_calculate_wm], FIFO watermark level: 29
>[  213.296007] [drm:i9xx_update_wm], FIFO watermarks - A: 6, B: 29
>[  213.296007] [drm:i9xx_update_wm], self-refresh entries: 25
>[  213.296007] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 6, B: 29, C: 2, SR 70
>[  213.320006] [drm:drm_helper_probe_single_connector_modes], VGA-1 is disconnected
>[  213.320006] [drm:drm_mode_getconnector], connector id 7:
>[  213.320006] [drm:drm_helper_probe_single_connector_modes], LVDS-1
>[  213.320006] [drm:drm_helper_probe_single_connector_modes], Probed modes for LVDS-1
>[  213.320006] [drm:drm_mode_debug_printmodeline], Modeline 26:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x8 0xa
>[  213.320006] [drm:drm_mode_getconnector], connector id 7:
>[  213.320006] [drm:drm_mode_getconnector], connector id 11:
>[  213.320006] [drm:drm_helper_probe_single_connector_modes], SVIDEO-1
>[  213.320006] [drm:intel_update_watermarks], plane B (pipe 0) clock: 107520
>[  213.320006] [drm:intel_update_watermarks], plane A (pipe 1) clock: 65000
>[  213.320006] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[  213.320006] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[  213.320006] [drm:intel_calculate_wm], FIFO entries required for mode: 20
>[  213.320006] [drm:intel_calculate_wm], FIFO watermark level: 6
>[  213.320006] [drm:intel_calculate_wm], FIFO entries required for mode: 33
>[  213.320006] [drm:intel_calculate_wm], FIFO watermark level: -4
>[  213.320006] [drm:i9xx_update_wm], FIFO watermarks - A: 6, B: 1
>[  213.320006] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 6, B: 1, C: 2, SR 1
>[  213.344007] [drm:intel_crtc_mode_set], Mode for pipe A:
>[  213.344007] [drm:drm_mode_debug_printmodeline], Modeline 0:"NTSC 480i" 0 107520 1280 1368 1496 1712 1024 1027 1034 1104 0x40 0x0
>[  213.368007] [drm:intel_pipe_set_base], No FB bound
>[  213.368007] [drm:intel_update_watermarks], plane B (pipe 0) clock: 107520
>[  213.368007] [drm:intel_update_watermarks], plane A (pipe 1) clock: 65000
>[  213.368007] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[  213.368007] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[  213.368007] [drm:intel_calculate_wm], FIFO entries required for mode: 20
>[  213.368007] [drm:intel_calculate_wm], FIFO watermark level: 6
>[  213.368007] [drm:intel_calculate_wm], FIFO entries required for mode: 33
>[  213.368007] [drm:intel_calculate_wm], FIFO watermark level: -4
>[  213.368007] [drm:i9xx_update_wm], FIFO watermarks - A: 6, B: 1
>[  213.368007] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 6, B: 1, C: 2, SR 1
>[  213.392006] [drm:intel_update_watermarks], plane B (pipe 0) clock: 107520
>[  213.392006] [drm:intel_update_watermarks], plane A (pipe 1) clock: 65000
>[  213.392006] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[  213.392006] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[  213.392006] [drm:intel_calculate_wm], FIFO entries required for mode: 20
>[  213.392006] [drm:intel_calculate_wm], FIFO watermark level: 6
>[  213.392006] [drm:intel_calculate_wm], FIFO entries required for mode: 33
>[  213.392006] [drm:intel_calculate_wm], FIFO watermark level: -4
>[  213.392006] [drm:i9xx_update_wm], FIFO watermarks - A: 6, B: 1
>[  213.392006] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 6, B: 1, C: 2, SR 1
>[  213.464006] [drm:intel_tv_detect_type], No TV connection detected
>[  213.464006] [drm:intel_update_watermarks], plane A (pipe 1) clock: 65000
>[  213.464006] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[  213.464006] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[  213.464006] [drm:intel_calculate_wm], FIFO entries required for mode: 20
>[  213.464006] [drm:intel_calculate_wm], FIFO watermark level: 6
>[  213.464006] [drm:intel_calculate_wm], FIFO entries required for mode: 0
>[  213.464006] [drm:intel_calculate_wm], FIFO watermark level: 29
>[  213.464006] [drm:i9xx_update_wm], FIFO watermarks - A: 6, B: 29
>[  213.464006] [drm:i9xx_update_wm], self-refresh entries: 25
>[  213.464006] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 6, B: 29, C: 2, SR 70
>[  213.488006] [drm:drm_helper_probe_single_connector_modes], SVIDEO-1 is disconnected
>[  213.488006] [drm:drm_mode_getconnector], connector id 11:
>[  213.488006] [drm:drm_helper_probe_single_connector_modes], SVIDEO-1
>[  213.488006] [drm:intel_update_watermarks], plane B (pipe 0) clock: 107520
>[  213.488006] [drm:intel_update_watermarks], plane A (pipe 1) clock: 65000
>[  213.488006] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[  213.488006] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[  213.488006] [drm:intel_calculate_wm], FIFO entries required for mode: 20
>[  213.488006] [drm:intel_calculate_wm], FIFO watermark level: 6
>[  213.488006] [drm:intel_calculate_wm], FIFO entries required for mode: 33
>[  213.488006] [drm:intel_calculate_wm], FIFO watermark level: -4
>[  213.488006] [drm:i9xx_update_wm], FIFO watermarks - A: 6, B: 1
>[  213.488006] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 6, B: 1, C: 2, SR 1
>[  213.512007] [drm:intel_crtc_mode_set], Mode for pipe A:
>[  213.512007] [drm:drm_mode_debug_printmodeline], Modeline 0:"NTSC 480i" 0 107520 1280 1368 1496 1712 1024 1027 1034 1104 0x40 0x0
>[  213.536007] [drm:intel_pipe_set_base], No FB bound
>[  213.536007] [drm:intel_update_watermarks], plane B (pipe 0) clock: 107520
>[  213.536007] [drm:intel_update_watermarks], plane A (pipe 1) clock: 65000
>[  213.536007] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[  213.536007] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[  213.536007] [drm:intel_calculate_wm], FIFO entries required for mode: 20
>[  213.536007] [drm:intel_calculate_wm], FIFO watermark level: 6
>[  213.536007] [drm:intel_calculate_wm], FIFO entries required for mode: 33
>[  213.536007] [drm:intel_calculate_wm], FIFO watermark level: -4
>[  213.536007] [drm:i9xx_update_wm], FIFO watermarks - A: 6, B: 1
>[  213.536007] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 6, B: 1, C: 2, SR 1
>[  213.560006] [drm:intel_update_watermarks], plane B (pipe 0) clock: 107520
>[  213.560006] [drm:intel_update_watermarks], plane A (pipe 1) clock: 65000
>[  213.560006] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[  213.560006] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[  213.560006] [drm:intel_calculate_wm], FIFO entries required for mode: 20
>[  213.560006] [drm:intel_calculate_wm], FIFO watermark level: 6
>[  213.560006] [drm:intel_calculate_wm], FIFO entries required for mode: 33
>[  213.560006] [drm:intel_calculate_wm], FIFO watermark level: -4
>[  213.560006] [drm:i9xx_update_wm], FIFO watermarks - A: 6, B: 1
>[  213.560006] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 6, B: 1, C: 2, SR 1
>[  213.632007] [drm:intel_tv_detect_type], No TV connection detected
>[  213.632007] [drm:intel_update_watermarks], plane A (pipe 1) clock: 65000
>[  213.632007] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[  213.632007] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[  213.632007] [drm:intel_calculate_wm], FIFO entries required for mode: 20
>[  213.632007] [drm:intel_calculate_wm], FIFO watermark level: 6
>[  213.632007] [drm:intel_calculate_wm], FIFO entries required for mode: 0
>[  213.632007] [drm:intel_calculate_wm], FIFO watermark level: 29
>[  213.632007] [drm:i9xx_update_wm], FIFO watermarks - A: 6, B: 29
>[  213.632007] [drm:i9xx_update_wm], self-refresh entries: 25
>[  213.632007] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 6, B: 29, C: 2, SR 70
>[  213.656007] [drm:drm_helper_probe_single_connector_modes], SVIDEO-1 is disconnected
>[  213.664011] [drm:intel_crtc_cursor_set], 
>[  214.212004] [drm:intel_update_watermarks], plane B (pipe 0) clock: 31500
>[  214.212004] [drm:intel_update_watermarks], plane A (pipe 1) clock: 65000
>[  214.212004] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[  214.212004] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[  214.212004] [drm:intel_calculate_wm], FIFO entries required for mode: 20
>[  214.212004] [drm:intel_calculate_wm], FIFO watermark level: 6
>[  214.212004] [drm:intel_calculate_wm], FIFO entries required for mode: 9
>[  214.212004] [drm:intel_calculate_wm], FIFO watermark level: 20
>[  214.212004] [drm:i9xx_update_wm], FIFO watermarks - A: 6, B: 20
>[  214.212004] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 6, B: 20, C: 2, SR 1
>[  214.236006] [drm:intel_crtc_mode_set], Mode for pipe A:
>[  214.236006] [drm:drm_mode_debug_printmodeline], Modeline 0:"640x480" 0 31500 640 664 704 832 480 489 491 520 0x10 0xa
>[  214.260006] [drm:intel_pipe_set_base], No FB bound
>[  214.260006] [drm:intel_update_watermarks], plane B (pipe 0) clock: 31500
>[  214.260006] [drm:intel_update_watermarks], plane A (pipe 1) clock: 65000
>[  214.260006] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[  214.260006] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[  214.260006] [drm:intel_calculate_wm], FIFO entries required for mode: 20
>[  214.260006] [drm:intel_calculate_wm], FIFO watermark level: 6
>[  214.260006] [drm:intel_calculate_wm], FIFO entries required for mode: 9
>[  214.260006] [drm:intel_calculate_wm], FIFO watermark level: 20
>[  214.260006] [drm:i9xx_update_wm], FIFO watermarks - A: 6, B: 20
>[  214.260006] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 6, B: 20, C: 2, SR 1
>[  214.260006] [drm:intel_update_watermarks], plane B (pipe 0) clock: 31500
>[  214.260006] [drm:intel_update_watermarks], plane A (pipe 1) clock: 65000
>[  214.260006] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[  214.260006] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[  214.260006] [drm:intel_calculate_wm], FIFO entries required for mode: 20
>[  214.260006] [drm:intel_calculate_wm], FIFO watermark level: 6
>[  214.260006] [drm:intel_calculate_wm], FIFO entries required for mode: 9
>[  214.260006] [drm:intel_calculate_wm], FIFO watermark level: 20
>[  214.260006] [drm:i9xx_update_wm], FIFO watermarks - A: 6, B: 20
>[  214.260006] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 6, B: 20, C: 2, SR 1
>[  214.308004] [drm:intel_update_watermarks], plane A (pipe 1) clock: 65000
>[  214.308004] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[  214.308004] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[  214.308004] [drm:intel_calculate_wm], FIFO entries required for mode: 20
>[  214.308004] [drm:intel_calculate_wm], FIFO watermark level: 6
>[  214.308004] [drm:intel_calculate_wm], FIFO entries required for mode: 0
>[  214.308004] [drm:intel_calculate_wm], FIFO watermark level: 29
>[  214.308004] [drm:i9xx_update_wm], FIFO watermarks - A: 6, B: 29
>[  214.308004] [drm:i9xx_update_wm], self-refresh entries: 25
>[  214.308004] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 6, B: 29, C: 2, SR 70
>[  222.188009] [drm:intel_crtc_cursor_set], 
>[  222.188009] [drm:intel_crtc_cursor_set], cursor off
>[  223.616696] [drm:intel_crtc_cursor_set], 
>[  224.356009] [drm:intel_update_watermarks], plane B (pipe 0) clock: 31500
>[  224.356009] [drm:intel_update_watermarks], plane A (pipe 1) clock: 65000
>[  224.356009] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[  224.356009] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[  224.356009] [drm:intel_calculate_wm], FIFO entries required for mode: 20
>[  224.356009] [drm:intel_calculate_wm], FIFO watermark level: 6
>[  224.356009] [drm:intel_calculate_wm], FIFO entries required for mode: 9
>[  224.356009] [drm:intel_calculate_wm], FIFO watermark level: 20
>[  224.356009] [drm:i9xx_update_wm], FIFO watermarks - A: 6, B: 20
>[  224.356009] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 6, B: 20, C: 2, SR 1
>[  224.380019] [drm:intel_crtc_mode_set], Mode for pipe A:
>[  224.380019] [drm:drm_mode_debug_printmodeline], Modeline 0:"640x480" 0 31500 640 664 704 832 480 489 491 520 0x10 0xa
>[  224.404061] [drm:intel_pipe_set_base], No FB bound
>[  224.404061] [drm:intel_update_watermarks], plane B (pipe 0) clock: 31500
>[  224.404061] [drm:intel_update_watermarks], plane A (pipe 1) clock: 65000
>[  224.404061] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[  224.404061] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[  224.404061] [drm:intel_calculate_wm], FIFO entries required for mode: 20
>[  224.404061] [drm:intel_calculate_wm], FIFO watermark level: 6
>[  224.404061] [drm:intel_calculate_wm], FIFO entries required for mode: 9
>[  224.404061] [drm:intel_calculate_wm], FIFO watermark level: 20
>[  224.404061] [drm:i9xx_update_wm], FIFO watermarks - A: 6, B: 20
>[  224.404061] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 6, B: 20, C: 2, SR 1
>[  224.404061] [drm:intel_update_watermarks], plane B (pipe 0) clock: 31500
>[  224.404061] [drm:intel_update_watermarks], plane A (pipe 1) clock: 65000
>[  224.404061] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[  224.404061] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[  224.404061] [drm:intel_calculate_wm], FIFO entries required for mode: 20
>[  224.404061] [drm:intel_calculate_wm], FIFO watermark level: 6
>[  224.404061] [drm:intel_calculate_wm], FIFO entries required for mode: 9
>[  224.404061] [drm:intel_calculate_wm], FIFO watermark level: 20
>[  224.404061] [drm:i9xx_update_wm], FIFO watermarks - A: 6, B: 20
>[  224.404061] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 6, B: 20, C: 2, SR 1
>[  224.452059] [drm:intel_update_watermarks], plane A (pipe 1) clock: 65000
>[  224.452059] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) A: 28
>[  224.452059] [drm:i9xx_get_fifo_size], FIFO size - (0x00001d9c) B: 31
>[  224.452059] [drm:intel_calculate_wm], FIFO entries required for mode: 20
>[  224.452059] [drm:intel_calculate_wm], FIFO watermark level: 6
>[  224.452059] [drm:intel_calculate_wm], FIFO entries required for mode: 0
>[  224.452059] [drm:intel_calculate_wm], FIFO watermark level: 29
>[  224.452059] [drm:i9xx_update_wm], FIFO watermarks - A: 6, B: 29
>[  224.452059] [drm:i9xx_update_wm], self-refresh entries: 25
>[  224.452059] [drm:i9xx_update_wm], Setting FIFO watermarks - A: 6, B: 29, C: 2, SR 70
>[  224.831905] [drm:intel_crtc_cursor_set], 
>[  224.831905] [drm:intel_crtc_cursor_set], cursor off

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Attachments on bug 26744: 33545 | 33546 | 33547 | 33577 | 33578 | 34097 | 34388 | 34389 | 36019 | 37360 | 37367 | 37381

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