Attachment 37680 Details for Bug 29441 – register state prior to forcing DMPS off

intel_reg_dumper.before.dpms.off.txt (text/plain), 8.74 KB, created by Brian Hall on 2010-08-07 15:16:20 UTC

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Creator: Brian Hall

Created: 2010-08-07 15:16:20 UTC

Size: 8.74 KB

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obsolete

>                 DCC: 0x00200010 (single channel, XOR randomization: enabled, XOR bit: 11)
>           CHDECMISC: 0x000000a4 (XOR bank/rank, ch2 enh disabled, ch1 enh disabled, ch0 enh enabled, flex disabled, ep not present)
>              C0DRB0: 0x00200010 (0x0010)
>              C0DRB1: 0x00300020 (0x0020)
>              C0DRB2: 0x00400030 (0x0030)
>              C0DRB3: 0x86860040 (0x0040)
>              C1DRB0: 0x00000000 (0x0000)
>              C1DRB1: 0x00000000 (0x0000)
>              C1DRB2: 0x00000000 (0x0000)
>              C1DRB3: 0x00000000 (0x0000)
>             C0DRA01: 0x86868686 (0x8686)
>             C0DRA23: 0x00008686 (0x8686)
>             C1DRA01: 0x00000000 (0x0000)
>             C1DRA23: 0x00000000 (0x0000)
>          PGETBL_CTL: 0x00000001
>   VCLK_DIVISOR_VGA0: 0x00200074 (n = 32, m1 = 0, m2 = 52)
>   VCLK_DIVISOR_VGA1: 0x00200074 (n = 32, m1 = 0, m2 = 52)
>       VCLK_POST_DIV: 0x00800100 (vga0 p1 = 2, p2 = 2, vga1 p1 = 3, p2 = 2)
>           DPLL_TEST: 0x00010001 ()
>        CACHE_MODE_0: 0x00006820
>             D_STATE: 0x0000000b
>       DSPCLK_GATE_D: 0x00000000 (clock gates disabled:)
>      RENCLK_GATE_D1: 0x00000000
>      RENCLK_GATE_D2: 0x00000000
>               SDVOB: 0x00300000 (disabled, pipe A, stall disabled, not detected)
>               SDVOC: 0x00300000 (disabled, pipe A, stall disabled, not detected)
>             SDVOUDI: 0x00000000
>              DSPARB: 0x00001d9c
>              DSPFW1: 0xf1030f0f
>              DSPFW2: 0x0000030f
>              DSPFW3: 0x6400012c
>                ADPA: 0x80000008 (enabled, pipe A, +hsync, -vsync)
>                LVDS: 0x40000000 (disabled, pipe B, 18 bit, 1 channel)
>                DVOA: 0x00000000 (disabled, pipe A, no stall, -hsync, -vsync)
>                DVOB: 0x00300000 (disabled, pipe A, no stall, -hsync, -vsync)
>                DVOC: 0x00300000 (disabled, pipe A, no stall, -hsync, -vsync)
>         DVOA_SRCDIM: 0x00000000
>         DVOB_SRCDIM: 0x00000000
>         DVOC_SRCDIM: 0x00000000
>          PP_CONTROL: 0x00000000 (power target: off)
>           PP_STATUS: 0x00000000 (off, not ready, sequencing idle)
>        PP_ON_DELAYS: 0x00000000
>       PP_OFF_DELAYS: 0x00000000
>          PP_DIVISOR: 0x00270f04
>        PFIT_CONTROL: 0x00000000
>     PFIT_PGM_RATIOS: 0x00000000
>     PORT_HOTPLUG_EN: 0x00000220
>   PORT_HOTPLUG_STAT: 0x00001300
>            DSPACNTR: 0x18000000 (disabled, pipe A)
>          DSPASTRIDE: 0x00000c80 (3200 bytes)
>             DSPAPOS: 0x00000000 (0, 0)
>            DSPASIZE: 0x0257031f (800, 600)
>            DSPABASE: 0x00000000
>            DSPASURF: 0x00000000
>         DSPATILEOFF: 0x00000000
>           PIPEACONF: 0x80000000 (enabled, single-wide)
>            PIPEASRC: 0x063f0383 (1600, 900)
>           PIPEASTAT: 0x00000203 (status: VSYNC_INT_STATUS VBLANK_INT_STATUS OREG_UPDATE_STATUS)
>   PIPEA_GMCH_DATA_M: 0x00000000
>   PIPEA_GMCH_DATA_N: 0x00000000
>     PIPEA_DP_LINK_M: 0x00000000
>     PIPEA_DP_LINK_N: 0x00000000
>       CURSOR_A_BASE: 0x00000000
>    CURSOR_A_CONTROL: 0x00000000
>   CURSOR_A_POSITION: 0x01e0016a
>                FPA0: 0x0008003b (n = 8, m1 = 0, m2 = 59)
>                FPA1: 0x0008003b (n = 8, m1 = 0, m2 = 59)
>              DPLL_A: 0x94010000 (enabled, non-dvo, default clock, DAC/serial mode, p1 = 2, p2 = 10, SDVO mult 1)
>           DPLL_A_MD: 0x00000000
>            HTOTAL_A: 0x06df063f (1600 active, 1760 total)
>            HBLANK_A: 0x06df063f (1600 start, 1760 end)
>             HSYNC_A: 0x068f066f (1648 start, 1680 end)
>            VTOTAL_A: 0x039d0383 (900 active, 926 total)
>            VBLANK_A: 0x039d0383 (900 start, 926 end)
>             VSYNC_A: 0x038b0386 (903 start, 908 end)
>           BCLRPAT_A: 0x00000000
>        VSYNCSHIFT_A: 0x00000000
>            DSPBCNTR: 0xd8000000 (enabled, pipe A)
>          DSPBSTRIDE: 0x00002000 (8192 bytes)
>             DSPBPOS: 0x00000000 (0, 0)
>            DSPBSIZE: 0x0383063f (1600, 900)
>            DSPBBASE: 0x01000000
>            DSPBSURF: 0x00000000
>         DSPBTILEOFF: 0x00000000
>           PIPEBCONF: 0x00000000 (disabled, single-wide)
>            PIPEBSRC: 0x027f01df (640, 480)
>           PIPEBSTAT: 0x00400000 (status: LBLC_EVENT_ENABLE)
>   PIPEB_GMCH_DATA_M: 0x00000000
>   PIPEB_GMCH_DATA_N: 0x00000000
>     PIPEB_DP_LINK_M: 0x00000000
>     PIPEB_DP_LINK_N: 0x00000000
>       CURSOR_B_BASE: 0x00000000
>    CURSOR_B_CONTROL: 0x00000000
>   CURSOR_B_POSITION: 0x00000000
>                FPB0: 0x00200074 (n = 32, m1 = 0, m2 = 52)
>                FPB1: 0x00200074 (n = 32, m1 = 0, m2 = 52)
>              DPLL_B: 0x04800000 (disabled, non-dvo, VGA, default clock, DAC/serial mode, p1 = 9, p2 = 10, SDVO mult 1)
>           DPLL_B_MD: 0x00000000
>            HTOTAL_B: 0x031f027f (640 active, 800 total)
>            HBLANK_B: 0x03170287 (648 start, 792 end)
>             HSYNC_B: 0x02ef028f (656 start, 752 end)
>            VTOTAL_B: 0x020c01df (480 active, 525 total)
>            VBLANK_B: 0x020401e7 (488 start, 517 end)
>             VSYNC_B: 0x01eb01e9 (490 start, 492 end)
>           BCLRPAT_B: 0x00000000
>        VSYNCSHIFT_B: 0x00000000
>   VCLK_DIVISOR_VGA0: 0x00200074
>   VCLK_DIVISOR_VGA1: 0x00200074
>       VCLK_POST_DIV: 0x00800100
>            VGACNTRL: 0x80000000 (disabled)
>              TV_CTL: 0x00000000
>              TV_DAC: 0x00000000
>            TV_CSC_Y: 0x00000000
>           TV_CSC_Y2: 0x00000000
>            TV_CSC_U: 0x00000000
>           TV_CSC_U2: 0x00000000
>            TV_CSC_V: 0x00000000
>           TV_CSC_V2: 0x00000000
>        TV_CLR_KNOBS: 0x00000000
>        TV_CLR_LEVEL: 0x00000000
>          TV_H_CTL_1: 0x00000000
>          TV_H_CTL_2: 0x00000000
>          TV_H_CTL_3: 0x00000000
>          TV_V_CTL_1: 0x00000000
>          TV_V_CTL_2: 0x00000000
>          TV_V_CTL_3: 0x00000000
>          TV_V_CTL_4: 0x00000000
>          TV_V_CTL_5: 0x00000000
>          TV_V_CTL_6: 0x00000000
>          TV_V_CTL_7: 0x00000000
>         TV_SC_CTL_1: 0x00000000
>         TV_SC_CTL_2: 0x00000000
>         TV_SC_CTL_3: 0x00000000
>          TV_WIN_POS: 0x00000000
>         TV_WIN_SIZE: 0x00000000
>     TV_FILTER_CTL_1: 0x00000000
>     TV_FILTER_CTL_2: 0x00000000
>     TV_FILTER_CTL_3: 0x00000000
>       TV_CC_CONTROL: 0x00000000
>          TV_CC_DATA: 0x00000000
>         TV_H_LUMA_0: 0x00000000
>        TV_H_LUMA_59: 0x00000000
>       TV_H_CHROMA_0: 0x00000000
>      TV_H_CHROMA_59: 0x00000000
>        FBC_CFB_BASE: 0xffffffff
>         FBC_LL_BASE: 0xffffffff
>         FBC_CONTROL: 0xffffffff
>         FBC_COMMAND: 0xffffffff
>          FBC_STATUS: 0xffffffff
>        FBC_CONTROL2: 0xffffffff
>       FBC_FENCE_OFF: 0xffffffff
>         FBC_MOD_NUM: 0xffffffff
>             MI_MODE: 0x00000200
>        MI_ARB_STATE: 0x00000840
>      MI_RDRET_STATE: 0x00000000
>             ECOSKPD: 0x00000307
>                DP_B: 0x00000000
>      DPB_AUX_CH_CTL: 0x00000000
>    DPB_AUX_CH_DATA1: 0x00000000
>    DPB_AUX_CH_DATA2: 0x00000000
>    DPB_AUX_CH_DATA3: 0x00000000
>    DPB_AUX_CH_DATA4: 0x00000000
>    DPB_AUX_CH_DATA5: 0x00000000
>                DP_C: 0x00000000
>      DPC_AUX_CH_CTL: 0x00000000
>    DPC_AUX_CH_DATA1: 0x00000000
>    DPC_AUX_CH_DATA2: 0x00000000
>    DPC_AUX_CH_DATA3: 0x00000000
>    DPC_AUX_CH_DATA4: 0x00000000
>    DPC_AUX_CH_DATA5: 0x00000000
>                DP_D: 0x00000000
>      DPD_AUX_CH_CTL: 0x00000000
>    DPD_AUX_CH_DATA1: 0x00000000
>    DPD_AUX_CH_DATA2: 0x00000000
>    DPD_AUX_CH_DATA3: 0x00000000
>    DPD_AUX_CH_DATA4: 0x00000000
>    DPD_AUX_CH_DATA5: 0x00000000
>          AUD_CONFIG: 0x00000000
>    AUD_HDMIW_STATUS: 0x00000000
>      AUD_CONV_CHCNT: 0x00000000
>       VIDEO_DIP_CTL: 0x00000000
>       AUD_PINW_CNTR: 0x00000000
>         AUD_CNTL_ST: 0x00000000
>         AUD_PIN_CAP: 0x00000000
>        AUD_PINW_CAP: 0x00000000
>  AUD_PINW_UNSOLRESP: 0x00000000
>    AUD_OUT_DIG_CNVT: 0x00000000
>       AUD_OUT_CWCAP: 0x00000000
>         AUD_GRP_CAP: 0x00000000
>            FENCE  0: 0x01000341 (enabled, X tiled, 8192 pitch, 0x01000000 - 0x01800000 (8192kb))
>            FENCE  1: 0x01800341 (enabled, X tiled, 8192 pitch, 0x01800000 - 0x02000000 (8192kb))
>            FENCE  2: 0x02000231 (enabled, X tiled, 4096 pitch, 0x02000000 - 0x02400000 (4096kb))
>            FENCE  3: 0x02800341 (enabled, X tiled, 8192 pitch, 0x02800000 - 0x03000000 (8192kb))
>            FENCE  4: 0x03800011 (enabled, X tiled, 1024 pitch, 0x03800000 - 0x03900000 (1024kb))
>            FENCE  5: 0x00000000 (disabled)
>            FENCE  6: 0x05000341 (enabled, X tiled, 8192 pitch, 0x05000000 - 0x05800000 (8192kb))
>            FENCE  7: 0x00000000 (disabled)
>            FENCE  8: 0x00000000 (disabled)
>            FENCE  9: 0x00000000 (disabled)
>           FENCE  10: 0x00000000 (disabled)
>           FENCE  11: 0x00000000 (disabled)
>           FENCE  12: 0x00000000 (disabled)
>           FENCE  13: 0x00000000 (disabled)
>           FENCE  14: 0x00000000 (disabled)
>           FENCE  15: 0x00000000 (disabled)
>             INST_PM: 0x00000000
>pipe A dot 97600 n 3 m1 0 m2 59 p1 2 p2 10
>pipe B dot 25173 n 5 m1 0 m2 116 p1 9 p2 10

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Attachments on bug 29441: 37677 | 37678 | 37679 | 37680 | 37681 | 37699 | 37700 | 37701 | 37703 | 60011

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