Attachment 37688 Details for Bug 29252 – My variant upon Jesse's idea.

[patch] My variant upon Jesse's idea.

0001-drm-i915-Clear-scanline-waits-before-disabling-the-p.patch (text/plain), 3.00 KB, created by Chris Wilson on 2010-08-08 04:03:55 UTC

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Creator: Chris Wilson

Created: 2010-08-08 04:03:55 UTC

Size: 3.00 KB

patch

obsolete

>From 1bc8334823f29d8e947cd2fe7ecb913438f62d5c Mon Sep 17 00:00:00 2001
>From: Chris Wilson <chris@chris-wilson.co.uk>
>Date: Sun, 8 Aug 2010 11:53:53 +0100
>Subject: [PATCH] drm/i915: Clear scanline waits before disabling the pipe.
>
>If we disable the pipe and the GPU is currently waiting on a scanline
>WAIT_FOR_EVENT, the GPU will hang. Fortunately, there is a magic bit
>which we can write on i915+ to break this wait before disabling the
>pipe.
>
>References:
>
>  Bug 29252 - [Arrandale] Hung WAIT_FOR_EVENT when running rss-glx-skyrocket
>  https://bugs.freedesktop.org/show_bug.cgi?id=29252
>
>  Bug 28964 - [i965gm] GPU infinite MI_WAIT_FOR_EVENT while watching video in Totem
>  https://bugs.freedesktop.org/show_bug.cgi?id=28964
>
>and many others.
>
>Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
>Cc: Jesse Barnes <jbarnes@virtuousgeek.org>
>---
> drivers/gpu/drm/i915/i915_reg.h      |    2 ++
> drivers/gpu/drm/i915/intel_display.c |   29 +++++++++++++++++++++++++++--
> 2 files changed, 29 insertions(+), 2 deletions(-)
>
>diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
>index 97a35a4..2953b0d 100644
>--- a/drivers/gpu/drm/i915/i915_reg.h
>+++ b/drivers/gpu/drm/i915/i915_reg.h
>@@ -288,6 +288,8 @@
> #define   RING_VALID_MASK	0x00000001
> #define   RING_VALID		0x00000001
> #define   RING_INVALID		0x00000000
>+#define   RING_WAIT_I8XX	(1<<0) /* gen2, PRBx_HEAD */
>+#define   RING_WAIT		(1<<11) /* gen3+, PRBx_CTL */
> #define PRB1_TAIL	0x02040 /* 915+ only */
> #define PRB1_HEAD	0x02044 /* 915+ only */
> #define PRB1_START	0x02048 /* 915+ only */
>diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
>index 2bb3196..696767c 100644
>--- a/drivers/gpu/drm/i915/intel_display.c
>+++ b/drivers/gpu/drm/i915/intel_display.c
>@@ -2410,6 +2410,28 @@ static int i9xx_crtc_dpms(struct drm_crtc *crtc, int mode)
> 	return 0;
> }
> 
>+/*
>+ * When we disable a pipe, we need to clear any pending scanline wait events
>+ * to avoid hanging the ring, which we assume we are waiting on.
>+ */
>+static void intel_clear_scanline_wait(struct drm_device *dev)
>+{
>+	struct drm_i915_private *dev_priv = dev->dev_private;
>+
>+	if (IS_GEN2(dev)) {
>+		if (I915_READ(PRB0_HEAD) & RING_WAIT_I8XX) {
>+			DRM_INFO("Forcing GPU idle to flush scanline wait");
>+			i915_gpu_idle(dev);
>+		}
>+	} else {
>+		u32 tmp = I915_READ(PRB0_CTL);
>+		if (tmp & RING_WAIT) {
>+			I915_WRITE(PRB0_CTL, tmp);
>+			POSTING_READ(PRB0_CTL);
>+		}
>+	}
>+}
>+
> /**
>  * Sets the power management mode of the pipe and plane.
>  */
>@@ -2429,12 +2451,15 @@ static int intel_crtc_dpms(struct drm_crtc *crtc, int mode)
> 	 * with multiple pipes prior to enabling to new pipe.
> 	 *
> 	 * When switching off the display, make sure the cursor is
>-	 * properly hidden prior to disabling the pipe.
>+	 * properly hidden and there are no pending waits prior to
>+	 * disabling the pipe.
> 	 */
> 	if (mode == DRM_MODE_DPMS_ON)
> 		intel_update_watermarks(dev);
>-	else
>+	else {
> 		intel_crtc_update_cursor(crtc);
>+		intel_clear_scanline_wait(dev);
>+	}
> 
> 	dev_priv->display.dpms(crtc, mode);
> 
>-- 
>1.7.1
>

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