Attachment 38205 Details for Bug 27139 – [PATCH 3/6] RADEONDownloadFromScreenCS: flush CS writes before mapping BO for read

[patch] [PATCH 3/6] RADEONDownloadFromScreenCS: flush CS writes before mapping BO for read

0003-RADEONDownloadFromScreenCS-flush-CS-writes-before-ma.patch (text/plain), 1.84 KB, created by Karl Tomlinson on 2010-08-26 15:26:11 UTC

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Creator: Karl Tomlinson

Created: 2010-08-26 15:26:11 UTC

Size: 1.84 KB

patch

obsolete

>From c486d7eb68edf3b4c7cfd59da50f30898f0b36f2 Mon Sep 17 00:00:00 2001
>From: Karl Tomlinson <karlt+@karlt.net>
>Date: Sun, 22 Aug 2010 20:04:42 +1200
>Subject: [PATCH 3/6] RADEONDownloadFromScreenCS: flush CS writes before mapping BO for read
>
>If unflushed CS operations write to the pixmap BO, then these need to be
>flushed before mapping the BO for read.  This currently only affects big
>endian systems and only when the operation writes to the GTT domain.
>---
> src/radeon_exa_funcs.c |   14 ++++++++++++--
> 1 files changed, 12 insertions(+), 2 deletions(-)
>
>diff --git a/src/radeon_exa_funcs.c b/src/radeon_exa_funcs.c
>index a82e416..d02c787 100644
>--- a/src/radeon_exa_funcs.c
>+++ b/src/radeon_exa_funcs.c
>@@ -567,6 +567,9 @@ RADEONDownloadFromScreenCS(PixmapPtr pSrc, int x, int y, int w,
>     unsigned bpp = pSrc->drawable.bitsPerPixel;
>     uint32_t scratch_pitch = RADEON_ALIGN(w * bpp / 8, 64);
>     uint32_t swap = RADEON_HOST_DATA_SWAP_NONE;
>+#if X_BYTE_ORDER == X_BIG_ENDIAN
>+    Bool flush = FALSE;
>+#endif
>     Bool r;
> 
>     if (bpp < 8)
>@@ -593,6 +596,10 @@ RADEONDownloadFromScreenCS(PixmapPtr pSrc, int x, int y, int w,
> 	if ((src_domain & (RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM)) ==
> 	    (RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM))
> 	    src_domain = 0;
>+#if X_BYTE_ORDER == X_BIG_ENDIAN
>+	else /* A write may be scheduled */
>+	    flush = TRUE;
>+#endif
>     }
> 
>     if (!src_domain)
>@@ -631,11 +638,14 @@ RADEONDownloadFromScreenCS(PixmapPtr pSrc, int x, int y, int w,
>                     scratch_pitch << 16, x, y, 0, 0, w, h,
>                     RADEON_GEM_DOMAIN_VRAM | RADEON_GEM_DOMAIN_GTT,
>                     RADEON_GEM_DOMAIN_GTT);
>-    FLUSH_RING();
>-
> #if X_BYTE_ORDER == X_BIG_ENDIAN
>+    flush = TRUE;
>+
> copy:
>+    if (flush)
> #endif
>+	FLUSH_RING();
>+
>     r = radeon_bo_map(scratch, 0);
>     if (r) {
>         r = FALSE;
>-- 
>1.7.1
>

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Attachments on bug 27139: 34163 | 37900 | 38202 | 38203 | 38204 | 38205 | 38206 | 38207 | 38208

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