Attachment 38473 Details for Bug 29449 – Compilation patch

[patch] Compilation patch

single.patch (text/plain), 51.32 KB, created by Chris Wilson on 2010-09-06 03:50:39 UTC

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Creator: Chris Wilson

Created: 2010-09-06 03:50:39 UTC

Size: 51.32 KB

patch

obsolete

>diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
>index 5c8e534..f6e98dd 100644
>--- a/drivers/gpu/drm/i915/Makefile
>+++ b/drivers/gpu/drm/i915/Makefile
>@@ -26,13 +26,13 @@ i915-y := i915_drv.o i915_dma.o i915_irq.o i915_mem.o \
> 	  intel_dvo.o \
> 	  intel_ringbuffer.o \
> 	  intel_overlay.o \
>+	  intel_opregion.o \
> 	  dvo_ch7xxx.o \
> 	  dvo_ch7017.o \
> 	  dvo_ivch.o \
> 	  dvo_tfp410.o \
> 	  dvo_sil164.o
> 
>-i915-$(CONFIG_ACPI)	+= i915_opregion.o
> i915-$(CONFIG_COMPAT)   += i915_ioc32.o
> 
> obj-$(CONFIG_DRM_I915)  += i915.o
>diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
>index 92d5605..2556aba 100644
>--- a/drivers/gpu/drm/i915/i915_debugfs.c
>+++ b/drivers/gpu/drm/i915/i915_debugfs.c
>@@ -669,6 +669,26 @@ static int i915_gfxec(struct seq_file *m, void *unused)
> 	return 0;
> }
> 
>+static int i915_opregion(struct seq_file *m, void *unused)
>+{
>+	struct drm_info_node *node = (struct drm_info_node *) m->private;
>+	struct drm_device *dev = node->minor->dev;
>+	drm_i915_private_t *dev_priv = dev->dev_private;
>+	struct intel_opregion *opregion = &dev_priv->opregion;
>+	int ret;
>+
>+	ret = mutex_lock_interruptible(&dev->struct_mutex);
>+	if (ret)
>+		return ret;
>+
>+	if (opregion->header)
>+		seq_write(m, opregion->header, OPREGION_SIZE);
>+
>+	mutex_unlock(&dev->struct_mutex);
>+
>+	return 0;
>+}
>+
> static int
> i915_wedged_open(struct inode *inode,
> 		 struct file *filp)
>@@ -795,6 +815,7 @@ static struct drm_info_list i915_debugfs_list[] = {
> 	{"i915_gfxec", i915_gfxec, 0},
> 	{"i915_fbc_status", i915_fbc_status, 0},
> 	{"i915_sr_status", i915_sr_status, 0},
>+	{"i915_opregion", i915_opregion, 0},
> };
> #define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list)
> 
>diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
>index e802c65..2dae3be 100644
>--- a/drivers/gpu/drm/i915/i915_dma.c
>+++ b/drivers/gpu/drm/i915/i915_dma.c
>@@ -40,6 +40,7 @@
> #include <linux/pnp.h>
> #include <linux/vga_switcheroo.h>
> #include <linux/slab.h>
>+#include <acpi/video.h>
> 
> extern int intel_max_stolen; /* from AGP driver */
> 
>@@ -891,7 +892,7 @@ intel_alloc_mchbar_resource(struct drm_device *dev)
> 	int reg = IS_I965G(dev) ? MCHBAR_I965 : MCHBAR_I915;
> 	u32 temp_lo, temp_hi = 0;
> 	u64 mchbar_addr;
>-	int ret = 0;
>+	int ret;
> 
> 	if (IS_I965G(dev))
> 		pci_read_config_dword(dev_priv->bridge_dev, reg + 4, &temp_hi);
>@@ -901,22 +902,23 @@ intel_alloc_mchbar_resource(struct drm_device *dev)
> 	/* If ACPI doesn't have it, assume we need to allocate it ourselves */
> #ifdef CONFIG_PNP
> 	if (mchbar_addr &&
>-	    pnp_range_reserved(mchbar_addr, mchbar_addr + MCHBAR_SIZE)) {
>-		ret = 0;
>-		goto out;
>-	}
>+	    pnp_range_reserved(mchbar_addr, mchbar_addr + MCHBAR_SIZE))
>+		return 0;
> #endif
> 
> 	/* Get some space for it */
>-	ret = pci_bus_alloc_resource(dev_priv->bridge_dev->bus, &dev_priv->mch_res,
>+	dev_priv->mch_res.name = "i915 MCHBAR";
>+	dev_priv->mch_res.flags = IORESOURCE_MEM;
>+	ret = pci_bus_alloc_resource(dev_priv->bridge_dev->bus,
>+				     &dev_priv->mch_res,
> 				     MCHBAR_SIZE, MCHBAR_SIZE,
> 				     PCIBIOS_MIN_MEM,
>-				     0,   pcibios_align_resource,
>+				     0, pcibios_align_resource,
> 				     dev_priv->bridge_dev);
> 	if (ret) {
> 		DRM_DEBUG_DRIVER("failed bus alloc: %d\n", ret);
> 		dev_priv->mch_res.start = 0;
>-		goto out;
>+		return ret;
> 	}
> 
> 	if (IS_I965G(dev))
>@@ -925,8 +927,7 @@ intel_alloc_mchbar_resource(struct drm_device *dev)
> 
> 	pci_write_config_dword(dev_priv->bridge_dev, reg,
> 			       lower_32_bits(dev_priv->mch_res.start));
>-out:
>-	return ret;
>+	return 0;
> }
> 
> /* Setup MCHBAR if possible, return true if we should disable it again */
>@@ -2166,6 +2167,7 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags)
> 
> 	/* Try to make sure MCHBAR is enabled before poking at it */
> 	intel_setup_mchbar(dev);
>+	intel_opregion_setup(dev);
> 
> 	i915_gem_load(dev);
> 
>@@ -2221,7 +2223,8 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags)
> 	}
> 
> 	/* Must be done after probing outputs */
>-	intel_opregion_init(dev, 0);
>+	intel_opregion_init(dev);
>+	acpi_video_register();
> 
> 	setup_timer(&dev_priv->hangcheck_timer, i915_hangcheck_elapsed,
> 		    (unsigned long) dev);
>@@ -2271,6 +2274,8 @@ int i915_driver_unload(struct drm_device *dev)
> 		dev_priv->mm.gtt_mtrr = -1;
> 	}
> 
>+	acpi_video_unregister();
>+
> 	if (drm_core_check_feature(dev, DRIVER_MODESET)) {
> 		intel_modeset_cleanup(dev);
> 
>@@ -2299,7 +2304,7 @@ int i915_driver_unload(struct drm_device *dev)
> 	if (dev_priv->regs != NULL)
> 		iounmap(dev_priv->regs);
> 
>-	intel_opregion_free(dev, 0);
>+	intel_opregion_fini(dev);
> 
> 	if (drm_core_check_feature(dev, DRIVER_MODESET)) {
> 		/* Flush any outstanding unpin_work. */
>diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
>index 5363985..0236b07 100644
>--- a/drivers/gpu/drm/i915/i915_drv.c
>+++ b/drivers/gpu/drm/i915/i915_drv.c
>@@ -232,7 +232,7 @@ static int i915_drm_freeze(struct drm_device *dev)
> 
> 	i915_save_state(dev);
> 
>-	intel_opregion_free(dev, 1);
>+	intel_opregion_fini(dev);
> 
> 	/* Modeset on resume, not lid events */
> 	dev_priv->modeset_on_lid = 0;
>@@ -272,8 +272,7 @@ static int i915_drm_thaw(struct drm_device *dev)
> 	int error = 0;
> 
> 	i915_restore_state(dev);
>-
>-	intel_opregion_init(dev, 1);
>+	intel_opregion_setup(dev);
> 
> 	/* KMS EnterVT equivalent */
> 	if (drm_core_check_feature(dev, DRIVER_MODESET)) {
>@@ -289,6 +288,8 @@ static int i915_drm_thaw(struct drm_device *dev)
> 		drm_helper_resume_force_mode(dev);
> 	}
> 
>+	intel_opregion_init(dev);
>+
> 	dev_priv->modeset_on_lid = 0;
> 
> 	return error;
>diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
>index 04aada0..f6940f1 100644
>--- a/drivers/gpu/drm/i915/i915_drv.h
>+++ b/drivers/gpu/drm/i915/i915_drv.h
>@@ -110,8 +110,9 @@ struct intel_opregion {
> 	struct opregion_acpi *acpi;
> 	struct opregion_swsci *swsci;
> 	struct opregion_asle *asle;
>-	int enabled;
>+	void *vbt;
> };
>+#define OPREGION_SIZE            (8*1024)
> 
> struct intel_overlay;
> struct intel_overlay_error_state;
>@@ -1053,19 +1054,20 @@ extern int i915_restore_state(struct drm_device *dev);
> extern int i915_save_state(struct drm_device *dev);
> extern int i915_restore_state(struct drm_device *dev);
> 
>+/* intel_opregion.c */
>+extern int intel_opregion_setup(struct drm_device *dev);
> #ifdef CONFIG_ACPI
>-/* i915_opregion.c */
>-extern int intel_opregion_init(struct drm_device *dev, int resume);
>-extern void intel_opregion_free(struct drm_device *dev, int suspend);
>-extern void opregion_asle_intr(struct drm_device *dev);
>-extern void ironlake_opregion_gse_intr(struct drm_device *dev);
>-extern void opregion_enable_asle(struct drm_device *dev);
>+extern void intel_opregion_init(struct drm_device *dev);
>+extern void intel_opregion_fini(struct drm_device *dev);
>+extern void intel_opregion_asle_intr(struct drm_device *dev);
>+extern void intel_opregion_gse_intr(struct drm_device *dev);
>+extern void intel_opregion_enable_asle(struct drm_device *dev);
> #else
>-static inline int intel_opregion_init(struct drm_device *dev, int resume) { return 0; }
>-static inline void intel_opregion_free(struct drm_device *dev, int suspend) { return; }
>-static inline void opregion_asle_intr(struct drm_device *dev) { return; }
>-static inline void ironlake_opregion_gse_intr(struct drm_device *dev) { return; }
>-static inline void opregion_enable_asle(struct drm_device *dev) { return; }
>+static inline void intel_opregion_init(struct drm_device *dev) { return; }
>+static inline void intel_opregion_fini(struct drm_device *dev) { return; }
>+static inline void intel_opregion_asle_intr(struct drm_device *dev) { return; }
>+static inline void intel_opregion_gse_intr(struct drm_device *dev) { return; }
>+static inline void intel_opregion_enable_asle(struct drm_device *dev) { return; }
> #endif
> 
> /* modesetting */
>diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
>index 16861b8..5704c97 100644
>--- a/drivers/gpu/drm/i915/i915_irq.c
>+++ b/drivers/gpu/drm/i915/i915_irq.c
>@@ -347,7 +347,7 @@ irqreturn_t ironlake_irq_handler(struct drm_device *dev)
> 
> 
> 	if (de_iir & DE_GSE)
>-		ironlake_opregion_gse_intr(dev);
>+		intel_opregion_gse_intr(dev);
> 
> 	if (de_iir & DE_PLANEA_FLIP_DONE) {
> 		intel_prepare_page_flip(dev, 0);
>@@ -1018,7 +1018,7 @@ irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS)
> 		if ((pipea_stats & PIPE_LEGACY_BLC_EVENT_STATUS) ||
> 		    (pipeb_stats & PIPE_LEGACY_BLC_EVENT_STATUS) ||
> 		    (iir & I915_ASLE_INTERRUPT))
>-			opregion_asle_intr(dev);
>+			intel_opregion_asle_intr(dev);
> 
> 		/* With MSI, interrupts are only generated when iir
> 		 * transitions from zero to nonzero.  If another bit got
>@@ -1205,7 +1205,7 @@ void i915_enable_interrupt (struct drm_device *dev)
> 	struct drm_i915_private *dev_priv = dev->dev_private;
> 
> 	if (!HAS_PCH_SPLIT(dev))
>-		opregion_enable_asle(dev);
>+		intel_opregion_enable_asle(dev);
> 	dev_priv->irq_enabled = 1;
> }
> 
>@@ -1523,7 +1523,7 @@ int i915_driver_irq_postinstall(struct drm_device *dev)
> 		I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
> 	}
> 
>-	opregion_enable_asle(dev);
>+	intel_opregion_enable_asle(dev);
> 
> 	return 0;
> }
>diff --git a/drivers/gpu/drm/i915/i915_opregion.c b/drivers/gpu/drm/i915/i915_opregion.c
>deleted file mode 100644
>index ea5d3fe..0000000
>--- a/drivers/gpu/drm/i915/i915_opregion.c
>+++ /dev/null
>@@ -1,562 +0,0 @@
>-/*
>- * Copyright 2008 Intel Corporation <hong.liu@intel.com>
>- * Copyright 2008 Red Hat <mjg@redhat.com>
>- *
>- * Permission is hereby granted, free of charge, to any person obtaining
>- * a copy of this software and associated documentation files (the
>- * "Software"), to deal in the Software without restriction, including
>- * without limitation the rights to use, copy, modify, merge, publish,
>- * distribute, sub license, and/or sell copies of the Software, and to
>- * permit persons to whom the Software is furnished to do so, subject to
>- * the following conditions:
>- *
>- * The above copyright notice and this permission notice (including the
>- * next paragraph) shall be included in all copies or substantial
>- * portions of the Software.
>- *
>- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
>- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
>- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
>- * NON-INFRINGEMENT.  IN NO EVENT SHALL INTEL AND/OR ITS SUPPLIERS BE
>- * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
>- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
>- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
>- * SOFTWARE.
>- *
>- */
>-
>-#include <linux/acpi.h>
>-#include <acpi/video.h>
>-
>-#include "drmP.h"
>-#include "i915_drm.h"
>-#include "i915_drv.h"
>-
>-#define PCI_ASLE 0xe4
>-#define PCI_LBPC 0xf4
>-#define PCI_ASLS 0xfc
>-
>-#define OPREGION_SZ            (8*1024)
>-#define OPREGION_HEADER_OFFSET 0
>-#define OPREGION_ACPI_OFFSET   0x100
>-#define OPREGION_SWSCI_OFFSET  0x200
>-#define OPREGION_ASLE_OFFSET   0x300
>-#define OPREGION_VBT_OFFSET    0x1000
>-
>-#define OPREGION_SIGNATURE "IntelGraphicsMem"
>-#define MBOX_ACPI      (1<<0)
>-#define MBOX_SWSCI     (1<<1)
>-#define MBOX_ASLE      (1<<2)
>-
>-struct opregion_header {
>-       u8 signature[16];
>-       u32 size;
>-       u32 opregion_ver;
>-       u8 bios_ver[32];
>-       u8 vbios_ver[16];
>-       u8 driver_ver[16];
>-       u32 mboxes;
>-       u8 reserved[164];
>-} __attribute__((packed));
>-
>-/* OpRegion mailbox #1: public ACPI methods */
>-struct opregion_acpi {
>-       u32 drdy;       /* driver readiness */
>-       u32 csts;       /* notification status */
>-       u32 cevt;       /* current event */
>-       u8 rsvd1[20];
>-       u32 didl[8];    /* supported display devices ID list */
>-       u32 cpdl[8];    /* currently presented display list */
>-       u32 cadl[8];    /* currently active display list */
>-       u32 nadl[8];    /* next active devices list */
>-       u32 aslp;       /* ASL sleep time-out */
>-       u32 tidx;       /* toggle table index */
>-       u32 chpd;       /* current hotplug enable indicator */
>-       u32 clid;       /* current lid state*/
>-       u32 cdck;       /* current docking state */
>-       u32 sxsw;       /* Sx state resume */
>-       u32 evts;       /* ASL supported events */
>-       u32 cnot;       /* current OS notification */
>-       u32 nrdy;       /* driver status */
>-       u8 rsvd2[60];
>-} __attribute__((packed));
>-
>-/* OpRegion mailbox #2: SWSCI */
>-struct opregion_swsci {
>-       u32 scic;       /* SWSCI command|status|data */
>-       u32 parm;       /* command parameters */
>-       u32 dslp;       /* driver sleep time-out */
>-       u8 rsvd[244];
>-} __attribute__((packed));
>-
>-/* OpRegion mailbox #3: ASLE */
>-struct opregion_asle {
>-       u32 ardy;       /* driver readiness */
>-       u32 aslc;       /* ASLE interrupt command */
>-       u32 tche;       /* technology enabled indicator */
>-       u32 alsi;       /* current ALS illuminance reading */
>-       u32 bclp;       /* backlight brightness to set */
>-       u32 pfit;       /* panel fitting state */
>-       u32 cblv;       /* current brightness level */
>-       u16 bclm[20];   /* backlight level duty cycle mapping table */
>-       u32 cpfm;       /* current panel fitting mode */
>-       u32 epfm;       /* enabled panel fitting modes */
>-       u8 plut[74];    /* panel LUT and identifier */
>-       u32 pfmb;       /* PWM freq and min brightness */
>-       u8 rsvd[102];
>-} __attribute__((packed));
>-
>-/* ASLE irq request bits */
>-#define ASLE_SET_ALS_ILLUM     (1 << 0)
>-#define ASLE_SET_BACKLIGHT     (1 << 1)
>-#define ASLE_SET_PFIT          (1 << 2)
>-#define ASLE_SET_PWM_FREQ      (1 << 3)
>-#define ASLE_REQ_MSK           0xf
>-
>-/* response bits of ASLE irq request */
>-#define ASLE_ALS_ILLUM_FAILED	(1<<10)
>-#define ASLE_BACKLIGHT_FAILED	(1<<12)
>-#define ASLE_PFIT_FAILED	(1<<14)
>-#define ASLE_PWM_FREQ_FAILED	(1<<16)
>-
>-/* ASLE backlight brightness to set */
>-#define ASLE_BCLP_VALID                (1<<31)
>-#define ASLE_BCLP_MSK          (~(1<<31))
>-
>-/* ASLE panel fitting request */
>-#define ASLE_PFIT_VALID         (1<<31)
>-#define ASLE_PFIT_CENTER (1<<0)
>-#define ASLE_PFIT_STRETCH_TEXT (1<<1)
>-#define ASLE_PFIT_STRETCH_GFX (1<<2)
>-
>-/* PWM frequency and minimum brightness */
>-#define ASLE_PFMB_BRIGHTNESS_MASK (0xff)
>-#define ASLE_PFMB_BRIGHTNESS_VALID (1<<8)
>-#define ASLE_PFMB_PWM_MASK (0x7ffffe00)
>-#define ASLE_PFMB_PWM_VALID (1<<31)
>-
>-#define ASLE_CBLV_VALID         (1<<31)
>-
>-#define ACPI_OTHER_OUTPUT (0<<8)
>-#define ACPI_VGA_OUTPUT (1<<8)
>-#define ACPI_TV_OUTPUT (2<<8)
>-#define ACPI_DIGITAL_OUTPUT (3<<8)
>-#define ACPI_LVDS_OUTPUT (4<<8)
>-
>-static u32 asle_set_backlight(struct drm_device *dev, u32 bclp)
>-{
>-	struct drm_i915_private *dev_priv = dev->dev_private;
>-	struct opregion_asle *asle = dev_priv->opregion.asle;
>-	u32 blc_pwm_ctl, blc_pwm_ctl2;
>-	u32 max_backlight, level, shift;
>-
>-	if (!(bclp & ASLE_BCLP_VALID))
>-		return ASLE_BACKLIGHT_FAILED;
>-
>-	bclp &= ASLE_BCLP_MSK;
>-	if (bclp < 0 || bclp > 255)
>-		return ASLE_BACKLIGHT_FAILED;
>-
>-	blc_pwm_ctl = I915_READ(BLC_PWM_CTL);
>-	blc_pwm_ctl2 = I915_READ(BLC_PWM_CTL2);
>-
>-	if (IS_I965G(dev) && (blc_pwm_ctl2 & BLM_COMBINATION_MODE))
>-		pci_write_config_dword(dev->pdev, PCI_LBPC, bclp);
>-	else {
>-		if (IS_PINEVIEW(dev)) {
>-			blc_pwm_ctl &= ~(BACKLIGHT_DUTY_CYCLE_MASK - 1);
>-			max_backlight = (blc_pwm_ctl & BACKLIGHT_MODULATION_FREQ_MASK) >> 
>-					BACKLIGHT_MODULATION_FREQ_SHIFT;
>-			shift = BACKLIGHT_DUTY_CYCLE_SHIFT + 1;
>-		} else {
>-			blc_pwm_ctl &= ~BACKLIGHT_DUTY_CYCLE_MASK;
>-			max_backlight = ((blc_pwm_ctl & BACKLIGHT_MODULATION_FREQ_MASK) >> 
>-					BACKLIGHT_MODULATION_FREQ_SHIFT) * 2;
>-			shift = BACKLIGHT_DUTY_CYCLE_SHIFT;
>-		}
>-		level = (bclp * max_backlight) / 255;
>-		I915_WRITE(BLC_PWM_CTL, blc_pwm_ctl | (level << shift));
>-	}
>-	asle->cblv = (bclp*0x64)/0xff | ASLE_CBLV_VALID;
>-
>-	return 0;
>-}
>-
>-static u32 asle_set_als_illum(struct drm_device *dev, u32 alsi)
>-{
>-	/* alsi is the current ALS reading in lux. 0 indicates below sensor
>-	   range, 0xffff indicates above sensor range. 1-0xfffe are valid */
>-	return 0;
>-}
>-
>-static u32 asle_set_pwm_freq(struct drm_device *dev, u32 pfmb)
>-{
>-	struct drm_i915_private *dev_priv = dev->dev_private;
>-	if (pfmb & ASLE_PFMB_PWM_VALID) {
>-		u32 blc_pwm_ctl = I915_READ(BLC_PWM_CTL);
>-		u32 pwm = pfmb & ASLE_PFMB_PWM_MASK;
>-		blc_pwm_ctl &= BACKLIGHT_DUTY_CYCLE_MASK;
>-		pwm = pwm >> 9;
>-		/* FIXME - what do we do with the PWM? */
>-	}
>-	return 0;
>-}
>-
>-static u32 asle_set_pfit(struct drm_device *dev, u32 pfit)
>-{
>-	/* Panel fitting is currently controlled by the X code, so this is a
>-	   noop until modesetting support works fully */
>-	if (!(pfit & ASLE_PFIT_VALID))
>-		return ASLE_PFIT_FAILED;
>-	return 0;
>-}
>-
>-void opregion_asle_intr(struct drm_device *dev)
>-{
>-	struct drm_i915_private *dev_priv = dev->dev_private;
>-	struct opregion_asle *asle = dev_priv->opregion.asle;
>-	u32 asle_stat = 0;
>-	u32 asle_req;
>-
>-	if (!asle)
>-		return;
>-
>-	asle_req = asle->aslc & ASLE_REQ_MSK;
>-
>-	if (!asle_req) {
>-		DRM_DEBUG_DRIVER("non asle set request??\n");
>-		return;
>-	}
>-
>-	if (asle_req & ASLE_SET_ALS_ILLUM)
>-		asle_stat |= asle_set_als_illum(dev, asle->alsi);
>-
>-	if (asle_req & ASLE_SET_BACKLIGHT)
>-		asle_stat |= asle_set_backlight(dev, asle->bclp);
>-
>-	if (asle_req & ASLE_SET_PFIT)
>-		asle_stat |= asle_set_pfit(dev, asle->pfit);
>-
>-	if (asle_req & ASLE_SET_PWM_FREQ)
>-		asle_stat |= asle_set_pwm_freq(dev, asle->pfmb);
>-
>-	asle->aslc = asle_stat;
>-}
>-
>-static u32 asle_set_backlight_ironlake(struct drm_device *dev, u32 bclp)
>-{
>-	struct drm_i915_private *dev_priv = dev->dev_private;
>-	struct opregion_asle *asle = dev_priv->opregion.asle;
>-	u32 cpu_pwm_ctl, pch_pwm_ctl2;
>-	u32 max_backlight, level;
>-
>-	if (!(bclp & ASLE_BCLP_VALID))
>-		return ASLE_BACKLIGHT_FAILED;
>-
>-	bclp &= ASLE_BCLP_MSK;
>-	if (bclp < 0 || bclp > 255)
>-		return ASLE_BACKLIGHT_FAILED;
>-
>-	cpu_pwm_ctl = I915_READ(BLC_PWM_CPU_CTL);
>-	pch_pwm_ctl2 = I915_READ(BLC_PWM_PCH_CTL2);
>-	/* get the max PWM frequency */
>-	max_backlight = (pch_pwm_ctl2 >> 16) & BACKLIGHT_DUTY_CYCLE_MASK;
>-	/* calculate the expected PMW frequency */
>-	level = (bclp * max_backlight) / 255;
>-	/* reserve the high 16 bits */
>-	cpu_pwm_ctl &= ~(BACKLIGHT_DUTY_CYCLE_MASK);
>-	/* write the updated PWM frequency */
>-	I915_WRITE(BLC_PWM_CPU_CTL, cpu_pwm_ctl | level);
>-
>-	asle->cblv = (bclp*0x64)/0xff | ASLE_CBLV_VALID;
>-
>-	return 0;
>-}
>-
>-void ironlake_opregion_gse_intr(struct drm_device *dev)
>-{
>-	struct drm_i915_private *dev_priv = dev->dev_private;
>-	struct opregion_asle *asle = dev_priv->opregion.asle;
>-	u32 asle_stat = 0;
>-	u32 asle_req;
>-
>-	if (!asle)
>-		return;
>-
>-	asle_req = asle->aslc & ASLE_REQ_MSK;
>-
>-	if (!asle_req) {
>-		DRM_DEBUG_DRIVER("non asle set request??\n");
>-		return;
>-	}
>-
>-	if (asle_req & ASLE_SET_ALS_ILLUM) {
>-		DRM_DEBUG_DRIVER("Illum is not supported\n");
>-		asle_stat |= ASLE_ALS_ILLUM_FAILED;
>-	}
>-
>-	if (asle_req & ASLE_SET_BACKLIGHT)
>-		asle_stat |= asle_set_backlight_ironlake(dev, asle->bclp);
>-
>-	if (asle_req & ASLE_SET_PFIT) {
>-		DRM_DEBUG_DRIVER("Pfit is not supported\n");
>-		asle_stat |= ASLE_PFIT_FAILED;
>-	}
>-
>-	if (asle_req & ASLE_SET_PWM_FREQ) {
>-		DRM_DEBUG_DRIVER("PWM freq is not supported\n");
>-		asle_stat |= ASLE_PWM_FREQ_FAILED;
>-	}
>-
>-	asle->aslc = asle_stat;
>-}
>-#define ASLE_ALS_EN    (1<<0)
>-#define ASLE_BLC_EN    (1<<1)
>-#define ASLE_PFIT_EN   (1<<2)
>-#define ASLE_PFMB_EN   (1<<3)
>-
>-void opregion_enable_asle(struct drm_device *dev)
>-{
>-	struct drm_i915_private *dev_priv = dev->dev_private;
>-	struct opregion_asle *asle = dev_priv->opregion.asle;
>-
>-	if (asle) {
>-		if (IS_MOBILE(dev)) {
>-			unsigned long irqflags;
>-
>-			spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags);
>-			intel_enable_asle(dev);
>-			spin_unlock_irqrestore(&dev_priv->user_irq_lock,
>-					       irqflags);
>-		}
>-
>-		asle->tche = ASLE_ALS_EN | ASLE_BLC_EN | ASLE_PFIT_EN |
>-			ASLE_PFMB_EN;
>-		asle->ardy = 1;
>-	}
>-}
>-
>-#define ACPI_EV_DISPLAY_SWITCH (1<<0)
>-#define ACPI_EV_LID            (1<<1)
>-#define ACPI_EV_DOCK           (1<<2)
>-
>-static struct intel_opregion *system_opregion;
>-
>-static int intel_opregion_video_event(struct notifier_block *nb,
>-				      unsigned long val, void *data)
>-{
>-	/* The only video events relevant to opregion are 0x80. These indicate
>-	   either a docking event, lid switch or display switch request. In
>-	   Linux, these are handled by the dock, button and video drivers.
>-	   We might want to fix the video driver to be opregion-aware in
>-	   future, but right now we just indicate to the firmware that the
>-	   request has been handled */
>-
>-	struct opregion_acpi *acpi;
>-
>-	if (!system_opregion)
>-		return NOTIFY_DONE;
>-
>-	acpi = system_opregion->acpi;
>-	acpi->csts = 0;
>-
>-	return NOTIFY_OK;
>-}
>-
>-static struct notifier_block intel_opregion_notifier = {
>-	.notifier_call = intel_opregion_video_event,
>-};
>-
>-/*
>- * Initialise the DIDL field in opregion. This passes a list of devices to
>- * the firmware. Values are defined by section B.4.2 of the ACPI specification
>- * (version 3)
>- */
>-
>-static void intel_didl_outputs(struct drm_device *dev)
>-{
>-	struct drm_i915_private *dev_priv = dev->dev_private;
>-	struct intel_opregion *opregion = &dev_priv->opregion;
>-	struct drm_connector *connector;
>-	acpi_handle handle;
>-	struct acpi_device *acpi_dev, *acpi_cdev, *acpi_video_bus = NULL;
>-	unsigned long long device_id;
>-	acpi_status status;
>-	int i = 0;
>-
>-	handle = DEVICE_ACPI_HANDLE(&dev->pdev->dev);
>-	if (!handle || ACPI_FAILURE(acpi_bus_get_device(handle, &acpi_dev)))
>-		return;
>-
>-	if (acpi_is_video_device(acpi_dev))
>-		acpi_video_bus = acpi_dev;
>-	else {
>-		list_for_each_entry(acpi_cdev, &acpi_dev->children, node) {
>-			if (acpi_is_video_device(acpi_cdev)) {
>-				acpi_video_bus = acpi_cdev;
>-				break;
>-			}
>-		}
>-	}
>-
>-	if (!acpi_video_bus) {
>-		printk(KERN_WARNING "No ACPI video bus found\n");
>-		return;
>-	}
>-
>-	list_for_each_entry(acpi_cdev, &acpi_video_bus->children, node) {
>-		if (i >= 8) {
>-			dev_printk (KERN_ERR, &dev->pdev->dev,
>-				    "More than 8 outputs detected\n");
>-			return;
>-		}
>-		status =
>-			acpi_evaluate_integer(acpi_cdev->handle, "_ADR",
>-						NULL, &device_id);
>-		if (ACPI_SUCCESS(status)) {
>-			if (!device_id)
>-				goto blind_set;
>-			opregion->acpi->didl[i] = (u32)(device_id & 0x0f0f);
>-			i++;
>-		}
>-	}
>-
>-end:
>-	/* If fewer than 8 outputs, the list must be null terminated */
>-	if (i < 8)
>-		opregion->acpi->didl[i] = 0;
>-	return;
>-
>-blind_set:
>-	i = 0;
>-	list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
>-		int output_type = ACPI_OTHER_OUTPUT;
>-		if (i >= 8) {
>-			dev_printk (KERN_ERR, &dev->pdev->dev,
>-				    "More than 8 outputs detected\n");
>-			return;
>-		}
>-		switch (connector->connector_type) {
>-		case DRM_MODE_CONNECTOR_VGA:
>-		case DRM_MODE_CONNECTOR_DVIA:
>-			output_type = ACPI_VGA_OUTPUT;
>-			break;
>-		case DRM_MODE_CONNECTOR_Composite:
>-		case DRM_MODE_CONNECTOR_SVIDEO:
>-		case DRM_MODE_CONNECTOR_Component:
>-		case DRM_MODE_CONNECTOR_9PinDIN:
>-			output_type = ACPI_TV_OUTPUT;
>-			break;
>-		case DRM_MODE_CONNECTOR_DVII:
>-		case DRM_MODE_CONNECTOR_DVID:
>-		case DRM_MODE_CONNECTOR_DisplayPort:
>-		case DRM_MODE_CONNECTOR_HDMIA:
>-		case DRM_MODE_CONNECTOR_HDMIB:
>-			output_type = ACPI_DIGITAL_OUTPUT;
>-			break;
>-		case DRM_MODE_CONNECTOR_LVDS:
>-			output_type = ACPI_LVDS_OUTPUT;
>-			break;
>-		}
>-		opregion->acpi->didl[i] |= (1<<31) | output_type | i;
>-		i++;
>-	}
>-	goto end;
>-}
>-
>-int intel_opregion_init(struct drm_device *dev, int resume)
>-{
>-	struct drm_i915_private *dev_priv = dev->dev_private;
>-	struct intel_opregion *opregion = &dev_priv->opregion;
>-	void *base;
>-	u32 asls, mboxes;
>-	int err = 0;
>-
>-	pci_read_config_dword(dev->pdev, PCI_ASLS, &asls);
>-	DRM_DEBUG_DRIVER("graphic opregion physical addr: 0x%x\n", asls);
>-	if (asls == 0) {
>-		DRM_DEBUG_DRIVER("ACPI OpRegion not supported!\n");
>-		return -ENOTSUPP;
>-	}
>-
>-	base = ioremap(asls, OPREGION_SZ);
>-	if (!base)
>-		return -ENOMEM;
>-
>-	opregion->header = base;
>-	if (memcmp(opregion->header->signature, OPREGION_SIGNATURE, 16)) {
>-		DRM_DEBUG_DRIVER("opregion signature mismatch\n");
>-		err = -EINVAL;
>-		goto err_out;
>-	}
>-
>-	mboxes = opregion->header->mboxes;
>-	if (mboxes & MBOX_ACPI) {
>-		DRM_DEBUG_DRIVER("Public ACPI methods supported\n");
>-		opregion->acpi = base + OPREGION_ACPI_OFFSET;
>-		if (drm_core_check_feature(dev, DRIVER_MODESET))
>-			intel_didl_outputs(dev);
>-	} else {
>-		DRM_DEBUG_DRIVER("Public ACPI methods not supported\n");
>-		err = -ENOTSUPP;
>-		goto err_out;
>-	}
>-	opregion->enabled = 1;
>-
>-	if (mboxes & MBOX_SWSCI) {
>-		DRM_DEBUG_DRIVER("SWSCI supported\n");
>-		opregion->swsci = base + OPREGION_SWSCI_OFFSET;
>-	}
>-	if (mboxes & MBOX_ASLE) {
>-		DRM_DEBUG_DRIVER("ASLE supported\n");
>-		opregion->asle = base + OPREGION_ASLE_OFFSET;
>-		opregion_enable_asle(dev);
>-	}
>-
>-	if (!resume)
>-		acpi_video_register();
>-
>-
>-	/* Notify BIOS we are ready to handle ACPI video ext notifs.
>-	 * Right now, all the events are handled by the ACPI video module.
>-	 * We don't actually need to do anything with them. */
>-	opregion->acpi->csts = 0;
>-	opregion->acpi->drdy = 1;
>-
>-	system_opregion = opregion;
>-	register_acpi_notifier(&intel_opregion_notifier);
>-
>-	return 0;
>-
>-err_out:
>-	iounmap(opregion->header);
>-	opregion->header = NULL;
>-	acpi_video_register();
>-	return err;
>-}
>-
>-void intel_opregion_free(struct drm_device *dev, int suspend)
>-{
>-	struct drm_i915_private *dev_priv = dev->dev_private;
>-	struct intel_opregion *opregion = &dev_priv->opregion;
>-
>-	if (!opregion->enabled)
>-		return;
>-
>-	if (!suspend)
>-		acpi_video_unregister();
>-
>-	opregion->acpi->drdy = 0;
>-
>-	system_opregion = NULL;
>-	unregister_acpi_notifier(&intel_opregion_notifier);
>-
>-	/* just clear all opregion memory pointers now */
>-	iounmap(opregion->header);
>-	opregion->header = NULL;
>-	opregion->acpi = NULL;
>-	opregion->swsci = NULL;
>-	opregion->asle = NULL;
>-
>-	opregion->enabled = 0;
>-}
>diff --git a/drivers/gpu/drm/i915/intel_bios.c b/drivers/gpu/drm/i915/intel_bios.c
>index 96f75d7..8d7deca 100644
>--- a/drivers/gpu/drm/i915/intel_bios.c
>+++ b/drivers/gpu/drm/i915/intel_bios.c
>@@ -317,7 +317,7 @@ parse_general_definitions(struct drm_i915_private *dev_priv,
> 
> static void
> parse_sdvo_device_mapping(struct drm_i915_private *dev_priv,
>-		       struct bdb_header *bdb)
>+			  struct bdb_header *bdb)
> {
> 	struct sdvo_device_mapping *p_mapping;
> 	struct bdb_general_definitions *p_defs;
>@@ -327,7 +327,7 @@ parse_sdvo_device_mapping(struct drm_i915_private *dev_priv,
> 
> 	p_defs = find_section(bdb, BDB_GENERAL_DEFINITIONS);
> 	if (!p_defs) {
>-		DRM_DEBUG_KMS("No general definition block is found\n");
>+		DRM_DEBUG_KMS("No general definition block is found, unable to construct sdvo mapping.\n");
> 		return;
> 	}
> 	/* judge whether the size of child device meets the requirements.
>@@ -460,7 +460,7 @@ parse_device_mapping(struct drm_i915_private *dev_priv,
> 
> 	p_defs = find_section(bdb, BDB_GENERAL_DEFINITIONS);
> 	if (!p_defs) {
>-		DRM_DEBUG_KMS("No general definition block is found\n");
>+		DRM_DEBUG_KMS("No general definition block is found, no devices defined.\n");
> 		return;
> 	}
> 	/* judge whether the size of child device meets the requirements.
>@@ -513,6 +513,7 @@ parse_device_mapping(struct drm_i915_private *dev_priv,
> 	}
> 	return;
> }
>+
> /**
>  * intel_init_bios - initialize VBIOS settings & find VBT
>  * @dev: DRM device
>@@ -520,11 +521,6 @@ parse_device_mapping(struct drm_i915_private *dev_priv,
>  * Loads the Video BIOS and checks that the VBT exists.  Sets scratch registers
>  * to appropriate values.
>  *
>- * VBT existence is a sanity check that is relied on by other i830_bios.c code.
>- * Note that it would be better to use a BIOS call to get the VBT, as BIOSes may
>- * feed an updated VBT back through that, compared to what we'll fetch using
>- * this method of groping around in the BIOS data.
>- *
>  * Returns 0 on success, nonzero on failure.
>  */
> bool
>@@ -532,31 +528,45 @@ intel_init_bios(struct drm_device *dev)
> {
> 	struct drm_i915_private *dev_priv = dev->dev_private;
> 	struct pci_dev *pdev = dev->pdev;
>-	struct vbt_header *vbt = NULL;
>-	struct bdb_header *bdb;
>-	u8 __iomem *bios;
>-	size_t size;
>-	int i;
>-
>-	bios = pci_map_rom(pdev, &size);
>-	if (!bios)
>-		return -1;
>-
>-	/* Scour memory looking for the VBT signature */
>-	for (i = 0; i + 4 < size; i++) {
>-		if (!memcmp(bios + i, "$VBT", 4)) {
>-			vbt = (struct vbt_header *)(bios + i);
>-			break;
>-		}
>+	struct bdb_header *bdb = NULL;
>+	u8 __iomem *bios = NULL;
>+
>+	/* XXX Should this validation be moved to intel_opregion.c? */
>+	if (dev_priv->opregion.vbt) {
>+		struct vbt_header *vbt = dev_priv->opregion.vbt;
>+		if (memcmp(vbt->signature, "$VBT", 4) == 0) {
>+			DRM_DEBUG_DRIVER("Using VBT from OpRegion: %20s\n",
>+					 vbt->signature);
>+			bdb = (struct bdb_header *)((char *)vbt + vbt->bdb_offset);
>+		} else
>+			dev_priv->opregion.vbt = NULL;
> 	}
> 
>-	if (!vbt) {
>-		DRM_ERROR("VBT signature missing\n");
>-		pci_unmap_rom(pdev, bios);
>-		return -1;
>-	}
>+	if (bdb == NULL) {
>+		struct vbt_header *vbt = NULL;
>+		size_t size;
>+		int i;
> 
>-	bdb = (struct bdb_header *)(bios + i + vbt->bdb_offset);
>+		bios = pci_map_rom(pdev, &size);
>+		if (!bios)
>+			return -1;
>+
>+		/* Scour memory looking for the VBT signature */
>+		for (i = 0; i + 4 < size; i++) {
>+			if (!memcmp(bios + i, "$VBT", 4)) {
>+				vbt = (struct vbt_header *)(bios + i);
>+				break;
>+			}
>+		}
>+
>+		if (!vbt) {
>+			DRM_ERROR("VBT signature missing\n");
>+			pci_unmap_rom(pdev, bios);
>+			return -1;
>+		}
>+
>+		bdb = (struct bdb_header *)(bios + i + vbt->bdb_offset);
>+	}
> 
> 	/* Grab useful general definitions */
> 	parse_general_features(dev_priv, bdb);
>@@ -568,7 +578,8 @@ intel_init_bios(struct drm_device *dev)
> 	parse_driver_features(dev_priv, bdb);
> 	parse_edp(dev_priv, bdb);
> 
>-	pci_unmap_rom(pdev, bios);
>+	if (bios)
>+		pci_unmap_rom(pdev, bios);
> 
> 	return 0;
> }
>diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
>index 0879331..3449a3b 100644
>--- a/drivers/gpu/drm/i915/intel_dp.c
>+++ b/drivers/gpu/drm/i915/intel_dp.c
>@@ -239,7 +239,6 @@ intel_dp_aux_ch(struct intel_dp *intel_dp,
> 	uint32_t ch_data = ch_ctl + 4;
> 	int i;
> 	int recv_bytes;
>-	uint32_t ctl;
> 	uint32_t status;
> 	uint32_t aux_clock_divider;
> 	int try, precharge;
>@@ -263,41 +262,43 @@ intel_dp_aux_ch(struct intel_dp *intel_dp,
> 	else
> 		precharge = 5;
> 
>+	if (I915_READ(ch_ctl) & DP_AUX_CH_CTL_SEND_BUSY) {
>+		DRM_ERROR("dp_aux_ch not started status 0x%08x\n",
>+			  I915_READ(ch_ctl));
>+		return -EBUSY;
>+	}
>+
> 	/* Must try at least 3 times according to DP spec */
> 	for (try = 0; try < 5; try++) {
> 		/* Load the send data into the aux channel data registers */
>-		for (i = 0; i < send_bytes; i += 4) {
>-			uint32_t    d = pack_aux(send + i, send_bytes - i);
>-	
>-			I915_WRITE(ch_data + i, d);
>-		}
>-	
>-		ctl = (DP_AUX_CH_CTL_SEND_BUSY |
>-		       DP_AUX_CH_CTL_TIME_OUT_400us |
>-		       (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
>-		       (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
>-		       (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT) |
>-		       DP_AUX_CH_CTL_DONE |
>-		       DP_AUX_CH_CTL_TIME_OUT_ERROR |
>-		       DP_AUX_CH_CTL_RECEIVE_ERROR);
>+		for (i = 0; i < send_bytes; i += 4)
>+			I915_WRITE(ch_data + i,
>+				   pack_aux(send + i, send_bytes - i));
> 	
> 		/* Send the command and wait for it to complete */
>-		I915_WRITE(ch_ctl, ctl);
>-		(void) I915_READ(ch_ctl);
>+		I915_WRITE(ch_ctl,
>+			   DP_AUX_CH_CTL_SEND_BUSY |
>+			   DP_AUX_CH_CTL_TIME_OUT_400us |
>+			   (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
>+			   (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
>+			   (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT) |
>+			   DP_AUX_CH_CTL_DONE |
>+			   DP_AUX_CH_CTL_TIME_OUT_ERROR |
>+			   DP_AUX_CH_CTL_RECEIVE_ERROR);
> 		for (;;) {
>-			udelay(100);
> 			status = I915_READ(ch_ctl);
> 			if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
> 				break;
>+			udelay(100);
> 		}
> 	
> 		/* Clear done status and any errors */
>-		I915_WRITE(ch_ctl, (status |
>-				DP_AUX_CH_CTL_DONE |
>-				DP_AUX_CH_CTL_TIME_OUT_ERROR |
>-				DP_AUX_CH_CTL_RECEIVE_ERROR));
>-		(void) I915_READ(ch_ctl);
>-		if ((status & DP_AUX_CH_CTL_TIME_OUT_ERROR) == 0)
>+		I915_WRITE(ch_ctl,
>+			   status |
>+			   DP_AUX_CH_CTL_DONE |
>+			   DP_AUX_CH_CTL_TIME_OUT_ERROR |
>+			   DP_AUX_CH_CTL_RECEIVE_ERROR);
>+		if (status & DP_AUX_CH_CTL_DONE)
> 			break;
> 	}
> 
>@@ -324,15 +325,12 @@ intel_dp_aux_ch(struct intel_dp *intel_dp,
> 	/* Unload any bytes sent back from the other side */
> 	recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
> 		      DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
>-
> 	if (recv_bytes > recv_size)
> 		recv_bytes = recv_size;
> 	
>-	for (i = 0; i < recv_bytes; i += 4) {
>-		uint32_t    d = I915_READ(ch_data + i);
>-
>-		unpack_aux(d, recv + i, recv_bytes - i);
>-	}
>+	for (i = 0; i < recv_bytes; i += 4)
>+		unpack_aux(I915_READ(ch_data + i),
>+			   recv + i, recv_bytes - i);
> 
> 	return recv_bytes;
> }
>diff --git a/drivers/gpu/drm/i915/intel_opregion.c b/drivers/gpu/drm/i915/intel_opregion.c
>new file mode 100644
>index 0000000..3cb1323
>--- /dev/null
>+++ b/drivers/gpu/drm/i915/intel_opregion.c
>@@ -0,0 +1,566 @@
>+/*
>+ * Copyright 2008 Intel Corporation <hong.liu@intel.com>
>+ * Copyright 2008 Red Hat <mjg@redhat.com>
>+ *
>+ * Permission is hereby granted, free of charge, to any person obtaining
>+ * a copy of this software and associated documentation files (the
>+ * "Software"), to deal in the Software without restriction, including
>+ * without limitation the rights to use, copy, modify, merge, publish,
>+ * distribute, sub license, and/or sell copies of the Software, and to
>+ * permit persons to whom the Software is furnished to do so, subject to
>+ * the following conditions:
>+ *
>+ * The above copyright notice and this permission notice (including the
>+ * next paragraph) shall be included in all copies or substantial
>+ * portions of the Software.
>+ *
>+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
>+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
>+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
>+ * NON-INFRINGEMENT.  IN NO EVENT SHALL INTEL AND/OR ITS SUPPLIERS BE
>+ * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
>+ * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
>+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
>+ * SOFTWARE.
>+ *
>+ */
>+
>+#include <linux/acpi.h>
>+#include <acpi/video.h>
>+
>+#include "drmP.h"
>+#include "i915_drm.h"
>+#include "i915_drv.h"
>+
>+#define PCI_ASLE 0xe4
>+#define PCI_LBPC 0xf4
>+#define PCI_ASLS 0xfc
>+
>+#define OPREGION_HEADER_OFFSET 0
>+#define OPREGION_ACPI_OFFSET   0x100
>+#define OPREGION_SWSCI_OFFSET  0x200
>+#define OPREGION_ASLE_OFFSET   0x300
>+#define OPREGION_VBT_OFFSET    0x400
>+
>+#define OPREGION_SIGNATURE "IntelGraphicsMem"
>+#define MBOX_ACPI      (1<<0)
>+#define MBOX_SWSCI     (1<<1)
>+#define MBOX_ASLE      (1<<2)
>+
>+struct opregion_header {
>+       u8 signature[16];
>+       u32 size;
>+       u32 opregion_ver;
>+       u8 bios_ver[32];
>+       u8 vbios_ver[16];
>+       u8 driver_ver[16];
>+       u32 mboxes;
>+       u8 reserved[164];
>+} __attribute__((packed));
>+
>+/* OpRegion mailbox #1: public ACPI methods */
>+struct opregion_acpi {
>+       u32 drdy;       /* driver readiness */
>+       u32 csts;       /* notification status */
>+       u32 cevt;       /* current event */
>+       u8 rsvd1[20];
>+       u32 didl[8];    /* supported display devices ID list */
>+       u32 cpdl[8];    /* currently presented display list */
>+       u32 cadl[8];    /* currently active display list */
>+       u32 nadl[8];    /* next active devices list */
>+       u32 aslp;       /* ASL sleep time-out */
>+       u32 tidx;       /* toggle table index */
>+       u32 chpd;       /* current hotplug enable indicator */
>+       u32 clid;       /* current lid state*/
>+       u32 cdck;       /* current docking state */
>+       u32 sxsw;       /* Sx state resume */
>+       u32 evts;       /* ASL supported events */
>+       u32 cnot;       /* current OS notification */
>+       u32 nrdy;       /* driver status */
>+       u8 rsvd2[60];
>+} __attribute__((packed));
>+
>+/* OpRegion mailbox #2: SWSCI */
>+struct opregion_swsci {
>+       u32 scic;       /* SWSCI command|status|data */
>+       u32 parm;       /* command parameters */
>+       u32 dslp;       /* driver sleep time-out */
>+       u8 rsvd[244];
>+} __attribute__((packed));
>+
>+/* OpRegion mailbox #3: ASLE */
>+struct opregion_asle {
>+       u32 ardy;       /* driver readiness */
>+       u32 aslc;       /* ASLE interrupt command */
>+       u32 tche;       /* technology enabled indicator */
>+       u32 alsi;       /* current ALS illuminance reading */
>+       u32 bclp;       /* backlight brightness to set */
>+       u32 pfit;       /* panel fitting state */
>+       u32 cblv;       /* current brightness level */
>+       u16 bclm[20];   /* backlight level duty cycle mapping table */
>+       u32 cpfm;       /* current panel fitting mode */
>+       u32 epfm;       /* enabled panel fitting modes */
>+       u8 plut[74];    /* panel LUT and identifier */
>+       u32 pfmb;       /* PWM freq and min brightness */
>+       u8 rsvd[102];
>+} __attribute__((packed));
>+
>+/* ASLE irq request bits */
>+#define ASLE_SET_ALS_ILLUM     (1 << 0)
>+#define ASLE_SET_BACKLIGHT     (1 << 1)
>+#define ASLE_SET_PFIT          (1 << 2)
>+#define ASLE_SET_PWM_FREQ      (1 << 3)
>+#define ASLE_REQ_MSK           0xf
>+
>+/* response bits of ASLE irq request */
>+#define ASLE_ALS_ILLUM_FAILED	(1<<10)
>+#define ASLE_BACKLIGHT_FAILED	(1<<12)
>+#define ASLE_PFIT_FAILED	(1<<14)
>+#define ASLE_PWM_FREQ_FAILED	(1<<16)
>+
>+/* ASLE backlight brightness to set */
>+#define ASLE_BCLP_VALID                (1<<31)
>+#define ASLE_BCLP_MSK          (~(1<<31))
>+
>+/* ASLE panel fitting request */
>+#define ASLE_PFIT_VALID         (1<<31)
>+#define ASLE_PFIT_CENTER (1<<0)
>+#define ASLE_PFIT_STRETCH_TEXT (1<<1)
>+#define ASLE_PFIT_STRETCH_GFX (1<<2)
>+
>+/* PWM frequency and minimum brightness */
>+#define ASLE_PFMB_BRIGHTNESS_MASK (0xff)
>+#define ASLE_PFMB_BRIGHTNESS_VALID (1<<8)
>+#define ASLE_PFMB_PWM_MASK (0x7ffffe00)
>+#define ASLE_PFMB_PWM_VALID (1<<31)
>+
>+#define ASLE_CBLV_VALID         (1<<31)
>+
>+#define ACPI_OTHER_OUTPUT (0<<8)
>+#define ACPI_VGA_OUTPUT (1<<8)
>+#define ACPI_TV_OUTPUT (2<<8)
>+#define ACPI_DIGITAL_OUTPUT (3<<8)
>+#define ACPI_LVDS_OUTPUT (4<<8)
>+
>+#ifdef CONFIG_ACPI
>+static u32 asle_set_backlight(struct drm_device *dev, u32 bclp)
>+{
>+	struct drm_i915_private *dev_priv = dev->dev_private;
>+	struct opregion_asle *asle = dev_priv->opregion.asle;
>+	u32 blc_pwm_ctl, blc_pwm_ctl2;
>+	u32 max_backlight, level, shift;
>+
>+	if (!(bclp & ASLE_BCLP_VALID))
>+		return ASLE_BACKLIGHT_FAILED;
>+
>+	bclp &= ASLE_BCLP_MSK;
>+	if (bclp < 0 || bclp > 255)
>+		return ASLE_BACKLIGHT_FAILED;
>+
>+	blc_pwm_ctl = I915_READ(BLC_PWM_CTL);
>+	blc_pwm_ctl2 = I915_READ(BLC_PWM_CTL2);
>+
>+	if (IS_I965G(dev) && (blc_pwm_ctl2 & BLM_COMBINATION_MODE))
>+		pci_write_config_dword(dev->pdev, PCI_LBPC, bclp);
>+	else {
>+		if (IS_PINEVIEW(dev)) {
>+			blc_pwm_ctl &= ~(BACKLIGHT_DUTY_CYCLE_MASK - 1);
>+			max_backlight = (blc_pwm_ctl & BACKLIGHT_MODULATION_FREQ_MASK) >> 
>+					BACKLIGHT_MODULATION_FREQ_SHIFT;
>+			shift = BACKLIGHT_DUTY_CYCLE_SHIFT + 1;
>+		} else {
>+			blc_pwm_ctl &= ~BACKLIGHT_DUTY_CYCLE_MASK;
>+			max_backlight = ((blc_pwm_ctl & BACKLIGHT_MODULATION_FREQ_MASK) >> 
>+					BACKLIGHT_MODULATION_FREQ_SHIFT) * 2;
>+			shift = BACKLIGHT_DUTY_CYCLE_SHIFT;
>+		}
>+		level = (bclp * max_backlight) / 255;
>+		I915_WRITE(BLC_PWM_CTL, blc_pwm_ctl | (level << shift));
>+	}
>+	asle->cblv = (bclp*0x64)/0xff | ASLE_CBLV_VALID;
>+
>+	return 0;
>+}
>+
>+static u32 asle_set_als_illum(struct drm_device *dev, u32 alsi)
>+{
>+	/* alsi is the current ALS reading in lux. 0 indicates below sensor
>+	   range, 0xffff indicates above sensor range. 1-0xfffe are valid */
>+	return 0;
>+}
>+
>+static u32 asle_set_pwm_freq(struct drm_device *dev, u32 pfmb)
>+{
>+	struct drm_i915_private *dev_priv = dev->dev_private;
>+	if (pfmb & ASLE_PFMB_PWM_VALID) {
>+		u32 blc_pwm_ctl = I915_READ(BLC_PWM_CTL);
>+		u32 pwm = pfmb & ASLE_PFMB_PWM_MASK;
>+		blc_pwm_ctl &= BACKLIGHT_DUTY_CYCLE_MASK;
>+		pwm = pwm >> 9;
>+		/* FIXME - what do we do with the PWM? */
>+	}
>+	return 0;
>+}
>+
>+static u32 asle_set_pfit(struct drm_device *dev, u32 pfit)
>+{
>+	/* Panel fitting is currently controlled by the X code, so this is a
>+	   noop until modesetting support works fully */
>+	if (!(pfit & ASLE_PFIT_VALID))
>+		return ASLE_PFIT_FAILED;
>+	return 0;
>+}
>+
>+void intel_opregion_asle_intr(struct drm_device *dev)
>+{
>+	struct drm_i915_private *dev_priv = dev->dev_private;
>+	struct opregion_asle *asle = dev_priv->opregion.asle;
>+	u32 asle_stat = 0;
>+	u32 asle_req;
>+
>+	if (!asle)
>+		return;
>+
>+	asle_req = asle->aslc & ASLE_REQ_MSK;
>+
>+	if (!asle_req) {
>+		DRM_DEBUG_DRIVER("non asle set request??\n");
>+		return;
>+	}
>+
>+	if (asle_req & ASLE_SET_ALS_ILLUM)
>+		asle_stat |= asle_set_als_illum(dev, asle->alsi);
>+
>+	if (asle_req & ASLE_SET_BACKLIGHT)
>+		asle_stat |= asle_set_backlight(dev, asle->bclp);
>+
>+	if (asle_req & ASLE_SET_PFIT)
>+		asle_stat |= asle_set_pfit(dev, asle->pfit);
>+
>+	if (asle_req & ASLE_SET_PWM_FREQ)
>+		asle_stat |= asle_set_pwm_freq(dev, asle->pfmb);
>+
>+	asle->aslc = asle_stat;
>+}
>+
>+static u32 asle_set_backlight_ironlake(struct drm_device *dev, u32 bclp)
>+{
>+	struct drm_i915_private *dev_priv = dev->dev_private;
>+	struct opregion_asle *asle = dev_priv->opregion.asle;
>+	u32 cpu_pwm_ctl, pch_pwm_ctl2;
>+	u32 max_backlight, level;
>+
>+	if (!(bclp & ASLE_BCLP_VALID))
>+		return ASLE_BACKLIGHT_FAILED;
>+
>+	bclp &= ASLE_BCLP_MSK;
>+	if (bclp < 0 || bclp > 255)
>+		return ASLE_BACKLIGHT_FAILED;
>+
>+	cpu_pwm_ctl = I915_READ(BLC_PWM_CPU_CTL);
>+	pch_pwm_ctl2 = I915_READ(BLC_PWM_PCH_CTL2);
>+	/* get the max PWM frequency */
>+	max_backlight = (pch_pwm_ctl2 >> 16) & BACKLIGHT_DUTY_CYCLE_MASK;
>+	/* calculate the expected PMW frequency */
>+	level = (bclp * max_backlight) / 255;
>+	/* reserve the high 16 bits */
>+	cpu_pwm_ctl &= ~(BACKLIGHT_DUTY_CYCLE_MASK);
>+	/* write the updated PWM frequency */
>+	I915_WRITE(BLC_PWM_CPU_CTL, cpu_pwm_ctl | level);
>+
>+	asle->cblv = (bclp*0x64)/0xff | ASLE_CBLV_VALID;
>+
>+	return 0;
>+}
>+
>+/* Only present on Ironlake+ */
>+void intel_opregion_gse_intr(struct drm_device *dev)
>+{
>+	struct drm_i915_private *dev_priv = dev->dev_private;
>+	struct opregion_asle *asle = dev_priv->opregion.asle;
>+	u32 asle_stat = 0;
>+	u32 asle_req;
>+
>+	if (!asle)
>+		return;
>+
>+	asle_req = asle->aslc & ASLE_REQ_MSK;
>+
>+	if (!asle_req) {
>+		DRM_DEBUG_DRIVER("non asle set request??\n");
>+		return;
>+	}
>+
>+	if (asle_req & ASLE_SET_ALS_ILLUM) {
>+		DRM_DEBUG_DRIVER("Illum is not supported\n");
>+		asle_stat |= ASLE_ALS_ILLUM_FAILED;
>+	}
>+
>+	if (asle_req & ASLE_SET_BACKLIGHT)
>+		asle_stat |= asle_set_backlight_ironlake(dev, asle->bclp);
>+
>+	if (asle_req & ASLE_SET_PFIT) {
>+		DRM_DEBUG_DRIVER("Pfit is not supported\n");
>+		asle_stat |= ASLE_PFIT_FAILED;
>+	}
>+
>+	if (asle_req & ASLE_SET_PWM_FREQ) {
>+		DRM_DEBUG_DRIVER("PWM freq is not supported\n");
>+		asle_stat |= ASLE_PWM_FREQ_FAILED;
>+	}
>+
>+	asle->aslc = asle_stat;
>+}
>+#define ASLE_ALS_EN    (1<<0)
>+#define ASLE_BLC_EN    (1<<1)
>+#define ASLE_PFIT_EN   (1<<2)
>+#define ASLE_PFMB_EN   (1<<3)
>+
>+void intel_opregion_enable_asle(struct drm_device *dev)
>+{
>+	struct drm_i915_private *dev_priv = dev->dev_private;
>+	struct opregion_asle *asle = dev_priv->opregion.asle;
>+
>+	if (asle) {
>+		if (IS_MOBILE(dev)) {
>+			unsigned long irqflags;
>+
>+			spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags);
>+			intel_enable_asle(dev);
>+			spin_unlock_irqrestore(&dev_priv->user_irq_lock,
>+					       irqflags);
>+		}
>+
>+		asle->tche = ASLE_ALS_EN | ASLE_BLC_EN | ASLE_PFIT_EN |
>+			ASLE_PFMB_EN;
>+		asle->ardy = 1;
>+	}
>+}
>+
>+#define ACPI_EV_DISPLAY_SWITCH (1<<0)
>+#define ACPI_EV_LID            (1<<1)
>+#define ACPI_EV_DOCK           (1<<2)
>+
>+static struct intel_opregion *system_opregion;
>+
>+static int intel_opregion_video_event(struct notifier_block *nb,
>+				      unsigned long val, void *data)
>+{
>+	/* The only video events relevant to opregion are 0x80. These indicate
>+	   either a docking event, lid switch or display switch request. In
>+	   Linux, these are handled by the dock, button and video drivers.
>+	   We might want to fix the video driver to be opregion-aware in
>+	   future, but right now we just indicate to the firmware that the
>+	   request has been handled */
>+
>+	struct opregion_acpi *acpi;
>+
>+	if (!system_opregion)
>+		return NOTIFY_DONE;
>+
>+	acpi = system_opregion->acpi;
>+	acpi->csts = 0;
>+
>+	return NOTIFY_OK;
>+}
>+
>+static struct notifier_block intel_opregion_notifier = {
>+	.notifier_call = intel_opregion_video_event,
>+};
>+
>+/*
>+ * Initialise the DIDL field in opregion. This passes a list of devices to
>+ * the firmware. Values are defined by section B.4.2 of the ACPI specification
>+ * (version 3)
>+ */
>+
>+static void intel_didl_outputs(struct drm_device *dev)
>+{
>+	struct drm_i915_private *dev_priv = dev->dev_private;
>+	struct intel_opregion *opregion = &dev_priv->opregion;
>+	struct drm_connector *connector;
>+	acpi_handle handle;
>+	struct acpi_device *acpi_dev, *acpi_cdev, *acpi_video_bus = NULL;
>+	unsigned long long device_id;
>+	acpi_status status;
>+	int i = 0;
>+
>+	handle = DEVICE_ACPI_HANDLE(&dev->pdev->dev);
>+	if (!handle || ACPI_FAILURE(acpi_bus_get_device(handle, &acpi_dev)))
>+		return;
>+
>+	if (acpi_is_video_device(acpi_dev))
>+		acpi_video_bus = acpi_dev;
>+	else {
>+		list_for_each_entry(acpi_cdev, &acpi_dev->children, node) {
>+			if (acpi_is_video_device(acpi_cdev)) {
>+				acpi_video_bus = acpi_cdev;
>+				break;
>+			}
>+		}
>+	}
>+
>+	if (!acpi_video_bus) {
>+		printk(KERN_WARNING "No ACPI video bus found\n");
>+		return;
>+	}
>+
>+	list_for_each_entry(acpi_cdev, &acpi_video_bus->children, node) {
>+		if (i >= 8) {
>+			dev_printk (KERN_ERR, &dev->pdev->dev,
>+				    "More than 8 outputs detected\n");
>+			return;
>+		}
>+		status =
>+			acpi_evaluate_integer(acpi_cdev->handle, "_ADR",
>+						NULL, &device_id);
>+		if (ACPI_SUCCESS(status)) {
>+			if (!device_id)
>+				goto blind_set;
>+			opregion->acpi->didl[i] = (u32)(device_id & 0x0f0f);
>+			i++;
>+		}
>+	}
>+
>+end:
>+	/* If fewer than 8 outputs, the list must be null terminated */
>+	if (i < 8)
>+		opregion->acpi->didl[i] = 0;
>+	return;
>+
>+blind_set:
>+	i = 0;
>+	list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
>+		int output_type = ACPI_OTHER_OUTPUT;
>+		if (i >= 8) {
>+			dev_printk (KERN_ERR, &dev->pdev->dev,
>+				    "More than 8 outputs detected\n");
>+			return;
>+		}
>+		switch (connector->connector_type) {
>+		case DRM_MODE_CONNECTOR_VGA:
>+		case DRM_MODE_CONNECTOR_DVIA:
>+			output_type = ACPI_VGA_OUTPUT;
>+			break;
>+		case DRM_MODE_CONNECTOR_Composite:
>+		case DRM_MODE_CONNECTOR_SVIDEO:
>+		case DRM_MODE_CONNECTOR_Component:
>+		case DRM_MODE_CONNECTOR_9PinDIN:
>+			output_type = ACPI_TV_OUTPUT;
>+			break;
>+		case DRM_MODE_CONNECTOR_DVII:
>+		case DRM_MODE_CONNECTOR_DVID:
>+		case DRM_MODE_CONNECTOR_DisplayPort:
>+		case DRM_MODE_CONNECTOR_HDMIA:
>+		case DRM_MODE_CONNECTOR_HDMIB:
>+			output_type = ACPI_DIGITAL_OUTPUT;
>+			break;
>+		case DRM_MODE_CONNECTOR_LVDS:
>+			output_type = ACPI_LVDS_OUTPUT;
>+			break;
>+		}
>+		opregion->acpi->didl[i] |= (1<<31) | output_type | i;
>+		i++;
>+	}
>+	goto end;
>+}
>+
>+void intel_opregion_init(struct drm_device *dev)
>+{
>+	struct drm_i915_private *dev_priv = dev->dev_private;
>+	struct intel_opregion *opregion = &dev_priv->opregion;
>+
>+	if (!opregion->header)
>+		return;
>+
>+	if (opregion->acpi) {
>+		if (drm_core_check_feature(dev, DRIVER_MODESET))
>+			intel_didl_outputs(dev);
>+
>+		/* Notify BIOS we are ready to handle ACPI video ext notifs.
>+		 * Right now, all the events are handled by the ACPI video module.
>+		 * We don't actually need to do anything with them. */
>+		opregion->acpi->csts = 0;
>+		opregion->acpi->drdy = 1;
>+
>+		system_opregion = opregion;
>+		register_acpi_notifier(&intel_opregion_notifier);
>+	}
>+
>+	if (opregion->asle)
>+		intel_opregion_enable_asle(dev);
>+}
>+
>+void intel_opregion_fini(struct drm_device *dev)
>+{
>+	struct drm_i915_private *dev_priv = dev->dev_private;
>+	struct intel_opregion *opregion = &dev_priv->opregion;
>+
>+	if (!opregion->header)
>+		return;
>+
>+	if (opregion->acpi) {
>+		opregion->acpi->drdy = 0;
>+
>+		system_opregion = NULL;
>+		unregister_acpi_notifier(&intel_opregion_notifier);
>+	}
>+
>+	/* just clear all opregion memory pointers now */
>+	iounmap(opregion->header);
>+	opregion->header = NULL;
>+	opregion->acpi = NULL;
>+	opregion->swsci = NULL;
>+	opregion->asle = NULL;
>+	opregion->vbt = NULL;
>+}
>+#endif
>+
>+int intel_opregion_setup(struct drm_device *dev)
>+{
>+	struct drm_i915_private *dev_priv = dev->dev_private;
>+	struct intel_opregion *opregion = &dev_priv->opregion;
>+	void *base;
>+	u32 asls, mboxes;
>+	int err = 0;
>+
>+	pci_read_config_dword(dev->pdev, PCI_ASLS, &asls);
>+	DRM_DEBUG_DRIVER("graphic opregion physical addr: 0x%x\n", asls);
>+	if (asls == 0) {
>+		DRM_DEBUG_DRIVER("ACPI OpRegion not supported!\n");
>+		return -ENOTSUPP;
>+	}
>+
>+	base = ioremap(asls, OPREGION_SIZE);
>+	if (!base)
>+		return -ENOMEM;
>+
>+	if (memcmp(base, OPREGION_SIGNATURE, 16)) {
>+		DRM_DEBUG_DRIVER("opregion signature mismatch\n");
>+		err = -EINVAL;
>+		goto err_out;
>+	}
>+	opregion->header = base;
>+	opregion->vbt = base + OPREGION_VBT_OFFSET;
>+
>+	mboxes = opregion->header->mboxes;
>+	if (mboxes & MBOX_ACPI) {
>+		DRM_DEBUG_DRIVER("Public ACPI methods supported\n");
>+		opregion->acpi = base + OPREGION_ACPI_OFFSET;
>+	}
>+
>+	if (mboxes & MBOX_SWSCI) {
>+		DRM_DEBUG_DRIVER("SWSCI supported\n");
>+		opregion->swsci = base + OPREGION_SWSCI_OFFSET;
>+	}
>+	if (mboxes & MBOX_ASLE) {
>+		DRM_DEBUG_DRIVER("ASLE supported\n");
>+		opregion->asle = base + OPREGION_ASLE_OFFSET;
>+	}
>+
>+	return 0;
>+
>+err_out:
>+	iounmap(opregion->header);
>+	return err;
>+}
>diff --git a/drivers/gpu/drm/i915/intel_sdvo.c b/drivers/gpu/drm/i915/intel_sdvo.c
>index 62d22ae..e3b7a7e 100644
>--- a/drivers/gpu/drm/i915/intel_sdvo.c
>+++ b/drivers/gpu/drm/i915/intel_sdvo.c
>@@ -1929,6 +1929,41 @@ static const struct drm_encoder_funcs intel_sdvo_enc_funcs = {
> 	.destroy = intel_sdvo_enc_destroy,
> };
> 
>+static void
>+intel_sdvo_guess_ddc_bus(struct intel_sdvo *sdvo)
>+{
>+	uint16_t mask = 0;
>+	unsigned int num_bits;
>+
>+	/* Make a mask of outputs less than or equal to our own priority in the
>+	 * list.
>+	 */
>+	switch (sdvo->controlled_output) {
>+	case SDVO_OUTPUT_LVDS1:
>+		mask |= SDVO_OUTPUT_LVDS1;
>+	case SDVO_OUTPUT_LVDS0:
>+		mask |= SDVO_OUTPUT_LVDS0;
>+	case SDVO_OUTPUT_TMDS1:
>+		mask |= SDVO_OUTPUT_TMDS1;
>+	case SDVO_OUTPUT_TMDS0:
>+		mask |= SDVO_OUTPUT_TMDS0;
>+	case SDVO_OUTPUT_RGB1:
>+		mask |= SDVO_OUTPUT_RGB1;
>+	case SDVO_OUTPUT_RGB0:
>+		mask |= SDVO_OUTPUT_RGB0;
>+		break;
>+	}
>+
>+	/* Count bits to find what number we are in the priority list. */
>+	mask &= sdvo->caps.output_flags;
>+	num_bits = hweight16(mask);
>+	/* If more than 3 outputs, default to DDC bus 3 for now. */
>+	if (num_bits > 3)
>+		num_bits = 3;
>+
>+	/* Corresponds to SDVO_CONTROL_BUS_DDCx */
>+	sdvo->ddc_bus = 1 << num_bits;
>+}
> 
> /**
>  * Choose the appropriate DDC bus for control bus switch command for this
>@@ -1948,7 +1983,10 @@ intel_sdvo_select_ddc_bus(struct drm_i915_private *dev_priv,
> 	else
> 		mapping = &(dev_priv->sdvo_mappings[1]);
> 
>-	sdvo->ddc_bus = 1 << ((mapping->ddc_pin & 0xf0) >> 4);
>+	if (mapping->initialized)
>+		sdvo->ddc_bus = 1 << ((mapping->ddc_pin & 0xf0) >> 4);
>+	else
>+		intel_sdvo_guess_ddc_bus(sdvo);
> }
> 
> static bool
>diff --git a/drivers/gpu/drm/i915/intel_tv.c b/drivers/gpu/drm/i915/intel_tv.c
>index d2029ef..19b9739 100644
>--- a/drivers/gpu/drm/i915/intel_tv.c
>+++ b/drivers/gpu/drm/i915/intel_tv.c
>@@ -1157,10 +1157,13 @@ intel_tv_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
> 		I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
> 
> 		/* Wait for vblank for the disable to take effect */
>-		if (!IS_I9XX(dev))
>+		if (!IS_I9XX(dev)) {
>+			POSTING_READ(dspbase_reg);
> 			intel_wait_for_vblank(dev, intel_crtc->pipe);
>+		}
> 
> 		I915_WRITE(pipeconf_reg, pipeconf & ~PIPEACONF_ENABLE);
>+		POSTING_READ(pipeconf_reg);
> 		/* Wait for vblank for the disable to take effect. */
> 		intel_wait_for_vblank(dev, intel_crtc->pipe);
> 
>@@ -1268,11 +1271,15 @@ intel_tv_detect_type (struct intel_tv *intel_tv)
> 		   DAC_C_0_7_V);
> 	I915_WRITE(TV_CTL, tv_ctl);
> 	I915_WRITE(TV_DAC, tv_dac);
>+	POSTING_READ(TV_DAC);
> 	intel_wait_for_vblank(dev, intel_crtc->pipe);
>+
> 	tv_dac = I915_READ(TV_DAC);
> 	I915_WRITE(TV_DAC, save_tv_dac);
> 	I915_WRITE(TV_CTL, save_tv_ctl);
>+	POSTING_READ(TV_CTL);
> 	intel_wait_for_vblank(dev, intel_crtc->pipe);
>+
> 	/*
> 	 *  A B C
> 	 *  0 1 1 Composite

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Attachments on bug 29449: 37689 | 37690 | 37691 | 37692 | 37693 | 37818 | 38473

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