Attachment 38581 Details for Bug 29082 – don't enable self-refresh on ilk

[patch] don't enable self-refresh on ilk

0001-drm-i915-don-t-enable-self-refresh-on-Ironlake.patch (text/plain), 2.27 KB, created by Jesse Barnes on 2010-09-09 11:56:43 UTC

(hide)

Description:

Filename:

MIME Type:

Creator: Jesse Barnes

Created: 2010-09-09 11:56:43 UTC

Size: 2.27 KB

patch

obsolete

>From e5eb85f840db5e1e5fe1f0351f9f82ea82afb438 Mon Sep 17 00:00:00 2001
>From: Jesse Barnes <jbarnes@virtuousgeek.org>
>Date: Thu, 9 Sep 2010 11:53:41 -0700
>Subject: [PATCH] drm/i915: don't enable self-refresh on Ironlake
>
>We don't know how to enable it safely, especially as outputs turn on and
>off.  When disabling LP1 we also need to make sure LP2 and 3 are already
>disabled.
>
>Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
>---
> drivers/gpu/drm/i915/i915_reg.h      |    8 ++++++++
> drivers/gpu/drm/i915/intel_display.c |    6 ++++--
> 2 files changed, 12 insertions(+), 2 deletions(-)
>
>diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
>index d0b4b23..aa82b0a 100644
>--- a/drivers/gpu/drm/i915/i915_reg.h
>+++ b/drivers/gpu/drm/i915/i915_reg.h
>@@ -2215,9 +2215,17 @@
> #define  WM1_LP_SR_EN		(1<<31)
> #define  WM1_LP_LATENCY_SHIFT	24
> #define  WM1_LP_LATENCY_MASK	(0x7f<<24)
>+#define  WM1_LP_FBC_LP1_MASK	(0xf<<20)
>+#define  WM1_LP_FBC_LP1_SHIFT	20
> #define  WM1_LP_SR_MASK		(0x1ff<<8)
> #define  WM1_LP_SR_SHIFT	8
> #define  WM1_LP_CURSOR_MASK	(0x3f)
>+#define WM2_LP_ILK		0x4510c
>+#define  WM2_LP_EN		(1<<31)
>+#define WM3_LP_ILK		0x45110
>+#define  WM3_LP_EN		(1<<31)
>+#define WM1S_LP_ILK		0x45120
>+#define  WM1S_LP_EN		(1<<31)
> 
> /* Memory latency timer register */
> #define MLTR_ILK		0x11222
>diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
>index 4b23646..8997bb7 100644
>--- a/drivers/gpu/drm/i915/intel_display.c
>+++ b/drivers/gpu/drm/i915/intel_display.c
>@@ -3395,8 +3395,7 @@ static void ironlake_update_wm(struct drm_device *dev,  int planea_clock,
> 		reg_value = I915_READ(WM1_LP_ILK);
> 		reg_value &= ~(WM1_LP_LATENCY_MASK | WM1_LP_SR_MASK |
> 			       WM1_LP_CURSOR_MASK);
>-		reg_value |= WM1_LP_SR_EN |
>-			     (ilk_sr_latency << WM1_LP_LATENCY_SHIFT) |
>+		reg_value |= (ilk_sr_latency << WM1_LP_LATENCY_SHIFT) |
> 			     (sr_wm << WM1_LP_SR_SHIFT) | cursor_wm;
> 
> 		I915_WRITE(WM1_LP_ILK, reg_value);
>@@ -5718,6 +5717,9 @@ void intel_init_clock_gating(struct drm_device *dev)
> 			I915_WRITE(DISP_ARB_CTL,
> 					(I915_READ(DISP_ARB_CTL) |
> 						DISP_FBC_WM_DIS));
>+		I915_WRITE(WM3_LP_ILK, 0);
>+		I915_WRITE(WM2_LP_ILK, 0);
>+		I915_WRITE(WM1_LP_ILK, 0);
> 		}
> 		/*
> 		 * Based on the document from hardware guys the following bits
>-- 
>1.6.3.3
>

Actions: View | Splinter Review

Attachments on bug 29082: 37080 | 37081 | 37082 | 37083 | 37088 | 37089 | 37090 | 37091 | 37092 | 37093 | 37094 | 37095 | 37096 | 37192 | 37567 | 38581

Use of freedesktop.org services, including Bugzilla, is subject to our Code of Conduct. How we collect and use information is described in our Privacy Policy.