Attachment 40129 Details for Bug 29647 – fulltext of intel_reg_dumper showing diff between no-fb (as -) and intelfb (as +)

fulltext of intel_reg_dumper showing diff between no-fb (as -) and intelfb (as +)

intel_reg_dumb-diff-vesa-to-intelfb-with-hacks.txt (text/plain), 11.95 KB, created by Vietor Davis on 2010-11-08 15:22:55 UTC

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Creator: Vietor Davis

Created: 2010-11-08 15:22:55 UTC

Size: 11.95 KB

patch

obsolete

>--- vesa.dmp	2010-11-08 14:17:00.482271740 -0800
>+++ intelfb.dmp5	2010-11-08 15:02:46.841398080 -0800
>@@ -1,164 +1,164 @@
>                     PGETBL_CTL: 0x00000001
>                GEN6_INSTDONE_1: 0xfffffffe
>                GEN6_INSTDONE_2: 0xffffffff
>-                  CPU_VGACNTRL: 0x0020298e (enabled)
>+                  CPU_VGACNTRL: 0x80000000 (disabled)
>     DIGITAL_PORT_HOTPLUG_CNTRL: 0x00000000
>                      RR_HW_CTL: 0x00000000 (low 0, high 0)
>                 FDI_PLL_BIOS_0: 0x082b3019
>                 FDI_PLL_BIOS_1: 0x00000000
>                 FDI_PLL_BIOS_2: 0x00000000
>        DISPLAY_PORT_PLL_BIOS_0: 0x0807012b
>        DISPLAY_PORT_PLL_BIOS_1: 0x00000000
>        DISPLAY_PORT_PLL_BIOS_2: 0x00000000
>               FDI_PLL_FREQ_CTL: 0x00053687
>-                     PIPEACONF: 0xc0000050 (enabled, active, 6bpc)
>+                     PIPEACONF: 0xc0000054 (enabled, active, 6bpc)
>                       HTOTAL_A: 0x05af0555 (1366 active, 1456 total)
>                       HBLANK_A: 0x05af0555 (1366 start, 1456 end)
>                        HSYNC_A: 0x05a50585 (1414 start, 1446 end)
>                       VTOTAL_A: 0x031802ff (768 active, 793 total)
>                       VBLANK_A: 0x031802ff (768 start, 793 end)
>                        VSYNC_A: 0x03080302 (771 start, 777 end)
>                   VSYNCSHIFT_A: 0x00000000
>-                      PIPEASRC: 0x027f018f (640, 400)
>+                      PIPEASRC: 0x055502ff (1366, 768)
>                  PIPEA_DATA_M1: 0x7e127ae1 (TU 64, val 0x127ae1 1211105)
>                  PIPEA_DATA_N1: 0x00800000 (val 0x800000 8388608)
>                  PIPEA_DATA_M2: 0x00000000 (TU 1, val 0x0 0)
>                  PIPEA_DATA_N2: 0x00000000 (val 0x0 0)
>                  PIPEA_LINK_M1: 0x00020da7 (val 0x20da7 134567)
>                  PIPEA_LINK_N1: 0x00080000 (val 0x80000 524288)
>                  PIPEA_LINK_M2: 0x00000000 (val 0x0 0)
>                  PIPEA_LINK_N2: 0x00000000 (val 0x0 0)
>-                      DSPACNTR: 0x18000000 (disabled)
>+                      DSPACNTR: 0xd8004000 (enabled)
>                       DSPABASE: 0x00000000
>-                    DSPASTRIDE: 0x00001000 (64)
>-                      DSPASURF: 0x00000000
>+                    DSPASTRIDE: 0x00001580 (86)
>+                      DSPASURF: 0x02042000
>                    DSPATILEOFF: 0x00000000 (0, 0)
>                      PIPEBCONF: 0x00000000 (disabled, inactive, 8bpc)
>                       HTOTAL_B: 0x031f027f (640 active, 800 total)
>                       HBLANK_B: 0x03170287 (648 start, 792 end)
>                        HSYNC_B: 0x02ef028f (656 start, 752 end)
>                       VTOTAL_B: 0x020c01df (480 active, 525 total)
>                       VBLANK_B: 0x020401e7 (488 start, 517 end)
>                        VSYNC_B: 0x01eb01e9 (490 start, 492 end)
>                   VSYNCSHIFT_B: 0x00000000
>                       DSPBCNTR: 0x00000000 (disabled)
>                       DSPBBASE: 0x00000000
>                     DSPBSTRIDE: 0x00000000 (0)
>                       DSPBSURF: 0x00000000
>                    DSPBTILEOFF: 0x00000000 (0, 0)
>                       PIPEBSRC: 0x027f01df (640, 480)
>                  PIPEB_DATA_M1: 0x00000000 (TU 1, val 0x0 0)
>                  PIPEB_DATA_N1: 0x00000000 (val 0x0 0)
>                  PIPEB_DATA_M2: 0x00000000 (TU 1, val 0x0 0)
>                  PIPEB_DATA_N2: 0x00000000 (val 0x0 0)
>                  PIPEB_LINK_M1: 0x00000000 (val 0x0 0)
>                  PIPEB_LINK_N1: 0x00000000 (val 0x0 0)
>                  PIPEB_LINK_M2: 0x00000000 (val 0x0 0)
>                  PIPEB_LINK_N2: 0x00000000 (val 0x0 0)
>-                     PFA_CTL_1: 0x80800000 (enable, auto_scale yes, auto_scale_cal no, v_filter enable, vadapt disable, mode least, filter_sel hardcoded,chroma pre-filter disable, vert3tap auto, v_inter_invert field 1)
>+                     PFA_CTL_1: 0x00000000 (disable, auto_scale yes, auto_scale_cal no, v_filter enable, vadapt disable, mode least, filter_sel programmed,chroma pre-filter disable, vert3tap auto, v_inter_invert field 1)
>                      PFA_CTL_2: 0x000042ab (vscale 0.520844)
>                      PFA_CTL_3: 0x00002155 (vscale initial phase 0.260406)
>-                     PFA_CTL_4: 0x00004378 (hscale 0.527100)
>+                     PFA_CTL_4: 0x00003bf8 (hscale 0.468506)
>                    PFA_WIN_POS: 0x00000000 (0, 0)
>-                  PFA_WIN_SIZE: 0x05560300 (1366, 768)
>+                  PFA_WIN_SIZE: 0x00000000 (0, 0)
>                      PFB_CTL_1: 0x00000000 (disable, auto_scale yes, auto_scale_cal no, v_filter enable, vadapt disable, mode least, filter_sel programmed,chroma pre-filter disable, vert3tap auto, v_inter_invert field 1)
>                      PFB_CTL_2: 0x00000000 (vscale 0.000000)
>                      PFB_CTL_3: 0x00000000 (vscale initial phase 0.000000)
>                      PFB_CTL_4: 0x00000000 (hscale 0.000000)
>                    PFB_WIN_POS: 0x00000000 (0, 0)
>                   PFB_WIN_SIZE: 0x00000000 (0, 0)
>               PCH_DREF_CONTROL: 0x00001002 (cpu source disable, ssc_source enable, nonspread_source disable, superspread_source disable, ssc4_mode downspread, ssc1 enable, ssc4 disable)
>                PCH_RAWCLK_FREQ: 0x0000007d (FDL_TP1 timer 0.5us, FDL_TP2 timer 1.5us, freq 125)
>               PCH_DPLL_TMR_CFG: 0x0271186a
>                 PCH_SSC4_PARMS: 0x00000000
>             PCH_SSC4_AUX_PARMS: 0x00000000
>            PCH_DPLL_ANALOG_CTL: 0x00008000
>                     PCH_DPLL_A: 0x88046004 (enable, sdvo high speed no, mode LVDS, p2 Div 14, FPA0 P1 3, FPA1 P1 3, refclk SSC, sdvo/hdmi mul 1)
>                     PCH_DPLL_B: 0x04800080 (disable, sdvo high speed no, mode (null), p2 (null), FPA0 P1 8, FPA1 P1 8, refclk default 120Mhz, sdvo/hdmi mul 1)
>                       PCH_FPA0: 0x00010e05 (n = 1, m1 = 14, m2 = 5)
>-                      PCH_FPA1: 0x00030d07 (n = 3, m1 = 13, m2 = 7)
>+                      PCH_FPA1: 0x00010e05 (n = 1, m1 = 14, m2 = 5)
>                       PCH_FPB0: 0x00030d07 (n = 3, m1 = 13, m2 = 7)
>                       PCH_FPB1: 0x00030d07 (n = 3, m1 = 13, m2 = 7)
>                 TRANS_HTOTAL_A: 0x05af0555 (1366 active, 1456 total)
>                 TRANS_HBLANK_A: 0x05af0555 (1366 start, 1456 end)
>                  TRANS_HSYNC_A: 0x05a50585 (1414 start, 1446 end)
>                 TRANS_VTOTAL_A: 0x031802ff (768 active, 793 total)
>                 TRANS_VBLANK_A: 0x031802ff (768 start, 793 end)
>                  TRANS_VSYNC_A: 0x03080302 (771 start, 777 end)
>                 TRANSA_DATA_M1: 0x00000000 (TU 1, val 0x0 0)
>                 TRANSA_DATA_N1: 0x00000000 (val 0x0 0)
>                 TRANSA_DATA_M2: 0x00000000 (TU 1, val 0x0 0)
>                 TRANSA_DATA_N2: 0x00000000 (val 0x0 0)
>              TRANSA_DP_LINK_M1: 0x00000000 (val 0x0 0)
>              TRANSA_DP_LINK_N1: 0x00000000 (val 0x0 0)
>              TRANSA_DP_LINK_M2: 0x00000000 (val 0x0 0)
>              TRANSA_DP_LINK_N2: 0x00000000 (val 0x0 0)
>                 TRANS_HTOTAL_B: 0x031f027f (640 active, 800 total)
>                 TRANS_HBLANK_B: 0x03170287 (648 start, 792 end)
>                  TRANS_HSYNC_B: 0x02ef028f (656 start, 752 end)
>                 TRANS_VTOTAL_B: 0x020c01df (480 active, 525 total)
>                 TRANS_VBLANK_B: 0x020401e7 (488 start, 517 end)
>                  TRANS_VSYNC_B: 0x01eb01e9 (490 start, 492 end)
>                 TRANSB_DATA_M1: 0x00000000 (TU 1, val 0x0 0)
>                 TRANSB_DATA_N1: 0x00000000 (val 0x0 0)
>                 TRANSB_DATA_M2: 0x00000000 (TU 1, val 0x0 0)
>                 TRANSB_DATA_N2: 0x00000000 (val 0x0 0)
>              TRANSB_DP_LINK_M1: 0x00000000 (val 0x0 0)
>              TRANSB_DP_LINK_N1: 0x00000000 (val 0x0 0)
>              TRANSB_DP_LINK_M2: 0x00000000 (val 0x0 0)
>              TRANSB_DP_LINK_N2: 0x00000000 (val 0x0 0)
>                 TRANS_HTOTAL_C: 0x00000000 (1 active, 1 total)
>                 TRANS_HBLANK_C: 0x00000000 (1 start, 1 end)
>                  TRANS_HSYNC_C: 0x00000000 (1 start, 1 end)
>                 TRANS_VTOTAL_C: 0x00000000 (1 active, 1 total)
>                 TRANS_VBLANK_C: 0x00000044 (69 start, 1 end)
>                  TRANS_VSYNC_C: 0x00000000 (1 start, 1 end)
>                 TRANSC_DATA_M1: 0x00000000 (TU 1, val 0x0 0)
>                 TRANSC_DATA_N1: 0x00000000 (val 0x0 0)
>                 TRANSC_DATA_M2: 0x00000000 (TU 1, val 0x0 0)
>                 TRANSC_DATA_N2: 0x00000000 (val 0x0 0)
>              TRANSC_DP_LINK_M1: 0x00000000 (val 0x0 0)
>              TRANSC_DP_LINK_N1: 0x00000000 (val 0x0 0)
>              TRANSC_DP_LINK_M2: 0x00000000 (val 0x0 0)
>              TRANSC_DP_LINK_N2: 0x00ffffff (val 0xffffff 16777215)
>                     TRANSACONF: 0xc0000040 (enable, active)
>                     TRANSBCONF: 0x00000000 (disable, inactive)
>                     TRANSCCONF: 0x00000000 (disable, inactive)
>                    FDI_TXA_CTL: 0xb01c4000 (enable, train pattern not train, voltage swing 0.4V,pre-emphasis none, port width X4, enhanced framing enable, FDI PLL enable, scrambing enable, master mode disable)
>                    FDI_TXB_CTL: 0x00044000 (disable, train pattern pattern_1, voltage swing 0.4V,pre-emphasis none, port width X1, enhanced framing enable, FDI PLL enable, scrambing enable, master mode disable)
>                    FDI_RXA_CTL: 0xb01a2050 (enable, train pattern not train, port width X4, 6bpc,link_reverse_strap_overwrite no, dmi_link_reverse no, FDI PLL enable,FS ecc disable, FE ecc disable, FS err report disable, FE err report disable,scrambing enable, enhanced framing enable, PCDClk)
>                    FDI_RXB_CTL: 0x00000040 (disable, train pattern pattern_1, port width X1, 8bpc,link_reverse_strap_overwrite no, dmi_link_reverse no, FDI PLL disable,FS ecc disable, FE ecc disable, FS err report disable, FE err report disable,scrambing enable, enhanced framing enable, RawClk)
>                    FDI_RXC_CTL: 0x00000000 (disable, train pattern pattern_1, port width X1, 8bpc,link_reverse_strap_overwrite no, dmi_link_reverse no, FDI PLL disable,FS ecc disable, FE ecc disable, FS err report disable, FE err report disable,scrambing enable, enhanced framing disable, RawClk)
>                   FDI_RXA_MISC: 0x00000080 (FDI Delay 128)
>                   FDI_RXB_MISC: 0x00000080 (FDI Delay 128)
>                   FDI_RXC_MISC: 0x00000000 (FDI Delay 0)
>                FDI_RXA_TUSIZE1: 0x7e000000
>                FDI_RXA_TUSIZE2: 0x7e000000
>                FDI_RXB_TUSIZE1: 0x7e000000
>                FDI_RXB_TUSIZE2: 0x7e000000
>                FDI_RXC_TUSIZE1: 0x00000000
>                FDI_RXC_TUSIZE2: 0x00000000
>                  FDI_PLL_CTL_1: 0x33505248
>                  FDI_PLL_CTL_2: 0x00000000
>-                   FDI_RXA_IIR: 0x00000600
>+                   FDI_RXA_IIR: 0x00000000
>                    FDI_RXA_IMR: 0x000000ff
>                    FDI_RXB_IIR: 0x00000000
>                    FDI_RXB_IMR: 0x000000ff
>                       PCH_ADPA: 0x00c00018 (disabled, transcoder A, +hsync, +vsync)
>                          HDMIB: 0x0000089c (disabled pipe A 8bpc TMDS DVI audio disabled +vsync +hsync detected)
>                          HDMIC: 0x00000018 (disabled pipe A 8bpc SDVO DVI audio disabled +vsync +hsync non-detected)
>                          HDMID: 0x00000018 (disabled pipe A 8bpc SDVO DVI audio disabled +vsync +hsync non-detected)
>                       PCH_LVDS: 0x80308302 (enabled, pipe A, 18 bit, 1 channel)
>                      CPU_eDP_A: 0x00000018
>-                      PCH_DP_B: 0x0000001c
>+                      PCH_DP_B: 0x00000004
>                       PCH_DP_C: 0x00000018
>                       PCH_DP_D: 0x00000018
>-              BLC_PWM_CPU_CTL2: 0x00000000
>-               BLC_PWM_CPU_CTL: 0x00000000
>+              BLC_PWM_CPU_CTL2: 0xa0000000
>+               BLC_PWM_CPU_CTL: 0x00000001
>               BLC_PWM_PCH_CTL1: 0x80000000
>               BLC_PWM_PCH_CTL2: 0x00000000
>                  PCH_PP_STATUS: 0xc0000008 (on, ready, sequencing idle)
>                 PCH_PP_CONTROL: 0x00000003 (blacklight disabled, power down on reset, panel on)
>               PCH_PP_ON_DELAYS: 0x012c0bb8
>              PCH_PP_OFF_DELAYS: 0x012c0bb8
>                 PCH_PP_DIVISOR: 0x00186906

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Attachments on bug 29647: 37954 | 37955 | 37956 | 38010 | 38133 | 38134 | 38486 | 38513 | 38514 | 38633 | 40129

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