Attachment 41388 Details for Bug 32589 – dmesg

dmesg

clipflat.dmesg (text/plain), 62.98 KB, created by Yi Sun on 2010-12-22 17:30:33 UTC

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Filename:

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Creator: Yi Sun

Created: 2010-12-22 17:30:33 UTC

Size: 62.98 KB

patch

obsolete

>[drm:drm_crtc_helper_set_config], 
>[drm:drm_crtc_helper_set_config], [CRTC:3] [FB:40] #connectors=1 (x y) (0 0)
>[drm:drm_crtc_helper_set_config], [CONNECTOR:9:VGA-1] to [CRTC:3]
>[drm:drm_crtc_helper_set_config], Setting connector DPMS state to on
>[drm:drm_crtc_helper_set_config], 	[CONNECTOR:9:VGA-1] set DPMS on
>[drm:i915_driver_open], 
>[drm:drm_crtc_helper_set_config], 
>[drm:drm_crtc_helper_set_config], [CRTC:3] [FB:40] #connectors=1 (x y) (0 0)
>[drm:drm_crtc_helper_set_config], [CONNECTOR:9:VGA-1] to [CRTC:3]
>[drm:drm_crtc_helper_set_config], Setting connector DPMS state to on
>[drm:drm_crtc_helper_set_config], 	[CONNECTOR:9:VGA-1] set DPMS on
>[drm:drm_crtc_helper_set_config], 
>[drm:drm_crtc_helper_set_config], [CRTC:4] [FB:40] #connectors=0 (x y) (0 0)
>[drm:drm_crtc_helper_set_config], crtc has no fb, full mode set
>[drm:drm_crtc_helper_set_config], [CONNECTOR:9:VGA-1] to [CRTC:3]
>[drm:drm_crtc_helper_set_config], Setting connector DPMS state to on
>[drm:i915_driver_open], 
>[drm:i915_getparam], Unknown parameter 12
>[drm:drm_mode_getresources], CRTC[2] CONNECTORS[6] ENCODERS[6]
>[drm:drm_mode_getresources], CRTC[2] CONNECTORS[6] ENCODERS[6]
>[drm:drm_mode_getconnector], [CONNECTOR:5:?]
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:5:LVDS-1]
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:5:LVDS-1] disconnected
>[drm:drm_mode_getconnector], [CONNECTOR:5:?]
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:5:LVDS-1]
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:5:LVDS-1] disconnected
>[drm:drm_mode_getconnector], [CONNECTOR:9:?]
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:9:VGA-1]
>[drm:intel_ironlake_crt_detect_hotplug], ironlake hotplug adpa=0x83f40010, result 1
>[drm:intel_crt_detect], CRT detected via hotplug
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:9:VGA-1] probed modes :
>[drm:drm_mode_debug_printmodeline], Modeline 24:"1920x1200" 60 193250 1920 2056 2256 2592 1200 1203 1209 1245 0x48 0x6
>[drm:drm_mode_debug_printmodeline], Modeline 26:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 30:"1680x1050" 60 146250 1680 1784 1960 2240 1050 1053 1059 1089 0x40 0x6
>[drm:drm_mode_debug_printmodeline], Modeline 35:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 25:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 28:"1280x800" 60 83500 1280 1352 1480 1680 800 803 809 831 0x40 0x9
>[drm:drm_mode_debug_printmodeline], Modeline 27:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 29:"1280x720" 60 74440 1280 1336 1472 1664 720 721 724 746 0x0 0x6
>[drm:drm_mode_debug_printmodeline], Modeline 36:"1024x768" 75 78800 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 37:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 38:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 31:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 32:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 33:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 34:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[drm:drm_mode_getconnector], [CONNECTOR:9:?]
>[drm:drm_mode_getconnector], [CONNECTOR:12:?]
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:12:HDMI Type A-1]
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:12:HDMI Type A-1] disconnected
>[drm:drm_mode_getconnector], [CONNECTOR:12:?]
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:12:HDMI Type A-1]
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:12:HDMI Type A-1] disconnected
>[drm:drm_mode_getconnector], [CONNECTOR:15:?]
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:15:HDMI Type A-2]
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:15:HDMI Type A-2] disconnected
>[drm:drm_mode_getconnector], [CONNECTOR:15:?]
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:15:HDMI Type A-2]
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:15:HDMI Type A-2] disconnected
>[drm:drm_mode_getconnector], [CONNECTOR:17:?]
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:17:DisplayPort-1]
>[drm:intel_dp_aux_ch], dp_aux_ch timeout status 0x5143003e
>[drm:ironlake_dp_detect], DPCD: 0000
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:17:DisplayPort-1] disconnected
>[drm:drm_mode_getconnector], [CONNECTOR:17:?]
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:17:DisplayPort-1]
>[drm:intel_dp_aux_ch], dp_aux_ch timeout status 0x5143003e
>[drm:ironlake_dp_detect], DPCD: 0000
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:17:DisplayPort-1] disconnected
>[drm:drm_mode_getconnector], [CONNECTOR:20:?]
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:20:DisplayPort-2]
>[drm:intel_dp_aux_ch], dp_aux_ch timeout status 0x5143003e
>[drm:ironlake_dp_detect], DPCD: 0000
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:20:DisplayPort-2] disconnected
>[drm:drm_mode_getconnector], [CONNECTOR:20:?]
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:20:DisplayPort-2]
>[drm:intel_dp_aux_ch], dp_aux_ch timeout status 0x5143003e
>[drm:ironlake_dp_detect], DPCD: 0000
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:20:DisplayPort-2] disconnected
>[drm:drm_mode_getconnector], [CONNECTOR:5:?]
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:5:LVDS-1]
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:5:LVDS-1] disconnected
>[drm:drm_mode_getconnector], [CONNECTOR:5:?]
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:5:LVDS-1]
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:5:LVDS-1] disconnected
>[drm:drm_mode_getconnector], [CONNECTOR:9:?]
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:9:VGA-1]
>[drm:intel_ironlake_crt_detect_hotplug], ironlake hotplug adpa=0x83f40010, result 1
>[drm:intel_crt_detect], CRT detected via hotplug
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:9:VGA-1] probed modes :
>[drm:drm_mode_debug_printmodeline], Modeline 24:"1920x1200" 60 193250 1920 2056 2256 2592 1200 1203 1209 1245 0x48 0x6
>[drm:drm_mode_debug_printmodeline], Modeline 26:"1600x1200" 60 162000 1600 1664 1856 2160 1200 1201 1204 1250 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 30:"1680x1050" 60 146250 1680 1784 1960 2240 1050 1053 1059 1089 0x40 0x6
>[drm:drm_mode_debug_printmodeline], Modeline 35:"1280x1024" 75 135000 1280 1296 1440 1688 1024 1025 1028 1066 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 25:"1280x1024" 60 108000 1280 1328 1440 1688 1024 1025 1028 1066 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 28:"1280x800" 60 83500 1280 1352 1480 1680 800 803 809 831 0x40 0x9
>[drm:drm_mode_debug_printmodeline], Modeline 27:"1152x864" 75 108000 1152 1216 1344 1600 864 865 868 900 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 29:"1280x720" 60 74440 1280 1336 1472 1664 720 721 724 746 0x0 0x6
>[drm:drm_mode_debug_printmodeline], Modeline 36:"1024x768" 75 78800 1024 1040 1136 1312 768 769 772 800 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 37:"1024x768" 60 65000 1024 1048 1184 1344 768 771 777 806 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 38:"800x600" 75 49500 800 816 896 1056 600 601 604 625 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 31:"800x600" 60 40000 800 840 968 1056 600 601 605 628 0x40 0x5
>[drm:drm_mode_debug_printmodeline], Modeline 32:"640x480" 75 31500 640 656 720 840 480 481 484 500 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 33:"640x480" 60 25200 640 656 752 800 480 490 492 525 0x40 0xa
>[drm:drm_mode_debug_printmodeline], Modeline 34:"720x400" 70 28320 720 738 846 900 400 412 414 449 0x40 0x6
>[drm:drm_mode_getconnector], [CONNECTOR:9:?]
>[drm:drm_mode_getconnector], [CONNECTOR:12:?]
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:12:HDMI Type A-1]
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:12:HDMI Type A-1] disconnected
>[drm:drm_mode_getconnector], [CONNECTOR:12:?]
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:12:HDMI Type A-1]
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:12:HDMI Type A-1] disconnected
>[drm:drm_mode_getconnector], [CONNECTOR:15:?]
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:15:HDMI Type A-2]
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:15:HDMI Type A-2] disconnected
>[drm:drm_mode_getconnector], [CONNECTOR:15:?]
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:15:HDMI Type A-2]
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:15:HDMI Type A-2] disconnected
>[drm:drm_mode_getconnector], [CONNECTOR:17:?]
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:17:DisplayPort-1]
>[drm:intel_dp_aux_ch], dp_aux_ch timeout status 0x5143003e
>[drm:ironlake_dp_detect], DPCD: 0000
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:17:DisplayPort-1] disconnected
>[drm:drm_mode_getconnector], [CONNECTOR:17:?]
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:17:DisplayPort-1]
>[drm:intel_dp_aux_ch], dp_aux_ch timeout status 0x5143003e
>[drm:ironlake_dp_detect], DPCD: 0000
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:17:DisplayPort-1] disconnected
>[drm:drm_mode_getconnector], [CONNECTOR:20:?]
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:20:DisplayPort-2]
>[drm:intel_dp_aux_ch], dp_aux_ch timeout status 0x5143003e
>[drm:ironlake_dp_detect], DPCD: 0000
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:20:DisplayPort-2] disconnected
>[drm:drm_mode_getconnector], [CONNECTOR:20:?]
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:20:DisplayPort-2]
>[drm:intel_dp_aux_ch], dp_aux_ch timeout status 0x5143003e
>[drm:ironlake_dp_detect], DPCD: 0000
>[drm:drm_helper_probe_single_connector_modes], [CONNECTOR:20:DisplayPort-2] disconnected
>[drm:i915_getparam], Unknown parameter 12
>[drm:i915_getparam], Unknown parameter 12
>[drm:drm_mode_addfb], [FB:41]
>[drm:drm_mode_setcrtc], [CRTC:3]
>[drm:drm_mode_setcrtc], [CONNECTOR:9:VGA-1]
>[drm:drm_crtc_helper_set_config], 
>[drm:drm_crtc_helper_set_config], [CRTC:3] [FB:41] #connectors=1 (x y) (0 0)
>[drm:drm_crtc_helper_set_config], [CONNECTOR:9:VGA-1] to [CRTC:3]
>[drm:intel_pipe_set_base_atomic], Writing base 02931000 00000000 0 0 8192
>[drm:intel_update_fbc], 
>[drm:drm_crtc_helper_set_config], Setting connector DPMS state to on
>[drm:drm_crtc_helper_set_config], 	[CONNECTOR:9:VGA-1] set DPMS on
>[drm:i915_getparam], Unknown parameter 12
>[drm:intel_panel_get_max_backlight], max backlight PWM = 4882
>[drm:intel_panel_set_backlight], set backlight PWM = 0
>[drm:intel_prepare_page_flip], preparing flip with no unpin work?
>[drm:i915_getparam], Unknown parameter 12
>[drm:i915_getparam], Unknown parameter 12
>[drm:drm_mode_addfb], [FB:49]
>[drm:drm_mode_setcrtc], [CRTC:3]
>[drm:drm_mode_setcrtc], [CONNECTOR:9:VGA-1]
>[drm:drm_crtc_helper_set_config], 
>[drm:drm_crtc_helper_set_config], [CRTC:3] [FB:49] #connectors=1 (x y) (0 0)
>[drm:drm_crtc_helper_set_config], [CONNECTOR:9:VGA-1] to [CRTC:3]
>[drm:intel_pipe_set_base_atomic], Writing base 04335000 00000000 0 0 7680
>[drm:intel_update_fbc], 
>[drm:drm_crtc_helper_set_config], Setting connector DPMS state to on
>[drm:drm_crtc_helper_set_config], 	[CONNECTOR:9:VGA-1] set DPMS on
>[drm:i915_getparam], Unknown parameter 12
>DRHD: handling fault status reg 3
>DMAR:[DMA Read] Request device [00:02.0] fault addr fb740000 
>DMAR:[fault reason 06] PTE Read access is not set
>DRHD: handling fault status reg 2
>DMAR:[DMA Read] Request device [00:02.0] fault addr fb740000 
>DMAR:[fault reason 06] PTE Read access is not set
>DRHD: handling fault status reg 3
>DMAR:[DMA Read] Request device [00:02.0] fault addr fb743000 
>DMAR:[fault reason 06] PTE Read access is not set
>DRHD: handling fault status reg 2
>DMAR:[DMA Read] Request device [00:02.0] fault addr fb749000 
>DMAR:[fault reason 06] PTE Read access is not set
>DRHD: handling fault status reg 2
>DMAR:[DMA Read] Request device [00:02.0] fault addr fb74e000 
>DMAR:[fault reason 06] PTE Read access is not set
>DRHD: handling fault status reg 2
>DMAR:[DMA Read] Request device [00:02.0] fault addr fb743000 
>DMAR:[fault reason 06] PTE Read access is not set
>DRHD: handling fault status reg 3
>DMAR:[DMA Read] Request device [00:02.0] fault addr fb748000 
>DMAR:[fault reason 06] PTE Read access is not set
>DRHD: handling fault status reg 2
>DMAR:[DMA Read] Request device [00:02.0] fault addr fb74e000 
>DMAR:[fault reason 06] PTE Read access is not set
>DRHD: handling fault status reg 2
>DMAR:[DMA Read] Request device [00:02.0] fault addr fb743000 
>DMAR:[fault reason 06] PTE Read access is not set
>DRHD: handling fault status reg 2
>DMAR:[DMA Read] Request device [00:02.0] fault addr fb748000 
>DMAR:[fault reason 06] PTE Read access is not set
>DRHD: handling fault status reg 2
>DMAR:[DMA Read] Request device [00:02.0] fault addr fb74d000 
>DMAR:[fault reason 06] PTE Read access is not set
>DRHD: handling fault status reg 2
>DMAR:[DMA Read] Request device [00:02.0] fault addr fb743000 
>DMAR:[fault reason 06] PTE Read access is not set
>DRHD: handling fault status reg 2
>DMAR:[DMA Read] Request device [00:02.0] fault addr fb748000 
>DMAR:[fault reason 06] PTE Read access is not set
>DRHD: handling fault status reg 2
>DMAR:[DMA Read] Request device [00:02.0] fault addr fb74d000 
>DMAR:[fault reason 06] PTE Read access is not set
>DRHD: handling fault status reg 2
>DMAR:[DMA Read] Request device [00:02.0] fault addr fb743000 
>DMAR:[fault reason 06] PTE Read access is not set
>DRHD: handling fault status reg 2
>DMAR:[DMA Read] Request device [00:02.0] fault addr fb74a000 
>DMAR:[fault reason 06] PTE Read access is not set
>DRHD: handling fault status reg 2
>DMAR:[DMA Read] Request device [00:02.0] fault addr fb742000 
>DMAR:[fault reason 06] PTE Read access is not set
>DMAR:[DMA Read] Request device [00:02.0] fault addr fb743000 
>DMAR:[fault reason 06] PTE Read access is not set
>DRHD: handling fault status reg 2
>DMAR:[DMA Read] Request device [00:02.0] fault addr fb743000 
>DMAR:[fault reason 06] PTE Read access is not set
>DRHD: handling fault status reg 2
>DMAR:[DMA Read] Request device [00:02.0] fault addr fb743000 
>DMAR:[fault reason 06] PTE Read access is not set
>DRHD: handling fault status reg 2
>DMAR:[DMA Read] Request device [00:02.0] fault addr fb74a000 
>DMAR:[fault reason 06] PTE Read access is not set
>DRHD: handling fault status reg 2
>DMAR:[DMA Read] Request device [00:02.0] fault addr fb752000 
>DMAR:[fault reason 06] PTE Read access is not set
>DMAR:[DMA Read] Request device [00:02.0] fault addr fb753000 
>DMAR:[fault reason 06] PTE Read access is not set
>DMAR:[DMA Read] Request device [00:02.0] fault addr fb754000 
>DMAR:[fault reason 06] PTE Read access is not set
>DRHD: handling fault status reg 2
>DMAR:[DMA Read] Request device [00:02.0] fault addr fb75d000 
>DMAR:[fault reason 06] PTE Read access is not set
>DRHD: handling fault status reg 2
>DMAR:[DMA Read] Request device [00:02.0] fault addr fb753000 
>DMAR:[fault reason 06] PTE Read access is not set
>DRHD: handling fault status reg 2
>DMAR:[DMA Read] Request device [00:02.0] fault addr fb75a000 
>DMAR:[fault reason 06] PTE Read access is not set
>DRHD: handling fault status reg 2
>DMAR:[DMA Read] Request device [00:02.0] fault addr fb752000 
>DMAR:[fault reason 06] PTE Read access is not set
>DMAR:[DMA Read] Request device [00:02.0] fault addr fb753000 
>DMAR:[fault reason 06] PTE Read access is not set
>DRHD: handling fault status reg 2
>DMAR:[DMA Read] Request device [00:02.0] fault addr fb758000 
>DMAR:[fault reason 06] PTE Read access is not set
>DRHD: handling fault status reg 2
>DMAR:[DMA Read] Request device [00:02.0] fault addr fb750000 
>DMAR:[fault reason 06] PTE Read access is not set
>DRHD: handling fault status reg 2
>DMAR:[DMA Read] Request device [00:02.0] fault addr fb753000 
>DMAR:[fault reason 06] PTE Read access is not set
>DRHD: handling fault status reg 2
>DMAR:[DMA Read] Request device [00:02.0] fault addr fb75b000 
>DMAR:[fault reason 06] PTE Read access is not set
>DRHD: handling fault status reg 3
>DMAR:[DMA Read] Request device [00:02.0] fault addr fb753000 
>DMAR:[fault reason 06] PTE Read access is not set
>DRHD: handling fault status reg 2
>DMAR:[DMA Read] Request device [00:02.0] fault addr fb75d000 
>DMAR:[fault reason 06] PTE Read access is not set
>DRHD: handling fault status reg 2
>DMAR:[DMA Read] Request device [00:02.0] fault addr fb753000 
>DMAR:[fault reason 06] PTE Read access is not set
>DRHD: handling fault status reg 2
>DMAR:[DMA Read] Request device [00:02.0] fault addr fb75a000 
>DMAR:[fault reason 06] PTE Read access is not set
>DRHD: handling fault status reg 2
>DMAR:[DMA Read] Request device [00:02.0] fault addr fb752000 
>DMAR:[fault reason 06] PTE Read access is not set
>DRHD: handling fault status reg 2
>DMAR:[DMA Read] Request device [00:02.0] fault addr fb753000 
>DMAR:[fault reason 06] PTE Read access is not set
>DRHD: handling fault status reg 2
>DMAR:[DMA Read] Request device [00:02.0] fault addr fb759000 
>DMAR:[fault reason 06] PTE Read access is not set
>DRHD: handling fault status reg 2
>DMAR:[DMA Read] Request device [00:02.0] fault addr fb751000 
>DMAR:[fault reason 06] PTE Read access is not set
>DRHD: handling fault status reg 2
>DMAR:[DMA Read] Request device [00:02.0] fault addr fb753000 
>DMAR:[fault reason 06] PTE Read access is not set
>DRHD: handling fault status reg 2
>DMAR:[DMA Read] Request device [00:02.0] fault addr fb75a000 
>DMAR:[fault reason 06] PTE Read access is not set
>DRHD: handling fault status reg 2
>DMAR:[DMA Read] Request device [00:02.0] fault addr fb762000 
>DMAR:[fault reason 06] PTE Read access is not set
>DRHD: handling fault status reg 2
>DMAR:[DMA Read] Request device [00:02.0] fault addr fb763000 
>DMAR:[fault reason 06] PTE Read access is not set
>DRHD: handling fault status reg 2
>DMAR:[DMA Read] Request device [00:02.0] fault addr fb769000 
>DMAR:[fault reason 06] PTE Read access is not set
>DRHD: handling fault status reg 2
>DMAR:[DMA Read] Request device [00:02.0] fault addr fb760000 
>DMAR:[fault reason 06] PTE Read access is not set
>DRHD: handling fault status reg 3
>DMAR:[DMA Read] Request device [00:02.0] fault addr fb763000 
>DMAR:[fault reason 06] PTE Read access is not set
>DRHD: handling fault status reg 2
>DMAR:[DMA Read] Request device [00:02.0] fault addr fb76b000 
>DMAR:[fault reason 06] PTE Read access is not set
>DRHD: handling fault status reg 2
>DMAR:[DMA Read] Request device [00:02.0] fault addr fb762000 
>DMAR:[fault reason 06] PTE Read access is not set
>DRHD: handling fault status reg 2
>DMAR:[DMA Read] Request device [00:02.0] fault addr fb763000 
>DMAR:[fault reason 06] PTE Read access is not set
>DRHD: handling fault status reg 2
>DMAR:[DMA Read] Request device [00:02.0] fault addr fb769000 
>DMAR:[fault reason 06] PTE Read access is not set
>DRHD: handling fault status reg 2
>DMAR:[DMA Read] Request device [00:02.0] fault addr fb761000 
>DMAR:[fault reason 06] PTE Read access is not set
>DRHD: handling fault status reg 2
>DMAR:[DMA Read] Request device [00:02.0] fault addr fb763000 
>DMAR:[fault reason 06] PTE Read access is not set
>DRHD: handling fault status reg 2
>DMAR:[DMA Read] Request device [00:02.0] fault addr fb769000 
>DMAR:[fault reason 06] PTE Read access is not set
>DRHD: handling fault status reg 2
>DMAR:[DMA Read] Request device [00:02.0] fault addr fb760000 
>DMAR:[fault reason 06] PTE Read access is not set
>DRHD: handling fault status reg 2
>DMAR:[DMA Read] Request device [00:02.0] fault addr fb763000 
>DMAR:[fault reason 06] PTE Read access is not set
>DRHD: handling fault status reg 2
>DMAR:[DMA Read] Request device [00:02.0] fault addr fb769000 
>DMAR:[fault reason 06] PTE Read access is not set
>DRHD: handling fault status reg 2
>DMAR:[DMA Read] Request device [00:02.0] fault addr fb761000 
>DMAR:[fault reason 06] PTE Read access is not set
>DRHD: handling fault status reg 2
>DMAR:[DMA Read] Request device [00:02.0] fault addr fb763000 
>DMAR:[fault reason 06] PTE Read access is not set
>DRHD: handling fault status reg 3
>DMAR:[DMA Read] Request device [00:02.0] fault addr fb769000 
>DMAR:[fault reason 06] PTE Read access is not set
>DRHD: handling fault status reg 2
>DMAR:[DMA Read] Request device [00:02.0] fault addr fb763000 
>DMAR:[fault reason 06] PTE Read access is not set
>DRHD: handling fault status reg 2
>DMAR:[DMA Read] Request device [00:02.0] fault addr fb76a000 
>DMAR:[fault reason 06] PTE Read access is not set
>DRHD: handling fault status reg 2
>DMAR:[DMA Read] Request device [00:02.0] fault addr fb762000 
>DMAR:[fault reason 06] PTE Read access is not set
>DRHD: handling fault status reg 2
>DMAR:[DMA Read] Request device [00:02.0] fault addr fb763000 
>DMAR:[fault reason 06] PTE Read access is not set
>DRHD: handling fault status reg 3
>DMAR:[DMA Read] Request device [00:02.0] fault addr fb76a000 
>DMAR:[fault reason 06] PTE Read access is not set
>DRHD: handling fault status reg 2
>DMAR:[DMA Read] Request device [00:02.0] fault addr fb772000 
>DMAR:[fault reason 06] PTE Read access is not set
>DRHD: handling fault status reg 2
>DMAR:[DMA Read] Request device [00:02.0] fault addr fb773000 
>DMAR:[fault reason 06] PTE Read access is not set
>DRHD: handling fault status reg 2
>DMAR:[DMA Read] Request device [00:02.0] fault addr fb778000 
>DMAR:[fault reason 06] PTE Read access is not set
>DRHD: handling fault status reg 2
>DMAR:[DMA Read] Request device [00:02.0] fault addr fb775000 
>DMAR:[fault reason 06] PTE Read access is not set
>DRHD: handling fault status reg 2
>DMAR:[DMA Read] Request device [00:02.0] fault addr fb77a000 
>DMAR:[fault reason 06] PTE Read access is not set
>DRHD: handling fault status reg 2
>DMAR:[DMA Read] Request device [00:02.0] fault addr fb770000 
>DMAR:[fault reason 06] PTE Read access is not set
>DRHD: handling fault status reg 2
>DMAR:[DMA Read] Request device [00:02.0] fault addr fb773000 
>DMAR:[fault reason 06] PTE Read access is not set
>DRHD: handling fault status reg 2
>DMAR:[DMA Read] Request device [00:02.0] fault addr fb778000 
>DMAR:[fault reason 06] PTE Read access is not set
>DRHD: handling fault status reg 2
>DMAR:[DMA Read] Request device [00:02.0] fault addr fb77d000 
>DMAR:[fault reason 06] PTE Read access is not set
>DRHD: handling fault status reg 2
>DMAR:[DMA Read] Request device [00:02.0] fault addr fb773000 
>DMAR:[fault reason 06] PTE Read access is not set
>DRHD: handling fault status reg 2
>DMAR:[DMA Read] Request device [00:02.0] fault addr fb779000 
>DMAR:[fault reason 06] PTE Read access is not set
>DRHD: handling fault status reg 2
>DMAR:[DMA Read] Request device [00:02.0] fault addr fb77e000 
>DMAR:[fault reason 06] PTE Read access is not set
>DRHD: handling fault status reg 2
>DMAR:[DMA Read] Request device [00:02.0] fault addr fb773000 
>DMAR:[fault reason 06] PTE Read access is not set
>DRHD: handling fault status reg 2
>DMAR:[DMA Read] Request device [00:02.0] fault addr fb778000 
>DMAR:[fault reason 06] PTE Read access is not set
>DRHD: handling fault status reg 2
>DMAR:[DMA Read] Request device [00:02.0] fault addr fb77d000 
>DMAR:[fault reason 06] PTE Read access is not set
>DRHD: handling fault status reg 3
>DMAR:[DMA Read] Request device [00:02.0] fault addr fb773000 
>DMAR:[fault reason 06] PTE Read access is not set
>DRHD: handling fault status reg 2
>DMAR:[DMA Read] Request device [00:02.0] fault addr fb779000 
>DMAR:[fault reason 06] PTE Read access is not set
>DRHD: handling fault status reg 2
>DMAR:[DMA Read] Request device [00:02.0] fault addr fb77e000 
>DMAR:[fault reason 06] PTE Read access is not set
>DRHD: handling fault status reg 2
>DMAR:[DMA Read] Request device [00:02.0] fault addr fb773000 
>DMAR:[fault reason 06] PTE Read access is not set
>DRHD: handling fault status reg 2
>DMAR:[DMA Read] Request device [00:02.0] fault addr fb778000 
>DMAR:[fault reason 06] PTE Read access is not set
>DRHD: handling fault status reg 2
>DMAR:[DMA Read] Request device [00:02.0] fault addr fb77e000 
>DMAR:[fault reason 06] PTE Read access is not set
>DRHD: handling fault status reg 2
>DMAR:[DMA Read] Request device [00:02.0] fault addr fb773000 
>DMAR:[fault reason 06] PTE Read access is not set
>DRHD: handling fault status reg 2
>DMAR:[DMA Read] Request device [00:02.0] fault addr fb77a000 
>DMAR:[fault reason 06] PTE Read access is not set
>[drm:intel_prepare_page_flip], preparing flip with no unpin work?
>[drm:blt_ring_add_request], blt ring 5699
>[drm:i915_driver_open], 
>[drm:i915_getparam], Unknown parameter 12
>[drm:i915_driver_open], 
>[drm:i915_getparam], Unknown parameter 12
>[drm:i915_driver_open], 
>[drm:blt_ring_add_request], blt ring 5821
>[drm:blt_ring_add_request], blt ring 5824
>[drm:blt_ring_add_request], blt ring 5825
>[drm:blt_ring_add_request], blt ring 5830
>[drm:i915_getparam], Unknown parameter 12
>[drm:blt_ring_add_request], blt ring 5831
>[drm:blt_ring_add_request], blt ring 5840
>[drm:blt_ring_add_request], blt ring 5849
>[drm:blt_ring_add_request], blt ring 5853
>[drm:blt_ring_add_request], blt ring 5859
>[drm:blt_ring_add_request], blt ring 5865
>[drm:blt_ring_add_request], blt ring 5871
>[drm:blt_ring_add_request], blt ring 5877
>[drm:blt_ring_add_request], blt ring 5883
>[drm:blt_ring_add_request], blt ring 5889
>[drm:blt_ring_add_request], blt ring 5895
>[drm:blt_ring_add_request], blt ring 5901
>[drm:blt_ring_add_request], blt ring 5907
>[drm:blt_ring_add_request], blt ring 5913
>[drm:blt_ring_add_request], blt ring 5919
>[drm:blt_ring_add_request], blt ring 5925
>[drm:blt_ring_add_request], blt ring 5931
>[drm:blt_ring_add_request], blt ring 5937
>[drm:blt_ring_add_request], blt ring 5943
>[drm:blt_ring_add_request], blt ring 5949
>[drm:blt_ring_add_request], blt ring 5955
>[drm:blt_ring_add_request], blt ring 5961
>[drm:blt_ring_add_request], blt ring 5967
>[drm:blt_ring_add_request], blt ring 5973
>[drm:blt_ring_add_request], blt ring 5979
>[drm:blt_ring_add_request], blt ring 5985
>[drm:blt_ring_add_request], blt ring 5991
>[drm:blt_ring_add_request], blt ring 5997
>[drm:blt_ring_add_request], blt ring 6003
>[drm:blt_ring_add_request], blt ring 6009
>[drm:blt_ring_add_request], blt ring 6015
>[drm:blt_ring_add_request], blt ring 6021
>[drm:blt_ring_add_request], blt ring 6027
>[drm:blt_ring_add_request], blt ring 6033
>[drm:blt_ring_add_request], blt ring 6039
>[drm:blt_ring_add_request], blt ring 6045
>[drm:blt_ring_add_request], blt ring 6051
>[drm:blt_ring_add_request], blt ring 6057
>[drm:blt_ring_add_request], blt ring 6063
>[drm:blt_ring_add_request], blt ring 6069
>[drm:blt_ring_add_request], blt ring 6075
>[drm:blt_ring_add_request], blt ring 6081
>[drm:blt_ring_add_request], blt ring 6087
>[drm:blt_ring_add_request], blt ring 6093
>[drm:blt_ring_add_request], blt ring 6099
>[drm:blt_ring_add_request], blt ring 6105
>[drm:blt_ring_add_request], blt ring 6111
>[drm:blt_ring_add_request], blt ring 6117
>[drm:blt_ring_add_request], blt ring 6123
>[drm:blt_ring_add_request], blt ring 6129
>[drm:blt_ring_add_request], blt ring 6135
>[drm:blt_ring_add_request], blt ring 6141
>[drm:blt_ring_add_request], blt ring 6147
>[drm:blt_ring_add_request], blt ring 6153
>[drm:blt_ring_add_request], blt ring 6159
>[drm:blt_ring_add_request], blt ring 6165
>[drm:blt_ring_add_request], blt ring 6171
>[drm:blt_ring_add_request], blt ring 6177
>[drm:blt_ring_add_request], blt ring 6183
>[drm:blt_ring_add_request], blt ring 6189
>[drm:blt_ring_add_request], blt ring 6195
>[drm:blt_ring_add_request], blt ring 6201
>[drm:blt_ring_add_request], blt ring 6207
>[drm:blt_ring_add_request], blt ring 6213
>[drm:blt_ring_add_request], blt ring 6219
>[drm:blt_ring_add_request], blt ring 6225
>[drm:blt_ring_add_request], blt ring 6231
>[drm:blt_ring_add_request], blt ring 6237
>[drm:blt_ring_add_request], blt ring 6243
>[drm:blt_ring_add_request], blt ring 6249
>[drm:blt_ring_add_request], blt ring 6255
>[drm:blt_ring_add_request], blt ring 6261
>[drm:blt_ring_add_request], blt ring 6267
>[drm:blt_ring_add_request], blt ring 6273
>[drm:blt_ring_add_request], blt ring 6279
>[drm:blt_ring_add_request], blt ring 6285
>[drm:blt_ring_add_request], blt ring 6291
>[drm:blt_ring_add_request], blt ring 6297
>[drm:blt_ring_add_request], blt ring 6303
>[drm:blt_ring_add_request], blt ring 6309
>[drm:blt_ring_add_request], blt ring 6315
>[drm:blt_ring_add_request], blt ring 6321
>[drm:blt_ring_add_request], blt ring 6327
>[drm:blt_ring_add_request], blt ring 6333
>[drm:blt_ring_add_request], blt ring 6339
>[drm:blt_ring_add_request], blt ring 6345
>[drm:blt_ring_add_request], blt ring 6351
>[drm:blt_ring_add_request], blt ring 6357
>[drm:blt_ring_add_request], blt ring 6363
>[drm:blt_ring_add_request], blt ring 6369
>[drm:blt_ring_add_request], blt ring 6375
>[drm:blt_ring_add_request], blt ring 6381
>[drm:blt_ring_add_request], blt ring 6387
>[drm:blt_ring_add_request], blt ring 6393
>[drm:blt_ring_add_request], blt ring 6399
>[drm:blt_ring_add_request], blt ring 6405
>[drm:blt_ring_add_request], blt ring 6411
>[drm:blt_ring_add_request], blt ring 6417
>[drm:blt_ring_add_request], blt ring 6423
>[drm:blt_ring_add_request], blt ring 6429
>[drm:blt_ring_add_request], blt ring 6435
>[drm:blt_ring_add_request], blt ring 6441
>[drm:blt_ring_add_request], blt ring 6447
>[drm:blt_ring_add_request], blt ring 6453
>[drm:blt_ring_add_request], blt ring 6459
>[drm:blt_ring_add_request], blt ring 6465
>[drm:blt_ring_add_request], blt ring 6471
>[drm:blt_ring_add_request], blt ring 6477
>[drm:blt_ring_add_request], blt ring 6483
>[drm:blt_ring_add_request], blt ring 6489
>[drm:blt_ring_add_request], blt ring 6495
>[drm:blt_ring_add_request], blt ring 6501
>[drm:blt_ring_add_request], blt ring 6507
>[drm:blt_ring_add_request], blt ring 6513
>[drm:blt_ring_add_request], blt ring 6519
>[drm:blt_ring_add_request], blt ring 6525
>[drm:blt_ring_add_request], blt ring 6531
>[drm:blt_ring_add_request], blt ring 6537
>[drm:blt_ring_add_request], blt ring 6543
>[drm:blt_ring_add_request], blt ring 6549
>[drm:blt_ring_add_request], blt ring 6555
>[drm:blt_ring_add_request], blt ring 6561
>[drm:blt_ring_add_request], blt ring 6567
>[drm:blt_ring_add_request], blt ring 6573
>[drm:blt_ring_add_request], blt ring 6579
>[drm:blt_ring_add_request], blt ring 6585
>[drm:blt_ring_add_request], blt ring 6591
>[drm:blt_ring_add_request], blt ring 6597
>[drm:blt_ring_add_request], blt ring 6603
>[drm:blt_ring_add_request], blt ring 6609
>[drm:blt_ring_add_request], blt ring 6615
>[drm:blt_ring_add_request], blt ring 6621
>[drm:blt_ring_add_request], blt ring 6627
>[drm:blt_ring_add_request], blt ring 6633
>[drm:blt_ring_add_request], blt ring 6639
>[drm:blt_ring_add_request], blt ring 6645
>[drm:blt_ring_add_request], blt ring 6651
>[drm:blt_ring_add_request], blt ring 6657
>[drm:blt_ring_add_request], blt ring 6663
>[drm:blt_ring_add_request], blt ring 6669
>[drm:blt_ring_add_request], blt ring 6675
>[drm:blt_ring_add_request], blt ring 6681
>[drm:blt_ring_add_request], blt ring 6687
>[drm:blt_ring_add_request], blt ring 6693
>[drm:blt_ring_add_request], blt ring 6699
>[drm:blt_ring_add_request], blt ring 6705
>[drm:blt_ring_add_request], blt ring 6711
>[drm:blt_ring_add_request], blt ring 6717
>[drm:blt_ring_add_request], blt ring 6723
>[drm:blt_ring_add_request], blt ring 6729
>[drm:blt_ring_add_request], blt ring 6735
>[drm:blt_ring_add_request], blt ring 6741
>[drm:blt_ring_add_request], blt ring 6747
>[drm:blt_ring_add_request], blt ring 6753
>[drm:blt_ring_add_request], blt ring 6759
>[drm:blt_ring_add_request], blt ring 6765
>[drm:blt_ring_add_request], blt ring 6771
>[drm:blt_ring_add_request], blt ring 6777
>[drm:blt_ring_add_request], blt ring 6783
>[drm:blt_ring_add_request], blt ring 6789
>[drm:blt_ring_add_request], blt ring 6795
>[drm:blt_ring_add_request], blt ring 6801
>[drm:blt_ring_add_request], blt ring 6807
>[drm:blt_ring_add_request], blt ring 6813
>[drm:blt_ring_add_request], blt ring 6819
>[drm:blt_ring_add_request], blt ring 6825
>[drm:blt_ring_add_request], blt ring 6831
>[drm:blt_ring_add_request], blt ring 6837
>[drm:blt_ring_add_request], blt ring 6843
>[drm:blt_ring_add_request], blt ring 6849
>[drm:blt_ring_add_request], blt ring 6855
>[drm:blt_ring_add_request], blt ring 6861
>[drm:blt_ring_add_request], blt ring 6867
>[drm:blt_ring_add_request], blt ring 6873
>[drm:blt_ring_add_request], blt ring 6879
>[drm:blt_ring_add_request], blt ring 6885
>[drm:blt_ring_add_request], blt ring 6891
>[drm:blt_ring_add_request], blt ring 6897
>[drm:blt_ring_add_request], blt ring 6903
>[drm:blt_ring_add_request], blt ring 6909
>[drm:blt_ring_add_request], blt ring 6915
>[drm:blt_ring_add_request], blt ring 6921
>[drm:blt_ring_add_request], blt ring 6927
>[drm:blt_ring_add_request], blt ring 6933
>[drm:blt_ring_add_request], blt ring 6939
>[drm:blt_ring_add_request], blt ring 6945
>[drm:blt_ring_add_request], blt ring 6951
>[drm:blt_ring_add_request], blt ring 6957
>[drm:blt_ring_add_request], blt ring 6963
>[drm:blt_ring_add_request], blt ring 6969
>[drm:blt_ring_add_request], blt ring 6975
>[drm:blt_ring_add_request], blt ring 6981
>[drm:blt_ring_add_request], blt ring 6987
>[drm:blt_ring_add_request], blt ring 6993
>[drm:blt_ring_add_request], blt ring 6999
>[drm:blt_ring_add_request], blt ring 7005
>[drm:blt_ring_add_request], blt ring 7011
>[drm:blt_ring_add_request], blt ring 7017
>[drm:blt_ring_add_request], blt ring 7023
>[drm:blt_ring_add_request], blt ring 7029
>[drm:blt_ring_add_request], blt ring 7035
>[drm:blt_ring_add_request], blt ring 7041
>[drm:blt_ring_add_request], blt ring 7047
>[drm:blt_ring_add_request], blt ring 7053
>[drm:blt_ring_add_request], blt ring 7059
>[drm:blt_ring_add_request], blt ring 7065
>[drm:blt_ring_add_request], blt ring 7071
>[drm:blt_ring_add_request], blt ring 7077
>[drm:blt_ring_add_request], blt ring 7083
>[drm:blt_ring_add_request], blt ring 7089
>[drm:blt_ring_add_request], blt ring 7095
>[drm:blt_ring_add_request], blt ring 7101
>[drm:blt_ring_add_request], blt ring 7107
>[drm:blt_ring_add_request], blt ring 7113
>[drm:blt_ring_add_request], blt ring 7119
>[drm:blt_ring_add_request], blt ring 7125
>[drm:blt_ring_add_request], blt ring 7131
>[drm:blt_ring_add_request], blt ring 7137
>[drm:blt_ring_add_request], blt ring 7143
>[drm:blt_ring_add_request], blt ring 7149
>[drm:blt_ring_add_request], blt ring 7155
>[drm:blt_ring_add_request], blt ring 7161
>[drm:blt_ring_add_request], blt ring 7167
>[drm:blt_ring_add_request], blt ring 7173
>[drm:blt_ring_add_request], blt ring 7179
>[drm:blt_ring_add_request], blt ring 7185
>[drm:blt_ring_add_request], blt ring 7191
>[drm:blt_ring_add_request], blt ring 7197
>[drm:blt_ring_add_request], blt ring 7203
>[drm:blt_ring_add_request], blt ring 7209
>[drm:blt_ring_add_request], blt ring 7215
>[drm:blt_ring_add_request], blt ring 7221
>[drm:blt_ring_add_request], blt ring 7227
>[drm:blt_ring_add_request], blt ring 7233
>[drm:blt_ring_add_request], blt ring 7239
>[drm:blt_ring_add_request], blt ring 7245
>[drm:blt_ring_add_request], blt ring 7251
>[drm:blt_ring_add_request], blt ring 7257
>[drm:blt_ring_add_request], blt ring 7263
>[drm:blt_ring_add_request], blt ring 7269
>[drm:blt_ring_add_request], blt ring 7275
>[drm:blt_ring_add_request], blt ring 7281
>[drm:blt_ring_add_request], blt ring 7287
>[drm:blt_ring_add_request], blt ring 7293
>[drm:blt_ring_add_request], blt ring 7299
>[drm:blt_ring_add_request], blt ring 7305
>[drm:blt_ring_add_request], blt ring 7311
>[drm:blt_ring_add_request], blt ring 7317
>[drm:blt_ring_add_request], blt ring 7323
>[drm:blt_ring_add_request], blt ring 7329
>[drm:blt_ring_add_request], blt ring 7335
>[drm:blt_ring_add_request], blt ring 7341
>[drm:blt_ring_add_request], blt ring 7347
>[drm:blt_ring_add_request], blt ring 7353
>[drm:blt_ring_add_request], blt ring 7359
>[drm:blt_ring_add_request], blt ring 7365
>[drm:blt_ring_add_request], blt ring 7371
>[drm:blt_ring_add_request], blt ring 7377
>[drm:blt_ring_add_request], blt ring 7383
>[drm:blt_ring_add_request], blt ring 7389
>[drm:blt_ring_add_request], blt ring 7395
>[drm:blt_ring_add_request], blt ring 7401
>[drm:blt_ring_add_request], blt ring 7407
>[drm:blt_ring_add_request], blt ring 7413
>[drm:blt_ring_add_request], blt ring 7419
>[drm:blt_ring_add_request], blt ring 7425
>[drm:blt_ring_add_request], blt ring 7431
>[drm:blt_ring_add_request], blt ring 7437
>[drm:blt_ring_add_request], blt ring 7443
>[drm:blt_ring_add_request], blt ring 7449
>[drm:blt_ring_add_request], blt ring 7455
>[drm:blt_ring_add_request], blt ring 7461
>[drm:blt_ring_add_request], blt ring 7467
>[drm:blt_ring_add_request], blt ring 7473
>[drm:blt_ring_add_request], blt ring 7479
>[drm:blt_ring_add_request], blt ring 7485
>[drm:blt_ring_add_request], blt ring 7491
>[drm:blt_ring_add_request], blt ring 7497
>[drm:blt_ring_add_request], blt ring 7503
>[drm:blt_ring_add_request], blt ring 7509
>[drm:blt_ring_add_request], blt ring 7515
>[drm:blt_ring_add_request], blt ring 7521
>[drm:blt_ring_add_request], blt ring 7527
>[drm:blt_ring_add_request], blt ring 7533
>[drm:blt_ring_add_request], blt ring 7539
>[drm:blt_ring_add_request], blt ring 7545
>[drm:blt_ring_add_request], blt ring 7551
>[drm:blt_ring_add_request], blt ring 7557
>[drm:blt_ring_add_request], blt ring 7563
>[drm:blt_ring_add_request], blt ring 7569
>[drm:blt_ring_add_request], blt ring 7575
>[drm:blt_ring_add_request], blt ring 7581
>[drm:blt_ring_add_request], blt ring 7587
>[drm:blt_ring_add_request], blt ring 7593
>[drm:blt_ring_add_request], blt ring 7599
>[drm:blt_ring_add_request], blt ring 7605
>[drm:blt_ring_add_request], blt ring 7611
>[drm:blt_ring_add_request], blt ring 7617
>[drm:blt_ring_add_request], blt ring 7623
>[drm:blt_ring_add_request], blt ring 7629
>[drm:blt_ring_add_request], blt ring 7635
>[drm:blt_ring_add_request], blt ring 7641
>[drm:blt_ring_add_request], blt ring 7647
>[drm:blt_ring_add_request], blt ring 7653
>[drm:blt_ring_add_request], blt ring 7659
>[drm:blt_ring_add_request], blt ring 7665
>[drm:blt_ring_add_request], blt ring 7671
>[drm:blt_ring_add_request], blt ring 7677
>[drm:blt_ring_add_request], blt ring 7683
>[drm:blt_ring_add_request], blt ring 7689
>[drm:blt_ring_add_request], blt ring 7695
>[drm:blt_ring_add_request], blt ring 7701
>[drm:blt_ring_add_request], blt ring 7707
>[drm:blt_ring_add_request], blt ring 7713
>[drm:blt_ring_add_request], blt ring 7719
>[drm:blt_ring_add_request], blt ring 7725
>[drm:blt_ring_add_request], blt ring 7731
>[drm:blt_ring_add_request], blt ring 7737
>[drm:blt_ring_add_request], blt ring 7743
>[drm:blt_ring_add_request], blt ring 7749
>[drm:blt_ring_add_request], blt ring 7755
>[drm:blt_ring_add_request], blt ring 7761
>[drm:blt_ring_add_request], blt ring 7767
>[drm:blt_ring_add_request], blt ring 7773
>[drm:blt_ring_add_request], blt ring 7779
>[drm:blt_ring_add_request], blt ring 7785
>[drm:blt_ring_add_request], blt ring 7791
>[drm:blt_ring_add_request], blt ring 7797
>[drm:blt_ring_add_request], blt ring 7803
>[drm:blt_ring_add_request], blt ring 7809
>[drm:blt_ring_add_request], blt ring 7815
>[drm:blt_ring_add_request], blt ring 7821
>[drm:blt_ring_add_request], blt ring 7827
>[drm:blt_ring_add_request], blt ring 7833
>[drm:blt_ring_add_request], blt ring 7839
>[drm:blt_ring_add_request], blt ring 7845
>[drm:blt_ring_add_request], blt ring 7851
>[drm:blt_ring_add_request], blt ring 7857
>[drm:blt_ring_add_request], blt ring 7863
>[drm:blt_ring_add_request], blt ring 7869
>[drm:blt_ring_add_request], blt ring 7875
>[drm:blt_ring_add_request], blt ring 7881
>[drm:blt_ring_add_request], blt ring 7887
>[drm:blt_ring_add_request], blt ring 7893
>[drm:blt_ring_add_request], blt ring 7899
>[drm:blt_ring_add_request], blt ring 7905
>[drm:blt_ring_add_request], blt ring 7911
>[drm:blt_ring_add_request], blt ring 7917
>[drm:blt_ring_add_request], blt ring 7923
>[drm:blt_ring_add_request], blt ring 7929
>[drm:blt_ring_add_request], blt ring 7935
>[drm:blt_ring_add_request], blt ring 7941
>[drm:blt_ring_add_request], blt ring 7947
>[drm:blt_ring_add_request], blt ring 7953
>[drm:blt_ring_add_request], blt ring 7959
>[drm:blt_ring_add_request], blt ring 7965
>[drm:blt_ring_add_request], blt ring 7971
>[drm:blt_ring_add_request], blt ring 7977
>[drm:blt_ring_add_request], blt ring 7983
>[drm:blt_ring_add_request], blt ring 7989
>[drm:blt_ring_add_request], blt ring 7995
>[drm:blt_ring_add_request], blt ring 8001
>[drm:blt_ring_add_request], blt ring 8007
>[drm:blt_ring_add_request], blt ring 8013
>[drm:blt_ring_add_request], blt ring 8019
>[drm:blt_ring_add_request], blt ring 8025
>[drm:blt_ring_add_request], blt ring 8031
>[drm:blt_ring_add_request], blt ring 8037
>[drm:blt_ring_add_request], blt ring 8043
>[drm:blt_ring_add_request], blt ring 8049
>[drm:blt_ring_add_request], blt ring 8055
>[drm:blt_ring_add_request], blt ring 8061
>[drm:blt_ring_add_request], blt ring 8067
>[drm:blt_ring_add_request], blt ring 8073
>[drm:blt_ring_add_request], blt ring 8079
>[drm:blt_ring_add_request], blt ring 8085
>[drm:blt_ring_add_request], blt ring 8091
>[drm:blt_ring_add_request], blt ring 8097
>[drm:blt_ring_add_request], blt ring 8103
>[drm:blt_ring_add_request], blt ring 8109
>[drm:blt_ring_add_request], blt ring 8115
>[drm:blt_ring_add_request], blt ring 8121
>[drm:blt_ring_add_request], blt ring 8127
>[drm:blt_ring_add_request], blt ring 8133
>[drm:blt_ring_add_request], blt ring 8139
>[drm:blt_ring_add_request], blt ring 8145
>[drm:blt_ring_add_request], blt ring 8151
>[drm:blt_ring_add_request], blt ring 8157
>[drm:blt_ring_add_request], blt ring 8163
>[drm:blt_ring_add_request], blt ring 8169
>[drm:blt_ring_add_request], blt ring 8175
>[drm:blt_ring_add_request], blt ring 8181
>[drm:blt_ring_add_request], blt ring 8187
>[drm:blt_ring_add_request], blt ring 8193
>[drm:blt_ring_add_request], blt ring 8199
>[drm:blt_ring_add_request], blt ring 8205
>[drm:blt_ring_add_request], blt ring 8211
>[drm:blt_ring_add_request], blt ring 8217
>[drm:blt_ring_add_request], blt ring 8223
>[drm:blt_ring_add_request], blt ring 8229
>[drm:blt_ring_add_request], blt ring 8235
>[drm:blt_ring_add_request], blt ring 8241
>[drm:blt_ring_add_request], blt ring 8247
>[drm:blt_ring_add_request], blt ring 8253
>[drm:blt_ring_add_request], blt ring 8259
>[drm:blt_ring_add_request], blt ring 8265
>[drm:blt_ring_add_request], blt ring 8271
>[drm:blt_ring_add_request], blt ring 8277
>[drm:blt_ring_add_request], blt ring 8283
>[drm:blt_ring_add_request], blt ring 8289
>[drm:blt_ring_add_request], blt ring 8295
>[drm:blt_ring_add_request], blt ring 8301
>[drm:blt_ring_add_request], blt ring 8307
>[drm:blt_ring_add_request], blt ring 8313
>[drm:blt_ring_add_request], blt ring 8319
>[drm:blt_ring_add_request], blt ring 8325
>[drm:blt_ring_add_request], blt ring 8331
>[drm:blt_ring_add_request], blt ring 8337
>[drm:blt_ring_add_request], blt ring 8343
>[drm:blt_ring_add_request], blt ring 8349
>[drm:blt_ring_add_request], blt ring 8355
>[drm:blt_ring_add_request], blt ring 8361
>[drm:blt_ring_add_request], blt ring 8367
>[drm:blt_ring_add_request], blt ring 8373
>[drm:blt_ring_add_request], blt ring 8379
>[drm:blt_ring_add_request], blt ring 8385
>[drm:blt_ring_add_request], blt ring 8391
>[drm:blt_ring_add_request], blt ring 8397
>[drm:blt_ring_add_request], blt ring 8403
>[drm:blt_ring_add_request], blt ring 8409
>[drm:blt_ring_add_request], blt ring 8415
>[drm:blt_ring_add_request], blt ring 8421
>[drm:blt_ring_add_request], blt ring 8427
>[drm:blt_ring_add_request], blt ring 8433
>[drm:blt_ring_add_request], blt ring 8439
>[drm:blt_ring_add_request], blt ring 8445
>[drm:blt_ring_add_request], blt ring 8451
>[drm:blt_ring_add_request], blt ring 8457
>[drm:blt_ring_add_request], blt ring 8463
>[drm:blt_ring_add_request], blt ring 8469
>[drm:blt_ring_add_request], blt ring 8475
>[drm:blt_ring_add_request], blt ring 8481
>[drm:blt_ring_add_request], blt ring 8487
>[drm:blt_ring_add_request], blt ring 8493
>[drm:blt_ring_add_request], blt ring 8499
>[drm:blt_ring_add_request], blt ring 8505
>[drm:blt_ring_add_request], blt ring 8511
>[drm:blt_ring_add_request], blt ring 8517
>[drm:blt_ring_add_request], blt ring 8523
>[drm:blt_ring_add_request], blt ring 8529
>[drm:blt_ring_add_request], blt ring 8535
>[drm:blt_ring_add_request], blt ring 8541
>[drm:blt_ring_add_request], blt ring 8547
>[drm:blt_ring_add_request], blt ring 8553
>[drm:blt_ring_add_request], blt ring 8559
>[drm:blt_ring_add_request], blt ring 8565
>[drm:blt_ring_add_request], blt ring 8571
>[drm:blt_ring_add_request], blt ring 8577
>[drm:blt_ring_add_request], blt ring 8583
>[drm:blt_ring_add_request], blt ring 8589
>[drm:blt_ring_add_request], blt ring 8595
>[drm:blt_ring_add_request], blt ring 8601
>[drm:blt_ring_add_request], blt ring 8607
>[drm:blt_ring_add_request], blt ring 8613
>[drm:blt_ring_add_request], blt ring 8619
>[drm:blt_ring_add_request], blt ring 8625
>[drm:blt_ring_add_request], blt ring 8631
>[drm:blt_ring_add_request], blt ring 8637
>[drm:blt_ring_add_request], blt ring 8643
>[drm:blt_ring_add_request], blt ring 8649
>[drm:blt_ring_add_request], blt ring 8655
>[drm:blt_ring_add_request], blt ring 8661
>[drm:blt_ring_add_request], blt ring 8667
>[drm:blt_ring_add_request], blt ring 8673
>[drm:blt_ring_add_request], blt ring 8679
>[drm:blt_ring_add_request], blt ring 8685
>[drm:blt_ring_add_request], blt ring 8691
>[drm:blt_ring_add_request], blt ring 8697
>[drm:blt_ring_add_request], blt ring 8703
>[drm:blt_ring_add_request], blt ring 8709
>[drm:blt_ring_add_request], blt ring 8715
>[drm:blt_ring_add_request], blt ring 8721
>[drm:blt_ring_add_request], blt ring 8727
>[drm:blt_ring_add_request], blt ring 8733
>[drm:blt_ring_add_request], blt ring 8739
>[drm:blt_ring_add_request], blt ring 8745
>[drm:blt_ring_add_request], blt ring 8751
>[drm:blt_ring_add_request], blt ring 8757
>[drm:blt_ring_add_request], blt ring 8763
>[drm:blt_ring_add_request], blt ring 8769
>[drm:blt_ring_add_request], blt ring 8775
>[drm:blt_ring_add_request], blt ring 8781
>[drm:blt_ring_add_request], blt ring 8787
>[drm:blt_ring_add_request], blt ring 8793
>[drm:blt_ring_add_request], blt ring 8799
>[drm:blt_ring_add_request], blt ring 8805
>[drm:blt_ring_add_request], blt ring 8811
>[drm:blt_ring_add_request], blt ring 8817
>[drm:blt_ring_add_request], blt ring 8823
>[drm:blt_ring_add_request], blt ring 8829
>[drm:blt_ring_add_request], blt ring 8835
>[drm:blt_ring_add_request], blt ring 8841
>[drm:blt_ring_add_request], blt ring 8847
>[drm:blt_ring_add_request], blt ring 8853
>[drm:blt_ring_add_request], blt ring 8859
>[drm:blt_ring_add_request], blt ring 8865
>[drm:blt_ring_add_request], blt ring 8871
>[drm:blt_ring_add_request], blt ring 8877
>[drm:blt_ring_add_request], blt ring 8883
>[drm:blt_ring_add_request], blt ring 8889
>[drm:blt_ring_add_request], blt ring 8895
>[drm:blt_ring_add_request], blt ring 8901
>[drm:blt_ring_add_request], blt ring 8907
>[drm:blt_ring_add_request], blt ring 8913
>[drm:blt_ring_add_request], blt ring 8919
>[drm:blt_ring_add_request], blt ring 8925
>[drm:blt_ring_add_request], blt ring 8931
>[drm:blt_ring_add_request], blt ring 8937
>[drm:blt_ring_add_request], blt ring 8943
>[drm:blt_ring_add_request], blt ring 8949
>[drm:blt_ring_add_request], blt ring 8955
>[drm:blt_ring_add_request], blt ring 8961
>[drm:blt_ring_add_request], blt ring 8967
>[drm:blt_ring_add_request], blt ring 8973
>[drm:blt_ring_add_request], blt ring 8979
>[drm:blt_ring_add_request], blt ring 8985
>[drm:blt_ring_add_request], blt ring 8991
>[drm:blt_ring_add_request], blt ring 8997
>[drm:blt_ring_add_request], blt ring 9003
>[drm:blt_ring_add_request], blt ring 9009
>[drm:blt_ring_add_request], blt ring 9015
>[drm:blt_ring_add_request], blt ring 9021
>[drm:blt_ring_add_request], blt ring 9027
>[drm:blt_ring_add_request], blt ring 9033
>[drm:blt_ring_add_request], blt ring 9039
>[drm:blt_ring_add_request], blt ring 9045
>[drm:blt_ring_add_request], blt ring 9051
>[drm:blt_ring_add_request], blt ring 9057
>[drm:blt_ring_add_request], blt ring 9063
>[drm:blt_ring_add_request], blt ring 9069
>[drm:intel_ironlake_crt_detect_hotplug], ironlake hotplug adpa=0x83f40010, result 1
>[drm:intel_crt_detect], CRT detected via hotplug
>[drm:output_poll_execute], connector status updated to 1
>[drm:output_poll_execute], connector status updated to 2
>[drm:output_poll_execute], connector status updated to 2
>[drm:intel_dp_aux_ch], dp_aux_ch timeout status 0x5143003e
>[drm:ironlake_dp_detect], DPCD: 0000
>[drm:output_poll_execute], connector status updated to 2
>[drm:intel_dp_aux_ch], dp_aux_ch timeout status 0x5143003e
>[drm:ironlake_dp_detect], DPCD: 0000
>[drm:output_poll_execute], connector status updated to 2
>[drm:blt_ring_add_request], blt ring 9075
>[drm:blt_ring_add_request], blt ring 9081
>[drm:blt_ring_add_request], blt ring 9087
>[drm:blt_ring_add_request], blt ring 9093
>[drm:blt_ring_add_request], blt ring 9099
>[drm:blt_ring_add_request], blt ring 9105
>[drm:blt_ring_add_request], blt ring 9111
>[drm:blt_ring_add_request], blt ring 9117
>[drm:blt_ring_add_request], blt ring 9123
>[drm:blt_ring_add_request], blt ring 9129
>[drm:blt_ring_add_request], blt ring 9135
>[drm:blt_ring_add_request], blt ring 9141
>[drm:blt_ring_add_request], blt ring 9147
>[drm:blt_ring_add_request], blt ring 9153
>[drm:blt_ring_add_request], blt ring 9159
>[drm:blt_ring_add_request], blt ring 9165
>[drm:blt_ring_add_request], blt ring 9171
>[drm:blt_ring_add_request], blt ring 9177
>[drm:blt_ring_add_request], blt ring 9183
>[drm:blt_ring_add_request], blt ring 9189
>[drm:blt_ring_add_request], blt ring 9195
>[drm:blt_ring_add_request], blt ring 9201
>[drm:blt_ring_add_request], blt ring 9207
>[drm:blt_ring_add_request], blt ring 9213
>[drm:blt_ring_add_request], blt ring 9219
>[drm:blt_ring_add_request], blt ring 9225
>[drm:blt_ring_add_request], blt ring 9231
>[drm:blt_ring_add_request], blt ring 9237
>[drm:blt_ring_add_request], blt ring 9243
>[drm:blt_ring_add_request], blt ring 9249
>[drm:blt_ring_add_request], blt ring 9255
>[drm:blt_ring_add_request], blt ring 9261
>[drm:blt_ring_add_request], blt ring 9267
>[drm:blt_ring_add_request], blt ring 9273
>[drm:blt_ring_add_request], blt ring 9279
>[drm:blt_ring_add_request], blt ring 9285
>[drm:blt_ring_add_request], blt ring 9291
>[drm:blt_ring_add_request], blt ring 9297
>[drm:blt_ring_add_request], blt ring 9303
>[drm:blt_ring_add_request], blt ring 9309
>[drm:blt_ring_add_request], blt ring 9315
>[drm:blt_ring_add_request], blt ring 9321
>[drm:blt_ring_add_request], blt ring 9327
>[drm:blt_ring_add_request], blt ring 9333
>[drm:blt_ring_add_request], blt ring 9339
>[drm:blt_ring_add_request], blt ring 9345
>[drm:blt_ring_add_request], blt ring 9351
>[drm:blt_ring_add_request], blt ring 9357
>[drm:blt_ring_add_request], blt ring 9363
>[drm:blt_ring_add_request], blt ring 9369
>[drm:blt_ring_add_request], blt ring 9375
>[drm:blt_ring_add_request], blt ring 9381
>[drm:blt_ring_add_request], blt ring 9387
>[drm:blt_ring_add_request], blt ring 9393
>[drm:blt_ring_add_request], blt ring 9399
>[drm:blt_ring_add_request], blt ring 9405
>[drm:blt_ring_add_request], blt ring 9411
>[drm:blt_ring_add_request], blt ring 9417
>[drm:blt_ring_add_request], blt ring 9423
>[drm:blt_ring_add_request], blt ring 9429
>[drm:blt_ring_add_request], blt ring 9435
>[drm:blt_ring_add_request], blt ring 9441
>[drm:blt_ring_add_request], blt ring 9447
>[drm:blt_ring_add_request], blt ring 9453
>[drm:blt_ring_add_request], blt ring 9459
>[drm:blt_ring_add_request], blt ring 9465
>[drm:blt_ring_add_request], blt ring 9471
>[drm:blt_ring_add_request], blt ring 9477
>[drm:blt_ring_add_request], blt ring 9483
>[drm:blt_ring_add_request], blt ring 9489
>[drm:blt_ring_add_request], blt ring 9495
>[drm:blt_ring_add_request], blt ring 9501
>[drm:blt_ring_add_request], blt ring 9507
>[drm:blt_ring_add_request], blt ring 9513
>[drm:blt_ring_add_request], blt ring 9519
>[drm:blt_ring_add_request], blt ring 9525
>[drm:blt_ring_add_request], blt ring 9531
>[drm:blt_ring_add_request], blt ring 9537
>[drm:blt_ring_add_request], blt ring 9543
>[drm:blt_ring_add_request], blt ring 9549
>[drm:blt_ring_add_request], blt ring 9555
>[drm:blt_ring_add_request], blt ring 9561
>[drm:blt_ring_add_request], blt ring 9567
>[drm:blt_ring_add_request], blt ring 9573
>[drm:blt_ring_add_request], blt ring 9579
>[drm:blt_ring_add_request], blt ring 9585
>[drm:blt_ring_add_request], blt ring 9591
>[drm:blt_ring_add_request], blt ring 9597
>[drm:blt_ring_add_request], blt ring 9603
>[drm:blt_ring_add_request], blt ring 9609
>[drm:blt_ring_add_request], blt ring 9615
>[drm:blt_ring_add_request], blt ring 9621
>[drm:blt_ring_add_request], blt ring 9627
>[drm:blt_ring_add_request], blt ring 9633
>[drm:blt_ring_add_request], blt ring 9639
>[drm:blt_ring_add_request], blt ring 9645
>[drm:blt_ring_add_request], blt ring 9651
>[drm:blt_ring_add_request], blt ring 9657
>[drm:blt_ring_add_request], blt ring 9663
>[drm:blt_ring_add_request], blt ring 9669
>[drm:blt_ring_add_request], blt ring 9675
>[drm:blt_ring_add_request], blt ring 9681
>[drm:blt_ring_add_request], blt ring 9687
>[drm:blt_ring_add_request], blt ring 9693
>[drm:blt_ring_add_request], blt ring 9699
>[drm:blt_ring_add_request], blt ring 9705
>[drm:blt_ring_add_request], blt ring 9711
>[drm:blt_ring_add_request], blt ring 9717
>[drm:blt_ring_add_request], blt ring 9723
>[drm:blt_ring_add_request], blt ring 9729
>[drm:blt_ring_add_request], blt ring 9735
>[drm:blt_ring_add_request], blt ring 9741
>[drm:blt_ring_add_request], blt ring 9747
>[drm:blt_ring_add_request], blt ring 9753
>[drm:blt_ring_add_request], blt ring 9759
>[drm:blt_ring_add_request], blt ring 9765
>[drm:blt_ring_add_request], blt ring 9771
>[drm:blt_ring_add_request], blt ring 9777
>[drm:blt_ring_add_request], blt ring 9783
>[drm:blt_ring_add_request], blt ring 9789
>[drm:blt_ring_add_request], blt ring 9795
>[drm:blt_ring_add_request], blt ring 9801
>[drm:blt_ring_add_request], blt ring 9807
>[drm:blt_ring_add_request], blt ring 9813
>[drm:blt_ring_add_request], blt ring 9819
>[drm:blt_ring_add_request], blt ring 9825
>[drm:blt_ring_add_request], blt ring 9831
>[drm:blt_ring_add_request], blt ring 9837
>[drm:blt_ring_add_request], blt ring 9843
>[drm:blt_ring_add_request], blt ring 9849
>[drm:blt_ring_add_request], blt ring 9855
>[drm:blt_ring_add_request], blt ring 9861
>[drm:blt_ring_add_request], blt ring 9867
>[drm:blt_ring_add_request], blt ring 9873
>[drm:blt_ring_add_request], blt ring 9879
>[drm:blt_ring_add_request], blt ring 9885
>[drm:blt_ring_add_request], blt ring 9891
>[drm:blt_ring_add_request], blt ring 9897
>[drm:blt_ring_add_request], blt ring 9903
>[drm:blt_ring_add_request], blt ring 9909
>[drm:blt_ring_add_request], blt ring 9915
>[drm:blt_ring_add_request], blt ring 9921
>[drm:blt_ring_add_request], blt ring 9927
>[drm:blt_ring_add_request], blt ring 9933
>[drm:blt_ring_add_request], blt ring 9939
>[drm:blt_ring_add_request], blt ring 9945
>[drm:blt_ring_add_request], blt ring 9951
>[drm:blt_ring_add_request], blt ring 9957
>[drm:blt_ring_add_request], blt ring 9963
>[drm:blt_ring_add_request], blt ring 9969
>[drm:blt_ring_add_request], blt ring 9975
>[drm:blt_ring_add_request], blt ring 9981
>[drm:blt_ring_add_request], blt ring 9987
>[drm:blt_ring_add_request], blt ring 9993
>[drm:blt_ring_add_request], blt ring 9999
>[drm:blt_ring_add_request], blt ring 10005
>[drm:blt_ring_add_request], blt ring 10011
>[drm:blt_ring_add_request], blt ring 10017
>[drm:blt_ring_add_request], blt ring 10023
>[drm:blt_ring_add_request], blt ring 10029
>[drm:blt_ring_add_request], blt ring 10035
>[drm:blt_ring_add_request], blt ring 10041
>[drm:blt_ring_add_request], blt ring 10047
>[drm:blt_ring_add_request], blt ring 10053
>[drm:blt_ring_add_request], blt ring 10059
>[drm:blt_ring_add_request], blt ring 10065
>[drm:blt_ring_add_request], blt ring 10071
>[drm:blt_ring_add_request], blt ring 10077
>[drm:blt_ring_add_request], blt ring 10083
>[drm:blt_ring_add_request], blt ring 10089
>[drm:blt_ring_add_request], blt ring 10095
>[drm:blt_ring_add_request], blt ring 10101
>[drm:blt_ring_add_request], blt ring 10107
>[drm:blt_ring_add_request], blt ring 10113
>[drm:blt_ring_add_request], blt ring 10119
>[drm:blt_ring_add_request], blt ring 10125
>[drm:blt_ring_add_request], blt ring 10131
>[drm:blt_ring_add_request], blt ring 10137
>[drm:blt_ring_add_request], blt ring 10143
>[drm:blt_ring_add_request], blt ring 10149
>[drm:blt_ring_add_request], blt ring 10155
>[drm:blt_ring_add_request], blt ring 10161
>[drm:blt_ring_add_request], blt ring 10167
>[drm:blt_ring_add_request], blt ring 10173
>[drm:blt_ring_add_request], blt ring 10179
>[drm:blt_ring_add_request], blt ring 10185
>[drm:blt_ring_add_request], blt ring 10191
>[drm:blt_ring_add_request], blt ring 10197
>[drm:blt_ring_add_request], blt ring 10203
>[drm:blt_ring_add_request], blt ring 10209
>[drm:blt_ring_add_request], blt ring 10215
>[drm:blt_ring_add_request], blt ring 10221
>[drm:blt_ring_add_request], blt ring 10227
>[drm:blt_ring_add_request], blt ring 10233
>[drm:blt_ring_add_request], blt ring 10239
>[drm:blt_ring_add_request], blt ring 10245
>[drm:blt_ring_add_request], blt ring 10251
>[drm:blt_ring_add_request], blt ring 10257
>[drm:blt_ring_add_request], blt ring 10263
>[drm:blt_ring_add_request], blt ring 10269
>[drm:blt_ring_add_request], blt ring 10275
>[drm:blt_ring_add_request], blt ring 10281
>[drm:blt_ring_add_request], blt ring 10287
>[drm:blt_ring_add_request], blt ring 10293
>[drm:blt_ring_add_request], blt ring 10299
>[drm:blt_ring_add_request], blt ring 10305
>[drm:blt_ring_add_request], blt ring 10311
>[drm:blt_ring_add_request], blt ring 10317
>[drm:blt_ring_add_request], blt ring 10323
>[drm:blt_ring_add_request], blt ring 10329
>[drm:blt_ring_add_request], blt ring 10335
>[drm:blt_ring_add_request], blt ring 10341
>[drm:blt_ring_add_request], blt ring 10347
>[drm:blt_ring_add_request], blt ring 10353
>[drm:blt_ring_add_request], blt ring 10359
>[drm:blt_ring_add_request], blt ring 10365
>[drm:blt_ring_add_request], blt ring 10371
>[drm:blt_ring_add_request], blt ring 10377
>[drm:blt_ring_add_request], blt ring 10383
>[drm:blt_ring_add_request], blt ring 10389
>[drm:blt_ring_add_request], blt ring 10395
>[drm:blt_ring_add_request], blt ring 10401
>[drm:blt_ring_add_request], blt ring 10407
>[drm:blt_ring_add_request], blt ring 10413
>[drm:blt_ring_add_request], blt ring 10419
>[drm:blt_ring_add_request], blt ring 10425
>[drm:blt_ring_add_request], blt ring 10431
>[drm:blt_ring_add_request], blt ring 10437
>[drm:blt_ring_add_request], blt ring 10443
>[drm:blt_ring_add_request], blt ring 10449
>[drm:blt_ring_add_request], blt ring 10455
>[drm:blt_ring_add_request], blt ring 10461
>[drm:blt_ring_add_request], blt ring 10467
>[drm:blt_ring_add_request], blt ring 10473
>[drm:blt_ring_add_request], blt ring 10479
>[drm:blt_ring_add_request], blt ring 10485
>[drm:blt_ring_add_request], blt ring 10491
>[drm:blt_ring_add_request], blt ring 10497
>[drm:blt_ring_add_request], blt ring 10503
>[drm:blt_ring_add_request], blt ring 10509
>[drm:blt_ring_add_request], blt ring 10515
>[drm:blt_ring_add_request], blt ring 10521
>[drm:blt_ring_add_request], blt ring 10527
>[drm:blt_ring_add_request], blt ring 10533
>[drm:blt_ring_add_request], blt ring 10539
>[drm:blt_ring_add_request], blt ring 10545
>[drm:blt_ring_add_request], blt ring 10551
>[drm:blt_ring_add_request], blt ring 10557
>[drm:blt_ring_add_request], blt ring 10563
>[drm:blt_ring_add_request], blt ring 10569
>[drm:blt_ring_add_request], blt ring 10575
>[drm:blt_ring_add_request], blt ring 10581
>[drm:blt_ring_add_request], blt ring 10587
>[drm:blt_ring_add_request], blt ring 10593
>[drm:blt_ring_add_request], blt ring 10599
>[drm:blt_ring_add_request], blt ring 10605
>[drm:blt_ring_add_request], blt ring 10611
>[drm:blt_ring_add_request], blt ring 10617
>[drm:blt_ring_add_request], blt ring 10623
>[drm:blt_ring_add_request], blt ring 10629
>[drm:blt_ring_add_request], blt ring 10635
>[drm:blt_ring_add_request], blt ring 10641
>[drm:blt_ring_add_request], blt ring 10647
>[drm:blt_ring_add_request], blt ring 10653
>[drm:blt_ring_add_request], blt ring 10659
>[drm:blt_ring_add_request], blt ring 10665
>[drm:blt_ring_add_request], blt ring 10671
>[drm:blt_ring_add_request], blt ring 10677
>[drm:blt_ring_add_request], blt ring 10683
>[drm:blt_ring_add_request], blt ring 10689
>[drm:blt_ring_add_request], blt ring 10695
>[drm:blt_ring_add_request], blt ring 10701
>[drm:blt_ring_add_request], blt ring 10707
>[drm:blt_ring_add_request], blt ring 10713
>[drm:blt_ring_add_request], blt ring 10719
>[drm:blt_ring_add_request], blt ring 10725
>[drm:blt_ring_add_request], blt ring 10731
>[drm:blt_ring_add_request], blt ring 10737
>[drm:blt_ring_add_request], blt ring 10743
>[drm:blt_ring_add_request], blt ring 10749
>[drm:blt_ring_add_request], blt ring 10755
>[drm:blt_ring_add_request], blt ring 10761
>[drm:blt_ring_add_request], blt ring 10767
>[drm:blt_ring_add_request], blt ring 10773
>[drm:blt_ring_add_request], blt ring 10779
>[drm:blt_ring_add_request], blt ring 10785
>[drm:blt_ring_add_request], blt ring 10791
>[drm:blt_ring_add_request], blt ring 10797
>[drm:blt_ring_add_request], blt ring 10803
>[drm:blt_ring_add_request], blt ring 10809
>[drm:blt_ring_add_request], blt ring 10815
>[drm:blt_ring_add_request], blt ring 10821
>[drm:blt_ring_add_request], blt ring 10827
>[drm:blt_ring_add_request], blt ring 10833
>[drm:blt_ring_add_request], blt ring 10839
>[drm:blt_ring_add_request], blt ring 10845
>[drm:blt_ring_add_request], blt ring 10851
>[drm:blt_ring_add_request], blt ring 10857
>[drm:blt_ring_add_request], blt ring 10863
>[drm:blt_ring_add_request], blt ring 10869
>[drm:blt_ring_add_request], blt ring 10875
>[drm:blt_ring_add_request], blt ring 10881
>[drm:blt_ring_add_request], blt ring 10887
>[drm:blt_ring_add_request], blt ring 10893
>[drm:blt_ring_add_request], blt ring 10899
>[drm:blt_ring_add_request], blt ring 10905
>[drm:blt_ring_add_request], blt ring 10911
>[drm:blt_ring_add_request], blt ring 10917
>[drm:blt_ring_add_request], blt ring 10923
>[drm:blt_ring_add_request], blt ring 10929
>[drm:blt_ring_add_request], blt ring 10935
>[drm:blt_ring_add_request], blt ring 10941
>[drm:blt_ring_add_request], blt ring 10947
>[drm:blt_ring_add_request], blt ring 10953
>[drm:blt_ring_add_request], blt ring 10959
>[drm:blt_ring_add_request], blt ring 10965
>[drm:blt_ring_add_request], blt ring 10971
>[drm:blt_ring_add_request], blt ring 10977
>[drm:blt_ring_add_request], blt ring 10983
>[drm:blt_ring_add_request], blt ring 10989
>[drm:blt_ring_add_request], blt ring 10995
>[drm:blt_ring_add_request], blt ring 11001
>[drm:blt_ring_add_request], blt ring 11007
>[drm:blt_ring_add_request], blt ring 11013
>[drm:blt_ring_add_request], blt ring 11019
>[drm:blt_ring_add_request], blt ring 11025
>[drm:blt_ring_add_request], blt ring 11030
>[drm:blt_ring_add_request], blt ring 11032
>[drm:blt_ring_add_request], blt ring 11033
>[drm:blt_ring_add_request], blt ring 11037
>[drm:drm_crtc_helper_set_config], 
>[drm:drm_crtc_helper_set_config], [CRTC:3] [NOFB] #connectors=0 (x y) (0 0)
>[drm:drm_crtc_helper_set_config], crtc changed, full mode switch
>[drm:drm_crtc_helper_set_config], [CONNECTOR:9:VGA-1] to [NOCRTC]
>[drm:drm_crtc_helper_set_config], Setting connector DPMS state to on
>[drm:drm_crtc_helper_set_config], 
>[drm:drm_crtc_helper_set_config], [CRTC:3] [FB:40] #connectors=1 (x y) (0 0)
>[drm:drm_crtc_helper_set_config], crtc has no fb, full mode set
>[drm:drm_crtc_helper_set_config], crtc changed, full mode switch
>[drm:drm_crtc_helper_set_config], [CONNECTOR:9:VGA-1] to [CRTC:3]
>[drm:drm_crtc_helper_set_config], attempting to set mode from userspace
>[drm:drm_mode_debug_printmodeline], Modeline 39:"1920x1200" 60 193250 1920 2056 2256 2592 1200 1203 1209 1245 0x48 0x6
>[drm:drm_crtc_helper_set_mode], [CRTC:3]
>[drm:intel_panel_get_backlight], get backlight PWM = 0
>[drm:intel_panel_set_backlight], set backlight PWM = 0
>[drm:intel_update_fbc], 
>[drm:intel_crtc_mode_set], Mode for pipe A:
>[drm:drm_mode_debug_printmodeline], Modeline 39:"1920x1200" 60 193250 1920 2056 2256 2592 1200 1203 1209 1245 0x48 0x6
>[drm:intel_wait_for_vblank], vblank wait timed out
>[drm:intel_pipe_set_base_atomic], Writing base 02063000 00000000 0 0 7680
>[drm:intel_update_fbc], 
>[drm:drm_crtc_helper_set_mode], [ENCODER:10:DAC-10] set [MODE:39:1920x1200]
>[drm:gen6_fdi_link_train], FDI_RX_IIR 0x100
>[drm:gen6_fdi_link_train], FDI train 1 done.
>[drm:gen6_fdi_link_train], FDI_RX_IIR 0x600
>[drm:gen6_fdi_link_train], FDI train 2 done.
>[drm:gen6_fdi_link_train], FDI train done.
>[drm:intel_update_fbc], 
>[drm:drm_crtc_helper_set_config], Setting connector DPMS state to on
>[drm:drm_crtc_helper_set_config], 	[CONNECTOR:9:VGA-1] set DPMS on
>[drm:drm_crtc_helper_set_config], 
>[drm:drm_crtc_helper_set_config], [CRTC:4] [FB:40] #connectors=0 (x y) (0 0)
>[drm:drm_crtc_helper_set_config], crtc has no fb, full mode set
>[drm:drm_crtc_helper_set_config], [CONNECTOR:9:VGA-1] to [CRTC:3]
>[drm:drm_crtc_helper_set_config], Setting connector DPMS state to on
>[drm:intel_prepare_page_flip], preparing flip with no unpin work?

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Attachments on bug 32589: 41388

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