Attachment 41501 Details for Bug 32698 – intel_reg_dumper

intel_reg_dumper

intel_reg_dumper.txt (text/plain), 7.79 KB, created by fangxun on 2010-12-29 01:37:45 UTC

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Creator: fangxun

Created: 2010-12-29 01:37:45 UTC

Size: 7.79 KB

patch

obsolete

>(II): DumpRegsBegin
>(II):         CPU_VGACNTRL: 0x80000000 (disabled)
>(II): DIGITAL_PORT_HOTPLUG: 0x00000000
>(II):            RR_HW_CTL: 0x00000000 (low 0, high 0)
>(II):       FDI_PLL_BIOS_0: 0x082b3019
>(II):       FDI_PLL_BIOS_1: 0x00000000
>(II):       FDI_PLL_BIOS_2: 0x00000000
>(II): DISPLAY_PORT_PLL_BIO: 0x0807012b
>(II): DISPLAY_PORT_PLL_BIO: 0x00000000
>(II): DISPLAY_PORT_PLL_BIO: 0x00000000
>(II):     FDI_PLL_FREQ_CTL: 0x00053687
>(II):            PIPEACONF: 0x00000050 (disabled, inactive, 6bpc)
>(II):             HTOTAL_A: 0x057b04ff (1280 active, 1404 total)
>(II):             HBLANK_A: 0x057b04ff (1280 start, 1404 end)
>(II):              HSYNC_A: 0x054f052f (1328 start, 1360 end)
>(II):             VTOTAL_A: 0x0335031f (800 active, 822 total)
>(II):             VBLANK_A: 0x0335031f (800 start, 822 end)
>(II):              VSYNC_A: 0x03280322 (803 start, 809 end)
>(II):         VSYNCSHIFT_A: 0x00000000
>(II):             PIPEASRC: 0x027f018f (640, 400)
>(II):        PIPEA_DATA_M1: 0x7e127ae1 (TU 64, val 0x127ae1 1211105)
>(II):        PIPEA_DATA_N1: 0x00800000 (val 0x800000 8388608)
>(II):        PIPEA_DATA_M2: 0x00000000 (TU 1, val 0x0 0)
>(II):        PIPEA_DATA_N2: 0x00000000 (val 0x0 0)
>(II):        PIPEA_LINK_M1: 0x00020da7 (val 0x20da7 134567)
>(II):        PIPEA_LINK_N1: 0x00080000 (val 0x80000 524288)
>(II):        PIPEA_LINK_M2: 0x00000000 (val 0x0 0)
>(II):        PIPEA_LINK_N2: 0x00000000 (val 0x0 0)
>(II):             DSPACNTR: 0x48000000 (disabled)
>(II):             DSPABASE: 0x00000000
>(II):           DSPASTRIDE: 0x00000300 (12)
>(II):             DSPASURF: 0x00000000
>(II):          DSPATILEOFF: 0x00000000 (0, 0)
>(II):            PIPEBCONF: 0xc0000054 (enabled, active, 6bpc)
>(II):             HTOTAL_B: 0x057b04ff (1280 active, 1404 total)
>(II):             HBLANK_B: 0x057b04ff (1280 start, 1404 end)
>(II):              HSYNC_B: 0x054f052f (1328 start, 1360 end)
>(II):             VTOTAL_B: 0x0335031f (800 active, 822 total)
>(II):             VBLANK_B: 0x0335031f (800 start, 822 end)
>(II):              VSYNC_B: 0x03280322 (803 start, 809 end)
>(II):         VSYNCSHIFT_B: 0x00000000
>(II):             DSPBCNTR: 0xd8004000 (enabled)
>(II):             DSPBBASE: 0x00000000
>(II):           DSPBSTRIDE: 0x00001400 (80)
>(II):             DSPBSURF: 0x02042000
>(II):          DSPBTILEOFF: 0x00000000 (0, 0)
>(II):             PIPEBSRC: 0x04ff031f (1280, 800)
>(II):        PIPEB_DATA_M1: 0x7e1308a8 (TU 64, val 0x1308a8 1247400)
>(II):        PIPEB_DATA_N1: 0x0020f580 (val 0x20f580 2160000)
>(II):        PIPEB_DATA_M2: 0x00000000 (TU 1, val 0x0 0)
>(II):        PIPEB_DATA_N2: 0x00000000 (val 0x0 0)
>(II):        PIPEB_LINK_M1: 0x00010eb4 (val 0x10eb4 69300)
>(II):        PIPEB_LINK_N1: 0x00041eb0 (val 0x41eb0 270000)
>(II):        PIPEB_LINK_M2: 0x00000000 (val 0x0 0)
>(II):        PIPEB_LINK_N2: 0x00000000 (val 0x0 0)
>(II):            PFA_CTL_1: 0x00000000 (disable, auto_scale yes, auto_scale_cal no, v_filter enable, vadapt disable, mode least, filter_sel programmed,chroma pre-filter disable, vert3tap auto, v_inter_invert field 1)
>(II):            PFB_CTL_1: 0x00000000 (disable, auto_scale yes, auto_scale_cal no, v_filter enable, vadapt disable, mode least, filter_sel programmed,chroma pre-filter disable, vert3tap auto, v_inter_invert field 1)
>(II):          PFA_WIN_POS: 0x00000000 (0, 0)
>(II):          PFB_WIN_POS: 0x00000000 (0, 0)
>(II):         PFA_WIN_SIZE: 0x00000000 (0, 0)
>(II):         PFB_WIN_SIZE: 0x00000000 (0, 0)
>(II):     PCH_DREF_CONTROL: 0x00001402 (cpu source disable, ssc_source enable, nonspread_source enable, superspread_source disable, ssc4_mode downspread, ssc1 enable, ssc4 disable)
>(II):      PCH_RAWCLK_FREQ: 0x0000007d (FDL_TP1 timer 0.5us, FDL_TP2 timer 1.5us, freq 125)
>(II):     PCH_DPLL_TMR_CFG: 0x0271186a
>(II):       PCH_SSC4_PARMS: 0x00000000
>(II):   PCH_SSC4_AUX_PARMS: 0x00000000
>(II):           PCH_DPLL_A: 0x88046004 (enable, sdvo high speed no, mode LVDS, p2 Div 14, FPA0 P1 3, FPA1 P1 3, refclk SSC, sdvo/hdmi mul 1)
>(II):           PCH_DPLL_B: 0x88046004 (enable, sdvo high speed no, mode LVDS, p2 Div 14, FPA0 P1 3, FPA1 P1 3, refclk SSC, sdvo/hdmi mul 1)
>(II):             PCH_FPA0: 0x00021005 (n = 2, m1 = 16, m2 = 5)
>(II):             PCH_FPA1: 0x00030d07 (n = 3, m1 = 13, m2 = 7)
>(II):             PCH_FPB0: 0x00010e05 (n = 1, m1 = 14, m2 = 5)
>(II):             PCH_FPB1: 0x00010e05 (n = 1, m1 = 14, m2 = 5)
>(II):       TRANS_HTOTAL_A: 0x057b04ff (1280 active, 1404 total)
>(II):       TRANS_HBLANK_A: 0x057b04ff (1280 start, 1404 end)
>(II):        TRANS_HSYNC_A: 0x054f052f (1328 start, 1360 end)
>(II):       TRANS_VTOTAL_A: 0x0335031f (800 active, 822 total)
>(II):       TRANS_VBLANK_A: 0x0335031f (800 start, 822 end)
>(II):        TRANS_VSYNC_A: 0x03280322 (803 start, 809 end)
>(II):       TRANSA_DATA_M1: 0x00000000 (TU 1, val 0x0 0)
>(II):       TRANSA_DATA_N1: 0x00000000 (val 0x0 0)
>(II):       TRANSA_DATA_M2: 0x00000000 (TU 1, val 0x0 0)
>(II):       TRANSA_DATA_N2: 0x00000000 (val 0x0 0)
>(II):    TRANSA_DP_LINK_M1: 0x00000000 (val 0x0 0)
>(II):    TRANSA_DP_LINK_N1: 0x00000000 (val 0x0 0)
>(II):    TRANSA_DP_LINK_M2: 0x00000000 (val 0x0 0)
>(II):    TRANSA_DP_LINK_N2: 0x00000000 (val 0x0 0)
>(II):       TRANS_HTOTAL_B: 0x057b04ff (1280 active, 1404 total)
>(II):       TRANS_HBLANK_B: 0x057b04ff (1280 start, 1404 end)
>(II):        TRANS_HSYNC_B: 0x054f052f (1328 start, 1360 end)
>(II):       TRANS_VTOTAL_B: 0x0335031f (800 active, 822 total)
>(II):       TRANS_VBLANK_B: 0x0335031f (800 start, 822 end)
>(II):        TRANS_VSYNC_B: 0x03280322 (803 start, 809 end)
>(II):       TRANSB_DATA_M1: 0x00000000 (TU 1, val 0x0 0)
>(II):       TRANSB_DATA_N1: 0x00000000 (val 0x0 0)
>(II):       TRANSB_DATA_M2: 0x00000000 (TU 1, val 0x0 0)
>(II):       TRANSB_DATA_N2: 0x00000000 (val 0x0 0)
>(II):    TRANSB_DP_LINK_M1: 0x00000000 (val 0x0 0)
>(II):    TRANSB_DP_LINK_N1: 0x00000000 (val 0x0 0)
>(II):    TRANSB_DP_LINK_M2: 0x00000000 (val 0x0 0)
>(II):    TRANSB_DP_LINK_N2: 0x00000000 (val 0x0 0)
>(II):           TRANSACONF: 0x00000040 (disable, inactive)
>(II):           TRANSBCONF: 0xc0000040 (enable, active)
>(II):          FDI_TXA_CTL: 0x001c4000 (disable, train pattern pattern_1, voltage swing 0.4V,pre-emphasis none, port width X4, enhanced framing enable, FDI PLL enable, scrambing enable, master mode disable)
>(II):          FDI_TXB_CTL: 0xb0044000 (enable, train pattern not train, voltage swing 0.4V,pre-emphasis none, port width X1, enhanced framing enable, FDI PLL enable, scrambing enable, master mode disable)
>(II):          FDI_RXA_CTL: 0x001a0040 (disable, train pattern pattern_1, port width X4, 6bpc,link_reverse_strap_overwrite no, dmi_link_reverse no, FDI PLL disable,FS ecc disable, FE ecc disable, FS err report disable, FE err report disable,scrambing enable, enhanced framing enable, RawClk)
>(II):          FDI_RXB_CTL: 0xb0022050 (enable, train pattern not train, port width X1, 6bpc,link_reverse_strap_overwrite no, dmi_link_reverse no, FDI PLL enable,FS ecc disable, FE ecc disable, FS err report disable, FE err report disable,scrambing enable, enhanced framing enable, PCDClk)
>(II):         FDI_RXA_MISC: 0x00000080 (FDI Delay 128)
>(II):         FDI_RXB_MISC: 0x00000080 (FDI Delay 128)
>(II):      FDI_RXA_TUSIZE1: 0x7e000000
>(II):      FDI_RXA_TUSIZE2: 0x7e000000
>(II):      FDI_RXB_TUSIZE1: 0x7e000000
>(II):      FDI_RXB_TUSIZE2: 0x7e000000
>(II):        FDI_PLL_CTL_1: 0x33505248
>(II):        FDI_PLL_CTL_2: 0x00000000
>(II):          FDI_RXA_IIR: 0x00000600
>(II):          FDI_RXA_IMR: 0x000000ff
>(II):          FDI_RXB_IIR: 0x00000000
>(II):          FDI_RXB_IMR: 0x000000ff
>(II):             PCH_ADPA: 0x00f40018 (disabled, transcoder A, +hsync, +vsync)
>(II):                HDMIB: 0x0000089c
>(II):                HDMIC: 0x0000001c
>(II):                HDMID: 0x0000001c
>(II):             PCH_LVDS: 0xc0308302 (enabled, pipe B, 18 bit, 1 channel)

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Attachments on bug 32698: 41485 | 41500 | 41501

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