Attachment 41950 Details for Bug 27470 – new pll algo

[patch] new pll algo

0001-drm-radeon-kms-Add-new-pll-calculation-for-avivo-asi.patch (text/plain), 8.22 KB, created by Alex Deucher on 2011-01-12 23:19:49 UTC

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Creator: Alex Deucher

Created: 2011-01-12 23:19:49 UTC

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patch

obsolete

>From 41f8ceb04681308d454210edbaaccadfa6741a01 Mon Sep 17 00:00:00 2001
>From: Alex Deucher <alexdeucher@gmail.com>
>Date: Wed, 12 Jan 2011 19:57:35 -0500
>Subject: [PATCH] drm/radeon/kms: Add new pll calculation for avivo+ asics
>
>Based on the algo used by the vbios.  Also, switch
>the legacy algo back to preferring lower post dividers.
>
>new algo is used for avivo+ and legacy is used for
>pre-avivo.
>
>Should fix:
>https://bugs.freedesktop.org/show_bug.cgi?id=32556
>https://bugzilla.kernel.org/show_bug.cgi?id=26552
>https://bugzilla.kernel.org/show_bug.cgi?id=26562
>
>Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
>---
> drivers/gpu/drm/radeon/atombios_crtc.c      |    8 ++-
> drivers/gpu/drm/radeon/radeon_display.c     |  121 +++++++++++++++++++++++++--
> drivers/gpu/drm/radeon/radeon_legacy_crtc.c |    6 +-
> drivers/gpu/drm/radeon/radeon_mode.h        |   23 ++++--
> 4 files changed, 138 insertions(+), 20 deletions(-)
>
>diff --git a/drivers/gpu/drm/radeon/atombios_crtc.c b/drivers/gpu/drm/radeon/atombios_crtc.c
>index b0ab185..46178f9 100644
>--- a/drivers/gpu/drm/radeon/atombios_crtc.c
>+++ b/drivers/gpu/drm/radeon/atombios_crtc.c
>@@ -963,8 +963,12 @@ static void atombios_crtc_set_pll(struct drm_crtc *crtc, struct drm_display_mode
> 	/* adjust pixel clock as needed */
> 	adjusted_clock = atombios_adjust_pll(crtc, mode, pll, ss_enabled, &ss);
> 
>-	radeon_compute_pll(pll, adjusted_clock, &pll_clock, &fb_div, &frac_fb_div,
>-			   &ref_div, &post_div);
>+	if (ASIC_IS_AVIVO(rdev))
>+		radeon_compute_pll_avivo(pll, adjusted_clock, &pll_clock, &fb_div, &frac_fb_div,
>+					 &ref_div, &post_div);
>+	else
>+		radeon_compute_pll_legacy(pll, adjusted_clock, &pll_clock, &fb_div, &frac_fb_div,
>+					  &ref_div, &post_div);
> 
> 	atombios_crtc_program_ss(crtc, ATOM_DISABLE, radeon_crtc->pll_id, &ss);
> 
>diff --git a/drivers/gpu/drm/radeon/radeon_display.c b/drivers/gpu/drm/radeon/radeon_display.c
>index d26dabf..645b09f 100644
>--- a/drivers/gpu/drm/radeon/radeon_display.c
>+++ b/drivers/gpu/drm/radeon/radeon_display.c
>@@ -780,6 +780,108 @@ static int radeon_ddc_dump(struct drm_connector *connector)
> 	return ret;
> }
> 
>+/* avivo */
>+static void avivo_get_fb_div(struct radeon_pll *pll,
>+			     u32 target_clock,
>+			     u32 post_div,
>+			     u32 ref_div,
>+			     u32 *fb_div,
>+			     u32 *frac_fb_div)
>+{
>+	u32 tmp = post_div * ref_div;
>+
>+	tmp *= target_clock;
>+	*fb_div = tmp / pll->reference_freq;
>+	*frac_fb_div = tmp % pll->reference_freq;
>+}
>+
>+static u32 avivo_get_post_div(struct radeon_pll *pll,
>+			      u32 target_clock)
>+{
>+	u32 vco, post_div, tmp;
>+
>+	if (pll->flags & RADEON_PLL_USE_POST_DIV)
>+		return pll->post_div;
>+
>+	if (pll->flags & RADEON_PLL_PREFER_MINM_OVER_MAXP)
>+		vco = pll->pll_out_min;
>+	else
>+		vco = pll->pll_out_max;
>+
>+	post_div = vco / target_clock;
>+	tmp = vco % target_clock;
>+
>+	if (pll->flags & RADEON_PLL_PREFER_MINM_OVER_MAXP) {
>+		if (tmp)
>+			post_div++;
>+	} else {
>+		if (!tmp)
>+			post_div--;
>+	}
>+
>+	return post_div;
>+}
>+
>+#define MAX_TOLERANCE 10
>+
>+void radeon_compute_pll_avivo(struct radeon_pll *pll,
>+			      u32 freq,
>+			      u32 *dot_clock_p,
>+			      u32 *fb_div_p,
>+			      u32 *frac_fb_div_p,
>+			      u32 *ref_div_p,
>+			      u32 *post_div_p)
>+{
>+	u32 target_clock = freq / 10;
>+	u32 post_div = avivo_get_post_div(pll, target_clock);
>+	u32 ref_div = pll->min_ref_div;
>+	u32 fb_div = 0, frac_fb_div = 0, tmp;
>+
>+	if (pll->flags & RADEON_PLL_USE_REF_DIV)
>+		ref_div = pll->reference_div;
>+
>+	if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) {
>+		avivo_get_fb_div(pll, target_clock, post_div, ref_div, &fb_div, &frac_fb_div);
>+		frac_fb_div = (100 * frac_fb_div) / pll->reference_freq;
>+		if (frac_fb_div >= 5) {
>+			frac_fb_div -= 5;
>+			frac_fb_div = frac_fb_div / 10;
>+			frac_fb_div++;
>+		}
>+		if (frac_fb_div >= 10) {
>+			fb_div++;
>+			frac_fb_div = 0;
>+		}
>+	} else {
>+		while (ref_div <= pll->max_ref_div) {
>+			avivo_get_fb_div(pll, target_clock, post_div, ref_div,
>+					 &fb_div, &frac_fb_div);
>+			if (frac_fb_div >= (pll->reference_freq / 2))
>+				fb_div++;
>+			frac_fb_div = 0;
>+			tmp = (pll->reference_freq * fb_div) / (post_div * ref_div);
>+			tmp = (tmp * 10000) / target_clock;
>+
>+			if (tmp > (10000 + MAX_TOLERANCE))
>+				ref_div++;
>+			else if (tmp >= (10000 - MAX_TOLERANCE))
>+				break;
>+			else
>+				ref_div++;
>+		}
>+	}
>+
>+	*dot_clock_p = ((pll->reference_freq * fb_div * 10) + (pll->reference_freq * frac_fb_div)) /
>+		(ref_div * post_div * 10);
>+	*fb_div_p = fb_div;
>+	*frac_fb_div_p = frac_fb_div;
>+	*ref_div_p = ref_div;
>+	*post_div_p = post_div;
>+	DRM_DEBUG_KMS("%d, pll dividers - fb: %d.%d ref: %d, post %d\n",
>+		      *dot_clock_p, fb_div, frac_fb_div, ref_div, post_div);
>+}
>+
>+/* pre-avivo */
> static inline uint32_t radeon_div(uint64_t n, uint32_t d)
> {
> 	uint64_t mod;
>@@ -790,13 +892,13 @@ static inline uint32_t radeon_div(uint64_t n, uint32_t d)
> 	return n;
> }
> 
>-void radeon_compute_pll(struct radeon_pll *pll,
>-			uint64_t freq,
>-			uint32_t *dot_clock_p,
>-			uint32_t *fb_div_p,
>-			uint32_t *frac_fb_div_p,
>-			uint32_t *ref_div_p,
>-			uint32_t *post_div_p)
>+void radeon_compute_pll_legacy(struct radeon_pll *pll,
>+			       uint64_t freq,
>+			       uint32_t *dot_clock_p,
>+			       uint32_t *fb_div_p,
>+			       uint32_t *frac_fb_div_p,
>+			       uint32_t *ref_div_p,
>+			       uint32_t *post_div_p)
> {
> 	uint32_t min_ref_div = pll->min_ref_div;
> 	uint32_t max_ref_div = pll->max_ref_div;
>@@ -849,7 +951,7 @@ void radeon_compute_pll(struct radeon_pll *pll,
> 		max_fractional_feed_div = pll->max_frac_feedback_div;
> 	}
> 
>-	for (post_div = max_post_div; post_div >= min_post_div; --post_div) {
>+	for (post_div = min_post_div; post_div <= max_post_div; ++post_div) {
> 		uint32_t ref_div;
> 
> 		if ((pll->flags & RADEON_PLL_NO_ODD_POST_DIV) && (post_div & 1))
>@@ -965,6 +1067,9 @@ void radeon_compute_pll(struct radeon_pll *pll,
> 	*frac_fb_div_p = best_frac_feedback_div;
> 	*ref_div_p = best_ref_div;
> 	*post_div_p = best_post_div;
>+	DRM_DEBUG_KMS("%d, pll dividers - fb: %d.%d ref: %d, post %d\n",
>+		      best_freq / 10000, best_feedback_div, best_frac_feedback_div,
>+		      best_ref_div, best_post_div);
> }
> 
> static void radeon_user_framebuffer_destroy(struct drm_framebuffer *fb)
>diff --git a/drivers/gpu/drm/radeon/radeon_legacy_crtc.c b/drivers/gpu/drm/radeon/radeon_legacy_crtc.c
>index ace2e63..cf0638c 100644
>--- a/drivers/gpu/drm/radeon/radeon_legacy_crtc.c
>+++ b/drivers/gpu/drm/radeon/radeon_legacy_crtc.c
>@@ -778,9 +778,9 @@ static void radeon_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode)
> 	DRM_DEBUG_KMS("\n");
> 
> 	if (!use_bios_divs) {
>-		radeon_compute_pll(pll, mode->clock,
>-				   &freq, &feedback_div, &frac_fb_div,
>-				   &reference_div, &post_divider);
>+		radeon_compute_pll_legacy(pll, mode->clock,
>+					  &freq, &feedback_div, &frac_fb_div,
>+					  &reference_div, &post_divider);
> 
> 		for (post_div = &post_divs[0]; post_div->divider; ++post_div) {
> 			if (post_div->divider == post_divider)
>diff --git a/drivers/gpu/drm/radeon/radeon_mode.h b/drivers/gpu/drm/radeon/radeon_mode.h
>index 12bdeab..6794cdf 100644
>--- a/drivers/gpu/drm/radeon/radeon_mode.h
>+++ b/drivers/gpu/drm/radeon/radeon_mode.h
>@@ -149,6 +149,7 @@ struct radeon_tmds_pll {
> #define RADEON_PLL_PREFER_CLOSEST_LOWER (1 << 11)
> #define RADEON_PLL_USE_POST_DIV         (1 << 12)
> #define RADEON_PLL_IS_LCD               (1 << 13)
>+#define RADEON_PLL_PREFER_MINM_OVER_MAXP (1 << 14)
> 
> struct radeon_pll {
> 	/* reference frequency */
>@@ -510,13 +511,21 @@ extern bool radeon_atombios_get_asic_ss_info(struct radeon_device *rdev,
> 					     struct radeon_atom_ss *ss,
> 					     int id, u32 clock);
> 
>-extern void radeon_compute_pll(struct radeon_pll *pll,
>-			       uint64_t freq,
>-			       uint32_t *dot_clock_p,
>-			       uint32_t *fb_div_p,
>-			       uint32_t *frac_fb_div_p,
>-			       uint32_t *ref_div_p,
>-			       uint32_t *post_div_p);
>+extern void radeon_compute_pll_legacy(struct radeon_pll *pll,
>+				      uint64_t freq,
>+				      uint32_t *dot_clock_p,
>+				      uint32_t *fb_div_p,
>+				      uint32_t *frac_fb_div_p,
>+				      uint32_t *ref_div_p,
>+				      uint32_t *post_div_p);
>+
>+extern void radeon_compute_pll_avivo(struct radeon_pll *pll,
>+				     u32 freq,
>+				     u32 *dot_clock_p,
>+				     u32 *fb_div_p,
>+				     u32 *frac_fb_div_p,
>+				     u32 *ref_div_p,
>+				     u32 *post_div_p);
> 
> extern void radeon_setup_encoder_clones(struct drm_device *dev);
> 
>-- 
>1.7.1.1
>

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