Attachment 42753 Details for Bug 33738 – handle tiling using dfs/uts like r6xx+

[patch] handle tiling using dfs/uts like r6xx+

0001-kms-r3xx-r5xx-fix-pageflipping-with-tiling.patch (text/plain), 3.97 KB, created by Alex Deucher on 2011-01-31 08:42:45 UTC

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Creator: Alex Deucher

Created: 2011-01-31 08:42:45 UTC

Size: 3.97 KB

patch

obsolete

>From b11fce88a300edb0aa7faeee92b600ede91e82d3 Mon Sep 17 00:00:00 2001
>From: Alex Deucher <alexdeucher@gmail.com>
>Date: Mon, 31 Jan 2011 11:32:31 -0500
>Subject: [PATCH] kms/r3xx-r5xx: fix pageflipping with tiling
>
>Use UTS/DFS to tile/untile as appropriate for sw access.
>
>Should fix:
>https://bugs.freedesktop.org/show_bug.cgi?id=33738
>
>Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
>---
> src/drmmode_display.c  |    3 +--
> src/radeon_exa.c       |   18 ++++++++----------
> src/radeon_exa_funcs.c |   21 ++++++++++++++-------
> 3 files changed, 23 insertions(+), 19 deletions(-)
>
>diff --git a/src/drmmode_display.c b/src/drmmode_display.c
>index 2ab4510..d5ad211 100644
>--- a/src/drmmode_display.c
>+++ b/src/drmmode_display.c
>@@ -1232,8 +1232,7 @@ drmmode_xf86crtc_resize (ScrnInfoPtr scrn, int width, int height)
> 	}
> #endif
> 	if (tiling_flags)
>-	    radeon_bo_set_tiling(info->front_bo,
>-				 tiling_flags | RADEON_TILING_SURFACE, pitch);
>+	    radeon_bo_set_tiling(info->front_bo, tiling_flags, pitch);
> 
> 	ret = drmModeAddFB(drmmode->fd, width, height, scrn->depth,
> 			   scrn->bitsPerPixel, pitch,
>diff --git a/src/radeon_exa.c b/src/radeon_exa.c
>index 9df7251..3dbdcae 100644
>--- a/src/radeon_exa.c
>+++ b/src/radeon_exa.c
>@@ -307,6 +307,7 @@ Bool RADEONPrepareAccess_CS(PixmapPtr pPix, int index)
> #endif
>     Bool flush = FALSE;
>     int ret;
>+    uint32_t tiling_flags = 0, pitch = 0;
> 
> #if X_BYTE_ORDER == X_BIG_ENDIAN
>     /* May need to handle byte swapping in DownloadFrom/UploadToScreen */
>@@ -318,16 +319,13 @@ Bool RADEONPrepareAccess_CS(PixmapPtr pPix, int index)
>     if (!driver_priv)
>       return FALSE;
> 
>-    if (info->ChipFamily >= CHIP_FAMILY_R600) {
>-	uint32_t tiling_flags = 0, pitch = 0;
>-
>-	ret = radeon_bo_get_tiling(driver_priv->bo, &tiling_flags, &pitch);
>-	if (ret)
>-	    return FALSE;
>-	/* untile in DFS/UTS */
>-	if (tiling_flags & (RADEON_TILING_MACRO | RADEON_TILING_MICRO))
>-	    return FALSE;
>-    }
>+    /* check if we are tiled */
>+    ret = radeon_bo_get_tiling(driver_priv->bo, &tiling_flags, &pitch);
>+    if (ret)
>+	return FALSE;
>+    /* untile in DFS/UTS */
>+    if (tiling_flags & (RADEON_TILING_MACRO | RADEON_TILING_MICRO))
>+	return FALSE;
> 
>     /* if we have more refs than just the BO then flush */
>     if (radeon_bo_is_referenced_by_cs(driver_priv->bo, info->cs)) {
>diff --git a/src/radeon_exa_funcs.c b/src/radeon_exa_funcs.c
>index e80a996..0bcaba0 100644
>--- a/src/radeon_exa_funcs.c
>+++ b/src/radeon_exa_funcs.c
>@@ -573,6 +573,7 @@ RADEONDownloadFromScreenCS(PixmapPtr pSrc, int x, int y, int w,
>     int ret;
>     Bool flush = FALSE;
>     Bool r;
>+    uint32_t tiling_flags = 0, pitch = 0;
> 
>     if (bpp < 8)
> 	return FALSE;
>@@ -581,6 +582,10 @@ RADEONDownloadFromScreenCS(PixmapPtr pSrc, int x, int y, int w,
>     if (!driver_priv || !driver_priv->bo)
> 	return FALSE;
> 
>+    ret = radeon_bo_get_tiling(driver_priv->bo, &tiling_flags, &pitch);
>+    if (ret)
>+	ErrorF("radeon_bo_get_tiling failed\n");
>+
> #if X_BYTE_ORDER == X_BIG_ENDIAN
>     switch (bpp) {
>     case 32:
>@@ -595,13 +600,15 @@ RADEONDownloadFromScreenCS(PixmapPtr pSrc, int x, int y, int w,
>     /* If we know the BO won't end up in VRAM anyway, don't bother with a scratch */
>     copy_src = driver_priv->bo;
>     copy_pitch = pSrc->devKind;
>-    if (radeon_bo_is_referenced_by_cs(driver_priv->bo, info->cs)) {
>-	src_domain = radeon_bo_get_src_domain(driver_priv->bo);
>-	if ((src_domain & (RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM)) ==
>-	    (RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM))
>-	    src_domain = 0;
>-	else /* A write may be scheduled */
>-	    flush = TRUE;
>+    if (!(tiling_flags & (RADEON_TILING_MACRO | RADEON_TILING_MICRO))) {
>+	if (radeon_bo_is_referenced_by_cs(driver_priv->bo, info->cs)) {
>+	    src_domain = radeon_bo_get_src_domain(driver_priv->bo);
>+	    if ((src_domain & (RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM)) ==
>+		(RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM))
>+		src_domain = 0;
>+	    else /* A write may be scheduled */
>+		flush = TRUE;
>+	}
>     }
> 
>     if (!src_domain)
>-- 
>1.7.1.1
>

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