Attachment 43011 Details for Bug 33887 – possible fix for nv4x/nv6x chipsets

[patch] possible fix for nv4x/nv6x chipsets

0001-drm-nv40-possible-tiling-fix-for-later-chipsets.patch (text/plain), 1.31 KB, created by Ben Skeggs on 2011-02-06 14:29:34 UTC

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Creator: Ben Skeggs

Created: 2011-02-06 14:29:34 UTC

Size: 1.31 KB

patch

obsolete

>From c8026b7544f4b45bb263fac068f7e3ef9d8272f0 Mon Sep 17 00:00:00 2001
>From: Ben Skeggs <bskeggs@redhat.com>
>Date: Mon, 7 Feb 2011 08:26:09 +1000
>Subject: [PATCH] drm/nv40: possible tiling fix for later chipsets
>
>---
> drivers/gpu/drm/nouveau/nv40_graph.c |    4 +++-
> 1 files changed, 3 insertions(+), 1 deletions(-)
>
>diff --git a/drivers/gpu/drm/nouveau/nv40_graph.c b/drivers/gpu/drm/nouveau/nv40_graph.c
>index 8870d72..fe9c37e 100644
>--- a/drivers/gpu/drm/nouveau/nv40_graph.c
>+++ b/drivers/gpu/drm/nouveau/nv40_graph.c
>@@ -223,6 +223,7 @@ nv40_graph_set_tile_region(struct drm_device *dev, int i)
> 	case 0x47:
> 	case 0x49:
> 	case 0x4b:
>+	default:
> 		nv_wr32(dev, NV47_PGRAPH_TSIZE(i), tile->pitch);
> 		nv_wr32(dev, NV47_PGRAPH_TLIMIT(i), tile->limit);
> 		nv_wr32(dev, NV47_PGRAPH_TILE(i), tile->addr);
>@@ -230,7 +231,7 @@ nv40_graph_set_tile_region(struct drm_device *dev, int i)
> 		nv_wr32(dev, NV40_PGRAPH_TLIMIT1(i), tile->limit);
> 		nv_wr32(dev, NV40_PGRAPH_TILE1(i), tile->addr);
> 		break;
>-
>+#if 0
> 	default:
> 		nv_wr32(dev, NV20_PGRAPH_TSIZE(i), tile->pitch);
> 		nv_wr32(dev, NV20_PGRAPH_TLIMIT(i), tile->limit);
>@@ -239,6 +240,7 @@ nv40_graph_set_tile_region(struct drm_device *dev, int i)
> 		nv_wr32(dev, NV40_PGRAPH_TLIMIT1(i), tile->limit);
> 		nv_wr32(dev, NV40_PGRAPH_TILE1(i), tile->addr);
> 		break;
>+#endif
> 	}
> }
> 
>-- 
>1.7.4
>

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