Attachment 43401 Details for Bug 29278 – skip FDI/PCH enabling backported to 2.6.38-rc4

[patch] skip FDI/PCH enabling backported to 2.6.38-rc4

0001-drm-i915-skip-FDI-PCH-enabling-for-DP_A.patch (text/plain), 4.00 KB, created by Jesse Barnes on 2011-02-15 15:09:21 UTC

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Creator: Jesse Barnes

Created: 2011-02-15 15:09:21 UTC

Size: 4.00 KB

patch

obsolete

>From 732b483e78e4226e5897aa120aefb3f976dec129 Mon Sep 17 00:00:00 2001
>From: Jesse Barnes <jbarnes@virtuousgeek.org>
>Date: Tue, 15 Feb 2011 15:06:34 -0800
>Subject: [PATCH] drm/i915: skip FDI & PCH enabling for DP_A
>
>eDP on the CPU doesn't need the PCH set up at all, it can in fact cause
>problems.  So avoid FDI training and PCH PLL enabling in that case.
>
>Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
>---
> drivers/gpu/drm/i915/intel_display.c |   83 +++++++++++++++++++++++++++++++++-
> 1 files changed, 81 insertions(+), 2 deletions(-)
>
>diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
>index 7e42aa5..08747ab 100644
>--- a/drivers/gpu/drm/i915/intel_display.c
>+++ b/drivers/gpu/drm/i915/intel_display.c
>@@ -2045,6 +2045,31 @@ static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
> 		   atomic_read(&obj->pending_flip) == 0);
> }
> 
>+static bool intel_crtc_driving_pch(struct drm_crtc *crtc)
>+{
>+	struct drm_device *dev = crtc->dev;
>+	struct drm_mode_config *mode_config = &dev->mode_config;
>+	struct intel_encoder *encoder;
>+
>+	/*
>+	 * If there's a non-PCH eDP on this crtc, it must be DP_A, and that
>+	 * must be driven by its own crtc; no sharing is possible.
>+	 */
>+	list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
>+		if (encoder->base.crtc != crtc)
>+			continue;
>+
>+		switch (encoder->type) {
>+		case INTEL_OUTPUT_EDP:
>+			if (!intel_encoder_is_pch_edp(&encoder->base))
>+				return false;
>+			continue;
>+		}
>+	}
>+
>+	return true;
>+}
>+
> static void ironlake_crtc_enable(struct drm_crtc *crtc)
> {
> 	struct drm_device *dev = crtc->dev;
>@@ -2053,6 +2078,7 @@ static void ironlake_crtc_enable(struct drm_crtc *crtc)
> 	int pipe = intel_crtc->pipe;
> 	int plane = intel_crtc->plane;
> 	u32 reg, temp;
>+	bool is_pch_port = false;
> 
> 	if (intel_crtc->active)
> 		return;
>@@ -2066,7 +2092,56 @@ static void ironlake_crtc_enable(struct drm_crtc *crtc)
> 			I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
> 	}
> 
>-	ironlake_fdi_enable(crtc);
>+	is_pch_port = intel_crtc_driving_pch(crtc);
>+
>+	if (is_pch_port)
>+		ironlake_fdi_enable(crtc);
>+	else {
>+		/* disable CPU FDI tx and PCH FDI rx */
>+		reg = FDI_TX_CTL(pipe);
>+		temp = I915_READ(reg);
>+		I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
>+		POSTING_READ(reg);
>+
>+		reg = FDI_RX_CTL(pipe);
>+		temp = I915_READ(reg);
>+		temp &= ~(0x7 << 16);
>+		temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
>+		I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
>+
>+		POSTING_READ(reg);
>+		udelay(100);
>+
>+		/* Ironlake workaround, disable clock pointer after downing FDI */
>+		if (HAS_PCH_IBX(dev))
>+			I915_WRITE(FDI_RX_CHICKEN(pipe),
>+				   I915_READ(FDI_RX_CHICKEN(pipe) &
>+					     ~FDI_RX_PHASE_SYNC_POINTER_ENABLE));
>+
>+		/* still set train pattern 1 */
>+		reg = FDI_TX_CTL(pipe);
>+		temp = I915_READ(reg);
>+		temp &= ~FDI_LINK_TRAIN_NONE;
>+		temp |= FDI_LINK_TRAIN_PATTERN_1;
>+		I915_WRITE(reg, temp);
>+
>+		reg = FDI_RX_CTL(pipe);
>+		temp = I915_READ(reg);
>+		if (HAS_PCH_CPT(dev)) {
>+			temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
>+			temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
>+		} else {
>+			temp &= ~FDI_LINK_TRAIN_NONE;
>+			temp |= FDI_LINK_TRAIN_PATTERN_1;
>+		}
>+		/* BPC in FDI rx is consistent with that in PIPECONF */
>+		temp &= ~(0x07 << 16);
>+		temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
>+		I915_WRITE(reg, temp);
>+
>+		POSTING_READ(reg);
>+		udelay(100);
>+	}
> 
> 	/* Enable panel fitting for LVDS */
> 	if (dev_priv->pch_pf_size &&
>@@ -2100,6 +2175,10 @@ static void ironlake_crtc_enable(struct drm_crtc *crtc)
> 		intel_flush_display_plane(dev, plane);
> 	}
> 
>+	/* Skip the PCH stuff if possible */
>+	if (!is_pch_port)
>+		goto done;
>+
> 	/* For PCH output, training FDI link */
> 	if (IS_GEN6(dev))
> 		gen6_fdi_link_train(crtc);
>@@ -2184,7 +2263,7 @@ static void ironlake_crtc_enable(struct drm_crtc *crtc)
> 	I915_WRITE(reg, temp | TRANS_ENABLE);
> 	if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
> 		DRM_ERROR("failed to enable transcoder %d\n", pipe);
>-
>+done:
> 	intel_crtc_load_lut(crtc);
> 	intel_update_fbc(dev);
> 	intel_crtc_update_cursor(crtc, true);
>-- 
>1.7.1
>

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